2 * Copyright 2019 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
24 #include <linux/delay.h>
25 #include <linux/kernel.h>
26 #include <linux/firmware.h>
27 #include <linux/module.h>
28 #include <linux/pci.h>
30 #include "amdgpu_gfx.h"
31 #include "amdgpu_psp.h"
32 #include "amdgpu_smu.h"
36 #include "gc/gc_10_1_0_offset.h"
37 #include "gc/gc_10_1_0_sh_mask.h"
38 #include "navi10_enum.h"
39 #include "hdp/hdp_5_0_0_offset.h"
40 #include "ivsrcid/gfx/irqsrcs_gfx_10_1.h"
44 #include "soc15_common.h"
45 #include "clearstate_gfx10.h"
46 #include "v10_structs.h"
47 #include "gfx_v10_0.h"
48 #include "nbio_v2_3.h"
51 * Navi10 has two graphic rings to share each graphic pipe.
55 #define GFX10_NUM_GFX_RINGS_NV1X 1
56 #define GFX10_MEC_HPD_SIZE 2048
58 #define F32_CE_PROGRAM_RAM_SIZE 65536
59 #define RLCG_UCODE_LOADING_START_ADDRESS 0x00002000L
61 #define mmCGTT_GS_NGG_CLK_CTRL 0x5087
62 #define mmCGTT_GS_NGG_CLK_CTRL_BASE_IDX 1
64 MODULE_FIRMWARE("amdgpu/navi10_ce.bin");
65 MODULE_FIRMWARE("amdgpu/navi10_pfp.bin");
66 MODULE_FIRMWARE("amdgpu/navi10_me.bin");
67 MODULE_FIRMWARE("amdgpu/navi10_mec.bin");
68 MODULE_FIRMWARE("amdgpu/navi10_mec2.bin");
69 MODULE_FIRMWARE("amdgpu/navi10_rlc.bin");
71 MODULE_FIRMWARE("amdgpu/navi14_ce_wks.bin");
72 MODULE_FIRMWARE("amdgpu/navi14_pfp_wks.bin");
73 MODULE_FIRMWARE("amdgpu/navi14_me_wks.bin");
74 MODULE_FIRMWARE("amdgpu/navi14_mec_wks.bin");
75 MODULE_FIRMWARE("amdgpu/navi14_mec2_wks.bin");
76 MODULE_FIRMWARE("amdgpu/navi14_ce.bin");
77 MODULE_FIRMWARE("amdgpu/navi14_pfp.bin");
78 MODULE_FIRMWARE("amdgpu/navi14_me.bin");
79 MODULE_FIRMWARE("amdgpu/navi14_mec.bin");
80 MODULE_FIRMWARE("amdgpu/navi14_mec2.bin");
81 MODULE_FIRMWARE("amdgpu/navi14_rlc.bin");
83 MODULE_FIRMWARE("amdgpu/navi12_ce.bin");
84 MODULE_FIRMWARE("amdgpu/navi12_pfp.bin");
85 MODULE_FIRMWARE("amdgpu/navi12_me.bin");
86 MODULE_FIRMWARE("amdgpu/navi12_mec.bin");
87 MODULE_FIRMWARE("amdgpu/navi12_mec2.bin");
88 MODULE_FIRMWARE("amdgpu/navi12_rlc.bin");
90 static const struct soc15_reg_golden golden_settings_gc_10_1[] =
92 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_4, 0xffffffff, 0x00400014),
93 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_CPF_CLK_CTRL, 0xfcff8fff, 0xf8000100),
94 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CLK_CTRL, 0xcd000000, 0x0d000100),
95 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQ_CLK_CTRL, 0x60000ff0, 0x60000100),
96 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQG_CLK_CTRL, 0x40000000, 0x40000100),
97 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_VGT_CLK_CTRL, 0xffff8fff, 0xffff8100),
98 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_WD_CLK_CTRL, 0xfeff8fff, 0xfeff8100),
99 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0xffffffff, 0xe4e4e4e4),
100 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_VC5_ENABLE, 0x00000002, 0x00000000),
101 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_SD_CNTL, 0x000007ff, 0x000005ff),
102 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG, 0x20000000, 0x20000000),
103 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG2, 0xffffffff, 0x00000420),
104 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0x00000200, 0x00000200),
105 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0x07900000, 0x04900000),
106 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DFSM_TILES_IN_FLIGHT, 0x0000ffff, 0x0000003f),
107 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_LAST_OF_BURST_CONFIG, 0xffffffff, 0x03860204),
108 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL, 0x1ff0ffff, 0x00000500),
109 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PRIV_CONTROL, 0x000007ff, 0x000001fe),
110 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0xffffffff, 0xe4e4e4e4),
111 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_0, 0x77777777, 0x10321032),
112 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_1, 0x77777777, 0x02310231),
113 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
114 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
115 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CGTT_SCLK_CTRL, 0x10000000, 0x10000100),
116 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL2, 0xffffffff, 0x1402002f),
117 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xffff9fff, 0x00001188),
118 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800),
119 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE, 0x3fffffff, 0x08000009),
120 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_1, 0x00400000, 0x04440000),
121 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0x00000800, 0x00000820),
122 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000),
123 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRMI_SPARE, 0xffffffff, 0xffff3101),
124 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1, 0x001f0000, 0x00070104),
125 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ALU_CLK_CTRL, 0xffffffff, 0xffffffff),
126 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ARB_CONFIG, 0x00000100, 0x00000130),
127 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_LDS_CLK_CTRL, 0xffffffff, 0xffffffff),
128 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000),
129 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CNTL, 0x60000010, 0x479c0010),
130 SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CGTT_CLK_CTRL, 0xfeff0fff, 0x40000100),
131 SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0x00c00000, 0x00c00000)
134 static const struct soc15_reg_golden golden_settings_gc_10_0_nv10[] =
136 /* Pending on emulation bring up */
139 static const struct soc15_reg_golden golden_settings_gc_10_1_1[] =
141 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_4, 0xffffffff, 0x003c0014),
142 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_GS_NGG_CLK_CTRL, 0xffff8fff, 0xffff8100),
143 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_IA_CLK_CTRL, 0xffff0fff, 0xffff0100),
144 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CLK_CTRL, 0xcd000000, 0x0d000100),
145 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQ_CLK_CTRL, 0xf8ff0fff, 0x60000100),
146 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQG_CLK_CTRL, 0x40000ff0, 0x40000100),
147 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_VGT_CLK_CTRL, 0xffff8fff, 0xffff8100),
148 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_WD_CLK_CTRL, 0xffff8fff, 0xffff8100),
149 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0xffffffff, 0xe4e4e4e4),
150 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_VC5_ENABLE, 0x00000002, 0x00000000),
151 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_SD_CNTL, 0x800007ff, 0x000005ff),
152 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG, 0xffffffff, 0x20000000),
153 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG2, 0xffffffff, 0x00000420),
154 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0x00000200, 0x00000200),
155 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x04900000),
156 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DFSM_TILES_IN_FLIGHT, 0x0000ffff, 0x0000003f),
157 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_LAST_OF_BURST_CONFIG, 0xffffffff, 0x03860204),
158 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL, 0x1ff0ffff, 0x00000500),
159 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PRIV_CONTROL, 0x000007ff, 0x000001fe),
160 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0xffffffff, 0xe4e4e4e4),
161 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffe7),
162 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffe7),
163 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CGTT_SCLK_CTRL, 0xffff0fff, 0x10000100),
164 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL2, 0xffffffff, 0x1402002f),
165 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xffffbfff, 0x00000188),
166 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800),
167 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE, 0x3fffffff, 0x08000009),
168 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_1, 0x00400000, 0x04440000),
169 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0x00000800, 0x00000820),
170 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000),
171 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRMI_SPARE, 0xffffffff, 0xffff3101),
172 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1, 0x001f0000, 0x00070105),
173 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ALU_CLK_CTRL, 0xffffffff, 0xffffffff),
174 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ARB_CONFIG, 0x00000133, 0x00000130),
175 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_LDS_CLK_CTRL, 0xffffffff, 0xffffffff),
176 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000),
177 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CNTL, 0x60000010, 0x479c0010),
178 SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0x00c00000, 0x00c00000),
181 static const struct soc15_reg_golden golden_settings_gc_10_1_2[] =
183 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_4, 0x003e001f, 0x003c0014),
184 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_GS_NGG_CLK_CTRL, 0xffff8fff, 0xffff8100),
185 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_IA_CLK_CTRL, 0xffff0fff, 0xffff0100),
186 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CLK_CTRL, 0xff7f0fff, 0x0d000100),
187 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQ_CLK_CTRL, 0xffffcfff, 0x60000100),
188 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQG_CLK_CTRL, 0xffff0fff, 0x40000100),
189 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_VGT_CLK_CTRL, 0xffff8fff, 0xffff8100),
190 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_WD_CLK_CTRL, 0xffff8fff, 0xffff8100),
191 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0xffffffff, 0xe4e4e4e4),
192 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_VC5_ENABLE, 0x00000003, 0x00000000),
193 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_SD_CNTL, 0x800007ff, 0x000005ff),
194 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG, 0xffffffff, 0x20000000),
195 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG2, 0xffffffff, 0x00000420),
196 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000200),
197 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x04800000),
198 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DFSM_TILES_IN_FLIGHT, 0x0000ffff, 0x0000003f),
199 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_LAST_OF_BURST_CONFIG, 0xffffffff, 0x03860204),
200 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL, 0x1ff0ffff, 0x00000500),
201 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PRIV_CONTROL, 0x00007fff, 0x000001fe),
202 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0xffffffff, 0xe4e4e4e4),
203 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_0, 0x77777777, 0x10321032),
204 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_1, 0x77777777, 0x02310231),
205 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
206 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
207 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CGTT_SCLK_CTRL, 0xffff0fff, 0x10000100),
208 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL2, 0xffffffff, 0x1402002f),
209 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xffffbfff, 0x00000188),
210 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_EVENT_CNTL_0, 0xffffffff, 0x842a4c02),
211 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800),
212 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE, 0x3fffffff, 0x08000009),
213 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_1, 0xffffffff, 0x04440000),
214 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0x00000820, 0x00000820),
215 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000),
216 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRMI_SPARE, 0xffffffff, 0xffff3101),
217 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ALU_CLK_CTRL, 0xffffffff, 0xffffffff),
218 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ARB_CONFIG, 0x00000133, 0x00000130),
219 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_LDS_CLK_CTRL, 0xffffffff, 0xffffffff),
220 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000),
221 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CNTL, 0xffdf80ff, 0x479c0010),
222 SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffffffff, 0x00800000)
225 static const struct soc15_reg_golden golden_settings_gc_10_1_nv14[] =
227 /* Pending on emulation bring up */
230 static const struct soc15_reg_golden golden_settings_gc_10_1_2_nv12[] =
232 /* Pending on emulation bring up */
235 #define DEFAULT_SH_MEM_CONFIG \
236 ((SH_MEM_ADDRESS_MODE_64 << SH_MEM_CONFIG__ADDRESS_MODE__SHIFT) | \
237 (SH_MEM_ALIGNMENT_MODE_UNALIGNED << SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT) | \
238 (SH_MEM_RETRY_MODE_ALL << SH_MEM_CONFIG__RETRY_MODE__SHIFT) | \
239 (3 << SH_MEM_CONFIG__INITIAL_INST_PREFETCH__SHIFT))
242 static void gfx_v10_0_set_ring_funcs(struct amdgpu_device *adev);
243 static void gfx_v10_0_set_irq_funcs(struct amdgpu_device *adev);
244 static void gfx_v10_0_set_gds_init(struct amdgpu_device *adev);
245 static void gfx_v10_0_set_rlc_funcs(struct amdgpu_device *adev);
246 static int gfx_v10_0_get_cu_info(struct amdgpu_device *adev,
247 struct amdgpu_cu_info *cu_info);
248 static uint64_t gfx_v10_0_get_gpu_clock_counter(struct amdgpu_device *adev);
249 static void gfx_v10_0_select_se_sh(struct amdgpu_device *adev, u32 se_num,
250 u32 sh_num, u32 instance);
251 static u32 gfx_v10_0_get_wgp_active_bitmap_per_sh(struct amdgpu_device *adev);
253 static int gfx_v10_0_rlc_backdoor_autoload_buffer_init(struct amdgpu_device *adev);
254 static void gfx_v10_0_rlc_backdoor_autoload_buffer_fini(struct amdgpu_device *adev);
255 static int gfx_v10_0_rlc_backdoor_autoload_enable(struct amdgpu_device *adev);
256 static int gfx_v10_0_wait_for_rlc_autoload_complete(struct amdgpu_device *adev);
257 static void gfx_v10_0_ring_emit_ce_meta(struct amdgpu_ring *ring, bool resume);
258 static void gfx_v10_0_ring_emit_de_meta(struct amdgpu_ring *ring, bool resume);
259 static void gfx_v10_0_ring_emit_tmz(struct amdgpu_ring *ring, bool start);
261 static void gfx10_kiq_set_resources(struct amdgpu_ring *kiq_ring, uint64_t queue_mask)
263 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_SET_RESOURCES, 6));
264 amdgpu_ring_write(kiq_ring, PACKET3_SET_RESOURCES_VMID_MASK(0) |
265 PACKET3_SET_RESOURCES_QUEUE_TYPE(0)); /* vmid_mask:0 queue_type:0 (KIQ) */
266 amdgpu_ring_write(kiq_ring, lower_32_bits(queue_mask)); /* queue mask lo */
267 amdgpu_ring_write(kiq_ring, upper_32_bits(queue_mask)); /* queue mask hi */
268 amdgpu_ring_write(kiq_ring, 0); /* gws mask lo */
269 amdgpu_ring_write(kiq_ring, 0); /* gws mask hi */
270 amdgpu_ring_write(kiq_ring, 0); /* oac mask */
271 amdgpu_ring_write(kiq_ring, 0); /* gds heap base:0, gds heap size:0 */
274 static void gfx10_kiq_map_queues(struct amdgpu_ring *kiq_ring,
275 struct amdgpu_ring *ring)
277 struct amdgpu_device *adev = kiq_ring->adev;
278 uint64_t mqd_addr = amdgpu_bo_gpu_offset(ring->mqd_obj);
279 uint64_t wptr_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
280 uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0;
282 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_MAP_QUEUES, 5));
283 /* Q_sel:0, vmid:0, vidmem: 1, engine:0, num_Q:1*/
284 amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */
285 PACKET3_MAP_QUEUES_QUEUE_SEL(0) | /* Queue_Sel */
286 PACKET3_MAP_QUEUES_VMID(0) | /* VMID */
287 PACKET3_MAP_QUEUES_QUEUE(ring->queue) |
288 PACKET3_MAP_QUEUES_PIPE(ring->pipe) |
289 PACKET3_MAP_QUEUES_ME((ring->me == 1 ? 0 : 1)) |
290 PACKET3_MAP_QUEUES_QUEUE_TYPE(0) | /*queue_type: normal compute queue */
291 PACKET3_MAP_QUEUES_ALLOC_FORMAT(0) | /* alloc format: all_on_one_pipe */
292 PACKET3_MAP_QUEUES_ENGINE_SEL(eng_sel) |
293 PACKET3_MAP_QUEUES_NUM_QUEUES(1)); /* num_queues: must be 1 */
294 amdgpu_ring_write(kiq_ring, PACKET3_MAP_QUEUES_DOORBELL_OFFSET(ring->doorbell_index));
295 amdgpu_ring_write(kiq_ring, lower_32_bits(mqd_addr));
296 amdgpu_ring_write(kiq_ring, upper_32_bits(mqd_addr));
297 amdgpu_ring_write(kiq_ring, lower_32_bits(wptr_addr));
298 amdgpu_ring_write(kiq_ring, upper_32_bits(wptr_addr));
301 static void gfx10_kiq_unmap_queues(struct amdgpu_ring *kiq_ring,
302 struct amdgpu_ring *ring,
303 enum amdgpu_unmap_queues_action action,
304 u64 gpu_addr, u64 seq)
306 uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0;
308 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_UNMAP_QUEUES, 4));
309 amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */
310 PACKET3_UNMAP_QUEUES_ACTION(action) |
311 PACKET3_UNMAP_QUEUES_QUEUE_SEL(0) |
312 PACKET3_UNMAP_QUEUES_ENGINE_SEL(eng_sel) |
313 PACKET3_UNMAP_QUEUES_NUM_QUEUES(1));
314 amdgpu_ring_write(kiq_ring,
315 PACKET3_UNMAP_QUEUES_DOORBELL_OFFSET0(ring->doorbell_index));
317 if (action == PREEMPT_QUEUES_NO_UNMAP) {
318 amdgpu_ring_write(kiq_ring, lower_32_bits(gpu_addr));
319 amdgpu_ring_write(kiq_ring, upper_32_bits(gpu_addr));
320 amdgpu_ring_write(kiq_ring, seq);
322 amdgpu_ring_write(kiq_ring, 0);
323 amdgpu_ring_write(kiq_ring, 0);
324 amdgpu_ring_write(kiq_ring, 0);
328 static void gfx10_kiq_query_status(struct amdgpu_ring *kiq_ring,
329 struct amdgpu_ring *ring,
333 uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0;
335 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_QUERY_STATUS, 5));
336 amdgpu_ring_write(kiq_ring,
337 PACKET3_QUERY_STATUS_CONTEXT_ID(0) |
338 PACKET3_QUERY_STATUS_INTERRUPT_SEL(0) |
339 PACKET3_QUERY_STATUS_COMMAND(2));
340 amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */
341 PACKET3_QUERY_STATUS_DOORBELL_OFFSET(ring->doorbell_index) |
342 PACKET3_QUERY_STATUS_ENG_SEL(eng_sel));
343 amdgpu_ring_write(kiq_ring, lower_32_bits(addr));
344 amdgpu_ring_write(kiq_ring, upper_32_bits(addr));
345 amdgpu_ring_write(kiq_ring, lower_32_bits(seq));
346 amdgpu_ring_write(kiq_ring, upper_32_bits(seq));
349 static void gfx10_kiq_invalidate_tlbs(struct amdgpu_ring *kiq_ring,
350 uint16_t pasid, uint32_t flush_type,
353 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_INVALIDATE_TLBS, 0));
354 amdgpu_ring_write(kiq_ring,
355 PACKET3_INVALIDATE_TLBS_DST_SEL(1) |
356 PACKET3_INVALIDATE_TLBS_ALL_HUB(all_hub) |
357 PACKET3_INVALIDATE_TLBS_PASID(pasid) |
358 PACKET3_INVALIDATE_TLBS_FLUSH_TYPE(flush_type));
361 static const struct kiq_pm4_funcs gfx_v10_0_kiq_pm4_funcs = {
362 .kiq_set_resources = gfx10_kiq_set_resources,
363 .kiq_map_queues = gfx10_kiq_map_queues,
364 .kiq_unmap_queues = gfx10_kiq_unmap_queues,
365 .kiq_query_status = gfx10_kiq_query_status,
366 .kiq_invalidate_tlbs = gfx10_kiq_invalidate_tlbs,
367 .set_resources_size = 8,
368 .map_queues_size = 7,
369 .unmap_queues_size = 6,
370 .query_status_size = 7,
371 .invalidate_tlbs_size = 2,
374 static void gfx_v10_0_set_kiq_pm4_funcs(struct amdgpu_device *adev)
376 adev->gfx.kiq.pmf = &gfx_v10_0_kiq_pm4_funcs;
379 static void gfx_v10_0_init_golden_registers(struct amdgpu_device *adev)
381 switch (adev->asic_type) {
383 soc15_program_register_sequence(adev,
384 golden_settings_gc_10_1,
385 (const u32)ARRAY_SIZE(golden_settings_gc_10_1));
386 soc15_program_register_sequence(adev,
387 golden_settings_gc_10_0_nv10,
388 (const u32)ARRAY_SIZE(golden_settings_gc_10_0_nv10));
391 soc15_program_register_sequence(adev,
392 golden_settings_gc_10_1_1,
393 (const u32)ARRAY_SIZE(golden_settings_gc_10_1_1));
394 soc15_program_register_sequence(adev,
395 golden_settings_gc_10_1_nv14,
396 (const u32)ARRAY_SIZE(golden_settings_gc_10_1_nv14));
399 soc15_program_register_sequence(adev,
400 golden_settings_gc_10_1_2,
401 (const u32)ARRAY_SIZE(golden_settings_gc_10_1_2));
402 soc15_program_register_sequence(adev,
403 golden_settings_gc_10_1_2_nv12,
404 (const u32)ARRAY_SIZE(golden_settings_gc_10_1_2_nv12));
411 static void gfx_v10_0_scratch_init(struct amdgpu_device *adev)
413 adev->gfx.scratch.num_reg = 8;
414 adev->gfx.scratch.reg_base = SOC15_REG_OFFSET(GC, 0, mmSCRATCH_REG0);
415 adev->gfx.scratch.free_mask = (1u << adev->gfx.scratch.num_reg) - 1;
418 static void gfx_v10_0_write_data_to_reg(struct amdgpu_ring *ring, int eng_sel,
419 bool wc, uint32_t reg, uint32_t val)
421 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
422 amdgpu_ring_write(ring, WRITE_DATA_ENGINE_SEL(eng_sel) |
423 WRITE_DATA_DST_SEL(0) | (wc ? WR_CONFIRM : 0));
424 amdgpu_ring_write(ring, reg);
425 amdgpu_ring_write(ring, 0);
426 amdgpu_ring_write(ring, val);
429 static void gfx_v10_0_wait_reg_mem(struct amdgpu_ring *ring, int eng_sel,
430 int mem_space, int opt, uint32_t addr0,
431 uint32_t addr1, uint32_t ref, uint32_t mask,
434 amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5));
435 amdgpu_ring_write(ring,
436 /* memory (1) or register (0) */
437 (WAIT_REG_MEM_MEM_SPACE(mem_space) |
438 WAIT_REG_MEM_OPERATION(opt) | /* wait */
439 WAIT_REG_MEM_FUNCTION(3) | /* equal */
440 WAIT_REG_MEM_ENGINE(eng_sel)));
443 BUG_ON(addr0 & 0x3); /* Dword align */
444 amdgpu_ring_write(ring, addr0);
445 amdgpu_ring_write(ring, addr1);
446 amdgpu_ring_write(ring, ref);
447 amdgpu_ring_write(ring, mask);
448 amdgpu_ring_write(ring, inv); /* poll interval */
451 static int gfx_v10_0_ring_test_ring(struct amdgpu_ring *ring)
453 struct amdgpu_device *adev = ring->adev;
459 r = amdgpu_gfx_scratch_get(adev, &scratch);
461 DRM_ERROR("amdgpu: cp failed to get scratch reg (%d).\n", r);
465 WREG32(scratch, 0xCAFEDEAD);
467 r = amdgpu_ring_alloc(ring, 3);
469 DRM_ERROR("amdgpu: cp failed to lock ring %d (%d).\n",
471 amdgpu_gfx_scratch_free(adev, scratch);
475 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1));
476 amdgpu_ring_write(ring, (scratch - PACKET3_SET_UCONFIG_REG_START));
477 amdgpu_ring_write(ring, 0xDEADBEEF);
478 amdgpu_ring_commit(ring);
480 for (i = 0; i < adev->usec_timeout; i++) {
481 tmp = RREG32(scratch);
482 if (tmp == 0xDEADBEEF)
484 if (amdgpu_emu_mode == 1)
490 if (i >= adev->usec_timeout)
493 amdgpu_gfx_scratch_free(adev, scratch);
498 static int gfx_v10_0_ring_test_ib(struct amdgpu_ring *ring, long timeout)
500 struct amdgpu_device *adev = ring->adev;
502 struct dma_fence *f = NULL;
508 r = amdgpu_device_wb_get(adev, &index);
512 gpu_addr = adev->wb.gpu_addr + (index * 4);
513 adev->wb.wb[index] = cpu_to_le32(0xCAFEDEAD);
514 memset(&ib, 0, sizeof(ib));
515 r = amdgpu_ib_get(adev, NULL, 16, &ib);
519 ib.ptr[0] = PACKET3(PACKET3_WRITE_DATA, 3);
520 ib.ptr[1] = WRITE_DATA_DST_SEL(5) | WR_CONFIRM;
521 ib.ptr[2] = lower_32_bits(gpu_addr);
522 ib.ptr[3] = upper_32_bits(gpu_addr);
523 ib.ptr[4] = 0xDEADBEEF;
526 r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f);
530 r = dma_fence_wait_timeout(f, false, timeout);
538 tmp = adev->wb.wb[index];
539 if (tmp == 0xDEADBEEF)
544 amdgpu_ib_free(adev, &ib, NULL);
547 amdgpu_device_wb_free(adev, index);
551 static void gfx_v10_0_free_microcode(struct amdgpu_device *adev)
553 release_firmware(adev->gfx.pfp_fw);
554 adev->gfx.pfp_fw = NULL;
555 release_firmware(adev->gfx.me_fw);
556 adev->gfx.me_fw = NULL;
557 release_firmware(adev->gfx.ce_fw);
558 adev->gfx.ce_fw = NULL;
559 release_firmware(adev->gfx.rlc_fw);
560 adev->gfx.rlc_fw = NULL;
561 release_firmware(adev->gfx.mec_fw);
562 adev->gfx.mec_fw = NULL;
563 release_firmware(adev->gfx.mec2_fw);
564 adev->gfx.mec2_fw = NULL;
566 kfree(adev->gfx.rlc.register_list_format);
569 static void gfx_v10_0_check_fw_write_wait(struct amdgpu_device *adev)
571 adev->gfx.cp_fw_write_wait = false;
573 switch (adev->asic_type) {
577 if ((adev->gfx.me_fw_version >= 0x00000046) &&
578 (adev->gfx.me_feature_version >= 27) &&
579 (adev->gfx.pfp_fw_version >= 0x00000068) &&
580 (adev->gfx.pfp_feature_version >= 27) &&
581 (adev->gfx.mec_fw_version >= 0x0000005b) &&
582 (adev->gfx.mec_feature_version >= 27))
583 adev->gfx.cp_fw_write_wait = true;
589 if (adev->gfx.cp_fw_write_wait == false)
590 DRM_WARN_ONCE("CP firmware version too old, please update!");
594 static void gfx_v10_0_init_rlc_ext_microcode(struct amdgpu_device *adev)
596 const struct rlc_firmware_header_v2_1 *rlc_hdr;
598 rlc_hdr = (const struct rlc_firmware_header_v2_1 *)adev->gfx.rlc_fw->data;
599 adev->gfx.rlc_srlc_fw_version = le32_to_cpu(rlc_hdr->save_restore_list_cntl_ucode_ver);
600 adev->gfx.rlc_srlc_feature_version = le32_to_cpu(rlc_hdr->save_restore_list_cntl_feature_ver);
601 adev->gfx.rlc.save_restore_list_cntl_size_bytes = le32_to_cpu(rlc_hdr->save_restore_list_cntl_size_bytes);
602 adev->gfx.rlc.save_restore_list_cntl = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->save_restore_list_cntl_offset_bytes);
603 adev->gfx.rlc_srlg_fw_version = le32_to_cpu(rlc_hdr->save_restore_list_gpm_ucode_ver);
604 adev->gfx.rlc_srlg_feature_version = le32_to_cpu(rlc_hdr->save_restore_list_gpm_feature_ver);
605 adev->gfx.rlc.save_restore_list_gpm_size_bytes = le32_to_cpu(rlc_hdr->save_restore_list_gpm_size_bytes);
606 adev->gfx.rlc.save_restore_list_gpm = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->save_restore_list_gpm_offset_bytes);
607 adev->gfx.rlc_srls_fw_version = le32_to_cpu(rlc_hdr->save_restore_list_srm_ucode_ver);
608 adev->gfx.rlc_srls_feature_version = le32_to_cpu(rlc_hdr->save_restore_list_srm_feature_ver);
609 adev->gfx.rlc.save_restore_list_srm_size_bytes = le32_to_cpu(rlc_hdr->save_restore_list_srm_size_bytes);
610 adev->gfx.rlc.save_restore_list_srm = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->save_restore_list_srm_offset_bytes);
611 adev->gfx.rlc.reg_list_format_direct_reg_list_length =
612 le32_to_cpu(rlc_hdr->reg_list_format_direct_reg_list_length);
615 static bool gfx_v10_0_navi10_gfxoff_should_enable(struct amdgpu_device *adev)
619 switch (adev->pdev->revision) {
632 static void gfx_v10_0_check_gfxoff_flag(struct amdgpu_device *adev)
634 switch (adev->asic_type) {
636 if (!gfx_v10_0_navi10_gfxoff_should_enable(adev))
637 adev->pm.pp_feature &= ~PP_GFXOFF_MASK;
644 static int gfx_v10_0_init_microcode(struct amdgpu_device *adev)
646 const char *chip_name;
650 struct amdgpu_firmware_info *info = NULL;
651 const struct common_firmware_header *header = NULL;
652 const struct gfx_firmware_header_v1_0 *cp_hdr;
653 const struct rlc_firmware_header_v2_0 *rlc_hdr;
654 unsigned int *tmp = NULL;
656 uint16_t version_major;
657 uint16_t version_minor;
661 memset(wks, 0, sizeof(wks));
662 switch (adev->asic_type) {
664 chip_name = "navi10";
667 chip_name = "navi14";
668 if (!(adev->pdev->device == 0x7340 &&
669 adev->pdev->revision != 0x00))
670 snprintf(wks, sizeof(wks), "_wks");
673 chip_name = "navi12";
679 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_pfp%s.bin", chip_name, wks);
680 err = request_firmware(&adev->gfx.pfp_fw, fw_name, adev->dev);
683 err = amdgpu_ucode_validate(adev->gfx.pfp_fw);
686 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.pfp_fw->data;
687 adev->gfx.pfp_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
688 adev->gfx.pfp_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
690 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_me%s.bin", chip_name, wks);
691 err = request_firmware(&adev->gfx.me_fw, fw_name, adev->dev);
694 err = amdgpu_ucode_validate(adev->gfx.me_fw);
697 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.me_fw->data;
698 adev->gfx.me_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
699 adev->gfx.me_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
701 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_ce%s.bin", chip_name, wks);
702 err = request_firmware(&adev->gfx.ce_fw, fw_name, adev->dev);
705 err = amdgpu_ucode_validate(adev->gfx.ce_fw);
708 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.ce_fw->data;
709 adev->gfx.ce_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
710 adev->gfx.ce_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
712 if (!amdgpu_sriov_vf(adev)) {
713 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_rlc.bin", chip_name);
714 err = request_firmware(&adev->gfx.rlc_fw, fw_name, adev->dev);
717 err = amdgpu_ucode_validate(adev->gfx.rlc_fw);
718 rlc_hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data;
719 version_major = le16_to_cpu(rlc_hdr->header.header_version_major);
720 version_minor = le16_to_cpu(rlc_hdr->header.header_version_minor);
721 if (version_major == 2 && version_minor == 1)
722 adev->gfx.rlc.is_rlc_v2_1 = true;
724 adev->gfx.rlc_fw_version = le32_to_cpu(rlc_hdr->header.ucode_version);
725 adev->gfx.rlc_feature_version = le32_to_cpu(rlc_hdr->ucode_feature_version);
726 adev->gfx.rlc.save_and_restore_offset =
727 le32_to_cpu(rlc_hdr->save_and_restore_offset);
728 adev->gfx.rlc.clear_state_descriptor_offset =
729 le32_to_cpu(rlc_hdr->clear_state_descriptor_offset);
730 adev->gfx.rlc.avail_scratch_ram_locations =
731 le32_to_cpu(rlc_hdr->avail_scratch_ram_locations);
732 adev->gfx.rlc.reg_restore_list_size =
733 le32_to_cpu(rlc_hdr->reg_restore_list_size);
734 adev->gfx.rlc.reg_list_format_start =
735 le32_to_cpu(rlc_hdr->reg_list_format_start);
736 adev->gfx.rlc.reg_list_format_separate_start =
737 le32_to_cpu(rlc_hdr->reg_list_format_separate_start);
738 adev->gfx.rlc.starting_offsets_start =
739 le32_to_cpu(rlc_hdr->starting_offsets_start);
740 adev->gfx.rlc.reg_list_format_size_bytes =
741 le32_to_cpu(rlc_hdr->reg_list_format_size_bytes);
742 adev->gfx.rlc.reg_list_size_bytes =
743 le32_to_cpu(rlc_hdr->reg_list_size_bytes);
744 adev->gfx.rlc.register_list_format =
745 kmalloc(adev->gfx.rlc.reg_list_format_size_bytes +
746 adev->gfx.rlc.reg_list_size_bytes, GFP_KERNEL);
747 if (!adev->gfx.rlc.register_list_format) {
752 tmp = (unsigned int *)((uintptr_t)rlc_hdr +
753 le32_to_cpu(rlc_hdr->reg_list_format_array_offset_bytes));
754 for (i = 0 ; i < (rlc_hdr->reg_list_format_size_bytes >> 2); i++)
755 adev->gfx.rlc.register_list_format[i] = le32_to_cpu(tmp[i]);
757 adev->gfx.rlc.register_restore = adev->gfx.rlc.register_list_format + i;
759 tmp = (unsigned int *)((uintptr_t)rlc_hdr +
760 le32_to_cpu(rlc_hdr->reg_list_array_offset_bytes));
761 for (i = 0 ; i < (rlc_hdr->reg_list_size_bytes >> 2); i++)
762 adev->gfx.rlc.register_restore[i] = le32_to_cpu(tmp[i]);
764 if (adev->gfx.rlc.is_rlc_v2_1)
765 gfx_v10_0_init_rlc_ext_microcode(adev);
768 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec%s.bin", chip_name, wks);
769 err = request_firmware(&adev->gfx.mec_fw, fw_name, adev->dev);
772 err = amdgpu_ucode_validate(adev->gfx.mec_fw);
775 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data;
776 adev->gfx.mec_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
777 adev->gfx.mec_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
779 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec2%s.bin", chip_name, wks);
780 err = request_firmware(&adev->gfx.mec2_fw, fw_name, adev->dev);
782 err = amdgpu_ucode_validate(adev->gfx.mec2_fw);
785 cp_hdr = (const struct gfx_firmware_header_v1_0 *)
786 adev->gfx.mec2_fw->data;
787 adev->gfx.mec2_fw_version =
788 le32_to_cpu(cp_hdr->header.ucode_version);
789 adev->gfx.mec2_feature_version =
790 le32_to_cpu(cp_hdr->ucode_feature_version);
793 adev->gfx.mec2_fw = NULL;
796 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
797 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_PFP];
798 info->ucode_id = AMDGPU_UCODE_ID_CP_PFP;
799 info->fw = adev->gfx.pfp_fw;
800 header = (const struct common_firmware_header *)info->fw->data;
801 adev->firmware.fw_size +=
802 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
804 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_ME];
805 info->ucode_id = AMDGPU_UCODE_ID_CP_ME;
806 info->fw = adev->gfx.me_fw;
807 header = (const struct common_firmware_header *)info->fw->data;
808 adev->firmware.fw_size +=
809 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
811 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_CE];
812 info->ucode_id = AMDGPU_UCODE_ID_CP_CE;
813 info->fw = adev->gfx.ce_fw;
814 header = (const struct common_firmware_header *)info->fw->data;
815 adev->firmware.fw_size +=
816 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
818 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_G];
819 info->ucode_id = AMDGPU_UCODE_ID_RLC_G;
820 info->fw = adev->gfx.rlc_fw;
822 header = (const struct common_firmware_header *)info->fw->data;
823 adev->firmware.fw_size +=
824 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
826 if (adev->gfx.rlc.is_rlc_v2_1 &&
827 adev->gfx.rlc.save_restore_list_cntl_size_bytes &&
828 adev->gfx.rlc.save_restore_list_gpm_size_bytes &&
829 adev->gfx.rlc.save_restore_list_srm_size_bytes) {
830 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL];
831 info->ucode_id = AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL;
832 info->fw = adev->gfx.rlc_fw;
833 adev->firmware.fw_size +=
834 ALIGN(adev->gfx.rlc.save_restore_list_cntl_size_bytes, PAGE_SIZE);
836 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM];
837 info->ucode_id = AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM;
838 info->fw = adev->gfx.rlc_fw;
839 adev->firmware.fw_size +=
840 ALIGN(adev->gfx.rlc.save_restore_list_gpm_size_bytes, PAGE_SIZE);
842 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM];
843 info->ucode_id = AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM;
844 info->fw = adev->gfx.rlc_fw;
845 adev->firmware.fw_size +=
846 ALIGN(adev->gfx.rlc.save_restore_list_srm_size_bytes, PAGE_SIZE);
849 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC1];
850 info->ucode_id = AMDGPU_UCODE_ID_CP_MEC1;
851 info->fw = adev->gfx.mec_fw;
852 header = (const struct common_firmware_header *)info->fw->data;
853 cp_hdr = (const struct gfx_firmware_header_v1_0 *)info->fw->data;
854 adev->firmware.fw_size +=
855 ALIGN(le32_to_cpu(header->ucode_size_bytes) -
856 le32_to_cpu(cp_hdr->jt_size) * 4, PAGE_SIZE);
858 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC1_JT];
859 info->ucode_id = AMDGPU_UCODE_ID_CP_MEC1_JT;
860 info->fw = adev->gfx.mec_fw;
861 adev->firmware.fw_size +=
862 ALIGN(le32_to_cpu(cp_hdr->jt_size) * 4, PAGE_SIZE);
864 if (adev->gfx.mec2_fw) {
865 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC2];
866 info->ucode_id = AMDGPU_UCODE_ID_CP_MEC2;
867 info->fw = adev->gfx.mec2_fw;
868 header = (const struct common_firmware_header *)info->fw->data;
869 cp_hdr = (const struct gfx_firmware_header_v1_0 *)info->fw->data;
870 adev->firmware.fw_size +=
871 ALIGN(le32_to_cpu(header->ucode_size_bytes) -
872 le32_to_cpu(cp_hdr->jt_size) * 4,
874 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC2_JT];
875 info->ucode_id = AMDGPU_UCODE_ID_CP_MEC2_JT;
876 info->fw = adev->gfx.mec2_fw;
877 adev->firmware.fw_size +=
878 ALIGN(le32_to_cpu(cp_hdr->jt_size) * 4,
883 gfx_v10_0_check_fw_write_wait(adev);
887 "gfx10: Failed to load firmware \"%s\"\n",
889 release_firmware(adev->gfx.pfp_fw);
890 adev->gfx.pfp_fw = NULL;
891 release_firmware(adev->gfx.me_fw);
892 adev->gfx.me_fw = NULL;
893 release_firmware(adev->gfx.ce_fw);
894 adev->gfx.ce_fw = NULL;
895 release_firmware(adev->gfx.rlc_fw);
896 adev->gfx.rlc_fw = NULL;
897 release_firmware(adev->gfx.mec_fw);
898 adev->gfx.mec_fw = NULL;
899 release_firmware(adev->gfx.mec2_fw);
900 adev->gfx.mec2_fw = NULL;
903 gfx_v10_0_check_gfxoff_flag(adev);
908 static u32 gfx_v10_0_get_csb_size(struct amdgpu_device *adev)
911 const struct cs_section_def *sect = NULL;
912 const struct cs_extent_def *ext = NULL;
914 /* begin clear state */
916 /* context control state */
919 for (sect = gfx10_cs_data; sect->section != NULL; ++sect) {
920 for (ext = sect->section; ext->extent != NULL; ++ext) {
921 if (sect->id == SECT_CONTEXT)
922 count += 2 + ext->reg_count;
928 /* set PA_SC_TILE_STEERING_OVERRIDE */
930 /* end clear state */
938 static void gfx_v10_0_get_csb_buffer(struct amdgpu_device *adev,
939 volatile u32 *buffer)
942 const struct cs_section_def *sect = NULL;
943 const struct cs_extent_def *ext = NULL;
946 if (adev->gfx.rlc.cs_data == NULL)
951 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0));
952 buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_BEGIN_CLEAR_STATE);
954 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CONTEXT_CONTROL, 1));
955 buffer[count++] = cpu_to_le32(0x80000000);
956 buffer[count++] = cpu_to_le32(0x80000000);
958 for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) {
959 for (ext = sect->section; ext->extent != NULL; ++ext) {
960 if (sect->id == SECT_CONTEXT) {
962 cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, ext->reg_count));
963 buffer[count++] = cpu_to_le32(ext->reg_index -
964 PACKET3_SET_CONTEXT_REG_START);
965 for (i = 0; i < ext->reg_count; i++)
966 buffer[count++] = cpu_to_le32(ext->extent[i]);
974 SOC15_REG_OFFSET(GC, 0, mmPA_SC_TILE_STEERING_OVERRIDE) - PACKET3_SET_CONTEXT_REG_START;
975 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, 1));
976 buffer[count++] = cpu_to_le32(ctx_reg_offset);
977 buffer[count++] = cpu_to_le32(adev->gfx.config.pa_sc_tile_steering_override);
979 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0));
980 buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_END_CLEAR_STATE);
982 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CLEAR_STATE, 0));
983 buffer[count++] = cpu_to_le32(0);
986 static void gfx_v10_0_rlc_fini(struct amdgpu_device *adev)
988 /* clear state block */
989 amdgpu_bo_free_kernel(&adev->gfx.rlc.clear_state_obj,
990 &adev->gfx.rlc.clear_state_gpu_addr,
991 (void **)&adev->gfx.rlc.cs_ptr);
993 /* jump table block */
994 amdgpu_bo_free_kernel(&adev->gfx.rlc.cp_table_obj,
995 &adev->gfx.rlc.cp_table_gpu_addr,
996 (void **)&adev->gfx.rlc.cp_table_ptr);
999 static int gfx_v10_0_rlc_init(struct amdgpu_device *adev)
1001 const struct cs_section_def *cs_data;
1004 adev->gfx.rlc.cs_data = gfx10_cs_data;
1006 cs_data = adev->gfx.rlc.cs_data;
1009 /* init clear state block */
1010 r = amdgpu_gfx_rlc_init_csb(adev);
1015 /* init spm vmid with 0xf */
1016 if (adev->gfx.rlc.funcs->update_spm_vmid)
1017 adev->gfx.rlc.funcs->update_spm_vmid(adev, 0xf);
1022 static void gfx_v10_0_mec_fini(struct amdgpu_device *adev)
1024 amdgpu_bo_free_kernel(&adev->gfx.mec.hpd_eop_obj, NULL, NULL);
1025 amdgpu_bo_free_kernel(&adev->gfx.mec.mec_fw_obj, NULL, NULL);
1028 static int gfx_v10_0_me_init(struct amdgpu_device *adev)
1032 bitmap_zero(adev->gfx.me.queue_bitmap, AMDGPU_MAX_GFX_QUEUES);
1034 amdgpu_gfx_graphics_queue_acquire(adev);
1036 r = gfx_v10_0_init_microcode(adev);
1038 DRM_ERROR("Failed to load gfx firmware!\n");
1043 static int gfx_v10_0_mec_init(struct amdgpu_device *adev)
1047 const __le32 *fw_data = NULL;
1050 size_t mec_hpd_size;
1052 const struct gfx_firmware_header_v1_0 *mec_hdr = NULL;
1054 bitmap_zero(adev->gfx.mec.queue_bitmap, AMDGPU_MAX_COMPUTE_QUEUES);
1056 /* take ownership of the relevant compute queues */
1057 amdgpu_gfx_compute_queue_acquire(adev);
1058 mec_hpd_size = adev->gfx.num_compute_rings * GFX10_MEC_HPD_SIZE;
1060 r = amdgpu_bo_create_reserved(adev, mec_hpd_size, PAGE_SIZE,
1061 AMDGPU_GEM_DOMAIN_GTT,
1062 &adev->gfx.mec.hpd_eop_obj,
1063 &adev->gfx.mec.hpd_eop_gpu_addr,
1066 dev_warn(adev->dev, "(%d) create HDP EOP bo failed\n", r);
1067 gfx_v10_0_mec_fini(adev);
1071 memset(hpd, 0, adev->gfx.mec.hpd_eop_obj->tbo.mem.size);
1073 amdgpu_bo_kunmap(adev->gfx.mec.hpd_eop_obj);
1074 amdgpu_bo_unreserve(adev->gfx.mec.hpd_eop_obj);
1076 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) {
1077 mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data;
1079 fw_data = (const __le32 *) (adev->gfx.mec_fw->data +
1080 le32_to_cpu(mec_hdr->header.ucode_array_offset_bytes));
1081 fw_size = le32_to_cpu(mec_hdr->header.ucode_size_bytes);
1083 r = amdgpu_bo_create_reserved(adev, mec_hdr->header.ucode_size_bytes,
1084 PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT,
1085 &adev->gfx.mec.mec_fw_obj,
1086 &adev->gfx.mec.mec_fw_gpu_addr,
1089 dev_err(adev->dev, "(%d) failed to create mec fw bo\n", r);
1090 gfx_v10_0_mec_fini(adev);
1094 memcpy(fw, fw_data, fw_size);
1096 amdgpu_bo_kunmap(adev->gfx.mec.mec_fw_obj);
1097 amdgpu_bo_unreserve(adev->gfx.mec.mec_fw_obj);
1103 static uint32_t wave_read_ind(struct amdgpu_device *adev, uint32_t wave, uint32_t address)
1105 WREG32_SOC15(GC, 0, mmSQ_IND_INDEX,
1106 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) |
1107 (address << SQ_IND_INDEX__INDEX__SHIFT));
1108 return RREG32_SOC15(GC, 0, mmSQ_IND_DATA);
1111 static void wave_read_regs(struct amdgpu_device *adev, uint32_t wave,
1112 uint32_t thread, uint32_t regno,
1113 uint32_t num, uint32_t *out)
1115 WREG32_SOC15(GC, 0, mmSQ_IND_INDEX,
1116 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) |
1117 (regno << SQ_IND_INDEX__INDEX__SHIFT) |
1118 (thread << SQ_IND_INDEX__WORKITEM_ID__SHIFT) |
1119 (SQ_IND_INDEX__AUTO_INCR_MASK));
1121 *(out++) = RREG32_SOC15(GC, 0, mmSQ_IND_DATA);
1124 static void gfx_v10_0_read_wave_data(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t *dst, int *no_fields)
1126 /* in gfx10 the SIMD_ID is specified as part of the INSTANCE
1127 * field when performing a select_se_sh so it should be
1131 /* type 2 wave data */
1132 dst[(*no_fields)++] = 2;
1133 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_STATUS);
1134 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_PC_LO);
1135 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_PC_HI);
1136 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_EXEC_LO);
1137 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_EXEC_HI);
1138 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_HW_ID1);
1139 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_HW_ID2);
1140 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_INST_DW0);
1141 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_GPR_ALLOC);
1142 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_LDS_ALLOC);
1143 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_TRAPSTS);
1144 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_IB_STS);
1145 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_IB_STS2);
1146 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_IB_DBG1);
1147 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_M0);
1150 static void gfx_v10_0_read_wave_sgprs(struct amdgpu_device *adev, uint32_t simd,
1151 uint32_t wave, uint32_t start,
1152 uint32_t size, uint32_t *dst)
1157 adev, wave, 0, start + SQIND_WAVE_SGPRS_OFFSET, size,
1161 static void gfx_v10_0_read_wave_vgprs(struct amdgpu_device *adev, uint32_t simd,
1162 uint32_t wave, uint32_t thread,
1163 uint32_t start, uint32_t size,
1168 start + SQIND_WAVE_VGPRS_OFFSET, size, dst);
1171 static void gfx_v10_0_select_me_pipe_q(struct amdgpu_device *adev,
1172 u32 me, u32 pipe, u32 q, u32 vm)
1174 nv_grbm_select(adev, me, pipe, q, vm);
1178 static const struct amdgpu_gfx_funcs gfx_v10_0_gfx_funcs = {
1179 .get_gpu_clock_counter = &gfx_v10_0_get_gpu_clock_counter,
1180 .select_se_sh = &gfx_v10_0_select_se_sh,
1181 .read_wave_data = &gfx_v10_0_read_wave_data,
1182 .read_wave_sgprs = &gfx_v10_0_read_wave_sgprs,
1183 .read_wave_vgprs = &gfx_v10_0_read_wave_vgprs,
1184 .select_me_pipe_q = &gfx_v10_0_select_me_pipe_q,
1187 static void gfx_v10_0_gpu_early_init(struct amdgpu_device *adev)
1191 adev->gfx.funcs = &gfx_v10_0_gfx_funcs;
1193 switch (adev->asic_type) {
1197 adev->gfx.config.max_hw_contexts = 8;
1198 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
1199 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
1200 adev->gfx.config.sc_hiz_tile_fifo_size = 0;
1201 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0;
1202 gb_addr_config = RREG32_SOC15(GC, 0, mmGB_ADDR_CONFIG);
1209 adev->gfx.config.gb_addr_config = gb_addr_config;
1211 adev->gfx.config.gb_addr_config_fields.num_pipes = 1 <<
1212 REG_GET_FIELD(adev->gfx.config.gb_addr_config,
1213 GB_ADDR_CONFIG, NUM_PIPES);
1215 adev->gfx.config.max_tile_pipes =
1216 adev->gfx.config.gb_addr_config_fields.num_pipes;
1218 adev->gfx.config.gb_addr_config_fields.max_compress_frags = 1 <<
1219 REG_GET_FIELD(adev->gfx.config.gb_addr_config,
1220 GB_ADDR_CONFIG, MAX_COMPRESSED_FRAGS);
1221 adev->gfx.config.gb_addr_config_fields.num_rb_per_se = 1 <<
1222 REG_GET_FIELD(adev->gfx.config.gb_addr_config,
1223 GB_ADDR_CONFIG, NUM_RB_PER_SE);
1224 adev->gfx.config.gb_addr_config_fields.num_se = 1 <<
1225 REG_GET_FIELD(adev->gfx.config.gb_addr_config,
1226 GB_ADDR_CONFIG, NUM_SHADER_ENGINES);
1227 adev->gfx.config.gb_addr_config_fields.pipe_interleave_size = 1 << (8 +
1228 REG_GET_FIELD(adev->gfx.config.gb_addr_config,
1229 GB_ADDR_CONFIG, PIPE_INTERLEAVE_SIZE));
1232 static int gfx_v10_0_gfx_ring_init(struct amdgpu_device *adev, int ring_id,
1233 int me, int pipe, int queue)
1236 struct amdgpu_ring *ring;
1237 unsigned int irq_type;
1239 ring = &adev->gfx.gfx_ring[ring_id];
1243 ring->queue = queue;
1245 ring->ring_obj = NULL;
1246 ring->use_doorbell = true;
1249 ring->doorbell_index = adev->doorbell_index.gfx_ring0 << 1;
1251 ring->doorbell_index = adev->doorbell_index.gfx_ring1 << 1;
1252 sprintf(ring->name, "gfx_%d.%d.%d", ring->me, ring->pipe, ring->queue);
1254 irq_type = AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP + ring->pipe;
1255 r = amdgpu_ring_init(adev, ring, 1024,
1256 &adev->gfx.eop_irq, irq_type);
1262 static int gfx_v10_0_compute_ring_init(struct amdgpu_device *adev, int ring_id,
1263 int mec, int pipe, int queue)
1267 struct amdgpu_ring *ring = &adev->gfx.compute_ring[ring_id];
1269 ring = &adev->gfx.compute_ring[ring_id];
1274 ring->queue = queue;
1276 ring->ring_obj = NULL;
1277 ring->use_doorbell = true;
1278 ring->doorbell_index = (adev->doorbell_index.mec_ring0 + ring_id) << 1;
1279 ring->eop_gpu_addr = adev->gfx.mec.hpd_eop_gpu_addr
1280 + (ring_id * GFX10_MEC_HPD_SIZE);
1281 sprintf(ring->name, "comp_%d.%d.%d", ring->me, ring->pipe, ring->queue);
1283 irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP
1284 + ((ring->me - 1) * adev->gfx.mec.num_pipe_per_mec)
1287 /* type-2 packets are deprecated on MEC, use type-3 instead */
1288 r = amdgpu_ring_init(adev, ring, 1024,
1289 &adev->gfx.eop_irq, irq_type);
1296 static int gfx_v10_0_sw_init(void *handle)
1298 int i, j, k, r, ring_id = 0;
1299 struct amdgpu_kiq *kiq;
1300 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1302 switch (adev->asic_type) {
1306 adev->gfx.me.num_me = 1;
1307 adev->gfx.me.num_pipe_per_me = 1;
1308 adev->gfx.me.num_queue_per_pipe = 1;
1309 adev->gfx.mec.num_mec = 2;
1310 adev->gfx.mec.num_pipe_per_mec = 4;
1311 adev->gfx.mec.num_queue_per_pipe = 8;
1314 adev->gfx.me.num_me = 1;
1315 adev->gfx.me.num_pipe_per_me = 1;
1316 adev->gfx.me.num_queue_per_pipe = 1;
1317 adev->gfx.mec.num_mec = 1;
1318 adev->gfx.mec.num_pipe_per_mec = 4;
1319 adev->gfx.mec.num_queue_per_pipe = 8;
1324 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP,
1325 GFX_10_1__SRCID__CP_IB2_INTERRUPT_PKT,
1326 &adev->gfx.kiq.irq);
1331 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP,
1332 GFX_10_1__SRCID__CP_EOP_INTERRUPT,
1333 &adev->gfx.eop_irq);
1337 /* Privileged reg */
1338 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, GFX_10_1__SRCID__CP_PRIV_REG_FAULT,
1339 &adev->gfx.priv_reg_irq);
1343 /* Privileged inst */
1344 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, GFX_10_1__SRCID__CP_PRIV_INSTR_FAULT,
1345 &adev->gfx.priv_inst_irq);
1349 adev->gfx.gfx_current_status = AMDGPU_GFX_NORMAL_MODE;
1351 gfx_v10_0_scratch_init(adev);
1353 r = gfx_v10_0_me_init(adev);
1357 r = gfx_v10_0_rlc_init(adev);
1359 DRM_ERROR("Failed to init rlc BOs!\n");
1363 r = gfx_v10_0_mec_init(adev);
1365 DRM_ERROR("Failed to init MEC BOs!\n");
1369 /* set up the gfx ring */
1370 for (i = 0; i < adev->gfx.me.num_me; i++) {
1371 for (j = 0; j < adev->gfx.me.num_queue_per_pipe; j++) {
1372 for (k = 0; k < adev->gfx.me.num_pipe_per_me; k++) {
1373 if (!amdgpu_gfx_is_me_queue_enabled(adev, i, k, j))
1376 r = gfx_v10_0_gfx_ring_init(adev, ring_id,
1386 /* set up the compute queues - allocate horizontally across pipes */
1387 for (i = 0; i < adev->gfx.mec.num_mec; ++i) {
1388 for (j = 0; j < adev->gfx.mec.num_queue_per_pipe; j++) {
1389 for (k = 0; k < adev->gfx.mec.num_pipe_per_mec; k++) {
1390 if (!amdgpu_gfx_is_mec_queue_enabled(adev, i, k,
1394 r = gfx_v10_0_compute_ring_init(adev, ring_id,
1404 r = amdgpu_gfx_kiq_init(adev, GFX10_MEC_HPD_SIZE);
1406 DRM_ERROR("Failed to init KIQ BOs!\n");
1410 kiq = &adev->gfx.kiq;
1411 r = amdgpu_gfx_kiq_init_ring(adev, &kiq->ring, &kiq->irq);
1415 r = amdgpu_gfx_mqd_sw_init(adev, sizeof(struct v10_compute_mqd));
1419 /* allocate visible FB for rlc auto-loading fw */
1420 if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) {
1421 r = gfx_v10_0_rlc_backdoor_autoload_buffer_init(adev);
1426 adev->gfx.ce_ram_size = F32_CE_PROGRAM_RAM_SIZE;
1428 gfx_v10_0_gpu_early_init(adev);
1433 static void gfx_v10_0_pfp_fini(struct amdgpu_device *adev)
1435 amdgpu_bo_free_kernel(&adev->gfx.pfp.pfp_fw_obj,
1436 &adev->gfx.pfp.pfp_fw_gpu_addr,
1437 (void **)&adev->gfx.pfp.pfp_fw_ptr);
1440 static void gfx_v10_0_ce_fini(struct amdgpu_device *adev)
1442 amdgpu_bo_free_kernel(&adev->gfx.ce.ce_fw_obj,
1443 &adev->gfx.ce.ce_fw_gpu_addr,
1444 (void **)&adev->gfx.ce.ce_fw_ptr);
1447 static void gfx_v10_0_me_fini(struct amdgpu_device *adev)
1449 amdgpu_bo_free_kernel(&adev->gfx.me.me_fw_obj,
1450 &adev->gfx.me.me_fw_gpu_addr,
1451 (void **)&adev->gfx.me.me_fw_ptr);
1454 static int gfx_v10_0_sw_fini(void *handle)
1457 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1459 for (i = 0; i < adev->gfx.num_gfx_rings; i++)
1460 amdgpu_ring_fini(&adev->gfx.gfx_ring[i]);
1461 for (i = 0; i < adev->gfx.num_compute_rings; i++)
1462 amdgpu_ring_fini(&adev->gfx.compute_ring[i]);
1464 amdgpu_gfx_mqd_sw_fini(adev);
1465 amdgpu_gfx_kiq_free_ring(&adev->gfx.kiq.ring);
1466 amdgpu_gfx_kiq_fini(adev);
1468 gfx_v10_0_pfp_fini(adev);
1469 gfx_v10_0_ce_fini(adev);
1470 gfx_v10_0_me_fini(adev);
1471 gfx_v10_0_rlc_fini(adev);
1472 gfx_v10_0_mec_fini(adev);
1474 if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO)
1475 gfx_v10_0_rlc_backdoor_autoload_buffer_fini(adev);
1477 gfx_v10_0_free_microcode(adev);
1483 static void gfx_v10_0_tiling_mode_table_init(struct amdgpu_device *adev)
1488 static void gfx_v10_0_select_se_sh(struct amdgpu_device *adev, u32 se_num,
1489 u32 sh_num, u32 instance)
1493 if (instance == 0xffffffff)
1494 data = REG_SET_FIELD(0, GRBM_GFX_INDEX,
1495 INSTANCE_BROADCAST_WRITES, 1);
1497 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_INDEX,
1500 if (se_num == 0xffffffff)
1501 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_BROADCAST_WRITES,
1504 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_INDEX, se_num);
1506 if (sh_num == 0xffffffff)
1507 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SA_BROADCAST_WRITES,
1510 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SA_INDEX, sh_num);
1512 WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, data);
1515 static u32 gfx_v10_0_get_rb_active_bitmap(struct amdgpu_device *adev)
1519 data = RREG32_SOC15(GC, 0, mmCC_RB_BACKEND_DISABLE);
1520 data |= RREG32_SOC15(GC, 0, mmGC_USER_RB_BACKEND_DISABLE);
1522 data &= CC_RB_BACKEND_DISABLE__BACKEND_DISABLE_MASK;
1523 data >>= GC_USER_RB_BACKEND_DISABLE__BACKEND_DISABLE__SHIFT;
1525 mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_backends_per_se /
1526 adev->gfx.config.max_sh_per_se);
1528 return (~data) & mask;
1531 static void gfx_v10_0_setup_rb(struct amdgpu_device *adev)
1536 u32 rb_bitmap_width_per_sh = adev->gfx.config.max_backends_per_se /
1537 adev->gfx.config.max_sh_per_se;
1539 mutex_lock(&adev->grbm_idx_mutex);
1540 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
1541 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
1542 gfx_v10_0_select_se_sh(adev, i, j, 0xffffffff);
1543 data = gfx_v10_0_get_rb_active_bitmap(adev);
1544 active_rbs |= data << ((i * adev->gfx.config.max_sh_per_se + j) *
1545 rb_bitmap_width_per_sh);
1548 gfx_v10_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
1549 mutex_unlock(&adev->grbm_idx_mutex);
1551 adev->gfx.config.backend_enable_mask = active_rbs;
1552 adev->gfx.config.num_rbs = hweight32(active_rbs);
1555 static u32 gfx_v10_0_init_pa_sc_tile_steering_override(struct amdgpu_device *adev)
1558 uint32_t enabled_rb_per_sh;
1559 uint32_t active_rb_bitmap;
1560 uint32_t num_rb_per_sc;
1561 uint32_t num_packer_per_sc;
1562 uint32_t pa_sc_tile_steering_override;
1565 num_sc = adev->gfx.config.max_shader_engines * adev->gfx.config.max_sh_per_se *
1566 adev->gfx.config.num_sc_per_sh;
1567 /* init num_rb_per_sc */
1568 active_rb_bitmap = gfx_v10_0_get_rb_active_bitmap(adev);
1569 enabled_rb_per_sh = hweight32(active_rb_bitmap);
1570 num_rb_per_sc = enabled_rb_per_sh / adev->gfx.config.num_sc_per_sh;
1571 /* init num_packer_per_sc */
1572 num_packer_per_sc = adev->gfx.config.num_packer_per_sc;
1574 pa_sc_tile_steering_override = 0;
1575 pa_sc_tile_steering_override |=
1576 (order_base_2(num_sc) << PA_SC_TILE_STEERING_OVERRIDE__NUM_SC__SHIFT) &
1577 PA_SC_TILE_STEERING_OVERRIDE__NUM_SC_MASK;
1578 pa_sc_tile_steering_override |=
1579 (order_base_2(num_rb_per_sc) << PA_SC_TILE_STEERING_OVERRIDE__NUM_RB_PER_SC__SHIFT) &
1580 PA_SC_TILE_STEERING_OVERRIDE__NUM_RB_PER_SC_MASK;
1581 pa_sc_tile_steering_override |=
1582 (order_base_2(num_packer_per_sc) << PA_SC_TILE_STEERING_OVERRIDE__NUM_PACKER_PER_SC__SHIFT) &
1583 PA_SC_TILE_STEERING_OVERRIDE__NUM_PACKER_PER_SC_MASK;
1585 return pa_sc_tile_steering_override;
1588 #define DEFAULT_SH_MEM_BASES (0x6000)
1589 #define FIRST_COMPUTE_VMID (8)
1590 #define LAST_COMPUTE_VMID (16)
1592 static void gfx_v10_0_init_compute_vmid(struct amdgpu_device *adev)
1595 uint32_t sh_mem_bases;
1598 * Configure apertures:
1599 * LDS: 0x60000000'00000000 - 0x60000001'00000000 (4GB)
1600 * Scratch: 0x60000001'00000000 - 0x60000002'00000000 (4GB)
1601 * GPUVM: 0x60010000'00000000 - 0x60020000'00000000 (1TB)
1603 sh_mem_bases = DEFAULT_SH_MEM_BASES | (DEFAULT_SH_MEM_BASES << 16);
1605 mutex_lock(&adev->srbm_mutex);
1606 for (i = FIRST_COMPUTE_VMID; i < LAST_COMPUTE_VMID; i++) {
1607 nv_grbm_select(adev, 0, 0, 0, i);
1608 /* CP and shaders */
1609 WREG32_SOC15(GC, 0, mmSH_MEM_CONFIG, DEFAULT_SH_MEM_CONFIG);
1610 WREG32_SOC15(GC, 0, mmSH_MEM_BASES, sh_mem_bases);
1612 nv_grbm_select(adev, 0, 0, 0, 0);
1613 mutex_unlock(&adev->srbm_mutex);
1615 /* Initialize all compute VMIDs to have no GDS, GWS, or OA
1616 acccess. These should be enabled by FW for target VMIDs. */
1617 for (i = FIRST_COMPUTE_VMID; i < LAST_COMPUTE_VMID; i++) {
1618 WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_BASE, 2 * i, 0);
1619 WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_SIZE, 2 * i, 0);
1620 WREG32_SOC15_OFFSET(GC, 0, mmGDS_GWS_VMID0, i, 0);
1621 WREG32_SOC15_OFFSET(GC, 0, mmGDS_OA_VMID0, i, 0);
1625 static void gfx_v10_0_init_gds_vmid(struct amdgpu_device *adev)
1630 * Initialize all compute and user-gfx VMIDs to have no GDS, GWS, or OA
1631 * access. Compute VMIDs should be enabled by FW for target VMIDs,
1632 * the driver can enable them for graphics. VMID0 should maintain
1633 * access so that HWS firmware can save/restore entries.
1635 for (vmid = 1; vmid < 16; vmid++) {
1636 WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_BASE, 2 * vmid, 0);
1637 WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_SIZE, 2 * vmid, 0);
1638 WREG32_SOC15_OFFSET(GC, 0, mmGDS_GWS_VMID0, vmid, 0);
1639 WREG32_SOC15_OFFSET(GC, 0, mmGDS_OA_VMID0, vmid, 0);
1644 static void gfx_v10_0_tcp_harvest(struct amdgpu_device *adev)
1647 int max_wgp_per_sh = adev->gfx.config.max_cu_per_sh >> 1;
1648 u32 tmp, wgp_active_bitmap = 0;
1649 u32 gcrd_targets_disable_tcp = 0;
1650 u32 utcl_invreq_disable = 0;
1652 * GCRD_TARGETS_DISABLE field contains
1653 * for Navi10/Navi12: GL1C=[18:15], SQC=[14:10], TCP=[9:0]
1654 * for Navi14: GL1C=[21:18], SQC=[17:12], TCP=[11:0]
1656 u32 gcrd_targets_disable_mask = amdgpu_gfx_create_bitmask(
1657 2 * max_wgp_per_sh + /* TCP */
1658 max_wgp_per_sh + /* SQC */
1661 * UTCL1_UTCL0_INVREQ_DISABLE field contains
1662 * for Navi10Navi12: SQG=[24], RMI=[23:20], SQC=[19:10], TCP=[9:0]
1663 * for Navi14: SQG=[28], RMI=[27:24], SQC=[23:12], TCP=[11:0]
1665 u32 utcl_invreq_disable_mask = amdgpu_gfx_create_bitmask(
1666 2 * max_wgp_per_sh + /* TCP */
1667 2 * max_wgp_per_sh + /* SQC */
1671 if (adev->asic_type == CHIP_NAVI10 ||
1672 adev->asic_type == CHIP_NAVI14 ||
1673 adev->asic_type == CHIP_NAVI12) {
1674 mutex_lock(&adev->grbm_idx_mutex);
1675 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
1676 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
1677 gfx_v10_0_select_se_sh(adev, i, j, 0xffffffff);
1678 wgp_active_bitmap = gfx_v10_0_get_wgp_active_bitmap_per_sh(adev);
1680 * Set corresponding TCP bits for the inactive WGPs in
1681 * GCRD_SA_TARGETS_DISABLE
1683 gcrd_targets_disable_tcp = 0;
1684 /* Set TCP & SQC bits in UTCL1_UTCL0_INVREQ_DISABLE */
1685 utcl_invreq_disable = 0;
1687 for (k = 0; k < max_wgp_per_sh; k++) {
1688 if (!(wgp_active_bitmap & (1 << k))) {
1689 gcrd_targets_disable_tcp |= 3 << (2 * k);
1690 utcl_invreq_disable |= (3 << (2 * k)) |
1691 (3 << (2 * (max_wgp_per_sh + k)));
1695 tmp = RREG32_SOC15(GC, 0, mmUTCL1_UTCL0_INVREQ_DISABLE);
1696 /* only override TCP & SQC bits */
1697 tmp &= 0xffffffff << (4 * max_wgp_per_sh);
1698 tmp |= (utcl_invreq_disable & utcl_invreq_disable_mask);
1699 WREG32_SOC15(GC, 0, mmUTCL1_UTCL0_INVREQ_DISABLE, tmp);
1701 tmp = RREG32_SOC15(GC, 0, mmGCRD_SA_TARGETS_DISABLE);
1702 /* only override TCP bits */
1703 tmp &= 0xffffffff << (2 * max_wgp_per_sh);
1704 tmp |= (gcrd_targets_disable_tcp & gcrd_targets_disable_mask);
1705 WREG32_SOC15(GC, 0, mmGCRD_SA_TARGETS_DISABLE, tmp);
1709 gfx_v10_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
1710 mutex_unlock(&adev->grbm_idx_mutex);
1714 static void gfx_v10_0_get_tcc_info(struct amdgpu_device *adev)
1716 /* TCCs are global (not instanced). */
1717 uint32_t tcc_disable = RREG32_SOC15(GC, 0, mmCGTS_TCC_DISABLE) |
1718 RREG32_SOC15(GC, 0, mmCGTS_USER_TCC_DISABLE);
1720 adev->gfx.config.tcc_disabled_mask =
1721 REG_GET_FIELD(tcc_disable, CGTS_TCC_DISABLE, TCC_DISABLE) |
1722 (REG_GET_FIELD(tcc_disable, CGTS_TCC_DISABLE, HI_TCC_DISABLE) << 16);
1725 static void gfx_v10_0_constants_init(struct amdgpu_device *adev)
1730 WREG32_FIELD15(GC, 0, GRBM_CNTL, READ_TIMEOUT, 0xff);
1732 gfx_v10_0_tiling_mode_table_init(adev);
1734 gfx_v10_0_setup_rb(adev);
1735 gfx_v10_0_get_cu_info(adev, &adev->gfx.cu_info);
1736 gfx_v10_0_get_tcc_info(adev);
1737 adev->gfx.config.pa_sc_tile_steering_override =
1738 gfx_v10_0_init_pa_sc_tile_steering_override(adev);
1740 /* XXX SH_MEM regs */
1741 /* where to put LDS, scratch, GPUVM in FSA64 space */
1742 mutex_lock(&adev->srbm_mutex);
1743 for (i = 0; i < adev->vm_manager.id_mgr[AMDGPU_GFXHUB_0].num_ids; i++) {
1744 nv_grbm_select(adev, 0, 0, 0, i);
1745 /* CP and shaders */
1746 WREG32_SOC15(GC, 0, mmSH_MEM_CONFIG, DEFAULT_SH_MEM_CONFIG);
1748 tmp = REG_SET_FIELD(0, SH_MEM_BASES, PRIVATE_BASE,
1749 (adev->gmc.private_aperture_start >> 48));
1750 tmp = REG_SET_FIELD(tmp, SH_MEM_BASES, SHARED_BASE,
1751 (adev->gmc.shared_aperture_start >> 48));
1752 WREG32_SOC15(GC, 0, mmSH_MEM_BASES, tmp);
1755 nv_grbm_select(adev, 0, 0, 0, 0);
1757 mutex_unlock(&adev->srbm_mutex);
1759 gfx_v10_0_init_compute_vmid(adev);
1760 gfx_v10_0_init_gds_vmid(adev);
1764 static void gfx_v10_0_enable_gui_idle_interrupt(struct amdgpu_device *adev,
1767 u32 tmp = RREG32_SOC15(GC, 0, mmCP_INT_CNTL_RING0);
1769 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_BUSY_INT_ENABLE,
1771 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_EMPTY_INT_ENABLE,
1773 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CMP_BUSY_INT_ENABLE,
1775 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, GFX_IDLE_INT_ENABLE,
1778 WREG32_SOC15(GC, 0, mmCP_INT_CNTL_RING0, tmp);
1781 static int gfx_v10_0_init_csb(struct amdgpu_device *adev)
1783 adev->gfx.rlc.funcs->get_csb_buffer(adev, adev->gfx.rlc.cs_ptr);
1786 WREG32_SOC15_RLC(GC, 0, mmRLC_CSIB_ADDR_HI,
1787 adev->gfx.rlc.clear_state_gpu_addr >> 32);
1788 WREG32_SOC15_RLC(GC, 0, mmRLC_CSIB_ADDR_LO,
1789 adev->gfx.rlc.clear_state_gpu_addr & 0xfffffffc);
1790 WREG32_SOC15_RLC(GC, 0, mmRLC_CSIB_LENGTH, adev->gfx.rlc.clear_state_size);
1795 void gfx_v10_0_rlc_stop(struct amdgpu_device *adev)
1797 u32 tmp = RREG32_SOC15(GC, 0, mmRLC_CNTL);
1799 tmp = REG_SET_FIELD(tmp, RLC_CNTL, RLC_ENABLE_F32, 0);
1800 WREG32_SOC15(GC, 0, mmRLC_CNTL, tmp);
1803 static void gfx_v10_0_rlc_reset(struct amdgpu_device *adev)
1805 WREG32_FIELD15(GC, 0, GRBM_SOFT_RESET, SOFT_RESET_RLC, 1);
1807 WREG32_FIELD15(GC, 0, GRBM_SOFT_RESET, SOFT_RESET_RLC, 0);
1811 static void gfx_v10_0_rlc_smu_handshake_cntl(struct amdgpu_device *adev,
1814 uint32_t rlc_pg_cntl;
1816 rlc_pg_cntl = RREG32_SOC15(GC, 0, mmRLC_PG_CNTL);
1819 /* RLC_PG_CNTL[23] = 0 (default)
1820 * RLC will wait for handshake acks with SMU
1821 * GFXOFF will be enabled
1822 * RLC_PG_CNTL[23] = 1
1823 * RLC will not issue any message to SMU
1824 * hence no handshake between SMU & RLC
1825 * GFXOFF will be disabled
1827 rlc_pg_cntl |= 0x800000;
1829 rlc_pg_cntl &= ~0x800000;
1830 WREG32_SOC15(GC, 0, mmRLC_PG_CNTL, rlc_pg_cntl);
1833 static void gfx_v10_0_rlc_start(struct amdgpu_device *adev)
1835 /* TODO: enable rlc & smu handshake until smu
1836 * and gfxoff feature works as expected */
1837 if (!(amdgpu_pp_feature_mask & PP_GFXOFF_MASK))
1838 gfx_v10_0_rlc_smu_handshake_cntl(adev, false);
1840 WREG32_FIELD15(GC, 0, RLC_CNTL, RLC_ENABLE_F32, 1);
1844 static void gfx_v10_0_rlc_enable_srm(struct amdgpu_device *adev)
1848 /* enable Save Restore Machine */
1849 tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_CNTL));
1850 tmp |= RLC_SRM_CNTL__AUTO_INCR_ADDR_MASK;
1851 tmp |= RLC_SRM_CNTL__SRM_ENABLE_MASK;
1852 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_CNTL), tmp);
1855 static int gfx_v10_0_rlc_load_microcode(struct amdgpu_device *adev)
1857 const struct rlc_firmware_header_v2_0 *hdr;
1858 const __le32 *fw_data;
1859 unsigned i, fw_size;
1861 if (!adev->gfx.rlc_fw)
1864 hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data;
1865 amdgpu_ucode_print_rlc_hdr(&hdr->header);
1867 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data +
1868 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
1869 fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
1871 WREG32_SOC15(GC, 0, mmRLC_GPM_UCODE_ADDR,
1872 RLCG_UCODE_LOADING_START_ADDRESS);
1874 for (i = 0; i < fw_size; i++)
1875 WREG32_SOC15(GC, 0, mmRLC_GPM_UCODE_DATA,
1876 le32_to_cpup(fw_data++));
1878 WREG32_SOC15(GC, 0, mmRLC_GPM_UCODE_ADDR, adev->gfx.rlc_fw_version);
1883 static int gfx_v10_0_rlc_resume(struct amdgpu_device *adev)
1887 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
1889 r = gfx_v10_0_wait_for_rlc_autoload_complete(adev);
1893 gfx_v10_0_init_csb(adev);
1895 if (!amdgpu_sriov_vf(adev)) /* enable RLC SRM */
1896 gfx_v10_0_rlc_enable_srm(adev);
1898 adev->gfx.rlc.funcs->stop(adev);
1901 WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL, 0);
1904 WREG32_SOC15(GC, 0, mmRLC_PG_CNTL, 0);
1906 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) {
1907 /* legacy rlc firmware loading */
1908 r = gfx_v10_0_rlc_load_microcode(adev);
1911 } else if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) {
1912 /* rlc backdoor autoload firmware */
1913 r = gfx_v10_0_rlc_backdoor_autoload_enable(adev);
1918 gfx_v10_0_init_csb(adev);
1920 adev->gfx.rlc.funcs->start(adev);
1922 if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) {
1923 r = gfx_v10_0_wait_for_rlc_autoload_complete(adev);
1933 unsigned int offset;
1935 } rlc_autoload_info[FIRMWARE_ID_MAX];
1937 static int gfx_v10_0_parse_rlc_toc(struct amdgpu_device *adev)
1940 RLC_TABLE_OF_CONTENT *rlc_toc;
1942 ret = amdgpu_bo_create_reserved(adev, adev->psp.toc_bin_size, PAGE_SIZE,
1943 AMDGPU_GEM_DOMAIN_GTT,
1944 &adev->gfx.rlc.rlc_toc_bo,
1945 &adev->gfx.rlc.rlc_toc_gpu_addr,
1946 (void **)&adev->gfx.rlc.rlc_toc_buf);
1948 dev_err(adev->dev, "(%d) failed to create rlc toc bo\n", ret);
1952 /* Copy toc from psp sos fw to rlc toc buffer */
1953 memcpy(adev->gfx.rlc.rlc_toc_buf, adev->psp.toc_start_addr, adev->psp.toc_bin_size);
1955 rlc_toc = (RLC_TABLE_OF_CONTENT *)adev->gfx.rlc.rlc_toc_buf;
1956 while (rlc_toc && (rlc_toc->id > FIRMWARE_ID_INVALID) &&
1957 (rlc_toc->id < FIRMWARE_ID_MAX)) {
1958 if ((rlc_toc->id >= FIRMWARE_ID_CP_CE) &&
1959 (rlc_toc->id <= FIRMWARE_ID_CP_MES)) {
1960 /* Offset needs 4KB alignment */
1961 rlc_toc->offset = ALIGN(rlc_toc->offset * 4, PAGE_SIZE);
1964 rlc_autoload_info[rlc_toc->id].id = rlc_toc->id;
1965 rlc_autoload_info[rlc_toc->id].offset = rlc_toc->offset * 4;
1966 rlc_autoload_info[rlc_toc->id].size = rlc_toc->size * 4;
1974 static uint32_t gfx_v10_0_calc_toc_total_size(struct amdgpu_device *adev)
1976 uint32_t total_size = 0;
1980 ret = gfx_v10_0_parse_rlc_toc(adev);
1982 dev_err(adev->dev, "failed to parse rlc toc\n");
1986 for (id = FIRMWARE_ID_RLC_G_UCODE; id < FIRMWARE_ID_MAX; id++)
1987 total_size += rlc_autoload_info[id].size;
1989 /* In case the offset in rlc toc ucode is aligned */
1990 if (total_size < rlc_autoload_info[FIRMWARE_ID_MAX-1].offset)
1991 total_size = rlc_autoload_info[FIRMWARE_ID_MAX-1].offset +
1992 rlc_autoload_info[FIRMWARE_ID_MAX-1].size;
1997 static int gfx_v10_0_rlc_backdoor_autoload_buffer_init(struct amdgpu_device *adev)
2000 uint32_t total_size;
2002 total_size = gfx_v10_0_calc_toc_total_size(adev);
2004 r = amdgpu_bo_create_reserved(adev, total_size, PAGE_SIZE,
2005 AMDGPU_GEM_DOMAIN_GTT,
2006 &adev->gfx.rlc.rlc_autoload_bo,
2007 &adev->gfx.rlc.rlc_autoload_gpu_addr,
2008 (void **)&adev->gfx.rlc.rlc_autoload_ptr);
2010 dev_err(adev->dev, "(%d) failed to create fw autoload bo\n", r);
2017 static void gfx_v10_0_rlc_backdoor_autoload_buffer_fini(struct amdgpu_device *adev)
2019 amdgpu_bo_free_kernel(&adev->gfx.rlc.rlc_toc_bo,
2020 &adev->gfx.rlc.rlc_toc_gpu_addr,
2021 (void **)&adev->gfx.rlc.rlc_toc_buf);
2022 amdgpu_bo_free_kernel(&adev->gfx.rlc.rlc_autoload_bo,
2023 &adev->gfx.rlc.rlc_autoload_gpu_addr,
2024 (void **)&adev->gfx.rlc.rlc_autoload_ptr);
2027 static void gfx_v10_0_rlc_backdoor_autoload_copy_ucode(struct amdgpu_device *adev,
2029 const void *fw_data,
2032 uint32_t toc_offset;
2033 uint32_t toc_fw_size;
2034 char *ptr = adev->gfx.rlc.rlc_autoload_ptr;
2036 if (id <= FIRMWARE_ID_INVALID || id >= FIRMWARE_ID_MAX)
2039 toc_offset = rlc_autoload_info[id].offset;
2040 toc_fw_size = rlc_autoload_info[id].size;
2043 fw_size = toc_fw_size;
2045 if (fw_size > toc_fw_size)
2046 fw_size = toc_fw_size;
2048 memcpy(ptr + toc_offset, fw_data, fw_size);
2050 if (fw_size < toc_fw_size)
2051 memset(ptr + toc_offset + fw_size, 0, toc_fw_size - fw_size);
2054 static void gfx_v10_0_rlc_backdoor_autoload_copy_toc_ucode(struct amdgpu_device *adev)
2059 data = adev->gfx.rlc.rlc_toc_buf;
2060 size = rlc_autoload_info[FIRMWARE_ID_RLC_TOC].size;
2062 gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
2063 FIRMWARE_ID_RLC_TOC,
2067 static void gfx_v10_0_rlc_backdoor_autoload_copy_gfx_ucode(struct amdgpu_device *adev)
2069 const __le32 *fw_data;
2071 const struct gfx_firmware_header_v1_0 *cp_hdr;
2072 const struct rlc_firmware_header_v2_0 *rlc_hdr;
2075 cp_hdr = (const struct gfx_firmware_header_v1_0 *)
2076 adev->gfx.pfp_fw->data;
2077 fw_data = (const __le32 *)(adev->gfx.pfp_fw->data +
2078 le32_to_cpu(cp_hdr->header.ucode_array_offset_bytes));
2079 fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes);
2080 gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
2085 cp_hdr = (const struct gfx_firmware_header_v1_0 *)
2086 adev->gfx.ce_fw->data;
2087 fw_data = (const __le32 *)(adev->gfx.ce_fw->data +
2088 le32_to_cpu(cp_hdr->header.ucode_array_offset_bytes));
2089 fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes);
2090 gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
2095 cp_hdr = (const struct gfx_firmware_header_v1_0 *)
2096 adev->gfx.me_fw->data;
2097 fw_data = (const __le32 *)(adev->gfx.me_fw->data +
2098 le32_to_cpu(cp_hdr->header.ucode_array_offset_bytes));
2099 fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes);
2100 gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
2105 rlc_hdr = (const struct rlc_firmware_header_v2_0 *)
2106 adev->gfx.rlc_fw->data;
2107 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data +
2108 le32_to_cpu(rlc_hdr->header.ucode_array_offset_bytes));
2109 fw_size = le32_to_cpu(rlc_hdr->header.ucode_size_bytes);
2110 gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
2111 FIRMWARE_ID_RLC_G_UCODE,
2115 cp_hdr = (const struct gfx_firmware_header_v1_0 *)
2116 adev->gfx.mec_fw->data;
2117 fw_data = (const __le32 *) (adev->gfx.mec_fw->data +
2118 le32_to_cpu(cp_hdr->header.ucode_array_offset_bytes));
2119 fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes) -
2120 cp_hdr->jt_size * 4;
2121 gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
2124 /* mec2 ucode is not necessary if mec2 ucode is same as mec1 */
2127 /* Temporarily put sdma part here */
2128 static void gfx_v10_0_rlc_backdoor_autoload_copy_sdma_ucode(struct amdgpu_device *adev)
2130 const __le32 *fw_data;
2132 const struct sdma_firmware_header_v1_0 *sdma_hdr;
2135 for (i = 0; i < adev->sdma.num_instances; i++) {
2136 sdma_hdr = (const struct sdma_firmware_header_v1_0 *)
2137 adev->sdma.instance[i].fw->data;
2138 fw_data = (const __le32 *) (adev->sdma.instance[i].fw->data +
2139 le32_to_cpu(sdma_hdr->header.ucode_array_offset_bytes));
2140 fw_size = le32_to_cpu(sdma_hdr->header.ucode_size_bytes);
2143 gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
2144 FIRMWARE_ID_SDMA0_UCODE, fw_data, fw_size);
2145 gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
2146 FIRMWARE_ID_SDMA0_JT,
2147 (uint32_t *)fw_data +
2148 sdma_hdr->jt_offset,
2149 sdma_hdr->jt_size * 4);
2150 } else if (i == 1) {
2151 gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
2152 FIRMWARE_ID_SDMA1_UCODE, fw_data, fw_size);
2153 gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
2154 FIRMWARE_ID_SDMA1_JT,
2155 (uint32_t *)fw_data +
2156 sdma_hdr->jt_offset,
2157 sdma_hdr->jt_size * 4);
2162 static int gfx_v10_0_rlc_backdoor_autoload_enable(struct amdgpu_device *adev)
2164 uint32_t rlc_g_offset, rlc_g_size, tmp;
2167 gfx_v10_0_rlc_backdoor_autoload_copy_toc_ucode(adev);
2168 gfx_v10_0_rlc_backdoor_autoload_copy_sdma_ucode(adev);
2169 gfx_v10_0_rlc_backdoor_autoload_copy_gfx_ucode(adev);
2171 rlc_g_offset = rlc_autoload_info[FIRMWARE_ID_RLC_G_UCODE].offset;
2172 rlc_g_size = rlc_autoload_info[FIRMWARE_ID_RLC_G_UCODE].size;
2173 gpu_addr = adev->gfx.rlc.rlc_autoload_gpu_addr + rlc_g_offset;
2175 WREG32_SOC15(GC, 0, mmRLC_HYP_BOOTLOAD_ADDR_HI, upper_32_bits(gpu_addr));
2176 WREG32_SOC15(GC, 0, mmRLC_HYP_BOOTLOAD_ADDR_LO, lower_32_bits(gpu_addr));
2177 WREG32_SOC15(GC, 0, mmRLC_HYP_BOOTLOAD_SIZE, rlc_g_size);
2179 tmp = RREG32_SOC15(GC, 0, mmRLC_HYP_RESET_VECTOR);
2180 if (!(tmp & (RLC_HYP_RESET_VECTOR__COLD_BOOT_EXIT_MASK |
2181 RLC_HYP_RESET_VECTOR__VDDGFX_EXIT_MASK))) {
2182 DRM_ERROR("Neither COLD_BOOT_EXIT nor VDDGFX_EXIT is set\n");
2186 tmp = RREG32_SOC15(GC, 0, mmRLC_CNTL);
2187 if (tmp & RLC_CNTL__RLC_ENABLE_F32_MASK) {
2188 DRM_ERROR("RLC ROM should halt itself\n");
2195 static int gfx_v10_0_rlc_backdoor_autoload_config_me_cache(struct amdgpu_device *adev)
2197 uint32_t usec_timeout = 50000; /* wait for 50ms */
2202 /* Trigger an invalidation of the L1 instruction caches */
2203 tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL);
2204 tmp = REG_SET_FIELD(tmp, CP_ME_IC_OP_CNTL, INVALIDATE_CACHE, 1);
2205 WREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL, tmp);
2207 /* Wait for invalidation complete */
2208 for (i = 0; i < usec_timeout; i++) {
2209 tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL);
2210 if (1 == REG_GET_FIELD(tmp, CP_ME_IC_OP_CNTL,
2211 INVALIDATE_CACHE_COMPLETE))
2216 if (i >= usec_timeout) {
2217 dev_err(adev->dev, "failed to invalidate instruction cache\n");
2221 /* Program me ucode address into intruction cache address register */
2222 addr = adev->gfx.rlc.rlc_autoload_gpu_addr +
2223 rlc_autoload_info[FIRMWARE_ID_CP_ME].offset;
2224 WREG32_SOC15(GC, 0, mmCP_ME_IC_BASE_LO,
2225 lower_32_bits(addr) & 0xFFFFF000);
2226 WREG32_SOC15(GC, 0, mmCP_ME_IC_BASE_HI,
2227 upper_32_bits(addr));
2232 static int gfx_v10_0_rlc_backdoor_autoload_config_ce_cache(struct amdgpu_device *adev)
2234 uint32_t usec_timeout = 50000; /* wait for 50ms */
2239 /* Trigger an invalidation of the L1 instruction caches */
2240 tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL);
2241 tmp = REG_SET_FIELD(tmp, CP_CE_IC_OP_CNTL, INVALIDATE_CACHE, 1);
2242 WREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL, tmp);
2244 /* Wait for invalidation complete */
2245 for (i = 0; i < usec_timeout; i++) {
2246 tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL);
2247 if (1 == REG_GET_FIELD(tmp, CP_CE_IC_OP_CNTL,
2248 INVALIDATE_CACHE_COMPLETE))
2253 if (i >= usec_timeout) {
2254 dev_err(adev->dev, "failed to invalidate instruction cache\n");
2258 /* Program ce ucode address into intruction cache address register */
2259 addr = adev->gfx.rlc.rlc_autoload_gpu_addr +
2260 rlc_autoload_info[FIRMWARE_ID_CP_CE].offset;
2261 WREG32_SOC15(GC, 0, mmCP_CE_IC_BASE_LO,
2262 lower_32_bits(addr) & 0xFFFFF000);
2263 WREG32_SOC15(GC, 0, mmCP_CE_IC_BASE_HI,
2264 upper_32_bits(addr));
2269 static int gfx_v10_0_rlc_backdoor_autoload_config_pfp_cache(struct amdgpu_device *adev)
2271 uint32_t usec_timeout = 50000; /* wait for 50ms */
2276 /* Trigger an invalidation of the L1 instruction caches */
2277 tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL);
2278 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_OP_CNTL, INVALIDATE_CACHE, 1);
2279 WREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL, tmp);
2281 /* Wait for invalidation complete */
2282 for (i = 0; i < usec_timeout; i++) {
2283 tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL);
2284 if (1 == REG_GET_FIELD(tmp, CP_PFP_IC_OP_CNTL,
2285 INVALIDATE_CACHE_COMPLETE))
2290 if (i >= usec_timeout) {
2291 dev_err(adev->dev, "failed to invalidate instruction cache\n");
2295 /* Program pfp ucode address into intruction cache address register */
2296 addr = adev->gfx.rlc.rlc_autoload_gpu_addr +
2297 rlc_autoload_info[FIRMWARE_ID_CP_PFP].offset;
2298 WREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_LO,
2299 lower_32_bits(addr) & 0xFFFFF000);
2300 WREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_HI,
2301 upper_32_bits(addr));
2306 static int gfx_v10_0_rlc_backdoor_autoload_config_mec_cache(struct amdgpu_device *adev)
2308 uint32_t usec_timeout = 50000; /* wait for 50ms */
2313 /* Trigger an invalidation of the L1 instruction caches */
2314 tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL);
2315 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_OP_CNTL, INVALIDATE_CACHE, 1);
2316 WREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL, tmp);
2318 /* Wait for invalidation complete */
2319 for (i = 0; i < usec_timeout; i++) {
2320 tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL);
2321 if (1 == REG_GET_FIELD(tmp, CP_CPC_IC_OP_CNTL,
2322 INVALIDATE_CACHE_COMPLETE))
2327 if (i >= usec_timeout) {
2328 dev_err(adev->dev, "failed to invalidate instruction cache\n");
2332 /* Program mec1 ucode address into intruction cache address register */
2333 addr = adev->gfx.rlc.rlc_autoload_gpu_addr +
2334 rlc_autoload_info[FIRMWARE_ID_CP_MEC].offset;
2335 WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_LO,
2336 lower_32_bits(addr) & 0xFFFFF000);
2337 WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_HI,
2338 upper_32_bits(addr));
2343 static int gfx_v10_0_wait_for_rlc_autoload_complete(struct amdgpu_device *adev)
2346 uint32_t bootload_status;
2349 for (i = 0; i < adev->usec_timeout; i++) {
2350 cp_status = RREG32_SOC15(GC, 0, mmCP_STAT);
2351 bootload_status = RREG32_SOC15(GC, 0, mmRLC_RLCS_BOOTLOAD_STATUS);
2352 if ((cp_status == 0) &&
2353 (REG_GET_FIELD(bootload_status,
2354 RLC_RLCS_BOOTLOAD_STATUS, BOOTLOAD_COMPLETE) == 1)) {
2360 if (i >= adev->usec_timeout) {
2361 dev_err(adev->dev, "rlc autoload: gc ucode autoload timeout\n");
2365 if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) {
2366 r = gfx_v10_0_rlc_backdoor_autoload_config_me_cache(adev);
2370 r = gfx_v10_0_rlc_backdoor_autoload_config_ce_cache(adev);
2374 r = gfx_v10_0_rlc_backdoor_autoload_config_pfp_cache(adev);
2378 r = gfx_v10_0_rlc_backdoor_autoload_config_mec_cache(adev);
2386 static int gfx_v10_0_cp_gfx_enable(struct amdgpu_device *adev, bool enable)
2389 u32 tmp = RREG32_SOC15(GC, 0, mmCP_ME_CNTL);
2391 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_HALT, enable ? 0 : 1);
2392 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_HALT, enable ? 0 : 1);
2393 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, CE_HALT, enable ? 0 : 1);
2395 for (i = 0; i < adev->gfx.num_gfx_rings; i++)
2396 adev->gfx.gfx_ring[i].sched.ready = false;
2398 WREG32_SOC15_RLC(GC, 0, mmCP_ME_CNTL, tmp);
2400 for (i = 0; i < adev->usec_timeout; i++) {
2401 if (RREG32_SOC15(GC, 0, mmCP_STAT) == 0)
2406 if (i >= adev->usec_timeout)
2407 DRM_ERROR("failed to %s cp gfx\n", enable ? "unhalt" : "halt");
2412 static int gfx_v10_0_cp_gfx_load_pfp_microcode(struct amdgpu_device *adev)
2415 const struct gfx_firmware_header_v1_0 *pfp_hdr;
2416 const __le32 *fw_data;
2417 unsigned i, fw_size;
2419 uint32_t usec_timeout = 50000; /* wait for 50ms */
2421 pfp_hdr = (const struct gfx_firmware_header_v1_0 *)
2422 adev->gfx.pfp_fw->data;
2424 amdgpu_ucode_print_gfx_hdr(&pfp_hdr->header);
2426 fw_data = (const __le32 *)(adev->gfx.pfp_fw->data +
2427 le32_to_cpu(pfp_hdr->header.ucode_array_offset_bytes));
2428 fw_size = le32_to_cpu(pfp_hdr->header.ucode_size_bytes);
2430 r = amdgpu_bo_create_reserved(adev, pfp_hdr->header.ucode_size_bytes,
2431 PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT,
2432 &adev->gfx.pfp.pfp_fw_obj,
2433 &adev->gfx.pfp.pfp_fw_gpu_addr,
2434 (void **)&adev->gfx.pfp.pfp_fw_ptr);
2436 dev_err(adev->dev, "(%d) failed to create pfp fw bo\n", r);
2437 gfx_v10_0_pfp_fini(adev);
2441 memcpy(adev->gfx.pfp.pfp_fw_ptr, fw_data, fw_size);
2443 amdgpu_bo_kunmap(adev->gfx.pfp.pfp_fw_obj);
2444 amdgpu_bo_unreserve(adev->gfx.pfp.pfp_fw_obj);
2446 /* Trigger an invalidation of the L1 instruction caches */
2447 tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL);
2448 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_OP_CNTL, INVALIDATE_CACHE, 1);
2449 WREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL, tmp);
2451 /* Wait for invalidation complete */
2452 for (i = 0; i < usec_timeout; i++) {
2453 tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL);
2454 if (1 == REG_GET_FIELD(tmp, CP_PFP_IC_OP_CNTL,
2455 INVALIDATE_CACHE_COMPLETE))
2460 if (i >= usec_timeout) {
2461 dev_err(adev->dev, "failed to invalidate instruction cache\n");
2465 if (amdgpu_emu_mode == 1)
2466 adev->nbio.funcs->hdp_flush(adev, NULL);
2468 tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_CNTL);
2469 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, VMID, 0);
2470 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, CACHE_POLICY, 0);
2471 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, EXE_DISABLE, 0);
2472 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, ADDRESS_CLAMP, 1);
2473 WREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_CNTL, tmp);
2474 WREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_LO,
2475 adev->gfx.pfp.pfp_fw_gpu_addr & 0xFFFFF000);
2476 WREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_HI,
2477 upper_32_bits(adev->gfx.pfp.pfp_fw_gpu_addr));
2482 static int gfx_v10_0_cp_gfx_load_ce_microcode(struct amdgpu_device *adev)
2485 const struct gfx_firmware_header_v1_0 *ce_hdr;
2486 const __le32 *fw_data;
2487 unsigned i, fw_size;
2489 uint32_t usec_timeout = 50000; /* wait for 50ms */
2491 ce_hdr = (const struct gfx_firmware_header_v1_0 *)
2492 adev->gfx.ce_fw->data;
2494 amdgpu_ucode_print_gfx_hdr(&ce_hdr->header);
2496 fw_data = (const __le32 *)(adev->gfx.ce_fw->data +
2497 le32_to_cpu(ce_hdr->header.ucode_array_offset_bytes));
2498 fw_size = le32_to_cpu(ce_hdr->header.ucode_size_bytes);
2500 r = amdgpu_bo_create_reserved(adev, ce_hdr->header.ucode_size_bytes,
2501 PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT,
2502 &adev->gfx.ce.ce_fw_obj,
2503 &adev->gfx.ce.ce_fw_gpu_addr,
2504 (void **)&adev->gfx.ce.ce_fw_ptr);
2506 dev_err(adev->dev, "(%d) failed to create ce fw bo\n", r);
2507 gfx_v10_0_ce_fini(adev);
2511 memcpy(adev->gfx.ce.ce_fw_ptr, fw_data, fw_size);
2513 amdgpu_bo_kunmap(adev->gfx.ce.ce_fw_obj);
2514 amdgpu_bo_unreserve(adev->gfx.ce.ce_fw_obj);
2516 /* Trigger an invalidation of the L1 instruction caches */
2517 tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL);
2518 tmp = REG_SET_FIELD(tmp, CP_CE_IC_OP_CNTL, INVALIDATE_CACHE, 1);
2519 WREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL, tmp);
2521 /* Wait for invalidation complete */
2522 for (i = 0; i < usec_timeout; i++) {
2523 tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL);
2524 if (1 == REG_GET_FIELD(tmp, CP_CE_IC_OP_CNTL,
2525 INVALIDATE_CACHE_COMPLETE))
2530 if (i >= usec_timeout) {
2531 dev_err(adev->dev, "failed to invalidate instruction cache\n");
2535 if (amdgpu_emu_mode == 1)
2536 adev->nbio.funcs->hdp_flush(adev, NULL);
2538 tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_BASE_CNTL);
2539 tmp = REG_SET_FIELD(tmp, CP_CE_IC_BASE_CNTL, VMID, 0);
2540 tmp = REG_SET_FIELD(tmp, CP_CE_IC_BASE_CNTL, CACHE_POLICY, 0);
2541 tmp = REG_SET_FIELD(tmp, CP_CE_IC_BASE_CNTL, EXE_DISABLE, 0);
2542 tmp = REG_SET_FIELD(tmp, CP_CE_IC_BASE_CNTL, ADDRESS_CLAMP, 1);
2543 WREG32_SOC15(GC, 0, mmCP_CE_IC_BASE_LO,
2544 adev->gfx.ce.ce_fw_gpu_addr & 0xFFFFF000);
2545 WREG32_SOC15(GC, 0, mmCP_CE_IC_BASE_HI,
2546 upper_32_bits(adev->gfx.ce.ce_fw_gpu_addr));
2551 static int gfx_v10_0_cp_gfx_load_me_microcode(struct amdgpu_device *adev)
2554 const struct gfx_firmware_header_v1_0 *me_hdr;
2555 const __le32 *fw_data;
2556 unsigned i, fw_size;
2558 uint32_t usec_timeout = 50000; /* wait for 50ms */
2560 me_hdr = (const struct gfx_firmware_header_v1_0 *)
2561 adev->gfx.me_fw->data;
2563 amdgpu_ucode_print_gfx_hdr(&me_hdr->header);
2565 fw_data = (const __le32 *)(adev->gfx.me_fw->data +
2566 le32_to_cpu(me_hdr->header.ucode_array_offset_bytes));
2567 fw_size = le32_to_cpu(me_hdr->header.ucode_size_bytes);
2569 r = amdgpu_bo_create_reserved(adev, me_hdr->header.ucode_size_bytes,
2570 PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT,
2571 &adev->gfx.me.me_fw_obj,
2572 &adev->gfx.me.me_fw_gpu_addr,
2573 (void **)&adev->gfx.me.me_fw_ptr);
2575 dev_err(adev->dev, "(%d) failed to create me fw bo\n", r);
2576 gfx_v10_0_me_fini(adev);
2580 memcpy(adev->gfx.me.me_fw_ptr, fw_data, fw_size);
2582 amdgpu_bo_kunmap(adev->gfx.me.me_fw_obj);
2583 amdgpu_bo_unreserve(adev->gfx.me.me_fw_obj);
2585 /* Trigger an invalidation of the L1 instruction caches */
2586 tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL);
2587 tmp = REG_SET_FIELD(tmp, CP_ME_IC_OP_CNTL, INVALIDATE_CACHE, 1);
2588 WREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL, tmp);
2590 /* Wait for invalidation complete */
2591 for (i = 0; i < usec_timeout; i++) {
2592 tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL);
2593 if (1 == REG_GET_FIELD(tmp, CP_ME_IC_OP_CNTL,
2594 INVALIDATE_CACHE_COMPLETE))
2599 if (i >= usec_timeout) {
2600 dev_err(adev->dev, "failed to invalidate instruction cache\n");
2604 if (amdgpu_emu_mode == 1)
2605 adev->nbio.funcs->hdp_flush(adev, NULL);
2607 tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_BASE_CNTL);
2608 tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, VMID, 0);
2609 tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, CACHE_POLICY, 0);
2610 tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, EXE_DISABLE, 0);
2611 tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, ADDRESS_CLAMP, 1);
2612 WREG32_SOC15(GC, 0, mmCP_ME_IC_BASE_LO,
2613 adev->gfx.me.me_fw_gpu_addr & 0xFFFFF000);
2614 WREG32_SOC15(GC, 0, mmCP_ME_IC_BASE_HI,
2615 upper_32_bits(adev->gfx.me.me_fw_gpu_addr));
2620 static int gfx_v10_0_cp_gfx_load_microcode(struct amdgpu_device *adev)
2624 if (!adev->gfx.me_fw || !adev->gfx.pfp_fw || !adev->gfx.ce_fw)
2627 gfx_v10_0_cp_gfx_enable(adev, false);
2629 r = gfx_v10_0_cp_gfx_load_pfp_microcode(adev);
2631 dev_err(adev->dev, "(%d) failed to load pfp fw\n", r);
2635 r = gfx_v10_0_cp_gfx_load_ce_microcode(adev);
2637 dev_err(adev->dev, "(%d) failed to load ce fw\n", r);
2641 r = gfx_v10_0_cp_gfx_load_me_microcode(adev);
2643 dev_err(adev->dev, "(%d) failed to load me fw\n", r);
2650 static int gfx_v10_0_cp_gfx_start(struct amdgpu_device *adev)
2652 struct amdgpu_ring *ring;
2653 const struct cs_section_def *sect = NULL;
2654 const struct cs_extent_def *ext = NULL;
2659 WREG32_SOC15(GC, 0, mmCP_MAX_CONTEXT,
2660 adev->gfx.config.max_hw_contexts - 1);
2661 WREG32_SOC15(GC, 0, mmCP_DEVICE_ID, 1);
2663 gfx_v10_0_cp_gfx_enable(adev, true);
2665 ring = &adev->gfx.gfx_ring[0];
2666 r = amdgpu_ring_alloc(ring, gfx_v10_0_get_csb_size(adev) + 4);
2668 DRM_ERROR("amdgpu: cp failed to lock ring (%d).\n", r);
2672 amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
2673 amdgpu_ring_write(ring, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE);
2675 amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1));
2676 amdgpu_ring_write(ring, 0x80000000);
2677 amdgpu_ring_write(ring, 0x80000000);
2679 for (sect = gfx10_cs_data; sect->section != NULL; ++sect) {
2680 for (ext = sect->section; ext->extent != NULL; ++ext) {
2681 if (sect->id == SECT_CONTEXT) {
2682 amdgpu_ring_write(ring,
2683 PACKET3(PACKET3_SET_CONTEXT_REG,
2685 amdgpu_ring_write(ring, ext->reg_index -
2686 PACKET3_SET_CONTEXT_REG_START);
2687 for (i = 0; i < ext->reg_count; i++)
2688 amdgpu_ring_write(ring, ext->extent[i]);
2694 SOC15_REG_OFFSET(GC, 0, mmPA_SC_TILE_STEERING_OVERRIDE) - PACKET3_SET_CONTEXT_REG_START;
2695 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 1));
2696 amdgpu_ring_write(ring, ctx_reg_offset);
2697 amdgpu_ring_write(ring, adev->gfx.config.pa_sc_tile_steering_override);
2699 amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
2700 amdgpu_ring_write(ring, PACKET3_PREAMBLE_END_CLEAR_STATE);
2702 amdgpu_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0));
2703 amdgpu_ring_write(ring, 0);
2705 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_BASE, 2));
2706 amdgpu_ring_write(ring, PACKET3_BASE_INDEX(CE_PARTITION_BASE));
2707 amdgpu_ring_write(ring, 0x8000);
2708 amdgpu_ring_write(ring, 0x8000);
2710 amdgpu_ring_commit(ring);
2712 /* submit cs packet to copy state 0 to next available state */
2713 if (adev->gfx.num_gfx_rings > 1) {
2714 /* maximum supported gfx ring is 2 */
2715 ring = &adev->gfx.gfx_ring[1];
2716 r = amdgpu_ring_alloc(ring, 2);
2718 DRM_ERROR("amdgpu: cp failed to lock ring (%d).\n", r);
2722 amdgpu_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0));
2723 amdgpu_ring_write(ring, 0);
2725 amdgpu_ring_commit(ring);
2730 static void gfx_v10_0_cp_gfx_switch_pipe(struct amdgpu_device *adev,
2735 tmp = RREG32_SOC15(GC, 0, mmGRBM_GFX_CNTL);
2736 tmp = REG_SET_FIELD(tmp, GRBM_GFX_CNTL, PIPEID, pipe);
2738 WREG32_SOC15(GC, 0, mmGRBM_GFX_CNTL, tmp);
2741 static void gfx_v10_0_cp_gfx_set_doorbell(struct amdgpu_device *adev,
2742 struct amdgpu_ring *ring)
2746 tmp = RREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL);
2747 if (ring->use_doorbell) {
2748 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
2749 DOORBELL_OFFSET, ring->doorbell_index);
2750 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
2753 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
2756 WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL, tmp);
2757 tmp = REG_SET_FIELD(0, CP_RB_DOORBELL_RANGE_LOWER,
2758 DOORBELL_RANGE_LOWER, ring->doorbell_index);
2759 WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_RANGE_LOWER, tmp);
2761 WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_RANGE_UPPER,
2762 CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_MASK);
2765 static int gfx_v10_0_cp_gfx_resume(struct amdgpu_device *adev)
2767 struct amdgpu_ring *ring;
2770 u64 rb_addr, rptr_addr, wptr_gpu_addr;
2773 /* Set the write pointer delay */
2774 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_DELAY, 0);
2776 /* set the RB to use vmid 0 */
2777 WREG32_SOC15(GC, 0, mmCP_RB_VMID, 0);
2779 /* Init gfx ring 0 for pipe 0 */
2780 mutex_lock(&adev->srbm_mutex);
2781 gfx_v10_0_cp_gfx_switch_pipe(adev, PIPE_ID0);
2783 /* Set ring buffer size */
2784 ring = &adev->gfx.gfx_ring[0];
2785 rb_bufsz = order_base_2(ring->ring_size / 8);
2786 tmp = REG_SET_FIELD(0, CP_RB0_CNTL, RB_BUFSZ, rb_bufsz);
2787 tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, RB_BLKSZ, rb_bufsz - 2);
2789 tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, BUF_SWAP, 1);
2791 WREG32_SOC15(GC, 0, mmCP_RB0_CNTL, tmp);
2793 /* Initialize the ring buffer's write pointers */
2795 WREG32_SOC15(GC, 0, mmCP_RB0_WPTR, lower_32_bits(ring->wptr));
2796 WREG32_SOC15(GC, 0, mmCP_RB0_WPTR_HI, upper_32_bits(ring->wptr));
2798 /* set the wb address wether it's enabled or not */
2799 rptr_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4);
2800 WREG32_SOC15(GC, 0, mmCP_RB0_RPTR_ADDR, lower_32_bits(rptr_addr));
2801 WREG32_SOC15(GC, 0, mmCP_RB0_RPTR_ADDR_HI, upper_32_bits(rptr_addr) &
2802 CP_RB_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK);
2804 wptr_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
2805 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_LO,
2806 lower_32_bits(wptr_gpu_addr));
2807 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_HI,
2808 upper_32_bits(wptr_gpu_addr));
2811 WREG32_SOC15(GC, 0, mmCP_RB0_CNTL, tmp);
2813 rb_addr = ring->gpu_addr >> 8;
2814 WREG32_SOC15(GC, 0, mmCP_RB0_BASE, rb_addr);
2815 WREG32_SOC15(GC, 0, mmCP_RB0_BASE_HI, upper_32_bits(rb_addr));
2817 WREG32_SOC15(GC, 0, mmCP_RB_ACTIVE, 1);
2819 gfx_v10_0_cp_gfx_set_doorbell(adev, ring);
2820 mutex_unlock(&adev->srbm_mutex);
2822 /* Init gfx ring 1 for pipe 1 */
2823 if (adev->gfx.num_gfx_rings > 1) {
2824 mutex_lock(&adev->srbm_mutex);
2825 gfx_v10_0_cp_gfx_switch_pipe(adev, PIPE_ID1);
2826 /* maximum supported gfx ring is 2 */
2827 ring = &adev->gfx.gfx_ring[1];
2828 rb_bufsz = order_base_2(ring->ring_size / 8);
2829 tmp = REG_SET_FIELD(0, CP_RB1_CNTL, RB_BUFSZ, rb_bufsz);
2830 tmp = REG_SET_FIELD(tmp, CP_RB1_CNTL, RB_BLKSZ, rb_bufsz - 2);
2831 WREG32_SOC15(GC, 0, mmCP_RB1_CNTL, tmp);
2832 /* Initialize the ring buffer's write pointers */
2834 WREG32_SOC15(GC, 0, mmCP_RB1_WPTR, lower_32_bits(ring->wptr));
2835 WREG32_SOC15(GC, 0, mmCP_RB1_WPTR_HI, upper_32_bits(ring->wptr));
2836 /* Set the wb address wether it's enabled or not */
2837 rptr_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4);
2838 WREG32_SOC15(GC, 0, mmCP_RB1_RPTR_ADDR, lower_32_bits(rptr_addr));
2839 WREG32_SOC15(GC, 0, mmCP_RB1_RPTR_ADDR_HI, upper_32_bits(rptr_addr) &
2840 CP_RB1_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK);
2841 wptr_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
2842 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_LO,
2843 lower_32_bits(wptr_gpu_addr));
2844 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_HI,
2845 upper_32_bits(wptr_gpu_addr));
2848 WREG32_SOC15(GC, 0, mmCP_RB1_CNTL, tmp);
2850 rb_addr = ring->gpu_addr >> 8;
2851 WREG32_SOC15(GC, 0, mmCP_RB1_BASE, rb_addr);
2852 WREG32_SOC15(GC, 0, mmCP_RB1_BASE_HI, upper_32_bits(rb_addr));
2853 WREG32_SOC15(GC, 0, mmCP_RB1_ACTIVE, 1);
2855 gfx_v10_0_cp_gfx_set_doorbell(adev, ring);
2856 mutex_unlock(&adev->srbm_mutex);
2858 /* Switch to pipe 0 */
2859 mutex_lock(&adev->srbm_mutex);
2860 gfx_v10_0_cp_gfx_switch_pipe(adev, PIPE_ID0);
2861 mutex_unlock(&adev->srbm_mutex);
2863 /* start the ring */
2864 gfx_v10_0_cp_gfx_start(adev);
2866 for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
2867 ring = &adev->gfx.gfx_ring[i];
2868 ring->sched.ready = true;
2874 static void gfx_v10_0_cp_compute_enable(struct amdgpu_device *adev, bool enable)
2879 WREG32_SOC15(GC, 0, mmCP_MEC_CNTL, 0);
2881 WREG32_SOC15(GC, 0, mmCP_MEC_CNTL,
2882 (CP_MEC_CNTL__MEC_ME1_HALT_MASK |
2883 CP_MEC_CNTL__MEC_ME2_HALT_MASK));
2884 for (i = 0; i < adev->gfx.num_compute_rings; i++)
2885 adev->gfx.compute_ring[i].sched.ready = false;
2886 adev->gfx.kiq.ring.sched.ready = false;
2891 static int gfx_v10_0_cp_compute_load_microcode(struct amdgpu_device *adev)
2893 const struct gfx_firmware_header_v1_0 *mec_hdr;
2894 const __le32 *fw_data;
2897 u32 usec_timeout = 50000; /* Wait for 50 ms */
2899 if (!adev->gfx.mec_fw)
2902 gfx_v10_0_cp_compute_enable(adev, false);
2904 mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data;
2905 amdgpu_ucode_print_gfx_hdr(&mec_hdr->header);
2907 fw_data = (const __le32 *)
2908 (adev->gfx.mec_fw->data +
2909 le32_to_cpu(mec_hdr->header.ucode_array_offset_bytes));
2911 /* Trigger an invalidation of the L1 instruction caches */
2912 tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL);
2913 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_OP_CNTL, INVALIDATE_CACHE, 1);
2914 WREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL, tmp);
2916 /* Wait for invalidation complete */
2917 for (i = 0; i < usec_timeout; i++) {
2918 tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL);
2919 if (1 == REG_GET_FIELD(tmp, CP_CPC_IC_OP_CNTL,
2920 INVALIDATE_CACHE_COMPLETE))
2925 if (i >= usec_timeout) {
2926 dev_err(adev->dev, "failed to invalidate instruction cache\n");
2930 if (amdgpu_emu_mode == 1)
2931 adev->nbio.funcs->hdp_flush(adev, NULL);
2933 tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_CNTL);
2934 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, CACHE_POLICY, 0);
2935 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, EXE_DISABLE, 0);
2936 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, ADDRESS_CLAMP, 1);
2937 WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_CNTL, tmp);
2939 WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_LO, adev->gfx.mec.mec_fw_gpu_addr &
2941 WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_HI,
2942 upper_32_bits(adev->gfx.mec.mec_fw_gpu_addr));
2945 WREG32_SOC15(GC, 0, mmCP_MEC_ME1_UCODE_ADDR, 0);
2947 for (i = 0; i < mec_hdr->jt_size; i++)
2948 WREG32_SOC15(GC, 0, mmCP_MEC_ME1_UCODE_DATA,
2949 le32_to_cpup(fw_data + mec_hdr->jt_offset + i));
2951 WREG32_SOC15(GC, 0, mmCP_MEC_ME1_UCODE_ADDR, adev->gfx.mec_fw_version);
2954 * TODO: Loading MEC2 firmware is only necessary if MEC2 should run
2955 * different microcode than MEC1.
2961 static void gfx_v10_0_kiq_setting(struct amdgpu_ring *ring)
2964 struct amdgpu_device *adev = ring->adev;
2966 /* tell RLC which is KIQ queue */
2967 tmp = RREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS);
2969 tmp |= (ring->me << 5) | (ring->pipe << 3) | (ring->queue);
2970 WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS, tmp);
2972 WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS, tmp);
2975 static int gfx_v10_0_gfx_mqd_init(struct amdgpu_ring *ring)
2977 struct amdgpu_device *adev = ring->adev;
2978 struct v10_gfx_mqd *mqd = ring->mqd_ptr;
2979 uint64_t hqd_gpu_addr, wb_gpu_addr;
2983 /* set up gfx hqd wptr */
2984 mqd->cp_gfx_hqd_wptr = 0;
2985 mqd->cp_gfx_hqd_wptr_hi = 0;
2987 /* set the pointer to the MQD */
2988 mqd->cp_mqd_base_addr = ring->mqd_gpu_addr & 0xfffffffc;
2989 mqd->cp_mqd_base_addr_hi = upper_32_bits(ring->mqd_gpu_addr);
2991 /* set up mqd control */
2992 tmp = RREG32_SOC15(GC, 0, mmCP_GFX_MQD_CONTROL);
2993 tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, VMID, 0);
2994 tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, PRIV_STATE, 1);
2995 tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, CACHE_POLICY, 0);
2996 mqd->cp_gfx_mqd_control = tmp;
2998 /* set up gfx_hqd_vimd with 0x0 to indicate the ring buffer's vmid */
2999 tmp = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_VMID);
3000 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_VMID, VMID, 0);
3001 mqd->cp_gfx_hqd_vmid = 0;
3003 /* set up default queue priority level
3004 * 0x0 = low priority, 0x1 = high priority */
3005 tmp = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_QUEUE_PRIORITY);
3006 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_QUEUE_PRIORITY, PRIORITY_LEVEL, 0);
3007 mqd->cp_gfx_hqd_queue_priority = tmp;
3009 /* set up time quantum */
3010 tmp = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_QUANTUM);
3011 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_QUANTUM, QUANTUM_EN, 1);
3012 mqd->cp_gfx_hqd_quantum = tmp;
3014 /* set up gfx hqd base. this is similar as CP_RB_BASE */
3015 hqd_gpu_addr = ring->gpu_addr >> 8;
3016 mqd->cp_gfx_hqd_base = hqd_gpu_addr;
3017 mqd->cp_gfx_hqd_base_hi = upper_32_bits(hqd_gpu_addr);
3019 /* set up hqd_rptr_addr/_hi, similar as CP_RB_RPTR */
3020 wb_gpu_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4);
3021 mqd->cp_gfx_hqd_rptr_addr = wb_gpu_addr & 0xfffffffc;
3022 mqd->cp_gfx_hqd_rptr_addr_hi =
3023 upper_32_bits(wb_gpu_addr) & 0xffff;
3025 /* set up rb_wptr_poll addr */
3026 wb_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
3027 mqd->cp_rb_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffffc;
3028 mqd->cp_rb_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff;
3030 /* set up the gfx_hqd_control, similar as CP_RB0_CNTL */
3031 rb_bufsz = order_base_2(ring->ring_size / 4) - 1;
3032 tmp = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_CNTL);
3033 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, RB_BUFSZ, rb_bufsz);
3034 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, RB_BLKSZ, rb_bufsz - 2);
3036 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, BUF_SWAP, 1);
3038 mqd->cp_gfx_hqd_cntl = tmp;
3040 /* set up cp_doorbell_control */
3041 tmp = RREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL);
3042 if (ring->use_doorbell) {
3043 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
3044 DOORBELL_OFFSET, ring->doorbell_index);
3045 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
3048 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
3050 mqd->cp_rb_doorbell_control = tmp;
3052 /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */
3054 mqd->cp_gfx_hqd_rptr = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_RPTR);
3056 /* active the queue */
3057 mqd->cp_gfx_hqd_active = 1;
3062 #ifdef BRING_UP_DEBUG
3063 static int gfx_v10_0_gfx_queue_init_register(struct amdgpu_ring *ring)
3065 struct amdgpu_device *adev = ring->adev;
3066 struct v10_gfx_mqd *mqd = ring->mqd_ptr;
3068 /* set mmCP_GFX_HQD_WPTR/_HI to 0 */
3069 WREG32_SOC15(GC, 0, mmCP_GFX_HQD_WPTR, mqd->cp_gfx_hqd_wptr);
3070 WREG32_SOC15(GC, 0, mmCP_GFX_HQD_WPTR_HI, mqd->cp_gfx_hqd_wptr_hi);
3072 /* set GFX_MQD_BASE */
3073 WREG32_SOC15(GC, 0, mmCP_MQD_BASE_ADDR, mqd->cp_mqd_base_addr);
3074 WREG32_SOC15(GC, 0, mmCP_MQD_BASE_ADDR_HI, mqd->cp_mqd_base_addr_hi);
3076 /* set GFX_MQD_CONTROL */
3077 WREG32_SOC15(GC, 0, mmCP_GFX_MQD_CONTROL, mqd->cp_gfx_mqd_control);
3079 /* set GFX_HQD_VMID to 0 */
3080 WREG32_SOC15(GC, 0, mmCP_GFX_HQD_VMID, mqd->cp_gfx_hqd_vmid);
3082 WREG32_SOC15(GC, 0, mmCP_GFX_HQD_QUEUE_PRIORITY,
3083 mqd->cp_gfx_hqd_queue_priority);
3084 WREG32_SOC15(GC, 0, mmCP_GFX_HQD_QUANTUM, mqd->cp_gfx_hqd_quantum);
3086 /* set GFX_HQD_BASE, similar as CP_RB_BASE */
3087 WREG32_SOC15(GC, 0, mmCP_GFX_HQD_BASE, mqd->cp_gfx_hqd_base);
3088 WREG32_SOC15(GC, 0, mmCP_GFX_HQD_BASE_HI, mqd->cp_gfx_hqd_base_hi);
3090 /* set GFX_HQD_RPTR_ADDR, similar as CP_RB_RPTR */
3091 WREG32_SOC15(GC, 0, mmCP_GFX_HQD_RPTR_ADDR, mqd->cp_gfx_hqd_rptr_addr);
3092 WREG32_SOC15(GC, 0, mmCP_GFX_HQD_RPTR_ADDR_HI, mqd->cp_gfx_hqd_rptr_addr_hi);
3094 /* set GFX_HQD_CNTL, similar as CP_RB_CNTL */
3095 WREG32_SOC15(GC, 0, mmCP_GFX_HQD_CNTL, mqd->cp_gfx_hqd_cntl);
3097 /* set RB_WPTR_POLL_ADDR */
3098 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_LO, mqd->cp_rb_wptr_poll_addr_lo);
3099 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_HI, mqd->cp_rb_wptr_poll_addr_hi);
3101 /* set RB_DOORBELL_CONTROL */
3102 WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL, mqd->cp_rb_doorbell_control);
3104 /* active the queue */
3105 WREG32_SOC15(GC, 0, mmCP_GFX_HQD_ACTIVE, mqd->cp_gfx_hqd_active);
3111 static int gfx_v10_0_gfx_init_queue(struct amdgpu_ring *ring)
3113 struct amdgpu_device *adev = ring->adev;
3114 struct v10_gfx_mqd *mqd = ring->mqd_ptr;
3115 int mqd_idx = ring - &adev->gfx.gfx_ring[0];
3117 if (!adev->in_gpu_reset && !adev->in_suspend) {
3118 memset((void *)mqd, 0, sizeof(*mqd));
3119 mutex_lock(&adev->srbm_mutex);
3120 nv_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
3121 gfx_v10_0_gfx_mqd_init(ring);
3122 #ifdef BRING_UP_DEBUG
3123 gfx_v10_0_gfx_queue_init_register(ring);
3125 nv_grbm_select(adev, 0, 0, 0, 0);
3126 mutex_unlock(&adev->srbm_mutex);
3127 if (adev->gfx.me.mqd_backup[mqd_idx])
3128 memcpy(adev->gfx.me.mqd_backup[mqd_idx], mqd, sizeof(*mqd));
3129 } else if (adev->in_gpu_reset) {
3130 /* reset mqd with the backup copy */
3131 if (adev->gfx.me.mqd_backup[mqd_idx])
3132 memcpy(mqd, adev->gfx.me.mqd_backup[mqd_idx], sizeof(*mqd));
3133 /* reset the ring */
3135 adev->wb.wb[ring->wptr_offs] = 0;
3136 amdgpu_ring_clear_ring(ring);
3137 #ifdef BRING_UP_DEBUG
3138 mutex_lock(&adev->srbm_mutex);
3139 nv_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
3140 gfx_v10_0_gfx_queue_init_register(ring);
3141 nv_grbm_select(adev, 0, 0, 0, 0);
3142 mutex_unlock(&adev->srbm_mutex);
3145 amdgpu_ring_clear_ring(ring);
3151 #ifndef BRING_UP_DEBUG
3152 static int gfx_v10_0_kiq_enable_kgq(struct amdgpu_device *adev)
3154 struct amdgpu_kiq *kiq = &adev->gfx.kiq;
3155 struct amdgpu_ring *kiq_ring = &adev->gfx.kiq.ring;
3158 if (!kiq->pmf || !kiq->pmf->kiq_map_queues)
3161 r = amdgpu_ring_alloc(kiq_ring, kiq->pmf->map_queues_size *
3162 adev->gfx.num_gfx_rings);
3164 DRM_ERROR("Failed to lock KIQ (%d).\n", r);
3168 for (i = 0; i < adev->gfx.num_gfx_rings; i++)
3169 kiq->pmf->kiq_map_queues(kiq_ring, &adev->gfx.gfx_ring[i]);
3171 return amdgpu_ring_test_helper(kiq_ring);
3175 static int gfx_v10_0_cp_async_gfx_ring_resume(struct amdgpu_device *adev)
3178 struct amdgpu_ring *ring;
3180 for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
3181 ring = &adev->gfx.gfx_ring[i];
3183 r = amdgpu_bo_reserve(ring->mqd_obj, false);
3184 if (unlikely(r != 0))
3187 r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr);
3189 r = gfx_v10_0_gfx_init_queue(ring);
3190 amdgpu_bo_kunmap(ring->mqd_obj);
3191 ring->mqd_ptr = NULL;
3193 amdgpu_bo_unreserve(ring->mqd_obj);
3197 #ifndef BRING_UP_DEBUG
3198 r = gfx_v10_0_kiq_enable_kgq(adev);
3202 r = gfx_v10_0_cp_gfx_start(adev);
3206 for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
3207 ring = &adev->gfx.gfx_ring[i];
3208 ring->sched.ready = true;
3214 static int gfx_v10_0_compute_mqd_init(struct amdgpu_ring *ring)
3216 struct amdgpu_device *adev = ring->adev;
3217 struct v10_compute_mqd *mqd = ring->mqd_ptr;
3218 uint64_t hqd_gpu_addr, wb_gpu_addr, eop_base_addr;
3221 mqd->header = 0xC0310800;
3222 mqd->compute_pipelinestat_enable = 0x00000001;
3223 mqd->compute_static_thread_mgmt_se0 = 0xffffffff;
3224 mqd->compute_static_thread_mgmt_se1 = 0xffffffff;
3225 mqd->compute_static_thread_mgmt_se2 = 0xffffffff;
3226 mqd->compute_static_thread_mgmt_se3 = 0xffffffff;
3227 mqd->compute_misc_reserved = 0x00000003;
3229 eop_base_addr = ring->eop_gpu_addr >> 8;
3230 mqd->cp_hqd_eop_base_addr_lo = eop_base_addr;
3231 mqd->cp_hqd_eop_base_addr_hi = upper_32_bits(eop_base_addr);
3233 /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */
3234 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_EOP_CONTROL);
3235 tmp = REG_SET_FIELD(tmp, CP_HQD_EOP_CONTROL, EOP_SIZE,
3236 (order_base_2(GFX10_MEC_HPD_SIZE / 4) - 1));
3238 mqd->cp_hqd_eop_control = tmp;
3240 /* enable doorbell? */
3241 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL);
3243 if (ring->use_doorbell) {
3244 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
3245 DOORBELL_OFFSET, ring->doorbell_index);
3246 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
3248 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
3249 DOORBELL_SOURCE, 0);
3250 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
3253 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
3257 mqd->cp_hqd_pq_doorbell_control = tmp;
3259 /* disable the queue if it's active */
3261 mqd->cp_hqd_dequeue_request = 0;
3262 mqd->cp_hqd_pq_rptr = 0;
3263 mqd->cp_hqd_pq_wptr_lo = 0;
3264 mqd->cp_hqd_pq_wptr_hi = 0;
3266 /* set the pointer to the MQD */
3267 mqd->cp_mqd_base_addr_lo = ring->mqd_gpu_addr & 0xfffffffc;
3268 mqd->cp_mqd_base_addr_hi = upper_32_bits(ring->mqd_gpu_addr);
3270 /* set MQD vmid to 0 */
3271 tmp = RREG32_SOC15(GC, 0, mmCP_MQD_CONTROL);
3272 tmp = REG_SET_FIELD(tmp, CP_MQD_CONTROL, VMID, 0);
3273 mqd->cp_mqd_control = tmp;
3275 /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */
3276 hqd_gpu_addr = ring->gpu_addr >> 8;
3277 mqd->cp_hqd_pq_base_lo = hqd_gpu_addr;
3278 mqd->cp_hqd_pq_base_hi = upper_32_bits(hqd_gpu_addr);
3280 /* set up the HQD, this is similar to CP_RB0_CNTL */
3281 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_CONTROL);
3282 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, QUEUE_SIZE,
3283 (order_base_2(ring->ring_size / 4) - 1));
3284 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, RPTR_BLOCK_SIZE,
3285 ((order_base_2(AMDGPU_GPU_PAGE_SIZE / 4) - 1) << 8));
3287 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, ENDIAN_SWAP, 1);
3289 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 0);
3290 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, TUNNEL_DISPATCH, 0);
3291 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1);
3292 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, KMD_QUEUE, 1);
3293 mqd->cp_hqd_pq_control = tmp;
3295 /* set the wb address whether it's enabled or not */
3296 wb_gpu_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4);
3297 mqd->cp_hqd_pq_rptr_report_addr_lo = wb_gpu_addr & 0xfffffffc;
3298 mqd->cp_hqd_pq_rptr_report_addr_hi =
3299 upper_32_bits(wb_gpu_addr) & 0xffff;
3301 /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */
3302 wb_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
3303 mqd->cp_hqd_pq_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffffc;
3304 mqd->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff;
3307 /* enable the doorbell if requested */
3308 if (ring->use_doorbell) {
3309 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL);
3310 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
3311 DOORBELL_OFFSET, ring->doorbell_index);
3313 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
3315 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
3316 DOORBELL_SOURCE, 0);
3317 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
3321 mqd->cp_hqd_pq_doorbell_control = tmp;
3323 /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */
3325 mqd->cp_hqd_pq_rptr = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR);
3327 /* set the vmid for the queue */
3328 mqd->cp_hqd_vmid = 0;
3330 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PERSISTENT_STATE);
3331 tmp = REG_SET_FIELD(tmp, CP_HQD_PERSISTENT_STATE, PRELOAD_SIZE, 0x53);
3332 mqd->cp_hqd_persistent_state = tmp;
3334 /* set MIN_IB_AVAIL_SIZE */
3335 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_IB_CONTROL);
3336 tmp = REG_SET_FIELD(tmp, CP_HQD_IB_CONTROL, MIN_IB_AVAIL_SIZE, 3);
3337 mqd->cp_hqd_ib_control = tmp;
3339 /* map_queues packet doesn't need activate the queue,
3340 * so only kiq need set this field.
3342 if (ring->funcs->type == AMDGPU_RING_TYPE_KIQ)
3343 mqd->cp_hqd_active = 1;
3348 static int gfx_v10_0_kiq_init_register(struct amdgpu_ring *ring)
3350 struct amdgpu_device *adev = ring->adev;
3351 struct v10_compute_mqd *mqd = ring->mqd_ptr;
3354 /* disable wptr polling */
3355 WREG32_FIELD15(GC, 0, CP_PQ_WPTR_POLL_CNTL, EN, 0);
3357 /* write the EOP addr */
3358 WREG32_SOC15(GC, 0, mmCP_HQD_EOP_BASE_ADDR,
3359 mqd->cp_hqd_eop_base_addr_lo);
3360 WREG32_SOC15(GC, 0, mmCP_HQD_EOP_BASE_ADDR_HI,
3361 mqd->cp_hqd_eop_base_addr_hi);
3363 /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */
3364 WREG32_SOC15(GC, 0, mmCP_HQD_EOP_CONTROL,
3365 mqd->cp_hqd_eop_control);
3367 /* enable doorbell? */
3368 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL,
3369 mqd->cp_hqd_pq_doorbell_control);
3371 /* disable the queue if it's active */
3372 if (RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE) & 1) {
3373 WREG32_SOC15(GC, 0, mmCP_HQD_DEQUEUE_REQUEST, 1);
3374 for (j = 0; j < adev->usec_timeout; j++) {
3375 if (!(RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE) & 1))
3379 WREG32_SOC15(GC, 0, mmCP_HQD_DEQUEUE_REQUEST,
3380 mqd->cp_hqd_dequeue_request);
3381 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR,
3382 mqd->cp_hqd_pq_rptr);
3383 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_LO,
3384 mqd->cp_hqd_pq_wptr_lo);
3385 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_HI,
3386 mqd->cp_hqd_pq_wptr_hi);
3389 /* set the pointer to the MQD */
3390 WREG32_SOC15(GC, 0, mmCP_MQD_BASE_ADDR,
3391 mqd->cp_mqd_base_addr_lo);
3392 WREG32_SOC15(GC, 0, mmCP_MQD_BASE_ADDR_HI,
3393 mqd->cp_mqd_base_addr_hi);
3395 /* set MQD vmid to 0 */
3396 WREG32_SOC15(GC, 0, mmCP_MQD_CONTROL,
3397 mqd->cp_mqd_control);
3399 /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */
3400 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_BASE,
3401 mqd->cp_hqd_pq_base_lo);
3402 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_BASE_HI,
3403 mqd->cp_hqd_pq_base_hi);
3405 /* set up the HQD, this is similar to CP_RB0_CNTL */
3406 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_CONTROL,
3407 mqd->cp_hqd_pq_control);
3409 /* set the wb address whether it's enabled or not */
3410 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR_REPORT_ADDR,
3411 mqd->cp_hqd_pq_rptr_report_addr_lo);
3412 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR_REPORT_ADDR_HI,
3413 mqd->cp_hqd_pq_rptr_report_addr_hi);
3415 /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */
3416 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR,
3417 mqd->cp_hqd_pq_wptr_poll_addr_lo);
3418 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR_HI,
3419 mqd->cp_hqd_pq_wptr_poll_addr_hi);
3421 /* enable the doorbell if requested */
3422 if (ring->use_doorbell) {
3423 WREG32_SOC15(GC, 0, mmCP_MEC_DOORBELL_RANGE_LOWER,
3424 (adev->doorbell_index.kiq * 2) << 2);
3425 WREG32_SOC15(GC, 0, mmCP_MEC_DOORBELL_RANGE_UPPER,
3426 (adev->doorbell_index.userqueue_end * 2) << 2);
3429 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL,
3430 mqd->cp_hqd_pq_doorbell_control);
3432 /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */
3433 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_LO,
3434 mqd->cp_hqd_pq_wptr_lo);
3435 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_HI,
3436 mqd->cp_hqd_pq_wptr_hi);
3438 /* set the vmid for the queue */
3439 WREG32_SOC15(GC, 0, mmCP_HQD_VMID, mqd->cp_hqd_vmid);
3441 WREG32_SOC15(GC, 0, mmCP_HQD_PERSISTENT_STATE,
3442 mqd->cp_hqd_persistent_state);
3444 /* activate the queue */
3445 WREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE,
3446 mqd->cp_hqd_active);
3448 if (ring->use_doorbell)
3449 WREG32_FIELD15(GC, 0, CP_PQ_STATUS, DOORBELL_ENABLE, 1);
3454 static int gfx_v10_0_kiq_init_queue(struct amdgpu_ring *ring)
3456 struct amdgpu_device *adev = ring->adev;
3457 struct v10_compute_mqd *mqd = ring->mqd_ptr;
3458 int mqd_idx = AMDGPU_MAX_COMPUTE_RINGS;
3460 gfx_v10_0_kiq_setting(ring);
3462 if (adev->in_gpu_reset) { /* for GPU_RESET case */
3463 /* reset MQD to a clean status */
3464 if (adev->gfx.mec.mqd_backup[mqd_idx])
3465 memcpy(mqd, adev->gfx.mec.mqd_backup[mqd_idx], sizeof(*mqd));
3467 /* reset ring buffer */
3469 amdgpu_ring_clear_ring(ring);
3471 mutex_lock(&adev->srbm_mutex);
3472 nv_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
3473 gfx_v10_0_kiq_init_register(ring);
3474 nv_grbm_select(adev, 0, 0, 0, 0);
3475 mutex_unlock(&adev->srbm_mutex);
3477 memset((void *)mqd, 0, sizeof(*mqd));
3478 mutex_lock(&adev->srbm_mutex);
3479 nv_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
3480 gfx_v10_0_compute_mqd_init(ring);
3481 gfx_v10_0_kiq_init_register(ring);
3482 nv_grbm_select(adev, 0, 0, 0, 0);
3483 mutex_unlock(&adev->srbm_mutex);
3485 if (adev->gfx.mec.mqd_backup[mqd_idx])
3486 memcpy(adev->gfx.mec.mqd_backup[mqd_idx], mqd, sizeof(*mqd));
3492 static int gfx_v10_0_kcq_init_queue(struct amdgpu_ring *ring)
3494 struct amdgpu_device *adev = ring->adev;
3495 struct v10_compute_mqd *mqd = ring->mqd_ptr;
3496 int mqd_idx = ring - &adev->gfx.compute_ring[0];
3498 if (!adev->in_gpu_reset && !adev->in_suspend) {
3499 memset((void *)mqd, 0, sizeof(*mqd));
3500 mutex_lock(&adev->srbm_mutex);
3501 nv_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
3502 gfx_v10_0_compute_mqd_init(ring);
3503 nv_grbm_select(adev, 0, 0, 0, 0);
3504 mutex_unlock(&adev->srbm_mutex);
3506 if (adev->gfx.mec.mqd_backup[mqd_idx])
3507 memcpy(adev->gfx.mec.mqd_backup[mqd_idx], mqd, sizeof(*mqd));
3508 } else if (adev->in_gpu_reset) { /* for GPU_RESET case */
3509 /* reset MQD to a clean status */
3510 if (adev->gfx.mec.mqd_backup[mqd_idx])
3511 memcpy(mqd, adev->gfx.mec.mqd_backup[mqd_idx], sizeof(*mqd));
3513 /* reset ring buffer */
3515 atomic64_set((atomic64_t *)&adev->wb.wb[ring->wptr_offs], 0);
3516 amdgpu_ring_clear_ring(ring);
3518 amdgpu_ring_clear_ring(ring);
3524 static int gfx_v10_0_kiq_resume(struct amdgpu_device *adev)
3526 struct amdgpu_ring *ring;
3529 ring = &adev->gfx.kiq.ring;
3531 r = amdgpu_bo_reserve(ring->mqd_obj, false);
3532 if (unlikely(r != 0))
3535 r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr);
3536 if (unlikely(r != 0))
3539 gfx_v10_0_kiq_init_queue(ring);
3540 amdgpu_bo_kunmap(ring->mqd_obj);
3541 ring->mqd_ptr = NULL;
3542 amdgpu_bo_unreserve(ring->mqd_obj);
3543 ring->sched.ready = true;
3547 static int gfx_v10_0_kcq_resume(struct amdgpu_device *adev)
3549 struct amdgpu_ring *ring = NULL;
3552 gfx_v10_0_cp_compute_enable(adev, true);
3554 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
3555 ring = &adev->gfx.compute_ring[i];
3557 r = amdgpu_bo_reserve(ring->mqd_obj, false);
3558 if (unlikely(r != 0))
3560 r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr);
3562 r = gfx_v10_0_kcq_init_queue(ring);
3563 amdgpu_bo_kunmap(ring->mqd_obj);
3564 ring->mqd_ptr = NULL;
3566 amdgpu_bo_unreserve(ring->mqd_obj);
3571 r = amdgpu_gfx_enable_kcq(adev);
3576 static int gfx_v10_0_cp_resume(struct amdgpu_device *adev)
3579 struct amdgpu_ring *ring;
3581 if (!(adev->flags & AMD_IS_APU))
3582 gfx_v10_0_enable_gui_idle_interrupt(adev, false);
3584 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) {
3585 /* legacy firmware loading */
3586 r = gfx_v10_0_cp_gfx_load_microcode(adev);
3590 r = gfx_v10_0_cp_compute_load_microcode(adev);
3595 r = gfx_v10_0_kiq_resume(adev);
3599 r = gfx_v10_0_kcq_resume(adev);
3603 if (!amdgpu_async_gfx_ring) {
3604 r = gfx_v10_0_cp_gfx_resume(adev);
3608 r = gfx_v10_0_cp_async_gfx_ring_resume(adev);
3613 for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
3614 ring = &adev->gfx.gfx_ring[i];
3615 r = amdgpu_ring_test_helper(ring);
3620 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
3621 ring = &adev->gfx.compute_ring[i];
3622 r = amdgpu_ring_test_helper(ring);
3630 static void gfx_v10_0_cp_enable(struct amdgpu_device *adev, bool enable)
3632 gfx_v10_0_cp_gfx_enable(adev, enable);
3633 gfx_v10_0_cp_compute_enable(adev, enable);
3636 static bool gfx_v10_0_check_grbm_cam_remapping(struct amdgpu_device *adev)
3638 uint32_t data, pattern = 0xDEADBEEF;
3640 /* check if mmVGT_ESGS_RING_SIZE_UMD
3641 * has been remapped to mmVGT_ESGS_RING_SIZE */
3642 data = RREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE);
3644 WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE, 0);
3646 WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_UMD, pattern);
3648 if (RREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE) == pattern) {
3649 WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_UMD, data);
3652 WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE, data);
3657 static void gfx_v10_0_setup_grbm_cam_remapping(struct amdgpu_device *adev)
3661 /* initialize cam_index to 0
3662 * index will auto-inc after each data writting */
3663 WREG32_SOC15(GC, 0, mmGRBM_CAM_INDEX, 0);
3665 /* mmVGT_TF_RING_SIZE_UMD -> mmVGT_TF_RING_SIZE */
3666 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_RING_SIZE_UMD) <<
3667 GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
3668 (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_RING_SIZE) <<
3669 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
3670 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
3671 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
3673 /* mmVGT_TF_MEMORY_BASE_UMD -> mmVGT_TF_MEMORY_BASE */
3674 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_UMD) <<
3675 GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
3676 (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE) <<
3677 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
3678 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
3679 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
3681 /* mmVGT_TF_MEMORY_BASE_HI_UMD -> mmVGT_TF_MEMORY_BASE_HI */
3682 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_HI_UMD) <<
3683 GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
3684 (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_HI) <<
3685 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
3686 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
3687 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
3689 /* mmVGT_HS_OFFCHIP_PARAM_UMD -> mmVGT_HS_OFFCHIP_PARAM */
3690 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_HS_OFFCHIP_PARAM_UMD) <<
3691 GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
3692 (SOC15_REG_OFFSET(GC, 0, mmVGT_HS_OFFCHIP_PARAM) <<
3693 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
3694 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
3695 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
3697 /* mmVGT_ESGS_RING_SIZE_UMD -> mmVGT_ESGS_RING_SIZE */
3698 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_ESGS_RING_SIZE_UMD) <<
3699 GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
3700 (SOC15_REG_OFFSET(GC, 0, mmVGT_ESGS_RING_SIZE) <<
3701 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
3702 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
3703 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
3705 /* mmVGT_GSVS_RING_SIZE_UMD -> mmVGT_GSVS_RING_SIZE */
3706 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_GSVS_RING_SIZE_UMD) <<
3707 GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
3708 (SOC15_REG_OFFSET(GC, 0, mmVGT_GSVS_RING_SIZE) <<
3709 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
3710 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
3711 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
3713 /* mmSPI_CONFIG_CNTL_REMAP -> mmSPI_CONFIG_CNTL */
3714 data = (SOC15_REG_OFFSET(GC, 0, mmSPI_CONFIG_CNTL_REMAP) <<
3715 GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
3716 (SOC15_REG_OFFSET(GC, 0, mmSPI_CONFIG_CNTL) <<
3717 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
3718 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
3719 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
3722 static int gfx_v10_0_hw_init(void *handle)
3725 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3727 if (!amdgpu_emu_mode)
3728 gfx_v10_0_init_golden_registers(adev);
3730 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) {
3732 * For gfx 10, rlc firmware loading relies on smu firmware is
3733 * loaded firstly, so in direct type, it has to load smc ucode
3736 r = smu_load_microcode(&adev->smu);
3740 r = smu_check_fw_status(&adev->smu);
3742 pr_err("SMC firmware status is not correct\n");
3747 /* if GRBM CAM not remapped, set up the remapping */
3748 if (!gfx_v10_0_check_grbm_cam_remapping(adev))
3749 gfx_v10_0_setup_grbm_cam_remapping(adev);
3751 gfx_v10_0_constants_init(adev);
3753 r = gfx_v10_0_rlc_resume(adev);
3758 * init golden registers and rlc resume may override some registers,
3759 * reconfig them here
3761 gfx_v10_0_tcp_harvest(adev);
3763 r = gfx_v10_0_cp_resume(adev);
3770 #ifndef BRING_UP_DEBUG
3771 static int gfx_v10_0_kiq_disable_kgq(struct amdgpu_device *adev)
3773 struct amdgpu_kiq *kiq = &adev->gfx.kiq;
3774 struct amdgpu_ring *kiq_ring = &kiq->ring;
3777 if (!kiq->pmf || !kiq->pmf->kiq_unmap_queues)
3780 if (amdgpu_ring_alloc(kiq_ring, kiq->pmf->unmap_queues_size *
3781 adev->gfx.num_gfx_rings))
3784 for (i = 0; i < adev->gfx.num_gfx_rings; i++)
3785 kiq->pmf->kiq_unmap_queues(kiq_ring, &adev->gfx.gfx_ring[i],
3786 PREEMPT_QUEUES, 0, 0);
3788 return amdgpu_ring_test_helper(kiq_ring);
3792 static int gfx_v10_0_hw_fini(void *handle)
3794 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3797 amdgpu_irq_put(adev, &adev->gfx.priv_reg_irq, 0);
3798 amdgpu_irq_put(adev, &adev->gfx.priv_inst_irq, 0);
3799 #ifndef BRING_UP_DEBUG
3800 if (amdgpu_async_gfx_ring) {
3801 r = gfx_v10_0_kiq_disable_kgq(adev);
3803 DRM_ERROR("KGQ disable failed\n");
3806 if (amdgpu_gfx_disable_kcq(adev))
3807 DRM_ERROR("KCQ disable failed\n");
3808 if (amdgpu_sriov_vf(adev)) {
3809 gfx_v10_0_cp_gfx_enable(adev, false);
3812 gfx_v10_0_cp_enable(adev, false);
3813 gfx_v10_0_enable_gui_idle_interrupt(adev, false);
3818 static int gfx_v10_0_suspend(void *handle)
3820 return gfx_v10_0_hw_fini(handle);
3823 static int gfx_v10_0_resume(void *handle)
3825 return gfx_v10_0_hw_init(handle);
3828 static bool gfx_v10_0_is_idle(void *handle)
3830 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3832 if (REG_GET_FIELD(RREG32_SOC15(GC, 0, mmGRBM_STATUS),
3833 GRBM_STATUS, GUI_ACTIVE))
3839 static int gfx_v10_0_wait_for_idle(void *handle)
3843 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3845 for (i = 0; i < adev->usec_timeout; i++) {
3846 /* read MC_STATUS */
3847 tmp = RREG32_SOC15(GC, 0, mmGRBM_STATUS) &
3848 GRBM_STATUS__GUI_ACTIVE_MASK;
3850 if (!REG_GET_FIELD(tmp, GRBM_STATUS, GUI_ACTIVE))
3857 static int gfx_v10_0_soft_reset(void *handle)
3859 u32 grbm_soft_reset = 0;
3861 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3864 tmp = RREG32_SOC15(GC, 0, mmGRBM_STATUS);
3865 if (tmp & (GRBM_STATUS__PA_BUSY_MASK | GRBM_STATUS__SC_BUSY_MASK |
3866 GRBM_STATUS__BCI_BUSY_MASK | GRBM_STATUS__SX_BUSY_MASK |
3867 GRBM_STATUS__TA_BUSY_MASK | GRBM_STATUS__DB_BUSY_MASK |
3868 GRBM_STATUS__CB_BUSY_MASK | GRBM_STATUS__GDS_BUSY_MASK |
3869 GRBM_STATUS__SPI_BUSY_MASK | GRBM_STATUS__GE_BUSY_NO_DMA_MASK
3870 | GRBM_STATUS__BCI_BUSY_MASK)) {
3871 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
3872 GRBM_SOFT_RESET, SOFT_RESET_CP,
3874 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
3875 GRBM_SOFT_RESET, SOFT_RESET_GFX,
3879 if (tmp & (GRBM_STATUS__CP_BUSY_MASK | GRBM_STATUS__CP_COHERENCY_BUSY_MASK)) {
3880 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
3881 GRBM_SOFT_RESET, SOFT_RESET_CP,
3886 tmp = RREG32_SOC15(GC, 0, mmGRBM_STATUS2);
3887 if (REG_GET_FIELD(tmp, GRBM_STATUS2, RLC_BUSY))
3888 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
3889 GRBM_SOFT_RESET, SOFT_RESET_RLC,
3892 if (grbm_soft_reset) {
3894 gfx_v10_0_rlc_stop(adev);
3896 /* Disable GFX parsing/prefetching */
3897 gfx_v10_0_cp_gfx_enable(adev, false);
3899 /* Disable MEC parsing/prefetching */
3900 gfx_v10_0_cp_compute_enable(adev, false);
3902 if (grbm_soft_reset) {
3903 tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET);
3904 tmp |= grbm_soft_reset;
3905 dev_info(adev->dev, "GRBM_SOFT_RESET=0x%08X\n", tmp);
3906 WREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET, tmp);
3907 tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET);
3911 tmp &= ~grbm_soft_reset;
3912 WREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET, tmp);
3913 tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET);
3916 /* Wait a little for things to settle down */
3922 static uint64_t gfx_v10_0_get_gpu_clock_counter(struct amdgpu_device *adev)
3926 amdgpu_gfx_off_ctrl(adev, false);
3927 mutex_lock(&adev->gfx.gpu_clock_mutex);
3928 WREG32_SOC15(GC, 0, mmRLC_CAPTURE_GPU_CLOCK_COUNT, 1);
3929 clock = (uint64_t)RREG32_SOC15(GC, 0, mmRLC_GPU_CLOCK_COUNT_LSB) |
3930 ((uint64_t)RREG32_SOC15(GC, 0, mmRLC_GPU_CLOCK_COUNT_MSB) << 32ULL);
3931 mutex_unlock(&adev->gfx.gpu_clock_mutex);
3932 amdgpu_gfx_off_ctrl(adev, true);
3936 static void gfx_v10_0_ring_emit_gds_switch(struct amdgpu_ring *ring,
3938 uint32_t gds_base, uint32_t gds_size,
3939 uint32_t gws_base, uint32_t gws_size,
3940 uint32_t oa_base, uint32_t oa_size)
3942 struct amdgpu_device *adev = ring->adev;
3945 gfx_v10_0_write_data_to_reg(ring, 0, false,
3946 SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_BASE) + 2 * vmid,
3950 gfx_v10_0_write_data_to_reg(ring, 0, false,
3951 SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_SIZE) + 2 * vmid,
3955 gfx_v10_0_write_data_to_reg(ring, 0, false,
3956 SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID0) + vmid,
3957 gws_size << GDS_GWS_VMID0__SIZE__SHIFT | gws_base);
3960 gfx_v10_0_write_data_to_reg(ring, 0, false,
3961 SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID0) + vmid,
3962 (1 << (oa_size + oa_base)) - (1 << oa_base));
3965 static int gfx_v10_0_early_init(void *handle)
3967 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3969 adev->gfx.num_gfx_rings = GFX10_NUM_GFX_RINGS_NV1X;
3971 adev->gfx.num_compute_rings = AMDGPU_MAX_COMPUTE_RINGS;
3973 gfx_v10_0_set_kiq_pm4_funcs(adev);
3974 gfx_v10_0_set_ring_funcs(adev);
3975 gfx_v10_0_set_irq_funcs(adev);
3976 gfx_v10_0_set_gds_init(adev);
3977 gfx_v10_0_set_rlc_funcs(adev);
3982 static int gfx_v10_0_late_init(void *handle)
3984 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3987 r = amdgpu_irq_get(adev, &adev->gfx.priv_reg_irq, 0);
3991 r = amdgpu_irq_get(adev, &adev->gfx.priv_inst_irq, 0);
3998 static bool gfx_v10_0_is_rlc_enabled(struct amdgpu_device *adev)
4002 /* if RLC is not enabled, do nothing */
4003 rlc_cntl = RREG32_SOC15(GC, 0, mmRLC_CNTL);
4004 return (REG_GET_FIELD(rlc_cntl, RLC_CNTL, RLC_ENABLE_F32)) ? true : false;
4007 static void gfx_v10_0_set_safe_mode(struct amdgpu_device *adev)
4012 data = RLC_SAFE_MODE__CMD_MASK;
4013 data |= (1 << RLC_SAFE_MODE__MESSAGE__SHIFT);
4014 WREG32_SOC15(GC, 0, mmRLC_SAFE_MODE, data);
4016 /* wait for RLC_SAFE_MODE */
4017 for (i = 0; i < adev->usec_timeout; i++) {
4018 if (!REG_GET_FIELD(RREG32_SOC15(GC, 0, mmRLC_SAFE_MODE), RLC_SAFE_MODE, CMD))
4024 static void gfx_v10_0_unset_safe_mode(struct amdgpu_device *adev)
4028 data = RLC_SAFE_MODE__CMD_MASK;
4029 WREG32_SOC15(GC, 0, mmRLC_SAFE_MODE, data);
4032 static void gfx_v10_0_update_medium_grain_clock_gating(struct amdgpu_device *adev,
4037 /* It is disabled by HW by default */
4038 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG)) {
4039 /* 1 - RLC_CGTT_MGCG_OVERRIDE */
4040 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
4041 data &= ~(RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK |
4042 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK |
4043 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGLS_OVERRIDE_MASK);
4045 /* only for Vega10 & Raven1 */
4046 data |= RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK;
4049 WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data);
4051 /* MGLS is a global flag to control all MGLS in GFX */
4052 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGLS) {
4053 /* 2 - RLC memory Light sleep */
4054 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_RLC_LS) {
4055 def = data = RREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL);
4056 data |= RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK;
4058 WREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL, data);
4060 /* 3 - CP memory Light sleep */
4061 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CP_LS) {
4062 def = data = RREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL);
4063 data |= CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK;
4065 WREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL, data);
4069 /* 1 - MGCG_OVERRIDE */
4070 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
4071 data |= (RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK |
4072 RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK |
4073 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK |
4074 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGLS_OVERRIDE_MASK);
4076 WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data);
4078 /* 2 - disable MGLS in RLC */
4079 data = RREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL);
4080 if (data & RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK) {
4081 data &= ~RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK;
4082 WREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL, data);
4085 /* 3 - disable MGLS in CP */
4086 data = RREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL);
4087 if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK) {
4088 data &= ~CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK;
4089 WREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL, data);
4094 static void gfx_v10_0_update_3d_clock_gating(struct amdgpu_device *adev,
4099 /* Enable 3D CGCG/CGLS */
4100 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGCG)) {
4101 /* write cmd to clear cgcg/cgls ov */
4102 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
4103 /* unset CGCG override */
4104 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_GFX3D_CG_OVERRIDE_MASK;
4105 /* update CGCG and CGLS override bits */
4107 WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data);
4108 /* enable 3Dcgcg FSM(0x0000363f) */
4109 def = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D);
4110 data = (0x36 << RLC_CGCG_CGLS_CTRL_3D__CGCG_GFX_IDLE_THRESHOLD__SHIFT) |
4111 RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK;
4112 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGLS)
4113 data |= (0x000F << RLC_CGCG_CGLS_CTRL_3D__CGLS_REP_COMPANSAT_DELAY__SHIFT) |
4114 RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK;
4116 WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D, data);
4118 /* set IDLE_POLL_COUNT(0x00900100) */
4119 def = RREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL);
4120 data = (0x0100 << CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY__SHIFT) |
4121 (0x0090 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT);
4123 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL, data);
4125 /* Disable CGCG/CGLS */
4126 def = data = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D);
4127 /* disable cgcg, cgls should be disabled */
4128 data &= ~(RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK |
4129 RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK);
4130 /* disable cgcg and cgls in FSM */
4132 WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D, data);
4136 static void gfx_v10_0_update_coarse_grain_clock_gating(struct amdgpu_device *adev,
4141 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG)) {
4142 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
4143 /* unset CGCG override */
4144 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGCG_OVERRIDE_MASK;
4145 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS)
4146 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGLS_OVERRIDE_MASK;
4148 data |= RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGLS_OVERRIDE_MASK;
4149 /* update CGCG and CGLS override bits */
4151 WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data);
4153 /* enable cgcg FSM(0x0000363F) */
4154 def = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL);
4155 data = (0x36 << RLC_CGCG_CGLS_CTRL__CGCG_GFX_IDLE_THRESHOLD__SHIFT) |
4156 RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK;
4157 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS)
4158 data |= (0x000F << RLC_CGCG_CGLS_CTRL__CGLS_REP_COMPANSAT_DELAY__SHIFT) |
4159 RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK;
4161 WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL, data);
4163 /* set IDLE_POLL_COUNT(0x00900100) */
4164 def = RREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL);
4165 data = (0x0100 << CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY__SHIFT) |
4166 (0x0090 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT);
4168 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL, data);
4170 def = data = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL);
4171 /* reset CGCG/CGLS bits */
4172 data &= ~(RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK | RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK);
4173 /* disable cgcg and cgls in FSM */
4175 WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL, data);
4179 static int gfx_v10_0_update_gfx_clock_gating(struct amdgpu_device *adev,
4182 amdgpu_gfx_rlc_enter_safe_mode(adev);
4185 /* CGCG/CGLS should be enabled after MGCG/MGLS
4186 * === MGCG + MGLS ===
4188 gfx_v10_0_update_medium_grain_clock_gating(adev, enable);
4189 /* === CGCG /CGLS for GFX 3D Only === */
4190 gfx_v10_0_update_3d_clock_gating(adev, enable);
4191 /* === CGCG + CGLS === */
4192 gfx_v10_0_update_coarse_grain_clock_gating(adev, enable);
4194 /* CGCG/CGLS should be disabled before MGCG/MGLS
4195 * === CGCG + CGLS ===
4197 gfx_v10_0_update_coarse_grain_clock_gating(adev, enable);
4198 /* === CGCG /CGLS for GFX 3D Only === */
4199 gfx_v10_0_update_3d_clock_gating(adev, enable);
4200 /* === MGCG + MGLS === */
4201 gfx_v10_0_update_medium_grain_clock_gating(adev, enable);
4204 if (adev->cg_flags &
4205 (AMD_CG_SUPPORT_GFX_MGCG |
4206 AMD_CG_SUPPORT_GFX_CGLS |
4207 AMD_CG_SUPPORT_GFX_CGCG |
4208 AMD_CG_SUPPORT_GFX_CGLS |
4209 AMD_CG_SUPPORT_GFX_3D_CGCG |
4210 AMD_CG_SUPPORT_GFX_3D_CGLS))
4211 gfx_v10_0_enable_gui_idle_interrupt(adev, enable);
4213 amdgpu_gfx_rlc_exit_safe_mode(adev);
4218 static void gfx_v10_0_update_spm_vmid(struct amdgpu_device *adev, unsigned vmid)
4222 data = RREG32_SOC15(GC, 0, mmRLC_SPM_MC_CNTL);
4224 data &= ~RLC_SPM_MC_CNTL__RLC_SPM_VMID_MASK;
4225 data |= (vmid & RLC_SPM_MC_CNTL__RLC_SPM_VMID_MASK) << RLC_SPM_MC_CNTL__RLC_SPM_VMID__SHIFT;
4227 WREG32_SOC15(GC, 0, mmRLC_SPM_MC_CNTL, data);
4230 static const struct amdgpu_rlc_funcs gfx_v10_0_rlc_funcs = {
4231 .is_rlc_enabled = gfx_v10_0_is_rlc_enabled,
4232 .set_safe_mode = gfx_v10_0_set_safe_mode,
4233 .unset_safe_mode = gfx_v10_0_unset_safe_mode,
4234 .init = gfx_v10_0_rlc_init,
4235 .get_csb_size = gfx_v10_0_get_csb_size,
4236 .get_csb_buffer = gfx_v10_0_get_csb_buffer,
4237 .resume = gfx_v10_0_rlc_resume,
4238 .stop = gfx_v10_0_rlc_stop,
4239 .reset = gfx_v10_0_rlc_reset,
4240 .start = gfx_v10_0_rlc_start,
4241 .update_spm_vmid = gfx_v10_0_update_spm_vmid
4244 static int gfx_v10_0_set_powergating_state(void *handle,
4245 enum amd_powergating_state state)
4247 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4248 bool enable = (state == AMD_PG_STATE_GATE);
4249 switch (adev->asic_type) {
4253 amdgpu_gfx_off_ctrl(adev, false);
4254 cancel_delayed_work_sync(&adev->gfx.gfx_off_delay_work);
4256 amdgpu_gfx_off_ctrl(adev, true);
4264 static int gfx_v10_0_set_clockgating_state(void *handle,
4265 enum amd_clockgating_state state)
4267 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4269 switch (adev->asic_type) {
4273 gfx_v10_0_update_gfx_clock_gating(adev,
4274 state == AMD_CG_STATE_GATE);
4282 static void gfx_v10_0_get_clockgating_state(void *handle, u32 *flags)
4284 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4287 /* AMD_CG_SUPPORT_GFX_MGCG */
4288 data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
4289 if (!(data & RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK))
4290 *flags |= AMD_CG_SUPPORT_GFX_MGCG;
4292 /* AMD_CG_SUPPORT_GFX_CGCG */
4293 data = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL);
4294 if (data & RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK)
4295 *flags |= AMD_CG_SUPPORT_GFX_CGCG;
4297 /* AMD_CG_SUPPORT_GFX_CGLS */
4298 if (data & RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK)
4299 *flags |= AMD_CG_SUPPORT_GFX_CGLS;
4301 /* AMD_CG_SUPPORT_GFX_RLC_LS */
4302 data = RREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL);
4303 if (data & RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK)
4304 *flags |= AMD_CG_SUPPORT_GFX_RLC_LS | AMD_CG_SUPPORT_GFX_MGLS;
4306 /* AMD_CG_SUPPORT_GFX_CP_LS */
4307 data = RREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL);
4308 if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK)
4309 *flags |= AMD_CG_SUPPORT_GFX_CP_LS | AMD_CG_SUPPORT_GFX_MGLS;
4311 /* AMD_CG_SUPPORT_GFX_3D_CGCG */
4312 data = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D);
4313 if (data & RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK)
4314 *flags |= AMD_CG_SUPPORT_GFX_3D_CGCG;
4316 /* AMD_CG_SUPPORT_GFX_3D_CGLS */
4317 if (data & RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK)
4318 *flags |= AMD_CG_SUPPORT_GFX_3D_CGLS;
4321 static u64 gfx_v10_0_ring_get_rptr_gfx(struct amdgpu_ring *ring)
4323 return ring->adev->wb.wb[ring->rptr_offs]; /* gfx10 is 32bit rptr*/
4326 static u64 gfx_v10_0_ring_get_wptr_gfx(struct amdgpu_ring *ring)
4328 struct amdgpu_device *adev = ring->adev;
4331 /* XXX check if swapping is necessary on BE */
4332 if (ring->use_doorbell) {
4333 wptr = atomic64_read((atomic64_t *)&adev->wb.wb[ring->wptr_offs]);
4335 wptr = RREG32_SOC15(GC, 0, mmCP_RB0_WPTR);
4336 wptr += (u64)RREG32_SOC15(GC, 0, mmCP_RB0_WPTR_HI) << 32;
4342 static void gfx_v10_0_ring_set_wptr_gfx(struct amdgpu_ring *ring)
4344 struct amdgpu_device *adev = ring->adev;
4346 if (ring->use_doorbell) {
4347 /* XXX check if swapping is necessary on BE */
4348 atomic64_set((atomic64_t *)&adev->wb.wb[ring->wptr_offs], ring->wptr);
4349 WDOORBELL64(ring->doorbell_index, ring->wptr);
4351 WREG32_SOC15(GC, 0, mmCP_RB0_WPTR, lower_32_bits(ring->wptr));
4352 WREG32_SOC15(GC, 0, mmCP_RB0_WPTR_HI, upper_32_bits(ring->wptr));
4356 static u64 gfx_v10_0_ring_get_rptr_compute(struct amdgpu_ring *ring)
4358 return ring->adev->wb.wb[ring->rptr_offs]; /* gfx10 hardware is 32bit rptr */
4361 static u64 gfx_v10_0_ring_get_wptr_compute(struct amdgpu_ring *ring)
4365 /* XXX check if swapping is necessary on BE */
4366 if (ring->use_doorbell)
4367 wptr = atomic64_read((atomic64_t *)&ring->adev->wb.wb[ring->wptr_offs]);
4373 static void gfx_v10_0_ring_set_wptr_compute(struct amdgpu_ring *ring)
4375 struct amdgpu_device *adev = ring->adev;
4377 /* XXX check if swapping is necessary on BE */
4378 if (ring->use_doorbell) {
4379 atomic64_set((atomic64_t *)&adev->wb.wb[ring->wptr_offs], ring->wptr);
4380 WDOORBELL64(ring->doorbell_index, ring->wptr);
4382 BUG(); /* only DOORBELL method supported on gfx10 now */
4386 static void gfx_v10_0_ring_emit_hdp_flush(struct amdgpu_ring *ring)
4388 struct amdgpu_device *adev = ring->adev;
4389 u32 ref_and_mask, reg_mem_engine;
4390 const struct nbio_hdp_flush_reg *nbio_hf_reg = adev->nbio.hdp_flush_reg;
4392 if (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE) {
4395 ref_and_mask = nbio_hf_reg->ref_and_mask_cp2 << ring->pipe;
4398 ref_and_mask = nbio_hf_reg->ref_and_mask_cp6 << ring->pipe;
4405 ref_and_mask = nbio_hf_reg->ref_and_mask_cp0;
4406 reg_mem_engine = 1; /* pfp */
4409 gfx_v10_0_wait_reg_mem(ring, reg_mem_engine, 0, 1,
4410 adev->nbio.funcs->get_hdp_flush_req_offset(adev),
4411 adev->nbio.funcs->get_hdp_flush_done_offset(adev),
4412 ref_and_mask, ref_and_mask, 0x20);
4415 static void gfx_v10_0_ring_emit_ib_gfx(struct amdgpu_ring *ring,
4416 struct amdgpu_job *job,
4417 struct amdgpu_ib *ib,
4420 unsigned vmid = AMDGPU_JOB_GET_VMID(job);
4421 u32 header, control = 0;
4423 if (ib->flags & AMDGPU_IB_FLAG_CE)
4424 header = PACKET3(PACKET3_INDIRECT_BUFFER_CNST, 2);
4426 header = PACKET3(PACKET3_INDIRECT_BUFFER, 2);
4428 control |= ib->length_dw | (vmid << 24);
4430 if ((amdgpu_sriov_vf(ring->adev) || amdgpu_mcbp) && (ib->flags & AMDGPU_IB_FLAG_PREEMPT)) {
4431 control |= INDIRECT_BUFFER_PRE_ENB(1);
4433 if (flags & AMDGPU_IB_PREEMPTED)
4434 control |= INDIRECT_BUFFER_PRE_RESUME(1);
4436 if (!(ib->flags & AMDGPU_IB_FLAG_CE) && vmid)
4437 gfx_v10_0_ring_emit_de_meta(ring,
4438 (!amdgpu_sriov_vf(ring->adev) && flags & AMDGPU_IB_PREEMPTED) ? true : false);
4441 amdgpu_ring_write(ring, header);
4442 BUG_ON(ib->gpu_addr & 0x3); /* Dword align */
4443 amdgpu_ring_write(ring,
4447 lower_32_bits(ib->gpu_addr));
4448 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
4449 amdgpu_ring_write(ring, control);
4452 static void gfx_v10_0_ring_emit_ib_compute(struct amdgpu_ring *ring,
4453 struct amdgpu_job *job,
4454 struct amdgpu_ib *ib,
4457 unsigned vmid = AMDGPU_JOB_GET_VMID(job);
4458 u32 control = INDIRECT_BUFFER_VALID | ib->length_dw | (vmid << 24);
4460 /* Currently, there is a high possibility to get wave ID mismatch
4461 * between ME and GDS, leading to a hw deadlock, because ME generates
4462 * different wave IDs than the GDS expects. This situation happens
4463 * randomly when at least 5 compute pipes use GDS ordered append.
4464 * The wave IDs generated by ME are also wrong after suspend/resume.
4465 * Those are probably bugs somewhere else in the kernel driver.
4467 * Writing GDS_COMPUTE_MAX_WAVE_ID resets wave ID counters in ME and
4468 * GDS to 0 for this ring (me/pipe).
4470 if (ib->flags & AMDGPU_IB_FLAG_RESET_GDS_MAX_WAVE_ID) {
4471 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
4472 amdgpu_ring_write(ring, mmGDS_COMPUTE_MAX_WAVE_ID);
4473 amdgpu_ring_write(ring, ring->adev->gds.gds_compute_max_wave_id);
4476 amdgpu_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2));
4477 BUG_ON(ib->gpu_addr & 0x3); /* Dword align */
4478 amdgpu_ring_write(ring,
4482 lower_32_bits(ib->gpu_addr));
4483 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
4484 amdgpu_ring_write(ring, control);
4487 static void gfx_v10_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr,
4488 u64 seq, unsigned flags)
4490 struct amdgpu_device *adev = ring->adev;
4491 bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT;
4492 bool int_sel = flags & AMDGPU_FENCE_FLAG_INT;
4494 /* Interrupt not work fine on GFX10.1 model yet. Use fallback instead */
4495 if (adev->pdev->device == 0x50)
4498 /* RELEASE_MEM - flush caches, send int */
4499 amdgpu_ring_write(ring, PACKET3(PACKET3_RELEASE_MEM, 6));
4500 amdgpu_ring_write(ring, (PACKET3_RELEASE_MEM_GCR_SEQ |
4501 PACKET3_RELEASE_MEM_GCR_GL2_WB |
4502 PACKET3_RELEASE_MEM_GCR_GLM_INV | /* must be set with GLM_WB */
4503 PACKET3_RELEASE_MEM_GCR_GLM_WB |
4504 PACKET3_RELEASE_MEM_CACHE_POLICY(3) |
4505 PACKET3_RELEASE_MEM_EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) |
4506 PACKET3_RELEASE_MEM_EVENT_INDEX(5)));
4507 amdgpu_ring_write(ring, (PACKET3_RELEASE_MEM_DATA_SEL(write64bit ? 2 : 1) |
4508 PACKET3_RELEASE_MEM_INT_SEL(int_sel ? 2 : 0)));
4511 * the address should be Qword aligned if 64bit write, Dword
4512 * aligned if only send 32bit data low (discard data high)
4518 amdgpu_ring_write(ring, lower_32_bits(addr));
4519 amdgpu_ring_write(ring, upper_32_bits(addr));
4520 amdgpu_ring_write(ring, lower_32_bits(seq));
4521 amdgpu_ring_write(ring, upper_32_bits(seq));
4522 amdgpu_ring_write(ring, 0);
4525 static void gfx_v10_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring)
4527 int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX);
4528 uint32_t seq = ring->fence_drv.sync_seq;
4529 uint64_t addr = ring->fence_drv.gpu_addr;
4531 gfx_v10_0_wait_reg_mem(ring, usepfp, 1, 0, lower_32_bits(addr),
4532 upper_32_bits(addr), seq, 0xffffffff, 4);
4535 static void gfx_v10_0_ring_emit_vm_flush(struct amdgpu_ring *ring,
4536 unsigned vmid, uint64_t pd_addr)
4538 amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr);
4540 /* compute doesn't have PFP */
4541 if (ring->funcs->type == AMDGPU_RING_TYPE_GFX) {
4542 /* sync PFP to ME, otherwise we might get invalid PFP reads */
4543 amdgpu_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0));
4544 amdgpu_ring_write(ring, 0x0);
4548 static void gfx_v10_0_ring_emit_fence_kiq(struct amdgpu_ring *ring, u64 addr,
4549 u64 seq, unsigned int flags)
4551 struct amdgpu_device *adev = ring->adev;
4553 /* we only allocate 32bit for each seq wb address */
4554 BUG_ON(flags & AMDGPU_FENCE_FLAG_64BIT);
4556 /* write fence seq to the "addr" */
4557 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
4558 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
4559 WRITE_DATA_DST_SEL(5) | WR_CONFIRM));
4560 amdgpu_ring_write(ring, lower_32_bits(addr));
4561 amdgpu_ring_write(ring, upper_32_bits(addr));
4562 amdgpu_ring_write(ring, lower_32_bits(seq));
4564 if (flags & AMDGPU_FENCE_FLAG_INT) {
4565 /* set register to trigger INT */
4566 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
4567 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
4568 WRITE_DATA_DST_SEL(0) | WR_CONFIRM));
4569 amdgpu_ring_write(ring, SOC15_REG_OFFSET(GC, 0, mmCPC_INT_STATUS));
4570 amdgpu_ring_write(ring, 0);
4571 amdgpu_ring_write(ring, 0x20000000); /* src_id is 178 */
4575 static void gfx_v10_0_ring_emit_sb(struct amdgpu_ring *ring)
4577 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0));
4578 amdgpu_ring_write(ring, 0);
4581 static void gfx_v10_0_ring_emit_cntxcntl(struct amdgpu_ring *ring, uint32_t flags)
4585 if (amdgpu_mcbp || amdgpu_sriov_vf(ring->adev))
4586 gfx_v10_0_ring_emit_ce_meta(ring,
4587 (!amdgpu_sriov_vf(ring->adev) && flags & AMDGPU_IB_PREEMPTED) ? true : false);
4589 gfx_v10_0_ring_emit_tmz(ring, true);
4591 dw2 |= 0x80000000; /* set load_enable otherwise this package is just NOPs */
4592 if (flags & AMDGPU_HAVE_CTX_SWITCH) {
4593 /* set load_global_config & load_global_uconfig */
4595 /* set load_cs_sh_regs */
4597 /* set load_per_context_state & load_gfx_sh_regs for GFX */
4600 /* set load_ce_ram if preamble presented */
4601 if (AMDGPU_PREAMBLE_IB_PRESENT & flags)
4604 /* still load_ce_ram if this is the first time preamble presented
4605 * although there is no context switch happens.
4607 if (AMDGPU_PREAMBLE_IB_PRESENT_FIRST & flags)
4611 amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1));
4612 amdgpu_ring_write(ring, dw2);
4613 amdgpu_ring_write(ring, 0);
4616 static unsigned gfx_v10_0_ring_emit_init_cond_exec(struct amdgpu_ring *ring)
4620 amdgpu_ring_write(ring, PACKET3(PACKET3_COND_EXEC, 3));
4621 amdgpu_ring_write(ring, lower_32_bits(ring->cond_exe_gpu_addr));
4622 amdgpu_ring_write(ring, upper_32_bits(ring->cond_exe_gpu_addr));
4623 amdgpu_ring_write(ring, 0); /* discard following DWs if *cond_exec_gpu_addr==0 */
4624 ret = ring->wptr & ring->buf_mask;
4625 amdgpu_ring_write(ring, 0x55aa55aa); /* patch dummy value later */
4630 static void gfx_v10_0_ring_emit_patch_cond_exec(struct amdgpu_ring *ring, unsigned offset)
4633 BUG_ON(offset > ring->buf_mask);
4634 BUG_ON(ring->ring[offset] != 0x55aa55aa);
4636 cur = (ring->wptr - 1) & ring->buf_mask;
4637 if (likely(cur > offset))
4638 ring->ring[offset] = cur - offset;
4640 ring->ring[offset] = (ring->buf_mask + 1) - offset + cur;
4643 static int gfx_v10_0_ring_preempt_ib(struct amdgpu_ring *ring)
4646 struct amdgpu_device *adev = ring->adev;
4647 struct amdgpu_kiq *kiq = &adev->gfx.kiq;
4648 struct amdgpu_ring *kiq_ring = &kiq->ring;
4650 if (!kiq->pmf || !kiq->pmf->kiq_unmap_queues)
4653 if (amdgpu_ring_alloc(kiq_ring, kiq->pmf->unmap_queues_size))
4656 /* assert preemption condition */
4657 amdgpu_ring_set_preempt_cond_exec(ring, false);
4659 /* assert IB preemption, emit the trailing fence */
4660 kiq->pmf->kiq_unmap_queues(kiq_ring, ring, PREEMPT_QUEUES_NO_UNMAP,
4661 ring->trail_fence_gpu_addr,
4663 amdgpu_ring_commit(kiq_ring);
4665 /* poll the trailing fence */
4666 for (i = 0; i < adev->usec_timeout; i++) {
4667 if (ring->trail_seq ==
4668 le32_to_cpu(*(ring->trail_fence_cpu_addr)))
4673 if (i >= adev->usec_timeout) {
4675 DRM_ERROR("ring %d failed to preempt ib\n", ring->idx);
4678 /* deassert preemption condition */
4679 amdgpu_ring_set_preempt_cond_exec(ring, true);
4683 static void gfx_v10_0_ring_emit_ce_meta(struct amdgpu_ring *ring, bool resume)
4685 struct amdgpu_device *adev = ring->adev;
4686 struct v10_ce_ib_state ce_payload = {0};
4690 cnt = (sizeof(ce_payload) >> 2) + 4 - 2;
4691 csa_addr = amdgpu_csa_vaddr(ring->adev);
4693 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, cnt));
4694 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(2) |
4695 WRITE_DATA_DST_SEL(8) |
4697 WRITE_DATA_CACHE_POLICY(0));
4698 amdgpu_ring_write(ring, lower_32_bits(csa_addr +
4699 offsetof(struct v10_gfx_meta_data, ce_payload)));
4700 amdgpu_ring_write(ring, upper_32_bits(csa_addr +
4701 offsetof(struct v10_gfx_meta_data, ce_payload)));
4704 amdgpu_ring_write_multiple(ring, adev->virt.csa_cpu_addr +
4705 offsetof(struct v10_gfx_meta_data,
4707 sizeof(ce_payload) >> 2);
4709 amdgpu_ring_write_multiple(ring, (void *)&ce_payload,
4710 sizeof(ce_payload) >> 2);
4713 static void gfx_v10_0_ring_emit_de_meta(struct amdgpu_ring *ring, bool resume)
4715 struct amdgpu_device *adev = ring->adev;
4716 struct v10_de_ib_state de_payload = {0};
4717 uint64_t csa_addr, gds_addr;
4720 csa_addr = amdgpu_csa_vaddr(ring->adev);
4721 gds_addr = ALIGN(csa_addr + AMDGPU_CSA_SIZE - adev->gds.gds_size,
4723 de_payload.gds_backup_addrlo = lower_32_bits(gds_addr);
4724 de_payload.gds_backup_addrhi = upper_32_bits(gds_addr);
4726 cnt = (sizeof(de_payload) >> 2) + 4 - 2;
4727 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, cnt));
4728 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(1) |
4729 WRITE_DATA_DST_SEL(8) |
4731 WRITE_DATA_CACHE_POLICY(0));
4732 amdgpu_ring_write(ring, lower_32_bits(csa_addr +
4733 offsetof(struct v10_gfx_meta_data, de_payload)));
4734 amdgpu_ring_write(ring, upper_32_bits(csa_addr +
4735 offsetof(struct v10_gfx_meta_data, de_payload)));
4738 amdgpu_ring_write_multiple(ring, adev->virt.csa_cpu_addr +
4739 offsetof(struct v10_gfx_meta_data,
4741 sizeof(de_payload) >> 2);
4743 amdgpu_ring_write_multiple(ring, (void *)&de_payload,
4744 sizeof(de_payload) >> 2);
4747 static void gfx_v10_0_ring_emit_tmz(struct amdgpu_ring *ring, bool start)
4749 amdgpu_ring_write(ring, PACKET3(PACKET3_FRAME_CONTROL, 0));
4750 amdgpu_ring_write(ring, FRAME_CMD(start ? 0 : 1)); /* frame_end */
4753 static void gfx_v10_0_ring_emit_rreg(struct amdgpu_ring *ring, uint32_t reg)
4755 struct amdgpu_device *adev = ring->adev;
4756 struct amdgpu_kiq *kiq = &adev->gfx.kiq;
4758 amdgpu_ring_write(ring, PACKET3(PACKET3_COPY_DATA, 4));
4759 amdgpu_ring_write(ring, 0 | /* src: register*/
4760 (5 << 8) | /* dst: memory */
4761 (1 << 20)); /* write confirm */
4762 amdgpu_ring_write(ring, reg);
4763 amdgpu_ring_write(ring, 0);
4764 amdgpu_ring_write(ring, lower_32_bits(adev->wb.gpu_addr +
4765 kiq->reg_val_offs * 4));
4766 amdgpu_ring_write(ring, upper_32_bits(adev->wb.gpu_addr +
4767 kiq->reg_val_offs * 4));
4770 static void gfx_v10_0_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg,
4775 switch (ring->funcs->type) {
4776 case AMDGPU_RING_TYPE_GFX:
4777 cmd = WRITE_DATA_ENGINE_SEL(1) | WR_CONFIRM;
4779 case AMDGPU_RING_TYPE_KIQ:
4780 cmd = (1 << 16); /* no inc addr */
4786 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
4787 amdgpu_ring_write(ring, cmd);
4788 amdgpu_ring_write(ring, reg);
4789 amdgpu_ring_write(ring, 0);
4790 amdgpu_ring_write(ring, val);
4793 static void gfx_v10_0_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg,
4794 uint32_t val, uint32_t mask)
4796 gfx_v10_0_wait_reg_mem(ring, 0, 0, 0, reg, 0, val, mask, 0x20);
4799 static void gfx_v10_0_ring_emit_reg_write_reg_wait(struct amdgpu_ring *ring,
4800 uint32_t reg0, uint32_t reg1,
4801 uint32_t ref, uint32_t mask)
4803 int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX);
4804 struct amdgpu_device *adev = ring->adev;
4805 bool fw_version_ok = false;
4807 fw_version_ok = adev->gfx.cp_fw_write_wait;
4810 gfx_v10_0_wait_reg_mem(ring, usepfp, 0, 1, reg0, reg1,
4813 amdgpu_ring_emit_reg_write_reg_wait_helper(ring, reg0, reg1,
4818 gfx_v10_0_set_gfx_eop_interrupt_state(struct amdgpu_device *adev,
4819 uint32_t me, uint32_t pipe,
4820 enum amdgpu_interrupt_state state)
4822 uint32_t cp_int_cntl, cp_int_cntl_reg;
4827 cp_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_INT_CNTL_RING0);
4830 cp_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_INT_CNTL_RING1);
4833 DRM_DEBUG("invalid pipe %d\n", pipe);
4837 DRM_DEBUG("invalid me %d\n", me);
4842 case AMDGPU_IRQ_STATE_DISABLE:
4843 cp_int_cntl = RREG32(cp_int_cntl_reg);
4844 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0,
4845 TIME_STAMP_INT_ENABLE, 0);
4846 WREG32(cp_int_cntl_reg, cp_int_cntl);
4848 case AMDGPU_IRQ_STATE_ENABLE:
4849 cp_int_cntl = RREG32(cp_int_cntl_reg);
4850 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0,
4851 TIME_STAMP_INT_ENABLE, 1);
4852 WREG32(cp_int_cntl_reg, cp_int_cntl);
4859 static void gfx_v10_0_set_compute_eop_interrupt_state(struct amdgpu_device *adev,
4861 enum amdgpu_interrupt_state state)
4863 u32 mec_int_cntl, mec_int_cntl_reg;
4866 * amdgpu controls only the first MEC. That's why this function only
4867 * handles the setting of interrupts for this specific MEC. All other
4868 * pipes' interrupts are set by amdkfd.
4874 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE0_INT_CNTL);
4877 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE1_INT_CNTL);
4880 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE2_INT_CNTL);
4883 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE3_INT_CNTL);
4886 DRM_DEBUG("invalid pipe %d\n", pipe);
4890 DRM_DEBUG("invalid me %d\n", me);
4895 case AMDGPU_IRQ_STATE_DISABLE:
4896 mec_int_cntl = RREG32(mec_int_cntl_reg);
4897 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL,
4898 TIME_STAMP_INT_ENABLE, 0);
4899 WREG32(mec_int_cntl_reg, mec_int_cntl);
4901 case AMDGPU_IRQ_STATE_ENABLE:
4902 mec_int_cntl = RREG32(mec_int_cntl_reg);
4903 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL,
4904 TIME_STAMP_INT_ENABLE, 1);
4905 WREG32(mec_int_cntl_reg, mec_int_cntl);
4912 static int gfx_v10_0_set_eop_interrupt_state(struct amdgpu_device *adev,
4913 struct amdgpu_irq_src *src,
4915 enum amdgpu_interrupt_state state)
4918 case AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP:
4919 gfx_v10_0_set_gfx_eop_interrupt_state(adev, 0, 0, state);
4921 case AMDGPU_CP_IRQ_GFX_ME0_PIPE1_EOP:
4922 gfx_v10_0_set_gfx_eop_interrupt_state(adev, 0, 1, state);
4924 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP:
4925 gfx_v10_0_set_compute_eop_interrupt_state(adev, 1, 0, state);
4927 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP:
4928 gfx_v10_0_set_compute_eop_interrupt_state(adev, 1, 1, state);
4930 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP:
4931 gfx_v10_0_set_compute_eop_interrupt_state(adev, 1, 2, state);
4933 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP:
4934 gfx_v10_0_set_compute_eop_interrupt_state(adev, 1, 3, state);
4936 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE0_EOP:
4937 gfx_v10_0_set_compute_eop_interrupt_state(adev, 2, 0, state);
4939 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE1_EOP:
4940 gfx_v10_0_set_compute_eop_interrupt_state(adev, 2, 1, state);
4942 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE2_EOP:
4943 gfx_v10_0_set_compute_eop_interrupt_state(adev, 2, 2, state);
4945 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE3_EOP:
4946 gfx_v10_0_set_compute_eop_interrupt_state(adev, 2, 3, state);
4954 static int gfx_v10_0_eop_irq(struct amdgpu_device *adev,
4955 struct amdgpu_irq_src *source,
4956 struct amdgpu_iv_entry *entry)
4959 u8 me_id, pipe_id, queue_id;
4960 struct amdgpu_ring *ring;
4962 DRM_DEBUG("IH: CP EOP\n");
4963 me_id = (entry->ring_id & 0x0c) >> 2;
4964 pipe_id = (entry->ring_id & 0x03) >> 0;
4965 queue_id = (entry->ring_id & 0x70) >> 4;
4970 amdgpu_fence_process(&adev->gfx.gfx_ring[0]);
4972 amdgpu_fence_process(&adev->gfx.gfx_ring[1]);
4976 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
4977 ring = &adev->gfx.compute_ring[i];
4978 /* Per-queue interrupt is supported for MEC starting from VI.
4979 * The interrupt can only be enabled/disabled per pipe instead of per queue.
4981 if ((ring->me == me_id) && (ring->pipe == pipe_id) && (ring->queue == queue_id))
4982 amdgpu_fence_process(ring);
4989 static int gfx_v10_0_set_priv_reg_fault_state(struct amdgpu_device *adev,
4990 struct amdgpu_irq_src *source,
4992 enum amdgpu_interrupt_state state)
4995 case AMDGPU_IRQ_STATE_DISABLE:
4996 case AMDGPU_IRQ_STATE_ENABLE:
4997 WREG32_FIELD15(GC, 0, CP_INT_CNTL_RING0,
4998 PRIV_REG_INT_ENABLE,
4999 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0);
5008 static int gfx_v10_0_set_priv_inst_fault_state(struct amdgpu_device *adev,
5009 struct amdgpu_irq_src *source,
5011 enum amdgpu_interrupt_state state)
5014 case AMDGPU_IRQ_STATE_DISABLE:
5015 case AMDGPU_IRQ_STATE_ENABLE:
5016 WREG32_FIELD15(GC, 0, CP_INT_CNTL_RING0,
5017 PRIV_INSTR_INT_ENABLE,
5018 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0);
5026 static void gfx_v10_0_handle_priv_fault(struct amdgpu_device *adev,
5027 struct amdgpu_iv_entry *entry)
5029 u8 me_id, pipe_id, queue_id;
5030 struct amdgpu_ring *ring;
5033 me_id = (entry->ring_id & 0x0c) >> 2;
5034 pipe_id = (entry->ring_id & 0x03) >> 0;
5035 queue_id = (entry->ring_id & 0x70) >> 4;
5039 for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
5040 ring = &adev->gfx.gfx_ring[i];
5041 /* we only enabled 1 gfx queue per pipe for now */
5042 if (ring->me == me_id && ring->pipe == pipe_id)
5043 drm_sched_fault(&ring->sched);
5048 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
5049 ring = &adev->gfx.compute_ring[i];
5050 if (ring->me == me_id && ring->pipe == pipe_id &&
5051 ring->queue == queue_id)
5052 drm_sched_fault(&ring->sched);
5060 static int gfx_v10_0_priv_reg_irq(struct amdgpu_device *adev,
5061 struct amdgpu_irq_src *source,
5062 struct amdgpu_iv_entry *entry)
5064 DRM_ERROR("Illegal register access in command stream\n");
5065 gfx_v10_0_handle_priv_fault(adev, entry);
5069 static int gfx_v10_0_priv_inst_irq(struct amdgpu_device *adev,
5070 struct amdgpu_irq_src *source,
5071 struct amdgpu_iv_entry *entry)
5073 DRM_ERROR("Illegal instruction in command stream\n");
5074 gfx_v10_0_handle_priv_fault(adev, entry);
5078 static int gfx_v10_0_kiq_set_interrupt_state(struct amdgpu_device *adev,
5079 struct amdgpu_irq_src *src,
5081 enum amdgpu_interrupt_state state)
5083 uint32_t tmp, target;
5084 struct amdgpu_ring *ring = &(adev->gfx.kiq.ring);
5087 target = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE0_INT_CNTL);
5089 target = SOC15_REG_OFFSET(GC, 0, mmCP_ME2_PIPE0_INT_CNTL);
5090 target += ring->pipe;
5093 case AMDGPU_CP_KIQ_IRQ_DRIVER0:
5094 if (state == AMDGPU_IRQ_STATE_DISABLE) {
5095 tmp = RREG32_SOC15(GC, 0, mmCPC_INT_CNTL);
5096 tmp = REG_SET_FIELD(tmp, CPC_INT_CNTL,
5097 GENERIC2_INT_ENABLE, 0);
5098 WREG32_SOC15(GC, 0, mmCPC_INT_CNTL, tmp);
5100 tmp = RREG32(target);
5101 tmp = REG_SET_FIELD(tmp, CP_ME2_PIPE0_INT_CNTL,
5102 GENERIC2_INT_ENABLE, 0);
5103 WREG32(target, tmp);
5105 tmp = RREG32_SOC15(GC, 0, mmCPC_INT_CNTL);
5106 tmp = REG_SET_FIELD(tmp, CPC_INT_CNTL,
5107 GENERIC2_INT_ENABLE, 1);
5108 WREG32_SOC15(GC, 0, mmCPC_INT_CNTL, tmp);
5110 tmp = RREG32(target);
5111 tmp = REG_SET_FIELD(tmp, CP_ME2_PIPE0_INT_CNTL,
5112 GENERIC2_INT_ENABLE, 1);
5113 WREG32(target, tmp);
5117 BUG(); /* kiq only support GENERIC2_INT now */
5123 static int gfx_v10_0_kiq_irq(struct amdgpu_device *adev,
5124 struct amdgpu_irq_src *source,
5125 struct amdgpu_iv_entry *entry)
5127 u8 me_id, pipe_id, queue_id;
5128 struct amdgpu_ring *ring = &(adev->gfx.kiq.ring);
5130 me_id = (entry->ring_id & 0x0c) >> 2;
5131 pipe_id = (entry->ring_id & 0x03) >> 0;
5132 queue_id = (entry->ring_id & 0x70) >> 4;
5133 DRM_DEBUG("IH: CPC GENERIC2_INT, me:%d, pipe:%d, queue:%d\n",
5134 me_id, pipe_id, queue_id);
5136 amdgpu_fence_process(ring);
5140 static const struct amd_ip_funcs gfx_v10_0_ip_funcs = {
5141 .name = "gfx_v10_0",
5142 .early_init = gfx_v10_0_early_init,
5143 .late_init = gfx_v10_0_late_init,
5144 .sw_init = gfx_v10_0_sw_init,
5145 .sw_fini = gfx_v10_0_sw_fini,
5146 .hw_init = gfx_v10_0_hw_init,
5147 .hw_fini = gfx_v10_0_hw_fini,
5148 .suspend = gfx_v10_0_suspend,
5149 .resume = gfx_v10_0_resume,
5150 .is_idle = gfx_v10_0_is_idle,
5151 .wait_for_idle = gfx_v10_0_wait_for_idle,
5152 .soft_reset = gfx_v10_0_soft_reset,
5153 .set_clockgating_state = gfx_v10_0_set_clockgating_state,
5154 .set_powergating_state = gfx_v10_0_set_powergating_state,
5155 .get_clockgating_state = gfx_v10_0_get_clockgating_state,
5158 static const struct amdgpu_ring_funcs gfx_v10_0_ring_funcs_gfx = {
5159 .type = AMDGPU_RING_TYPE_GFX,
5161 .nop = PACKET3(PACKET3_NOP, 0x3FFF),
5162 .support_64bit_ptrs = true,
5163 .vmhub = AMDGPU_GFXHUB_0,
5164 .get_rptr = gfx_v10_0_ring_get_rptr_gfx,
5165 .get_wptr = gfx_v10_0_ring_get_wptr_gfx,
5166 .set_wptr = gfx_v10_0_ring_set_wptr_gfx,
5167 .emit_frame_size = /* totally 242 maximum if 16 IBs */
5169 7 + /* PIPELINE_SYNC */
5170 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 +
5171 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 +
5173 8 + /* FENCE for VM_FLUSH */
5174 20 + /* GDS switch */
5175 4 + /* double SWITCH_BUFFER,
5176 * the first COND_EXEC jump to the place
5177 * just prior to this double SWITCH_BUFFER
5186 8 + 8 + /* FENCE x2 */
5187 2, /* SWITCH_BUFFER */
5188 .emit_ib_size = 4, /* gfx_v10_0_ring_emit_ib_gfx */
5189 .emit_ib = gfx_v10_0_ring_emit_ib_gfx,
5190 .emit_fence = gfx_v10_0_ring_emit_fence,
5191 .emit_pipeline_sync = gfx_v10_0_ring_emit_pipeline_sync,
5192 .emit_vm_flush = gfx_v10_0_ring_emit_vm_flush,
5193 .emit_gds_switch = gfx_v10_0_ring_emit_gds_switch,
5194 .emit_hdp_flush = gfx_v10_0_ring_emit_hdp_flush,
5195 .test_ring = gfx_v10_0_ring_test_ring,
5196 .test_ib = gfx_v10_0_ring_test_ib,
5197 .insert_nop = amdgpu_ring_insert_nop,
5198 .pad_ib = amdgpu_ring_generic_pad_ib,
5199 .emit_switch_buffer = gfx_v10_0_ring_emit_sb,
5200 .emit_cntxcntl = gfx_v10_0_ring_emit_cntxcntl,
5201 .init_cond_exec = gfx_v10_0_ring_emit_init_cond_exec,
5202 .patch_cond_exec = gfx_v10_0_ring_emit_patch_cond_exec,
5203 .preempt_ib = gfx_v10_0_ring_preempt_ib,
5204 .emit_tmz = gfx_v10_0_ring_emit_tmz,
5205 .emit_wreg = gfx_v10_0_ring_emit_wreg,
5206 .emit_reg_wait = gfx_v10_0_ring_emit_reg_wait,
5207 .emit_reg_write_reg_wait = gfx_v10_0_ring_emit_reg_write_reg_wait,
5210 static const struct amdgpu_ring_funcs gfx_v10_0_ring_funcs_compute = {
5211 .type = AMDGPU_RING_TYPE_COMPUTE,
5213 .nop = PACKET3(PACKET3_NOP, 0x3FFF),
5214 .support_64bit_ptrs = true,
5215 .vmhub = AMDGPU_GFXHUB_0,
5216 .get_rptr = gfx_v10_0_ring_get_rptr_compute,
5217 .get_wptr = gfx_v10_0_ring_get_wptr_compute,
5218 .set_wptr = gfx_v10_0_ring_set_wptr_compute,
5220 20 + /* gfx_v10_0_ring_emit_gds_switch */
5221 7 + /* gfx_v10_0_ring_emit_hdp_flush */
5222 5 + /* hdp invalidate */
5223 7 + /* gfx_v10_0_ring_emit_pipeline_sync */
5224 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 +
5225 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 +
5226 2 + /* gfx_v10_0_ring_emit_vm_flush */
5227 8 + 8 + 8, /* gfx_v10_0_ring_emit_fence x3 for user fence, vm fence */
5228 .emit_ib_size = 7, /* gfx_v10_0_ring_emit_ib_compute */
5229 .emit_ib = gfx_v10_0_ring_emit_ib_compute,
5230 .emit_fence = gfx_v10_0_ring_emit_fence,
5231 .emit_pipeline_sync = gfx_v10_0_ring_emit_pipeline_sync,
5232 .emit_vm_flush = gfx_v10_0_ring_emit_vm_flush,
5233 .emit_gds_switch = gfx_v10_0_ring_emit_gds_switch,
5234 .emit_hdp_flush = gfx_v10_0_ring_emit_hdp_flush,
5235 .test_ring = gfx_v10_0_ring_test_ring,
5236 .test_ib = gfx_v10_0_ring_test_ib,
5237 .insert_nop = amdgpu_ring_insert_nop,
5238 .pad_ib = amdgpu_ring_generic_pad_ib,
5239 .emit_wreg = gfx_v10_0_ring_emit_wreg,
5240 .emit_reg_wait = gfx_v10_0_ring_emit_reg_wait,
5241 .emit_reg_write_reg_wait = gfx_v10_0_ring_emit_reg_write_reg_wait,
5244 static const struct amdgpu_ring_funcs gfx_v10_0_ring_funcs_kiq = {
5245 .type = AMDGPU_RING_TYPE_KIQ,
5247 .nop = PACKET3(PACKET3_NOP, 0x3FFF),
5248 .support_64bit_ptrs = true,
5249 .vmhub = AMDGPU_GFXHUB_0,
5250 .get_rptr = gfx_v10_0_ring_get_rptr_compute,
5251 .get_wptr = gfx_v10_0_ring_get_wptr_compute,
5252 .set_wptr = gfx_v10_0_ring_set_wptr_compute,
5254 20 + /* gfx_v10_0_ring_emit_gds_switch */
5255 7 + /* gfx_v10_0_ring_emit_hdp_flush */
5256 5 + /*hdp invalidate */
5257 7 + /* gfx_v10_0_ring_emit_pipeline_sync */
5258 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 +
5259 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 +
5260 2 + /* gfx_v10_0_ring_emit_vm_flush */
5261 8 + 8 + 8, /* gfx_v10_0_ring_emit_fence_kiq x3 for user fence, vm fence */
5262 .emit_ib_size = 7, /* gfx_v10_0_ring_emit_ib_compute */
5263 .emit_ib = gfx_v10_0_ring_emit_ib_compute,
5264 .emit_fence = gfx_v10_0_ring_emit_fence_kiq,
5265 .test_ring = gfx_v10_0_ring_test_ring,
5266 .test_ib = gfx_v10_0_ring_test_ib,
5267 .insert_nop = amdgpu_ring_insert_nop,
5268 .pad_ib = amdgpu_ring_generic_pad_ib,
5269 .emit_rreg = gfx_v10_0_ring_emit_rreg,
5270 .emit_wreg = gfx_v10_0_ring_emit_wreg,
5271 .emit_reg_wait = gfx_v10_0_ring_emit_reg_wait,
5272 .emit_reg_write_reg_wait = gfx_v10_0_ring_emit_reg_write_reg_wait,
5275 static void gfx_v10_0_set_ring_funcs(struct amdgpu_device *adev)
5279 adev->gfx.kiq.ring.funcs = &gfx_v10_0_ring_funcs_kiq;
5281 for (i = 0; i < adev->gfx.num_gfx_rings; i++)
5282 adev->gfx.gfx_ring[i].funcs = &gfx_v10_0_ring_funcs_gfx;
5284 for (i = 0; i < adev->gfx.num_compute_rings; i++)
5285 adev->gfx.compute_ring[i].funcs = &gfx_v10_0_ring_funcs_compute;
5288 static const struct amdgpu_irq_src_funcs gfx_v10_0_eop_irq_funcs = {
5289 .set = gfx_v10_0_set_eop_interrupt_state,
5290 .process = gfx_v10_0_eop_irq,
5293 static const struct amdgpu_irq_src_funcs gfx_v10_0_priv_reg_irq_funcs = {
5294 .set = gfx_v10_0_set_priv_reg_fault_state,
5295 .process = gfx_v10_0_priv_reg_irq,
5298 static const struct amdgpu_irq_src_funcs gfx_v10_0_priv_inst_irq_funcs = {
5299 .set = gfx_v10_0_set_priv_inst_fault_state,
5300 .process = gfx_v10_0_priv_inst_irq,
5303 static const struct amdgpu_irq_src_funcs gfx_v10_0_kiq_irq_funcs = {
5304 .set = gfx_v10_0_kiq_set_interrupt_state,
5305 .process = gfx_v10_0_kiq_irq,
5308 static void gfx_v10_0_set_irq_funcs(struct amdgpu_device *adev)
5310 adev->gfx.eop_irq.num_types = AMDGPU_CP_IRQ_LAST;
5311 adev->gfx.eop_irq.funcs = &gfx_v10_0_eop_irq_funcs;
5313 adev->gfx.kiq.irq.num_types = AMDGPU_CP_KIQ_IRQ_LAST;
5314 adev->gfx.kiq.irq.funcs = &gfx_v10_0_kiq_irq_funcs;
5316 adev->gfx.priv_reg_irq.num_types = 1;
5317 adev->gfx.priv_reg_irq.funcs = &gfx_v10_0_priv_reg_irq_funcs;
5319 adev->gfx.priv_inst_irq.num_types = 1;
5320 adev->gfx.priv_inst_irq.funcs = &gfx_v10_0_priv_inst_irq_funcs;
5323 static void gfx_v10_0_set_rlc_funcs(struct amdgpu_device *adev)
5325 switch (adev->asic_type) {
5329 adev->gfx.rlc.funcs = &gfx_v10_0_rlc_funcs;
5336 static void gfx_v10_0_set_gds_init(struct amdgpu_device *adev)
5338 unsigned total_cu = adev->gfx.config.max_cu_per_sh *
5339 adev->gfx.config.max_sh_per_se *
5340 adev->gfx.config.max_shader_engines;
5342 adev->gds.gds_size = 0x10000;
5343 adev->gds.gds_compute_max_wave_id = total_cu * 32 - 1;
5344 adev->gds.gws_size = 64;
5345 adev->gds.oa_size = 16;
5348 static void gfx_v10_0_set_user_wgp_inactive_bitmap_per_sh(struct amdgpu_device *adev,
5356 data = bitmap << GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_WGPS__SHIFT;
5357 data &= GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_WGPS_MASK;
5359 WREG32_SOC15(GC, 0, mmGC_USER_SHADER_ARRAY_CONFIG, data);
5362 static u32 gfx_v10_0_get_wgp_active_bitmap_per_sh(struct amdgpu_device *adev)
5364 u32 data, wgp_bitmask;
5365 data = RREG32_SOC15(GC, 0, mmCC_GC_SHADER_ARRAY_CONFIG);
5366 data |= RREG32_SOC15(GC, 0, mmGC_USER_SHADER_ARRAY_CONFIG);
5368 data &= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_WGPS_MASK;
5369 data >>= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_WGPS__SHIFT;
5372 amdgpu_gfx_create_bitmask(adev->gfx.config.max_cu_per_sh >> 1);
5374 return (~data) & wgp_bitmask;
5377 static u32 gfx_v10_0_get_cu_active_bitmap_per_sh(struct amdgpu_device *adev)
5379 u32 wgp_idx, wgp_active_bitmap;
5380 u32 cu_bitmap_per_wgp, cu_active_bitmap;
5382 wgp_active_bitmap = gfx_v10_0_get_wgp_active_bitmap_per_sh(adev);
5383 cu_active_bitmap = 0;
5385 for (wgp_idx = 0; wgp_idx < 16; wgp_idx++) {
5386 /* if there is one WGP enabled, it means 2 CUs will be enabled */
5387 cu_bitmap_per_wgp = 3 << (2 * wgp_idx);
5388 if (wgp_active_bitmap & (1 << wgp_idx))
5389 cu_active_bitmap |= cu_bitmap_per_wgp;
5392 return cu_active_bitmap;
5395 static int gfx_v10_0_get_cu_info(struct amdgpu_device *adev,
5396 struct amdgpu_cu_info *cu_info)
5398 int i, j, k, counter, active_cu_number = 0;
5399 u32 mask, bitmap, ao_bitmap, ao_cu_mask = 0;
5400 unsigned disable_masks[4 * 2];
5402 if (!adev || !cu_info)
5405 amdgpu_gfx_parse_disable_cu(disable_masks, 4, 2);
5407 mutex_lock(&adev->grbm_idx_mutex);
5408 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
5409 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
5413 gfx_v10_0_select_se_sh(adev, i, j, 0xffffffff);
5415 gfx_v10_0_set_user_wgp_inactive_bitmap_per_sh(
5416 adev, disable_masks[i * 2 + j]);
5417 bitmap = gfx_v10_0_get_cu_active_bitmap_per_sh(adev);
5418 cu_info->bitmap[i][j] = bitmap;
5420 for (k = 0; k < adev->gfx.config.max_cu_per_sh; k++) {
5421 if (bitmap & mask) {
5422 if (counter < adev->gfx.config.max_cu_per_sh)
5428 active_cu_number += counter;
5430 ao_cu_mask |= (ao_bitmap << (i * 16 + j * 8));
5431 cu_info->ao_cu_bitmap[i][j] = ao_bitmap;
5434 gfx_v10_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
5435 mutex_unlock(&adev->grbm_idx_mutex);
5437 cu_info->number = active_cu_number;
5438 cu_info->ao_cu_mask = ao_cu_mask;
5439 cu_info->simd_per_cu = NUM_SIMD_PER_CU;
5444 const struct amdgpu_ip_block_version gfx_v10_0_ip_block =
5446 .type = AMD_IP_BLOCK_TYPE_GFX,
5450 .funcs = &gfx_v10_0_ip_funcs,