drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c

   1 /*
   2  * Copyright 2019 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23
  24 #include <linux/delay.h>
  25 #include <linux/kernel.h>
  26 #include <linux/firmware.h>
  27 #include <linux/module.h>
  28 #include <linux/pci.h>
  29 #include "amdgpu.h"
  30 #include "amdgpu_gfx.h"
  31 #include "amdgpu_psp.h"
  32 #include "nv.h"
  33 #include "nvd.h"
  34
  35 #include "gc/gc_10_1_0_offset.h"
  36 #include "gc/gc_10_1_0_sh_mask.h"
  37 #include "smuio/smuio_11_0_0_offset.h"
  38 #include "smuio/smuio_11_0_0_sh_mask.h"
  39 #include "navi10_enum.h"
  40 #include "ivsrcid/gfx/irqsrcs_gfx_10_1.h"
  41
  42 #include "soc15.h"
  43 #include "soc15d.h"
  44 #include "soc15_common.h"
  45 #include "clearstate_gfx10.h"
  46 #include "v10_structs.h"
  47 #include "gfx_v10_0.h"
  48 #include "nbio_v2_3.h"
  49
  50 /**
  51  * Navi10 has two graphic rings to share each graphic pipe.
  52  * 1. Primary ring
  53  * 2. Async ring
  54  */
  55 #define GFX10_NUM_GFX_RINGS_NV1X        1
  56 #define GFX10_NUM_GFX_RINGS_Sienna_Cichlid      1
  57 #define GFX10_MEC_HPD_SIZE      2048
  58
  59 #define F32_CE_PROGRAM_RAM_SIZE         65536
  60 #define RLCG_UCODE_LOADING_START_ADDRESS        0x00002000L
  61
  62 #define mmCGTT_GS_NGG_CLK_CTRL  0x5087
  63 #define mmCGTT_GS_NGG_CLK_CTRL_BASE_IDX 1
  64 #define mmCGTT_SPI_RA0_CLK_CTRL 0x507a
  65 #define mmCGTT_SPI_RA0_CLK_CTRL_BASE_IDX 1
  66 #define mmCGTT_SPI_RA1_CLK_CTRL 0x507b
  67 #define mmCGTT_SPI_RA1_CLK_CTRL_BASE_IDX 1
  68
  69 #define GB_ADDR_CONFIG__NUM_PKRS__SHIFT                                                                       0x8
  70 #define GB_ADDR_CONFIG__NUM_PKRS_MASK                                                                         0x00000700L
  71
  72 #define mmCGTS_TCC_DISABLE_gc_10_3                 0x5006
  73 #define mmCGTS_TCC_DISABLE_gc_10_3_BASE_IDX        1
  74 #define mmCGTS_USER_TCC_DISABLE_gc_10_3            0x5007
  75 #define mmCGTS_USER_TCC_DISABLE_gc_10_3_BASE_IDX   1
  76
  77 #define mmCP_MEC_CNTL_Sienna_Cichlid                      0x0f55
  78 #define mmCP_MEC_CNTL_Sienna_Cichlid_BASE_IDX             0
  79 #define mmRLC_SAFE_MODE_Sienna_Cichlid                  0x4ca0
  80 #define mmRLC_SAFE_MODE_Sienna_Cichlid_BASE_IDX         1
  81 #define mmRLC_CP_SCHEDULERS_Sienna_Cichlid              0x4ca1
  82 #define mmRLC_CP_SCHEDULERS_Sienna_Cichlid_BASE_IDX     1
  83 #define mmSPI_CONFIG_CNTL_Sienna_Cichlid                        0x11ec
  84 #define mmSPI_CONFIG_CNTL_Sienna_Cichlid_BASE_IDX               0
  85 #define mmVGT_ESGS_RING_SIZE_Sienna_Cichlid             0x0fc1
  86 #define mmVGT_ESGS_RING_SIZE_Sienna_Cichlid_BASE_IDX    0
  87 #define mmVGT_GSVS_RING_SIZE_Sienna_Cichlid             0x0fc2
  88 #define mmVGT_GSVS_RING_SIZE_Sienna_Cichlid_BASE_IDX    0
  89 #define mmVGT_TF_RING_SIZE_Sienna_Cichlid                       0x0fc3
  90 #define mmVGT_TF_RING_SIZE_Sienna_Cichlid_BASE_IDX      0
  91 #define mmVGT_HS_OFFCHIP_PARAM_Sienna_Cichlid           0x0fc4
  92 #define mmVGT_HS_OFFCHIP_PARAM_Sienna_Cichlid_BASE_IDX  0
  93 #define mmVGT_TF_MEMORY_BASE_Sienna_Cichlid             0x0fc5
  94 #define mmVGT_TF_MEMORY_BASE_Sienna_Cichlid_BASE_IDX    0
  95 #define mmVGT_TF_MEMORY_BASE_HI_Sienna_Cichlid          0x0fc6
  96 #define mmVGT_TF_MEMORY_BASE_HI_Sienna_Cichlid_BASE_IDX 0
  97 #define GRBM_STATUS2__RLC_BUSY_Sienna_Cichlid__SHIFT    0x1a
  98 #define GRBM_STATUS2__RLC_BUSY_Sienna_Cichlid_MASK      0x04000000L
  99 #define CP_RB_DOORBELL_RANGE_LOWER__DOORBELL_RANGE_LOWER_Sienna_Cichlid_MASK    0x00000FFCL
 100 #define CP_RB_DOORBELL_RANGE_LOWER__DOORBELL_RANGE_LOWER_Sienna_Cichlid__SHIFT  0x2
 101 #define CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_Sienna_Cichlid_MASK    0x00000FFCL
 102 #define mmGCR_GENERAL_CNTL_Sienna_Cichlid                       0x1580
 103 #define mmGCR_GENERAL_CNTL_Sienna_Cichlid_BASE_IDX      0
 104
 105 #define mmGOLDEN_TSC_COUNT_UPPER_Vangogh                0x0025
 106 #define mmGOLDEN_TSC_COUNT_UPPER_Vangogh_BASE_IDX       1
 107 #define mmGOLDEN_TSC_COUNT_LOWER_Vangogh                0x0026
 108 #define mmGOLDEN_TSC_COUNT_LOWER_Vangogh_BASE_IDX       1
 109 #define mmSPI_CONFIG_CNTL_1_Vangogh              0x2441
 110 #define mmSPI_CONFIG_CNTL_1_Vangogh_BASE_IDX     1
 111 #define mmVGT_TF_MEMORY_BASE_HI_Vangogh          0x2261
 112 #define mmVGT_TF_MEMORY_BASE_HI_Vangogh_BASE_IDX 1
 113 #define mmVGT_HS_OFFCHIP_PARAM_Vangogh           0x224f
 114 #define mmVGT_HS_OFFCHIP_PARAM_Vangogh_BASE_IDX  1
 115 #define mmVGT_TF_RING_SIZE_Vangogh               0x224e
 116 #define mmVGT_TF_RING_SIZE_Vangogh_BASE_IDX      1
 117 #define mmVGT_GSVS_RING_SIZE_Vangogh             0x2241
 118 #define mmVGT_GSVS_RING_SIZE_Vangogh_BASE_IDX    1
 119 #define mmVGT_TF_MEMORY_BASE_Vangogh             0x2250
 120 #define mmVGT_TF_MEMORY_BASE_Vangogh_BASE_IDX    1
 121 #define mmVGT_ESGS_RING_SIZE_Vangogh             0x2240
 122 #define mmVGT_ESGS_RING_SIZE_Vangogh_BASE_IDX    1
 123 #define mmSPI_CONFIG_CNTL_Vangogh                0x2440
 124 #define mmSPI_CONFIG_CNTL_Vangogh_BASE_IDX       1
 125 #define mmGCR_GENERAL_CNTL_Vangogh               0x1580
 126 #define mmGCR_GENERAL_CNTL_Vangogh_BASE_IDX      0
 127 #define RLC_PG_DELAY_3__CGCG_ACTIVE_BEFORE_CGPG_MASK_Vangogh   0x0000FFFFL
 128
 129 #define mmCP_HYP_PFP_UCODE_ADDR                 0x5814
 130 #define mmCP_HYP_PFP_UCODE_ADDR_BASE_IDX        1
 131 #define mmCP_HYP_PFP_UCODE_DATA                 0x5815
 132 #define mmCP_HYP_PFP_UCODE_DATA_BASE_IDX        1
 133 #define mmCP_HYP_CE_UCODE_ADDR                  0x5818
 134 #define mmCP_HYP_CE_UCODE_ADDR_BASE_IDX         1
 135 #define mmCP_HYP_CE_UCODE_DATA                  0x5819
 136 #define mmCP_HYP_CE_UCODE_DATA_BASE_IDX         1
 137 #define mmCP_HYP_ME_UCODE_ADDR                  0x5816
 138 #define mmCP_HYP_ME_UCODE_ADDR_BASE_IDX         1
 139 #define mmCP_HYP_ME_UCODE_DATA                  0x5817
 140 #define mmCP_HYP_ME_UCODE_DATA_BASE_IDX         1
 141
 142 #define mmCPG_PSP_DEBUG                         0x5c10
 143 #define mmCPG_PSP_DEBUG_BASE_IDX                1
 144 #define mmCPC_PSP_DEBUG                         0x5c11
 145 #define mmCPC_PSP_DEBUG_BASE_IDX                1
 146 #define CPC_PSP_DEBUG__GPA_OVERRIDE_MASK        0x00000008L
 147 #define CPG_PSP_DEBUG__GPA_OVERRIDE_MASK        0x00000008L
 148
 149 //CC_GC_SA_UNIT_DISABLE
 150 #define mmCC_GC_SA_UNIT_DISABLE                 0x0fe9
 151 #define mmCC_GC_SA_UNIT_DISABLE_BASE_IDX        0
 152 #define CC_GC_SA_UNIT_DISABLE__SA_DISABLE__SHIFT        0x8
 153 #define CC_GC_SA_UNIT_DISABLE__SA_DISABLE_MASK          0x0000FF00L
 154 //GC_USER_SA_UNIT_DISABLE
 155 #define mmGC_USER_SA_UNIT_DISABLE               0x0fea
 156 #define mmGC_USER_SA_UNIT_DISABLE_BASE_IDX      0
 157 #define GC_USER_SA_UNIT_DISABLE__SA_DISABLE__SHIFT      0x8
 158 #define GC_USER_SA_UNIT_DISABLE__SA_DISABLE_MASK        0x0000FF00L
 159 //PA_SC_ENHANCE_3
 160 #define mmPA_SC_ENHANCE_3                       0x1085
 161 #define mmPA_SC_ENHANCE_3_BASE_IDX              0
 162 #define PA_SC_ENHANCE_3__FORCE_PBB_WORKLOAD_MODE_TO_ZERO__SHIFT 0x3
 163 #define PA_SC_ENHANCE_3__FORCE_PBB_WORKLOAD_MODE_TO_ZERO_MASK   0x00000008L
 164
 165 #define mmCGTT_SPI_CS_CLK_CTRL                  0x507c
 166 #define mmCGTT_SPI_CS_CLK_CTRL_BASE_IDX         1
 167
 168 #define mmGCUTCL2_CGTT_CLK_CTRL_Sienna_Cichlid          0x16f3
 169 #define mmGCUTCL2_CGTT_CLK_CTRL_Sienna_Cichlid_BASE_IDX 0
 170 #define mmGCVM_L2_CGTT_CLK_CTRL_Sienna_Cichlid          0x15db
 171 #define mmGCVM_L2_CGTT_CLK_CTRL_Sienna_Cichlid_BASE_IDX 0
 172
 173 #define mmGC_THROTTLE_CTRL_Sienna_Cichlid              0x2030
 174 #define mmGC_THROTTLE_CTRL_Sienna_Cichlid_BASE_IDX     0
 175
 176 #define GFX_RLCG_GC_WRITE_OLD   (0x8 << 28)
 177 #define GFX_RLCG_GC_WRITE       (0x0 << 28)
 178 #define GFX_RLCG_GC_READ        (0x1 << 28)
 179 #define GFX_RLCG_MMHUB_WRITE    (0x2 << 28)
 180
 181 MODULE_FIRMWARE("amdgpu/navi10_ce.bin");
 182 MODULE_FIRMWARE("amdgpu/navi10_pfp.bin");
 183 MODULE_FIRMWARE("amdgpu/navi10_me.bin");
 184 MODULE_FIRMWARE("amdgpu/navi10_mec.bin");
 185 MODULE_FIRMWARE("amdgpu/navi10_mec2.bin");
 186 MODULE_FIRMWARE("amdgpu/navi10_rlc.bin");
 187
 188 MODULE_FIRMWARE("amdgpu/navi14_ce_wks.bin");
 189 MODULE_FIRMWARE("amdgpu/navi14_pfp_wks.bin");
 190 MODULE_FIRMWARE("amdgpu/navi14_me_wks.bin");
 191 MODULE_FIRMWARE("amdgpu/navi14_mec_wks.bin");
 192 MODULE_FIRMWARE("amdgpu/navi14_mec2_wks.bin");
 193 MODULE_FIRMWARE("amdgpu/navi14_ce.bin");
 194 MODULE_FIRMWARE("amdgpu/navi14_pfp.bin");
 195 MODULE_FIRMWARE("amdgpu/navi14_me.bin");
 196 MODULE_FIRMWARE("amdgpu/navi14_mec.bin");
 197 MODULE_FIRMWARE("amdgpu/navi14_mec2.bin");
 198 MODULE_FIRMWARE("amdgpu/navi14_rlc.bin");
 199
 200 MODULE_FIRMWARE("amdgpu/navi12_ce.bin");
 201 MODULE_FIRMWARE("amdgpu/navi12_pfp.bin");
 202 MODULE_FIRMWARE("amdgpu/navi12_me.bin");
 203 MODULE_FIRMWARE("amdgpu/navi12_mec.bin");
 204 MODULE_FIRMWARE("amdgpu/navi12_mec2.bin");
 205 MODULE_FIRMWARE("amdgpu/navi12_rlc.bin");
 206
 207 MODULE_FIRMWARE("amdgpu/sienna_cichlid_ce.bin");
 208 MODULE_FIRMWARE("amdgpu/sienna_cichlid_pfp.bin");
 209 MODULE_FIRMWARE("amdgpu/sienna_cichlid_me.bin");
 210 MODULE_FIRMWARE("amdgpu/sienna_cichlid_mec.bin");
 211 MODULE_FIRMWARE("amdgpu/sienna_cichlid_mec2.bin");
 212 MODULE_FIRMWARE("amdgpu/sienna_cichlid_rlc.bin");
 213
 214 MODULE_FIRMWARE("amdgpu/navy_flounder_ce.bin");
 215 MODULE_FIRMWARE("amdgpu/navy_flounder_pfp.bin");
 216 MODULE_FIRMWARE("amdgpu/navy_flounder_me.bin");
 217 MODULE_FIRMWARE("amdgpu/navy_flounder_mec.bin");
 218 MODULE_FIRMWARE("amdgpu/navy_flounder_mec2.bin");
 219 MODULE_FIRMWARE("amdgpu/navy_flounder_rlc.bin");
 220
 221 MODULE_FIRMWARE("amdgpu/vangogh_ce.bin");
 222 MODULE_FIRMWARE("amdgpu/vangogh_pfp.bin");
 223 MODULE_FIRMWARE("amdgpu/vangogh_me.bin");
 224 MODULE_FIRMWARE("amdgpu/vangogh_mec.bin");
 225 MODULE_FIRMWARE("amdgpu/vangogh_mec2.bin");
 226 MODULE_FIRMWARE("amdgpu/vangogh_rlc.bin");
 227
 228 MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_ce.bin");
 229 MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_pfp.bin");
 230 MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_me.bin");
 231 MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_mec.bin");
 232 MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_mec2.bin");
 233 MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_rlc.bin");
 234
 235 static const struct soc15_reg_golden golden_settings_gc_10_1[] =
 236 {
 237         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_4, 0xffffffff, 0x00400014),
 238         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_CPF_CLK_CTRL, 0xfcff8fff, 0xf8000100),
 239         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CLK_CTRL, 0xcd000000, 0x0d000100),
 240         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQ_CLK_CTRL, 0x60000ff0, 0x60000100),
 241         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQG_CLK_CTRL, 0x40000000, 0x40000100),
 242         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_VGT_CLK_CTRL, 0xffff8fff, 0xffff8100),
 243         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_WD_CLK_CTRL, 0xfeff8fff, 0xfeff8100),
 244         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0xffffffff, 0xe4e4e4e4),
 245         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_VC5_ENABLE, 0x00000002, 0x00000000),
 246         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_SD_CNTL, 0x000007ff, 0x000005ff),
 247         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG, 0x20000000, 0x20000000),
 248         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG2, 0xffffffff, 0x00000420),
 249         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0x00000200, 0x00000200),
 250         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0x07900000, 0x04900000),
 251         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DFSM_TILES_IN_FLIGHT, 0x0000ffff, 0x0000003f),
 252         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_LAST_OF_BURST_CONFIG, 0xffffffff, 0x03860204),
 253         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL, 0x1ff0ffff, 0x00000500),
 254         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PRIV_CONTROL, 0x000007ff, 0x000001fe),
 255         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0xffffffff, 0xe4e4e4e4),
 256         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_0, 0x77777777, 0x10321032),
 257         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_1, 0x77777777, 0x02310231),
 258         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
 259         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
 260         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CGTT_SCLK_CTRL, 0x10000000, 0x10000100),
 261         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL2, 0xffffffff, 0x1402002f),
 262         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xffff9fff, 0x00001188),
 263         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800),
 264         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE, 0x3fffffff, 0x08000009),
 265         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_1, 0x00400000, 0x04440000),
 266         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0x00000800, 0x00000820),
 267         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000),
 268         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRMI_SPARE, 0xffffffff, 0xffff3101),
 269         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1, 0x001f0000, 0x00070104),
 270         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ALU_CLK_CTRL, 0xffffffff, 0xffffffff),
 271         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ARB_CONFIG, 0x00000100, 0x00000130),
 272         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_LDS_CLK_CTRL, 0xffffffff, 0xffffffff),
 273         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000),
 274         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CNTL, 0x60000010, 0x479c0010),
 275         SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CGTT_CLK_CTRL, 0xfeff0fff, 0x40000100),
 276         SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0x00c00000, 0x00c00000)
 277 };
 278
 279 static const struct soc15_reg_golden golden_settings_gc_10_0_nv10[] =
 280 {
 281         /* Pending on emulation bring up */
 282 };
 283
 284 static const struct soc15_reg_golden golden_settings_gc_rlc_spm_10_0_nv10[] =
 285 {
 286         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xe0000000, 0x0),
 287         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 288         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28),
 289         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 290         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
 291         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 292         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8),
 293         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 294         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
 295         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 296         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8),
 297         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 298         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
 299         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 300         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20),
 301         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 302         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
 303         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 304         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8),
 305         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 306         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
 307         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 308         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc),
 309         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 310         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
 311         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 312         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0),
 313         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 314         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
 315         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 316         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4),
 317         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 318         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
 319         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 320         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
 321         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 322         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
 323         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 324         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
 325         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 326         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
 327         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 328         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4),
 329         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 330         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
 331         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 332         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8),
 333         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 334         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
 335         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 336         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0),
 337         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 338         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
 339         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 340         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc),
 341         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 342         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
 343         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 344         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc),
 345         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 346         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
 347         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 348         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88),
 349         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 350         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
 351         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 352         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c),
 353         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 354         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
 355         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 356         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0),
 357         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 358         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
 359         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 360         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4),
 361         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 362         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
 363         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 364         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8),
 365         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 366         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
 367         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 368         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc),
 369         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 370         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
 371         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 372         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0),
 373         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 374         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
 375         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 376         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4),
 377         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 378         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
 379         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 380         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90),
 381         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 382         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
 383         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 384         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94),
 385         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 386         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
 387         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 388         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98),
 389         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 390         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
 391         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 392         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c),
 393         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 394         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
 395         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 396         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0),
 397         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 398         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
 399         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 400         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4),
 401         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 402         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
 403         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 404         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8),
 405         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 406         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
 407         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 408         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac),
 409         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 410         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
 411         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 412         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10),
 413         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 414         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
 415         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 416         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc),
 417         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 418         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
 419         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 420         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18),
 421         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 422         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
 423         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 424         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38),
 425         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 426         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
 427         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 428         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c),
 429         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 430         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
 431         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 432         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40),
 433         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 434         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
 435         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 436         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44),
 437         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 438         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
 439         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 440         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48),
 441         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 442         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
 443         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 444         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c),
 445         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 446         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
 447         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 448         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70),
 449         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 450         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
 451         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 452         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74),
 453         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 454         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
 455         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 456         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78),
 457         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 458         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
 459         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 460         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c),
 461         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 462         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
 463         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 464         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80),
 465         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 466         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
 467         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 468         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84),
 469         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 470         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
 471         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 472         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50),
 473         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 474         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
 475         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 476         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54),
 477         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 478         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
 479         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 480         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58),
 481         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 482         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
 483         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 484         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c),
 485         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 486         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
 487         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 488         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60),
 489         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 490         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
 491         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 492         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64),
 493         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 494         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
 495         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 496         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68),
 497         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 498         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
 499         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 500         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c),
 501         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 502         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
 503         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 504         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1c),
 505         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 506         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
 507         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 508         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14),
 509         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 510         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 511         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 512         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20),
 513         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 514         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
 515         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 516         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20),
 517         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 518         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
 519         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 520         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
 521         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 522         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
 523         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 524         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
 525         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 526         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
 527         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 528         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28),
 529         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 530         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
 531         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 532         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28),
 533         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 534         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
 535         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 536         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c),
 537         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 538         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
 539         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 540         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c),
 541         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 542         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
 543         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 544         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30),
 545         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 546         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
 547         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 548         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30),
 549         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 550         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
 551         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 552         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34),
 553         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 554         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
 555         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 556         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34),
 557         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 558         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
 559         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 560         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38),
 561         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 562         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
 563         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 564         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38),
 565         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 566         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
 567         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 568         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c),
 569         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 570         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
 571         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 572         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c),
 573         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 574         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
 575         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 576         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18),
 577         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 578         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
 579         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 580         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18),
 581         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 582         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
 583         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 584         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50),
 585         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 586         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
 587         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 588         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50),
 589         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 590         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
 591         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 592         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54),
 593         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 594         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
 595         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 596         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54),
 597         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 598         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
 599         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 600         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58),
 601         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 602         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
 603         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 604         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58),
 605         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 606         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
 607         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 608         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c),
 609         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 610         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
 611         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 612         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c),
 613         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 614         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
 615         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 616         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14),
 617         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 618         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d),
 619         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 620         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14),
 621         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 622         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d),
 623         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 624         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48),
 625         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 626         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
 627         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 628         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48),
 629         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 630         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
 631         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 632         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c),
 633         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 634         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
 635         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 636         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c),
 637         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 638         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
 639         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 640         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40),
 641         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 642         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c),
 643         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 644         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40),
 645         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 646         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c),
 647         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 648         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44),
 649         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 650         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
 651         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 652         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44),
 653         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 654         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
 655         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 656         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10),
 657         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 658         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17),
 659         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 660         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10),
 661         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 662         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17),
 663         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 664         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60),
 665         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 666         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 667         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 668         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60),
 669         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 670         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 671         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 672         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64),
 673         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 674         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
 675         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 676         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64),
 677         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 678         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
 679         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 680         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70),
 681         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 682         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
 683         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 684         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70),
 685         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 686         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
 687         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 688         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74),
 689         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 690         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 691         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 692         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74),
 693         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 694         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 695         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 696         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68),
 697         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 698         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 699         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 700         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68),
 701         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 702         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 703         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 704         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c),
 705         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 706         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
 707         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 708         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c),
 709         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 710         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
 711         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 712         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78),
 713         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 714         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
 715         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 716         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78),
 717         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 718         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
 719         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 720         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c),
 721         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 722         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
 723         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 724         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c),
 725         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 726         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
 727         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 728         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88),
 729         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 730         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
 731         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 732         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88),
 733         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 734         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
 735         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 736         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c),
 737         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 738         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
 739         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 740         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c),
 741         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 742         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
 743         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 744         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80),
 745         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 746         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
 747         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 748         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80),
 749         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 750         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
 751         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 752         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84),
 753         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 754         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
 755         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 756         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84),
 757         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 758         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
 759         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 760         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90),
 761         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 762         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
 763         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 764         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90),
 765         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 766         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
 767         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 768         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94),
 769         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 770         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
 771         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 772         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94),
 773         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 774         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
 775         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 776         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0),
 777         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 778         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
 779         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 780         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0),
 781         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 782         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
 783         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 784         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4),
 785         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 786         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
 787         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 788         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4),
 789         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 790         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
 791         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 792         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98),
 793         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 794         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
 795         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 796         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98),
 797         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 798         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
 799         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 800         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c),
 801         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 802         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
 803         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 804         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c),
 805         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 806         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
 807         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 808         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8),
 809         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 810         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 811         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 812         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8),
 813         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 814         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 815         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 816         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac),
 817         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 818         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
 819         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 820         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac),
 821         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 822         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
 823         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 824         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8),
 825         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 826         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
 827         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 828         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8),
 829         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 830         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
 831         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 832         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc),
 833         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 834         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
 835         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 836         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc),
 837         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 838         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
 839         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 840         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0),
 841         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 842         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 843         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 844         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0),
 845         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 846         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 847         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 848         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4),
 849         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 850         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
 851         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 852         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4),
 853         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 854         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
 855         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 856         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0),
 857         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 858         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
 859         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 860         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0),
 861         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 862         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
 863         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 864         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4),
 865         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 866         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
 867         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 868         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4),
 869         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 870         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
 871         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 872         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0),
 873         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 874         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
 875         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 876         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0),
 877         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 878         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
 879         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 880         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4),
 881         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 882         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
 883         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 884         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4),
 885         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 886         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
 887         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 888         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8),
 889         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 890         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
 891         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 892         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8),
 893         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 894         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
 895         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 896         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc),
 897         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 898         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
 899         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 900         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc),
 901         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 902         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
 903         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 904         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe8),
 905         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 906         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 907         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 908         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe8),
 909         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 910         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 911         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 912         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xec),
 913         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 914         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
 915         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 916         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xec),
 917         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 918         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
 919         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 920         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf0),
 921         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 922         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
 923         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 924         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf0),
 925         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 926         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
 927         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 928         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf4),
 929         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 930         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
 931         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 932         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf4),
 933         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 934         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
 935         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 936         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf8),
 937         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 938         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 939         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 940         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf8),
 941         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 942         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 943         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 944         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xfc),
 945         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 946         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
 947         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 948         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xfc),
 949         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 950         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
 951         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 952         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x100),
 953         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 954         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 955         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 956         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x100),
 957         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 958         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 959         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 960         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x104),
 961         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 962         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
 963         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 964         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x104),
 965         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 966         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
 967         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 968         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe0),
 969         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 970         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
 971         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 972         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe0),
 973         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 974         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
 975         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 976         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x118),
 977         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 978         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
 979         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 980         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x118),
 981         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 982         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
 983         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 984         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x11c),
 985         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 986         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
 987         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 988         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x11c),
 989         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 990         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
 991         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 992         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x120),
 993         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 994         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
 995         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 996         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x120),
 997         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 998         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
 999         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1000         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x124),
1001         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1002         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
1003         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1004         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x124),
1005         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1006         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
1007         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1008         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xdc),
1009         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1010         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
1011         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1012         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xdc),
1013         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1014         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
1015         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1016         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x110),
1017         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1018         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
1019         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1020         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x110),
1021         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1022         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
1023         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1024         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x114),
1025         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1026         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
1027         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1028         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x114),
1029         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1030         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
1031         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1032         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x108),
1033         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1034         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1035         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1036         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x108),
1037         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1038         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1039         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1040         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10c),
1041         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1042         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1043         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1044         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10c),
1045         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1046         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1047         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1048         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd8),
1049         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1050         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17),
1051         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1052         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd8),
1053         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1054         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17),
1055         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1056         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x128),
1057         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1058         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
1059         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1060         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x128),
1061         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1062         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
1063         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1064         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x12c),
1065         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1066         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1067         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1068         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x12c),
1069         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1070         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1071         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1072         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x138),
1073         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1074         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1075         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1076         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x138),
1077         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1078         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1079         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1080         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x13c),
1081         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1082         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
1083         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1084         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x13c),
1085         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1086         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
1087         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1088         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x130),
1089         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1090         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1091         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1092         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x130),
1093         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1094         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1095         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1096         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x134),
1097         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1098         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1099         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1100         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x134),
1101         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1102         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1103         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1104         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x140),
1105         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1106         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1107         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1108         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x140),
1109         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1110         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1111         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1112         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x144),
1113         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1114         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
1115         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1116         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x144),
1117         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1118         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
1119         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1120         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x150),
1121         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1122         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1123         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1124         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x150),
1125         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1126         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1127         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1128         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x154),
1129         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1130         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
1131         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1132         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x154),
1133         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1134         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
1135         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1136         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x148),
1137         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1138         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1139         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1140         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x148),
1141         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1142         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1143         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1144         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14c),
1145         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1146         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
1147         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1148         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14c),
1149         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1150         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
1151         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1152         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x158),
1153         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1154         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
1155         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1156         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x158),
1157         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1158         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
1159         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1160         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x15c),
1161         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1162         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1163         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1164         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x15c),
1165         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1166         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1167         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1168         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x168),
1169         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1170         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1),
1171         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1172         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x168),
1173         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1174         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1),
1175         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1176         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x16c),
1177         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1178         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
1179         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1180         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x16c),
1181         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1182         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
1183         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1184         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x160),
1185         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1186         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
1187         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1188         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x160),
1189         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1190         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
1191         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1192         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x164),
1193         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1194         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1195         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1196         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x164),
1197         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1198         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1199         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1200         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x170),
1201         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1202         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
1203         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1204         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x170),
1205         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1206         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
1207         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1208         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x174),
1209         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1210         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
1211         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1212         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x174),
1213         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1214         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
1215         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1216         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x180),
1217         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1218         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
1219         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1220         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x180),
1221         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1222         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
1223         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1224         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x184),
1225         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1226         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1227         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1228         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x184),
1229         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1230         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1231         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1232         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x178),
1233         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1234         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
1235         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1236         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x178),
1237         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1238         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
1239         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1240         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x17c),
1241         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1242         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
1243         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1244         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x17c),
1245         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1246         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
1247         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1248         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x188),
1249         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1250         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1251         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1252         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x188),
1253         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1254         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1255         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1256         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18c),
1257         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1258         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
1259         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1260         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18c),
1261         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1262         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
1263         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1264         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x198),
1265         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1266         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
1267         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1268         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x198),
1269         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1270         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
1271         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1272         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x19c),
1273         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1274         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
1275         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1276         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x19c),
1277         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1278         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
1279         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1280         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x190),
1281         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1282         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1283         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1284         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x190),
1285         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1286         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1287         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1288         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x194),
1289         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1290         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
1291         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1292         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x194),
1293         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1294         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
1295         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1296         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30),
1297         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1298         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
1299         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1300         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34),
1301         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1302         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
1303         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1304         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0),
1305         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1306         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d),
1307         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1308         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0),
1309         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1310         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d),
1311         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1312         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4),
1313         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1314         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1f),
1315         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1316         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4),
1317         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1318         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1f),
1319         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1320         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c),
1321         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1322         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
1323         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1324         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLOBALS_SAMPLE_SKEW, 0x000000FF, 0x19),
1325         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1326         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLOBALS_MUXSEL_SKEW, 0x000000FF, 0x20),
1327         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1328         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLE_SKEW, 0x000000FF, 0x5),
1329         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1330         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLE_SKEW, 0x000000FF, 0xa),
1331         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1332         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_MUXSEL_SKEW, 0x000000FF, 0x14),
1333         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1334         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_MUXSEL_SKEW, 0x000000FF, 0x19),
1335         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1336         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_DESER_START_SKEW, 0x000000FF, 0x33),
1337         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xFFFFFFFF, 0xe0000000)
1338 };
1339
1340 static const struct soc15_reg_golden golden_settings_gc_10_1_1[] =
1341 {
1342         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_4, 0xffffffff, 0x003c0014),
1343         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_GS_NGG_CLK_CTRL, 0xffff8fff, 0xffff8100),
1344         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_IA_CLK_CTRL, 0xffff0fff, 0xffff0100),
1345         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CLK_CTRL, 0xcd000000, 0x0d000100),
1346         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQ_CLK_CTRL, 0xf8ff0fff, 0x60000100),
1347         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQG_CLK_CTRL, 0x40000ff0, 0x40000100),
1348         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_VGT_CLK_CTRL, 0xffff8fff, 0xffff8100),
1349         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_WD_CLK_CTRL, 0xffff8fff, 0xffff8100),
1350         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0xffffffff, 0xe4e4e4e4),
1351         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_VC5_ENABLE, 0x00000002, 0x00000000),
1352         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_SD_CNTL, 0x800007ff, 0x000005ff),
1353         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG, 0xffffffff, 0x20000000),
1354         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG2, 0xffffffff, 0x00000420),
1355         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0x00000200, 0x00000200),
1356         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x04900000),
1357         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DFSM_TILES_IN_FLIGHT, 0x0000ffff, 0x0000003f),
1358         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_LAST_OF_BURST_CONFIG, 0xffffffff, 0x03860204),
1359         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL, 0x1ff0ffff, 0x00000500),
1360         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PRIV_CONTROL, 0x000007ff, 0x000001fe),
1361         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0xffffffff, 0xe4e4e4e4),
1362         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffe7),
1363         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffe7),
1364         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CGTT_SCLK_CTRL, 0xffff0fff, 0x10000100),
1365         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL2, 0xffffffff, 0x1402002f),
1366         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xffffbfff, 0x00000188),
1367         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800),
1368         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE, 0x3fffffff, 0x08000009),
1369         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_1, 0x00400000, 0x04440000),
1370         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0x00000800, 0x00000820),
1371         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000),
1372         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRMI_SPARE, 0xffffffff, 0xffff3101),
1373         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1, 0x001f0000, 0x00070105),
1374         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ALU_CLK_CTRL, 0xffffffff, 0xffffffff),
1375         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ARB_CONFIG, 0x00000133, 0x00000130),
1376         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_LDS_CLK_CTRL, 0xffffffff, 0xffffffff),
1377         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000),
1378         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CNTL, 0x60000010, 0x479c0010),
1379         SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0x00c00000, 0x00c00000),
1380 };
1381
1382 static const struct soc15_reg_golden golden_settings_gc_10_1_2[] =
1383 {
1384         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_4, 0x003e001f, 0x003c0014),
1385         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_GS_NGG_CLK_CTRL, 0xffff8fff, 0xffff8100),
1386         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_IA_CLK_CTRL, 0xffff0fff, 0xffff0100),
1387         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CLK_CTRL, 0xff7f0fff, 0x0d000100),
1388         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQ_CLK_CTRL, 0xffffcfff, 0x60000100),
1389         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQG_CLK_CTRL, 0xffff0fff, 0x40000100),
1390         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_VGT_CLK_CTRL, 0xffff8fff, 0xffff8100),
1391         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_WD_CLK_CTRL, 0xffff8fff, 0xffff8100),
1392         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0xffffffff, 0xe4e4e4e4),
1393         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_VC5_ENABLE, 0x00000003, 0x00000000),
1394         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_SD_CNTL, 0x800007ff, 0x000005ff),
1395         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG, 0xffffffff, 0x20000000),
1396         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG2, 0xffffffff, 0x00000420),
1397         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000200),
1398         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x04800000),
1399         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DFSM_TILES_IN_FLIGHT, 0x0000ffff, 0x0000003f),
1400         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_LAST_OF_BURST_CONFIG, 0xffffffff, 0x03860204),
1401         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL, 0x1ff0ffff, 0x00000500),
1402         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PRIV_CONTROL, 0x00007fff, 0x000001fe),
1403         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0xffffffff, 0xe4e4e4e4),
1404         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_0, 0x77777777, 0x10321032),
1405         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_1, 0x77777777, 0x02310231),
1406         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
1407         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
1408         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CGTT_SCLK_CTRL, 0xffff0fff, 0x10000100),
1409         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL2, 0xffffffff, 0x1402002f),
1410         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xffffbfff, 0x00000188),
1411         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_EVENT_CNTL_0, 0xffffffff, 0x842a4c02),
1412         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800),
1413         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE, 0x3fffffff, 0x08000009),
1414         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_1, 0xffffffff, 0x04440000),
1415         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0x00000820, 0x00000820),
1416         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000),
1417         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRMI_SPARE, 0xffffffff, 0xffff3101),
1418         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ALU_CLK_CTRL, 0xffffffff, 0xffffffff),
1419         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ARB_CONFIG, 0x00000133, 0x00000130),
1420         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_LDS_CLK_CTRL, 0xffffffff, 0xffffffff),
1421         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000),
1422         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CNTL, 0xffdf80ff, 0x479c0010),
1423         SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffffffff, 0x00800000)
1424 };
1425
1426 static bool gfx_v10_is_rlcg_rw(struct amdgpu_device *adev, u32 offset, uint32_t *flag, bool write)
1427 {
1428         /* always programed by rlcg, only for gc */
1429         if (offset == SOC15_REG_OFFSET(GC, 0, mmRLC_CSIB_ADDR_HI) ||
1430             offset == SOC15_REG_OFFSET(GC, 0, mmRLC_CSIB_ADDR_LO) ||
1431             offset == SOC15_REG_OFFSET(GC, 0, mmRLC_CSIB_LENGTH) ||
1432             offset == SOC15_REG_OFFSET(GC, 0, mmGRBM_GFX_CNTL) ||
1433             offset == SOC15_REG_OFFSET(GC, 0, mmGRBM_GFX_INDEX) ||
1434             offset == SOC15_REG_OFFSET(GC, 0, mmCP_ME_CNTL)) {
1435                 if (!amdgpu_sriov_reg_indirect_gc(adev))
1436                         *flag = GFX_RLCG_GC_WRITE_OLD;
1437                 else
1438                         *flag = write ? GFX_RLCG_GC_WRITE : GFX_RLCG_GC_READ;
1439
1440                 return true;
1441         }
1442
1443         /* currently support gc read/write, mmhub write */
1444         if (offset >= SOC15_REG_OFFSET(GC, 0, mmSDMA0_DEC_START) &&
1445             offset <= SOC15_REG_OFFSET(GC, 0, mmRLC_GTS_OFFSET_MSB)) {
1446                 if (amdgpu_sriov_reg_indirect_gc(adev))
1447                         *flag = write ? GFX_RLCG_GC_WRITE : GFX_RLCG_GC_READ;
1448                 else
1449                         return false;
1450         } else {
1451                 if (amdgpu_sriov_reg_indirect_mmhub(adev))
1452                         *flag = GFX_RLCG_MMHUB_WRITE;
1453                 else
1454                         return false;
1455         }
1456
1457         return true;
1458 }
1459
1460 static u32 gfx_v10_rlcg_rw(struct amdgpu_device *adev, u32 offset, u32 v, uint32_t flag)
1461 {
1462         static void *scratch_reg0;
1463         static void *scratch_reg1;
1464         static void *scratch_reg2;
1465         static void *scratch_reg3;
1466         static void *spare_int;
1467         static uint32_t grbm_cntl;
1468         static uint32_t grbm_idx;
1469         uint32_t i = 0;
1470         uint32_t retries = 50000;
1471         u32 ret = 0;
1472
1473         scratch_reg0 = adev->rmmio +
1474                        (adev->reg_offset[GC_HWIP][0][mmSCRATCH_REG0_BASE_IDX] + mmSCRATCH_REG0) * 4;
1475         scratch_reg1 = adev->rmmio +
1476                        (adev->reg_offset[GC_HWIP][0][mmSCRATCH_REG1_BASE_IDX] + mmSCRATCH_REG1) * 4;
1477         scratch_reg2 = adev->rmmio +
1478                        (adev->reg_offset[GC_HWIP][0][mmSCRATCH_REG0_BASE_IDX] + mmSCRATCH_REG2) * 4;
1479         scratch_reg3 = adev->rmmio +
1480                        (adev->reg_offset[GC_HWIP][0][mmSCRATCH_REG1_BASE_IDX] + mmSCRATCH_REG3) * 4;
1481         spare_int = adev->rmmio +
1482                     (adev->reg_offset[GC_HWIP][0][mmRLC_SPARE_INT_BASE_IDX] + mmRLC_SPARE_INT) * 4;
1483
1484         grbm_cntl = adev->reg_offset[GC_HWIP][0][mmGRBM_GFX_CNTL_BASE_IDX] + mmGRBM_GFX_CNTL;
1485         grbm_idx = adev->reg_offset[GC_HWIP][0][mmGRBM_GFX_INDEX_BASE_IDX] + mmGRBM_GFX_INDEX;
1486
1487         if (offset == grbm_cntl || offset == grbm_idx) {
1488                 if (offset  == grbm_cntl)
1489                         writel(v, scratch_reg2);
1490                 else if (offset == grbm_idx)
1491                         writel(v, scratch_reg3);
1492
1493                 writel(v, ((void __iomem *)adev->rmmio) + (offset * 4));
1494         } else {
1495                 writel(v, scratch_reg0);
1496                 writel(offset | flag, scratch_reg1);
1497                 writel(1, spare_int);
1498                 for (i = 0; i < retries; i++) {
1499                         u32 tmp;
1500
1501                         tmp = readl(scratch_reg1);
1502                         if (!(tmp & flag))
1503                                 break;
1504
1505                         udelay(10);
1506                 }
1507
1508                 if (i >= retries)
1509                         pr_err("timeout: rlcg program reg:0x%05x failed !\n", offset);
1510         }
1511
1512         ret = readl(scratch_reg0);
1513
1514         return ret;
1515 }
1516
1517 static void gfx_v10_rlcg_wreg(struct amdgpu_device *adev, u32 offset, u32 value, u32 flag)
1518 {
1519         uint32_t rlcg_flag;
1520
1521         if (amdgpu_sriov_fullaccess(adev) &&
1522             gfx_v10_is_rlcg_rw(adev, offset, &rlcg_flag, 1)) {
1523                 gfx_v10_rlcg_rw(adev, offset, value, rlcg_flag);
1524
1525                 return;
1526         }
1527         if (flag & AMDGPU_REGS_NO_KIQ)
1528                 WREG32_NO_KIQ(offset, value);
1529         else
1530                 WREG32(offset, value);
1531 }
1532
1533 static u32 gfx_v10_rlcg_rreg(struct amdgpu_device *adev, u32 offset, u32 flag)
1534 {
1535         uint32_t rlcg_flag;
1536
1537         if (amdgpu_sriov_fullaccess(adev) &&
1538             gfx_v10_is_rlcg_rw(adev, offset, &rlcg_flag, 0))
1539                 return gfx_v10_rlcg_rw(adev, offset, 0, rlcg_flag);
1540
1541         if (flag & AMDGPU_REGS_NO_KIQ)
1542                 return RREG32_NO_KIQ(offset);
1543         else
1544                 return RREG32(offset);
1545
1546         return 0;
1547 }
1548
1549 static const struct soc15_reg_golden golden_settings_gc_10_1_nv14[] =
1550 {
1551         /* Pending on emulation bring up */
1552 };
1553
1554 static const struct soc15_reg_golden golden_settings_gc_rlc_spm_10_1_nv14[] =
1555 {
1556         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xE0000000L, 0x0),
1557         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1558         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28),
1559         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1560         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1561         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1562         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8),
1563         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1564         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c),
1565         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1566         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20),
1567         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1568         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
1569         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1570         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80),
1571         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1572         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1573         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1574         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84),
1575         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1576         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1577         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1578         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88),
1579         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1580         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1581         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1582         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c),
1583         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1584         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1585         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1586         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
1587         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1588         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1589         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1590         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
1591         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1592         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1593         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1594         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4),
1595         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1596         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1597         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1598         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8),
1599         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1600         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
1601         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1602         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0),
1603         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1604         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1605         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1606         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc),
1607         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1608         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x20),
1609         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1610         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60),
1611         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1612         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
1613         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1614         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64),
1615         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1616         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1617         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1618         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68),
1619         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1620         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1621         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1622         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c),
1623         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1624         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1625         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1626         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70),
1627         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1628         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1629         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1630         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74),
1631         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1632         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1633         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1634         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78),
1635         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1636         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
1637         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1638         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c),
1639         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1640         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1641         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1642         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10),
1643         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1644         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1645         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1646         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc),
1647         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1648         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
1649         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1650         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18),
1651         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1652         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1653         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1654         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38),
1655         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1656         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
1657         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1658         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c),
1659         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1660         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
1661         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1662         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40),
1663         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1664         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
1665         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1666         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44),
1667         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1668         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
1669         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1670         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48),
1671         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1672         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
1673         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1674         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c),
1675         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1676         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
1677         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1678         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50),
1679         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1680         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
1681         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1682         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54),
1683         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1684         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
1685         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1686         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58),
1687         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1688         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
1689         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1690         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c),
1691         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1692         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
1693         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1694         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1c),
1695         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1696         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1697         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1698         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14),
1699         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1700         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
1701         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1702         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20),
1703         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1704         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
1705         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1706         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
1707         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1708         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
1709         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1710         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28),
1711         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1712         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1713         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1714         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c),
1715         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1716         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
1717         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1718         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30),
1719         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1720         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
1721         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1722         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34),
1723         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1724         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1725         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1726         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38),
1727         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1728         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
1729         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1730         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c),
1731         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1732         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c),
1733         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1734         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18),
1735         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1736         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
1737         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1738         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50),
1739         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1740         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1e),
1741         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1742         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54),
1743         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1744         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1e),
1745         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1746         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58),
1747         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1748         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1e),
1749         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1750         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c),
1751         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1752         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1e),
1753         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1754         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14),
1755         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1756         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x20),
1757         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1758         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48),
1759         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1760         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
1761         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1762         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c),
1763         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1764         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
1765         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1766         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40),
1767         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1768         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1e),
1769         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1770         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44),
1771         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1772         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1e),
1773         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1774         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10),
1775         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1776         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
1777         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1778         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60),
1779         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1780         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
1781         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1782         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64),
1783         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1784         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1785         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1786         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70),
1787         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1788         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
1789         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1790         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74),
1791         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1792         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
1793         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1794         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68),
1795         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1796         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
1797         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1798         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c),
1799         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1800         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1801         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1802         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78),
1803         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1804         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1805         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1806         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c),
1807         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1808         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1809         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1810         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88),
1811         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1812         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
1813         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1814         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c),
1815         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1816         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1817         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1818         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80),
1819         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1820         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1821         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1822         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84),
1823         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1824         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1825         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1826         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90),
1827         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1828         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1829         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1830         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94),
1831         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1832         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
1833         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1834         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0),
1835         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1836         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1837         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1838         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4),
1839         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1840         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
1841         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1842         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98),
1843         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1844         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1845         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1846         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c),
1847         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1848         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
1849         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1850         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8),
1851         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1852         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c),
1853         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1854         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac),
1855         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1856         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1857         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1858         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8),
1859         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1860         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1861         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1862         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc),
1863         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1864         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1865         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1866         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0),
1867         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1868         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c),
1869         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1870         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4),
1871         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1872         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1873         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1874         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0),
1875         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1876         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
1877         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1878         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4),
1879         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1880         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1881         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1882         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0),
1883         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1884         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
1885         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1886         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4),
1887         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1888         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
1889         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1890         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8),
1891         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1892         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
1893         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1894         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc),
1895         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1896         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1897         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1898         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd8),
1899         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1900         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1901         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1902         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xdc),
1903         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1904         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1905         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1906         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe8),
1907         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1908         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1909         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1910         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xec),
1911         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1912         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1913         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1914         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe0),
1915         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1916         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1917         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1918         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe4),
1919         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1920         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1921         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1922         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x100),
1923         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1924         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
1925         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1926         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x104),
1927         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1928         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1929         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1930         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x108),
1931         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1932         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1933         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1934         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10c),
1935         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1936         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
1937         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1938         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x110),
1939         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1940         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1941         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1942         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x114),
1943         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1944         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1945         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1946         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x118),
1947         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1948         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
1949         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1950         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x11c),
1951         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1952         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
1953         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1954         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf8),
1955         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1956         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17),
1957         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1958         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x130),
1959         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1960         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1961         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1962         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x134),
1963         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1964         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1965         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1966         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x138),
1967         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1968         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1969         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1970         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x13c),
1971         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1972         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1973         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1974         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf4),
1975         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1976         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x20),
1977         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1978         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x128),
1979         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1980         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1981         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1982         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x12c),
1983         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1984         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1985         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1986         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x120),
1987         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1988         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1989         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1990         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x124),
1991         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1992         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1993         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1994         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf0),
1995         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1996         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
1997         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1998         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x140),
1999         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2000         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2001         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2002         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x144),
2003         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2004         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
2005         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2006         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x150),
2007         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2008         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2009         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2010         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x154),
2011         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2012         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2013         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2014         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x148),
2015         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2016         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2017         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2018         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14c),
2019         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2020         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
2021         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2022         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x158),
2023         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2024         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
2025         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2026         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x15c),
2027         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2028         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2029         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2030         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x168),
2031         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2032         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2033         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2034         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x16c),
2035         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2036         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
2037         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2038         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x160),
2039         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2040         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
2041         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2042         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x164),
2043         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2044         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2045         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2046         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x170),
2047         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2048         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
2049         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2050         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x174),
2051         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2052         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
2053         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2054         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x180),
2055         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2056         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
2057         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2058         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x184),
2059         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2060         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
2061         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2062         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x178),
2063         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2064         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
2065         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2066         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x17c),
2067         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2068         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
2069         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2070         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x188),
2071         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2072         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
2073         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2074         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18c),
2075         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2076         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2077         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2078         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x198),
2079         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2080         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2081         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2082         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x19c),
2083         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2084         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2085         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2086         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x190),
2087         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2088         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
2089         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2090         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x194),
2091         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2092         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2093         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2094         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1a0),
2095         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2096         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2097         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2098         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1a4),
2099         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2100         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
2101         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2102         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1b0),
2103         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2104         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2105         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2106         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1b4),
2107         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2108         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2109         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2110         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1a8),
2111         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2112         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2113         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2114         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1ac),
2115         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2116         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
2117         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2118         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1b8),
2119         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2120         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
2121         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2122         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1bc),
2123         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2124         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2125         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2126         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1c8),
2127         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2128         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
2129         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2130         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1cc),
2131         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2132         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
2133         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2134         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1c0),
2135         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2136         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
2137         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2138         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1c4),
2139         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2140         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2141         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2142         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30),
2143         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2144         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2145         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2146         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34),
2147         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2148         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2149         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2150         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0),
2151         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2152         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x20),
2153         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2154         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4),
2155         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2156         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x20),
2157         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2158         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c),
2159         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2160         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
2161         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2162         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLOBALS_SAMPLE_SKEW, 0x000000FF, 0x26),
2163         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2164         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLOBALS_MUXSEL_SKEW, 0x000000FF, 0x28),
2165         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2166         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLE_SKEW, 0x000000FF, 0xf),
2167         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2168         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLE_SKEW, 0x000000FF, 0x15),
2169         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2170         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_MUXSEL_SKEW, 0x000000FF, 0x1f),
2171         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2172         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_MUXSEL_SKEW, 0x000000FF, 0x25),
2173         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2174         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_DESER_START_SKEW, 0x000000FF, 0x3b),
2175         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xFFFFFFFF, 0xe0000000)
2176 };
2177
2178 static const struct soc15_reg_golden golden_settings_gc_10_1_2_nv12[] =
2179 {
2180         /* Pending on emulation bring up */
2181 };
2182
2183 static const struct soc15_reg_golden golden_settings_gc_rlc_spm_10_1_2_nv12[] =
2184 {
2185         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xe0000000L, 0x0),
2186         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2187         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28),
2188         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2189         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
2190         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2191         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8),
2192         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2193         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
2194         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2195         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8),
2196         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2197         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
2198         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2199         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20),
2200         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2201         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
2202         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2203         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8),
2204         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2205         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2206         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2207         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc),
2208         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2209         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2210         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2211         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0),
2212         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2213         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2214         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2215         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4),
2216         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2217         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2218         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2219         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
2220         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2221         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2222         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2223         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
2224         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2225         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2226         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2227         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4),
2228         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2229         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
2230         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2231         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8),
2232         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2233         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
2234         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2235         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0),
2236         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2237         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2238         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2239         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc),
2240         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2241         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2242         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2243         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc),
2244         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2245         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2246         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2247         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88),
2248         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2249         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
2250         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2251         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c),
2252         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2253         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
2254         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2255         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0),
2256         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2257         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
2258         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2259         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4),
2260         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2261         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
2262         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2263         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8),
2264         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2265         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2266         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2267         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc),
2268         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2269         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2270         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2271         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0),
2272         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2273         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
2274         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2275         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4),
2276         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2277         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2278         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2279         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90),
2280         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2281         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
2282         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2283         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94),
2284         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2285         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1),
2286         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2287         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98),
2288         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2289         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
2290         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2291         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c),
2292         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2293         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
2294         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2295         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0),
2296         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2297         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1),
2298         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2299         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4),
2300         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2301         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2302         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2303         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8),
2304         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2305         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2306         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2307         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac),
2308         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2309         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2310         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2311         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10),
2312         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2313         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
2314         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2315         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc),
2316         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2317         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2318         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2319         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18),
2320         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2321         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
2322         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2323         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38),
2324         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2325         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
2326         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2327         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c),
2328         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2329         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
2330         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2331         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40),
2332         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2333         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2334         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2335         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44),
2336         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2337         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
2338         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2339         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48),
2340         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2341         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
2342         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2343         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c),
2344         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2345         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
2346         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2347         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70),
2348         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2349         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
2350         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2351         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74),
2352         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2353         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
2354         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2355         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78),
2356         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2357         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
2358         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2359         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c),
2360         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2361         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
2362         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2363         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80),
2364         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2365         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
2366         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2367         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84),
2368         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2369         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2370         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2371         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50),
2372         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2373         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2374         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2375         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54),
2376         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2377         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
2378         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2379         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58),
2380         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2381         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
2382         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2383         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c),
2384         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2385         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
2386         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2387         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60),
2388         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2389         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2390         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2391         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64),
2392         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2393         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
2394         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2395         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68),
2396         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2397         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
2398         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2399         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c),
2400         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2401         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
2402         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2403         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1c),
2404         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2405         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
2406         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2407         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14),
2408         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2409         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
2410         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2411         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20),
2412         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2413         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c),
2414         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2415         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20),
2416         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2417         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c),
2418         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2419         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
2420         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2421         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2422         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2423         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
2424         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2425         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2426         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2427         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28),
2428         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2429         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2430         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2431         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28),
2432         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2433         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2434         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2435         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c),
2436         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2437         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
2438         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2439         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c),
2440         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2441         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
2442         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2443         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30),
2444         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2445         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d),
2446         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2447         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30),
2448         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2449         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d),
2450         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2451         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34),
2452         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2453         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
2454         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2455         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34),
2456         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2457         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
2458         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2459         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38),
2460         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2461         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
2462         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2463         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38),
2464         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2465         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
2466         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2467         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c),
2468         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2469         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2470         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2471         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c),
2472         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2473         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2474         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2475         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18),
2476         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2477         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
2478         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2479         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18),
2480         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2481         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
2482         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2483         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50),
2484         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2485         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2486         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2487         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50),
2488         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2489         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2490         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2491         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54),
2492         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2493         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2494         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2495         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54),
2496         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2497         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2498         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2499         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58),
2500         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2501         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2502         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2503         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58),
2504         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2505         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2506         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2507         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c),
2508         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2509         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2510         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2511         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c),
2512         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2513         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2514         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2515         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14),
2516         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2517         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
2518         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2519         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14),
2520         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2521         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
2522         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2523         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48),
2524         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2525         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2526         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2527         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48),
2528         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2529         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2530         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2531         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c),
2532         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2533         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2534         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2535         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c),
2536         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2537         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2538         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2539         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40),
2540         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2541         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
2542         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2543         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40),
2544         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2545         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
2546         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2547         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44),
2548         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2549         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
2550         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2551         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44),
2552         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2553         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
2554         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2555         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10),
2556         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2557         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
2558         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2559         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10),
2560         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2561         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
2562         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2563         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60),
2564         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2565         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2566         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2567         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60),
2568         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2569         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2570         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2571         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64),
2572         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2573         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
2574         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2575         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64),
2576         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2577         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
2578         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2579         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70),
2580         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2581         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
2582         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2583         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70),
2584         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2585         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
2586         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2587         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74),
2588         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2589         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2590         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2591         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74),
2592         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2593         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2594         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2595         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68),
2596         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2597         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2598         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2599         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68),
2600         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2601         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2602         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2603         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c),
2604         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2605         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
2606         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2607         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c),
2608         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2609         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
2610         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2611         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78),
2612         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2613         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2614         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2615         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78),
2616         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2617         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2618         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2619         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c),
2620         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2621         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
2622         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2623         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c),
2624         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2625         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
2626         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2627         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88),
2628         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2629         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2630         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2631         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88),
2632         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2633         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2634         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2635         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c),
2636         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2637         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2638         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2639         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c),
2640         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2641         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2642         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2643         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80),
2644         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2645         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2646         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2647         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80),
2648         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2649         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2650         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2651         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84),
2652         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2653         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
2654         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2655         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84),
2656         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2657         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
2658         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2659         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90),
2660         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2661         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
2662         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2663         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90),
2664         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2665         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
2666         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2667         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94),
2668         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2669         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
2670         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2671         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94),
2672         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2673         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
2674         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2675         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0),
2676         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2677         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2678         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2679         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0),
2680         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2681         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2682         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2683         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4),
2684         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2685         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2686         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2687         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4),
2688         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2689         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2690         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2691         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98),
2692         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2693         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
2694         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2695         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98),
2696         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2697         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
2698         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2699         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c),
2700         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2701         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
2702         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2703         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c),
2704         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2705         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
2706         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2707         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8),
2708         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2709         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2710         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2711         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8),
2712         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2713         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2714         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2715         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac),
2716         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2717         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2718         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2719         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac),
2720         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2721         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2722         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2723         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8),
2724         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2725         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2726         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2727         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8),
2728         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2729         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2730         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2731         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc),
2732         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2733         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2734         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2735         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc),
2736         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2737         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2738         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2739         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0),
2740         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2741         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2742         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2743         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0),
2744         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2745         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2746         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2747         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4),
2748         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2749         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2750         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2751         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4),
2752         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2753         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2754         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2755         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0),
2756         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2757         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
2758         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2759         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0),
2760         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2761         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
2762         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2763         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4),
2764         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2765         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
2766         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2767         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4),
2768         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2769         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
2770         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2771         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0),
2772         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2773         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2774         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2775         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0),
2776         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2777         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2778         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2779         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4),
2780         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2781         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2782         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2783         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4),
2784         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2785         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2786         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2787         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8),
2788         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2789         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
2790         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2791         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8),
2792         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2793         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
2794         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2795         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc),
2796         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2797         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
2798         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2799         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc),
2800         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2801         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
2802         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2803         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe8),
2804         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2805         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2806         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2807         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe8),
2808         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2809         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2810         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2811         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xec),
2812         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2813         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
2814         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2815         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xec),
2816         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2817         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
2818         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2819         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf0),
2820         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2821         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2822         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2823         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf0),
2824         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2825         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2826         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2827         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf4),
2828         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2829         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2830         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2831         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf4),
2832         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2833         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2834         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2835         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf8),
2836         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2837         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2838         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2839         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf8),
2840         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2841         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2842         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2843         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xfc),
2844         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2845         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17),
2846         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2847         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xfc),
2848         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2849         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17),
2850         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2851         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x100),
2852         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2853         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
2854         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2855         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x100),
2856         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2857         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
2858         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2859         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x104),
2860         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2861         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
2862         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2863         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x104),
2864         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2865         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
2866         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2867         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe0),
2868         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2869         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2870         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2871         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe0),
2872         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2873         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2874         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2875         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x118),
2876         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2877         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2878         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2879         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x118),
2880         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2881         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2882         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2883         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x11c),
2884         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2885         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2886         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2887         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x11c),
2888         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2889         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2890         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2891         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x120),
2892         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2893         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2894         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2895         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x120),
2896         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2897         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2898         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2899         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x124),
2900         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2901         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2902         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2903         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x124),
2904         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2905         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2906         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2907         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xdc),
2908         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2909         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2910         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2911         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xdc),
2912         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2913         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2914         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2915         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x110),
2916         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2917         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2918         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2919         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x110),
2920         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2921         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2922         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2923         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x114),
2924         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2925         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2926         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2927         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x114),
2928         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2929         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2930         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2931         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x108),
2932         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2933         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2934         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2935         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x108),
2936         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2937         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2938         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2939         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10c),
2940         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2941         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2942         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2943         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10c),
2944         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2945         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2946         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2947         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd8),
2948         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2949         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
2950         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2951         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd8),
2952         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2953         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
2954         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2955         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x128),
2956         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2957         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2958         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2959         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x128),
2960         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2961         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2962         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2963         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x12c),
2964         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2965         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2966         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2967         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x12c),
2968         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2969         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2970         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2971         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x138),
2972         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2973         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2974         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2975         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x138),
2976         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2977         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2978         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2979         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x13c),
2980         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2981         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2982         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2983         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x13c),
2984         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2985         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2986         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2987         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x130),
2988         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2989         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2990         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2991         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x130),
2992         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2993         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2994         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2995         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x134),
2996         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2997         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
2998         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2999         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x134),
3000         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3001         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
3002         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3003         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x140),
3004         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3005         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
3006         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3007         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x140),
3008         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3009         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
3010         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3011         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x144),
3012         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3013         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
3014         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3015         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x144),
3016         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3017         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
3018         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3019         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x150),
3020         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3021         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
3022         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3023         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x150),
3024         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3025         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
3026         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3027         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x154),
3028         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3029         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
3030         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3031         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x154),
3032         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3033         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
3034         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3035         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x148),
3036         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3037         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
3038         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3039         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x148),
3040         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3041         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
3042         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3043         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14c),
3044         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3045         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
3046         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3047         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14c),
3048         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3049         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
3050         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3051         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x158),
3052         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3053         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
3054         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3055         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x158),
3056         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3057         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
3058         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3059         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x15c),
3060         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3061         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
3062         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3063         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x15c),
3064         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3065         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
3066         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3067         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x168),
3068         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3069         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
3070         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3071         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x168),
3072         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3073         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
3074         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3075         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x16c),
3076         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3077         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
3078         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3079         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x16c),
3080         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3081         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
3082         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3083         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x160),
3084         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3085         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
3086         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3087         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x160),
3088         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3089         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
3090         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3091         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x164),
3092         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3093         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
3094         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3095         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x164),
3096         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3097         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
3098         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3099         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x170),
3100         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3101         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
3102         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3103         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x170),
3104         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3105         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
3106         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3107         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x174),
3108         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3109         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
3110         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3111         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x174),
3112         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3113         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
3114         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3115         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x180),
3116         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3117         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
3118         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3119         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x180),
3120         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3121         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
3122         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3123         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x184),
3124         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3125         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
3126         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3127         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x184),
3128         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3129         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
3130         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3131         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x178),
3132         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3133         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
3134         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3135         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x178),
3136         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3137         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
3138         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3139         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x17c),
3140         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3141         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
3142         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3143         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x17c),
3144         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3145         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
3146         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3147         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x188),
3148         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3149         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
3150         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3151         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x188),
3152         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3153         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
3154         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3155         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18c),
3156         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3157         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
3158         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3159         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18c),
3160         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3161         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
3162         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3163         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x198),
3164         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3165         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
3166         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3167         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x198),
3168         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3169         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
3170         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3171         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x19c),
3172         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3173         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
3174         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3175         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x19c),
3176         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3177         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
3178         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3179         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x190),
3180         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3181         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
3182         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3183         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x190),
3184         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3185         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
3186         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3187         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x194),
3188         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3189         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
3190         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3191         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x194),
3192         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3193         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
3194         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3195         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30),
3196         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3197         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
3198         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3199         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34),
3200         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3201         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
3202         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3203         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0),
3204         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3205         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d),
3206         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3207         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0),
3208         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3209         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d),
3210         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3211         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4),
3212         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3213         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1f),
3214         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3215         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4),
3216         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3217         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1f),
3218         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3219         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c),
3220         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3221         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
3222         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3223         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLOBALS_SAMPLE_SKEW, 0x000000FF, 0x1f),
3224         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3225         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLOBALS_MUXSEL_SKEW, 0x000000FF, 0x22),
3226         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3227         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLE_SKEW, 0x000000FF, 0x1),
3228         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3229         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLE_SKEW, 0x000000FF, 0x6),
3230         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3231         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_MUXSEL_SKEW, 0x000000FF, 0x10),
3232         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3233         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_MUXSEL_SKEW, 0x000000FF, 0x15),
3234         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3235         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_DESER_START_SKEW, 0x000000FF, 0x35),
3236         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xFFFFFFFF, 0xe0000000)
3237 };
3238
3239 static const struct soc15_reg_golden golden_settings_gc_10_3[] =
3240 {
3241         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CS_CLK_CTRL, 0x78000000, 0x78000100),
3242         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_PS_CLK_CTRL, 0xff7f0fff, 0x78000100),
3243         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA0_CLK_CTRL, 0xff7f0fff, 0x30000100),
3244         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA1_CLK_CTRL, 0xff7f0fff, 0x7e000100),
3245         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_GCR_CNTL, 0x0007ffff, 0x0000c000),
3246         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000280),
3247         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x00800000),
3248         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_EXCEPTION_CONTROL, 0x7fff0f1f, 0x00b80000),
3249         SOC15_REG_GOLDEN_VALUE(GC, 0 ,mmGCEA_SDP_TAG_RESERVE0, 0xffffffff, 0x10100100),
3250         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCEA_SDP_TAG_RESERVE1, 0xffffffff, 0x17000088),
3251         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL_Sienna_Cichlid, 0x1ff1ffff, 0x00000500),
3252         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCUTCL2_CGTT_CLK_CTRL_Sienna_Cichlid, 0xff000000, 0xff008080),
3253         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCVM_L2_CGTT_CLK_CTRL_Sienna_Cichlid, 0xff000000, 0xff008080),
3254         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PC_CNTL, 0x003fffff, 0x00280400),
3255         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
3256         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
3257         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CM_CTRL1, 0xff8fff0f, 0x580f1008),
3258         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xf7ffffff, 0x10f80988),
3259         SOC15_REG_GOLDEN_VALUE(GC, 0, mmLDS_CONFIG,  0x00000020, 0x00000020),
3260         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_CL_ENHANCE, 0xf17fffff, 0x01200007),
3261         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800),
3262         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0xffffffbf, 0x00000820),
3263         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1, 0xffffffff, 0x00070104),
3264         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_CONFIG, 0xe07df47f, 0x00180070),
3265         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER0_SELECT, 0xf0f001ff, 0x00000000),
3266         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER1_SELECT, 0xf0f001ff, 0x00000000),
3267         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER10_SELECT, 0xf0f001ff, 0x00000000),
3268         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER11_SELECT, 0xf0f001ff, 0x00000000),
3269         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER12_SELECT, 0xf0f001ff, 0x00000000),
3270         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER13_SELECT, 0xf0f001ff, 0x00000000),
3271         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER14_SELECT, 0xf0f001ff, 0x00000000),
3272         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER15_SELECT, 0xf0f001ff, 0x00000000),
3273         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER2_SELECT, 0xf0f001ff, 0x00000000),
3274         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER3_SELECT, 0xf0f001ff, 0x00000000),
3275         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER4_SELECT, 0xf0f001ff, 0x00000000),
3276         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER5_SELECT, 0xf0f001ff, 0x00000000),
3277         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER6_SELECT, 0xf0f001ff, 0x00000000),
3278         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER7_SELECT, 0xf0f001ff, 0x00000000),
3279         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER8_SELECT, 0xf0f001ff, 0x00000000),
3280         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER9_SELECT, 0xf0f001ff, 0x00000000),
3281         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000),
3282         SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffbfffff, 0x00a00000)
3283 };
3284
3285 static const struct soc15_reg_golden golden_settings_gc_10_3_sienna_cichlid[] =
3286 {
3287         /* Pending on emulation bring up */
3288 };
3289
3290 static const struct soc15_reg_golden golden_settings_gc_10_3_2[] =
3291 {
3292         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CS_CLK_CTRL, 0xff7f0fff, 0x78000100),
3293         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_PS_CLK_CTRL, 0xff7f0fff, 0x78000100),
3294         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA0_CLK_CTRL, 0xff7f0fff, 0x30000100),
3295         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA1_CLK_CTRL, 0xff7f0fff, 0x7e000100),
3296         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_GCR_CNTL, 0x0007ffff, 0x0000c000),
3297         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000280),
3298         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x00800000),
3299         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_EXCEPTION_CONTROL, 0x7fff0f1f, 0x00b80000),
3300         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL_Sienna_Cichlid, 0x1ff1ffff, 0x00000500),
3301         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCUTCL2_CGTT_CLK_CTRL_Sienna_Cichlid, 0xffffffff, 0xff008080),
3302         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCVM_L2_CGTT_CLK_CTRL_Sienna_Cichlid, 0xffff8fff, 0xff008080),
3303         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PC_CNTL, 0x003fffff, 0x00280400),
3304         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
3305         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
3306         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CM_CTRL1, 0xff8fff0f, 0x580f1008),
3307         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xf7ffffff, 0x00f80988),
3308         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_CL_ENHANCE, 0xf17fffff, 0x01200007),
3309         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800),
3310         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0xffffffbf, 0x00000820),
3311         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1, 0xffffffff, 0x00070104),
3312         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_START_PHASE, 0x000000ff, 0x00000004),
3313         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_CONFIG, 0xe07df47f, 0x00180070),
3314         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER0_SELECT, 0xf0f001ff, 0x00000000),
3315         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER1_SELECT, 0xf0f001ff, 0x00000000),
3316         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER10_SELECT, 0xf0f001ff, 0x00000000),
3317         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER11_SELECT, 0xf0f001ff, 0x00000000),
3318         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER12_SELECT, 0xf0f001ff, 0x00000000),
3319         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER13_SELECT, 0xf0f001ff, 0x00000000),
3320         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER14_SELECT, 0xf0f001ff, 0x00000000),
3321         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER15_SELECT, 0xf0f001ff, 0x00000000),
3322         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER2_SELECT, 0xf0f001ff, 0x00000000),
3323         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER3_SELECT, 0xf0f001ff, 0x00000000),
3324         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER4_SELECT, 0xf0f001ff, 0x00000000),
3325         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER5_SELECT, 0xf0f001ff, 0x00000000),
3326         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER6_SELECT, 0xf0f001ff, 0x00000000),
3327         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER7_SELECT, 0xf0f001ff, 0x00000000),
3328         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER8_SELECT, 0xf0f001ff, 0x00000000),
3329         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER9_SELECT, 0xf0f001ff, 0x00000000),
3330         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000),
3331         SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffbfffff, 0x00a00000),
3332         SOC15_REG_GOLDEN_VALUE(GC, 0, mmVGT_GS_MAX_WAVE_ID, 0x00000fff, 0x000003ff),
3333
3334         /* This is not in GDB yet. Don't remove it. It fixes a GPU hang on Navy Flounder. */
3335         SOC15_REG_GOLDEN_VALUE(GC, 0, mmLDS_CONFIG,  0x00000020, 0x00000020),
3336 };
3337
3338 static const struct soc15_reg_golden golden_settings_gc_10_3_vangogh[] =
3339 {
3340         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA0_CLK_CTRL, 0xff7f0fff, 0x30000100),
3341         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA1_CLK_CTRL, 0xff7f0fff, 0x7e000100),
3342         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0x000000ff, 0x000000e4),
3343         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000200),
3344         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x00800000),
3345         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_EXCEPTION_CONTROL, 0x7fff0f1f, 0x00b80000),
3346         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0x0c1807ff, 0x00000142),
3347         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL_Vangogh, 0x1ff1ffff, 0x00000500),
3348         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0x000000ff, 0x000000e4),
3349         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_0, 0x77777777, 0x32103210),
3350         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_1, 0x77777777, 0x32103210),
3351         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xfffffff3),
3352         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xfffffff3),
3353         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CM_CTRL1, 0xff8fff0f, 0x580f1008),
3354         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xf7ffffff, 0x00f80988),
3355         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_CL_ENHANCE, 0xf17fffff, 0x01200007),
3356         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800),
3357         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0xffffffbf, 0x00000020),
3358         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1_Vangogh, 0xffffffff, 0x00070103),
3359         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQG_CONFIG, 0x000017ff, 0x00001000),
3360         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000),
3361         SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffffffff, 0x00400000),
3362         SOC15_REG_GOLDEN_VALUE(GC, 0, mmVGT_GS_MAX_WAVE_ID, 0x00000fff, 0x000000ff),
3363
3364         /* This is not in GDB yet. Don't remove it. It fixes a GPU hang on VanGogh. */
3365         SOC15_REG_GOLDEN_VALUE(GC, 0, mmLDS_CONFIG,  0x00000020, 0x00000020),
3366 };
3367
3368 static const struct soc15_reg_golden golden_settings_gc_10_3_4[] =
3369 {
3370         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CS_CLK_CTRL, 0x78000000, 0x78000100),
3371         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA0_CLK_CTRL, 0x30000000, 0x30000100),
3372         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA1_CLK_CTRL, 0x7e000000, 0x7e000100),
3373         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_GCR_CNTL, 0x0007ffff, 0x0000c000),
3374         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0x00000280, 0x00000280),
3375         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0x07800000, 0x00800000),
3376         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL_Sienna_Cichlid, 0x00001d00, 0x00000500),
3377         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PC_CNTL, 0x003c0000, 0x00280400),
3378         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
3379         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
3380         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CM_CTRL1, 0x40000000, 0x580f1008),
3381         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0x00040000, 0x00f80988),
3382         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_CL_ENHANCE, 0x01000000, 0x01200007),
3383         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800),
3384         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0x00000800, 0x00000820),
3385         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_CONFIG, 0x0000001f, 0x00180070),
3386         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER0_SELECT, 0xf0f001ff, 0x00000000),
3387         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER1_SELECT, 0xf0f001ff, 0x00000000),
3388         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER10_SELECT, 0xf0f001ff, 0x00000000),
3389         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER11_SELECT, 0xf0f001ff, 0x00000000),
3390         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER12_SELECT, 0xf0f001ff, 0x00000000),
3391         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER13_SELECT, 0xf0f001ff, 0x00000000),
3392         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER14_SELECT, 0xf0f001ff, 0x00000000),
3393         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER15_SELECT, 0xf0f001ff, 0x00000000),
3394         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER2_SELECT, 0xf0f001ff, 0x00000000),
3395         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER3_SELECT, 0xf0f001ff, 0x00000000),
3396         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER4_SELECT, 0xf0f001ff, 0x00000000),
3397         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER5_SELECT, 0xf0f001ff, 0x00000000),
3398         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER6_SELECT, 0xf0f001ff, 0x00000000),
3399         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER7_SELECT, 0xf0f001ff, 0x00000000),
3400         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER8_SELECT, 0xf0f001ff, 0x00000000),
3401         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER9_SELECT, 0xf0f001ff, 0x00000000),
3402         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0x01030000, 0x01030000),
3403         SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0x03a00000, 0x00a00000),
3404         SOC15_REG_GOLDEN_VALUE(GC, 0, mmLDS_CONFIG,  0x00000020, 0x00000020)
3405 };
3406
3407 #define DEFAULT_SH_MEM_CONFIG \
3408         ((SH_MEM_ADDRESS_MODE_64 << SH_MEM_CONFIG__ADDRESS_MODE__SHIFT) | \
3409          (SH_MEM_ALIGNMENT_MODE_UNALIGNED << SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT) | \
3410          (SH_MEM_RETRY_MODE_ALL << SH_MEM_CONFIG__RETRY_MODE__SHIFT) | \
3411          (3 << SH_MEM_CONFIG__INITIAL_INST_PREFETCH__SHIFT))
3412
3413
3414 static void gfx_v10_0_set_ring_funcs(struct amdgpu_device *adev);
3415 static void gfx_v10_0_set_irq_funcs(struct amdgpu_device *adev);
3416 static void gfx_v10_0_set_gds_init(struct amdgpu_device *adev);
3417 static void gfx_v10_0_set_rlc_funcs(struct amdgpu_device *adev);
3418 static int gfx_v10_0_get_cu_info(struct amdgpu_device *adev,
3419                                  struct amdgpu_cu_info *cu_info);
3420 static uint64_t gfx_v10_0_get_gpu_clock_counter(struct amdgpu_device *adev);
3421 static void gfx_v10_0_select_se_sh(struct amdgpu_device *adev, u32 se_num,
3422                                    u32 sh_num, u32 instance);
3423 static u32 gfx_v10_0_get_wgp_active_bitmap_per_sh(struct amdgpu_device *adev);
3424
3425 static int gfx_v10_0_rlc_backdoor_autoload_buffer_init(struct amdgpu_device *adev);
3426 static void gfx_v10_0_rlc_backdoor_autoload_buffer_fini(struct amdgpu_device *adev);
3427 static int gfx_v10_0_rlc_backdoor_autoload_enable(struct amdgpu_device *adev);
3428 static int gfx_v10_0_wait_for_rlc_autoload_complete(struct amdgpu_device *adev);
3429 static void gfx_v10_0_ring_emit_ce_meta(struct amdgpu_ring *ring, bool resume);
3430 static void gfx_v10_0_ring_emit_de_meta(struct amdgpu_ring *ring, bool resume);
3431 static void gfx_v10_0_ring_emit_frame_cntl(struct amdgpu_ring *ring, bool start, bool secure);
3432 static u32 gfx_v10_3_get_disabled_sa(struct amdgpu_device *adev);
3433 static void gfx_v10_3_program_pbb_mode(struct amdgpu_device *adev);
3434 static void gfx_v10_3_set_power_brake_sequence(struct amdgpu_device *adev);
3435
3436 static void gfx10_kiq_set_resources(struct amdgpu_ring *kiq_ring, uint64_t queue_mask)
3437 {
3438         amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_SET_RESOURCES, 6));
3439         amdgpu_ring_write(kiq_ring, PACKET3_SET_RESOURCES_VMID_MASK(0) |
3440                           PACKET3_SET_RESOURCES_QUEUE_TYPE(0)); /* vmid_mask:0 queue_type:0 (KIQ) */
3441         amdgpu_ring_write(kiq_ring, lower_32_bits(queue_mask)); /* queue mask lo */
3442         amdgpu_ring_write(kiq_ring, upper_32_bits(queue_mask)); /* queue mask hi */
3443         amdgpu_ring_write(kiq_ring, 0); /* gws mask lo */
3444         amdgpu_ring_write(kiq_ring, 0); /* gws mask hi */
3445         amdgpu_ring_write(kiq_ring, 0); /* oac mask */
3446         amdgpu_ring_write(kiq_ring, 0); /* gds heap base:0, gds heap size:0 */
3447 }
3448
3449 static void gfx10_kiq_map_queues(struct amdgpu_ring *kiq_ring,
3450                                  struct amdgpu_ring *ring)
3451 {
3452         struct amdgpu_device *adev = kiq_ring->adev;
3453         uint64_t mqd_addr = amdgpu_bo_gpu_offset(ring->mqd_obj);
3454         uint64_t wptr_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
3455         uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0;
3456
3457         amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_MAP_QUEUES, 5));
3458         /* Q_sel:0, vmid:0, vidmem: 1, engine:0, num_Q:1*/
3459         amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */
3460                           PACKET3_MAP_QUEUES_QUEUE_SEL(0) | /* Queue_Sel */
3461                           PACKET3_MAP_QUEUES_VMID(0) | /* VMID */
3462                           PACKET3_MAP_QUEUES_QUEUE(ring->queue) |
3463                           PACKET3_MAP_QUEUES_PIPE(ring->pipe) |
3464                           PACKET3_MAP_QUEUES_ME((ring->me == 1 ? 0 : 1)) |
3465                           PACKET3_MAP_QUEUES_QUEUE_TYPE(0) | /*queue_type: normal compute queue */
3466                           PACKET3_MAP_QUEUES_ALLOC_FORMAT(0) | /* alloc format: all_on_one_pipe */
3467                           PACKET3_MAP_QUEUES_ENGINE_SEL(eng_sel) |
3468                           PACKET3_MAP_QUEUES_NUM_QUEUES(1)); /* num_queues: must be 1 */
3469         amdgpu_ring_write(kiq_ring, PACKET3_MAP_QUEUES_DOORBELL_OFFSET(ring->doorbell_index));
3470         amdgpu_ring_write(kiq_ring, lower_32_bits(mqd_addr));
3471         amdgpu_ring_write(kiq_ring, upper_32_bits(mqd_addr));
3472         amdgpu_ring_write(kiq_ring, lower_32_bits(wptr_addr));
3473         amdgpu_ring_write(kiq_ring, upper_32_bits(wptr_addr));
3474 }
3475
3476 static void gfx10_kiq_unmap_queues(struct amdgpu_ring *kiq_ring,
3477                                    struct amdgpu_ring *ring,
3478                                    enum amdgpu_unmap_queues_action action,
3479                                    u64 gpu_addr, u64 seq)
3480 {
3481         uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0;
3482
3483         amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_UNMAP_QUEUES, 4));
3484         amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */
3485                           PACKET3_UNMAP_QUEUES_ACTION(action) |
3486                           PACKET3_UNMAP_QUEUES_QUEUE_SEL(0) |
3487                           PACKET3_UNMAP_QUEUES_ENGINE_SEL(eng_sel) |
3488                           PACKET3_UNMAP_QUEUES_NUM_QUEUES(1));
3489         amdgpu_ring_write(kiq_ring,
3490                   PACKET3_UNMAP_QUEUES_DOORBELL_OFFSET0(ring->doorbell_index));
3491
3492         if (action == PREEMPT_QUEUES_NO_UNMAP) {
3493                 amdgpu_ring_write(kiq_ring, lower_32_bits(gpu_addr));
3494                 amdgpu_ring_write(kiq_ring, upper_32_bits(gpu_addr));
3495                 amdgpu_ring_write(kiq_ring, seq);
3496         } else {
3497                 amdgpu_ring_write(kiq_ring, 0);
3498                 amdgpu_ring_write(kiq_ring, 0);
3499                 amdgpu_ring_write(kiq_ring, 0);
3500         }
3501 }
3502
3503 static void gfx10_kiq_query_status(struct amdgpu_ring *kiq_ring,
3504                                    struct amdgpu_ring *ring,
3505                                    u64 addr,
3506                                    u64 seq)
3507 {
3508         uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0;
3509
3510         amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_QUERY_STATUS, 5));
3511         amdgpu_ring_write(kiq_ring,
3512                           PACKET3_QUERY_STATUS_CONTEXT_ID(0) |
3513                           PACKET3_QUERY_STATUS_INTERRUPT_SEL(0) |
3514                           PACKET3_QUERY_STATUS_COMMAND(2));
3515         amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */
3516                           PACKET3_QUERY_STATUS_DOORBELL_OFFSET(ring->doorbell_index) |
3517                           PACKET3_QUERY_STATUS_ENG_SEL(eng_sel));
3518         amdgpu_ring_write(kiq_ring, lower_32_bits(addr));
3519         amdgpu_ring_write(kiq_ring, upper_32_bits(addr));
3520         amdgpu_ring_write(kiq_ring, lower_32_bits(seq));
3521         amdgpu_ring_write(kiq_ring, upper_32_bits(seq));
3522 }
3523
3524 static void gfx10_kiq_invalidate_tlbs(struct amdgpu_ring *kiq_ring,
3525                                 uint16_t pasid, uint32_t flush_type,
3526                                 bool all_hub)
3527 {
3528         amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_INVALIDATE_TLBS, 0));
3529         amdgpu_ring_write(kiq_ring,
3530                         PACKET3_INVALIDATE_TLBS_DST_SEL(1) |
3531                         PACKET3_INVALIDATE_TLBS_ALL_HUB(all_hub) |
3532                         PACKET3_INVALIDATE_TLBS_PASID(pasid) |
3533                         PACKET3_INVALIDATE_TLBS_FLUSH_TYPE(flush_type));
3534 }
3535
3536 static const struct kiq_pm4_funcs gfx_v10_0_kiq_pm4_funcs = {
3537         .kiq_set_resources = gfx10_kiq_set_resources,
3538         .kiq_map_queues = gfx10_kiq_map_queues,
3539         .kiq_unmap_queues = gfx10_kiq_unmap_queues,
3540         .kiq_query_status = gfx10_kiq_query_status,
3541         .kiq_invalidate_tlbs = gfx10_kiq_invalidate_tlbs,
3542         .set_resources_size = 8,
3543         .map_queues_size = 7,
3544         .unmap_queues_size = 6,
3545         .query_status_size = 7,
3546         .invalidate_tlbs_size = 2,
3547 };
3548
3549 static void gfx_v10_0_set_kiq_pm4_funcs(struct amdgpu_device *adev)
3550 {
3551         adev->gfx.kiq.pmf = &gfx_v10_0_kiq_pm4_funcs;
3552 }
3553
3554 static void gfx_v10_0_init_spm_golden_registers(struct amdgpu_device *adev)
3555 {
3556         switch (adev->asic_type) {
3557         case CHIP_NAVI10:
3558                 soc15_program_register_sequence(adev,
3559                                                 golden_settings_gc_rlc_spm_10_0_nv10,
3560                                                 (const u32)ARRAY_SIZE(golden_settings_gc_rlc_spm_10_0_nv10));
3561                 break;
3562         case CHIP_NAVI14:
3563                 soc15_program_register_sequence(adev,
3564                                                 golden_settings_gc_rlc_spm_10_1_nv14,
3565                                                 (const u32)ARRAY_SIZE(golden_settings_gc_rlc_spm_10_1_nv14));
3566                 break;
3567         case CHIP_NAVI12:
3568                 soc15_program_register_sequence(adev,
3569                                                 golden_settings_gc_rlc_spm_10_1_2_nv12,
3570                                                 (const u32)ARRAY_SIZE(golden_settings_gc_rlc_spm_10_1_2_nv12));
3571                 break;
3572         default:
3573                 break;
3574         }
3575 }
3576
3577 static void gfx_v10_0_init_golden_registers(struct amdgpu_device *adev)
3578 {
3579         switch (adev->asic_type) {
3580         case CHIP_NAVI10:
3581                 soc15_program_register_sequence(adev,
3582                                                 golden_settings_gc_10_1,
3583                                                 (const u32)ARRAY_SIZE(golden_settings_gc_10_1));
3584                 soc15_program_register_sequence(adev,
3585                                                 golden_settings_gc_10_0_nv10,
3586                                                 (const u32)ARRAY_SIZE(golden_settings_gc_10_0_nv10));
3587                 break;
3588         case CHIP_NAVI14:
3589                 soc15_program_register_sequence(adev,
3590                                                 golden_settings_gc_10_1_1,
3591                                                 (const u32)ARRAY_SIZE(golden_settings_gc_10_1_1));
3592                 soc15_program_register_sequence(adev,
3593                                                 golden_settings_gc_10_1_nv14,
3594                                                 (const u32)ARRAY_SIZE(golden_settings_gc_10_1_nv14));
3595                 break;
3596         case CHIP_NAVI12:
3597                 soc15_program_register_sequence(adev,
3598                                                 golden_settings_gc_10_1_2,
3599                                                 (const u32)ARRAY_SIZE(golden_settings_gc_10_1_2));
3600                 soc15_program_register_sequence(adev,
3601                                                 golden_settings_gc_10_1_2_nv12,
3602                                                 (const u32)ARRAY_SIZE(golden_settings_gc_10_1_2_nv12));
3603                 break;
3604         case CHIP_SIENNA_CICHLID:
3605                 soc15_program_register_sequence(adev,
3606                                                 golden_settings_gc_10_3,
3607                                                 (const u32)ARRAY_SIZE(golden_settings_gc_10_3));
3608                 soc15_program_register_sequence(adev,
3609                                                 golden_settings_gc_10_3_sienna_cichlid,
3610                                                 (const u32)ARRAY_SIZE(golden_settings_gc_10_3_sienna_cichlid));
3611                 break;
3612         case CHIP_NAVY_FLOUNDER:
3613                 soc15_program_register_sequence(adev,
3614                                                 golden_settings_gc_10_3_2,
3615                                                 (const u32)ARRAY_SIZE(golden_settings_gc_10_3_2));
3616                 break;
3617         case CHIP_VANGOGH:
3618                 soc15_program_register_sequence(adev,
3619                                                 golden_settings_gc_10_3_vangogh,
3620                                                 (const u32)ARRAY_SIZE(golden_settings_gc_10_3_vangogh));
3621                 break;
3622         case CHIP_DIMGREY_CAVEFISH:
3623                 soc15_program_register_sequence(adev,
3624                                                 golden_settings_gc_10_3_4,
3625                                                 (const u32)ARRAY_SIZE(golden_settings_gc_10_3_4));
3626                 break;
3627         default:
3628                 break;
3629         }
3630         gfx_v10_0_init_spm_golden_registers(adev);
3631 }
3632
3633 static void gfx_v10_0_scratch_init(struct amdgpu_device *adev)
3634 {
3635         adev->gfx.scratch.num_reg = 8;
3636         adev->gfx.scratch.reg_base = SOC15_REG_OFFSET(GC, 0, mmSCRATCH_REG0);
3637         adev->gfx.scratch.free_mask = (1u << adev->gfx.scratch.num_reg) - 1;
3638 }
3639
3640 static void gfx_v10_0_write_data_to_reg(struct amdgpu_ring *ring, int eng_sel,
3641                                        bool wc, uint32_t reg, uint32_t val)
3642 {
3643         amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
3644         amdgpu_ring_write(ring, WRITE_DATA_ENGINE_SEL(eng_sel) |
3645                           WRITE_DATA_DST_SEL(0) | (wc ? WR_CONFIRM : 0));
3646         amdgpu_ring_write(ring, reg);
3647         amdgpu_ring_write(ring, 0);
3648         amdgpu_ring_write(ring, val);
3649 }
3650
3651 static void gfx_v10_0_wait_reg_mem(struct amdgpu_ring *ring, int eng_sel,
3652                                   int mem_space, int opt, uint32_t addr0,
3653                                   uint32_t addr1, uint32_t ref, uint32_t mask,
3654                                   uint32_t inv)
3655 {
3656         amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5));
3657         amdgpu_ring_write(ring,
3658                           /* memory (1) or register (0) */
3659                           (WAIT_REG_MEM_MEM_SPACE(mem_space) |
3660                            WAIT_REG_MEM_OPERATION(opt) | /* wait */
3661                            WAIT_REG_MEM_FUNCTION(3) |  /* equal */
3662                            WAIT_REG_MEM_ENGINE(eng_sel)));
3663
3664         if (mem_space)
3665                 BUG_ON(addr0 & 0x3); /* Dword align */
3666         amdgpu_ring_write(ring, addr0);
3667         amdgpu_ring_write(ring, addr1);
3668         amdgpu_ring_write(ring, ref);
3669         amdgpu_ring_write(ring, mask);
3670         amdgpu_ring_write(ring, inv); /* poll interval */
3671 }
3672
3673 static int gfx_v10_0_ring_test_ring(struct amdgpu_ring *ring)
3674 {
3675         struct amdgpu_device *adev = ring->adev;
3676         uint32_t scratch;
3677         uint32_t tmp = 0;
3678         unsigned i;
3679         int r;
3680
3681         r = amdgpu_gfx_scratch_get(adev, &scratch);
3682         if (r) {
3683                 DRM_ERROR("amdgpu: cp failed to get scratch reg (%d).\n", r);
3684                 return r;
3685         }
3686
3687         WREG32(scratch, 0xCAFEDEAD);
3688
3689         r = amdgpu_ring_alloc(ring, 3);
3690         if (r) {
3691                 DRM_ERROR("amdgpu: cp failed to lock ring %d (%d).\n",
3692                           ring->idx, r);
3693                 amdgpu_gfx_scratch_free(adev, scratch);
3694                 return r;
3695         }
3696
3697         amdgpu_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1));
3698         amdgpu_ring_write(ring, (scratch - PACKET3_SET_UCONFIG_REG_START));
3699         amdgpu_ring_write(ring, 0xDEADBEEF);
3700         amdgpu_ring_commit(ring);
3701
3702         for (i = 0; i < adev->usec_timeout; i++) {
3703                 tmp = RREG32(scratch);
3704                 if (tmp == 0xDEADBEEF)
3705                         break;
3706                 if (amdgpu_emu_mode == 1)
3707                         msleep(1);
3708                 else
3709                         udelay(1);
3710         }
3711
3712         if (i >= adev->usec_timeout)
3713                 r = -ETIMEDOUT;
3714
3715         amdgpu_gfx_scratch_free(adev, scratch);
3716
3717         return r;
3718 }
3719
3720 static int gfx_v10_0_ring_test_ib(struct amdgpu_ring *ring, long timeout)
3721 {
3722         struct amdgpu_device *adev = ring->adev;
3723         struct amdgpu_ib ib;
3724         struct dma_fence *f = NULL;
3725         unsigned index;
3726         uint64_t gpu_addr;
3727         uint32_t tmp;
3728         long r;
3729
3730         r = amdgpu_device_wb_get(adev, &index);
3731         if (r)
3732                 return r;
3733
3734         gpu_addr = adev->wb.gpu_addr + (index * 4);
3735         adev->wb.wb[index] = cpu_to_le32(0xCAFEDEAD);
3736         memset(&ib, 0, sizeof(ib));
3737         r = amdgpu_ib_get(adev, NULL, 16,
3738                                         AMDGPU_IB_POOL_DIRECT, &ib);
3739         if (r)
3740                 goto err1;
3741
3742         ib.ptr[0] = PACKET3(PACKET3_WRITE_DATA, 3);
3743         ib.ptr[1] = WRITE_DATA_DST_SEL(5) | WR_CONFIRM;
3744         ib.ptr[2] = lower_32_bits(gpu_addr);
3745         ib.ptr[3] = upper_32_bits(gpu_addr);
3746         ib.ptr[4] = 0xDEADBEEF;
3747         ib.length_dw = 5;
3748
3749         r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f);
3750         if (r)
3751                 goto err2;
3752
3753         r = dma_fence_wait_timeout(f, false, timeout);
3754         if (r == 0) {
3755                 r = -ETIMEDOUT;
3756                 goto err2;
3757         } else if (r < 0) {
3758                 goto err2;
3759         }
3760
3761         tmp = adev->wb.wb[index];
3762         if (tmp == 0xDEADBEEF)
3763                 r = 0;
3764         else
3765                 r = -EINVAL;
3766 err2:
3767         amdgpu_ib_free(adev, &ib, NULL);
3768         dma_fence_put(f);
3769 err1:
3770         amdgpu_device_wb_free(adev, index);
3771         return r;
3772 }
3773
3774 static void gfx_v10_0_free_microcode(struct amdgpu_device *adev)
3775 {
3776         release_firmware(adev->gfx.pfp_fw);
3777         adev->gfx.pfp_fw = NULL;
3778         release_firmware(adev->gfx.me_fw);
3779         adev->gfx.me_fw = NULL;
3780         release_firmware(adev->gfx.ce_fw);
3781         adev->gfx.ce_fw = NULL;
3782         release_firmware(adev->gfx.rlc_fw);
3783         adev->gfx.rlc_fw = NULL;
3784         release_firmware(adev->gfx.mec_fw);
3785         adev->gfx.mec_fw = NULL;
3786         release_firmware(adev->gfx.mec2_fw);
3787         adev->gfx.mec2_fw = NULL;
3788
3789         kfree(adev->gfx.rlc.register_list_format);
3790 }
3791
3792 static void gfx_v10_0_check_fw_write_wait(struct amdgpu_device *adev)
3793 {
3794         adev->gfx.cp_fw_write_wait = false;
3795
3796         switch (adev->asic_type) {
3797         case CHIP_NAVI10:
3798         case CHIP_NAVI12:
3799         case CHIP_NAVI14:
3800                 if ((adev->gfx.me_fw_version >= 0x00000046) &&
3801                     (adev->gfx.me_feature_version >= 27) &&
3802                     (adev->gfx.pfp_fw_version >= 0x00000068) &&
3803                     (adev->gfx.pfp_feature_version >= 27) &&
3804                     (adev->gfx.mec_fw_version >= 0x0000005b) &&
3805                     (adev->gfx.mec_feature_version >= 27))
3806                         adev->gfx.cp_fw_write_wait = true;
3807                 break;
3808         case CHIP_SIENNA_CICHLID:
3809         case CHIP_NAVY_FLOUNDER:
3810         case CHIP_VANGOGH:
3811         case CHIP_DIMGREY_CAVEFISH:
3812                 adev->gfx.cp_fw_write_wait = true;
3813                 break;
3814         default:
3815                 break;
3816         }
3817
3818         if (!adev->gfx.cp_fw_write_wait)
3819                 DRM_WARN_ONCE("CP firmware version too old, please update!");
3820 }
3821
3822
3823 static void gfx_v10_0_init_rlc_ext_microcode(struct amdgpu_device *adev)
3824 {
3825         const struct rlc_firmware_header_v2_1 *rlc_hdr;
3826
3827         rlc_hdr = (const struct rlc_firmware_header_v2_1 *)adev->gfx.rlc_fw->data;
3828         adev->gfx.rlc_srlc_fw_version = le32_to_cpu(rlc_hdr->save_restore_list_cntl_ucode_ver);
3829         adev->gfx.rlc_srlc_feature_version = le32_to_cpu(rlc_hdr->save_restore_list_cntl_feature_ver);
3830         adev->gfx.rlc.save_restore_list_cntl_size_bytes = le32_to_cpu(rlc_hdr->save_restore_list_cntl_size_bytes);
3831         adev->gfx.rlc.save_restore_list_cntl = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->save_restore_list_cntl_offset_bytes);
3832         adev->gfx.rlc_srlg_fw_version = le32_to_cpu(rlc_hdr->save_restore_list_gpm_ucode_ver);
3833         adev->gfx.rlc_srlg_feature_version = le32_to_cpu(rlc_hdr->save_restore_list_gpm_feature_ver);
3834         adev->gfx.rlc.save_restore_list_gpm_size_bytes = le32_to_cpu(rlc_hdr->save_restore_list_gpm_size_bytes);
3835         adev->gfx.rlc.save_restore_list_gpm = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->save_restore_list_gpm_offset_bytes);
3836         adev->gfx.rlc_srls_fw_version = le32_to_cpu(rlc_hdr->save_restore_list_srm_ucode_ver);
3837         adev->gfx.rlc_srls_feature_version = le32_to_cpu(rlc_hdr->save_restore_list_srm_feature_ver);
3838         adev->gfx.rlc.save_restore_list_srm_size_bytes = le32_to_cpu(rlc_hdr->save_restore_list_srm_size_bytes);
3839         adev->gfx.rlc.save_restore_list_srm = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->save_restore_list_srm_offset_bytes);
3840         adev->gfx.rlc.reg_list_format_direct_reg_list_length =
3841                         le32_to_cpu(rlc_hdr->reg_list_format_direct_reg_list_length);
3842 }
3843
3844 static void gfx_v10_0_init_rlc_iram_dram_microcode(struct amdgpu_device *adev)
3845 {
3846         const struct rlc_firmware_header_v2_2 *rlc_hdr;
3847
3848         rlc_hdr = (const struct rlc_firmware_header_v2_2 *)adev->gfx.rlc_fw->data;
3849         adev->gfx.rlc.rlc_iram_ucode_size_bytes = le32_to_cpu(rlc_hdr->rlc_iram_ucode_size_bytes);
3850         adev->gfx.rlc.rlc_iram_ucode = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->rlc_iram_ucode_offset_bytes);
3851         adev->gfx.rlc.rlc_dram_ucode_size_bytes = le32_to_cpu(rlc_hdr->rlc_dram_ucode_size_bytes);
3852         adev->gfx.rlc.rlc_dram_ucode = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->rlc_dram_ucode_offset_bytes);
3853 }
3854
3855 static bool gfx_v10_0_navi10_gfxoff_should_enable(struct amdgpu_device *adev)
3856 {
3857         bool ret = false;
3858
3859         switch (adev->pdev->revision) {
3860         case 0xc2:
3861         case 0xc3:
3862                 ret = true;
3863                 break;
3864         default:
3865                 ret = false;
3866                 break;
3867         }
3868
3869         return ret ;
3870 }
3871
3872 static void gfx_v10_0_check_gfxoff_flag(struct amdgpu_device *adev)
3873 {
3874         switch (adev->asic_type) {
3875         case CHIP_NAVI10:
3876                 if (!gfx_v10_0_navi10_gfxoff_should_enable(adev))
3877                         adev->pm.pp_feature &= ~PP_GFXOFF_MASK;
3878                 break;
3879         default:
3880                 break;
3881         }
3882 }
3883
3884 static int gfx_v10_0_init_microcode(struct amdgpu_device *adev)
3885 {
3886         const char *chip_name;
3887         char fw_name[40];
3888         char wks[10];
3889         int err;
3890         struct amdgpu_firmware_info *info = NULL;
3891         const struct common_firmware_header *header = NULL;
3892         const struct gfx_firmware_header_v1_0 *cp_hdr;
3893         const struct rlc_firmware_header_v2_0 *rlc_hdr;
3894         unsigned int *tmp = NULL;
3895         unsigned int i = 0;
3896         uint16_t version_major;
3897         uint16_t version_minor;
3898
3899         DRM_DEBUG("\n");
3900
3901         memset(wks, 0, sizeof(wks));
3902         switch (adev->asic_type) {
3903         case CHIP_NAVI10:
3904                 chip_name = "navi10";
3905                 break;
3906         case CHIP_NAVI14:
3907                 chip_name = "navi14";
3908                 if (!(adev->pdev->device == 0x7340 &&
3909                       adev->pdev->revision != 0x00))
3910                         snprintf(wks, sizeof(wks), "_wks");
3911                 break;
3912         case CHIP_NAVI12:
3913                 chip_name = "navi12";
3914                 break;
3915         case CHIP_SIENNA_CICHLID:
3916                 chip_name = "sienna_cichlid";
3917                 break;
3918         case CHIP_NAVY_FLOUNDER:
3919                 chip_name = "navy_flounder";
3920                 break;
3921         case CHIP_VANGOGH:
3922                 chip_name = "vangogh";
3923                 break;
3924         case CHIP_DIMGREY_CAVEFISH:
3925                 chip_name = "dimgrey_cavefish";
3926                 break;
3927         default:
3928                 BUG();
3929         }
3930
3931         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_pfp%s.bin", chip_name, wks);
3932         err = request_firmware(&adev->gfx.pfp_fw, fw_name, adev->dev);
3933         if (err)
3934                 goto out;
3935         err = amdgpu_ucode_validate(adev->gfx.pfp_fw);
3936         if (err)
3937                 goto out;
3938         cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.pfp_fw->data;
3939         adev->gfx.pfp_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
3940         adev->gfx.pfp_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
3941
3942         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_me%s.bin", chip_name, wks);
3943         err = request_firmware(&adev->gfx.me_fw, fw_name, adev->dev);
3944         if (err)
3945                 goto out;
3946         err = amdgpu_ucode_validate(adev->gfx.me_fw);
3947         if (err)
3948                 goto out;
3949         cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.me_fw->data;
3950         adev->gfx.me_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
3951         adev->gfx.me_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
3952
3953         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_ce%s.bin", chip_name, wks);
3954         err = request_firmware(&adev->gfx.ce_fw, fw_name, adev->dev);
3955         if (err)
3956                 goto out;
3957         err = amdgpu_ucode_validate(adev->gfx.ce_fw);
3958         if (err)
3959                 goto out;
3960         cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.ce_fw->data;
3961         adev->gfx.ce_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
3962         adev->gfx.ce_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
3963
3964         if (!amdgpu_sriov_vf(adev)) {
3965                 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_rlc.bin", chip_name);
3966                 err = request_firmware(&adev->gfx.rlc_fw, fw_name, adev->dev);
3967                 if (err)
3968                         goto out;
3969                 err = amdgpu_ucode_validate(adev->gfx.rlc_fw);
3970                 rlc_hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data;
3971                 version_major = le16_to_cpu(rlc_hdr->header.header_version_major);
3972                 version_minor = le16_to_cpu(rlc_hdr->header.header_version_minor);
3973
3974                 adev->gfx.rlc_fw_version = le32_to_cpu(rlc_hdr->header.ucode_version);
3975                 adev->gfx.rlc_feature_version = le32_to_cpu(rlc_hdr->ucode_feature_version);
3976                 adev->gfx.rlc.save_and_restore_offset =
3977                         le32_to_cpu(rlc_hdr->save_and_restore_offset);
3978                 adev->gfx.rlc.clear_state_descriptor_offset =
3979                         le32_to_cpu(rlc_hdr->clear_state_descriptor_offset);
3980                 adev->gfx.rlc.avail_scratch_ram_locations =
3981                         le32_to_cpu(rlc_hdr->avail_scratch_ram_locations);
3982                 adev->gfx.rlc.reg_restore_list_size =
3983                         le32_to_cpu(rlc_hdr->reg_restore_list_size);
3984                 adev->gfx.rlc.reg_list_format_start =
3985                         le32_to_cpu(rlc_hdr->reg_list_format_start);
3986                 adev->gfx.rlc.reg_list_format_separate_start =
3987                         le32_to_cpu(rlc_hdr->reg_list_format_separate_start);
3988                 adev->gfx.rlc.starting_offsets_start =
3989                         le32_to_cpu(rlc_hdr->starting_offsets_start);
3990                 adev->gfx.rlc.reg_list_format_size_bytes =
3991                         le32_to_cpu(rlc_hdr->reg_list_format_size_bytes);
3992                 adev->gfx.rlc.reg_list_size_bytes =
3993                         le32_to_cpu(rlc_hdr->reg_list_size_bytes);
3994                 adev->gfx.rlc.register_list_format =
3995                         kmalloc(adev->gfx.rlc.reg_list_format_size_bytes +
3996                                         adev->gfx.rlc.reg_list_size_bytes, GFP_KERNEL);
3997                 if (!adev->gfx.rlc.register_list_format) {
3998                         err = -ENOMEM;
3999                         goto out;
4000                 }
4001
4002                 tmp = (unsigned int *)((uintptr_t)rlc_hdr +
4003                                                            le32_to_cpu(rlc_hdr->reg_list_format_array_offset_bytes));
4004                 for (i = 0 ; i < (rlc_hdr->reg_list_format_size_bytes >> 2); i++)
4005                         adev->gfx.rlc.register_list_format[i] = le32_to_cpu(tmp[i]);
4006
4007                 adev->gfx.rlc.register_restore = adev->gfx.rlc.register_list_format + i;
4008
4009                 tmp = (unsigned int *)((uintptr_t)rlc_hdr +
4010                                                            le32_to_cpu(rlc_hdr->reg_list_array_offset_bytes));
4011                 for (i = 0 ; i < (rlc_hdr->reg_list_size_bytes >> 2); i++)
4012                         adev->gfx.rlc.register_restore[i] = le32_to_cpu(tmp[i]);
4013
4014                 if (version_major == 2) {
4015                         if (version_minor >= 1)
4016                                 gfx_v10_0_init_rlc_ext_microcode(adev);
4017                         if (version_minor == 2)
4018                                 gfx_v10_0_init_rlc_iram_dram_microcode(adev);
4019                 }
4020         }
4021
4022         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec%s.bin", chip_name, wks);
4023         err = request_firmware(&adev->gfx.mec_fw, fw_name, adev->dev);
4024         if (err)
4025                 goto out;
4026         err = amdgpu_ucode_validate(adev->gfx.mec_fw);
4027         if (err)
4028                 goto out;
4029         cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data;
4030         adev->gfx.mec_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
4031         adev->gfx.mec_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
4032
4033         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec2%s.bin", chip_name, wks);
4034         err = request_firmware(&adev->gfx.mec2_fw, fw_name, adev->dev);
4035         if (!err) {
4036                 err = amdgpu_ucode_validate(adev->gfx.mec2_fw);
4037                 if (err)
4038                         goto out;
4039                 cp_hdr = (const struct gfx_firmware_header_v1_0 *)
4040                 adev->gfx.mec2_fw->data;
4041                 adev->gfx.mec2_fw_version =
4042                 le32_to_cpu(cp_hdr->header.ucode_version);
4043                 adev->gfx.mec2_feature_version =
4044                 le32_to_cpu(cp_hdr->ucode_feature_version);
4045         } else {
4046                 err = 0;
4047                 adev->gfx.mec2_fw = NULL;
4048         }
4049
4050         if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
4051                 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_PFP];
4052                 info->ucode_id = AMDGPU_UCODE_ID_CP_PFP;
4053                 info->fw = adev->gfx.pfp_fw;
4054                 header = (const struct common_firmware_header *)info->fw->data;
4055                 adev->firmware.fw_size +=
4056                         ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
4057
4058                 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_ME];
4059                 info->ucode_id = AMDGPU_UCODE_ID_CP_ME;
4060                 info->fw = adev->gfx.me_fw;
4061                 header = (const struct common_firmware_header *)info->fw->data;
4062                 adev->firmware.fw_size +=
4063                         ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
4064
4065                 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_CE];
4066                 info->ucode_id = AMDGPU_UCODE_ID_CP_CE;
4067                 info->fw = adev->gfx.ce_fw;
4068                 header = (const struct common_firmware_header *)info->fw->data;
4069                 adev->firmware.fw_size +=
4070                         ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
4071
4072                 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_G];
4073                 info->ucode_id = AMDGPU_UCODE_ID_RLC_G;
4074                 info->fw = adev->gfx.rlc_fw;
4075                 if (info->fw) {
4076                         header = (const struct common_firmware_header *)info->fw->data;
4077                         adev->firmware.fw_size +=
4078                                 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
4079                 }
4080                 if (adev->gfx.rlc.save_restore_list_cntl_size_bytes &&
4081                     adev->gfx.rlc.save_restore_list_gpm_size_bytes &&
4082                     adev->gfx.rlc.save_restore_list_srm_size_bytes) {
4083                         info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL];
4084                         info->ucode_id = AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL;
4085                         info->fw = adev->gfx.rlc_fw;
4086                         adev->firmware.fw_size +=
4087                                 ALIGN(adev->gfx.rlc.save_restore_list_cntl_size_bytes, PAGE_SIZE);
4088
4089                         info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM];
4090                         info->ucode_id = AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM;
4091                         info->fw = adev->gfx.rlc_fw;
4092                         adev->firmware.fw_size +=
4093                                 ALIGN(adev->gfx.rlc.save_restore_list_gpm_size_bytes, PAGE_SIZE);
4094
4095                         info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM];
4096                         info->ucode_id = AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM;
4097                         info->fw = adev->gfx.rlc_fw;
4098                         adev->firmware.fw_size +=
4099                                 ALIGN(adev->gfx.rlc.save_restore_list_srm_size_bytes, PAGE_SIZE);
4100
4101                         if (adev->gfx.rlc.rlc_iram_ucode_size_bytes &&
4102                             adev->gfx.rlc.rlc_dram_ucode_size_bytes) {
4103                                 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_IRAM];
4104                                 info->ucode_id = AMDGPU_UCODE_ID_RLC_IRAM;
4105                                 info->fw = adev->gfx.rlc_fw;
4106                                 adev->firmware.fw_size +=
4107                                         ALIGN(adev->gfx.rlc.rlc_iram_ucode_size_bytes, PAGE_SIZE);
4108
4109                                 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_DRAM];
4110                                 info->ucode_id = AMDGPU_UCODE_ID_RLC_DRAM;
4111                                 info->fw = adev->gfx.rlc_fw;
4112                                 adev->firmware.fw_size +=
4113                                         ALIGN(adev->gfx.rlc.rlc_dram_ucode_size_bytes, PAGE_SIZE);
4114                         }
4115                 }
4116
4117                 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC1];
4118                 info->ucode_id = AMDGPU_UCODE_ID_CP_MEC1;
4119                 info->fw = adev->gfx.mec_fw;
4120                 header = (const struct common_firmware_header *)info->fw->data;
4121                 cp_hdr = (const struct gfx_firmware_header_v1_0 *)info->fw->data;
4122                 adev->firmware.fw_size +=
4123                         ALIGN(le32_to_cpu(header->ucode_size_bytes) -
4124                               le32_to_cpu(cp_hdr->jt_size) * 4, PAGE_SIZE);
4125
4126                 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC1_JT];
4127                 info->ucode_id = AMDGPU_UCODE_ID_CP_MEC1_JT;
4128                 info->fw = adev->gfx.mec_fw;
4129                 adev->firmware.fw_size +=
4130                         ALIGN(le32_to_cpu(cp_hdr->jt_size) * 4, PAGE_SIZE);
4131
4132                 if (adev->gfx.mec2_fw) {
4133                         info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC2];
4134                         info->ucode_id = AMDGPU_UCODE_ID_CP_MEC2;
4135                         info->fw = adev->gfx.mec2_fw;
4136                         header = (const struct common_firmware_header *)info->fw->data;
4137                         cp_hdr = (const struct gfx_firmware_header_v1_0 *)info->fw->data;
4138                         adev->firmware.fw_size +=
4139                                 ALIGN(le32_to_cpu(header->ucode_size_bytes) -
4140                                       le32_to_cpu(cp_hdr->jt_size) * 4,
4141                                       PAGE_SIZE);
4142                         info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC2_JT];
4143                         info->ucode_id = AMDGPU_UCODE_ID_CP_MEC2_JT;
4144                         info->fw = adev->gfx.mec2_fw;
4145                         adev->firmware.fw_size +=
4146                                 ALIGN(le32_to_cpu(cp_hdr->jt_size) * 4,
4147                                       PAGE_SIZE);
4148                 }
4149         }
4150
4151         gfx_v10_0_check_fw_write_wait(adev);
4152 out:
4153         if (err) {
4154                 dev_err(adev->dev,
4155                         "gfx10: Failed to load firmware \"%s\"\n",
4156                         fw_name);
4157                 release_firmware(adev->gfx.pfp_fw);
4158                 adev->gfx.pfp_fw = NULL;
4159                 release_firmware(adev->gfx.me_fw);
4160                 adev->gfx.me_fw = NULL;
4161                 release_firmware(adev->gfx.ce_fw);
4162                 adev->gfx.ce_fw = NULL;
4163                 release_firmware(adev->gfx.rlc_fw);
4164                 adev->gfx.rlc_fw = NULL;
4165                 release_firmware(adev->gfx.mec_fw);
4166                 adev->gfx.mec_fw = NULL;
4167                 release_firmware(adev->gfx.mec2_fw);
4168                 adev->gfx.mec2_fw = NULL;
4169         }
4170
4171         gfx_v10_0_check_gfxoff_flag(adev);
4172
4173         return err;
4174 }
4175
4176 static u32 gfx_v10_0_get_csb_size(struct amdgpu_device *adev)
4177 {
4178         u32 count = 0;
4179         const struct cs_section_def *sect = NULL;
4180         const struct cs_extent_def *ext = NULL;
4181
4182         /* begin clear state */
4183         count += 2;
4184         /* context control state */
4185         count += 3;
4186
4187         for (sect = gfx10_cs_data; sect->section != NULL; ++sect) {
4188                 for (ext = sect->section; ext->extent != NULL; ++ext) {
4189                         if (sect->id == SECT_CONTEXT)
4190                                 count += 2 + ext->reg_count;
4191                         else
4192                                 return 0;
4193                 }
4194         }
4195
4196         /* set PA_SC_TILE_STEERING_OVERRIDE */
4197         count += 3;
4198         /* end clear state */
4199         count += 2;
4200         /* clear state */
4201         count += 2;
4202
4203         return count;
4204 }
4205
4206 static void gfx_v10_0_get_csb_buffer(struct amdgpu_device *adev,
4207                                     volatile u32 *buffer)
4208 {
4209         u32 count = 0, i;
4210         const struct cs_section_def *sect = NULL;
4211         const struct cs_extent_def *ext = NULL;
4212         int ctx_reg_offset;
4213
4214         if (adev->gfx.rlc.cs_data == NULL)
4215                 return;
4216         if (buffer == NULL)
4217                 return;
4218
4219         buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0));
4220         buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_BEGIN_CLEAR_STATE);
4221
4222         buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CONTEXT_CONTROL, 1));
4223         buffer[count++] = cpu_to_le32(0x80000000);
4224         buffer[count++] = cpu_to_le32(0x80000000);
4225
4226         for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) {
4227                 for (ext = sect->section; ext->extent != NULL; ++ext) {
4228                         if (sect->id == SECT_CONTEXT) {
4229                                 buffer[count++] =
4230                                         cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, ext->reg_count));
4231                                 buffer[count++] = cpu_to_le32(ext->reg_index -
4232                                                 PACKET3_SET_CONTEXT_REG_START);
4233                                 for (i = 0; i < ext->reg_count; i++)
4234                                         buffer[count++] = cpu_to_le32(ext->extent[i]);
4235                         } else {
4236                                 return;
4237                         }
4238                 }
4239         }
4240
4241         ctx_reg_offset =
4242                 SOC15_REG_OFFSET(GC, 0, mmPA_SC_TILE_STEERING_OVERRIDE) - PACKET3_SET_CONTEXT_REG_START;
4243         buffer[count++] = cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, 1));
4244         buffer[count++] = cpu_to_le32(ctx_reg_offset);
4245         buffer[count++] = cpu_to_le32(adev->gfx.config.pa_sc_tile_steering_override);
4246
4247         buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0));
4248         buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_END_CLEAR_STATE);
4249
4250         buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CLEAR_STATE, 0));
4251         buffer[count++] = cpu_to_le32(0);
4252 }
4253
4254 static void gfx_v10_0_rlc_fini(struct amdgpu_device *adev)
4255 {
4256         /* clear state block */
4257         amdgpu_bo_free_kernel(&adev->gfx.rlc.clear_state_obj,
4258                         &adev->gfx.rlc.clear_state_gpu_addr,
4259                         (void **)&adev->gfx.rlc.cs_ptr);
4260
4261         /* jump table block */
4262         amdgpu_bo_free_kernel(&adev->gfx.rlc.cp_table_obj,
4263                         &adev->gfx.rlc.cp_table_gpu_addr,
4264                         (void **)&adev->gfx.rlc.cp_table_ptr);
4265 }
4266
4267 static int gfx_v10_0_rlc_init(struct amdgpu_device *adev)
4268 {
4269         const struct cs_section_def *cs_data;
4270         int r;
4271
4272         adev->gfx.rlc.cs_data = gfx10_cs_data;
4273
4274         cs_data = adev->gfx.rlc.cs_data;
4275
4276         if (cs_data) {
4277                 /* init clear state block */
4278                 r = amdgpu_gfx_rlc_init_csb(adev);
4279                 if (r)
4280                         return r;
4281         }
4282
4283         /* init spm vmid with 0xf */
4284         if (adev->gfx.rlc.funcs->update_spm_vmid)
4285                 adev->gfx.rlc.funcs->update_spm_vmid(adev, 0xf);
4286
4287         return 0;
4288 }
4289
4290 static void gfx_v10_0_mec_fini(struct amdgpu_device *adev)
4291 {
4292         amdgpu_bo_free_kernel(&adev->gfx.mec.hpd_eop_obj, NULL, NULL);
4293         amdgpu_bo_free_kernel(&adev->gfx.mec.mec_fw_obj, NULL, NULL);
4294 }
4295
4296 static int gfx_v10_0_me_init(struct amdgpu_device *adev)
4297 {
4298         int r;
4299
4300         bitmap_zero(adev->gfx.me.queue_bitmap, AMDGPU_MAX_GFX_QUEUES);
4301
4302         amdgpu_gfx_graphics_queue_acquire(adev);
4303
4304         r = gfx_v10_0_init_microcode(adev);
4305         if (r)
4306                 DRM_ERROR("Failed to load gfx firmware!\n");
4307
4308         return r;
4309 }
4310
4311 static int gfx_v10_0_mec_init(struct amdgpu_device *adev)
4312 {
4313         int r;
4314         u32 *hpd;
4315         const __le32 *fw_data = NULL;
4316         unsigned fw_size;
4317         u32 *fw = NULL;
4318         size_t mec_hpd_size;
4319
4320         const struct gfx_firmware_header_v1_0 *mec_hdr = NULL;
4321
4322         bitmap_zero(adev->gfx.mec.queue_bitmap, AMDGPU_MAX_COMPUTE_QUEUES);
4323
4324         /* take ownership of the relevant compute queues */
4325         amdgpu_gfx_compute_queue_acquire(adev);
4326         mec_hpd_size = adev->gfx.num_compute_rings * GFX10_MEC_HPD_SIZE;
4327
4328         if (mec_hpd_size) {
4329                 r = amdgpu_bo_create_reserved(adev, mec_hpd_size, PAGE_SIZE,
4330                                               AMDGPU_GEM_DOMAIN_GTT,
4331                                               &adev->gfx.mec.hpd_eop_obj,
4332                                               &adev->gfx.mec.hpd_eop_gpu_addr,
4333                                               (void **)&hpd);
4334                 if (r) {
4335                         dev_warn(adev->dev, "(%d) create HDP EOP bo failed\n", r);
4336                         gfx_v10_0_mec_fini(adev);
4337                         return r;
4338                 }
4339
4340                 memset(hpd, 0, mec_hpd_size);
4341
4342                 amdgpu_bo_kunmap(adev->gfx.mec.hpd_eop_obj);
4343                 amdgpu_bo_unreserve(adev->gfx.mec.hpd_eop_obj);
4344         }
4345
4346         if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) {
4347                 mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data;
4348
4349                 fw_data = (const __le32 *) (adev->gfx.mec_fw->data +
4350                          le32_to_cpu(mec_hdr->header.ucode_array_offset_bytes));
4351                 fw_size = le32_to_cpu(mec_hdr->header.ucode_size_bytes);
4352
4353                 r = amdgpu_bo_create_reserved(adev, mec_hdr->header.ucode_size_bytes,
4354                                               PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT,
4355                                               &adev->gfx.mec.mec_fw_obj,
4356                                               &adev->gfx.mec.mec_fw_gpu_addr,
4357                                               (void **)&fw);
4358                 if (r) {
4359                         dev_err(adev->dev, "(%d) failed to create mec fw bo\n", r);
4360                         gfx_v10_0_mec_fini(adev);
4361                         return r;
4362                 }
4363
4364                 memcpy(fw, fw_data, fw_size);
4365
4366                 amdgpu_bo_kunmap(adev->gfx.mec.mec_fw_obj);
4367                 amdgpu_bo_unreserve(adev->gfx.mec.mec_fw_obj);
4368         }
4369
4370         return 0;
4371 }
4372
4373 static uint32_t wave_read_ind(struct amdgpu_device *adev, uint32_t wave, uint32_t address)
4374 {
4375         WREG32_SOC15(GC, 0, mmSQ_IND_INDEX,
4376                 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) |
4377                 (address << SQ_IND_INDEX__INDEX__SHIFT));
4378         return RREG32_SOC15(GC, 0, mmSQ_IND_DATA);
4379 }
4380
4381 static void wave_read_regs(struct amdgpu_device *adev, uint32_t wave,
4382                            uint32_t thread, uint32_t regno,
4383                            uint32_t num, uint32_t *out)
4384 {
4385         WREG32_SOC15(GC, 0, mmSQ_IND_INDEX,
4386                 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) |
4387                 (regno << SQ_IND_INDEX__INDEX__SHIFT) |
4388                 (thread << SQ_IND_INDEX__WORKITEM_ID__SHIFT) |
4389                 (SQ_IND_INDEX__AUTO_INCR_MASK));
4390         while (num--)
4391                 *(out++) = RREG32_SOC15(GC, 0, mmSQ_IND_DATA);
4392 }
4393
4394 static void gfx_v10_0_read_wave_data(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t *dst, int *no_fields)
4395 {
4396         /* in gfx10 the SIMD_ID is specified as part of the INSTANCE
4397          * field when performing a select_se_sh so it should be
4398          * zero here */
4399         WARN_ON(simd != 0);
4400
4401         /* type 2 wave data */
4402         dst[(*no_fields)++] = 2;
4403         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_STATUS);
4404         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_PC_LO);
4405         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_PC_HI);
4406         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_EXEC_LO);
4407         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_EXEC_HI);
4408         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_HW_ID1);
4409         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_HW_ID2);
4410         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_INST_DW0);
4411         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_GPR_ALLOC);
4412         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_LDS_ALLOC);
4413         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_TRAPSTS);
4414         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_IB_STS);
4415         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_IB_STS2);
4416         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_IB_DBG1);
4417         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_M0);
4418 }
4419
4420 static void gfx_v10_0_read_wave_sgprs(struct amdgpu_device *adev, uint32_t simd,
4421                                      uint32_t wave, uint32_t start,
4422                                      uint32_t size, uint32_t *dst)
4423 {
4424         WARN_ON(simd != 0);
4425
4426         wave_read_regs(
4427                 adev, wave, 0, start + SQIND_WAVE_SGPRS_OFFSET, size,
4428                 dst);
4429 }
4430
4431 static void gfx_v10_0_read_wave_vgprs(struct amdgpu_device *adev, uint32_t simd,
4432                                       uint32_t wave, uint32_t thread,
4433                                       uint32_t start, uint32_t size,
4434                                       uint32_t *dst)
4435 {
4436         wave_read_regs(
4437                 adev, wave, thread,
4438                 start + SQIND_WAVE_VGPRS_OFFSET, size, dst);
4439 }
4440
4441 static void gfx_v10_0_select_me_pipe_q(struct amdgpu_device *adev,
4442                                        u32 me, u32 pipe, u32 q, u32 vm)
4443 {
4444         nv_grbm_select(adev, me, pipe, q, vm);
4445 }
4446
4447 static void gfx_v10_0_update_perfmon_mgcg(struct amdgpu_device *adev,
4448                                           bool enable)
4449 {
4450         uint32_t data, def;
4451
4452         data = def = RREG32_SOC15(GC, 0, mmRLC_PERFMON_CLK_CNTL);
4453
4454         if (enable)
4455                 data |= RLC_PERFMON_CLK_CNTL__PERFMON_CLOCK_STATE_MASK;
4456         else
4457                 data &= ~RLC_PERFMON_CLK_CNTL__PERFMON_CLOCK_STATE_MASK;
4458
4459         if (data != def)
4460                 WREG32_SOC15(GC, 0, mmRLC_PERFMON_CLK_CNTL, data);
4461 }
4462
4463 static const struct amdgpu_gfx_funcs gfx_v10_0_gfx_funcs = {
4464         .get_gpu_clock_counter = &gfx_v10_0_get_gpu_clock_counter,
4465         .select_se_sh = &gfx_v10_0_select_se_sh,
4466         .read_wave_data = &gfx_v10_0_read_wave_data,
4467         .read_wave_sgprs = &gfx_v10_0_read_wave_sgprs,
4468         .read_wave_vgprs = &gfx_v10_0_read_wave_vgprs,
4469         .select_me_pipe_q = &gfx_v10_0_select_me_pipe_q,
4470         .init_spm_golden = &gfx_v10_0_init_spm_golden_registers,
4471         .update_perfmon_mgcg = &gfx_v10_0_update_perfmon_mgcg,
4472 };
4473
4474 static void gfx_v10_0_gpu_early_init(struct amdgpu_device *adev)
4475 {
4476         u32 gb_addr_config;
4477
4478         adev->gfx.funcs = &gfx_v10_0_gfx_funcs;
4479
4480         switch (adev->asic_type) {
4481         case CHIP_NAVI10:
4482         case CHIP_NAVI14:
4483         case CHIP_NAVI12:
4484                 adev->gfx.config.max_hw_contexts = 8;
4485                 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
4486                 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
4487                 adev->gfx.config.sc_hiz_tile_fifo_size = 0;
4488                 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0;
4489                 gb_addr_config = RREG32_SOC15(GC, 0, mmGB_ADDR_CONFIG);
4490                 break;
4491         case CHIP_SIENNA_CICHLID:
4492         case CHIP_NAVY_FLOUNDER:
4493         case CHIP_VANGOGH:
4494         case CHIP_DIMGREY_CAVEFISH:
4495                 adev->gfx.config.max_hw_contexts = 8;
4496                 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
4497                 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
4498                 adev->gfx.config.sc_hiz_tile_fifo_size = 0;
4499                 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0;
4500                 gb_addr_config = RREG32_SOC15(GC, 0, mmGB_ADDR_CONFIG);
4501                 adev->gfx.config.gb_addr_config_fields.num_pkrs =
4502                         1 << REG_GET_FIELD(gb_addr_config, GB_ADDR_CONFIG, NUM_PKRS);
4503                 break;
4504         default:
4505                 BUG();
4506                 break;
4507         }
4508
4509         adev->gfx.config.gb_addr_config = gb_addr_config;
4510
4511         adev->gfx.config.gb_addr_config_fields.num_pipes = 1 <<
4512                         REG_GET_FIELD(adev->gfx.config.gb_addr_config,
4513                                       GB_ADDR_CONFIG, NUM_PIPES);
4514
4515         adev->gfx.config.max_tile_pipes =
4516                 adev->gfx.config.gb_addr_config_fields.num_pipes;
4517
4518         adev->gfx.config.gb_addr_config_fields.max_compress_frags = 1 <<
4519                         REG_GET_FIELD(adev->gfx.config.gb_addr_config,
4520                                       GB_ADDR_CONFIG, MAX_COMPRESSED_FRAGS);
4521         adev->gfx.config.gb_addr_config_fields.num_rb_per_se = 1 <<
4522                         REG_GET_FIELD(adev->gfx.config.gb_addr_config,
4523                                       GB_ADDR_CONFIG, NUM_RB_PER_SE);
4524         adev->gfx.config.gb_addr_config_fields.num_se = 1 <<
4525                         REG_GET_FIELD(adev->gfx.config.gb_addr_config,
4526                                       GB_ADDR_CONFIG, NUM_SHADER_ENGINES);
4527         adev->gfx.config.gb_addr_config_fields.pipe_interleave_size = 1 << (8 +
4528                         REG_GET_FIELD(adev->gfx.config.gb_addr_config,
4529                                       GB_ADDR_CONFIG, PIPE_INTERLEAVE_SIZE));
4530 }
4531
4532 static int gfx_v10_0_gfx_ring_init(struct amdgpu_device *adev, int ring_id,
4533                                    int me, int pipe, int queue)
4534 {
4535         int r;
4536         struct amdgpu_ring *ring;
4537         unsigned int irq_type;
4538
4539         ring = &adev->gfx.gfx_ring[ring_id];
4540
4541         ring->me = me;
4542         ring->pipe = pipe;
4543         ring->queue = queue;
4544
4545         ring->ring_obj = NULL;
4546         ring->use_doorbell = true;
4547
4548         if (!ring_id)
4549                 ring->doorbell_index = adev->doorbell_index.gfx_ring0 << 1;
4550         else
4551                 ring->doorbell_index = adev->doorbell_index.gfx_ring1 << 1;
4552         sprintf(ring->name, "gfx_%d.%d.%d", ring->me, ring->pipe, ring->queue);
4553
4554         irq_type = AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP + ring->pipe;
4555         r = amdgpu_ring_init(adev, ring, 1024, &adev->gfx.eop_irq, irq_type,
4556                              AMDGPU_RING_PRIO_DEFAULT, NULL);
4557         if (r)
4558                 return r;
4559         return 0;
4560 }
4561
4562 static int gfx_v10_0_compute_ring_init(struct amdgpu_device *adev, int ring_id,
4563                                        int mec, int pipe, int queue)
4564 {
4565         int r;
4566         unsigned irq_type;
4567         struct amdgpu_ring *ring;
4568         unsigned int hw_prio;
4569
4570         ring = &adev->gfx.compute_ring[ring_id];
4571
4572         /* mec0 is me1 */
4573         ring->me = mec + 1;
4574         ring->pipe = pipe;
4575         ring->queue = queue;
4576
4577         ring->ring_obj = NULL;
4578         ring->use_doorbell = true;
4579         ring->doorbell_index = (adev->doorbell_index.mec_ring0 + ring_id) << 1;
4580         ring->eop_gpu_addr = adev->gfx.mec.hpd_eop_gpu_addr
4581                                 + (ring_id * GFX10_MEC_HPD_SIZE);
4582         sprintf(ring->name, "comp_%d.%d.%d", ring->me, ring->pipe, ring->queue);
4583
4584         irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP
4585                 + ((ring->me - 1) * adev->gfx.mec.num_pipe_per_mec)
4586                 + ring->pipe;
4587         hw_prio = amdgpu_gfx_is_high_priority_compute_queue(adev, ring) ?
4588                         AMDGPU_GFX_PIPE_PRIO_HIGH : AMDGPU_GFX_PIPE_PRIO_NORMAL;
4589         /* type-2 packets are deprecated on MEC, use type-3 instead */
4590         r = amdgpu_ring_init(adev, ring, 1024, &adev->gfx.eop_irq, irq_type,
4591                              hw_prio, NULL);
4592         if (r)
4593                 return r;
4594
4595         return 0;
4596 }
4597
4598 static int gfx_v10_0_sw_init(void *handle)
4599 {
4600         int i, j, k, r, ring_id = 0;
4601         struct amdgpu_kiq *kiq;
4602         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4603
4604         switch (adev->asic_type) {
4605         case CHIP_NAVI10:
4606         case CHIP_NAVI14:
4607         case CHIP_NAVI12:
4608                 adev->gfx.me.num_me = 1;
4609                 adev->gfx.me.num_pipe_per_me = 1;
4610                 adev->gfx.me.num_queue_per_pipe = 1;
4611                 adev->gfx.mec.num_mec = 2;
4612                 adev->gfx.mec.num_pipe_per_mec = 4;
4613                 adev->gfx.mec.num_queue_per_pipe = 8;
4614                 break;
4615         case CHIP_SIENNA_CICHLID:
4616         case CHIP_NAVY_FLOUNDER:
4617         case CHIP_VANGOGH:
4618         case CHIP_DIMGREY_CAVEFISH:
4619                 adev->gfx.me.num_me = 1;
4620                 adev->gfx.me.num_pipe_per_me = 1;
4621                 adev->gfx.me.num_queue_per_pipe = 1;
4622                 adev->gfx.mec.num_mec = 2;
4623                 adev->gfx.mec.num_pipe_per_mec = 4;
4624                 adev->gfx.mec.num_queue_per_pipe = 4;
4625                 break;
4626         default:
4627                 adev->gfx.me.num_me = 1;
4628                 adev->gfx.me.num_pipe_per_me = 1;
4629                 adev->gfx.me.num_queue_per_pipe = 1;
4630                 adev->gfx.mec.num_mec = 1;
4631                 adev->gfx.mec.num_pipe_per_mec = 4;
4632                 adev->gfx.mec.num_queue_per_pipe = 8;
4633                 break;
4634         }
4635
4636         /* KIQ event */
4637         r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP,
4638                               GFX_10_1__SRCID__CP_IB2_INTERRUPT_PKT,
4639                               &adev->gfx.kiq.irq);
4640         if (r)
4641                 return r;
4642
4643         /* EOP Event */
4644         r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP,
4645                               GFX_10_1__SRCID__CP_EOP_INTERRUPT,
4646                               &adev->gfx.eop_irq);
4647         if (r)
4648                 return r;
4649
4650         /* Privileged reg */
4651         r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, GFX_10_1__SRCID__CP_PRIV_REG_FAULT,
4652                               &adev->gfx.priv_reg_irq);
4653         if (r)
4654                 return r;
4655
4656         /* Privileged inst */
4657         r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, GFX_10_1__SRCID__CP_PRIV_INSTR_FAULT,
4658                               &adev->gfx.priv_inst_irq);
4659         if (r)
4660                 return r;
4661
4662         adev->gfx.gfx_current_status = AMDGPU_GFX_NORMAL_MODE;
4663
4664         gfx_v10_0_scratch_init(adev);
4665
4666         r = gfx_v10_0_me_init(adev);
4667         if (r)
4668                 return r;
4669
4670         r = gfx_v10_0_rlc_init(adev);
4671         if (r) {
4672                 DRM_ERROR("Failed to init rlc BOs!\n");
4673                 return r;
4674         }
4675
4676         r = gfx_v10_0_mec_init(adev);
4677         if (r) {
4678                 DRM_ERROR("Failed to init MEC BOs!\n");
4679                 return r;
4680         }
4681
4682         /* set up the gfx ring */
4683         for (i = 0; i < adev->gfx.me.num_me; i++) {
4684                 for (j = 0; j < adev->gfx.me.num_queue_per_pipe; j++) {
4685                         for (k = 0; k < adev->gfx.me.num_pipe_per_me; k++) {
4686                                 if (!amdgpu_gfx_is_me_queue_enabled(adev, i, k, j))
4687                                         continue;
4688
4689                                 r = gfx_v10_0_gfx_ring_init(adev, ring_id,
4690                                                             i, k, j);
4691                                 if (r)
4692                                         return r;
4693                                 ring_id++;
4694                         }
4695                 }
4696         }
4697
4698         ring_id = 0;
4699         /* set up the compute queues - allocate horizontally across pipes */
4700         for (i = 0; i < adev->gfx.mec.num_mec; ++i) {
4701                 for (j = 0; j < adev->gfx.mec.num_queue_per_pipe; j++) {
4702                         for (k = 0; k < adev->gfx.mec.num_pipe_per_mec; k++) {
4703                                 if (!amdgpu_gfx_is_mec_queue_enabled(adev, i, k,
4704                                                                      j))
4705                                         continue;
4706
4707                                 r = gfx_v10_0_compute_ring_init(adev, ring_id,
4708                                                                 i, k, j);
4709                                 if (r)
4710                                         return r;
4711
4712                                 ring_id++;
4713                         }
4714                 }
4715         }
4716
4717         r = amdgpu_gfx_kiq_init(adev, GFX10_MEC_HPD_SIZE);
4718         if (r) {
4719                 DRM_ERROR("Failed to init KIQ BOs!\n");
4720                 return r;
4721         }
4722
4723         kiq = &adev->gfx.kiq;
4724         r = amdgpu_gfx_kiq_init_ring(adev, &kiq->ring, &kiq->irq);
4725         if (r)
4726                 return r;
4727
4728         r = amdgpu_gfx_mqd_sw_init(adev, sizeof(struct v10_compute_mqd));
4729         if (r)
4730                 return r;
4731
4732         /* allocate visible FB for rlc auto-loading fw */
4733         if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) {
4734                 r = gfx_v10_0_rlc_backdoor_autoload_buffer_init(adev);
4735                 if (r)
4736                         return r;
4737         }
4738
4739         adev->gfx.ce_ram_size = F32_CE_PROGRAM_RAM_SIZE;
4740
4741         gfx_v10_0_gpu_early_init(adev);
4742
4743         return 0;
4744 }
4745
4746 static void gfx_v10_0_pfp_fini(struct amdgpu_device *adev)
4747 {
4748         amdgpu_bo_free_kernel(&adev->gfx.pfp.pfp_fw_obj,
4749                               &adev->gfx.pfp.pfp_fw_gpu_addr,
4750                               (void **)&adev->gfx.pfp.pfp_fw_ptr);
4751 }
4752
4753 static void gfx_v10_0_ce_fini(struct amdgpu_device *adev)
4754 {
4755         amdgpu_bo_free_kernel(&adev->gfx.ce.ce_fw_obj,
4756                               &adev->gfx.ce.ce_fw_gpu_addr,
4757                               (void **)&adev->gfx.ce.ce_fw_ptr);
4758 }
4759
4760 static void gfx_v10_0_me_fini(struct amdgpu_device *adev)
4761 {
4762         amdgpu_bo_free_kernel(&adev->gfx.me.me_fw_obj,
4763                               &adev->gfx.me.me_fw_gpu_addr,
4764                               (void **)&adev->gfx.me.me_fw_ptr);
4765 }
4766
4767 static int gfx_v10_0_sw_fini(void *handle)
4768 {
4769         int i;
4770         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4771
4772         for (i = 0; i < adev->gfx.num_gfx_rings; i++)
4773                 amdgpu_ring_fini(&adev->gfx.gfx_ring[i]);
4774         for (i = 0; i < adev->gfx.num_compute_rings; i++)
4775                 amdgpu_ring_fini(&adev->gfx.compute_ring[i]);
4776
4777         amdgpu_gfx_mqd_sw_fini(adev);
4778         amdgpu_gfx_kiq_free_ring(&adev->gfx.kiq.ring);
4779         amdgpu_gfx_kiq_fini(adev);
4780
4781         gfx_v10_0_pfp_fini(adev);
4782         gfx_v10_0_ce_fini(adev);
4783         gfx_v10_0_me_fini(adev);
4784         gfx_v10_0_rlc_fini(adev);
4785         gfx_v10_0_mec_fini(adev);
4786
4787         if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO)
4788                 gfx_v10_0_rlc_backdoor_autoload_buffer_fini(adev);
4789
4790         gfx_v10_0_free_microcode(adev);
4791
4792         return 0;
4793 }
4794
4795 static void gfx_v10_0_select_se_sh(struct amdgpu_device *adev, u32 se_num,
4796                                    u32 sh_num, u32 instance)
4797 {
4798         u32 data;
4799
4800         if (instance == 0xffffffff)
4801                 data = REG_SET_FIELD(0, GRBM_GFX_INDEX,
4802                                      INSTANCE_BROADCAST_WRITES, 1);
4803         else
4804                 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_INDEX,
4805                                      instance);
4806
4807         if (se_num == 0xffffffff)
4808                 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_BROADCAST_WRITES,
4809                                      1);
4810         else
4811                 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_INDEX, se_num);
4812
4813         if (sh_num == 0xffffffff)
4814                 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SA_BROADCAST_WRITES,
4815                                      1);
4816         else
4817                 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SA_INDEX, sh_num);
4818
4819         WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, data);
4820 }
4821
4822 static u32 gfx_v10_0_get_rb_active_bitmap(struct amdgpu_device *adev)
4823 {
4824         u32 data, mask;
4825
4826         data = RREG32_SOC15(GC, 0, mmCC_RB_BACKEND_DISABLE);
4827         data |= RREG32_SOC15(GC, 0, mmGC_USER_RB_BACKEND_DISABLE);
4828
4829         data &= CC_RB_BACKEND_DISABLE__BACKEND_DISABLE_MASK;
4830         data >>= GC_USER_RB_BACKEND_DISABLE__BACKEND_DISABLE__SHIFT;
4831
4832         mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_backends_per_se /
4833                                          adev->gfx.config.max_sh_per_se);
4834
4835         return (~data) & mask;
4836 }
4837
4838 static void gfx_v10_0_setup_rb(struct amdgpu_device *adev)
4839 {
4840         int i, j;
4841         u32 data;
4842         u32 active_rbs = 0;
4843         u32 bitmap;
4844         u32 rb_bitmap_width_per_sh = adev->gfx.config.max_backends_per_se /
4845                                         adev->gfx.config.max_sh_per_se;
4846
4847         mutex_lock(&adev->grbm_idx_mutex);
4848         for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
4849                 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
4850                         bitmap = i * adev->gfx.config.max_sh_per_se + j;
4851                         if ((adev->asic_type == CHIP_SIENNA_CICHLID) &&
4852                             ((gfx_v10_3_get_disabled_sa(adev) >> bitmap) & 1))
4853                                 continue;
4854                         gfx_v10_0_select_se_sh(adev, i, j, 0xffffffff);
4855                         data = gfx_v10_0_get_rb_active_bitmap(adev);
4856                         active_rbs |= data << ((i * adev->gfx.config.max_sh_per_se + j) *
4857                                                rb_bitmap_width_per_sh);
4858                 }
4859         }
4860         gfx_v10_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
4861         mutex_unlock(&adev->grbm_idx_mutex);
4862
4863         adev->gfx.config.backend_enable_mask = active_rbs;
4864         adev->gfx.config.num_rbs = hweight32(active_rbs);
4865 }
4866
4867 static u32 gfx_v10_0_init_pa_sc_tile_steering_override(struct amdgpu_device *adev)
4868 {
4869         uint32_t num_sc;
4870         uint32_t enabled_rb_per_sh;
4871         uint32_t active_rb_bitmap;
4872         uint32_t num_rb_per_sc;
4873         uint32_t num_packer_per_sc;
4874         uint32_t pa_sc_tile_steering_override;
4875
4876         /* for ASICs that integrates GFX v10.3
4877          * pa_sc_tile_steering_override should be set to 0 */
4878         if (adev->asic_type >= CHIP_SIENNA_CICHLID)
4879                 return 0;
4880
4881         /* init num_sc */
4882         num_sc = adev->gfx.config.max_shader_engines * adev->gfx.config.max_sh_per_se *
4883                         adev->gfx.config.num_sc_per_sh;
4884         /* init num_rb_per_sc */
4885         active_rb_bitmap = gfx_v10_0_get_rb_active_bitmap(adev);
4886         enabled_rb_per_sh = hweight32(active_rb_bitmap);
4887         num_rb_per_sc = enabled_rb_per_sh / adev->gfx.config.num_sc_per_sh;
4888         /* init num_packer_per_sc */
4889         num_packer_per_sc = adev->gfx.config.num_packer_per_sc;
4890
4891         pa_sc_tile_steering_override = 0;
4892         pa_sc_tile_steering_override |=
4893                 (order_base_2(num_sc) << PA_SC_TILE_STEERING_OVERRIDE__NUM_SC__SHIFT) &
4894                 PA_SC_TILE_STEERING_OVERRIDE__NUM_SC_MASK;
4895         pa_sc_tile_steering_override |=
4896                 (order_base_2(num_rb_per_sc) << PA_SC_TILE_STEERING_OVERRIDE__NUM_RB_PER_SC__SHIFT) &
4897                 PA_SC_TILE_STEERING_OVERRIDE__NUM_RB_PER_SC_MASK;
4898         pa_sc_tile_steering_override |=
4899                 (order_base_2(num_packer_per_sc) << PA_SC_TILE_STEERING_OVERRIDE__NUM_PACKER_PER_SC__SHIFT) &
4900                 PA_SC_TILE_STEERING_OVERRIDE__NUM_PACKER_PER_SC_MASK;
4901
4902         return pa_sc_tile_steering_override;
4903 }
4904
4905 #define DEFAULT_SH_MEM_BASES    (0x6000)
4906
4907 static void gfx_v10_0_init_compute_vmid(struct amdgpu_device *adev)
4908 {
4909         int i;
4910         uint32_t sh_mem_bases;
4911
4912         /*
4913          * Configure apertures:
4914          * LDS:         0x60000000'00000000 - 0x60000001'00000000 (4GB)
4915          * Scratch:     0x60000001'00000000 - 0x60000002'00000000 (4GB)
4916          * GPUVM:       0x60010000'00000000 - 0x60020000'00000000 (1TB)
4917          */
4918         sh_mem_bases = DEFAULT_SH_MEM_BASES | (DEFAULT_SH_MEM_BASES << 16);
4919
4920         mutex_lock(&adev->srbm_mutex);
4921         for (i = adev->vm_manager.first_kfd_vmid; i < AMDGPU_NUM_VMID; i++) {
4922                 nv_grbm_select(adev, 0, 0, 0, i);
4923                 /* CP and shaders */
4924                 WREG32_SOC15(GC, 0, mmSH_MEM_CONFIG, DEFAULT_SH_MEM_CONFIG);
4925                 WREG32_SOC15(GC, 0, mmSH_MEM_BASES, sh_mem_bases);
4926         }
4927         nv_grbm_select(adev, 0, 0, 0, 0);
4928         mutex_unlock(&adev->srbm_mutex);
4929
4930         /* Initialize all compute VMIDs to have no GDS, GWS, or OA
4931            acccess. These should be enabled by FW for target VMIDs. */
4932         for (i = adev->vm_manager.first_kfd_vmid; i < AMDGPU_NUM_VMID; i++) {
4933                 WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_BASE, 2 * i, 0);
4934                 WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_SIZE, 2 * i, 0);
4935                 WREG32_SOC15_OFFSET(GC, 0, mmGDS_GWS_VMID0, i, 0);
4936                 WREG32_SOC15_OFFSET(GC, 0, mmGDS_OA_VMID0, i, 0);
4937         }
4938 }
4939
4940 static void gfx_v10_0_init_gds_vmid(struct amdgpu_device *adev)
4941 {
4942         int vmid;
4943
4944         /*
4945          * Initialize all compute and user-gfx VMIDs to have no GDS, GWS, or OA
4946          * access. Compute VMIDs should be enabled by FW for target VMIDs,
4947          * the driver can enable them for graphics. VMID0 should maintain
4948          * access so that HWS firmware can save/restore entries.
4949          */
4950         for (vmid = 1; vmid < AMDGPU_NUM_VMID; vmid++) {
4951                 WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_BASE, 2 * vmid, 0);
4952                 WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_SIZE, 2 * vmid, 0);
4953                 WREG32_SOC15_OFFSET(GC, 0, mmGDS_GWS_VMID0, vmid, 0);
4954                 WREG32_SOC15_OFFSET(GC, 0, mmGDS_OA_VMID0, vmid, 0);
4955         }
4956 }
4957
4958
4959 static void gfx_v10_0_tcp_harvest(struct amdgpu_device *adev)
4960 {
4961         int i, j, k;
4962         int max_wgp_per_sh = adev->gfx.config.max_cu_per_sh >> 1;
4963         u32 tmp, wgp_active_bitmap = 0;
4964         u32 gcrd_targets_disable_tcp = 0;
4965         u32 utcl_invreq_disable = 0;
4966         /*
4967          * GCRD_TARGETS_DISABLE field contains
4968          * for Navi10/Navi12: GL1C=[18:15], SQC=[14:10], TCP=[9:0]
4969          * for Navi14: GL1C=[21:18], SQC=[17:12], TCP=[11:0]
4970          */
4971         u32 gcrd_targets_disable_mask = amdgpu_gfx_create_bitmask(
4972                 2 * max_wgp_per_sh + /* TCP */
4973                 max_wgp_per_sh + /* SQC */
4974                 4); /* GL1C */
4975         /*
4976          * UTCL1_UTCL0_INVREQ_DISABLE field contains
4977          * for Navi10Navi12: SQG=[24], RMI=[23:20], SQC=[19:10], TCP=[9:0]
4978          * for Navi14: SQG=[28], RMI=[27:24], SQC=[23:12], TCP=[11:0]
4979          */
4980         u32 utcl_invreq_disable_mask = amdgpu_gfx_create_bitmask(
4981                 2 * max_wgp_per_sh + /* TCP */
4982                 2 * max_wgp_per_sh + /* SQC */
4983                 4 + /* RMI */
4984                 1); /* SQG */
4985
4986         if (adev->asic_type == CHIP_NAVI10 ||
4987             adev->asic_type == CHIP_NAVI14 ||
4988             adev->asic_type == CHIP_NAVI12) {
4989                 mutex_lock(&adev->grbm_idx_mutex);
4990                 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
4991                         for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
4992                                 gfx_v10_0_select_se_sh(adev, i, j, 0xffffffff);
4993                                 wgp_active_bitmap = gfx_v10_0_get_wgp_active_bitmap_per_sh(adev);
4994                                 /*
4995                                  * Set corresponding TCP bits for the inactive WGPs in
4996                                  * GCRD_SA_TARGETS_DISABLE
4997                                  */
4998                                 gcrd_targets_disable_tcp = 0;
4999                                 /* Set TCP & SQC bits in UTCL1_UTCL0_INVREQ_DISABLE */
5000                                 utcl_invreq_disable = 0;
5001
5002                                 for (k = 0; k < max_wgp_per_sh; k++) {
5003                                         if (!(wgp_active_bitmap & (1 << k))) {
5004                                                 gcrd_targets_disable_tcp |= 3 << (2 * k);
5005                                                 utcl_invreq_disable |= (3 << (2 * k)) |
5006                                                         (3 << (2 * (max_wgp_per_sh + k)));
5007                                         }
5008                                 }
5009
5010                                 tmp = RREG32_SOC15(GC, 0, mmUTCL1_UTCL0_INVREQ_DISABLE);
5011                                 /* only override TCP & SQC bits */
5012                                 tmp &= 0xffffffff << (4 * max_wgp_per_sh);
5013                                 tmp |= (utcl_invreq_disable & utcl_invreq_disable_mask);
5014                                 WREG32_SOC15(GC, 0, mmUTCL1_UTCL0_INVREQ_DISABLE, tmp);
5015
5016                                 tmp = RREG32_SOC15(GC, 0, mmGCRD_SA_TARGETS_DISABLE);
5017                                 /* only override TCP bits */
5018                                 tmp &= 0xffffffff << (2 * max_wgp_per_sh);
5019                                 tmp |= (gcrd_targets_disable_tcp & gcrd_targets_disable_mask);
5020                                 WREG32_SOC15(GC, 0, mmGCRD_SA_TARGETS_DISABLE, tmp);
5021                         }
5022                 }
5023
5024                 gfx_v10_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
5025                 mutex_unlock(&adev->grbm_idx_mutex);
5026         }
5027 }
5028
5029 static void gfx_v10_0_get_tcc_info(struct amdgpu_device *adev)
5030 {
5031         /* TCCs are global (not instanced). */
5032         uint32_t tcc_disable;
5033
5034         if (adev->asic_type >= CHIP_SIENNA_CICHLID) {
5035                 tcc_disable = RREG32_SOC15(GC, 0, mmCGTS_TCC_DISABLE_gc_10_3) |
5036                               RREG32_SOC15(GC, 0, mmCGTS_USER_TCC_DISABLE_gc_10_3);
5037         } else {
5038                 tcc_disable = RREG32_SOC15(GC, 0, mmCGTS_TCC_DISABLE) |
5039                               RREG32_SOC15(GC, 0, mmCGTS_USER_TCC_DISABLE);
5040         }
5041
5042         adev->gfx.config.tcc_disabled_mask =
5043                 REG_GET_FIELD(tcc_disable, CGTS_TCC_DISABLE, TCC_DISABLE) |
5044                 (REG_GET_FIELD(tcc_disable, CGTS_TCC_DISABLE, HI_TCC_DISABLE) << 16);
5045 }
5046
5047 static void gfx_v10_0_constants_init(struct amdgpu_device *adev)
5048 {
5049         u32 tmp;
5050         int i;
5051
5052         WREG32_FIELD15(GC, 0, GRBM_CNTL, READ_TIMEOUT, 0xff);
5053
5054         gfx_v10_0_setup_rb(adev);
5055         gfx_v10_0_get_cu_info(adev, &adev->gfx.cu_info);
5056         gfx_v10_0_get_tcc_info(adev);
5057         adev->gfx.config.pa_sc_tile_steering_override =
5058                 gfx_v10_0_init_pa_sc_tile_steering_override(adev);
5059
5060         /* XXX SH_MEM regs */
5061         /* where to put LDS, scratch, GPUVM in FSA64 space */
5062         mutex_lock(&adev->srbm_mutex);
5063         for (i = 0; i < adev->vm_manager.id_mgr[AMDGPU_GFXHUB_0].num_ids; i++) {
5064                 nv_grbm_select(adev, 0, 0, 0, i);
5065                 /* CP and shaders */
5066                 WREG32_SOC15(GC, 0, mmSH_MEM_CONFIG, DEFAULT_SH_MEM_CONFIG);
5067                 if (i != 0) {
5068                         tmp = REG_SET_FIELD(0, SH_MEM_BASES, PRIVATE_BASE,
5069                                 (adev->gmc.private_aperture_start >> 48));
5070                         tmp = REG_SET_FIELD(tmp, SH_MEM_BASES, SHARED_BASE,
5071                                 (adev->gmc.shared_aperture_start >> 48));
5072                         WREG32_SOC15(GC, 0, mmSH_MEM_BASES, tmp);
5073                 }
5074         }
5075         nv_grbm_select(adev, 0, 0, 0, 0);
5076
5077         mutex_unlock(&adev->srbm_mutex);
5078
5079         gfx_v10_0_init_compute_vmid(adev);
5080         gfx_v10_0_init_gds_vmid(adev);
5081
5082 }
5083
5084 static void gfx_v10_0_enable_gui_idle_interrupt(struct amdgpu_device *adev,
5085                                                bool enable)
5086 {
5087         u32 tmp;
5088
5089         if (amdgpu_sriov_vf(adev))
5090                 return;
5091
5092         tmp = RREG32_SOC15(GC, 0, mmCP_INT_CNTL_RING0);
5093
5094         tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_BUSY_INT_ENABLE,
5095                             enable ? 1 : 0);
5096         tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_EMPTY_INT_ENABLE,
5097                             enable ? 1 : 0);
5098         tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CMP_BUSY_INT_ENABLE,
5099                             enable ? 1 : 0);
5100         tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, GFX_IDLE_INT_ENABLE,
5101                             enable ? 1 : 0);
5102
5103         WREG32_SOC15(GC, 0, mmCP_INT_CNTL_RING0, tmp);
5104 }
5105
5106 static int gfx_v10_0_init_csb(struct amdgpu_device *adev)
5107 {
5108         adev->gfx.rlc.funcs->get_csb_buffer(adev, adev->gfx.rlc.cs_ptr);
5109
5110         /* csib */
5111         if (adev->asic_type == CHIP_NAVI12) {
5112                 WREG32_SOC15_RLC(GC, 0, mmRLC_CSIB_ADDR_HI,
5113                                 adev->gfx.rlc.clear_state_gpu_addr >> 32);
5114                 WREG32_SOC15_RLC(GC, 0, mmRLC_CSIB_ADDR_LO,
5115                                 adev->gfx.rlc.clear_state_gpu_addr & 0xfffffffc);
5116                 WREG32_SOC15_RLC(GC, 0, mmRLC_CSIB_LENGTH, adev->gfx.rlc.clear_state_size);
5117         } else {
5118                 WREG32_SOC15(GC, 0, mmRLC_CSIB_ADDR_HI,
5119                                 adev->gfx.rlc.clear_state_gpu_addr >> 32);
5120                 WREG32_SOC15(GC, 0, mmRLC_CSIB_ADDR_LO,
5121                                 adev->gfx.rlc.clear_state_gpu_addr & 0xfffffffc);
5122                 WREG32_SOC15(GC, 0, mmRLC_CSIB_LENGTH, adev->gfx.rlc.clear_state_size);
5123         }
5124         return 0;
5125 }
5126
5127 static void gfx_v10_0_rlc_stop(struct amdgpu_device *adev)
5128 {
5129         u32 tmp = RREG32_SOC15(GC, 0, mmRLC_CNTL);
5130
5131         tmp = REG_SET_FIELD(tmp, RLC_CNTL, RLC_ENABLE_F32, 0);
5132         WREG32_SOC15(GC, 0, mmRLC_CNTL, tmp);
5133 }
5134
5135 static void gfx_v10_0_rlc_reset(struct amdgpu_device *adev)
5136 {
5137         WREG32_FIELD15(GC, 0, GRBM_SOFT_RESET, SOFT_RESET_RLC, 1);
5138         udelay(50);
5139         WREG32_FIELD15(GC, 0, GRBM_SOFT_RESET, SOFT_RESET_RLC, 0);
5140         udelay(50);
5141 }
5142
5143 static void gfx_v10_0_rlc_smu_handshake_cntl(struct amdgpu_device *adev,
5144                                              bool enable)
5145 {
5146         uint32_t rlc_pg_cntl;
5147
5148         rlc_pg_cntl = RREG32_SOC15(GC, 0, mmRLC_PG_CNTL);
5149
5150         if (!enable) {
5151                 /* RLC_PG_CNTL[23] = 0 (default)
5152                  * RLC will wait for handshake acks with SMU
5153                  * GFXOFF will be enabled
5154                  * RLC_PG_CNTL[23] = 1
5155                  * RLC will not issue any message to SMU
5156                  * hence no handshake between SMU & RLC
5157                  * GFXOFF will be disabled
5158                  */
5159                 rlc_pg_cntl |= 0x800000;
5160         } else
5161                 rlc_pg_cntl &= ~0x800000;
5162         WREG32_SOC15(GC, 0, mmRLC_PG_CNTL, rlc_pg_cntl);
5163 }
5164
5165 static void gfx_v10_0_rlc_start(struct amdgpu_device *adev)
5166 {
5167         /* TODO: enable rlc & smu handshake until smu
5168          * and gfxoff feature works as expected */
5169         if (!(amdgpu_pp_feature_mask & PP_GFXOFF_MASK))
5170                 gfx_v10_0_rlc_smu_handshake_cntl(adev, false);
5171
5172         WREG32_FIELD15(GC, 0, RLC_CNTL, RLC_ENABLE_F32, 1);
5173         udelay(50);
5174 }
5175
5176 static void gfx_v10_0_rlc_enable_srm(struct amdgpu_device *adev)
5177 {
5178         uint32_t tmp;
5179
5180         /* enable Save Restore Machine */
5181         tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_CNTL));
5182         tmp |= RLC_SRM_CNTL__AUTO_INCR_ADDR_MASK;
5183         tmp |= RLC_SRM_CNTL__SRM_ENABLE_MASK;
5184         WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_CNTL), tmp);
5185 }
5186
5187 static int gfx_v10_0_rlc_load_microcode(struct amdgpu_device *adev)
5188 {
5189         const struct rlc_firmware_header_v2_0 *hdr;
5190         const __le32 *fw_data;
5191         unsigned i, fw_size;
5192
5193         if (!adev->gfx.rlc_fw)
5194                 return -EINVAL;
5195
5196         hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data;
5197         amdgpu_ucode_print_rlc_hdr(&hdr->header);
5198
5199         fw_data = (const __le32 *)(adev->gfx.rlc_fw->data +
5200                            le32_to_cpu(hdr->header.ucode_array_offset_bytes));
5201         fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
5202
5203         WREG32_SOC15(GC, 0, mmRLC_GPM_UCODE_ADDR,
5204                      RLCG_UCODE_LOADING_START_ADDRESS);
5205
5206         for (i = 0; i < fw_size; i++)
5207                 WREG32_SOC15(GC, 0, mmRLC_GPM_UCODE_DATA,
5208                              le32_to_cpup(fw_data++));
5209
5210         WREG32_SOC15(GC, 0, mmRLC_GPM_UCODE_ADDR, adev->gfx.rlc_fw_version);
5211
5212         return 0;
5213 }
5214
5215 static int gfx_v10_0_rlc_resume(struct amdgpu_device *adev)
5216 {
5217         int r;
5218
5219         if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
5220
5221                 r = gfx_v10_0_wait_for_rlc_autoload_complete(adev);
5222                 if (r)
5223                         return r;
5224
5225                 gfx_v10_0_init_csb(adev);
5226
5227                 if (!amdgpu_sriov_vf(adev)) /* enable RLC SRM */
5228                         gfx_v10_0_rlc_enable_srm(adev);
5229         } else {
5230                 if (amdgpu_sriov_vf(adev)) {
5231                         gfx_v10_0_init_csb(adev);
5232                         return 0;
5233                 }
5234
5235                 adev->gfx.rlc.funcs->stop(adev);
5236
5237                 /* disable CG */
5238                 WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL, 0);
5239
5240                 /* disable PG */
5241                 WREG32_SOC15(GC, 0, mmRLC_PG_CNTL, 0);
5242
5243                 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) {
5244                         /* legacy rlc firmware loading */
5245                         r = gfx_v10_0_rlc_load_microcode(adev);
5246                         if (r)
5247                                 return r;
5248                 } else if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) {
5249                         /* rlc backdoor autoload firmware */
5250                         r = gfx_v10_0_rlc_backdoor_autoload_enable(adev);
5251                         if (r)
5252                                 return r;
5253                 }
5254
5255                 gfx_v10_0_init_csb(adev);
5256
5257                 adev->gfx.rlc.funcs->start(adev);
5258
5259                 if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) {
5260                         r = gfx_v10_0_wait_for_rlc_autoload_complete(adev);
5261                         if (r)
5262                                 return r;
5263                 }
5264         }
5265         return 0;
5266 }
5267
5268 static struct {
5269         FIRMWARE_ID     id;
5270         unsigned int    offset;
5271         unsigned int    size;
5272 } rlc_autoload_info[FIRMWARE_ID_MAX];
5273
5274 static int gfx_v10_0_parse_rlc_toc(struct amdgpu_device *adev)
5275 {
5276         int ret;
5277         RLC_TABLE_OF_CONTENT *rlc_toc;
5278
5279         ret = amdgpu_bo_create_reserved(adev, adev->psp.toc_bin_size, PAGE_SIZE,
5280                                         AMDGPU_GEM_DOMAIN_GTT,
5281                                         &adev->gfx.rlc.rlc_toc_bo,
5282                                         &adev->gfx.rlc.rlc_toc_gpu_addr,
5283                                         (void **)&adev->gfx.rlc.rlc_toc_buf);
5284         if (ret) {
5285                 dev_err(adev->dev, "(%d) failed to create rlc toc bo\n", ret);
5286                 return ret;
5287         }
5288
5289         /* Copy toc from psp sos fw to rlc toc buffer */
5290         memcpy(adev->gfx.rlc.rlc_toc_buf, adev->psp.toc_start_addr, adev->psp.toc_bin_size);
5291
5292         rlc_toc = (RLC_TABLE_OF_CONTENT *)adev->gfx.rlc.rlc_toc_buf;
5293         while (rlc_toc && (rlc_toc->id > FIRMWARE_ID_INVALID) &&
5294                 (rlc_toc->id < FIRMWARE_ID_MAX)) {
5295                 if ((rlc_toc->id >= FIRMWARE_ID_CP_CE) &&
5296                     (rlc_toc->id <= FIRMWARE_ID_CP_MES)) {
5297                         /* Offset needs 4KB alignment */
5298                         rlc_toc->offset = ALIGN(rlc_toc->offset * 4, PAGE_SIZE);
5299                 }
5300
5301                 rlc_autoload_info[rlc_toc->id].id = rlc_toc->id;
5302                 rlc_autoload_info[rlc_toc->id].offset = rlc_toc->offset * 4;
5303                 rlc_autoload_info[rlc_toc->id].size = rlc_toc->size * 4;
5304
5305                 rlc_toc++;
5306         }
5307
5308         return 0;
5309 }
5310
5311 static uint32_t gfx_v10_0_calc_toc_total_size(struct amdgpu_device *adev)
5312 {
5313         uint32_t total_size = 0;
5314         FIRMWARE_ID id;
5315         int ret;
5316
5317         ret = gfx_v10_0_parse_rlc_toc(adev);
5318         if (ret) {
5319                 dev_err(adev->dev, "failed to parse rlc toc\n");
5320                 return 0;
5321         }
5322
5323         for (id = FIRMWARE_ID_RLC_G_UCODE; id < FIRMWARE_ID_MAX; id++)
5324                 total_size += rlc_autoload_info[id].size;
5325
5326         /* In case the offset in rlc toc ucode is aligned */
5327         if (total_size < rlc_autoload_info[FIRMWARE_ID_MAX-1].offset)
5328                 total_size = rlc_autoload_info[FIRMWARE_ID_MAX-1].offset +
5329                                 rlc_autoload_info[FIRMWARE_ID_MAX-1].size;
5330
5331         return total_size;
5332 }
5333
5334 static int gfx_v10_0_rlc_backdoor_autoload_buffer_init(struct amdgpu_device *adev)
5335 {
5336         int r;
5337         uint32_t total_size;
5338
5339         total_size = gfx_v10_0_calc_toc_total_size(adev);
5340
5341         r = amdgpu_bo_create_reserved(adev, total_size, PAGE_SIZE,
5342                                       AMDGPU_GEM_DOMAIN_GTT,
5343                                       &adev->gfx.rlc.rlc_autoload_bo,
5344                                       &adev->gfx.rlc.rlc_autoload_gpu_addr,
5345                                       (void **)&adev->gfx.rlc.rlc_autoload_ptr);
5346         if (r) {
5347                 dev_err(adev->dev, "(%d) failed to create fw autoload bo\n", r);
5348                 return r;
5349         }
5350
5351         return 0;
5352 }
5353
5354 static void gfx_v10_0_rlc_backdoor_autoload_buffer_fini(struct amdgpu_device *adev)
5355 {
5356         amdgpu_bo_free_kernel(&adev->gfx.rlc.rlc_toc_bo,
5357                               &adev->gfx.rlc.rlc_toc_gpu_addr,
5358                               (void **)&adev->gfx.rlc.rlc_toc_buf);
5359         amdgpu_bo_free_kernel(&adev->gfx.rlc.rlc_autoload_bo,
5360                               &adev->gfx.rlc.rlc_autoload_gpu_addr,
5361                               (void **)&adev->gfx.rlc.rlc_autoload_ptr);
5362 }
5363
5364 static void gfx_v10_0_rlc_backdoor_autoload_copy_ucode(struct amdgpu_device *adev,
5365                                                        FIRMWARE_ID id,
5366                                                        const void *fw_data,
5367                                                        uint32_t fw_size)
5368 {
5369         uint32_t toc_offset;
5370         uint32_t toc_fw_size;
5371         char *ptr = adev->gfx.rlc.rlc_autoload_ptr;
5372
5373         if (id <= FIRMWARE_ID_INVALID || id >= FIRMWARE_ID_MAX)
5374                 return;
5375
5376         toc_offset = rlc_autoload_info[id].offset;
5377         toc_fw_size = rlc_autoload_info[id].size;
5378
5379         if (fw_size == 0)
5380                 fw_size = toc_fw_size;
5381
5382         if (fw_size > toc_fw_size)
5383                 fw_size = toc_fw_size;
5384
5385         memcpy(ptr + toc_offset, fw_data, fw_size);
5386
5387         if (fw_size < toc_fw_size)
5388                 memset(ptr + toc_offset + fw_size, 0, toc_fw_size - fw_size);
5389 }
5390
5391 static void gfx_v10_0_rlc_backdoor_autoload_copy_toc_ucode(struct amdgpu_device *adev)
5392 {
5393         void *data;
5394         uint32_t size;
5395
5396         data = adev->gfx.rlc.rlc_toc_buf;
5397         size = rlc_autoload_info[FIRMWARE_ID_RLC_TOC].size;
5398
5399         gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
5400                                                    FIRMWARE_ID_RLC_TOC,
5401                                                    data, size);
5402 }
5403
5404 static void gfx_v10_0_rlc_backdoor_autoload_copy_gfx_ucode(struct amdgpu_device *adev)
5405 {
5406         const __le32 *fw_data;
5407         uint32_t fw_size;
5408         const struct gfx_firmware_header_v1_0 *cp_hdr;
5409         const struct rlc_firmware_header_v2_0 *rlc_hdr;
5410
5411         /* pfp ucode */
5412         cp_hdr = (const struct gfx_firmware_header_v1_0 *)
5413                 adev->gfx.pfp_fw->data;
5414         fw_data = (const __le32 *)(adev->gfx.pfp_fw->data +
5415                 le32_to_cpu(cp_hdr->header.ucode_array_offset_bytes));
5416         fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes);
5417         gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
5418                                                    FIRMWARE_ID_CP_PFP,
5419                                                    fw_data, fw_size);
5420
5421         /* ce ucode */
5422         cp_hdr = (const struct gfx_firmware_header_v1_0 *)
5423                 adev->gfx.ce_fw->data;
5424         fw_data = (const __le32 *)(adev->gfx.ce_fw->data +
5425                 le32_to_cpu(cp_hdr->header.ucode_array_offset_bytes));
5426         fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes);
5427         gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
5428                                                    FIRMWARE_ID_CP_CE,
5429                                                    fw_data, fw_size);
5430
5431         /* me ucode */
5432         cp_hdr = (const struct gfx_firmware_header_v1_0 *)
5433                 adev->gfx.me_fw->data;
5434         fw_data = (const __le32 *)(adev->gfx.me_fw->data +
5435                 le32_to_cpu(cp_hdr->header.ucode_array_offset_bytes));
5436         fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes);
5437         gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
5438                                                    FIRMWARE_ID_CP_ME,
5439                                                    fw_data, fw_size);
5440
5441         /* rlc ucode */
5442         rlc_hdr = (const struct rlc_firmware_header_v2_0 *)
5443                 adev->gfx.rlc_fw->data;
5444         fw_data = (const __le32 *)(adev->gfx.rlc_fw->data +
5445                 le32_to_cpu(rlc_hdr->header.ucode_array_offset_bytes));
5446         fw_size = le32_to_cpu(rlc_hdr->header.ucode_size_bytes);
5447         gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
5448                                                    FIRMWARE_ID_RLC_G_UCODE,
5449                                                    fw_data, fw_size);
5450
5451         /* mec1 ucode */
5452         cp_hdr = (const struct gfx_firmware_header_v1_0 *)
5453                 adev->gfx.mec_fw->data;
5454         fw_data = (const __le32 *) (adev->gfx.mec_fw->data +
5455                 le32_to_cpu(cp_hdr->header.ucode_array_offset_bytes));
5456         fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes) -
5457                 cp_hdr->jt_size * 4;
5458         gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
5459                                                    FIRMWARE_ID_CP_MEC,
5460                                                    fw_data, fw_size);
5461         /* mec2 ucode is not necessary if mec2 ucode is same as mec1 */
5462 }
5463
5464 /* Temporarily put sdma part here */
5465 static void gfx_v10_0_rlc_backdoor_autoload_copy_sdma_ucode(struct amdgpu_device *adev)
5466 {
5467         const __le32 *fw_data;
5468         uint32_t fw_size;
5469         const struct sdma_firmware_header_v1_0 *sdma_hdr;
5470         int i;
5471
5472         for (i = 0; i < adev->sdma.num_instances; i++) {
5473                 sdma_hdr = (const struct sdma_firmware_header_v1_0 *)
5474                         adev->sdma.instance[i].fw->data;
5475                 fw_data = (const __le32 *) (adev->sdma.instance[i].fw->data +
5476                         le32_to_cpu(sdma_hdr->header.ucode_array_offset_bytes));
5477                 fw_size = le32_to_cpu(sdma_hdr->header.ucode_size_bytes);
5478
5479                 if (i == 0) {
5480                         gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
5481                                 FIRMWARE_ID_SDMA0_UCODE, fw_data, fw_size);
5482                         gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
5483                                 FIRMWARE_ID_SDMA0_JT,
5484                                 (uint32_t *)fw_data +
5485                                 sdma_hdr->jt_offset,
5486                                 sdma_hdr->jt_size * 4);
5487                 } else if (i == 1) {
5488                         gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
5489                                 FIRMWARE_ID_SDMA1_UCODE, fw_data, fw_size);
5490                         gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
5491                                 FIRMWARE_ID_SDMA1_JT,
5492                                 (uint32_t *)fw_data +
5493                                 sdma_hdr->jt_offset,
5494                                 sdma_hdr->jt_size * 4);
5495                 }
5496         }
5497 }
5498
5499 static int gfx_v10_0_rlc_backdoor_autoload_enable(struct amdgpu_device *adev)
5500 {
5501         uint32_t rlc_g_offset, rlc_g_size, tmp;
5502         uint64_t gpu_addr;
5503
5504         gfx_v10_0_rlc_backdoor_autoload_copy_toc_ucode(adev);
5505         gfx_v10_0_rlc_backdoor_autoload_copy_sdma_ucode(adev);
5506         gfx_v10_0_rlc_backdoor_autoload_copy_gfx_ucode(adev);
5507
5508         rlc_g_offset = rlc_autoload_info[FIRMWARE_ID_RLC_G_UCODE].offset;
5509         rlc_g_size = rlc_autoload_info[FIRMWARE_ID_RLC_G_UCODE].size;
5510         gpu_addr = adev->gfx.rlc.rlc_autoload_gpu_addr + rlc_g_offset;
5511
5512         WREG32_SOC15(GC, 0, mmRLC_HYP_BOOTLOAD_ADDR_HI, upper_32_bits(gpu_addr));
5513         WREG32_SOC15(GC, 0, mmRLC_HYP_BOOTLOAD_ADDR_LO, lower_32_bits(gpu_addr));
5514         WREG32_SOC15(GC, 0, mmRLC_HYP_BOOTLOAD_SIZE, rlc_g_size);
5515
5516         tmp = RREG32_SOC15(GC, 0, mmRLC_HYP_RESET_VECTOR);
5517         if (!(tmp & (RLC_HYP_RESET_VECTOR__COLD_BOOT_EXIT_MASK |
5518                    RLC_HYP_RESET_VECTOR__VDDGFX_EXIT_MASK))) {
5519                 DRM_ERROR("Neither COLD_BOOT_EXIT nor VDDGFX_EXIT is set\n");
5520                 return -EINVAL;
5521         }
5522
5523         tmp = RREG32_SOC15(GC, 0, mmRLC_CNTL);
5524         if (tmp & RLC_CNTL__RLC_ENABLE_F32_MASK) {
5525                 DRM_ERROR("RLC ROM should halt itself\n");
5526                 return -EINVAL;
5527         }
5528
5529         return 0;
5530 }
5531
5532 static int gfx_v10_0_rlc_backdoor_autoload_config_me_cache(struct amdgpu_device *adev)
5533 {
5534         uint32_t usec_timeout = 50000;  /* wait for 50ms */
5535         uint32_t tmp;
5536         int i;
5537         uint64_t addr;
5538
5539         /* Trigger an invalidation of the L1 instruction caches */
5540         tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL);
5541         tmp = REG_SET_FIELD(tmp, CP_ME_IC_OP_CNTL, INVALIDATE_CACHE, 1);
5542         WREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL, tmp);
5543
5544         /* Wait for invalidation complete */
5545         for (i = 0; i < usec_timeout; i++) {
5546                 tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL);
5547                 if (1 == REG_GET_FIELD(tmp, CP_ME_IC_OP_CNTL,
5548                         INVALIDATE_CACHE_COMPLETE))
5549                         break;
5550                 udelay(1);
5551         }
5552
5553         if (i >= usec_timeout) {
5554                 dev_err(adev->dev, "failed to invalidate instruction cache\n");
5555                 return -EINVAL;
5556         }
5557
5558         /* Program me ucode address into intruction cache address register */
5559         addr = adev->gfx.rlc.rlc_autoload_gpu_addr +
5560                 rlc_autoload_info[FIRMWARE_ID_CP_ME].offset;
5561         WREG32_SOC15(GC, 0, mmCP_ME_IC_BASE_LO,
5562                         lower_32_bits(addr) & 0xFFFFF000);
5563         WREG32_SOC15(GC, 0, mmCP_ME_IC_BASE_HI,
5564                         upper_32_bits(addr));
5565
5566         return 0;
5567 }
5568
5569 static int gfx_v10_0_rlc_backdoor_autoload_config_ce_cache(struct amdgpu_device *adev)
5570 {
5571         uint32_t usec_timeout = 50000;  /* wait for 50ms */
5572         uint32_t tmp;
5573         int i;
5574         uint64_t addr;
5575
5576         /* Trigger an invalidation of the L1 instruction caches */
5577         tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL);
5578         tmp = REG_SET_FIELD(tmp, CP_CE_IC_OP_CNTL, INVALIDATE_CACHE, 1);
5579         WREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL, tmp);
5580
5581         /* Wait for invalidation complete */
5582         for (i = 0; i < usec_timeout; i++) {
5583                 tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL);
5584                 if (1 == REG_GET_FIELD(tmp, CP_CE_IC_OP_CNTL,
5585                         INVALIDATE_CACHE_COMPLETE))
5586                         break;
5587                 udelay(1);
5588         }
5589
5590         if (i >= usec_timeout) {
5591                 dev_err(adev->dev, "failed to invalidate instruction cache\n");
5592                 return -EINVAL;
5593         }
5594
5595         /* Program ce ucode address into intruction cache address register */
5596         addr = adev->gfx.rlc.rlc_autoload_gpu_addr +
5597                 rlc_autoload_info[FIRMWARE_ID_CP_CE].offset;
5598         WREG32_SOC15(GC, 0, mmCP_CE_IC_BASE_LO,
5599                         lower_32_bits(addr) & 0xFFFFF000);
5600         WREG32_SOC15(GC, 0, mmCP_CE_IC_BASE_HI,
5601                         upper_32_bits(addr));
5602
5603         return 0;
5604 }
5605
5606 static int gfx_v10_0_rlc_backdoor_autoload_config_pfp_cache(struct amdgpu_device *adev)
5607 {
5608         uint32_t usec_timeout = 50000;  /* wait for 50ms */
5609         uint32_t tmp;
5610         int i;
5611         uint64_t addr;
5612
5613         /* Trigger an invalidation of the L1 instruction caches */
5614         tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL);
5615         tmp = REG_SET_FIELD(tmp, CP_PFP_IC_OP_CNTL, INVALIDATE_CACHE, 1);
5616         WREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL, tmp);
5617
5618         /* Wait for invalidation complete */
5619         for (i = 0; i < usec_timeout; i++) {
5620                 tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL);
5621                 if (1 == REG_GET_FIELD(tmp, CP_PFP_IC_OP_CNTL,
5622                         INVALIDATE_CACHE_COMPLETE))
5623                         break;
5624                 udelay(1);
5625         }
5626
5627         if (i >= usec_timeout) {
5628                 dev_err(adev->dev, "failed to invalidate instruction cache\n");
5629                 return -EINVAL;
5630         }
5631
5632         /* Program pfp ucode address into intruction cache address register */
5633         addr = adev->gfx.rlc.rlc_autoload_gpu_addr +
5634                 rlc_autoload_info[FIRMWARE_ID_CP_PFP].offset;
5635         WREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_LO,
5636                         lower_32_bits(addr) & 0xFFFFF000);
5637         WREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_HI,
5638                         upper_32_bits(addr));
5639
5640         return 0;
5641 }
5642
5643 static int gfx_v10_0_rlc_backdoor_autoload_config_mec_cache(struct amdgpu_device *adev)
5644 {
5645         uint32_t usec_timeout = 50000;  /* wait for 50ms */
5646         uint32_t tmp;
5647         int i;
5648         uint64_t addr;
5649
5650         /* Trigger an invalidation of the L1 instruction caches */
5651         tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL);
5652         tmp = REG_SET_FIELD(tmp, CP_CPC_IC_OP_CNTL, INVALIDATE_CACHE, 1);
5653         WREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL, tmp);
5654
5655         /* Wait for invalidation complete */
5656         for (i = 0; i < usec_timeout; i++) {
5657                 tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL);
5658                 if (1 == REG_GET_FIELD(tmp, CP_CPC_IC_OP_CNTL,
5659                         INVALIDATE_CACHE_COMPLETE))
5660                         break;
5661                 udelay(1);
5662         }
5663
5664         if (i >= usec_timeout) {
5665                 dev_err(adev->dev, "failed to invalidate instruction cache\n");
5666                 return -EINVAL;
5667         }
5668
5669         /* Program mec1 ucode address into intruction cache address register */
5670         addr = adev->gfx.rlc.rlc_autoload_gpu_addr +
5671                 rlc_autoload_info[FIRMWARE_ID_CP_MEC].offset;
5672         WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_LO,
5673                         lower_32_bits(addr) & 0xFFFFF000);
5674         WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_HI,
5675                         upper_32_bits(addr));
5676
5677         return 0;
5678 }
5679
5680 static int gfx_v10_0_wait_for_rlc_autoload_complete(struct amdgpu_device *adev)
5681 {
5682         uint32_t cp_status;
5683         uint32_t bootload_status;
5684         int i, r;
5685
5686         for (i = 0; i < adev->usec_timeout; i++) {
5687                 cp_status = RREG32_SOC15(GC, 0, mmCP_STAT);
5688                 bootload_status = RREG32_SOC15(GC, 0, mmRLC_RLCS_BOOTLOAD_STATUS);
5689                 if ((cp_status == 0) &&
5690                     (REG_GET_FIELD(bootload_status,
5691                         RLC_RLCS_BOOTLOAD_STATUS, BOOTLOAD_COMPLETE) == 1)) {
5692                         break;
5693                 }
5694                 udelay(1);
5695         }
5696
5697         if (i >= adev->usec_timeout) {
5698                 dev_err(adev->dev, "rlc autoload: gc ucode autoload timeout\n");
5699                 return -ETIMEDOUT;
5700         }
5701
5702         if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) {
5703                 r = gfx_v10_0_rlc_backdoor_autoload_config_me_cache(adev);
5704                 if (r)
5705                         return r;
5706
5707                 r = gfx_v10_0_rlc_backdoor_autoload_config_ce_cache(adev);
5708                 if (r)
5709                         return r;
5710
5711                 r = gfx_v10_0_rlc_backdoor_autoload_config_pfp_cache(adev);
5712                 if (r)
5713                         return r;
5714
5715                 r = gfx_v10_0_rlc_backdoor_autoload_config_mec_cache(adev);
5716                 if (r)
5717                         return r;
5718         }
5719
5720         return 0;
5721 }
5722
5723 static int gfx_v10_0_cp_gfx_enable(struct amdgpu_device *adev, bool enable)
5724 {
5725         int i;
5726         u32 tmp = RREG32_SOC15(GC, 0, mmCP_ME_CNTL);
5727
5728         tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_HALT, enable ? 0 : 1);
5729         tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_HALT, enable ? 0 : 1);
5730         tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, CE_HALT, enable ? 0 : 1);
5731
5732         if (adev->asic_type == CHIP_NAVI12) {
5733                 WREG32_SOC15_RLC(GC, 0, mmCP_ME_CNTL, tmp);
5734         } else {
5735                 WREG32_SOC15(GC, 0, mmCP_ME_CNTL, tmp);
5736         }
5737
5738         for (i = 0; i < adev->usec_timeout; i++) {
5739                 if (RREG32_SOC15(GC, 0, mmCP_STAT) == 0)
5740                         break;
5741                 udelay(1);
5742         }
5743
5744         if (i >= adev->usec_timeout)
5745                 DRM_ERROR("failed to %s cp gfx\n", enable ? "unhalt" : "halt");
5746
5747         return 0;
5748 }
5749
5750 static int gfx_v10_0_cp_gfx_load_pfp_microcode(struct amdgpu_device *adev)
5751 {
5752         int r;
5753         const struct gfx_firmware_header_v1_0 *pfp_hdr;
5754         const __le32 *fw_data;
5755         unsigned i, fw_size;
5756         uint32_t tmp;
5757         uint32_t usec_timeout = 50000;  /* wait for 50ms */
5758
5759         pfp_hdr = (const struct gfx_firmware_header_v1_0 *)
5760                 adev->gfx.pfp_fw->data;
5761
5762         amdgpu_ucode_print_gfx_hdr(&pfp_hdr->header);
5763
5764         fw_data = (const __le32 *)(adev->gfx.pfp_fw->data +
5765                 le32_to_cpu(pfp_hdr->header.ucode_array_offset_bytes));
5766         fw_size = le32_to_cpu(pfp_hdr->header.ucode_size_bytes);
5767
5768         r = amdgpu_bo_create_reserved(adev, pfp_hdr->header.ucode_size_bytes,
5769                                       PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT,
5770                                       &adev->gfx.pfp.pfp_fw_obj,
5771                                       &adev->gfx.pfp.pfp_fw_gpu_addr,
5772                                       (void **)&adev->gfx.pfp.pfp_fw_ptr);
5773         if (r) {
5774                 dev_err(adev->dev, "(%d) failed to create pfp fw bo\n", r);
5775                 gfx_v10_0_pfp_fini(adev);
5776                 return r;
5777         }
5778
5779         memcpy(adev->gfx.pfp.pfp_fw_ptr, fw_data, fw_size);
5780
5781         amdgpu_bo_kunmap(adev->gfx.pfp.pfp_fw_obj);
5782         amdgpu_bo_unreserve(adev->gfx.pfp.pfp_fw_obj);
5783
5784         /* Trigger an invalidation of the L1 instruction caches */
5785         tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL);
5786         tmp = REG_SET_FIELD(tmp, CP_PFP_IC_OP_CNTL, INVALIDATE_CACHE, 1);
5787         WREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL, tmp);
5788
5789         /* Wait for invalidation complete */
5790         for (i = 0; i < usec_timeout; i++) {
5791                 tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL);
5792                 if (1 == REG_GET_FIELD(tmp, CP_PFP_IC_OP_CNTL,
5793                         INVALIDATE_CACHE_COMPLETE))
5794                         break;
5795                 udelay(1);
5796         }
5797
5798         if (i >= usec_timeout) {
5799                 dev_err(adev->dev, "failed to invalidate instruction cache\n");
5800                 return -EINVAL;
5801         }
5802
5803         if (amdgpu_emu_mode == 1)
5804                 adev->hdp.funcs->flush_hdp(adev, NULL);
5805
5806         tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_CNTL);
5807         tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, VMID, 0);
5808         tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, CACHE_POLICY, 0);
5809         tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, EXE_DISABLE, 0);
5810         tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, ADDRESS_CLAMP, 1);
5811         WREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_CNTL, tmp);
5812         WREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_LO,
5813                 adev->gfx.pfp.pfp_fw_gpu_addr & 0xFFFFF000);
5814         WREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_HI,
5815                 upper_32_bits(adev->gfx.pfp.pfp_fw_gpu_addr));
5816
5817         WREG32_SOC15(GC, 0, mmCP_HYP_PFP_UCODE_ADDR, 0);
5818
5819         for (i = 0; i < pfp_hdr->jt_size; i++)
5820                 WREG32_SOC15(GC, 0, mmCP_HYP_PFP_UCODE_DATA,
5821                              le32_to_cpup(fw_data + pfp_hdr->jt_offset + i));
5822
5823         WREG32_SOC15(GC, 0, mmCP_HYP_PFP_UCODE_ADDR, adev->gfx.pfp_fw_version);
5824
5825         return 0;
5826 }
5827
5828 static int gfx_v10_0_cp_gfx_load_ce_microcode(struct amdgpu_device *adev)
5829 {
5830         int r;
5831         const struct gfx_firmware_header_v1_0 *ce_hdr;
5832         const __le32 *fw_data;
5833         unsigned i, fw_size;
5834         uint32_t tmp;
5835         uint32_t usec_timeout = 50000;  /* wait for 50ms */
5836
5837         ce_hdr = (const struct gfx_firmware_header_v1_0 *)
5838                 adev->gfx.ce_fw->data;
5839
5840         amdgpu_ucode_print_gfx_hdr(&ce_hdr->header);
5841
5842         fw_data = (const __le32 *)(adev->gfx.ce_fw->data +
5843                 le32_to_cpu(ce_hdr->header.ucode_array_offset_bytes));
5844         fw_size = le32_to_cpu(ce_hdr->header.ucode_size_bytes);
5845
5846         r = amdgpu_bo_create_reserved(adev, ce_hdr->header.ucode_size_bytes,
5847                                       PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT,
5848                                       &adev->gfx.ce.ce_fw_obj,
5849                                       &adev->gfx.ce.ce_fw_gpu_addr,
5850                                       (void **)&adev->gfx.ce.ce_fw_ptr);
5851         if (r) {
5852                 dev_err(adev->dev, "(%d) failed to create ce fw bo\n", r);
5853                 gfx_v10_0_ce_fini(adev);
5854                 return r;
5855         }
5856
5857         memcpy(adev->gfx.ce.ce_fw_ptr, fw_data, fw_size);
5858
5859         amdgpu_bo_kunmap(adev->gfx.ce.ce_fw_obj);
5860         amdgpu_bo_unreserve(adev->gfx.ce.ce_fw_obj);
5861
5862         /* Trigger an invalidation of the L1 instruction caches */
5863         tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL);
5864         tmp = REG_SET_FIELD(tmp, CP_CE_IC_OP_CNTL, INVALIDATE_CACHE, 1);
5865         WREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL, tmp);
5866
5867         /* Wait for invalidation complete */
5868         for (i = 0; i < usec_timeout; i++) {
5869                 tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL);
5870                 if (1 == REG_GET_FIELD(tmp, CP_CE_IC_OP_CNTL,
5871                         INVALIDATE_CACHE_COMPLETE))
5872                         break;
5873                 udelay(1);
5874         }
5875
5876         if (i >= usec_timeout) {
5877                 dev_err(adev->dev, "failed to invalidate instruction cache\n");
5878                 return -EINVAL;
5879         }
5880
5881         if (amdgpu_emu_mode == 1)
5882                 adev->hdp.funcs->flush_hdp(adev, NULL);
5883
5884         tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_BASE_CNTL);
5885         tmp = REG_SET_FIELD(tmp, CP_CE_IC_BASE_CNTL, VMID, 0);
5886         tmp = REG_SET_FIELD(tmp, CP_CE_IC_BASE_CNTL, CACHE_POLICY, 0);
5887         tmp = REG_SET_FIELD(tmp, CP_CE_IC_BASE_CNTL, EXE_DISABLE, 0);
5888         tmp = REG_SET_FIELD(tmp, CP_CE_IC_BASE_CNTL, ADDRESS_CLAMP, 1);
5889         WREG32_SOC15(GC, 0, mmCP_CE_IC_BASE_LO,
5890                 adev->gfx.ce.ce_fw_gpu_addr & 0xFFFFF000);
5891         WREG32_SOC15(GC, 0, mmCP_CE_IC_BASE_HI,
5892                 upper_32_bits(adev->gfx.ce.ce_fw_gpu_addr));
5893
5894         WREG32_SOC15(GC, 0, mmCP_HYP_CE_UCODE_ADDR, 0);
5895
5896         for (i = 0; i < ce_hdr->jt_size; i++)
5897                 WREG32_SOC15(GC, 0, mmCP_HYP_CE_UCODE_DATA,
5898                              le32_to_cpup(fw_data + ce_hdr->jt_offset + i));
5899
5900         WREG32_SOC15(GC, 0, mmCP_HYP_CE_UCODE_ADDR, adev->gfx.ce_fw_version);
5901
5902         return 0;
5903 }
5904
5905 static int gfx_v10_0_cp_gfx_load_me_microcode(struct amdgpu_device *adev)
5906 {
5907         int r;
5908         const struct gfx_firmware_header_v1_0 *me_hdr;
5909         const __le32 *fw_data;
5910         unsigned i, fw_size;
5911         uint32_t tmp;
5912         uint32_t usec_timeout = 50000;  /* wait for 50ms */
5913
5914         me_hdr = (const struct gfx_firmware_header_v1_0 *)
5915                 adev->gfx.me_fw->data;
5916
5917         amdgpu_ucode_print_gfx_hdr(&me_hdr->header);
5918
5919         fw_data = (const __le32 *)(adev->gfx.me_fw->data +
5920                 le32_to_cpu(me_hdr->header.ucode_array_offset_bytes));
5921         fw_size = le32_to_cpu(me_hdr->header.ucode_size_bytes);
5922
5923         r = amdgpu_bo_create_reserved(adev, me_hdr->header.ucode_size_bytes,
5924                                       PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT,
5925                                       &adev->gfx.me.me_fw_obj,
5926                                       &adev->gfx.me.me_fw_gpu_addr,
5927                                       (void **)&adev->gfx.me.me_fw_ptr);
5928         if (r) {
5929                 dev_err(adev->dev, "(%d) failed to create me fw bo\n", r);
5930                 gfx_v10_0_me_fini(adev);
5931                 return r;
5932         }
5933
5934         memcpy(adev->gfx.me.me_fw_ptr, fw_data, fw_size);
5935
5936         amdgpu_bo_kunmap(adev->gfx.me.me_fw_obj);
5937         amdgpu_bo_unreserve(adev->gfx.me.me_fw_obj);
5938
5939         /* Trigger an invalidation of the L1 instruction caches */
5940         tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL);
5941         tmp = REG_SET_FIELD(tmp, CP_ME_IC_OP_CNTL, INVALIDATE_CACHE, 1);
5942         WREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL, tmp);
5943
5944         /* Wait for invalidation complete */
5945         for (i = 0; i < usec_timeout; i++) {
5946                 tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL);
5947                 if (1 == REG_GET_FIELD(tmp, CP_ME_IC_OP_CNTL,
5948                         INVALIDATE_CACHE_COMPLETE))
5949                         break;
5950                 udelay(1);
5951         }
5952
5953         if (i >= usec_timeout) {
5954                 dev_err(adev->dev, "failed to invalidate instruction cache\n");
5955                 return -EINVAL;
5956         }
5957
5958         if (amdgpu_emu_mode == 1)
5959                 adev->hdp.funcs->flush_hdp(adev, NULL);
5960
5961         tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_BASE_CNTL);
5962         tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, VMID, 0);
5963         tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, CACHE_POLICY, 0);
5964         tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, EXE_DISABLE, 0);
5965         tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, ADDRESS_CLAMP, 1);
5966         WREG32_SOC15(GC, 0, mmCP_ME_IC_BASE_LO,
5967                 adev->gfx.me.me_fw_gpu_addr & 0xFFFFF000);
5968         WREG32_SOC15(GC, 0, mmCP_ME_IC_BASE_HI,
5969                 upper_32_bits(adev->gfx.me.me_fw_gpu_addr));
5970
5971         WREG32_SOC15(GC, 0, mmCP_HYP_ME_UCODE_ADDR, 0);
5972
5973         for (i = 0; i < me_hdr->jt_size; i++)
5974                 WREG32_SOC15(GC, 0, mmCP_HYP_ME_UCODE_DATA,
5975                              le32_to_cpup(fw_data + me_hdr->jt_offset + i));
5976
5977         WREG32_SOC15(GC, 0, mmCP_HYP_ME_UCODE_ADDR, adev->gfx.me_fw_version);
5978
5979         return 0;
5980 }
5981
5982 static int gfx_v10_0_cp_gfx_load_microcode(struct amdgpu_device *adev)
5983 {
5984         int r;
5985
5986         if (!adev->gfx.me_fw || !adev->gfx.pfp_fw || !adev->gfx.ce_fw)
5987                 return -EINVAL;
5988
5989         gfx_v10_0_cp_gfx_enable(adev, false);
5990
5991         r = gfx_v10_0_cp_gfx_load_pfp_microcode(adev);
5992         if (r) {
5993                 dev_err(adev->dev, "(%d) failed to load pfp fw\n", r);
5994                 return r;
5995         }
5996
5997         r = gfx_v10_0_cp_gfx_load_ce_microcode(adev);
5998         if (r) {
5999                 dev_err(adev->dev, "(%d) failed to load ce fw\n", r);
6000                 return r;
6001         }
6002
6003         r = gfx_v10_0_cp_gfx_load_me_microcode(adev);
6004         if (r) {
6005                 dev_err(adev->dev, "(%d) failed to load me fw\n", r);
6006                 return r;
6007         }
6008
6009         return 0;
6010 }
6011
6012 static int gfx_v10_0_cp_gfx_start(struct amdgpu_device *adev)
6013 {
6014         struct amdgpu_ring *ring;
6015         const struct cs_section_def *sect = NULL;
6016         const struct cs_extent_def *ext = NULL;
6017         int r, i;
6018         int ctx_reg_offset;
6019
6020         /* init the CP */
6021         WREG32_SOC15(GC, 0, mmCP_MAX_CONTEXT,
6022                      adev->gfx.config.max_hw_contexts - 1);
6023         WREG32_SOC15(GC, 0, mmCP_DEVICE_ID, 1);
6024
6025         gfx_v10_0_cp_gfx_enable(adev, true);
6026
6027         ring = &adev->gfx.gfx_ring[0];
6028         r = amdgpu_ring_alloc(ring, gfx_v10_0_get_csb_size(adev) + 4);
6029         if (r) {
6030                 DRM_ERROR("amdgpu: cp failed to lock ring (%d).\n", r);
6031                 return r;
6032         }
6033
6034         amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
6035         amdgpu_ring_write(ring, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE);
6036
6037         amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1));
6038         amdgpu_ring_write(ring, 0x80000000);
6039         amdgpu_ring_write(ring, 0x80000000);
6040
6041         for (sect = gfx10_cs_data; sect->section != NULL; ++sect) {
6042                 for (ext = sect->section; ext->extent != NULL; ++ext) {
6043                         if (sect->id == SECT_CONTEXT) {
6044                                 amdgpu_ring_write(ring,
6045                                                   PACKET3(PACKET3_SET_CONTEXT_REG,
6046                                                           ext->reg_count));
6047                                 amdgpu_ring_write(ring, ext->reg_index -
6048                                                   PACKET3_SET_CONTEXT_REG_START);
6049                                 for (i = 0; i < ext->reg_count; i++)
6050                                         amdgpu_ring_write(ring, ext->extent[i]);
6051                         }
6052                 }
6053         }
6054
6055         ctx_reg_offset =
6056                 SOC15_REG_OFFSET(GC, 0, mmPA_SC_TILE_STEERING_OVERRIDE) - PACKET3_SET_CONTEXT_REG_START;
6057         amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 1));
6058         amdgpu_ring_write(ring, ctx_reg_offset);
6059         amdgpu_ring_write(ring, adev->gfx.config.pa_sc_tile_steering_override);
6060
6061         amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
6062         amdgpu_ring_write(ring, PACKET3_PREAMBLE_END_CLEAR_STATE);
6063
6064         amdgpu_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0));
6065         amdgpu_ring_write(ring, 0);
6066
6067         amdgpu_ring_write(ring, PACKET3(PACKET3_SET_BASE, 2));
6068         amdgpu_ring_write(ring, PACKET3_BASE_INDEX(CE_PARTITION_BASE));
6069         amdgpu_ring_write(ring, 0x8000);
6070         amdgpu_ring_write(ring, 0x8000);
6071
6072         amdgpu_ring_commit(ring);
6073
6074         /* submit cs packet to copy state 0 to next available state */
6075         if (adev->gfx.num_gfx_rings > 1) {
6076                 /* maximum supported gfx ring is 2 */
6077                 ring = &adev->gfx.gfx_ring[1];
6078                 r = amdgpu_ring_alloc(ring, 2);
6079                 if (r) {
6080                         DRM_ERROR("amdgpu: cp failed to lock ring (%d).\n", r);
6081                         return r;
6082                 }
6083
6084                 amdgpu_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0));
6085                 amdgpu_ring_write(ring, 0);
6086
6087                 amdgpu_ring_commit(ring);
6088         }
6089         return 0;
6090 }
6091
6092 static void gfx_v10_0_cp_gfx_switch_pipe(struct amdgpu_device *adev,
6093                                          CP_PIPE_ID pipe)
6094 {
6095         u32 tmp;
6096
6097         tmp = RREG32_SOC15(GC, 0, mmGRBM_GFX_CNTL);
6098         tmp = REG_SET_FIELD(tmp, GRBM_GFX_CNTL, PIPEID, pipe);
6099
6100         WREG32_SOC15(GC, 0, mmGRBM_GFX_CNTL, tmp);
6101 }
6102
6103 static void gfx_v10_0_cp_gfx_set_doorbell(struct amdgpu_device *adev,
6104                                           struct amdgpu_ring *ring)
6105 {
6106         u32 tmp;
6107
6108         if (!amdgpu_async_gfx_ring) {
6109                 tmp = RREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL);
6110                 if (ring->use_doorbell) {
6111                         tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
6112                                                 DOORBELL_OFFSET, ring->doorbell_index);
6113                         tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
6114                                                 DOORBELL_EN, 1);
6115                 } else {
6116                         tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
6117                                                 DOORBELL_EN, 0);
6118                 }
6119                 WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL, tmp);
6120         }
6121         switch (adev->asic_type) {
6122         case CHIP_SIENNA_CICHLID:
6123         case CHIP_NAVY_FLOUNDER:
6124         case CHIP_VANGOGH:
6125         case CHIP_DIMGREY_CAVEFISH:
6126                 tmp = REG_SET_FIELD(0, CP_RB_DOORBELL_RANGE_LOWER,
6127                                     DOORBELL_RANGE_LOWER_Sienna_Cichlid, ring->doorbell_index);
6128                 WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_RANGE_LOWER, tmp);
6129
6130                 WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_RANGE_UPPER,
6131                              CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_Sienna_Cichlid_MASK);
6132                 break;
6133         default:
6134                 tmp = REG_SET_FIELD(0, CP_RB_DOORBELL_RANGE_LOWER,
6135                                     DOORBELL_RANGE_LOWER, ring->doorbell_index);
6136                 WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_RANGE_LOWER, tmp);
6137
6138                 WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_RANGE_UPPER,
6139                              CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_MASK);
6140                 break;
6141         }
6142 }
6143
6144 static int gfx_v10_0_cp_gfx_resume(struct amdgpu_device *adev)
6145 {
6146         struct amdgpu_ring *ring;
6147         u32 tmp;
6148         u32 rb_bufsz;
6149         u64 rb_addr, rptr_addr, wptr_gpu_addr;
6150         u32 i;
6151
6152         /* Set the write pointer delay */
6153         WREG32_SOC15(GC, 0, mmCP_RB_WPTR_DELAY, 0);
6154
6155         /* set the RB to use vmid 0 */
6156         WREG32_SOC15(GC, 0, mmCP_RB_VMID, 0);
6157
6158         /* Init gfx ring 0 for pipe 0 */
6159         mutex_lock(&adev->srbm_mutex);
6160         gfx_v10_0_cp_gfx_switch_pipe(adev, PIPE_ID0);
6161
6162         /* Set ring buffer size */
6163         ring = &adev->gfx.gfx_ring[0];
6164         rb_bufsz = order_base_2(ring->ring_size / 8);
6165         tmp = REG_SET_FIELD(0, CP_RB0_CNTL, RB_BUFSZ, rb_bufsz);
6166         tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, RB_BLKSZ, rb_bufsz - 2);
6167 #ifdef __BIG_ENDIAN
6168         tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, BUF_SWAP, 1);
6169 #endif
6170         WREG32_SOC15(GC, 0, mmCP_RB0_CNTL, tmp);
6171
6172         /* Initialize the ring buffer's write pointers */
6173         ring->wptr = 0;
6174         WREG32_SOC15(GC, 0, mmCP_RB0_WPTR, lower_32_bits(ring->wptr));
6175         WREG32_SOC15(GC, 0, mmCP_RB0_WPTR_HI, upper_32_bits(ring->wptr));
6176
6177         /* set the wb address wether it's enabled or not */
6178         rptr_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4);
6179         WREG32_SOC15(GC, 0, mmCP_RB0_RPTR_ADDR, lower_32_bits(rptr_addr));
6180         WREG32_SOC15(GC, 0, mmCP_RB0_RPTR_ADDR_HI, upper_32_bits(rptr_addr) &
6181                      CP_RB_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK);
6182
6183         wptr_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
6184         WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_LO,
6185                      lower_32_bits(wptr_gpu_addr));
6186         WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_HI,
6187                      upper_32_bits(wptr_gpu_addr));
6188
6189         mdelay(1);
6190         WREG32_SOC15(GC, 0, mmCP_RB0_CNTL, tmp);
6191
6192         rb_addr = ring->gpu_addr >> 8;
6193         WREG32_SOC15(GC, 0, mmCP_RB0_BASE, rb_addr);
6194         WREG32_SOC15(GC, 0, mmCP_RB0_BASE_HI, upper_32_bits(rb_addr));
6195
6196         WREG32_SOC15(GC, 0, mmCP_RB_ACTIVE, 1);
6197
6198         gfx_v10_0_cp_gfx_set_doorbell(adev, ring);
6199         mutex_unlock(&adev->srbm_mutex);
6200
6201         /* Init gfx ring 1 for pipe 1 */
6202         if (adev->gfx.num_gfx_rings > 1) {
6203                 mutex_lock(&adev->srbm_mutex);
6204                 gfx_v10_0_cp_gfx_switch_pipe(adev, PIPE_ID1);
6205                 /* maximum supported gfx ring is 2 */
6206                 ring = &adev->gfx.gfx_ring[1];
6207                 rb_bufsz = order_base_2(ring->ring_size / 8);
6208                 tmp = REG_SET_FIELD(0, CP_RB1_CNTL, RB_BUFSZ, rb_bufsz);
6209                 tmp = REG_SET_FIELD(tmp, CP_RB1_CNTL, RB_BLKSZ, rb_bufsz - 2);
6210                 WREG32_SOC15(GC, 0, mmCP_RB1_CNTL, tmp);
6211                 /* Initialize the ring buffer's write pointers */
6212                 ring->wptr = 0;
6213                 WREG32_SOC15(GC, 0, mmCP_RB1_WPTR, lower_32_bits(ring->wptr));
6214                 WREG32_SOC15(GC, 0, mmCP_RB1_WPTR_HI, upper_32_bits(ring->wptr));
6215                 /* Set the wb address wether it's enabled or not */
6216                 rptr_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4);
6217                 WREG32_SOC15(GC, 0, mmCP_RB1_RPTR_ADDR, lower_32_bits(rptr_addr));
6218                 WREG32_SOC15(GC, 0, mmCP_RB1_RPTR_ADDR_HI, upper_32_bits(rptr_addr) &
6219                              CP_RB1_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK);
6220                 wptr_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
6221                 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_LO,
6222                              lower_32_bits(wptr_gpu_addr));
6223                 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_HI,
6224                              upper_32_bits(wptr_gpu_addr));
6225
6226                 mdelay(1);
6227                 WREG32_SOC15(GC, 0, mmCP_RB1_CNTL, tmp);
6228
6229                 rb_addr = ring->gpu_addr >> 8;
6230                 WREG32_SOC15(GC, 0, mmCP_RB1_BASE, rb_addr);
6231                 WREG32_SOC15(GC, 0, mmCP_RB1_BASE_HI, upper_32_bits(rb_addr));
6232                 WREG32_SOC15(GC, 0, mmCP_RB1_ACTIVE, 1);
6233
6234                 gfx_v10_0_cp_gfx_set_doorbell(adev, ring);
6235                 mutex_unlock(&adev->srbm_mutex);
6236         }
6237         /* Switch to pipe 0 */
6238         mutex_lock(&adev->srbm_mutex);
6239         gfx_v10_0_cp_gfx_switch_pipe(adev, PIPE_ID0);
6240         mutex_unlock(&adev->srbm_mutex);
6241
6242         /* start the ring */
6243         gfx_v10_0_cp_gfx_start(adev);
6244
6245         for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
6246                 ring = &adev->gfx.gfx_ring[i];
6247                 ring->sched.ready = true;
6248         }
6249
6250         return 0;
6251 }
6252
6253 static void gfx_v10_0_cp_compute_enable(struct amdgpu_device *adev, bool enable)
6254 {
6255         if (enable) {
6256                 switch (adev->asic_type) {
6257                 case CHIP_SIENNA_CICHLID:
6258                 case CHIP_NAVY_FLOUNDER:
6259                 case CHIP_VANGOGH:
6260                 case CHIP_DIMGREY_CAVEFISH:
6261                         WREG32_SOC15(GC, 0, mmCP_MEC_CNTL_Sienna_Cichlid, 0);
6262                         break;
6263                 default:
6264                         WREG32_SOC15(GC, 0, mmCP_MEC_CNTL, 0);
6265                         break;
6266                 }
6267         } else {
6268                 switch (adev->asic_type) {
6269                 case CHIP_SIENNA_CICHLID:
6270                 case CHIP_NAVY_FLOUNDER:
6271                 case CHIP_VANGOGH:
6272                 case CHIP_DIMGREY_CAVEFISH:
6273                         WREG32_SOC15(GC, 0, mmCP_MEC_CNTL_Sienna_Cichlid,
6274                                      (CP_MEC_CNTL__MEC_ME1_HALT_MASK |
6275                                       CP_MEC_CNTL__MEC_ME2_HALT_MASK));
6276                         break;
6277                 default:
6278                         WREG32_SOC15(GC, 0, mmCP_MEC_CNTL,
6279                                      (CP_MEC_CNTL__MEC_ME1_HALT_MASK |
6280                                       CP_MEC_CNTL__MEC_ME2_HALT_MASK));
6281                         break;
6282                 }
6283                 adev->gfx.kiq.ring.sched.ready = false;
6284         }
6285         udelay(50);
6286 }
6287
6288 static int gfx_v10_0_cp_compute_load_microcode(struct amdgpu_device *adev)
6289 {
6290         const struct gfx_firmware_header_v1_0 *mec_hdr;
6291         const __le32 *fw_data;
6292         unsigned i;
6293         u32 tmp;
6294         u32 usec_timeout = 50000; /* Wait for 50 ms */
6295
6296         if (!adev->gfx.mec_fw)
6297                 return -EINVAL;
6298
6299         gfx_v10_0_cp_compute_enable(adev, false);
6300
6301         mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data;
6302         amdgpu_ucode_print_gfx_hdr(&mec_hdr->header);
6303
6304         fw_data = (const __le32 *)
6305                 (adev->gfx.mec_fw->data +
6306                  le32_to_cpu(mec_hdr->header.ucode_array_offset_bytes));
6307
6308         /* Trigger an invalidation of the L1 instruction caches */
6309         tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL);
6310         tmp = REG_SET_FIELD(tmp, CP_CPC_IC_OP_CNTL, INVALIDATE_CACHE, 1);
6311         WREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL, tmp);
6312
6313         /* Wait for invalidation complete */
6314         for (i = 0; i < usec_timeout; i++) {
6315                 tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL);
6316                 if (1 == REG_GET_FIELD(tmp, CP_CPC_IC_OP_CNTL,
6317                                        INVALIDATE_CACHE_COMPLETE))
6318                         break;
6319                 udelay(1);
6320         }
6321
6322         if (i >= usec_timeout) {
6323                 dev_err(adev->dev, "failed to invalidate instruction cache\n");
6324                 return -EINVAL;
6325         }
6326
6327         if (amdgpu_emu_mode == 1)
6328                 adev->hdp.funcs->flush_hdp(adev, NULL);
6329
6330         tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_CNTL);
6331         tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, CACHE_POLICY, 0);
6332         tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, EXE_DISABLE, 0);
6333         tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, ADDRESS_CLAMP, 1);
6334         WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_CNTL, tmp);
6335
6336         WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_LO, adev->gfx.mec.mec_fw_gpu_addr &
6337                      0xFFFFF000);
6338         WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_HI,
6339                      upper_32_bits(adev->gfx.mec.mec_fw_gpu_addr));
6340
6341         /* MEC1 */
6342         WREG32_SOC15(GC, 0, mmCP_MEC_ME1_UCODE_ADDR, 0);
6343
6344         for (i = 0; i < mec_hdr->jt_size; i++)
6345                 WREG32_SOC15(GC, 0, mmCP_MEC_ME1_UCODE_DATA,
6346                              le32_to_cpup(fw_data + mec_hdr->jt_offset + i));
6347
6348         WREG32_SOC15(GC, 0, mmCP_MEC_ME1_UCODE_ADDR, adev->gfx.mec_fw_version);
6349
6350         /*
6351          * TODO: Loading MEC2 firmware is only necessary if MEC2 should run
6352          * different microcode than MEC1.
6353          */
6354
6355         return 0;
6356 }
6357
6358 static void gfx_v10_0_kiq_setting(struct amdgpu_ring *ring)
6359 {
6360         uint32_t tmp;
6361         struct amdgpu_device *adev = ring->adev;
6362
6363         /* tell RLC which is KIQ queue */
6364         switch (adev->asic_type) {
6365         case CHIP_SIENNA_CICHLID:
6366         case CHIP_NAVY_FLOUNDER:
6367         case CHIP_VANGOGH:
6368         case CHIP_DIMGREY_CAVEFISH:
6369                 tmp = RREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS_Sienna_Cichlid);
6370                 tmp &= 0xffffff00;
6371                 tmp |= (ring->me << 5) | (ring->pipe << 3) | (ring->queue);
6372                 WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS_Sienna_Cichlid, tmp);
6373                 tmp |= 0x80;
6374                 WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS_Sienna_Cichlid, tmp);
6375                 break;
6376         default:
6377                 tmp = RREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS);
6378                 tmp &= 0xffffff00;
6379                 tmp |= (ring->me << 5) | (ring->pipe << 3) | (ring->queue);
6380                 WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS, tmp);
6381                 tmp |= 0x80;
6382                 WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS, tmp);
6383                 break;
6384         }
6385 }
6386
6387 static int gfx_v10_0_gfx_mqd_init(struct amdgpu_ring *ring)
6388 {
6389         struct amdgpu_device *adev = ring->adev;
6390         struct v10_gfx_mqd *mqd = ring->mqd_ptr;
6391         uint64_t hqd_gpu_addr, wb_gpu_addr;
6392         uint32_t tmp;
6393         uint32_t rb_bufsz;
6394
6395         /* set up gfx hqd wptr */
6396         mqd->cp_gfx_hqd_wptr = 0;
6397         mqd->cp_gfx_hqd_wptr_hi = 0;
6398
6399         /* set the pointer to the MQD */
6400         mqd->cp_mqd_base_addr = ring->mqd_gpu_addr & 0xfffffffc;
6401         mqd->cp_mqd_base_addr_hi = upper_32_bits(ring->mqd_gpu_addr);
6402
6403         /* set up mqd control */
6404         tmp = RREG32_SOC15(GC, 0, mmCP_GFX_MQD_CONTROL);
6405         tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, VMID, 0);
6406         tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, PRIV_STATE, 1);
6407         tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, CACHE_POLICY, 0);
6408         mqd->cp_gfx_mqd_control = tmp;
6409
6410         /* set up gfx_hqd_vimd with 0x0 to indicate the ring buffer's vmid */
6411         tmp = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_VMID);
6412         tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_VMID, VMID, 0);
6413         mqd->cp_gfx_hqd_vmid = 0;
6414
6415         /* set up default queue priority level
6416          * 0x0 = low priority, 0x1 = high priority */
6417         tmp = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_QUEUE_PRIORITY);
6418         tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_QUEUE_PRIORITY, PRIORITY_LEVEL, 0);
6419         mqd->cp_gfx_hqd_queue_priority = tmp;
6420
6421         /* set up time quantum */
6422         tmp = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_QUANTUM);
6423         tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_QUANTUM, QUANTUM_EN, 1);
6424         mqd->cp_gfx_hqd_quantum = tmp;
6425
6426         /* set up gfx hqd base. this is similar as CP_RB_BASE */
6427         hqd_gpu_addr = ring->gpu_addr >> 8;
6428         mqd->cp_gfx_hqd_base = hqd_gpu_addr;
6429         mqd->cp_gfx_hqd_base_hi = upper_32_bits(hqd_gpu_addr);
6430
6431         /* set up hqd_rptr_addr/_hi, similar as CP_RB_RPTR */
6432         wb_gpu_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4);
6433         mqd->cp_gfx_hqd_rptr_addr = wb_gpu_addr & 0xfffffffc;
6434         mqd->cp_gfx_hqd_rptr_addr_hi =
6435                 upper_32_bits(wb_gpu_addr) & 0xffff;
6436
6437         /* set up rb_wptr_poll addr */
6438         wb_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
6439         mqd->cp_rb_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffffc;
6440         mqd->cp_rb_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff;
6441
6442         /* set up the gfx_hqd_control, similar as CP_RB0_CNTL */
6443         rb_bufsz = order_base_2(ring->ring_size / 4) - 1;
6444         tmp = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_CNTL);
6445         tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, RB_BUFSZ, rb_bufsz);
6446         tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, RB_BLKSZ, rb_bufsz - 2);
6447 #ifdef __BIG_ENDIAN
6448         tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, BUF_SWAP, 1);
6449 #endif
6450         mqd->cp_gfx_hqd_cntl = tmp;
6451
6452         /* set up cp_doorbell_control */
6453         tmp = RREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL);
6454         if (ring->use_doorbell) {
6455                 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
6456                                     DOORBELL_OFFSET, ring->doorbell_index);
6457                 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
6458                                     DOORBELL_EN, 1);
6459         } else
6460                 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
6461                                     DOORBELL_EN, 0);
6462         mqd->cp_rb_doorbell_control = tmp;
6463
6464         /*if there are 2 gfx rings, set the lower doorbell range of the first ring,
6465          *otherwise the range of the second ring will override the first ring */
6466         if (ring->doorbell_index == adev->doorbell_index.gfx_ring0 << 1)
6467                 gfx_v10_0_cp_gfx_set_doorbell(adev, ring);
6468
6469         /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */
6470         ring->wptr = 0;
6471         mqd->cp_gfx_hqd_rptr = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_RPTR);
6472
6473         /* active the queue */
6474         mqd->cp_gfx_hqd_active = 1;
6475
6476         return 0;
6477 }
6478
6479 #ifdef BRING_UP_DEBUG
6480 static int gfx_v10_0_gfx_queue_init_register(struct amdgpu_ring *ring)
6481 {
6482         struct amdgpu_device *adev = ring->adev;
6483         struct v10_gfx_mqd *mqd = ring->mqd_ptr;
6484
6485         /* set mmCP_GFX_HQD_WPTR/_HI to 0 */
6486         WREG32_SOC15(GC, 0, mmCP_GFX_HQD_WPTR, mqd->cp_gfx_hqd_wptr);
6487         WREG32_SOC15(GC, 0, mmCP_GFX_HQD_WPTR_HI, mqd->cp_gfx_hqd_wptr_hi);
6488
6489         /* set GFX_MQD_BASE */
6490         WREG32_SOC15(GC, 0, mmCP_MQD_BASE_ADDR, mqd->cp_mqd_base_addr);
6491         WREG32_SOC15(GC, 0, mmCP_MQD_BASE_ADDR_HI, mqd->cp_mqd_base_addr_hi);
6492
6493         /* set GFX_MQD_CONTROL */
6494         WREG32_SOC15(GC, 0, mmCP_GFX_MQD_CONTROL, mqd->cp_gfx_mqd_control);
6495
6496         /* set GFX_HQD_VMID to 0 */
6497         WREG32_SOC15(GC, 0, mmCP_GFX_HQD_VMID, mqd->cp_gfx_hqd_vmid);
6498
6499         WREG32_SOC15(GC, 0, mmCP_GFX_HQD_QUEUE_PRIORITY,
6500                         mqd->cp_gfx_hqd_queue_priority);
6501         WREG32_SOC15(GC, 0, mmCP_GFX_HQD_QUANTUM, mqd->cp_gfx_hqd_quantum);
6502
6503         /* set GFX_HQD_BASE, similar as CP_RB_BASE */
6504         WREG32_SOC15(GC, 0, mmCP_GFX_HQD_BASE, mqd->cp_gfx_hqd_base);
6505         WREG32_SOC15(GC, 0, mmCP_GFX_HQD_BASE_HI, mqd->cp_gfx_hqd_base_hi);
6506
6507         /* set GFX_HQD_RPTR_ADDR, similar as CP_RB_RPTR */
6508         WREG32_SOC15(GC, 0, mmCP_GFX_HQD_RPTR_ADDR, mqd->cp_gfx_hqd_rptr_addr);
6509         WREG32_SOC15(GC, 0, mmCP_GFX_HQD_RPTR_ADDR_HI, mqd->cp_gfx_hqd_rptr_addr_hi);
6510
6511         /* set GFX_HQD_CNTL, similar as CP_RB_CNTL */
6512         WREG32_SOC15(GC, 0, mmCP_GFX_HQD_CNTL, mqd->cp_gfx_hqd_cntl);
6513
6514         /* set RB_WPTR_POLL_ADDR */
6515         WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_LO, mqd->cp_rb_wptr_poll_addr_lo);
6516         WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_HI, mqd->cp_rb_wptr_poll_addr_hi);
6517
6518         /* set RB_DOORBELL_CONTROL */
6519         WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL, mqd->cp_rb_doorbell_control);
6520
6521         /* active the queue */
6522         WREG32_SOC15(GC, 0, mmCP_GFX_HQD_ACTIVE, mqd->cp_gfx_hqd_active);
6523
6524         return 0;
6525 }
6526 #endif
6527
6528 static int gfx_v10_0_gfx_init_queue(struct amdgpu_ring *ring)
6529 {
6530         struct amdgpu_device *adev = ring->adev;
6531         struct v10_gfx_mqd *mqd = ring->mqd_ptr;
6532         int mqd_idx = ring - &adev->gfx.gfx_ring[0];
6533
6534         if (!amdgpu_in_reset(adev) && !adev->in_suspend) {
6535                 memset((void *)mqd, 0, sizeof(*mqd));
6536                 mutex_lock(&adev->srbm_mutex);
6537                 nv_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
6538                 gfx_v10_0_gfx_mqd_init(ring);
6539 #ifdef BRING_UP_DEBUG
6540                 gfx_v10_0_gfx_queue_init_register(ring);
6541 #endif
6542                 nv_grbm_select(adev, 0, 0, 0, 0);
6543                 mutex_unlock(&adev->srbm_mutex);
6544                 if (adev->gfx.me.mqd_backup[mqd_idx])
6545                         memcpy(adev->gfx.me.mqd_backup[mqd_idx], mqd, sizeof(*mqd));
6546         } else if (amdgpu_in_reset(adev)) {
6547                 /* reset mqd with the backup copy */
6548                 if (adev->gfx.me.mqd_backup[mqd_idx])
6549                         memcpy(mqd, adev->gfx.me.mqd_backup[mqd_idx], sizeof(*mqd));
6550                 /* reset the ring */
6551                 ring->wptr = 0;
6552                 adev->wb.wb[ring->wptr_offs] = 0;
6553                 amdgpu_ring_clear_ring(ring);
6554 #ifdef BRING_UP_DEBUG
6555                 mutex_lock(&adev->srbm_mutex);
6556                 nv_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
6557                 gfx_v10_0_gfx_queue_init_register(ring);
6558                 nv_grbm_select(adev, 0, 0, 0, 0);
6559                 mutex_unlock(&adev->srbm_mutex);
6560 #endif
6561         } else {
6562                 amdgpu_ring_clear_ring(ring);
6563         }
6564
6565         return 0;
6566 }
6567
6568 #ifndef BRING_UP_DEBUG
6569 static int gfx_v10_0_kiq_enable_kgq(struct amdgpu_device *adev)
6570 {
6571         struct amdgpu_kiq *kiq = &adev->gfx.kiq;
6572         struct amdgpu_ring *kiq_ring = &adev->gfx.kiq.ring;
6573         int r, i;
6574
6575         if (!kiq->pmf || !kiq->pmf->kiq_map_queues)
6576                 return -EINVAL;
6577
6578         r = amdgpu_ring_alloc(kiq_ring, kiq->pmf->map_queues_size *
6579                                         adev->gfx.num_gfx_rings);
6580         if (r) {
6581                 DRM_ERROR("Failed to lock KIQ (%d).\n", r);
6582                 return r;
6583         }
6584
6585         for (i = 0; i < adev->gfx.num_gfx_rings; i++)
6586                 kiq->pmf->kiq_map_queues(kiq_ring, &adev->gfx.gfx_ring[i]);
6587
6588         return amdgpu_ring_test_helper(kiq_ring);
6589 }
6590 #endif
6591
6592 static int gfx_v10_0_cp_async_gfx_ring_resume(struct amdgpu_device *adev)
6593 {
6594         int r, i;
6595         struct amdgpu_ring *ring;
6596
6597         for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
6598                 ring = &adev->gfx.gfx_ring[i];
6599
6600                 r = amdgpu_bo_reserve(ring->mqd_obj, false);
6601                 if (unlikely(r != 0))
6602                         goto done;
6603
6604                 r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr);
6605                 if (!r) {
6606                         r = gfx_v10_0_gfx_init_queue(ring);
6607                         amdgpu_bo_kunmap(ring->mqd_obj);
6608                         ring->mqd_ptr = NULL;
6609                 }
6610                 amdgpu_bo_unreserve(ring->mqd_obj);
6611                 if (r)
6612                         goto done;
6613         }
6614 #ifndef BRING_UP_DEBUG
6615         r = gfx_v10_0_kiq_enable_kgq(adev);
6616         if (r)
6617                 goto done;
6618 #endif
6619         r = gfx_v10_0_cp_gfx_start(adev);
6620         if (r)
6621                 goto done;
6622
6623         for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
6624                 ring = &adev->gfx.gfx_ring[i];
6625                 ring->sched.ready = true;
6626         }
6627 done:
6628         return r;
6629 }
6630
6631 static void gfx_v10_0_compute_mqd_set_priority(struct amdgpu_ring *ring, struct v10_compute_mqd *mqd)
6632 {
6633         struct amdgpu_device *adev = ring->adev;
6634
6635         if (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE) {
6636                 if (amdgpu_gfx_is_high_priority_compute_queue(adev, ring)) {
6637                         mqd->cp_hqd_pipe_priority = AMDGPU_GFX_PIPE_PRIO_HIGH;
6638                         mqd->cp_hqd_queue_priority =
6639                                 AMDGPU_GFX_QUEUE_PRIORITY_MAXIMUM;
6640                 }
6641         }
6642 }
6643
6644 static int gfx_v10_0_compute_mqd_init(struct amdgpu_ring *ring)
6645 {
6646         struct amdgpu_device *adev = ring->adev;
6647         struct v10_compute_mqd *mqd = ring->mqd_ptr;
6648         uint64_t hqd_gpu_addr, wb_gpu_addr, eop_base_addr;
6649         uint32_t tmp;
6650
6651         mqd->header = 0xC0310800;
6652         mqd->compute_pipelinestat_enable = 0x00000001;
6653         mqd->compute_static_thread_mgmt_se0 = 0xffffffff;
6654         mqd->compute_static_thread_mgmt_se1 = 0xffffffff;
6655         mqd->compute_static_thread_mgmt_se2 = 0xffffffff;
6656         mqd->compute_static_thread_mgmt_se3 = 0xffffffff;
6657         mqd->compute_misc_reserved = 0x00000003;
6658
6659         eop_base_addr = ring->eop_gpu_addr >> 8;
6660         mqd->cp_hqd_eop_base_addr_lo = eop_base_addr;
6661         mqd->cp_hqd_eop_base_addr_hi = upper_32_bits(eop_base_addr);
6662
6663         /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */
6664         tmp = RREG32_SOC15(GC, 0, mmCP_HQD_EOP_CONTROL);
6665         tmp = REG_SET_FIELD(tmp, CP_HQD_EOP_CONTROL, EOP_SIZE,
6666                         (order_base_2(GFX10_MEC_HPD_SIZE / 4) - 1));
6667
6668         mqd->cp_hqd_eop_control = tmp;
6669
6670         /* enable doorbell? */
6671         tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL);
6672
6673         if (ring->use_doorbell) {
6674                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
6675                                     DOORBELL_OFFSET, ring->doorbell_index);
6676                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
6677                                     DOORBELL_EN, 1);
6678                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
6679                                     DOORBELL_SOURCE, 0);
6680                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
6681                                     DOORBELL_HIT, 0);
6682         } else {
6683                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
6684                                     DOORBELL_EN, 0);
6685         }
6686
6687         mqd->cp_hqd_pq_doorbell_control = tmp;
6688
6689         /* disable the queue if it's active */
6690         ring->wptr = 0;
6691         mqd->cp_hqd_dequeue_request = 0;
6692         mqd->cp_hqd_pq_rptr = 0;
6693         mqd->cp_hqd_pq_wptr_lo = 0;
6694         mqd->cp_hqd_pq_wptr_hi = 0;
6695
6696         /* set the pointer to the MQD */
6697         mqd->cp_mqd_base_addr_lo = ring->mqd_gpu_addr & 0xfffffffc;
6698         mqd->cp_mqd_base_addr_hi = upper_32_bits(ring->mqd_gpu_addr);
6699
6700         /* set MQD vmid to 0 */
6701         tmp = RREG32_SOC15(GC, 0, mmCP_MQD_CONTROL);
6702         tmp = REG_SET_FIELD(tmp, CP_MQD_CONTROL, VMID, 0);
6703         mqd->cp_mqd_control = tmp;
6704
6705         /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */
6706         hqd_gpu_addr = ring->gpu_addr >> 8;
6707         mqd->cp_hqd_pq_base_lo = hqd_gpu_addr;
6708         mqd->cp_hqd_pq_base_hi = upper_32_bits(hqd_gpu_addr);
6709
6710         /* set up the HQD, this is similar to CP_RB0_CNTL */
6711         tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_CONTROL);
6712         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, QUEUE_SIZE,
6713                             (order_base_2(ring->ring_size / 4) - 1));
6714         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, RPTR_BLOCK_SIZE,
6715                             ((order_base_2(AMDGPU_GPU_PAGE_SIZE / 4) - 1) << 8));
6716 #ifdef __BIG_ENDIAN
6717         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, ENDIAN_SWAP, 1);
6718 #endif
6719         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 0);
6720         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, TUNNEL_DISPATCH, 0);
6721         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1);
6722         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, KMD_QUEUE, 1);
6723         mqd->cp_hqd_pq_control = tmp;
6724
6725         /* set the wb address whether it's enabled or not */
6726         wb_gpu_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4);
6727         mqd->cp_hqd_pq_rptr_report_addr_lo = wb_gpu_addr & 0xfffffffc;
6728         mqd->cp_hqd_pq_rptr_report_addr_hi =
6729                 upper_32_bits(wb_gpu_addr) & 0xffff;
6730
6731         /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */
6732         wb_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
6733         mqd->cp_hqd_pq_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffffc;
6734         mqd->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff;
6735
6736         tmp = 0;
6737         /* enable the doorbell if requested */
6738         if (ring->use_doorbell) {
6739                 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL);
6740                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
6741                                 DOORBELL_OFFSET, ring->doorbell_index);
6742
6743                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
6744                                     DOORBELL_EN, 1);
6745                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
6746                                     DOORBELL_SOURCE, 0);
6747                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
6748                                     DOORBELL_HIT, 0);
6749         }
6750
6751         mqd->cp_hqd_pq_doorbell_control = tmp;
6752
6753         /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */
6754         ring->wptr = 0;
6755         mqd->cp_hqd_pq_rptr = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR);
6756
6757         /* set the vmid for the queue */
6758         mqd->cp_hqd_vmid = 0;
6759
6760         tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PERSISTENT_STATE);
6761         tmp = REG_SET_FIELD(tmp, CP_HQD_PERSISTENT_STATE, PRELOAD_SIZE, 0x53);
6762         mqd->cp_hqd_persistent_state = tmp;
6763
6764         /* set MIN_IB_AVAIL_SIZE */
6765         tmp = RREG32_SOC15(GC, 0, mmCP_HQD_IB_CONTROL);
6766         tmp = REG_SET_FIELD(tmp, CP_HQD_IB_CONTROL, MIN_IB_AVAIL_SIZE, 3);
6767         mqd->cp_hqd_ib_control = tmp;
6768
6769         /* set static priority for a compute queue/ring */
6770         gfx_v10_0_compute_mqd_set_priority(ring, mqd);
6771
6772         /* map_queues packet doesn't need activate the queue,
6773          * so only kiq need set this field.
6774          */
6775         if (ring->funcs->type == AMDGPU_RING_TYPE_KIQ)
6776                 mqd->cp_hqd_active = 1;
6777
6778         return 0;
6779 }
6780
6781 static int gfx_v10_0_kiq_init_register(struct amdgpu_ring *ring)
6782 {
6783         struct amdgpu_device *adev = ring->adev;
6784         struct v10_compute_mqd *mqd = ring->mqd_ptr;
6785         int j;
6786
6787         /* inactivate the queue */
6788         if (amdgpu_sriov_vf(adev))
6789                 WREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE, 0);
6790
6791         /* disable wptr polling */
6792         WREG32_FIELD15(GC, 0, CP_PQ_WPTR_POLL_CNTL, EN, 0);
6793
6794         /* write the EOP addr */
6795         WREG32_SOC15(GC, 0, mmCP_HQD_EOP_BASE_ADDR,
6796                mqd->cp_hqd_eop_base_addr_lo);
6797         WREG32_SOC15(GC, 0, mmCP_HQD_EOP_BASE_ADDR_HI,
6798                mqd->cp_hqd_eop_base_addr_hi);
6799
6800         /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */
6801         WREG32_SOC15(GC, 0, mmCP_HQD_EOP_CONTROL,
6802                mqd->cp_hqd_eop_control);
6803
6804         /* enable doorbell? */
6805         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL,
6806                mqd->cp_hqd_pq_doorbell_control);
6807
6808         /* disable the queue if it's active */
6809         if (RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE) & 1) {
6810                 WREG32_SOC15(GC, 0, mmCP_HQD_DEQUEUE_REQUEST, 1);
6811                 for (j = 0; j < adev->usec_timeout; j++) {
6812                         if (!(RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE) & 1))
6813                                 break;
6814                         udelay(1);
6815                 }
6816                 WREG32_SOC15(GC, 0, mmCP_HQD_DEQUEUE_REQUEST,
6817                        mqd->cp_hqd_dequeue_request);
6818                 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR,
6819                        mqd->cp_hqd_pq_rptr);
6820                 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_LO,
6821                        mqd->cp_hqd_pq_wptr_lo);
6822                 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_HI,
6823                        mqd->cp_hqd_pq_wptr_hi);
6824         }
6825
6826         /* set the pointer to the MQD */
6827         WREG32_SOC15(GC, 0, mmCP_MQD_BASE_ADDR,
6828                mqd->cp_mqd_base_addr_lo);
6829         WREG32_SOC15(GC, 0, mmCP_MQD_BASE_ADDR_HI,
6830                mqd->cp_mqd_base_addr_hi);
6831
6832         /* set MQD vmid to 0 */
6833         WREG32_SOC15(GC, 0, mmCP_MQD_CONTROL,
6834                mqd->cp_mqd_control);
6835
6836         /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */
6837         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_BASE,
6838                mqd->cp_hqd_pq_base_lo);
6839         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_BASE_HI,
6840                mqd->cp_hqd_pq_base_hi);
6841
6842         /* set up the HQD, this is similar to CP_RB0_CNTL */
6843         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_CONTROL,
6844                mqd->cp_hqd_pq_control);
6845
6846         /* set the wb address whether it's enabled or not */
6847         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR_REPORT_ADDR,
6848                 mqd->cp_hqd_pq_rptr_report_addr_lo);
6849         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR_REPORT_ADDR_HI,
6850                 mqd->cp_hqd_pq_rptr_report_addr_hi);
6851
6852         /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */
6853         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR,
6854                mqd->cp_hqd_pq_wptr_poll_addr_lo);
6855         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR_HI,
6856                mqd->cp_hqd_pq_wptr_poll_addr_hi);
6857
6858         /* enable the doorbell if requested */
6859         if (ring->use_doorbell) {
6860                 WREG32_SOC15(GC, 0, mmCP_MEC_DOORBELL_RANGE_LOWER,
6861                         (adev->doorbell_index.kiq * 2) << 2);
6862                 WREG32_SOC15(GC, 0, mmCP_MEC_DOORBELL_RANGE_UPPER,
6863                         (adev->doorbell_index.userqueue_end * 2) << 2);
6864         }
6865
6866         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL,
6867                mqd->cp_hqd_pq_doorbell_control);
6868
6869         /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */
6870         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_LO,
6871                mqd->cp_hqd_pq_wptr_lo);
6872         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_HI,
6873                mqd->cp_hqd_pq_wptr_hi);
6874
6875         /* set the vmid for the queue */
6876         WREG32_SOC15(GC, 0, mmCP_HQD_VMID, mqd->cp_hqd_vmid);
6877
6878         WREG32_SOC15(GC, 0, mmCP_HQD_PERSISTENT_STATE,
6879                mqd->cp_hqd_persistent_state);
6880
6881         /* activate the queue */
6882         WREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE,
6883                mqd->cp_hqd_active);
6884
6885         if (ring->use_doorbell)
6886                 WREG32_FIELD15(GC, 0, CP_PQ_STATUS, DOORBELL_ENABLE, 1);
6887
6888         return 0;
6889 }
6890
6891 static int gfx_v10_0_kiq_init_queue(struct amdgpu_ring *ring)
6892 {
6893         struct amdgpu_device *adev = ring->adev;
6894         struct v10_compute_mqd *mqd = ring->mqd_ptr;
6895         int mqd_idx = AMDGPU_MAX_COMPUTE_RINGS;
6896
6897         gfx_v10_0_kiq_setting(ring);
6898
6899         if (amdgpu_in_reset(adev)) { /* for GPU_RESET case */
6900                 /* reset MQD to a clean status */
6901                 if (adev->gfx.mec.mqd_backup[mqd_idx])
6902                         memcpy(mqd, adev->gfx.mec.mqd_backup[mqd_idx], sizeof(*mqd));
6903
6904                 /* reset ring buffer */
6905                 ring->wptr = 0;
6906                 amdgpu_ring_clear_ring(ring);
6907
6908                 mutex_lock(&adev->srbm_mutex);
6909                 nv_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
6910                 gfx_v10_0_kiq_init_register(ring);
6911                 nv_grbm_select(adev, 0, 0, 0, 0);
6912                 mutex_unlock(&adev->srbm_mutex);
6913         } else {
6914                 memset((void *)mqd, 0, sizeof(*mqd));
6915                 mutex_lock(&adev->srbm_mutex);
6916                 nv_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
6917                 gfx_v10_0_compute_mqd_init(ring);
6918                 gfx_v10_0_kiq_init_register(ring);
6919                 nv_grbm_select(adev, 0, 0, 0, 0);
6920                 mutex_unlock(&adev->srbm_mutex);
6921
6922                 if (adev->gfx.mec.mqd_backup[mqd_idx])
6923                         memcpy(adev->gfx.mec.mqd_backup[mqd_idx], mqd, sizeof(*mqd));
6924         }
6925
6926         return 0;
6927 }
6928
6929 static int gfx_v10_0_kcq_init_queue(struct amdgpu_ring *ring)
6930 {
6931         struct amdgpu_device *adev = ring->adev;
6932         struct v10_compute_mqd *mqd = ring->mqd_ptr;
6933         int mqd_idx = ring - &adev->gfx.compute_ring[0];
6934
6935         if (!amdgpu_in_reset(adev) && !adev->in_suspend) {
6936                 memset((void *)mqd, 0, sizeof(*mqd));
6937                 mutex_lock(&adev->srbm_mutex);
6938                 nv_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
6939                 gfx_v10_0_compute_mqd_init(ring);
6940                 nv_grbm_select(adev, 0, 0, 0, 0);
6941                 mutex_unlock(&adev->srbm_mutex);
6942
6943                 if (adev->gfx.mec.mqd_backup[mqd_idx])
6944                         memcpy(adev->gfx.mec.mqd_backup[mqd_idx], mqd, sizeof(*mqd));
6945         } else if (amdgpu_in_reset(adev)) { /* for GPU_RESET case */
6946                 /* reset MQD to a clean status */
6947                 if (adev->gfx.mec.mqd_backup[mqd_idx])
6948                         memcpy(mqd, adev->gfx.mec.mqd_backup[mqd_idx], sizeof(*mqd));
6949
6950                 /* reset ring buffer */
6951                 ring->wptr = 0;
6952                 atomic64_set((atomic64_t *)&adev->wb.wb[ring->wptr_offs], 0);
6953                 amdgpu_ring_clear_ring(ring);
6954         } else {
6955                 amdgpu_ring_clear_ring(ring);
6956         }
6957
6958         return 0;
6959 }
6960
6961 static int gfx_v10_0_kiq_resume(struct amdgpu_device *adev)
6962 {
6963         struct amdgpu_ring *ring;
6964         int r;
6965
6966         ring = &adev->gfx.kiq.ring;
6967
6968         r = amdgpu_bo_reserve(ring->mqd_obj, false);
6969         if (unlikely(r != 0))
6970                 return r;
6971
6972         r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr);
6973         if (unlikely(r != 0))
6974                 return r;
6975
6976         gfx_v10_0_kiq_init_queue(ring);
6977         amdgpu_bo_kunmap(ring->mqd_obj);
6978         ring->mqd_ptr = NULL;
6979         amdgpu_bo_unreserve(ring->mqd_obj);
6980         ring->sched.ready = true;
6981         return 0;
6982 }
6983
6984 static int gfx_v10_0_kcq_resume(struct amdgpu_device *adev)
6985 {
6986         struct amdgpu_ring *ring = NULL;
6987         int r = 0, i;
6988
6989         gfx_v10_0_cp_compute_enable(adev, true);
6990
6991         for (i = 0; i < adev->gfx.num_compute_rings; i++) {
6992                 ring = &adev->gfx.compute_ring[i];
6993
6994                 r = amdgpu_bo_reserve(ring->mqd_obj, false);
6995                 if (unlikely(r != 0))
6996                         goto done;
6997                 r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr);
6998                 if (!r) {
6999                         r = gfx_v10_0_kcq_init_queue(ring);
7000                         amdgpu_bo_kunmap(ring->mqd_obj);
7001                         ring->mqd_ptr = NULL;
7002                 }
7003                 amdgpu_bo_unreserve(ring->mqd_obj);
7004                 if (r)
7005                         goto done;
7006         }
7007
7008         r = amdgpu_gfx_enable_kcq(adev);
7009 done:
7010         return r;
7011 }
7012
7013 static int gfx_v10_0_cp_resume(struct amdgpu_device *adev)
7014 {
7015         int r, i;
7016         struct amdgpu_ring *ring;
7017
7018         if (!(adev->flags & AMD_IS_APU))
7019                 gfx_v10_0_enable_gui_idle_interrupt(adev, false);
7020
7021         if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) {
7022                 /* legacy firmware loading */
7023                 r = gfx_v10_0_cp_gfx_load_microcode(adev);
7024                 if (r)
7025                         return r;
7026
7027                 r = gfx_v10_0_cp_compute_load_microcode(adev);
7028                 if (r)
7029                         return r;
7030         }
7031
7032         r = gfx_v10_0_kiq_resume(adev);
7033         if (r)
7034                 return r;
7035
7036         r = gfx_v10_0_kcq_resume(adev);
7037         if (r)
7038                 return r;
7039
7040         if (!amdgpu_async_gfx_ring) {
7041                 r = gfx_v10_0_cp_gfx_resume(adev);
7042                 if (r)
7043                         return r;
7044         } else {
7045                 r = gfx_v10_0_cp_async_gfx_ring_resume(adev);
7046                 if (r)
7047                         return r;
7048         }
7049
7050         for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
7051                 ring = &adev->gfx.gfx_ring[i];
7052                 r = amdgpu_ring_test_helper(ring);
7053                 if (r)
7054                         return r;
7055         }
7056
7057         for (i = 0; i < adev->gfx.num_compute_rings; i++) {
7058                 ring = &adev->gfx.compute_ring[i];
7059                 r = amdgpu_ring_test_helper(ring);
7060                 if (r)
7061                         return r;
7062         }
7063
7064         return 0;
7065 }
7066
7067 static void gfx_v10_0_cp_enable(struct amdgpu_device *adev, bool enable)
7068 {
7069         gfx_v10_0_cp_gfx_enable(adev, enable);
7070         gfx_v10_0_cp_compute_enable(adev, enable);
7071 }
7072
7073 static bool gfx_v10_0_check_grbm_cam_remapping(struct amdgpu_device *adev)
7074 {
7075         uint32_t data, pattern = 0xDEADBEEF;
7076
7077         /* check if mmVGT_ESGS_RING_SIZE_UMD
7078          * has been remapped to mmVGT_ESGS_RING_SIZE */
7079         switch (adev->asic_type) {
7080         case CHIP_SIENNA_CICHLID:
7081         case CHIP_NAVY_FLOUNDER:
7082         case CHIP_DIMGREY_CAVEFISH:
7083                 data = RREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_Sienna_Cichlid);
7084                 WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_Sienna_Cichlid, 0);
7085                 WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_UMD, pattern);
7086
7087                 if (RREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_Sienna_Cichlid) == pattern) {
7088                         WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_UMD , data);
7089                         return true;
7090                 } else {
7091                         WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_Sienna_Cichlid, data);
7092                         return false;
7093                 }
7094                 break;
7095         case CHIP_VANGOGH:
7096                 return true;
7097         default:
7098                 data = RREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE);
7099                 WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE, 0);
7100                 WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_UMD, pattern);
7101
7102                 if (RREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE) == pattern) {
7103                         WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_UMD, data);
7104                         return true;
7105                 } else {
7106                         WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE, data);
7107                         return false;
7108                 }
7109                 break;
7110         }
7111 }
7112
7113 static void gfx_v10_0_setup_grbm_cam_remapping(struct amdgpu_device *adev)
7114 {
7115         uint32_t data;
7116
7117         /* initialize cam_index to 0
7118          * index will auto-inc after each data writting */
7119         WREG32_SOC15(GC, 0, mmGRBM_CAM_INDEX, 0);
7120
7121         switch (adev->asic_type) {
7122         case CHIP_SIENNA_CICHLID:
7123         case CHIP_NAVY_FLOUNDER:
7124         case CHIP_VANGOGH:
7125         case CHIP_DIMGREY_CAVEFISH:
7126                 /* mmVGT_TF_RING_SIZE_UMD -> mmVGT_TF_RING_SIZE */
7127                 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_RING_SIZE_UMD) <<
7128                         GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
7129                        (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_RING_SIZE_Sienna_Cichlid) <<
7130                         GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
7131                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
7132                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
7133
7134                 /* mmVGT_TF_MEMORY_BASE_UMD -> mmVGT_TF_MEMORY_BASE */
7135                 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_UMD) <<
7136                         GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
7137                        (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_Sienna_Cichlid) <<
7138                         GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
7139                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
7140                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
7141
7142                 /* mmVGT_TF_MEMORY_BASE_HI_UMD -> mmVGT_TF_MEMORY_BASE_HI */
7143                 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_HI_UMD) <<
7144                         GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
7145                        (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_HI_Sienna_Cichlid) <<
7146                         GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
7147                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
7148                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
7149
7150                 /* mmVGT_HS_OFFCHIP_PARAM_UMD -> mmVGT_HS_OFFCHIP_PARAM */
7151                 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_HS_OFFCHIP_PARAM_UMD) <<
7152                         GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
7153                        (SOC15_REG_OFFSET(GC, 0, mmVGT_HS_OFFCHIP_PARAM_Sienna_Cichlid) <<
7154                         GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
7155                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
7156                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
7157
7158                 /* mmVGT_ESGS_RING_SIZE_UMD -> mmVGT_ESGS_RING_SIZE */
7159                 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_ESGS_RING_SIZE_UMD) <<
7160                         GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
7161                        (SOC15_REG_OFFSET(GC, 0, mmVGT_ESGS_RING_SIZE_Sienna_Cichlid) <<
7162                         GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
7163                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
7164                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
7165
7166                 /* mmVGT_GSVS_RING_SIZE_UMD -> mmVGT_GSVS_RING_SIZE */
7167                 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_GSVS_RING_SIZE_UMD) <<
7168                         GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
7169                        (SOC15_REG_OFFSET(GC, 0, mmVGT_GSVS_RING_SIZE_Sienna_Cichlid) <<
7170                         GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
7171                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
7172                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
7173
7174                 /* mmSPI_CONFIG_CNTL_REMAP -> mmSPI_CONFIG_CNTL */
7175                 data = (SOC15_REG_OFFSET(GC, 0, mmSPI_CONFIG_CNTL_REMAP) <<
7176                         GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
7177                        (SOC15_REG_OFFSET(GC, 0, mmSPI_CONFIG_CNTL_Sienna_Cichlid) <<
7178                         GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
7179                 break;
7180         default:
7181                 /* mmVGT_TF_RING_SIZE_UMD -> mmVGT_TF_RING_SIZE */
7182                 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_RING_SIZE_UMD) <<
7183                         GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
7184                        (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_RING_SIZE) <<
7185                         GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
7186                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
7187                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
7188
7189                 /* mmVGT_TF_MEMORY_BASE_UMD -> mmVGT_TF_MEMORY_BASE */
7190                 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_UMD) <<
7191                         GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
7192                        (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE) <<
7193                         GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
7194                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
7195                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
7196
7197                 /* mmVGT_TF_MEMORY_BASE_HI_UMD -> mmVGT_TF_MEMORY_BASE_HI */
7198                 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_HI_UMD) <<
7199                         GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
7200                        (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_HI) <<
7201                         GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
7202                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
7203                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
7204
7205                 /* mmVGT_HS_OFFCHIP_PARAM_UMD -> mmVGT_HS_OFFCHIP_PARAM */
7206                 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_HS_OFFCHIP_PARAM_UMD) <<
7207                         GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
7208                        (SOC15_REG_OFFSET(GC, 0, mmVGT_HS_OFFCHIP_PARAM) <<
7209                         GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
7210                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
7211                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
7212
7213                 /* mmVGT_ESGS_RING_SIZE_UMD -> mmVGT_ESGS_RING_SIZE */
7214                 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_ESGS_RING_SIZE_UMD) <<
7215                         GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
7216                        (SOC15_REG_OFFSET(GC, 0, mmVGT_ESGS_RING_SIZE) <<
7217                         GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
7218                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
7219                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
7220
7221                 /* mmVGT_GSVS_RING_SIZE_UMD -> mmVGT_GSVS_RING_SIZE */
7222                 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_GSVS_RING_SIZE_UMD) <<
7223                         GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
7224                        (SOC15_REG_OFFSET(GC, 0, mmVGT_GSVS_RING_SIZE) <<
7225                         GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
7226                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
7227                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
7228
7229                 /* mmSPI_CONFIG_CNTL_REMAP -> mmSPI_CONFIG_CNTL */
7230                 data = (SOC15_REG_OFFSET(GC, 0, mmSPI_CONFIG_CNTL_REMAP) <<
7231                         GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
7232                        (SOC15_REG_OFFSET(GC, 0, mmSPI_CONFIG_CNTL) <<
7233                         GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
7234                 break;
7235         }
7236
7237         WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
7238         WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
7239 }
7240
7241 static void gfx_v10_0_disable_gpa_mode(struct amdgpu_device *adev)
7242 {
7243         uint32_t data;
7244         data = RREG32_SOC15(GC, 0, mmCPC_PSP_DEBUG);
7245         data |= CPC_PSP_DEBUG__GPA_OVERRIDE_MASK;
7246         WREG32_SOC15(GC, 0, mmCPC_PSP_DEBUG, data);
7247
7248         data = RREG32_SOC15(GC, 0, mmCPG_PSP_DEBUG);
7249         data |= CPG_PSP_DEBUG__GPA_OVERRIDE_MASK;
7250         WREG32_SOC15(GC, 0, mmCPG_PSP_DEBUG, data);
7251 }
7252
7253 static int gfx_v10_0_hw_init(void *handle)
7254 {
7255         int r;
7256         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7257
7258         if (!amdgpu_emu_mode)
7259                 gfx_v10_0_init_golden_registers(adev);
7260
7261         if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) {
7262                 /**
7263                  * For gfx 10, rlc firmware loading relies on smu firmware is
7264                  * loaded firstly, so in direct type, it has to load smc ucode
7265                  * here before rlc.
7266                  */
7267                 if (!(adev->flags & AMD_IS_APU)) {
7268                         r = amdgpu_pm_load_smu_firmware(adev, NULL);
7269                         if (r)
7270                                 return r;
7271                 }
7272                 gfx_v10_0_disable_gpa_mode(adev);
7273         }
7274
7275         /* if GRBM CAM not remapped, set up the remapping */
7276         if (!gfx_v10_0_check_grbm_cam_remapping(adev))
7277                 gfx_v10_0_setup_grbm_cam_remapping(adev);
7278
7279         gfx_v10_0_constants_init(adev);
7280
7281         r = gfx_v10_0_rlc_resume(adev);
7282         if (r)
7283                 return r;
7284
7285         /*
7286          * init golden registers and rlc resume may override some registers,
7287          * reconfig them here
7288          */
7289         gfx_v10_0_tcp_harvest(adev);
7290
7291         r = gfx_v10_0_cp_resume(adev);
7292         if (r)
7293                 return r;
7294
7295         if (adev->asic_type == CHIP_SIENNA_CICHLID)
7296                 gfx_v10_3_program_pbb_mode(adev);
7297
7298         if (adev->asic_type >= CHIP_SIENNA_CICHLID)
7299                 gfx_v10_3_set_power_brake_sequence(adev);
7300
7301         return r;
7302 }
7303
7304 #ifndef BRING_UP_DEBUG
7305 static int gfx_v10_0_kiq_disable_kgq(struct amdgpu_device *adev)
7306 {
7307         struct amdgpu_kiq *kiq = &adev->gfx.kiq;
7308         struct amdgpu_ring *kiq_ring = &kiq->ring;
7309         int i;
7310
7311         if (!kiq->pmf || !kiq->pmf->kiq_unmap_queues)
7312                 return -EINVAL;
7313
7314         if (amdgpu_ring_alloc(kiq_ring, kiq->pmf->unmap_queues_size *
7315                                         adev->gfx.num_gfx_rings))
7316                 return -ENOMEM;
7317
7318         for (i = 0; i < adev->gfx.num_gfx_rings; i++)
7319                 kiq->pmf->kiq_unmap_queues(kiq_ring, &adev->gfx.gfx_ring[i],
7320                                            PREEMPT_QUEUES, 0, 0);
7321
7322         return amdgpu_ring_test_helper(kiq_ring);
7323 }
7324 #endif
7325
7326 static int gfx_v10_0_hw_fini(void *handle)
7327 {
7328         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7329         int r;
7330         uint32_t tmp;
7331
7332         amdgpu_irq_put(adev, &adev->gfx.priv_reg_irq, 0);
7333         amdgpu_irq_put(adev, &adev->gfx.priv_inst_irq, 0);
7334
7335         if (!adev->in_pci_err_recovery) {
7336 #ifndef BRING_UP_DEBUG
7337                 if (amdgpu_async_gfx_ring) {
7338                         r = gfx_v10_0_kiq_disable_kgq(adev);
7339                         if (r)
7340                                 DRM_ERROR("KGQ disable failed\n");
7341                 }
7342 #endif
7343                 if (amdgpu_gfx_disable_kcq(adev))
7344                         DRM_ERROR("KCQ disable failed\n");
7345         }
7346
7347         if (amdgpu_sriov_vf(adev)) {
7348                 gfx_v10_0_cp_gfx_enable(adev, false);
7349                 /* Program KIQ position of RLC_CP_SCHEDULERS during destroy */
7350                 tmp = RREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS);
7351                 tmp &= 0xffffff00;
7352                 WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS, tmp);
7353
7354                 return 0;
7355         }
7356         gfx_v10_0_cp_enable(adev, false);
7357         gfx_v10_0_enable_gui_idle_interrupt(adev, false);
7358
7359         return 0;
7360 }
7361
7362 static int gfx_v10_0_suspend(void *handle)
7363 {
7364         return gfx_v10_0_hw_fini(handle);
7365 }
7366
7367 static int gfx_v10_0_resume(void *handle)
7368 {
7369         return gfx_v10_0_hw_init(handle);
7370 }
7371
7372 static bool gfx_v10_0_is_idle(void *handle)
7373 {
7374         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7375
7376         if (REG_GET_FIELD(RREG32_SOC15(GC, 0, mmGRBM_STATUS),
7377                                 GRBM_STATUS, GUI_ACTIVE))
7378                 return false;
7379         else
7380                 return true;
7381 }
7382
7383 static int gfx_v10_0_wait_for_idle(void *handle)
7384 {
7385         unsigned i;
7386         u32 tmp;
7387         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7388
7389         for (i = 0; i < adev->usec_timeout; i++) {
7390                 /* read MC_STATUS */
7391                 tmp = RREG32_SOC15(GC, 0, mmGRBM_STATUS) &
7392                         GRBM_STATUS__GUI_ACTIVE_MASK;
7393
7394                 if (!REG_GET_FIELD(tmp, GRBM_STATUS, GUI_ACTIVE))
7395                         return 0;
7396                 udelay(1);
7397         }
7398         return -ETIMEDOUT;
7399 }
7400
7401 static int gfx_v10_0_soft_reset(void *handle)
7402 {
7403         u32 grbm_soft_reset = 0;
7404         u32 tmp;
7405         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7406
7407         /* GRBM_STATUS */
7408         tmp = RREG32_SOC15(GC, 0, mmGRBM_STATUS);
7409         if (tmp & (GRBM_STATUS__PA_BUSY_MASK | GRBM_STATUS__SC_BUSY_MASK |
7410                    GRBM_STATUS__BCI_BUSY_MASK | GRBM_STATUS__SX_BUSY_MASK |
7411                    GRBM_STATUS__TA_BUSY_MASK | GRBM_STATUS__DB_BUSY_MASK |
7412                    GRBM_STATUS__CB_BUSY_MASK | GRBM_STATUS__GDS_BUSY_MASK |
7413                    GRBM_STATUS__SPI_BUSY_MASK | GRBM_STATUS__GE_BUSY_NO_DMA_MASK)) {
7414                 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
7415                                                 GRBM_SOFT_RESET, SOFT_RESET_CP,
7416                                                 1);
7417                 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
7418                                                 GRBM_SOFT_RESET, SOFT_RESET_GFX,
7419                                                 1);
7420         }
7421
7422         if (tmp & (GRBM_STATUS__CP_BUSY_MASK | GRBM_STATUS__CP_COHERENCY_BUSY_MASK)) {
7423                 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
7424                                                 GRBM_SOFT_RESET, SOFT_RESET_CP,
7425                                                 1);
7426         }
7427
7428         /* GRBM_STATUS2 */
7429         tmp = RREG32_SOC15(GC, 0, mmGRBM_STATUS2);
7430         switch (adev->asic_type) {
7431         case CHIP_SIENNA_CICHLID:
7432         case CHIP_NAVY_FLOUNDER:
7433         case CHIP_VANGOGH:
7434         case CHIP_DIMGREY_CAVEFISH:
7435                 if (REG_GET_FIELD(tmp, GRBM_STATUS2, RLC_BUSY_Sienna_Cichlid))
7436                         grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
7437                                                         GRBM_SOFT_RESET,
7438                                                         SOFT_RESET_RLC,
7439                                                         1);
7440                 break;
7441         default:
7442                 if (REG_GET_FIELD(tmp, GRBM_STATUS2, RLC_BUSY))
7443                         grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
7444                                                         GRBM_SOFT_RESET,
7445                                                         SOFT_RESET_RLC,
7446                                                         1);
7447                 break;
7448         }
7449
7450         if (grbm_soft_reset) {
7451                 /* stop the rlc */
7452                 gfx_v10_0_rlc_stop(adev);
7453
7454                 /* Disable GFX parsing/prefetching */
7455                 gfx_v10_0_cp_gfx_enable(adev, false);
7456
7457                 /* Disable MEC parsing/prefetching */
7458                 gfx_v10_0_cp_compute_enable(adev, false);
7459
7460                 if (grbm_soft_reset) {
7461                         tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET);
7462                         tmp |= grbm_soft_reset;
7463                         dev_info(adev->dev, "GRBM_SOFT_RESET=0x%08X\n", tmp);
7464                         WREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET, tmp);
7465                         tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET);
7466
7467                         udelay(50);
7468
7469                         tmp &= ~grbm_soft_reset;
7470                         WREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET, tmp);
7471                         tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET);
7472                 }
7473
7474                 /* Wait a little for things to settle down */
7475                 udelay(50);
7476         }
7477         return 0;
7478 }
7479
7480 static uint64_t gfx_v10_0_get_gpu_clock_counter(struct amdgpu_device *adev)
7481 {
7482         uint64_t clock;
7483
7484         amdgpu_gfx_off_ctrl(adev, false);
7485         mutex_lock(&adev->gfx.gpu_clock_mutex);
7486         switch (adev->asic_type) {
7487         case CHIP_VANGOGH:
7488                 clock = (uint64_t)RREG32_SOC15(SMUIO, 0, mmGOLDEN_TSC_COUNT_LOWER_Vangogh) |
7489                         ((uint64_t)RREG32_SOC15(SMUIO, 0, mmGOLDEN_TSC_COUNT_UPPER_Vangogh) << 32ULL);
7490                 break;
7491         default:
7492                 clock = (uint64_t)RREG32_SOC15(SMUIO, 0, mmGOLDEN_TSC_COUNT_LOWER) |
7493                         ((uint64_t)RREG32_SOC15(SMUIO, 0, mmGOLDEN_TSC_COUNT_UPPER) << 32ULL);
7494                 break;
7495         }
7496         mutex_unlock(&adev->gfx.gpu_clock_mutex);
7497         amdgpu_gfx_off_ctrl(adev, true);
7498         return clock;
7499 }
7500
7501 static void gfx_v10_0_ring_emit_gds_switch(struct amdgpu_ring *ring,
7502                                            uint32_t vmid,
7503                                            uint32_t gds_base, uint32_t gds_size,
7504                                            uint32_t gws_base, uint32_t gws_size,
7505                                            uint32_t oa_base, uint32_t oa_size)
7506 {
7507         struct amdgpu_device *adev = ring->adev;
7508
7509         /* GDS Base */
7510         gfx_v10_0_write_data_to_reg(ring, 0, false,
7511                                     SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_BASE) + 2 * vmid,
7512                                     gds_base);
7513
7514         /* GDS Size */
7515         gfx_v10_0_write_data_to_reg(ring, 0, false,
7516                                     SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_SIZE) + 2 * vmid,
7517                                     gds_size);
7518
7519         /* GWS */
7520         gfx_v10_0_write_data_to_reg(ring, 0, false,
7521                                     SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID0) + vmid,
7522                                     gws_size << GDS_GWS_VMID0__SIZE__SHIFT | gws_base);
7523
7524         /* OA */
7525         gfx_v10_0_write_data_to_reg(ring, 0, false,
7526                                     SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID0) + vmid,
7527                                     (1 << (oa_size + oa_base)) - (1 << oa_base));
7528 }
7529
7530 static int gfx_v10_0_early_init(void *handle)
7531 {
7532         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7533
7534         switch (adev->asic_type) {
7535         case CHIP_NAVI10:
7536         case CHIP_NAVI14:
7537         case CHIP_NAVI12:
7538                 adev->gfx.num_gfx_rings = GFX10_NUM_GFX_RINGS_NV1X;
7539                 break;
7540         case CHIP_SIENNA_CICHLID:
7541         case CHIP_NAVY_FLOUNDER:
7542         case CHIP_VANGOGH:
7543         case CHIP_DIMGREY_CAVEFISH:
7544                 adev->gfx.num_gfx_rings = GFX10_NUM_GFX_RINGS_Sienna_Cichlid;
7545                 break;
7546         default:
7547                 break;
7548         }
7549
7550         adev->gfx.num_compute_rings = min(amdgpu_gfx_get_num_kcq(adev),
7551                                           AMDGPU_MAX_COMPUTE_RINGS);
7552
7553         gfx_v10_0_set_kiq_pm4_funcs(adev);
7554         gfx_v10_0_set_ring_funcs(adev);
7555         gfx_v10_0_set_irq_funcs(adev);
7556         gfx_v10_0_set_gds_init(adev);
7557         gfx_v10_0_set_rlc_funcs(adev);
7558
7559         return 0;
7560 }
7561
7562 static int gfx_v10_0_late_init(void *handle)
7563 {
7564         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7565         int r;
7566
7567         r = amdgpu_irq_get(adev, &adev->gfx.priv_reg_irq, 0);
7568         if (r)
7569                 return r;
7570
7571         r = amdgpu_irq_get(adev, &adev->gfx.priv_inst_irq, 0);
7572         if (r)
7573                 return r;
7574
7575         return 0;
7576 }
7577
7578 static bool gfx_v10_0_is_rlc_enabled(struct amdgpu_device *adev)
7579 {
7580         uint32_t rlc_cntl;
7581
7582         /* if RLC is not enabled, do nothing */
7583         rlc_cntl = RREG32_SOC15(GC, 0, mmRLC_CNTL);
7584         return (REG_GET_FIELD(rlc_cntl, RLC_CNTL, RLC_ENABLE_F32)) ? true : false;
7585 }
7586
7587 static void gfx_v10_0_set_safe_mode(struct amdgpu_device *adev)
7588 {
7589         uint32_t data;
7590         unsigned i;
7591
7592         data = RLC_SAFE_MODE__CMD_MASK;
7593         data |= (1 << RLC_SAFE_MODE__MESSAGE__SHIFT);
7594
7595         switch (adev->asic_type) {
7596         case CHIP_SIENNA_CICHLID:
7597         case CHIP_NAVY_FLOUNDER:
7598         case CHIP_VANGOGH:
7599         case CHIP_DIMGREY_CAVEFISH:
7600                 WREG32_SOC15(GC, 0, mmRLC_SAFE_MODE_Sienna_Cichlid, data);
7601
7602                 /* wait for RLC_SAFE_MODE */
7603                 for (i = 0; i < adev->usec_timeout; i++) {
7604                         if (!REG_GET_FIELD(RREG32_SOC15(GC, 0, mmRLC_SAFE_MODE_Sienna_Cichlid),
7605                                            RLC_SAFE_MODE, CMD))
7606                                 break;
7607                         udelay(1);
7608                 }
7609                 break;
7610         default:
7611                 WREG32_SOC15(GC, 0, mmRLC_SAFE_MODE, data);
7612
7613                 /* wait for RLC_SAFE_MODE */
7614                 for (i = 0; i < adev->usec_timeout; i++) {
7615                         if (!REG_GET_FIELD(RREG32_SOC15(GC, 0, mmRLC_SAFE_MODE),
7616                                            RLC_SAFE_MODE, CMD))
7617                                 break;
7618                         udelay(1);
7619                 }
7620                 break;
7621         }
7622 }
7623
7624 static void gfx_v10_0_unset_safe_mode(struct amdgpu_device *adev)
7625 {
7626         uint32_t data;
7627
7628         data = RLC_SAFE_MODE__CMD_MASK;
7629         switch (adev->asic_type) {
7630         case CHIP_SIENNA_CICHLID:
7631         case CHIP_NAVY_FLOUNDER:
7632         case CHIP_VANGOGH:
7633         case CHIP_DIMGREY_CAVEFISH:
7634                 WREG32_SOC15(GC, 0, mmRLC_SAFE_MODE_Sienna_Cichlid, data);
7635                 break;
7636         default:
7637                 WREG32_SOC15(GC, 0, mmRLC_SAFE_MODE, data);
7638                 break;
7639         }
7640 }
7641
7642 static void gfx_v10_0_update_medium_grain_clock_gating(struct amdgpu_device *adev,
7643                                                       bool enable)
7644 {
7645         uint32_t data, def;
7646
7647         /* It is disabled by HW by default */
7648         if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG)) {
7649                 /* 0 - Disable some blocks' MGCG */
7650                 WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, 0xe0000000);
7651                 WREG32_SOC15(GC, 0, mmCGTT_WD_CLK_CTRL, 0xff000000);
7652                 WREG32_SOC15(GC, 0, mmCGTT_VGT_CLK_CTRL, 0xff000000);
7653                 WREG32_SOC15(GC, 0, mmCGTT_IA_CLK_CTRL, 0xff000000);
7654
7655                 /* 1 - RLC_CGTT_MGCG_OVERRIDE */
7656                 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
7657                 data &= ~(RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK |
7658                           RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK |
7659                           RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK |
7660                           RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGLS_OVERRIDE_MASK |
7661                           RLC_CGTT_MGCG_OVERRIDE__ENABLE_CGTS_LEGACY_MASK);
7662
7663                 if (def != data)
7664                         WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data);
7665
7666                 /* MGLS is a global flag to control all MGLS in GFX */
7667                 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGLS) {
7668                         /* 2 - RLC memory Light sleep */
7669                         if (adev->cg_flags & AMD_CG_SUPPORT_GFX_RLC_LS) {
7670                                 def = data = RREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL);
7671                                 data |= RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK;
7672                                 if (def != data)
7673                                         WREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL, data);
7674                         }
7675                         /* 3 - CP memory Light sleep */
7676                         if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CP_LS) {
7677                                 def = data = RREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL);
7678                                 data |= CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK;
7679                                 if (def != data)
7680                                         WREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL, data);
7681                         }
7682                 }
7683         } else {
7684                 /* 1 - MGCG_OVERRIDE */
7685                 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
7686                 data |= (RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK |
7687                          RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK |
7688                          RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK |
7689                          RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGLS_OVERRIDE_MASK);
7690                 if (def != data)
7691                         WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data);
7692
7693                 /* 2 - disable MGLS in CP */
7694                 data = RREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL);
7695                 if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK) {
7696                         data &= ~CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK;
7697                         WREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL, data);
7698                 }
7699
7700                 /* 3 - disable MGLS in RLC */
7701                 data = RREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL);
7702                 if (data & RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK) {
7703                         data &= ~RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK;
7704                         WREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL, data);
7705                 }
7706
7707         }
7708 }
7709
7710 static void gfx_v10_0_update_3d_clock_gating(struct amdgpu_device *adev,
7711                                            bool enable)
7712 {
7713         uint32_t data, def;
7714
7715         /* Enable 3D CGCG/CGLS */
7716         if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGCG)) {
7717                 /* write cmd to clear cgcg/cgls ov */
7718                 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
7719                 /* unset CGCG override */
7720                 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_GFX3D_CG_OVERRIDE_MASK;
7721                 /* update CGCG and CGLS override bits */
7722                 if (def != data)
7723                         WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data);
7724                 /* enable 3Dcgcg FSM(0x0000363f) */
7725                 def = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D);
7726                 data = (0x36 << RLC_CGCG_CGLS_CTRL_3D__CGCG_GFX_IDLE_THRESHOLD__SHIFT) |
7727                         RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK;
7728                 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGLS)
7729                         data |= (0x000F << RLC_CGCG_CGLS_CTRL_3D__CGLS_REP_COMPANSAT_DELAY__SHIFT) |
7730                                 RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK;
7731                 if (def != data)
7732                         WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D, data);
7733
7734                 /* set IDLE_POLL_COUNT(0x00900100) */
7735                 def = RREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL);
7736                 data = (0x0100 << CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY__SHIFT) |
7737                         (0x0090 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT);
7738                 if (def != data)
7739                         WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL, data);
7740         } else {
7741                 /* Disable CGCG/CGLS */
7742                 def = data = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D);
7743                 /* disable cgcg, cgls should be disabled */
7744                 data &= ~(RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK |
7745                           RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK);
7746                 /* disable cgcg and cgls in FSM */
7747                 if (def != data)
7748                         WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D, data);
7749         }
7750 }
7751
7752 static void gfx_v10_0_update_coarse_grain_clock_gating(struct amdgpu_device *adev,
7753                                                       bool enable)
7754 {
7755         uint32_t def, data;
7756
7757         if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG)) {
7758                 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
7759                 /* unset CGCG override */
7760                 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGCG_OVERRIDE_MASK;
7761                 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS)
7762                         data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGLS_OVERRIDE_MASK;
7763                 else
7764                         data |= RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGLS_OVERRIDE_MASK;
7765                 /* update CGCG and CGLS override bits */
7766                 if (def != data)
7767                         WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data);
7768
7769                 /* enable cgcg FSM(0x0000363F) */
7770                 def = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL);
7771                 data = (0x36 << RLC_CGCG_CGLS_CTRL__CGCG_GFX_IDLE_THRESHOLD__SHIFT) |
7772                         RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK;
7773                 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS)
7774                         data |= (0x000F << RLC_CGCG_CGLS_CTRL__CGLS_REP_COMPANSAT_DELAY__SHIFT) |
7775                                 RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK;
7776                 if (def != data)
7777                         WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL, data);
7778
7779                 /* set IDLE_POLL_COUNT(0x00900100) */
7780                 def = RREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL);
7781                 data = (0x0100 << CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY__SHIFT) |
7782                         (0x0090 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT);
7783                 if (def != data)
7784                         WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL, data);
7785         } else {
7786                 def = data = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL);
7787                 /* reset CGCG/CGLS bits */
7788                 data &= ~(RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK | RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK);
7789                 /* disable cgcg and cgls in FSM */
7790                 if (def != data)
7791                         WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL, data);
7792         }
7793 }
7794
7795 static void gfx_v10_0_update_fine_grain_clock_gating(struct amdgpu_device *adev,
7796                                                       bool enable)
7797 {
7798         uint32_t def, data;
7799
7800         if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_FGCG)) {
7801                 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
7802                 /* unset FGCG override */
7803                 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK;
7804                 /* update FGCG override bits */
7805                 if (def != data)
7806                         WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data);
7807
7808                 def = data = RREG32_SOC15(GC, 0, mmRLC_CLK_CNTL);
7809                 /* unset RLC SRAM CLK GATER override */
7810                 data &= ~RLC_CLK_CNTL__RLC_SRAM_CLK_GATER_OVERRIDE_MASK;
7811                 /* update RLC SRAM CLK GATER override bits */
7812                 if (def != data)
7813                         WREG32_SOC15(GC, 0, mmRLC_CLK_CNTL, data);
7814         } else {
7815                 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
7816                 /* reset FGCG bits */
7817                 data |= RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK;
7818                 /* disable FGCG*/
7819                 if (def != data)
7820                         WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data);
7821
7822                 def = data = RREG32_SOC15(GC, 0, mmRLC_CLK_CNTL);
7823                 /* reset RLC SRAM CLK GATER bits */
7824                 data |= RLC_CLK_CNTL__RLC_SRAM_CLK_GATER_OVERRIDE_MASK;
7825                 /* disable RLC SRAM CLK*/
7826                 if (def != data)
7827                         WREG32_SOC15(GC, 0, mmRLC_CLK_CNTL, data);
7828         }
7829 }
7830
7831 static int gfx_v10_0_update_gfx_clock_gating(struct amdgpu_device *adev,
7832                                             bool enable)
7833 {
7834         amdgpu_gfx_rlc_enter_safe_mode(adev);
7835
7836         if (enable) {
7837                 /* enable FGCG firstly*/
7838                 gfx_v10_0_update_fine_grain_clock_gating(adev, enable);
7839                 /* CGCG/CGLS should be enabled after MGCG/MGLS
7840                  * ===  MGCG + MGLS ===
7841                  */
7842                 gfx_v10_0_update_medium_grain_clock_gating(adev, enable);
7843                 /* ===  CGCG /CGLS for GFX 3D Only === */
7844                 gfx_v10_0_update_3d_clock_gating(adev, enable);
7845                 /* ===  CGCG + CGLS === */
7846                 gfx_v10_0_update_coarse_grain_clock_gating(adev, enable);
7847         } else {
7848                 /* CGCG/CGLS should be disabled before MGCG/MGLS
7849                  * ===  CGCG + CGLS ===
7850                  */
7851                 gfx_v10_0_update_coarse_grain_clock_gating(adev, enable);
7852                 /* ===  CGCG /CGLS for GFX 3D Only === */
7853                 gfx_v10_0_update_3d_clock_gating(adev, enable);
7854                 /* ===  MGCG + MGLS === */
7855                 gfx_v10_0_update_medium_grain_clock_gating(adev, enable);
7856                 /* disable fgcg at last*/
7857                 gfx_v10_0_update_fine_grain_clock_gating(adev, enable);
7858         }
7859
7860         if (adev->cg_flags &
7861             (AMD_CG_SUPPORT_GFX_MGCG |
7862              AMD_CG_SUPPORT_GFX_CGLS |
7863              AMD_CG_SUPPORT_GFX_CGCG |
7864              AMD_CG_SUPPORT_GFX_3D_CGCG |
7865              AMD_CG_SUPPORT_GFX_3D_CGLS))
7866                 gfx_v10_0_enable_gui_idle_interrupt(adev, enable);
7867
7868         amdgpu_gfx_rlc_exit_safe_mode(adev);
7869
7870         return 0;
7871 }
7872
7873 static void gfx_v10_0_update_spm_vmid(struct amdgpu_device *adev, unsigned vmid)
7874 {
7875         u32 reg, data;
7876
7877         reg = SOC15_REG_OFFSET(GC, 0, mmRLC_SPM_MC_CNTL);
7878         if (amdgpu_sriov_is_pp_one_vf(adev))
7879                 data = RREG32_NO_KIQ(reg);
7880         else
7881                 data = RREG32(reg);
7882
7883         data &= ~RLC_SPM_MC_CNTL__RLC_SPM_VMID_MASK;
7884         data |= (vmid & RLC_SPM_MC_CNTL__RLC_SPM_VMID_MASK) << RLC_SPM_MC_CNTL__RLC_SPM_VMID__SHIFT;
7885
7886         if (amdgpu_sriov_is_pp_one_vf(adev))
7887                 WREG32_SOC15_NO_KIQ(GC, 0, mmRLC_SPM_MC_CNTL, data);
7888         else
7889                 WREG32_SOC15(GC, 0, mmRLC_SPM_MC_CNTL, data);
7890 }
7891
7892 static bool gfx_v10_0_check_rlcg_range(struct amdgpu_device *adev,
7893                                         uint32_t offset,
7894                                         struct soc15_reg_rlcg *entries, int arr_size)
7895 {
7896         int i;
7897         uint32_t reg;
7898
7899         if (!entries)
7900                 return false;
7901
7902         for (i = 0; i < arr_size; i++) {
7903                 const struct soc15_reg_rlcg *entry;
7904
7905                 entry = &entries[i];
7906                 reg = adev->reg_offset[entry->hwip][entry->instance][entry->segment] + entry->reg;
7907                 if (offset == reg)
7908                         return true;
7909         }
7910
7911         return false;
7912 }
7913
7914 static bool gfx_v10_0_is_rlcg_access_range(struct amdgpu_device *adev, u32 offset)
7915 {
7916         return gfx_v10_0_check_rlcg_range(adev, offset, NULL, 0);
7917 }
7918
7919 static void gfx_v10_cntl_power_gating(struct amdgpu_device *adev, bool enable)
7920 {
7921         u32 data = RREG32_SOC15(GC, 0, mmRLC_PG_CNTL);
7922
7923         if (enable && (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG))
7924                 data |= RLC_PG_CNTL__GFX_POWER_GATING_ENABLE_MASK;
7925         else
7926                 data &= ~RLC_PG_CNTL__GFX_POWER_GATING_ENABLE_MASK;
7927
7928         WREG32_SOC15(GC, 0, mmRLC_PG_CNTL, data);
7929
7930         /*
7931          * CGPG enablement required and the register to program the hysteresis value
7932          * RLC_PG_DELAY_3.CGCG_ACTIVE_BEFORE_CGPG to the desired CGPG hysteresis value
7933          * in refclk count. Note that RLC FW is modified to take 16 bits from
7934          * RLC_PG_DELAY_3[15:0] as the hysteresis instead of just 8 bits.
7935          *
7936          * The recommendation from RLC team is setting RLC_PG_DELAY_3 to 200us(0x4E20)
7937          * as part of CGPG enablement starting point.
7938          */
7939         if (enable && (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG) && adev->asic_type == CHIP_VANGOGH) {
7940                 data = 0x4E20 & RLC_PG_DELAY_3__CGCG_ACTIVE_BEFORE_CGPG_MASK_Vangogh;
7941                 WREG32_SOC15(GC, 0, mmRLC_PG_DELAY_3, data);
7942         }
7943 }
7944
7945 static void gfx_v10_cntl_pg(struct amdgpu_device *adev, bool enable)
7946 {
7947         amdgpu_gfx_rlc_enter_safe_mode(adev);
7948
7949         gfx_v10_cntl_power_gating(adev, enable);
7950
7951         amdgpu_gfx_rlc_exit_safe_mode(adev);
7952 }
7953
7954 static const struct amdgpu_rlc_funcs gfx_v10_0_rlc_funcs = {
7955         .is_rlc_enabled = gfx_v10_0_is_rlc_enabled,
7956         .set_safe_mode = gfx_v10_0_set_safe_mode,
7957         .unset_safe_mode = gfx_v10_0_unset_safe_mode,
7958         .init = gfx_v10_0_rlc_init,
7959         .get_csb_size = gfx_v10_0_get_csb_size,
7960         .get_csb_buffer = gfx_v10_0_get_csb_buffer,
7961         .resume = gfx_v10_0_rlc_resume,
7962         .stop = gfx_v10_0_rlc_stop,
7963         .reset = gfx_v10_0_rlc_reset,
7964         .start = gfx_v10_0_rlc_start,
7965         .update_spm_vmid = gfx_v10_0_update_spm_vmid,
7966 };
7967
7968 static const struct amdgpu_rlc_funcs gfx_v10_0_rlc_funcs_sriov = {
7969         .is_rlc_enabled = gfx_v10_0_is_rlc_enabled,
7970         .set_safe_mode = gfx_v10_0_set_safe_mode,
7971         .unset_safe_mode = gfx_v10_0_unset_safe_mode,
7972         .init = gfx_v10_0_rlc_init,
7973         .get_csb_size = gfx_v10_0_get_csb_size,
7974         .get_csb_buffer = gfx_v10_0_get_csb_buffer,
7975         .resume = gfx_v10_0_rlc_resume,
7976         .stop = gfx_v10_0_rlc_stop,
7977         .reset = gfx_v10_0_rlc_reset,
7978         .start = gfx_v10_0_rlc_start,
7979         .update_spm_vmid = gfx_v10_0_update_spm_vmid,
7980         .rlcg_wreg = gfx_v10_rlcg_wreg,
7981         .rlcg_rreg = gfx_v10_rlcg_rreg,
7982         .is_rlcg_access_range = gfx_v10_0_is_rlcg_access_range,
7983 };
7984
7985 static int gfx_v10_0_set_powergating_state(void *handle,
7986                                           enum amd_powergating_state state)
7987 {
7988         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7989         bool enable = (state == AMD_PG_STATE_GATE);
7990
7991         if (amdgpu_sriov_vf(adev))
7992                 return 0;
7993
7994         switch (adev->asic_type) {
7995         case CHIP_NAVI10:
7996         case CHIP_NAVI14:
7997         case CHIP_NAVI12:
7998         case CHIP_SIENNA_CICHLID:
7999         case CHIP_NAVY_FLOUNDER:
8000         case CHIP_DIMGREY_CAVEFISH:
8001                 amdgpu_gfx_off_ctrl(adev, enable);
8002                 break;
8003         case CHIP_VANGOGH:
8004                 gfx_v10_cntl_pg(adev, enable);
8005                 amdgpu_gfx_off_ctrl(adev, enable);
8006                 break;
8007         default:
8008                 break;
8009         }
8010         return 0;
8011 }
8012
8013 static int gfx_v10_0_set_clockgating_state(void *handle,
8014                                           enum amd_clockgating_state state)
8015 {
8016         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
8017
8018         if (amdgpu_sriov_vf(adev))
8019                 return 0;
8020
8021         switch (adev->asic_type) {
8022         case CHIP_NAVI10:
8023         case CHIP_NAVI14:
8024         case CHIP_NAVI12:
8025         case CHIP_SIENNA_CICHLID:
8026         case CHIP_NAVY_FLOUNDER:
8027         case CHIP_VANGOGH:
8028         case CHIP_DIMGREY_CAVEFISH:
8029                 gfx_v10_0_update_gfx_clock_gating(adev,
8030                                                  state == AMD_CG_STATE_GATE);
8031                 break;
8032         default:
8033                 break;
8034         }
8035         return 0;
8036 }
8037
8038 static void gfx_v10_0_get_clockgating_state(void *handle, u32 *flags)
8039 {
8040         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
8041         int data;
8042
8043         /* AMD_CG_SUPPORT_GFX_FGCG */
8044         data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE));
8045         if (!(data & RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK))
8046                 *flags |= AMD_CG_SUPPORT_GFX_FGCG;
8047
8048         /* AMD_CG_SUPPORT_GFX_MGCG */
8049         data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE));
8050         if (!(data & RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK))
8051                 *flags |= AMD_CG_SUPPORT_GFX_MGCG;
8052
8053         /* AMD_CG_SUPPORT_GFX_CGCG */
8054         data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_CGCG_CGLS_CTRL));
8055         if (data & RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK)
8056                 *flags |= AMD_CG_SUPPORT_GFX_CGCG;
8057
8058         /* AMD_CG_SUPPORT_GFX_CGLS */
8059         if (data & RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK)
8060                 *flags |= AMD_CG_SUPPORT_GFX_CGLS;
8061
8062         /* AMD_CG_SUPPORT_GFX_RLC_LS */
8063         data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_MEM_SLP_CNTL));
8064         if (data & RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK)
8065                 *flags |= AMD_CG_SUPPORT_GFX_RLC_LS | AMD_CG_SUPPORT_GFX_MGLS;
8066
8067         /* AMD_CG_SUPPORT_GFX_CP_LS */
8068         data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmCP_MEM_SLP_CNTL));
8069         if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK)
8070                 *flags |= AMD_CG_SUPPORT_GFX_CP_LS | AMD_CG_SUPPORT_GFX_MGLS;
8071
8072         /* AMD_CG_SUPPORT_GFX_3D_CGCG */
8073         data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D));
8074         if (data & RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK)
8075                 *flags |= AMD_CG_SUPPORT_GFX_3D_CGCG;
8076
8077         /* AMD_CG_SUPPORT_GFX_3D_CGLS */
8078         if (data & RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK)
8079                 *flags |= AMD_CG_SUPPORT_GFX_3D_CGLS;
8080 }
8081
8082 static u64 gfx_v10_0_ring_get_rptr_gfx(struct amdgpu_ring *ring)
8083 {
8084         return ring->adev->wb.wb[ring->rptr_offs]; /* gfx10 is 32bit rptr*/
8085 }
8086
8087 static u64 gfx_v10_0_ring_get_wptr_gfx(struct amdgpu_ring *ring)
8088 {
8089         struct amdgpu_device *adev = ring->adev;
8090         u64 wptr;
8091
8092         /* XXX check if swapping is necessary on BE */
8093         if (ring->use_doorbell) {
8094                 wptr = atomic64_read((atomic64_t *)&adev->wb.wb[ring->wptr_offs]);
8095         } else {
8096                 wptr = RREG32_SOC15(GC, 0, mmCP_RB0_WPTR);
8097                 wptr += (u64)RREG32_SOC15(GC, 0, mmCP_RB0_WPTR_HI) << 32;
8098         }
8099
8100         return wptr;
8101 }
8102
8103 static void gfx_v10_0_ring_set_wptr_gfx(struct amdgpu_ring *ring)
8104 {
8105         struct amdgpu_device *adev = ring->adev;
8106
8107         if (ring->use_doorbell) {
8108                 /* XXX check if swapping is necessary on BE */
8109                 atomic64_set((atomic64_t *)&adev->wb.wb[ring->wptr_offs], ring->wptr);
8110                 WDOORBELL64(ring->doorbell_index, ring->wptr);
8111         } else {
8112                 WREG32_SOC15(GC, 0, mmCP_RB0_WPTR, lower_32_bits(ring->wptr));
8113                 WREG32_SOC15(GC, 0, mmCP_RB0_WPTR_HI, upper_32_bits(ring->wptr));
8114         }
8115 }
8116
8117 static u64 gfx_v10_0_ring_get_rptr_compute(struct amdgpu_ring *ring)
8118 {
8119         return ring->adev->wb.wb[ring->rptr_offs]; /* gfx10 hardware is 32bit rptr */
8120 }
8121
8122 static u64 gfx_v10_0_ring_get_wptr_compute(struct amdgpu_ring *ring)
8123 {
8124         u64 wptr;
8125
8126         /* XXX check if swapping is necessary on BE */
8127         if (ring->use_doorbell)
8128                 wptr = atomic64_read((atomic64_t *)&ring->adev->wb.wb[ring->wptr_offs]);
8129         else
8130                 BUG();
8131         return wptr;
8132 }
8133
8134 static void gfx_v10_0_ring_set_wptr_compute(struct amdgpu_ring *ring)
8135 {
8136         struct amdgpu_device *adev = ring->adev;
8137
8138         /* XXX check if swapping is necessary on BE */
8139         if (ring->use_doorbell) {
8140                 atomic64_set((atomic64_t *)&adev->wb.wb[ring->wptr_offs], ring->wptr);
8141                 WDOORBELL64(ring->doorbell_index, ring->wptr);
8142         } else {
8143                 BUG(); /* only DOORBELL method supported on gfx10 now */
8144         }
8145 }
8146
8147 static void gfx_v10_0_ring_emit_hdp_flush(struct amdgpu_ring *ring)
8148 {
8149         struct amdgpu_device *adev = ring->adev;
8150         u32 ref_and_mask, reg_mem_engine;
8151         const struct nbio_hdp_flush_reg *nbio_hf_reg = adev->nbio.hdp_flush_reg;
8152
8153         if (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE) {
8154                 switch (ring->me) {
8155                 case 1:
8156                         ref_and_mask = nbio_hf_reg->ref_and_mask_cp2 << ring->pipe;
8157                         break;
8158                 case 2:
8159                         ref_and_mask = nbio_hf_reg->ref_and_mask_cp6 << ring->pipe;
8160                         break;
8161                 default:
8162                         return;
8163                 }
8164                 reg_mem_engine = 0;
8165         } else {
8166                 ref_and_mask = nbio_hf_reg->ref_and_mask_cp0;
8167                 reg_mem_engine = 1; /* pfp */
8168         }
8169
8170         gfx_v10_0_wait_reg_mem(ring, reg_mem_engine, 0, 1,
8171                                adev->nbio.funcs->get_hdp_flush_req_offset(adev),
8172                                adev->nbio.funcs->get_hdp_flush_done_offset(adev),
8173                                ref_and_mask, ref_and_mask, 0x20);
8174 }
8175
8176 static void gfx_v10_0_ring_emit_ib_gfx(struct amdgpu_ring *ring,
8177                                        struct amdgpu_job *job,
8178                                        struct amdgpu_ib *ib,
8179                                        uint32_t flags)
8180 {
8181         unsigned vmid = AMDGPU_JOB_GET_VMID(job);
8182         u32 header, control = 0;
8183
8184         if (ib->flags & AMDGPU_IB_FLAG_CE)
8185                 header = PACKET3(PACKET3_INDIRECT_BUFFER_CNST, 2);
8186         else
8187                 header = PACKET3(PACKET3_INDIRECT_BUFFER, 2);
8188
8189         control |= ib->length_dw | (vmid << 24);
8190
8191         if ((amdgpu_sriov_vf(ring->adev) || amdgpu_mcbp) && (ib->flags & AMDGPU_IB_FLAG_PREEMPT)) {
8192                 control |= INDIRECT_BUFFER_PRE_ENB(1);
8193
8194                 if (flags & AMDGPU_IB_PREEMPTED)
8195                         control |= INDIRECT_BUFFER_PRE_RESUME(1);
8196
8197                 if (!(ib->flags & AMDGPU_IB_FLAG_CE) && vmid)
8198                         gfx_v10_0_ring_emit_de_meta(ring,
8199                                     (!amdgpu_sriov_vf(ring->adev) && flags & AMDGPU_IB_PREEMPTED) ? true : false);
8200         }
8201
8202         amdgpu_ring_write(ring, header);
8203         BUG_ON(ib->gpu_addr & 0x3); /* Dword align */
8204         amdgpu_ring_write(ring,
8205 #ifdef __BIG_ENDIAN
8206                 (2 << 0) |
8207 #endif
8208                 lower_32_bits(ib->gpu_addr));
8209         amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
8210         amdgpu_ring_write(ring, control);
8211 }
8212
8213 static void gfx_v10_0_ring_emit_ib_compute(struct amdgpu_ring *ring,
8214                                            struct amdgpu_job *job,
8215                                            struct amdgpu_ib *ib,
8216                                            uint32_t flags)
8217 {
8218         unsigned vmid = AMDGPU_JOB_GET_VMID(job);
8219         u32 control = INDIRECT_BUFFER_VALID | ib->length_dw | (vmid << 24);
8220
8221         /* Currently, there is a high possibility to get wave ID mismatch
8222          * between ME and GDS, leading to a hw deadlock, because ME generates
8223          * different wave IDs than the GDS expects. This situation happens
8224          * randomly when at least 5 compute pipes use GDS ordered append.
8225          * The wave IDs generated by ME are also wrong after suspend/resume.
8226          * Those are probably bugs somewhere else in the kernel driver.
8227          *
8228          * Writing GDS_COMPUTE_MAX_WAVE_ID resets wave ID counters in ME and
8229          * GDS to 0 for this ring (me/pipe).
8230          */
8231         if (ib->flags & AMDGPU_IB_FLAG_RESET_GDS_MAX_WAVE_ID) {
8232                 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
8233                 amdgpu_ring_write(ring, mmGDS_COMPUTE_MAX_WAVE_ID);
8234                 amdgpu_ring_write(ring, ring->adev->gds.gds_compute_max_wave_id);
8235         }
8236
8237         amdgpu_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2));
8238         BUG_ON(ib->gpu_addr & 0x3); /* Dword align */
8239         amdgpu_ring_write(ring,
8240 #ifdef __BIG_ENDIAN
8241                                 (2 << 0) |
8242 #endif
8243                                 lower_32_bits(ib->gpu_addr));
8244         amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
8245         amdgpu_ring_write(ring, control);
8246 }
8247
8248 static void gfx_v10_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr,
8249                                      u64 seq, unsigned flags)
8250 {
8251         bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT;
8252         bool int_sel = flags & AMDGPU_FENCE_FLAG_INT;
8253
8254         /* RELEASE_MEM - flush caches, send int */
8255         amdgpu_ring_write(ring, PACKET3(PACKET3_RELEASE_MEM, 6));
8256         amdgpu_ring_write(ring, (PACKET3_RELEASE_MEM_GCR_SEQ |
8257                                  PACKET3_RELEASE_MEM_GCR_GL2_WB |
8258                                  PACKET3_RELEASE_MEM_GCR_GLM_INV | /* must be set with GLM_WB */
8259                                  PACKET3_RELEASE_MEM_GCR_GLM_WB |
8260                                  PACKET3_RELEASE_MEM_CACHE_POLICY(3) |
8261                                  PACKET3_RELEASE_MEM_EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) |
8262                                  PACKET3_RELEASE_MEM_EVENT_INDEX(5)));
8263         amdgpu_ring_write(ring, (PACKET3_RELEASE_MEM_DATA_SEL(write64bit ? 2 : 1) |
8264                                  PACKET3_RELEASE_MEM_INT_SEL(int_sel ? 2 : 0)));
8265
8266         /*
8267          * the address should be Qword aligned if 64bit write, Dword
8268          * aligned if only send 32bit data low (discard data high)
8269          */
8270         if (write64bit)
8271                 BUG_ON(addr & 0x7);
8272         else
8273                 BUG_ON(addr & 0x3);
8274         amdgpu_ring_write(ring, lower_32_bits(addr));
8275         amdgpu_ring_write(ring, upper_32_bits(addr));
8276         amdgpu_ring_write(ring, lower_32_bits(seq));
8277         amdgpu_ring_write(ring, upper_32_bits(seq));
8278         amdgpu_ring_write(ring, 0);
8279 }
8280
8281 static void gfx_v10_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring)
8282 {
8283         int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX);
8284         uint32_t seq = ring->fence_drv.sync_seq;
8285         uint64_t addr = ring->fence_drv.gpu_addr;
8286
8287         gfx_v10_0_wait_reg_mem(ring, usepfp, 1, 0, lower_32_bits(addr),
8288                                upper_32_bits(addr), seq, 0xffffffff, 4);
8289 }
8290
8291 static void gfx_v10_0_ring_emit_vm_flush(struct amdgpu_ring *ring,
8292                                          unsigned vmid, uint64_t pd_addr)
8293 {
8294         amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr);
8295
8296         /* compute doesn't have PFP */
8297         if (ring->funcs->type == AMDGPU_RING_TYPE_GFX) {
8298                 /* sync PFP to ME, otherwise we might get invalid PFP reads */
8299                 amdgpu_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0));
8300                 amdgpu_ring_write(ring, 0x0);
8301         }
8302 }
8303
8304 static void gfx_v10_0_ring_emit_fence_kiq(struct amdgpu_ring *ring, u64 addr,
8305                                           u64 seq, unsigned int flags)
8306 {
8307         struct amdgpu_device *adev = ring->adev;
8308
8309         /* we only allocate 32bit for each seq wb address */
8310         BUG_ON(flags & AMDGPU_FENCE_FLAG_64BIT);
8311
8312         /* write fence seq to the "addr" */
8313         amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
8314         amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
8315                                  WRITE_DATA_DST_SEL(5) | WR_CONFIRM));
8316         amdgpu_ring_write(ring, lower_32_bits(addr));
8317         amdgpu_ring_write(ring, upper_32_bits(addr));
8318         amdgpu_ring_write(ring, lower_32_bits(seq));
8319
8320         if (flags & AMDGPU_FENCE_FLAG_INT) {
8321                 /* set register to trigger INT */
8322                 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
8323                 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
8324                                          WRITE_DATA_DST_SEL(0) | WR_CONFIRM));
8325                 amdgpu_ring_write(ring, SOC15_REG_OFFSET(GC, 0, mmCPC_INT_STATUS));
8326                 amdgpu_ring_write(ring, 0);
8327                 amdgpu_ring_write(ring, 0x20000000); /* src_id is 178 */
8328         }
8329 }
8330
8331 static void gfx_v10_0_ring_emit_sb(struct amdgpu_ring *ring)
8332 {
8333         amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0));
8334         amdgpu_ring_write(ring, 0);
8335 }
8336
8337 static void gfx_v10_0_ring_emit_cntxcntl(struct amdgpu_ring *ring,
8338                                          uint32_t flags)
8339 {
8340         uint32_t dw2 = 0;
8341
8342         if (amdgpu_mcbp || amdgpu_sriov_vf(ring->adev))
8343                 gfx_v10_0_ring_emit_ce_meta(ring,
8344                                     (!amdgpu_sriov_vf(ring->adev) && flags & AMDGPU_IB_PREEMPTED) ? true : false);
8345
8346         dw2 |= 0x80000000; /* set load_enable otherwise this package is just NOPs */
8347         if (flags & AMDGPU_HAVE_CTX_SWITCH) {
8348                 /* set load_global_config & load_global_uconfig */
8349                 dw2 |= 0x8001;
8350                 /* set load_cs_sh_regs */
8351                 dw2 |= 0x01000000;
8352                 /* set load_per_context_state & load_gfx_sh_regs for GFX */
8353                 dw2 |= 0x10002;
8354
8355                 /* set load_ce_ram if preamble presented */
8356                 if (AMDGPU_PREAMBLE_IB_PRESENT & flags)
8357                         dw2 |= 0x10000000;
8358         } else {
8359                 /* still load_ce_ram if this is the first time preamble presented
8360                  * although there is no context switch happens.
8361                  */
8362                 if (AMDGPU_PREAMBLE_IB_PRESENT_FIRST & flags)
8363                         dw2 |= 0x10000000;
8364         }
8365
8366         amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1));
8367         amdgpu_ring_write(ring, dw2);
8368         amdgpu_ring_write(ring, 0);
8369 }
8370
8371 static unsigned gfx_v10_0_ring_emit_init_cond_exec(struct amdgpu_ring *ring)
8372 {
8373         unsigned ret;
8374
8375         amdgpu_ring_write(ring, PACKET3(PACKET3_COND_EXEC, 3));
8376         amdgpu_ring_write(ring, lower_32_bits(ring->cond_exe_gpu_addr));
8377         amdgpu_ring_write(ring, upper_32_bits(ring->cond_exe_gpu_addr));
8378         amdgpu_ring_write(ring, 0); /* discard following DWs if *cond_exec_gpu_addr==0 */
8379         ret = ring->wptr & ring->buf_mask;
8380         amdgpu_ring_write(ring, 0x55aa55aa); /* patch dummy value later */
8381
8382         return ret;
8383 }
8384
8385 static void gfx_v10_0_ring_emit_patch_cond_exec(struct amdgpu_ring *ring, unsigned offset)
8386 {
8387         unsigned cur;
8388         BUG_ON(offset > ring->buf_mask);
8389         BUG_ON(ring->ring[offset] != 0x55aa55aa);
8390
8391         cur = (ring->wptr - 1) & ring->buf_mask;
8392         if (likely(cur > offset))
8393                 ring->ring[offset] = cur - offset;
8394         else
8395                 ring->ring[offset] = (ring->buf_mask + 1) - offset + cur;
8396 }
8397
8398 static int gfx_v10_0_ring_preempt_ib(struct amdgpu_ring *ring)
8399 {
8400         int i, r = 0;
8401         struct amdgpu_device *adev = ring->adev;
8402         struct amdgpu_kiq *kiq = &adev->gfx.kiq;
8403         struct amdgpu_ring *kiq_ring = &kiq->ring;
8404         unsigned long flags;
8405
8406         if (!kiq->pmf || !kiq->pmf->kiq_unmap_queues)
8407                 return -EINVAL;
8408
8409         spin_lock_irqsave(&kiq->ring_lock, flags);
8410
8411         if (amdgpu_ring_alloc(kiq_ring, kiq->pmf->unmap_queues_size)) {
8412                 spin_unlock_irqrestore(&kiq->ring_lock, flags);
8413                 return -ENOMEM;
8414         }
8415
8416         /* assert preemption condition */
8417         amdgpu_ring_set_preempt_cond_exec(ring, false);
8418
8419         /* assert IB preemption, emit the trailing fence */
8420         kiq->pmf->kiq_unmap_queues(kiq_ring, ring, PREEMPT_QUEUES_NO_UNMAP,
8421                                    ring->trail_fence_gpu_addr,
8422                                    ++ring->trail_seq);
8423         amdgpu_ring_commit(kiq_ring);
8424
8425         spin_unlock_irqrestore(&kiq->ring_lock, flags);
8426
8427         /* poll the trailing fence */
8428         for (i = 0; i < adev->usec_timeout; i++) {
8429                 if (ring->trail_seq ==
8430                     le32_to_cpu(*(ring->trail_fence_cpu_addr)))
8431                         break;
8432                 udelay(1);
8433         }
8434
8435         if (i >= adev->usec_timeout) {
8436                 r = -EINVAL;
8437                 DRM_ERROR("ring %d failed to preempt ib\n", ring->idx);
8438         }
8439
8440         /* deassert preemption condition */
8441         amdgpu_ring_set_preempt_cond_exec(ring, true);
8442         return r;
8443 }
8444
8445 static void gfx_v10_0_ring_emit_ce_meta(struct amdgpu_ring *ring, bool resume)
8446 {
8447         struct amdgpu_device *adev = ring->adev;
8448         struct v10_ce_ib_state ce_payload = {0};
8449         uint64_t csa_addr;
8450         int cnt;
8451
8452         cnt = (sizeof(ce_payload) >> 2) + 4 - 2;
8453         csa_addr = amdgpu_csa_vaddr(ring->adev);
8454
8455         amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, cnt));
8456         amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(2) |
8457                                  WRITE_DATA_DST_SEL(8) |
8458                                  WR_CONFIRM) |
8459                                  WRITE_DATA_CACHE_POLICY(0));
8460         amdgpu_ring_write(ring, lower_32_bits(csa_addr +
8461                               offsetof(struct v10_gfx_meta_data, ce_payload)));
8462         amdgpu_ring_write(ring, upper_32_bits(csa_addr +
8463                               offsetof(struct v10_gfx_meta_data, ce_payload)));
8464
8465         if (resume)
8466                 amdgpu_ring_write_multiple(ring, adev->virt.csa_cpu_addr +
8467                                            offsetof(struct v10_gfx_meta_data,
8468                                                     ce_payload),
8469                                            sizeof(ce_payload) >> 2);
8470         else
8471                 amdgpu_ring_write_multiple(ring, (void *)&ce_payload,
8472                                            sizeof(ce_payload) >> 2);
8473 }
8474
8475 static void gfx_v10_0_ring_emit_de_meta(struct amdgpu_ring *ring, bool resume)
8476 {
8477         struct amdgpu_device *adev = ring->adev;
8478         struct v10_de_ib_state de_payload = {0};
8479         uint64_t csa_addr, gds_addr;
8480         int cnt;
8481
8482         csa_addr = amdgpu_csa_vaddr(ring->adev);
8483         gds_addr = ALIGN(csa_addr + AMDGPU_CSA_SIZE - adev->gds.gds_size,
8484                          PAGE_SIZE);
8485         de_payload.gds_backup_addrlo = lower_32_bits(gds_addr);
8486         de_payload.gds_backup_addrhi = upper_32_bits(gds_addr);
8487
8488         cnt = (sizeof(de_payload) >> 2) + 4 - 2;
8489         amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, cnt));
8490         amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(1) |
8491                                  WRITE_DATA_DST_SEL(8) |
8492                                  WR_CONFIRM) |
8493                                  WRITE_DATA_CACHE_POLICY(0));
8494         amdgpu_ring_write(ring, lower_32_bits(csa_addr +
8495                               offsetof(struct v10_gfx_meta_data, de_payload)));
8496         amdgpu_ring_write(ring, upper_32_bits(csa_addr +
8497                               offsetof(struct v10_gfx_meta_data, de_payload)));
8498
8499         if (resume)
8500                 amdgpu_ring_write_multiple(ring, adev->virt.csa_cpu_addr +
8501                                            offsetof(struct v10_gfx_meta_data,
8502                                                     de_payload),
8503                                            sizeof(de_payload) >> 2);
8504         else
8505                 amdgpu_ring_write_multiple(ring, (void *)&de_payload,
8506                                            sizeof(de_payload) >> 2);
8507 }
8508
8509 static void gfx_v10_0_ring_emit_frame_cntl(struct amdgpu_ring *ring, bool start,
8510                                     bool secure)
8511 {
8512         uint32_t v = secure ? FRAME_TMZ : 0;
8513
8514         amdgpu_ring_write(ring, PACKET3(PACKET3_FRAME_CONTROL, 0));
8515         amdgpu_ring_write(ring, v | FRAME_CMD(start ? 0 : 1));
8516 }
8517
8518 static void gfx_v10_0_ring_emit_rreg(struct amdgpu_ring *ring, uint32_t reg,
8519                                      uint32_t reg_val_offs)
8520 {
8521         struct amdgpu_device *adev = ring->adev;
8522
8523         amdgpu_ring_write(ring, PACKET3(PACKET3_COPY_DATA, 4));
8524         amdgpu_ring_write(ring, 0 |     /* src: register*/
8525                                 (5 << 8) |      /* dst: memory */
8526                                 (1 << 20));     /* write confirm */
8527         amdgpu_ring_write(ring, reg);
8528         amdgpu_ring_write(ring, 0);
8529         amdgpu_ring_write(ring, lower_32_bits(adev->wb.gpu_addr +
8530                                 reg_val_offs * 4));
8531         amdgpu_ring_write(ring, upper_32_bits(adev->wb.gpu_addr +
8532                                 reg_val_offs * 4));
8533 }
8534
8535 static void gfx_v10_0_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg,
8536                                    uint32_t val)
8537 {
8538         uint32_t cmd = 0;
8539
8540         switch (ring->funcs->type) {
8541         case AMDGPU_RING_TYPE_GFX:
8542                 cmd = WRITE_DATA_ENGINE_SEL(1) | WR_CONFIRM;
8543                 break;
8544         case AMDGPU_RING_TYPE_KIQ:
8545                 cmd = (1 << 16); /* no inc addr */
8546                 break;
8547         default:
8548                 cmd = WR_CONFIRM;
8549                 break;
8550         }
8551         amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
8552         amdgpu_ring_write(ring, cmd);
8553         amdgpu_ring_write(ring, reg);
8554         amdgpu_ring_write(ring, 0);
8555         amdgpu_ring_write(ring, val);
8556 }
8557
8558 static void gfx_v10_0_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg,
8559                                         uint32_t val, uint32_t mask)
8560 {
8561         gfx_v10_0_wait_reg_mem(ring, 0, 0, 0, reg, 0, val, mask, 0x20);
8562 }
8563
8564 static void gfx_v10_0_ring_emit_reg_write_reg_wait(struct amdgpu_ring *ring,
8565                                                    uint32_t reg0, uint32_t reg1,
8566                                                    uint32_t ref, uint32_t mask)
8567 {
8568         int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX);
8569         struct amdgpu_device *adev = ring->adev;
8570         bool fw_version_ok = false;
8571
8572         fw_version_ok = adev->gfx.cp_fw_write_wait;
8573
8574         if (fw_version_ok)
8575                 gfx_v10_0_wait_reg_mem(ring, usepfp, 0, 1, reg0, reg1,
8576                                        ref, mask, 0x20);
8577         else
8578                 amdgpu_ring_emit_reg_write_reg_wait_helper(ring, reg0, reg1,
8579                                                            ref, mask);
8580 }
8581
8582 static void gfx_v10_0_ring_soft_recovery(struct amdgpu_ring *ring,
8583                                          unsigned vmid)
8584 {
8585         struct amdgpu_device *adev = ring->adev;
8586         uint32_t value = 0;
8587
8588         value = REG_SET_FIELD(value, SQ_CMD, CMD, 0x03);
8589         value = REG_SET_FIELD(value, SQ_CMD, MODE, 0x01);
8590         value = REG_SET_FIELD(value, SQ_CMD, CHECK_VMID, 1);
8591         value = REG_SET_FIELD(value, SQ_CMD, VM_ID, vmid);
8592         WREG32_SOC15(GC, 0, mmSQ_CMD, value);
8593 }
8594
8595 static void
8596 gfx_v10_0_set_gfx_eop_interrupt_state(struct amdgpu_device *adev,
8597                                       uint32_t me, uint32_t pipe,
8598                                       enum amdgpu_interrupt_state state)
8599 {
8600         uint32_t cp_int_cntl, cp_int_cntl_reg;
8601
8602         if (!me) {
8603                 switch (pipe) {
8604                 case 0:
8605                         cp_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_INT_CNTL_RING0);
8606                         break;
8607                 case 1:
8608                         cp_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_INT_CNTL_RING1);
8609                         break;
8610                 default:
8611                         DRM_DEBUG("invalid pipe %d\n", pipe);
8612                         return;
8613                 }
8614         } else {
8615                 DRM_DEBUG("invalid me %d\n", me);
8616                 return;
8617         }
8618
8619         switch (state) {
8620         case AMDGPU_IRQ_STATE_DISABLE:
8621                 cp_int_cntl = RREG32(cp_int_cntl_reg);
8622                 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0,
8623                                             TIME_STAMP_INT_ENABLE, 0);
8624                 WREG32(cp_int_cntl_reg, cp_int_cntl);
8625                 break;
8626         case AMDGPU_IRQ_STATE_ENABLE:
8627                 cp_int_cntl = RREG32(cp_int_cntl_reg);
8628                 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0,
8629                                             TIME_STAMP_INT_ENABLE, 1);
8630                 WREG32(cp_int_cntl_reg, cp_int_cntl);
8631                 break;
8632         default:
8633                 break;
8634         }
8635 }
8636
8637 static void gfx_v10_0_set_compute_eop_interrupt_state(struct amdgpu_device *adev,
8638                                                      int me, int pipe,
8639                                                      enum amdgpu_interrupt_state state)
8640 {
8641         u32 mec_int_cntl, mec_int_cntl_reg;
8642
8643         /*
8644          * amdgpu controls only the first MEC. That's why this function only
8645          * handles the setting of interrupts for this specific MEC. All other
8646          * pipes' interrupts are set by amdkfd.
8647          */
8648
8649         if (me == 1) {
8650                 switch (pipe) {
8651                 case 0:
8652                         mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE0_INT_CNTL);
8653                         break;
8654                 case 1:
8655                         mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE1_INT_CNTL);
8656                         break;
8657                 case 2:
8658                         mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE2_INT_CNTL);
8659                         break;
8660                 case 3:
8661                         mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE3_INT_CNTL);
8662                         break;
8663                 default:
8664                         DRM_DEBUG("invalid pipe %d\n", pipe);
8665                         return;
8666                 }
8667         } else {
8668                 DRM_DEBUG("invalid me %d\n", me);
8669                 return;
8670         }
8671
8672         switch (state) {
8673         case AMDGPU_IRQ_STATE_DISABLE:
8674                 mec_int_cntl = RREG32(mec_int_cntl_reg);
8675                 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL,
8676                                              TIME_STAMP_INT_ENABLE, 0);
8677                 WREG32(mec_int_cntl_reg, mec_int_cntl);
8678                 break;
8679         case AMDGPU_IRQ_STATE_ENABLE:
8680                 mec_int_cntl = RREG32(mec_int_cntl_reg);
8681                 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL,
8682                                              TIME_STAMP_INT_ENABLE, 1);
8683                 WREG32(mec_int_cntl_reg, mec_int_cntl);
8684                 break;
8685         default:
8686                 break;
8687         }
8688 }
8689
8690 static int gfx_v10_0_set_eop_interrupt_state(struct amdgpu_device *adev,
8691                                             struct amdgpu_irq_src *src,
8692                                             unsigned type,
8693                                             enum amdgpu_interrupt_state state)
8694 {
8695         switch (type) {
8696         case AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP:
8697                 gfx_v10_0_set_gfx_eop_interrupt_state(adev, 0, 0, state);
8698                 break;
8699         case AMDGPU_CP_IRQ_GFX_ME0_PIPE1_EOP:
8700                 gfx_v10_0_set_gfx_eop_interrupt_state(adev, 0, 1, state);
8701                 break;
8702         case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP:
8703                 gfx_v10_0_set_compute_eop_interrupt_state(adev, 1, 0, state);
8704                 break;
8705         case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP:
8706                 gfx_v10_0_set_compute_eop_interrupt_state(adev, 1, 1, state);
8707                 break;
8708         case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP:
8709                 gfx_v10_0_set_compute_eop_interrupt_state(adev, 1, 2, state);
8710                 break;
8711         case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP:
8712                 gfx_v10_0_set_compute_eop_interrupt_state(adev, 1, 3, state);
8713                 break;
8714         case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE0_EOP:
8715                 gfx_v10_0_set_compute_eop_interrupt_state(adev, 2, 0, state);
8716                 break;
8717         case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE1_EOP:
8718                 gfx_v10_0_set_compute_eop_interrupt_state(adev, 2, 1, state);
8719                 break;
8720         case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE2_EOP:
8721                 gfx_v10_0_set_compute_eop_interrupt_state(adev, 2, 2, state);
8722                 break;
8723         case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE3_EOP:
8724                 gfx_v10_0_set_compute_eop_interrupt_state(adev, 2, 3, state);
8725                 break;
8726         default:
8727                 break;
8728         }
8729         return 0;
8730 }
8731
8732 static int gfx_v10_0_eop_irq(struct amdgpu_device *adev,
8733                              struct amdgpu_irq_src *source,
8734                              struct amdgpu_iv_entry *entry)
8735 {
8736         int i;
8737         u8 me_id, pipe_id, queue_id;
8738         struct amdgpu_ring *ring;
8739
8740         DRM_DEBUG("IH: CP EOP\n");
8741         me_id = (entry->ring_id & 0x0c) >> 2;
8742         pipe_id = (entry->ring_id & 0x03) >> 0;
8743         queue_id = (entry->ring_id & 0x70) >> 4;
8744
8745         switch (me_id) {
8746         case 0:
8747                 if (pipe_id == 0)
8748                         amdgpu_fence_process(&adev->gfx.gfx_ring[0]);
8749                 else
8750                         amdgpu_fence_process(&adev->gfx.gfx_ring[1]);
8751                 break;
8752         case 1:
8753         case 2:
8754                 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
8755                         ring = &adev->gfx.compute_ring[i];
8756                         /* Per-queue interrupt is supported for MEC starting from VI.
8757                           * The interrupt can only be enabled/disabled per pipe instead of per queue.
8758                           */
8759                         if ((ring->me == me_id) && (ring->pipe == pipe_id) && (ring->queue == queue_id))
8760                                 amdgpu_fence_process(ring);
8761                 }
8762                 break;
8763         }
8764         return 0;
8765 }
8766
8767 static int gfx_v10_0_set_priv_reg_fault_state(struct amdgpu_device *adev,
8768                                               struct amdgpu_irq_src *source,
8769                                               unsigned type,
8770                                               enum amdgpu_interrupt_state state)
8771 {
8772         switch (state) {
8773         case AMDGPU_IRQ_STATE_DISABLE:
8774         case AMDGPU_IRQ_STATE_ENABLE:
8775                 WREG32_FIELD15(GC, 0, CP_INT_CNTL_RING0,
8776                                PRIV_REG_INT_ENABLE,
8777                                state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0);
8778                 break;
8779         default:
8780                 break;
8781         }
8782
8783         return 0;
8784 }
8785
8786 static int gfx_v10_0_set_priv_inst_fault_state(struct amdgpu_device *adev,
8787                                                struct amdgpu_irq_src *source,
8788                                                unsigned type,
8789                                                enum amdgpu_interrupt_state state)
8790 {
8791         switch (state) {
8792         case AMDGPU_IRQ_STATE_DISABLE:
8793         case AMDGPU_IRQ_STATE_ENABLE:
8794                 WREG32_FIELD15(GC, 0, CP_INT_CNTL_RING0,
8795                                PRIV_INSTR_INT_ENABLE,
8796                                state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0);
8797                 break;
8798         default:
8799                 break;
8800         }
8801
8802         return 0;
8803 }
8804
8805 static void gfx_v10_0_handle_priv_fault(struct amdgpu_device *adev,
8806                                         struct amdgpu_iv_entry *entry)
8807 {
8808         u8 me_id, pipe_id, queue_id;
8809         struct amdgpu_ring *ring;
8810         int i;
8811
8812         me_id = (entry->ring_id & 0x0c) >> 2;
8813         pipe_id = (entry->ring_id & 0x03) >> 0;
8814         queue_id = (entry->ring_id & 0x70) >> 4;
8815
8816         switch (me_id) {
8817         case 0:
8818                 for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
8819                         ring = &adev->gfx.gfx_ring[i];
8820                         /* we only enabled 1 gfx queue per pipe for now */
8821                         if (ring->me == me_id && ring->pipe == pipe_id)
8822                                 drm_sched_fault(&ring->sched);
8823                 }
8824                 break;
8825         case 1:
8826         case 2:
8827                 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
8828                         ring = &adev->gfx.compute_ring[i];
8829                         if (ring->me == me_id && ring->pipe == pipe_id &&
8830                             ring->queue == queue_id)
8831                                 drm_sched_fault(&ring->sched);
8832                 }
8833                 break;
8834         default:
8835                 BUG();
8836         }
8837 }
8838
8839 static int gfx_v10_0_priv_reg_irq(struct amdgpu_device *adev,
8840                                   struct amdgpu_irq_src *source,
8841                                   struct amdgpu_iv_entry *entry)
8842 {
8843         DRM_ERROR("Illegal register access in command stream\n");
8844         gfx_v10_0_handle_priv_fault(adev, entry);
8845         return 0;
8846 }
8847
8848 static int gfx_v10_0_priv_inst_irq(struct amdgpu_device *adev,
8849                                    struct amdgpu_irq_src *source,
8850                                    struct amdgpu_iv_entry *entry)
8851 {
8852         DRM_ERROR("Illegal instruction in command stream\n");
8853         gfx_v10_0_handle_priv_fault(adev, entry);
8854         return 0;
8855 }
8856
8857 static int gfx_v10_0_kiq_set_interrupt_state(struct amdgpu_device *adev,
8858                                              struct amdgpu_irq_src *src,
8859                                              unsigned int type,
8860                                              enum amdgpu_interrupt_state state)
8861 {
8862         uint32_t tmp, target;
8863         struct amdgpu_ring *ring = &(adev->gfx.kiq.ring);
8864
8865         if (ring->me == 1)
8866                 target = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE0_INT_CNTL);
8867         else
8868                 target = SOC15_REG_OFFSET(GC, 0, mmCP_ME2_PIPE0_INT_CNTL);
8869         target += ring->pipe;
8870
8871         switch (type) {
8872         case AMDGPU_CP_KIQ_IRQ_DRIVER0:
8873                 if (state == AMDGPU_IRQ_STATE_DISABLE) {
8874                         tmp = RREG32_SOC15(GC, 0, mmCPC_INT_CNTL);
8875                         tmp = REG_SET_FIELD(tmp, CPC_INT_CNTL,
8876                                             GENERIC2_INT_ENABLE, 0);
8877                         WREG32_SOC15(GC, 0, mmCPC_INT_CNTL, tmp);
8878
8879                         tmp = RREG32(target);
8880                         tmp = REG_SET_FIELD(tmp, CP_ME2_PIPE0_INT_CNTL,
8881                                             GENERIC2_INT_ENABLE, 0);
8882                         WREG32(target, tmp);
8883                 } else {
8884                         tmp = RREG32_SOC15(GC, 0, mmCPC_INT_CNTL);
8885                         tmp = REG_SET_FIELD(tmp, CPC_INT_CNTL,
8886                                             GENERIC2_INT_ENABLE, 1);
8887                         WREG32_SOC15(GC, 0, mmCPC_INT_CNTL, tmp);
8888
8889                         tmp = RREG32(target);
8890                         tmp = REG_SET_FIELD(tmp, CP_ME2_PIPE0_INT_CNTL,
8891                                             GENERIC2_INT_ENABLE, 1);
8892                         WREG32(target, tmp);
8893                 }
8894                 break;
8895         default:
8896                 BUG(); /* kiq only support GENERIC2_INT now */
8897                 break;
8898         }
8899         return 0;
8900 }
8901
8902 static int gfx_v10_0_kiq_irq(struct amdgpu_device *adev,
8903                              struct amdgpu_irq_src *source,
8904                              struct amdgpu_iv_entry *entry)
8905 {
8906         u8 me_id, pipe_id, queue_id;
8907         struct amdgpu_ring *ring = &(adev->gfx.kiq.ring);
8908
8909         me_id = (entry->ring_id & 0x0c) >> 2;
8910         pipe_id = (entry->ring_id & 0x03) >> 0;
8911         queue_id = (entry->ring_id & 0x70) >> 4;
8912         DRM_DEBUG("IH: CPC GENERIC2_INT, me:%d, pipe:%d, queue:%d\n",
8913                    me_id, pipe_id, queue_id);
8914
8915         amdgpu_fence_process(ring);
8916         return 0;
8917 }
8918
8919 static void gfx_v10_0_emit_mem_sync(struct amdgpu_ring *ring)
8920 {
8921         const unsigned int gcr_cntl =
8922                         PACKET3_ACQUIRE_MEM_GCR_CNTL_GL2_INV(1) |
8923                         PACKET3_ACQUIRE_MEM_GCR_CNTL_GL2_WB(1) |
8924                         PACKET3_ACQUIRE_MEM_GCR_CNTL_GLM_INV(1) |
8925                         PACKET3_ACQUIRE_MEM_GCR_CNTL_GLM_WB(1) |
8926                         PACKET3_ACQUIRE_MEM_GCR_CNTL_GL1_INV(1) |
8927                         PACKET3_ACQUIRE_MEM_GCR_CNTL_GLV_INV(1) |
8928                         PACKET3_ACQUIRE_MEM_GCR_CNTL_GLK_INV(1) |
8929                         PACKET3_ACQUIRE_MEM_GCR_CNTL_GLI_INV(1);
8930
8931         /* ACQUIRE_MEM - make one or more surfaces valid for use by the subsequent operations */
8932         amdgpu_ring_write(ring, PACKET3(PACKET3_ACQUIRE_MEM, 6));
8933         amdgpu_ring_write(ring, 0); /* CP_COHER_CNTL */
8934         amdgpu_ring_write(ring, 0xffffffff);  /* CP_COHER_SIZE */
8935         amdgpu_ring_write(ring, 0xffffff);  /* CP_COHER_SIZE_HI */
8936         amdgpu_ring_write(ring, 0); /* CP_COHER_BASE */
8937         amdgpu_ring_write(ring, 0);  /* CP_COHER_BASE_HI */
8938         amdgpu_ring_write(ring, 0x0000000A); /* POLL_INTERVAL */
8939         amdgpu_ring_write(ring, gcr_cntl); /* GCR_CNTL */
8940 }
8941
8942 static const struct amd_ip_funcs gfx_v10_0_ip_funcs = {
8943         .name = "gfx_v10_0",
8944         .early_init = gfx_v10_0_early_init,
8945         .late_init = gfx_v10_0_late_init,
8946         .sw_init = gfx_v10_0_sw_init,
8947         .sw_fini = gfx_v10_0_sw_fini,
8948         .hw_init = gfx_v10_0_hw_init,
8949         .hw_fini = gfx_v10_0_hw_fini,
8950         .suspend = gfx_v10_0_suspend,
8951         .resume = gfx_v10_0_resume,
8952         .is_idle = gfx_v10_0_is_idle,
8953         .wait_for_idle = gfx_v10_0_wait_for_idle,
8954         .soft_reset = gfx_v10_0_soft_reset,
8955         .set_clockgating_state = gfx_v10_0_set_clockgating_state,
8956         .set_powergating_state = gfx_v10_0_set_powergating_state,
8957         .get_clockgating_state = gfx_v10_0_get_clockgating_state,
8958 };
8959
8960 static const struct amdgpu_ring_funcs gfx_v10_0_ring_funcs_gfx = {
8961         .type = AMDGPU_RING_TYPE_GFX,
8962         .align_mask = 0xff,
8963         .nop = PACKET3(PACKET3_NOP, 0x3FFF),
8964         .support_64bit_ptrs = true,
8965         .vmhub = AMDGPU_GFXHUB_0,
8966         .get_rptr = gfx_v10_0_ring_get_rptr_gfx,
8967         .get_wptr = gfx_v10_0_ring_get_wptr_gfx,
8968         .set_wptr = gfx_v10_0_ring_set_wptr_gfx,
8969         .emit_frame_size = /* totally 242 maximum if 16 IBs */
8970                 5 + /* COND_EXEC */
8971                 7 + /* PIPELINE_SYNC */
8972                 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 +
8973                 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 +
8974                 2 + /* VM_FLUSH */
8975                 8 + /* FENCE for VM_FLUSH */
8976                 20 + /* GDS switch */
8977                 4 + /* double SWITCH_BUFFER,
8978                      * the first COND_EXEC jump to the place
8979                      * just prior to this double SWITCH_BUFFER
8980                      */
8981                 5 + /* COND_EXEC */
8982                 7 + /* HDP_flush */
8983                 4 + /* VGT_flush */
8984                 14 + /* CE_META */
8985                 31 + /* DE_META */
8986                 3 + /* CNTX_CTRL */
8987                 5 + /* HDP_INVL */
8988                 8 + 8 + /* FENCE x2 */
8989                 2 + /* SWITCH_BUFFER */
8990                 8, /* gfx_v10_0_emit_mem_sync */
8991         .emit_ib_size = 4, /* gfx_v10_0_ring_emit_ib_gfx */
8992         .emit_ib = gfx_v10_0_ring_emit_ib_gfx,
8993         .emit_fence = gfx_v10_0_ring_emit_fence,
8994         .emit_pipeline_sync = gfx_v10_0_ring_emit_pipeline_sync,
8995         .emit_vm_flush = gfx_v10_0_ring_emit_vm_flush,
8996         .emit_gds_switch = gfx_v10_0_ring_emit_gds_switch,
8997         .emit_hdp_flush = gfx_v10_0_ring_emit_hdp_flush,
8998         .test_ring = gfx_v10_0_ring_test_ring,
8999         .test_ib = gfx_v10_0_ring_test_ib,
9000         .insert_nop = amdgpu_ring_insert_nop,
9001         .pad_ib = amdgpu_ring_generic_pad_ib,
9002         .emit_switch_buffer = gfx_v10_0_ring_emit_sb,
9003         .emit_cntxcntl = gfx_v10_0_ring_emit_cntxcntl,
9004         .init_cond_exec = gfx_v10_0_ring_emit_init_cond_exec,
9005         .patch_cond_exec = gfx_v10_0_ring_emit_patch_cond_exec,
9006         .preempt_ib = gfx_v10_0_ring_preempt_ib,
9007         .emit_frame_cntl = gfx_v10_0_ring_emit_frame_cntl,
9008         .emit_wreg = gfx_v10_0_ring_emit_wreg,
9009         .emit_reg_wait = gfx_v10_0_ring_emit_reg_wait,
9010         .emit_reg_write_reg_wait = gfx_v10_0_ring_emit_reg_write_reg_wait,
9011         .soft_recovery = gfx_v10_0_ring_soft_recovery,
9012         .emit_mem_sync = gfx_v10_0_emit_mem_sync,
9013 };
9014
9015 static const struct amdgpu_ring_funcs gfx_v10_0_ring_funcs_compute = {
9016         .type = AMDGPU_RING_TYPE_COMPUTE,
9017         .align_mask = 0xff,
9018         .nop = PACKET3(PACKET3_NOP, 0x3FFF),
9019         .support_64bit_ptrs = true,
9020         .vmhub = AMDGPU_GFXHUB_0,
9021         .get_rptr = gfx_v10_0_ring_get_rptr_compute,
9022         .get_wptr = gfx_v10_0_ring_get_wptr_compute,
9023         .set_wptr = gfx_v10_0_ring_set_wptr_compute,
9024         .emit_frame_size =
9025                 20 + /* gfx_v10_0_ring_emit_gds_switch */
9026                 7 + /* gfx_v10_0_ring_emit_hdp_flush */
9027                 5 + /* hdp invalidate */
9028                 7 + /* gfx_v10_0_ring_emit_pipeline_sync */
9029                 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 +
9030                 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 +
9031                 2 + /* gfx_v10_0_ring_emit_vm_flush */
9032                 8 + 8 + 8 + /* gfx_v10_0_ring_emit_fence x3 for user fence, vm fence */
9033                 8, /* gfx_v10_0_emit_mem_sync */
9034         .emit_ib_size = 7, /* gfx_v10_0_ring_emit_ib_compute */
9035         .emit_ib = gfx_v10_0_ring_emit_ib_compute,
9036         .emit_fence = gfx_v10_0_ring_emit_fence,
9037         .emit_pipeline_sync = gfx_v10_0_ring_emit_pipeline_sync,
9038         .emit_vm_flush = gfx_v10_0_ring_emit_vm_flush,
9039         .emit_gds_switch = gfx_v10_0_ring_emit_gds_switch,
9040         .emit_hdp_flush = gfx_v10_0_ring_emit_hdp_flush,
9041         .test_ring = gfx_v10_0_ring_test_ring,
9042         .test_ib = gfx_v10_0_ring_test_ib,
9043         .insert_nop = amdgpu_ring_insert_nop,
9044         .pad_ib = amdgpu_ring_generic_pad_ib,
9045         .emit_wreg = gfx_v10_0_ring_emit_wreg,
9046         .emit_reg_wait = gfx_v10_0_ring_emit_reg_wait,
9047         .emit_reg_write_reg_wait = gfx_v10_0_ring_emit_reg_write_reg_wait,
9048         .emit_mem_sync = gfx_v10_0_emit_mem_sync,
9049 };
9050
9051 static const struct amdgpu_ring_funcs gfx_v10_0_ring_funcs_kiq = {
9052         .type = AMDGPU_RING_TYPE_KIQ,
9053         .align_mask = 0xff,
9054         .nop = PACKET3(PACKET3_NOP, 0x3FFF),
9055         .support_64bit_ptrs = true,
9056         .vmhub = AMDGPU_GFXHUB_0,
9057         .get_rptr = gfx_v10_0_ring_get_rptr_compute,
9058         .get_wptr = gfx_v10_0_ring_get_wptr_compute,
9059         .set_wptr = gfx_v10_0_ring_set_wptr_compute,
9060         .emit_frame_size =
9061                 20 + /* gfx_v10_0_ring_emit_gds_switch */
9062                 7 + /* gfx_v10_0_ring_emit_hdp_flush */
9063                 5 + /*hdp invalidate */
9064                 7 + /* gfx_v10_0_ring_emit_pipeline_sync */
9065                 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 +
9066                 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 +
9067                 2 + /* gfx_v10_0_ring_emit_vm_flush */
9068                 8 + 8 + 8, /* gfx_v10_0_ring_emit_fence_kiq x3 for user fence, vm fence */
9069         .emit_ib_size = 7, /* gfx_v10_0_ring_emit_ib_compute */
9070         .emit_ib = gfx_v10_0_ring_emit_ib_compute,
9071         .emit_fence = gfx_v10_0_ring_emit_fence_kiq,
9072         .test_ring = gfx_v10_0_ring_test_ring,
9073         .test_ib = gfx_v10_0_ring_test_ib,
9074         .insert_nop = amdgpu_ring_insert_nop,
9075         .pad_ib = amdgpu_ring_generic_pad_ib,
9076         .emit_rreg = gfx_v10_0_ring_emit_rreg,
9077         .emit_wreg = gfx_v10_0_ring_emit_wreg,
9078         .emit_reg_wait = gfx_v10_0_ring_emit_reg_wait,
9079         .emit_reg_write_reg_wait = gfx_v10_0_ring_emit_reg_write_reg_wait,
9080 };
9081
9082 static void gfx_v10_0_set_ring_funcs(struct amdgpu_device *adev)
9083 {
9084         int i;
9085
9086         adev->gfx.kiq.ring.funcs = &gfx_v10_0_ring_funcs_kiq;
9087
9088         for (i = 0; i < adev->gfx.num_gfx_rings; i++)
9089                 adev->gfx.gfx_ring[i].funcs = &gfx_v10_0_ring_funcs_gfx;
9090
9091         for (i = 0; i < adev->gfx.num_compute_rings; i++)
9092                 adev->gfx.compute_ring[i].funcs = &gfx_v10_0_ring_funcs_compute;
9093 }
9094
9095 static const struct amdgpu_irq_src_funcs gfx_v10_0_eop_irq_funcs = {
9096         .set = gfx_v10_0_set_eop_interrupt_state,
9097         .process = gfx_v10_0_eop_irq,
9098 };
9099
9100 static const struct amdgpu_irq_src_funcs gfx_v10_0_priv_reg_irq_funcs = {
9101         .set = gfx_v10_0_set_priv_reg_fault_state,
9102         .process = gfx_v10_0_priv_reg_irq,
9103 };
9104
9105 static const struct amdgpu_irq_src_funcs gfx_v10_0_priv_inst_irq_funcs = {
9106         .set = gfx_v10_0_set_priv_inst_fault_state,
9107         .process = gfx_v10_0_priv_inst_irq,
9108 };
9109
9110 static const struct amdgpu_irq_src_funcs gfx_v10_0_kiq_irq_funcs = {
9111         .set = gfx_v10_0_kiq_set_interrupt_state,
9112         .process = gfx_v10_0_kiq_irq,
9113 };
9114
9115 static void gfx_v10_0_set_irq_funcs(struct amdgpu_device *adev)
9116 {
9117         adev->gfx.eop_irq.num_types = AMDGPU_CP_IRQ_LAST;
9118         adev->gfx.eop_irq.funcs = &gfx_v10_0_eop_irq_funcs;
9119
9120         adev->gfx.kiq.irq.num_types = AMDGPU_CP_KIQ_IRQ_LAST;
9121         adev->gfx.kiq.irq.funcs = &gfx_v10_0_kiq_irq_funcs;
9122
9123         adev->gfx.priv_reg_irq.num_types = 1;
9124         adev->gfx.priv_reg_irq.funcs = &gfx_v10_0_priv_reg_irq_funcs;
9125
9126         adev->gfx.priv_inst_irq.num_types = 1;
9127         adev->gfx.priv_inst_irq.funcs = &gfx_v10_0_priv_inst_irq_funcs;
9128 }
9129
9130 static void gfx_v10_0_set_rlc_funcs(struct amdgpu_device *adev)
9131 {
9132         switch (adev->asic_type) {
9133         case CHIP_NAVI10:
9134         case CHIP_NAVI14:
9135         case CHIP_SIENNA_CICHLID:
9136         case CHIP_NAVY_FLOUNDER:
9137         case CHIP_VANGOGH:
9138         case CHIP_DIMGREY_CAVEFISH:
9139                 adev->gfx.rlc.funcs = &gfx_v10_0_rlc_funcs;
9140                 break;
9141         case CHIP_NAVI12:
9142                 adev->gfx.rlc.funcs = &gfx_v10_0_rlc_funcs_sriov;
9143                 break;
9144         default:
9145                 break;
9146         }
9147 }
9148
9149 static void gfx_v10_0_set_gds_init(struct amdgpu_device *adev)
9150 {
9151         unsigned total_cu = adev->gfx.config.max_cu_per_sh *
9152                             adev->gfx.config.max_sh_per_se *
9153                             adev->gfx.config.max_shader_engines;
9154
9155         adev->gds.gds_size = 0x10000;
9156         adev->gds.gds_compute_max_wave_id = total_cu * 32 - 1;
9157         adev->gds.gws_size = 64;
9158         adev->gds.oa_size = 16;
9159 }
9160
9161 static void gfx_v10_0_set_user_wgp_inactive_bitmap_per_sh(struct amdgpu_device *adev,
9162                                                           u32 bitmap)
9163 {
9164         u32 data;
9165
9166         if (!bitmap)
9167                 return;
9168
9169         data = bitmap << GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_WGPS__SHIFT;
9170         data &= GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_WGPS_MASK;
9171
9172         WREG32_SOC15(GC, 0, mmGC_USER_SHADER_ARRAY_CONFIG, data);
9173 }
9174
9175 static u32 gfx_v10_0_get_wgp_active_bitmap_per_sh(struct amdgpu_device *adev)
9176 {
9177         u32 data, wgp_bitmask;
9178         data = RREG32_SOC15(GC, 0, mmCC_GC_SHADER_ARRAY_CONFIG);
9179         data |= RREG32_SOC15(GC, 0, mmGC_USER_SHADER_ARRAY_CONFIG);
9180
9181         data &= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_WGPS_MASK;
9182         data >>= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_WGPS__SHIFT;
9183
9184         wgp_bitmask =
9185                 amdgpu_gfx_create_bitmask(adev->gfx.config.max_cu_per_sh >> 1);
9186
9187         return (~data) & wgp_bitmask;
9188 }
9189
9190 static u32 gfx_v10_0_get_cu_active_bitmap_per_sh(struct amdgpu_device *adev)
9191 {
9192         u32 wgp_idx, wgp_active_bitmap;
9193         u32 cu_bitmap_per_wgp, cu_active_bitmap;
9194
9195         wgp_active_bitmap = gfx_v10_0_get_wgp_active_bitmap_per_sh(adev);
9196         cu_active_bitmap = 0;
9197
9198         for (wgp_idx = 0; wgp_idx < 16; wgp_idx++) {
9199                 /* if there is one WGP enabled, it means 2 CUs will be enabled */
9200                 cu_bitmap_per_wgp = 3 << (2 * wgp_idx);
9201                 if (wgp_active_bitmap & (1 << wgp_idx))
9202                         cu_active_bitmap |= cu_bitmap_per_wgp;
9203         }
9204
9205         return cu_active_bitmap;
9206 }
9207
9208 static int gfx_v10_0_get_cu_info(struct amdgpu_device *adev,
9209                                  struct amdgpu_cu_info *cu_info)
9210 {
9211         int i, j, k, counter, active_cu_number = 0;
9212         u32 mask, bitmap, ao_bitmap, ao_cu_mask = 0;
9213         unsigned disable_masks[4 * 2];
9214
9215         if (!adev || !cu_info)
9216                 return -EINVAL;
9217
9218         amdgpu_gfx_parse_disable_cu(disable_masks, 4, 2);
9219
9220         mutex_lock(&adev->grbm_idx_mutex);
9221         for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
9222                 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
9223                         bitmap = i * adev->gfx.config.max_sh_per_se + j;
9224                         if ((adev->asic_type == CHIP_SIENNA_CICHLID) &&
9225                             ((gfx_v10_3_get_disabled_sa(adev) >> bitmap) & 1))
9226                                 continue;
9227                         mask = 1;
9228                         ao_bitmap = 0;
9229                         counter = 0;
9230                         gfx_v10_0_select_se_sh(adev, i, j, 0xffffffff);
9231                         if (i < 4 && j < 2)
9232                                 gfx_v10_0_set_user_wgp_inactive_bitmap_per_sh(
9233                                         adev, disable_masks[i * 2 + j]);
9234                         bitmap = gfx_v10_0_get_cu_active_bitmap_per_sh(adev);
9235                         cu_info->bitmap[i][j] = bitmap;
9236
9237                         for (k = 0; k < adev->gfx.config.max_cu_per_sh; k++) {
9238                                 if (bitmap & mask) {
9239                                         if (counter < adev->gfx.config.max_cu_per_sh)
9240                                                 ao_bitmap |= mask;
9241                                         counter++;
9242                                 }
9243                                 mask <<= 1;
9244                         }
9245                         active_cu_number += counter;
9246                         if (i < 2 && j < 2)
9247                                 ao_cu_mask |= (ao_bitmap << (i * 16 + j * 8));
9248                         cu_info->ao_cu_bitmap[i][j] = ao_bitmap;
9249                 }
9250         }
9251         gfx_v10_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
9252         mutex_unlock(&adev->grbm_idx_mutex);
9253
9254         cu_info->number = active_cu_number;
9255         cu_info->ao_cu_mask = ao_cu_mask;
9256         cu_info->simd_per_cu = NUM_SIMD_PER_CU;
9257
9258         return 0;
9259 }
9260
9261 static u32 gfx_v10_3_get_disabled_sa(struct amdgpu_device *adev)
9262 {
9263         uint32_t efuse_setting, vbios_setting, disabled_sa, max_sa_mask;
9264
9265         efuse_setting = RREG32_SOC15(GC, 0, mmCC_GC_SA_UNIT_DISABLE);
9266         efuse_setting &= CC_GC_SA_UNIT_DISABLE__SA_DISABLE_MASK;
9267         efuse_setting >>= CC_GC_SA_UNIT_DISABLE__SA_DISABLE__SHIFT;
9268
9269         vbios_setting = RREG32_SOC15(GC, 0, mmGC_USER_SA_UNIT_DISABLE);
9270         vbios_setting &= GC_USER_SA_UNIT_DISABLE__SA_DISABLE_MASK;
9271         vbios_setting >>= GC_USER_SA_UNIT_DISABLE__SA_DISABLE__SHIFT;
9272
9273         max_sa_mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_sh_per_se *
9274                                                 adev->gfx.config.max_shader_engines);
9275         disabled_sa = efuse_setting | vbios_setting;
9276         disabled_sa &= max_sa_mask;
9277
9278         return disabled_sa;
9279 }
9280
9281 static void gfx_v10_3_program_pbb_mode(struct amdgpu_device *adev)
9282 {
9283         uint32_t max_sa_per_se, max_sa_per_se_mask, max_shader_engines;
9284         uint32_t disabled_sa_mask, se_index, disabled_sa_per_se;
9285
9286         disabled_sa_mask = gfx_v10_3_get_disabled_sa(adev);
9287
9288         max_sa_per_se = adev->gfx.config.max_sh_per_se;
9289         max_sa_per_se_mask = (1 << max_sa_per_se) - 1;
9290         max_shader_engines = adev->gfx.config.max_shader_engines;
9291
9292         for (se_index = 0; max_shader_engines > se_index; se_index++) {
9293                 disabled_sa_per_se = disabled_sa_mask >> (se_index * max_sa_per_se);
9294                 disabled_sa_per_se &= max_sa_per_se_mask;
9295                 if (disabled_sa_per_se == max_sa_per_se_mask) {
9296                         WREG32_FIELD15(GC, 0, PA_SC_ENHANCE_3, FORCE_PBB_WORKLOAD_MODE_TO_ZERO, 1);
9297                         break;
9298                 }
9299         }
9300 }
9301
9302 static void gfx_v10_3_set_power_brake_sequence(struct amdgpu_device *adev)
9303 {
9304         WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX,
9305                      (0x1 << GRBM_GFX_INDEX__SA_BROADCAST_WRITES__SHIFT) |
9306                      (0x1 << GRBM_GFX_INDEX__INSTANCE_BROADCAST_WRITES__SHIFT) |
9307                      (0x1 << GRBM_GFX_INDEX__SE_BROADCAST_WRITES__SHIFT));
9308
9309         WREG32_SOC15(GC, 0, mmGC_CAC_IND_INDEX, ixPWRBRK_STALL_PATTERN_CTRL);
9310         WREG32_SOC15(GC, 0, mmGC_CAC_IND_DATA,
9311                      (0x1 << PWRBRK_STALL_PATTERN_CTRL__PWRBRK_STEP_INTERVAL__SHIFT) |
9312                      (0x12 << PWRBRK_STALL_PATTERN_CTRL__PWRBRK_BEGIN_STEP__SHIFT) |
9313                      (0x13 << PWRBRK_STALL_PATTERN_CTRL__PWRBRK_END_STEP__SHIFT) |
9314                      (0xf << PWRBRK_STALL_PATTERN_CTRL__PWRBRK_THROTTLE_PATTERN_BIT_NUMS__SHIFT));
9315
9316         WREG32_SOC15(GC, 0, mmGC_THROTTLE_CTRL_Sienna_Cichlid,
9317                      (0x1 << GC_THROTTLE_CTRL__PWRBRK_STALL_EN__SHIFT) |
9318                      (0x1 << GC_THROTTLE_CTRL__PATTERN_MODE__SHIFT) |
9319                      (0x5 << GC_THROTTLE_CTRL__RELEASE_STEP_INTERVAL__SHIFT));
9320
9321         WREG32_SOC15(GC, 0, mmDIDT_IND_INDEX, ixDIDT_SQ_THROTTLE_CTRL);
9322
9323         WREG32_SOC15(GC, 0, mmDIDT_IND_DATA,
9324                      (0x1 << DIDT_SQ_THROTTLE_CTRL__PWRBRK_STALL_EN__SHIFT));
9325 }
9326
9327 const struct amdgpu_ip_block_version gfx_v10_0_ip_block =
9328 {
9329         .type = AMD_IP_BLOCK_TYPE_GFX,
9330         .major = 10,
9331         .minor = 0,
9332         .rev = 0,
9333         .funcs = &gfx_v10_0_ip_funcs,
9334 };