drivers/gpu/drm/amd/amdgpu/df_v1_7.c

   1 /*
   2  * Copyright 2018 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23 #include "amdgpu.h"
  24 #include "df_v1_7.h"
  25
  26 #include "df/df_1_7_default.h"
  27 #include "df/df_1_7_offset.h"
  28 #include "df/df_1_7_sh_mask.h"
  29
  30 static u32 df_v1_7_channel_number[] = {1, 2, 0, 4, 0, 8, 0, 16, 2};
  31
  32 static void df_v1_7_sw_init(struct amdgpu_device *adev)
  33 {
  34         adev->df.hash_status.hash_64k = false;
  35         adev->df.hash_status.hash_2m = false;
  36         adev->df.hash_status.hash_1g = false;
  37 }
  38
  39 static void df_v1_7_sw_fini(struct amdgpu_device *adev)
  40 {
  41 }
  42
  43 static void df_v1_7_enable_broadcast_mode(struct amdgpu_device *adev,
  44                                           bool enable)
  45 {
  46         u32 tmp;
  47
  48         if (enable) {
  49                 tmp = RREG32_SOC15(DF, 0, mmFabricConfigAccessControl);
  50                 tmp &= ~FabricConfigAccessControl__CfgRegInstAccEn_MASK;
  51                 WREG32_SOC15(DF, 0, mmFabricConfigAccessControl, tmp);
  52         } else
  53                 WREG32_SOC15(DF, 0, mmFabricConfigAccessControl,
  54                              mmFabricConfigAccessControl_DEFAULT);
  55 }
  56
  57 static u32 df_v1_7_get_fb_channel_number(struct amdgpu_device *adev)
  58 {
  59         u32 tmp;
  60
  61         tmp = RREG32_SOC15(DF, 0, mmDF_CS_AON0_DramBaseAddress0);
  62         tmp &= DF_CS_AON0_DramBaseAddress0__IntLvNumChan_MASK;
  63         tmp >>= DF_CS_AON0_DramBaseAddress0__IntLvNumChan__SHIFT;
  64
  65         return tmp;
  66 }
  67
  68 static u32 df_v1_7_get_hbm_channel_number(struct amdgpu_device *adev)
  69 {
  70         int fb_channel_number;
  71
  72         fb_channel_number = adev->df.funcs->get_fb_channel_number(adev);
  73         if (fb_channel_number >= ARRAY_SIZE(df_v1_7_channel_number))
  74                 fb_channel_number = 0;
  75
  76         return df_v1_7_channel_number[fb_channel_number];
  77 }
  78
  79 static void df_v1_7_update_medium_grain_clock_gating(struct amdgpu_device *adev,
  80                                                      bool enable)
  81 {
  82         u32 tmp;
  83
  84         /* Put DF on broadcast mode */
  85         adev->df.funcs->enable_broadcast_mode(adev, true);
  86
  87         if (enable && (adev->cg_flags & AMD_CG_SUPPORT_DF_MGCG)) {
  88                 tmp = RREG32_SOC15(DF, 0, mmDF_PIE_AON0_DfGlobalClkGater);
  89                 tmp &= ~DF_PIE_AON0_DfGlobalClkGater__MGCGMode_MASK;
  90                 tmp |= DF_V1_7_MGCG_ENABLE_15_CYCLE_DELAY;
  91                 WREG32_SOC15(DF, 0, mmDF_PIE_AON0_DfGlobalClkGater, tmp);
  92         } else {
  93                 tmp = RREG32_SOC15(DF, 0, mmDF_PIE_AON0_DfGlobalClkGater);
  94                 tmp &= ~DF_PIE_AON0_DfGlobalClkGater__MGCGMode_MASK;
  95                 tmp |= DF_V1_7_MGCG_DISABLE;
  96                 WREG32_SOC15(DF, 0, mmDF_PIE_AON0_DfGlobalClkGater, tmp);
  97         }
  98
  99         /* Exit broadcast mode */
 100         adev->df.funcs->enable_broadcast_mode(adev, false);
 101 }
 102
 103 static void df_v1_7_get_clockgating_state(struct amdgpu_device *adev,
 104                                           u64 *flags)
 105 {
 106         u32 tmp;
 107
 108         /* AMD_CG_SUPPORT_DF_MGCG */
 109         tmp = RREG32_SOC15(DF, 0, mmDF_PIE_AON0_DfGlobalClkGater);
 110         if (tmp & DF_V1_7_MGCG_ENABLE_15_CYCLE_DELAY)
 111                 *flags |= AMD_CG_SUPPORT_DF_MGCG;
 112 }
 113
 114 static void df_v1_7_enable_ecc_force_par_wr_rmw(struct amdgpu_device *adev,
 115                                                 bool enable)
 116 {
 117         WREG32_FIELD15(DF, 0, DF_CS_AON0_CoherentSlaveModeCtrlA0,
 118                        ForceParWrRMW, enable);
 119 }
 120
 121 const struct amdgpu_df_funcs df_v1_7_funcs = {
 122         .sw_init = df_v1_7_sw_init,
 123         .sw_fini = df_v1_7_sw_fini,
 124         .enable_broadcast_mode = df_v1_7_enable_broadcast_mode,
 125         .get_fb_channel_number = df_v1_7_get_fb_channel_number,
 126         .get_hbm_channel_number = df_v1_7_get_hbm_channel_number,
 127         .update_medium_grain_clock_gating = df_v1_7_update_medium_grain_clock_gating,
 128         .get_clockgating_state = df_v1_7_get_clockgating_state,
 129         .enable_ecc_force_par_wr_rmw = df_v1_7_enable_ecc_force_par_wr_rmw,
 130 };