2 * Copyright 2014 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
24 #include <drm/drm_vblank.h>
27 #include "amdgpu_pm.h"
28 #include "amdgpu_i2c.h"
30 #include "amdgpu_pll.h"
31 #include "amdgpu_connectors.h"
32 #ifdef CONFIG_DRM_AMDGPU_SI
35 #ifdef CONFIG_DRM_AMDGPU_CIK
38 #include "dce_v10_0.h"
39 #include "dce_v11_0.h"
40 #include "dce_virtual.h"
41 #include "ivsrcid/ivsrcid_vislands30.h"
42 #include "amdgpu_display.h"
44 #define DCE_VIRTUAL_VBLANK_PERIOD 16666666
47 static void dce_virtual_set_display_funcs(struct amdgpu_device *adev);
48 static void dce_virtual_set_irq_funcs(struct amdgpu_device *adev);
49 static int dce_virtual_connector_encoder_init(struct amdgpu_device *adev,
51 static int dce_virtual_pageflip(struct amdgpu_device *adev,
53 static enum hrtimer_restart dce_virtual_vblank_timer_handle(struct hrtimer *vblank_timer);
54 static void dce_virtual_set_crtc_vblank_interrupt_state(struct amdgpu_device *adev,
56 enum amdgpu_interrupt_state state);
58 static u32 dce_virtual_vblank_get_counter(struct amdgpu_device *adev, int crtc)
63 static void dce_virtual_page_flip(struct amdgpu_device *adev,
64 int crtc_id, u64 crtc_base, bool async)
69 static int dce_virtual_crtc_get_scanoutpos(struct amdgpu_device *adev, int crtc,
70 u32 *vbl, u32 *position)
78 static bool dce_virtual_hpd_sense(struct amdgpu_device *adev,
79 enum amdgpu_hpd_id hpd)
84 static void dce_virtual_hpd_set_polarity(struct amdgpu_device *adev,
85 enum amdgpu_hpd_id hpd)
90 static u32 dce_virtual_hpd_get_gpio_reg(struct amdgpu_device *adev)
96 * dce_virtual_bandwidth_update - program display watermarks
98 * @adev: amdgpu_device pointer
100 * Calculate and program the display watermarks and line
101 * buffer allocation (CIK).
103 static void dce_virtual_bandwidth_update(struct amdgpu_device *adev)
108 static int dce_virtual_crtc_gamma_set(struct drm_crtc *crtc, u16 *red,
109 u16 *green, u16 *blue, uint32_t size,
110 struct drm_modeset_acquire_ctx *ctx)
115 static void dce_virtual_crtc_destroy(struct drm_crtc *crtc)
117 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
119 drm_crtc_cleanup(crtc);
123 static const struct drm_crtc_funcs dce_virtual_crtc_funcs = {
126 .gamma_set = dce_virtual_crtc_gamma_set,
127 .set_config = amdgpu_display_crtc_set_config,
128 .destroy = dce_virtual_crtc_destroy,
129 .page_flip_target = amdgpu_display_crtc_page_flip_target,
130 .get_vblank_counter = amdgpu_get_vblank_counter_kms,
131 .enable_vblank = amdgpu_enable_vblank_kms,
132 .disable_vblank = amdgpu_disable_vblank_kms,
133 .get_vblank_timestamp = drm_crtc_vblank_helper_get_vblank_timestamp,
136 static void dce_virtual_crtc_dpms(struct drm_crtc *crtc, int mode)
138 struct drm_device *dev = crtc->dev;
139 struct amdgpu_device *adev = drm_to_adev(dev);
140 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
144 case DRM_MODE_DPMS_ON:
145 amdgpu_crtc->enabled = true;
146 /* Make sure VBLANK interrupts are still enabled */
147 type = amdgpu_display_crtc_idx_to_irq_type(adev,
148 amdgpu_crtc->crtc_id);
149 amdgpu_irq_update(adev, &adev->crtc_irq, type);
150 drm_crtc_vblank_on(crtc);
152 case DRM_MODE_DPMS_STANDBY:
153 case DRM_MODE_DPMS_SUSPEND:
154 case DRM_MODE_DPMS_OFF:
155 drm_crtc_vblank_off(crtc);
156 amdgpu_crtc->enabled = false;
162 static void dce_virtual_crtc_prepare(struct drm_crtc *crtc)
164 dce_virtual_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);
167 static void dce_virtual_crtc_commit(struct drm_crtc *crtc)
169 dce_virtual_crtc_dpms(crtc, DRM_MODE_DPMS_ON);
172 static void dce_virtual_crtc_disable(struct drm_crtc *crtc)
174 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
175 struct drm_device *dev = crtc->dev;
178 drm_crtc_vblank_off(crtc);
180 amdgpu_crtc->enabled = false;
181 amdgpu_crtc->pll_id = ATOM_PPLL_INVALID;
182 amdgpu_crtc->encoder = NULL;
183 amdgpu_crtc->connector = NULL;
186 static int dce_virtual_crtc_mode_set(struct drm_crtc *crtc,
187 struct drm_display_mode *mode,
188 struct drm_display_mode *adjusted_mode,
189 int x, int y, struct drm_framebuffer *old_fb)
191 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
193 /* update the hw version fpr dpm */
194 amdgpu_crtc->hw_mode = *adjusted_mode;
199 static bool dce_virtual_crtc_mode_fixup(struct drm_crtc *crtc,
200 const struct drm_display_mode *mode,
201 struct drm_display_mode *adjusted_mode)
207 static int dce_virtual_crtc_set_base(struct drm_crtc *crtc, int x, int y,
208 struct drm_framebuffer *old_fb)
213 static int dce_virtual_crtc_set_base_atomic(struct drm_crtc *crtc,
214 struct drm_framebuffer *fb,
215 int x, int y, enum mode_set_atomic state)
220 static const struct drm_crtc_helper_funcs dce_virtual_crtc_helper_funcs = {
221 .dpms = dce_virtual_crtc_dpms,
222 .mode_fixup = dce_virtual_crtc_mode_fixup,
223 .mode_set = dce_virtual_crtc_mode_set,
224 .mode_set_base = dce_virtual_crtc_set_base,
225 .mode_set_base_atomic = dce_virtual_crtc_set_base_atomic,
226 .prepare = dce_virtual_crtc_prepare,
227 .commit = dce_virtual_crtc_commit,
228 .disable = dce_virtual_crtc_disable,
229 .get_scanout_position = amdgpu_crtc_get_scanout_position,
232 static int dce_virtual_crtc_init(struct amdgpu_device *adev, int index)
234 struct amdgpu_crtc *amdgpu_crtc;
236 amdgpu_crtc = kzalloc(sizeof(struct amdgpu_crtc) +
237 (AMDGPUFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
238 if (amdgpu_crtc == NULL)
241 drm_crtc_init(adev_to_drm(adev), &amdgpu_crtc->base, &dce_virtual_crtc_funcs);
243 drm_mode_crtc_set_gamma_size(&amdgpu_crtc->base, 256);
244 amdgpu_crtc->crtc_id = index;
245 adev->mode_info.crtcs[index] = amdgpu_crtc;
247 amdgpu_crtc->pll_id = ATOM_PPLL_INVALID;
248 amdgpu_crtc->encoder = NULL;
249 amdgpu_crtc->connector = NULL;
250 amdgpu_crtc->vsync_timer_enabled = AMDGPU_IRQ_STATE_DISABLE;
251 drm_crtc_helper_add(&amdgpu_crtc->base, &dce_virtual_crtc_helper_funcs);
253 hrtimer_init(&amdgpu_crtc->vblank_timer, CLOCK_MONOTONIC, HRTIMER_MODE_REL);
254 hrtimer_set_expires(&amdgpu_crtc->vblank_timer, DCE_VIRTUAL_VBLANK_PERIOD);
255 amdgpu_crtc->vblank_timer.function = dce_virtual_vblank_timer_handle;
256 hrtimer_start(&amdgpu_crtc->vblank_timer,
257 DCE_VIRTUAL_VBLANK_PERIOD, HRTIMER_MODE_REL);
261 static int dce_virtual_early_init(void *handle)
263 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
265 dce_virtual_set_display_funcs(adev);
266 dce_virtual_set_irq_funcs(adev);
268 adev->mode_info.num_hpd = 1;
269 adev->mode_info.num_dig = 1;
273 static struct drm_encoder *
274 dce_virtual_encoder(struct drm_connector *connector)
276 struct drm_encoder *encoder;
278 drm_connector_for_each_possible_encoder(connector, encoder) {
279 if (encoder->encoder_type == DRM_MODE_ENCODER_VIRTUAL)
283 /* pick the first one */
284 drm_connector_for_each_possible_encoder(connector, encoder)
290 static int dce_virtual_get_modes(struct drm_connector *connector)
292 struct drm_device *dev = connector->dev;
293 struct drm_display_mode *mode = NULL;
295 static const struct mode_size {
323 for (i = 0; i < ARRAY_SIZE(common_modes); i++) {
324 mode = drm_cvt_mode(dev, common_modes[i].w, common_modes[i].h, 60, false, false, false);
325 drm_mode_probed_add(connector, mode);
331 static enum drm_mode_status dce_virtual_mode_valid(struct drm_connector *connector,
332 struct drm_display_mode *mode)
338 dce_virtual_dpms(struct drm_connector *connector, int mode)
344 dce_virtual_set_property(struct drm_connector *connector,
345 struct drm_property *property,
351 static void dce_virtual_destroy(struct drm_connector *connector)
353 drm_connector_unregister(connector);
354 drm_connector_cleanup(connector);
358 static void dce_virtual_force(struct drm_connector *connector)
363 static const struct drm_connector_helper_funcs dce_virtual_connector_helper_funcs = {
364 .get_modes = dce_virtual_get_modes,
365 .mode_valid = dce_virtual_mode_valid,
366 .best_encoder = dce_virtual_encoder,
369 static const struct drm_connector_funcs dce_virtual_connector_funcs = {
370 .dpms = dce_virtual_dpms,
371 .fill_modes = drm_helper_probe_single_connector_modes,
372 .set_property = dce_virtual_set_property,
373 .destroy = dce_virtual_destroy,
374 .force = dce_virtual_force,
377 static int dce_virtual_sw_init(void *handle)
380 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
382 r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, VISLANDS30_IV_SRCID_SMU_DISP_TIMER2_TRIGGER, &adev->crtc_irq);
386 adev_to_drm(adev)->max_vblank_count = 0;
388 adev_to_drm(adev)->mode_config.funcs = &amdgpu_mode_funcs;
390 adev_to_drm(adev)->mode_config.max_width = 16384;
391 adev_to_drm(adev)->mode_config.max_height = 16384;
393 adev_to_drm(adev)->mode_config.preferred_depth = 24;
394 adev_to_drm(adev)->mode_config.prefer_shadow = 1;
396 adev_to_drm(adev)->mode_config.fb_base = adev->gmc.aper_base;
398 r = amdgpu_display_modeset_create_props(adev);
402 adev_to_drm(adev)->mode_config.max_width = 16384;
403 adev_to_drm(adev)->mode_config.max_height = 16384;
405 /* allocate crtcs, encoders, connectors */
406 for (i = 0; i < adev->mode_info.num_crtc; i++) {
407 r = dce_virtual_crtc_init(adev, i);
410 r = dce_virtual_connector_encoder_init(adev, i);
415 drm_kms_helper_poll_init(adev_to_drm(adev));
417 adev->mode_info.mode_config_initialized = true;
421 static int dce_virtual_sw_fini(void *handle)
423 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
426 for (i = 0; i < adev->mode_info.num_crtc; i++)
427 if (adev->mode_info.crtcs[i])
428 hrtimer_cancel(&adev->mode_info.crtcs[i]->vblank_timer);
430 kfree(adev->mode_info.bios_hardcoded_edid);
432 drm_kms_helper_poll_fini(adev_to_drm(adev));
434 drm_mode_config_cleanup(adev_to_drm(adev));
435 /* clear crtcs pointer to avoid dce irq finish routine access freed data */
436 memset(adev->mode_info.crtcs, 0, sizeof(adev->mode_info.crtcs[0]) * AMDGPU_MAX_CRTCS);
437 adev->mode_info.mode_config_initialized = false;
441 static int dce_virtual_hw_init(void *handle)
443 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
445 switch (adev->asic_type) {
446 #ifdef CONFIG_DRM_AMDGPU_SI
451 dce_v6_0_disable_dce(adev);
454 #ifdef CONFIG_DRM_AMDGPU_CIK
460 dce_v8_0_disable_dce(adev);
465 dce_v10_0_disable_dce(adev);
472 dce_v11_0_disable_dce(adev);
475 #ifdef CONFIG_DRM_AMDGPU_SI
486 static int dce_virtual_hw_fini(void *handle)
491 static int dce_virtual_suspend(void *handle)
493 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
496 r = amdgpu_display_suspend_helper(adev);
499 return dce_virtual_hw_fini(handle);
502 static int dce_virtual_resume(void *handle)
504 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
507 r = dce_virtual_hw_init(handle);
510 return amdgpu_display_resume_helper(adev);
513 static bool dce_virtual_is_idle(void *handle)
518 static int dce_virtual_wait_for_idle(void *handle)
523 static int dce_virtual_soft_reset(void *handle)
528 static int dce_virtual_set_clockgating_state(void *handle,
529 enum amd_clockgating_state state)
534 static int dce_virtual_set_powergating_state(void *handle,
535 enum amd_powergating_state state)
540 static const struct amd_ip_funcs dce_virtual_ip_funcs = {
541 .name = "dce_virtual",
542 .early_init = dce_virtual_early_init,
544 .sw_init = dce_virtual_sw_init,
545 .sw_fini = dce_virtual_sw_fini,
546 .hw_init = dce_virtual_hw_init,
547 .hw_fini = dce_virtual_hw_fini,
548 .suspend = dce_virtual_suspend,
549 .resume = dce_virtual_resume,
550 .is_idle = dce_virtual_is_idle,
551 .wait_for_idle = dce_virtual_wait_for_idle,
552 .soft_reset = dce_virtual_soft_reset,
553 .set_clockgating_state = dce_virtual_set_clockgating_state,
554 .set_powergating_state = dce_virtual_set_powergating_state,
557 /* these are handled by the primary encoders */
558 static void dce_virtual_encoder_prepare(struct drm_encoder *encoder)
563 static void dce_virtual_encoder_commit(struct drm_encoder *encoder)
569 dce_virtual_encoder_mode_set(struct drm_encoder *encoder,
570 struct drm_display_mode *mode,
571 struct drm_display_mode *adjusted_mode)
576 static void dce_virtual_encoder_disable(struct drm_encoder *encoder)
582 dce_virtual_encoder_dpms(struct drm_encoder *encoder, int mode)
587 static bool dce_virtual_encoder_mode_fixup(struct drm_encoder *encoder,
588 const struct drm_display_mode *mode,
589 struct drm_display_mode *adjusted_mode)
594 static const struct drm_encoder_helper_funcs dce_virtual_encoder_helper_funcs = {
595 .dpms = dce_virtual_encoder_dpms,
596 .mode_fixup = dce_virtual_encoder_mode_fixup,
597 .prepare = dce_virtual_encoder_prepare,
598 .mode_set = dce_virtual_encoder_mode_set,
599 .commit = dce_virtual_encoder_commit,
600 .disable = dce_virtual_encoder_disable,
603 static void dce_virtual_encoder_destroy(struct drm_encoder *encoder)
605 drm_encoder_cleanup(encoder);
609 static const struct drm_encoder_funcs dce_virtual_encoder_funcs = {
610 .destroy = dce_virtual_encoder_destroy,
613 static int dce_virtual_connector_encoder_init(struct amdgpu_device *adev,
616 struct drm_encoder *encoder;
617 struct drm_connector *connector;
619 /* add a new encoder */
620 encoder = kzalloc(sizeof(struct drm_encoder), GFP_KERNEL);
623 encoder->possible_crtcs = 1 << index;
624 drm_encoder_init(adev_to_drm(adev), encoder, &dce_virtual_encoder_funcs,
625 DRM_MODE_ENCODER_VIRTUAL, NULL);
626 drm_encoder_helper_add(encoder, &dce_virtual_encoder_helper_funcs);
628 connector = kzalloc(sizeof(struct drm_connector), GFP_KERNEL);
634 /* add a new connector */
635 drm_connector_init(adev_to_drm(adev), connector, &dce_virtual_connector_funcs,
636 DRM_MODE_CONNECTOR_VIRTUAL);
637 drm_connector_helper_add(connector, &dce_virtual_connector_helper_funcs);
638 connector->display_info.subpixel_order = SubPixelHorizontalRGB;
639 connector->interlace_allowed = false;
640 connector->doublescan_allowed = false;
643 drm_connector_attach_encoder(connector, encoder);
648 static const struct amdgpu_display_funcs dce_virtual_display_funcs = {
649 .bandwidth_update = &dce_virtual_bandwidth_update,
650 .vblank_get_counter = &dce_virtual_vblank_get_counter,
651 .backlight_set_level = NULL,
652 .backlight_get_level = NULL,
653 .hpd_sense = &dce_virtual_hpd_sense,
654 .hpd_set_polarity = &dce_virtual_hpd_set_polarity,
655 .hpd_get_gpio_reg = &dce_virtual_hpd_get_gpio_reg,
656 .page_flip = &dce_virtual_page_flip,
657 .page_flip_get_scanoutpos = &dce_virtual_crtc_get_scanoutpos,
659 .add_connector = NULL,
662 static void dce_virtual_set_display_funcs(struct amdgpu_device *adev)
664 adev->mode_info.funcs = &dce_virtual_display_funcs;
667 static int dce_virtual_pageflip(struct amdgpu_device *adev,
671 struct amdgpu_crtc *amdgpu_crtc;
672 struct amdgpu_flip_work *works;
674 amdgpu_crtc = adev->mode_info.crtcs[crtc_id];
676 if (crtc_id >= adev->mode_info.num_crtc) {
677 DRM_ERROR("invalid pageflip crtc %d\n", crtc_id);
681 /* IRQ could occur when in initial stage */
682 if (amdgpu_crtc == NULL)
685 spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags);
686 works = amdgpu_crtc->pflip_works;
687 if (amdgpu_crtc->pflip_status != AMDGPU_FLIP_SUBMITTED) {
688 DRM_DEBUG_DRIVER("amdgpu_crtc->pflip_status = %d != "
689 "AMDGPU_FLIP_SUBMITTED(%d)\n",
690 amdgpu_crtc->pflip_status,
691 AMDGPU_FLIP_SUBMITTED);
692 spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags);
696 /* page flip completed. clean up */
697 amdgpu_crtc->pflip_status = AMDGPU_FLIP_NONE;
698 amdgpu_crtc->pflip_works = NULL;
700 /* wakeup usersapce */
702 drm_crtc_send_vblank_event(&amdgpu_crtc->base, works->event);
704 spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags);
706 drm_crtc_vblank_put(&amdgpu_crtc->base);
707 amdgpu_bo_unref(&works->old_abo);
708 kfree(works->shared);
714 static enum hrtimer_restart dce_virtual_vblank_timer_handle(struct hrtimer *vblank_timer)
716 struct amdgpu_crtc *amdgpu_crtc = container_of(vblank_timer,
717 struct amdgpu_crtc, vblank_timer);
718 struct drm_device *ddev = amdgpu_crtc->base.dev;
719 struct amdgpu_device *adev = drm_to_adev(ddev);
720 struct amdgpu_irq_src *source = adev->irq.client[AMDGPU_IRQ_CLIENTID_LEGACY].sources
721 [VISLANDS30_IV_SRCID_SMU_DISP_TIMER2_TRIGGER];
722 int irq_type = amdgpu_display_crtc_idx_to_irq_type(adev,
723 amdgpu_crtc->crtc_id);
725 if (amdgpu_irq_enabled(adev, source, irq_type)) {
726 drm_handle_vblank(ddev, amdgpu_crtc->crtc_id);
727 dce_virtual_pageflip(adev, amdgpu_crtc->crtc_id);
729 hrtimer_start(vblank_timer, DCE_VIRTUAL_VBLANK_PERIOD,
732 return HRTIMER_NORESTART;
735 static void dce_virtual_set_crtc_vblank_interrupt_state(struct amdgpu_device *adev,
737 enum amdgpu_interrupt_state state)
739 if (crtc >= adev->mode_info.num_crtc || !adev->mode_info.crtcs[crtc]) {
740 DRM_DEBUG("invalid crtc %d\n", crtc);
744 adev->mode_info.crtcs[crtc]->vsync_timer_enabled = state;
745 DRM_DEBUG("[FM]set crtc %d vblank interrupt state %d\n", crtc, state);
749 static int dce_virtual_set_crtc_irq_state(struct amdgpu_device *adev,
750 struct amdgpu_irq_src *source,
752 enum amdgpu_interrupt_state state)
754 if (type > AMDGPU_CRTC_IRQ_VBLANK6)
757 dce_virtual_set_crtc_vblank_interrupt_state(adev, type, state);
762 static const struct amdgpu_irq_src_funcs dce_virtual_crtc_irq_funcs = {
763 .set = dce_virtual_set_crtc_irq_state,
767 static void dce_virtual_set_irq_funcs(struct amdgpu_device *adev)
769 adev->crtc_irq.num_types = adev->mode_info.num_crtc;
770 adev->crtc_irq.funcs = &dce_virtual_crtc_irq_funcs;
773 const struct amdgpu_ip_block_version dce_virtual_ip_block =
775 .type = AMD_IP_BLOCK_TYPE_DCE,
779 .funcs = &dce_virtual_ip_funcs,