2 * Copyright 2014 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
25 #include "amdgpu_pm.h"
26 #include "amdgpu_i2c.h"
28 #include "amdgpu_pll.h"
29 #include "amdgpu_connectors.h"
30 #ifdef CONFIG_DRM_AMDGPU_SI
33 #ifdef CONFIG_DRM_AMDGPU_CIK
36 #include "dce_v10_0.h"
37 #include "dce_v11_0.h"
38 #include "dce_virtual.h"
39 #include "ivsrcid/ivsrcid_vislands30.h"
41 #define DCE_VIRTUAL_VBLANK_PERIOD 16666666
44 static void dce_virtual_set_display_funcs(struct amdgpu_device *adev);
45 static void dce_virtual_set_irq_funcs(struct amdgpu_device *adev);
46 static int dce_virtual_connector_encoder_init(struct amdgpu_device *adev,
48 static void dce_virtual_set_crtc_vblank_interrupt_state(struct amdgpu_device *adev,
50 enum amdgpu_interrupt_state state);
52 static u32 dce_virtual_vblank_get_counter(struct amdgpu_device *adev, int crtc)
57 static void dce_virtual_page_flip(struct amdgpu_device *adev,
58 int crtc_id, u64 crtc_base, bool async)
63 static int dce_virtual_crtc_get_scanoutpos(struct amdgpu_device *adev, int crtc,
64 u32 *vbl, u32 *position)
72 static bool dce_virtual_hpd_sense(struct amdgpu_device *adev,
73 enum amdgpu_hpd_id hpd)
78 static void dce_virtual_hpd_set_polarity(struct amdgpu_device *adev,
79 enum amdgpu_hpd_id hpd)
84 static u32 dce_virtual_hpd_get_gpio_reg(struct amdgpu_device *adev)
90 * dce_virtual_bandwidth_update - program display watermarks
92 * @adev: amdgpu_device pointer
94 * Calculate and program the display watermarks and line
95 * buffer allocation (CIK).
97 static void dce_virtual_bandwidth_update(struct amdgpu_device *adev)
102 static int dce_virtual_crtc_gamma_set(struct drm_crtc *crtc, u16 *red,
103 u16 *green, u16 *blue, uint32_t size,
104 struct drm_modeset_acquire_ctx *ctx)
109 static void dce_virtual_crtc_destroy(struct drm_crtc *crtc)
111 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
113 drm_crtc_cleanup(crtc);
117 static const struct drm_crtc_funcs dce_virtual_crtc_funcs = {
120 .gamma_set = dce_virtual_crtc_gamma_set,
121 .set_config = amdgpu_display_crtc_set_config,
122 .destroy = dce_virtual_crtc_destroy,
123 .page_flip_target = amdgpu_display_crtc_page_flip_target,
126 static void dce_virtual_crtc_dpms(struct drm_crtc *crtc, int mode)
128 struct drm_device *dev = crtc->dev;
129 struct amdgpu_device *adev = dev->dev_private;
130 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
133 if (amdgpu_sriov_vf(adev))
137 case DRM_MODE_DPMS_ON:
138 amdgpu_crtc->enabled = true;
139 /* Make sure VBLANK interrupts are still enabled */
140 type = amdgpu_display_crtc_idx_to_irq_type(adev,
141 amdgpu_crtc->crtc_id);
142 amdgpu_irq_update(adev, &adev->crtc_irq, type);
143 drm_crtc_vblank_on(crtc);
145 case DRM_MODE_DPMS_STANDBY:
146 case DRM_MODE_DPMS_SUSPEND:
147 case DRM_MODE_DPMS_OFF:
148 drm_crtc_vblank_off(crtc);
149 amdgpu_crtc->enabled = false;
155 static void dce_virtual_crtc_prepare(struct drm_crtc *crtc)
157 dce_virtual_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);
160 static void dce_virtual_crtc_commit(struct drm_crtc *crtc)
162 dce_virtual_crtc_dpms(crtc, DRM_MODE_DPMS_ON);
165 static void dce_virtual_crtc_disable(struct drm_crtc *crtc)
167 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
169 dce_virtual_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);
170 if (crtc->primary->fb) {
172 struct amdgpu_bo *abo;
174 abo = gem_to_amdgpu_bo(crtc->primary->fb->obj[0]);
175 r = amdgpu_bo_reserve(abo, true);
177 DRM_ERROR("failed to reserve abo before unpin\n");
179 amdgpu_bo_unpin(abo);
180 amdgpu_bo_unreserve(abo);
184 amdgpu_crtc->pll_id = ATOM_PPLL_INVALID;
185 amdgpu_crtc->encoder = NULL;
186 amdgpu_crtc->connector = NULL;
189 static int dce_virtual_crtc_mode_set(struct drm_crtc *crtc,
190 struct drm_display_mode *mode,
191 struct drm_display_mode *adjusted_mode,
192 int x, int y, struct drm_framebuffer *old_fb)
194 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
196 /* update the hw version fpr dpm */
197 amdgpu_crtc->hw_mode = *adjusted_mode;
202 static bool dce_virtual_crtc_mode_fixup(struct drm_crtc *crtc,
203 const struct drm_display_mode *mode,
204 struct drm_display_mode *adjusted_mode)
210 static int dce_virtual_crtc_set_base(struct drm_crtc *crtc, int x, int y,
211 struct drm_framebuffer *old_fb)
216 static int dce_virtual_crtc_set_base_atomic(struct drm_crtc *crtc,
217 struct drm_framebuffer *fb,
218 int x, int y, enum mode_set_atomic state)
223 static const struct drm_crtc_helper_funcs dce_virtual_crtc_helper_funcs = {
224 .dpms = dce_virtual_crtc_dpms,
225 .mode_fixup = dce_virtual_crtc_mode_fixup,
226 .mode_set = dce_virtual_crtc_mode_set,
227 .mode_set_base = dce_virtual_crtc_set_base,
228 .mode_set_base_atomic = dce_virtual_crtc_set_base_atomic,
229 .prepare = dce_virtual_crtc_prepare,
230 .commit = dce_virtual_crtc_commit,
231 .disable = dce_virtual_crtc_disable,
234 static int dce_virtual_crtc_init(struct amdgpu_device *adev, int index)
236 struct amdgpu_crtc *amdgpu_crtc;
238 amdgpu_crtc = kzalloc(sizeof(struct amdgpu_crtc) +
239 (AMDGPUFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
240 if (amdgpu_crtc == NULL)
243 drm_crtc_init(adev->ddev, &amdgpu_crtc->base, &dce_virtual_crtc_funcs);
245 drm_mode_crtc_set_gamma_size(&amdgpu_crtc->base, 256);
246 amdgpu_crtc->crtc_id = index;
247 adev->mode_info.crtcs[index] = amdgpu_crtc;
249 amdgpu_crtc->pll_id = ATOM_PPLL_INVALID;
250 amdgpu_crtc->encoder = NULL;
251 amdgpu_crtc->connector = NULL;
252 amdgpu_crtc->vsync_timer_enabled = AMDGPU_IRQ_STATE_DISABLE;
253 drm_crtc_helper_add(&amdgpu_crtc->base, &dce_virtual_crtc_helper_funcs);
258 static int dce_virtual_early_init(void *handle)
260 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
262 dce_virtual_set_display_funcs(adev);
263 dce_virtual_set_irq_funcs(adev);
265 adev->mode_info.num_hpd = 1;
266 adev->mode_info.num_dig = 1;
270 static struct drm_encoder *
271 dce_virtual_encoder(struct drm_connector *connector)
273 struct drm_encoder *encoder;
276 drm_connector_for_each_possible_encoder(connector, encoder, i) {
277 if (encoder->encoder_type == DRM_MODE_ENCODER_VIRTUAL)
281 /* pick the first one */
282 drm_connector_for_each_possible_encoder(connector, encoder, i)
288 static int dce_virtual_get_modes(struct drm_connector *connector)
290 struct drm_device *dev = connector->dev;
291 struct drm_display_mode *mode = NULL;
293 static const struct mode_size {
296 } common_modes[17] = {
316 for (i = 0; i < 17; i++) {
317 mode = drm_cvt_mode(dev, common_modes[i].w, common_modes[i].h, 60, false, false, false);
318 drm_mode_probed_add(connector, mode);
324 static enum drm_mode_status dce_virtual_mode_valid(struct drm_connector *connector,
325 struct drm_display_mode *mode)
331 dce_virtual_dpms(struct drm_connector *connector, int mode)
337 dce_virtual_set_property(struct drm_connector *connector,
338 struct drm_property *property,
344 static void dce_virtual_destroy(struct drm_connector *connector)
346 drm_connector_unregister(connector);
347 drm_connector_cleanup(connector);
351 static void dce_virtual_force(struct drm_connector *connector)
356 static const struct drm_connector_helper_funcs dce_virtual_connector_helper_funcs = {
357 .get_modes = dce_virtual_get_modes,
358 .mode_valid = dce_virtual_mode_valid,
359 .best_encoder = dce_virtual_encoder,
362 static const struct drm_connector_funcs dce_virtual_connector_funcs = {
363 .dpms = dce_virtual_dpms,
364 .fill_modes = drm_helper_probe_single_connector_modes,
365 .set_property = dce_virtual_set_property,
366 .destroy = dce_virtual_destroy,
367 .force = dce_virtual_force,
370 static int dce_virtual_sw_init(void *handle)
373 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
375 r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, VISLANDS30_IV_SRCID_SMU_DISP_TIMER2_TRIGGER, &adev->crtc_irq);
379 adev->ddev->max_vblank_count = 0;
381 adev->ddev->mode_config.funcs = &amdgpu_mode_funcs;
383 adev->ddev->mode_config.max_width = 16384;
384 adev->ddev->mode_config.max_height = 16384;
386 adev->ddev->mode_config.preferred_depth = 24;
387 adev->ddev->mode_config.prefer_shadow = 1;
389 adev->ddev->mode_config.fb_base = adev->gmc.aper_base;
391 r = amdgpu_display_modeset_create_props(adev);
395 adev->ddev->mode_config.max_width = 16384;
396 adev->ddev->mode_config.max_height = 16384;
398 /* allocate crtcs, encoders, connectors */
399 for (i = 0; i < adev->mode_info.num_crtc; i++) {
400 r = dce_virtual_crtc_init(adev, i);
403 r = dce_virtual_connector_encoder_init(adev, i);
408 drm_kms_helper_poll_init(adev->ddev);
410 adev->mode_info.mode_config_initialized = true;
414 static int dce_virtual_sw_fini(void *handle)
416 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
418 kfree(adev->mode_info.bios_hardcoded_edid);
420 drm_kms_helper_poll_fini(adev->ddev);
422 drm_mode_config_cleanup(adev->ddev);
423 /* clear crtcs pointer to avoid dce irq finish routine access freed data */
424 memset(adev->mode_info.crtcs, 0, sizeof(adev->mode_info.crtcs[0]) * AMDGPU_MAX_CRTCS);
425 adev->mode_info.mode_config_initialized = false;
429 static int dce_virtual_hw_init(void *handle)
431 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
433 switch (adev->asic_type) {
434 #ifdef CONFIG_DRM_AMDGPU_SI
439 dce_v6_0_disable_dce(adev);
442 #ifdef CONFIG_DRM_AMDGPU_CIK
448 dce_v8_0_disable_dce(adev);
453 dce_v10_0_disable_dce(adev);
460 dce_v11_0_disable_dce(adev);
463 #ifdef CONFIG_DRM_AMDGPU_SI
473 DRM_ERROR("Virtual display unsupported ASIC type: 0x%X\n", adev->asic_type);
478 static int dce_virtual_hw_fini(void *handle)
480 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
483 for (i = 0; i<adev->mode_info.num_crtc; i++)
484 if (adev->mode_info.crtcs[i])
485 dce_virtual_set_crtc_vblank_interrupt_state(adev, i, AMDGPU_IRQ_STATE_DISABLE);
490 static int dce_virtual_suspend(void *handle)
492 return dce_virtual_hw_fini(handle);
495 static int dce_virtual_resume(void *handle)
497 return dce_virtual_hw_init(handle);
500 static bool dce_virtual_is_idle(void *handle)
505 static int dce_virtual_wait_for_idle(void *handle)
510 static int dce_virtual_soft_reset(void *handle)
515 static int dce_virtual_set_clockgating_state(void *handle,
516 enum amd_clockgating_state state)
521 static int dce_virtual_set_powergating_state(void *handle,
522 enum amd_powergating_state state)
527 static const struct amd_ip_funcs dce_virtual_ip_funcs = {
528 .name = "dce_virtual",
529 .early_init = dce_virtual_early_init,
531 .sw_init = dce_virtual_sw_init,
532 .sw_fini = dce_virtual_sw_fini,
533 .hw_init = dce_virtual_hw_init,
534 .hw_fini = dce_virtual_hw_fini,
535 .suspend = dce_virtual_suspend,
536 .resume = dce_virtual_resume,
537 .is_idle = dce_virtual_is_idle,
538 .wait_for_idle = dce_virtual_wait_for_idle,
539 .soft_reset = dce_virtual_soft_reset,
540 .set_clockgating_state = dce_virtual_set_clockgating_state,
541 .set_powergating_state = dce_virtual_set_powergating_state,
544 /* these are handled by the primary encoders */
545 static void dce_virtual_encoder_prepare(struct drm_encoder *encoder)
550 static void dce_virtual_encoder_commit(struct drm_encoder *encoder)
556 dce_virtual_encoder_mode_set(struct drm_encoder *encoder,
557 struct drm_display_mode *mode,
558 struct drm_display_mode *adjusted_mode)
563 static void dce_virtual_encoder_disable(struct drm_encoder *encoder)
569 dce_virtual_encoder_dpms(struct drm_encoder *encoder, int mode)
574 static bool dce_virtual_encoder_mode_fixup(struct drm_encoder *encoder,
575 const struct drm_display_mode *mode,
576 struct drm_display_mode *adjusted_mode)
581 static const struct drm_encoder_helper_funcs dce_virtual_encoder_helper_funcs = {
582 .dpms = dce_virtual_encoder_dpms,
583 .mode_fixup = dce_virtual_encoder_mode_fixup,
584 .prepare = dce_virtual_encoder_prepare,
585 .mode_set = dce_virtual_encoder_mode_set,
586 .commit = dce_virtual_encoder_commit,
587 .disable = dce_virtual_encoder_disable,
590 static void dce_virtual_encoder_destroy(struct drm_encoder *encoder)
592 drm_encoder_cleanup(encoder);
596 static const struct drm_encoder_funcs dce_virtual_encoder_funcs = {
597 .destroy = dce_virtual_encoder_destroy,
600 static int dce_virtual_connector_encoder_init(struct amdgpu_device *adev,
603 struct drm_encoder *encoder;
604 struct drm_connector *connector;
606 /* add a new encoder */
607 encoder = kzalloc(sizeof(struct drm_encoder), GFP_KERNEL);
610 encoder->possible_crtcs = 1 << index;
611 drm_encoder_init(adev->ddev, encoder, &dce_virtual_encoder_funcs,
612 DRM_MODE_ENCODER_VIRTUAL, NULL);
613 drm_encoder_helper_add(encoder, &dce_virtual_encoder_helper_funcs);
615 connector = kzalloc(sizeof(struct drm_connector), GFP_KERNEL);
621 /* add a new connector */
622 drm_connector_init(adev->ddev, connector, &dce_virtual_connector_funcs,
623 DRM_MODE_CONNECTOR_VIRTUAL);
624 drm_connector_helper_add(connector, &dce_virtual_connector_helper_funcs);
625 connector->display_info.subpixel_order = SubPixelHorizontalRGB;
626 connector->interlace_allowed = false;
627 connector->doublescan_allowed = false;
628 drm_connector_register(connector);
631 drm_connector_attach_encoder(connector, encoder);
636 static const struct amdgpu_display_funcs dce_virtual_display_funcs = {
637 .bandwidth_update = &dce_virtual_bandwidth_update,
638 .vblank_get_counter = &dce_virtual_vblank_get_counter,
639 .backlight_set_level = NULL,
640 .backlight_get_level = NULL,
641 .hpd_sense = &dce_virtual_hpd_sense,
642 .hpd_set_polarity = &dce_virtual_hpd_set_polarity,
643 .hpd_get_gpio_reg = &dce_virtual_hpd_get_gpio_reg,
644 .page_flip = &dce_virtual_page_flip,
645 .page_flip_get_scanoutpos = &dce_virtual_crtc_get_scanoutpos,
647 .add_connector = NULL,
650 static void dce_virtual_set_display_funcs(struct amdgpu_device *adev)
652 adev->mode_info.funcs = &dce_virtual_display_funcs;
655 static int dce_virtual_pageflip(struct amdgpu_device *adev,
659 struct amdgpu_crtc *amdgpu_crtc;
660 struct amdgpu_flip_work *works;
662 amdgpu_crtc = adev->mode_info.crtcs[crtc_id];
664 if (crtc_id >= adev->mode_info.num_crtc) {
665 DRM_ERROR("invalid pageflip crtc %d\n", crtc_id);
669 /* IRQ could occur when in initial stage */
670 if (amdgpu_crtc == NULL)
673 spin_lock_irqsave(&adev->ddev->event_lock, flags);
674 works = amdgpu_crtc->pflip_works;
675 if (amdgpu_crtc->pflip_status != AMDGPU_FLIP_SUBMITTED) {
676 DRM_DEBUG_DRIVER("amdgpu_crtc->pflip_status = %d != "
677 "AMDGPU_FLIP_SUBMITTED(%d)\n",
678 amdgpu_crtc->pflip_status,
679 AMDGPU_FLIP_SUBMITTED);
680 spin_unlock_irqrestore(&adev->ddev->event_lock, flags);
684 /* page flip completed. clean up */
685 amdgpu_crtc->pflip_status = AMDGPU_FLIP_NONE;
686 amdgpu_crtc->pflip_works = NULL;
688 /* wakeup usersapce */
690 drm_crtc_send_vblank_event(&amdgpu_crtc->base, works->event);
692 spin_unlock_irqrestore(&adev->ddev->event_lock, flags);
694 drm_crtc_vblank_put(&amdgpu_crtc->base);
695 schedule_work(&works->unpin_work);
700 static enum hrtimer_restart dce_virtual_vblank_timer_handle(struct hrtimer *vblank_timer)
702 struct amdgpu_crtc *amdgpu_crtc = container_of(vblank_timer,
703 struct amdgpu_crtc, vblank_timer);
704 struct drm_device *ddev = amdgpu_crtc->base.dev;
705 struct amdgpu_device *adev = ddev->dev_private;
707 drm_handle_vblank(ddev, amdgpu_crtc->crtc_id);
708 dce_virtual_pageflip(adev, amdgpu_crtc->crtc_id);
709 hrtimer_start(vblank_timer, DCE_VIRTUAL_VBLANK_PERIOD,
712 return HRTIMER_NORESTART;
715 static void dce_virtual_set_crtc_vblank_interrupt_state(struct amdgpu_device *adev,
717 enum amdgpu_interrupt_state state)
719 if (crtc >= adev->mode_info.num_crtc || !adev->mode_info.crtcs[crtc]) {
720 DRM_DEBUG("invalid crtc %d\n", crtc);
724 if (state && !adev->mode_info.crtcs[crtc]->vsync_timer_enabled) {
725 DRM_DEBUG("Enable software vsync timer\n");
726 hrtimer_init(&adev->mode_info.crtcs[crtc]->vblank_timer,
727 CLOCK_MONOTONIC, HRTIMER_MODE_REL);
728 hrtimer_set_expires(&adev->mode_info.crtcs[crtc]->vblank_timer,
729 DCE_VIRTUAL_VBLANK_PERIOD);
730 adev->mode_info.crtcs[crtc]->vblank_timer.function =
731 dce_virtual_vblank_timer_handle;
732 hrtimer_start(&adev->mode_info.crtcs[crtc]->vblank_timer,
733 DCE_VIRTUAL_VBLANK_PERIOD, HRTIMER_MODE_REL);
734 } else if (!state && adev->mode_info.crtcs[crtc]->vsync_timer_enabled) {
735 DRM_DEBUG("Disable software vsync timer\n");
736 hrtimer_cancel(&adev->mode_info.crtcs[crtc]->vblank_timer);
739 adev->mode_info.crtcs[crtc]->vsync_timer_enabled = state;
740 DRM_DEBUG("[FM]set crtc %d vblank interrupt state %d\n", crtc, state);
744 static int dce_virtual_set_crtc_irq_state(struct amdgpu_device *adev,
745 struct amdgpu_irq_src *source,
747 enum amdgpu_interrupt_state state)
749 if (type > AMDGPU_CRTC_IRQ_VBLANK6)
752 dce_virtual_set_crtc_vblank_interrupt_state(adev, type, state);
757 static const struct amdgpu_irq_src_funcs dce_virtual_crtc_irq_funcs = {
758 .set = dce_virtual_set_crtc_irq_state,
762 static void dce_virtual_set_irq_funcs(struct amdgpu_device *adev)
764 adev->crtc_irq.num_types = AMDGPU_CRTC_IRQ_VBLANK6 + 1;
765 adev->crtc_irq.funcs = &dce_virtual_crtc_irq_funcs;
768 const struct amdgpu_ip_block_version dce_virtual_ip_block =
770 .type = AMD_IP_BLOCK_TYPE_DCE,
774 .funcs = &dce_virtual_ip_funcs,