drivers/gpu/drm/amd/amdgpu/dce_virtual.c

   1 /*
   2  * Copyright 2014 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23
  24 #include <drm/drm_vblank.h>
  25
  26 #include "amdgpu.h"
  27 #include "amdgpu_pm.h"
  28 #include "amdgpu_i2c.h"
  29 #include "atom.h"
  30 #include "amdgpu_pll.h"
  31 #include "amdgpu_connectors.h"
  32 #ifdef CONFIG_DRM_AMDGPU_SI
  33 #include "dce_v6_0.h"
  34 #endif
  35 #ifdef CONFIG_DRM_AMDGPU_CIK
  36 #include "dce_v8_0.h"
  37 #endif
  38 #include "dce_v10_0.h"
  39 #include "dce_v11_0.h"
  40 #include "dce_virtual.h"
  41 #include "ivsrcid/ivsrcid_vislands30.h"
  42
  43 #define DCE_VIRTUAL_VBLANK_PERIOD 16666666
  44
  45
  46 static void dce_virtual_set_display_funcs(struct amdgpu_device *adev);
  47 static void dce_virtual_set_irq_funcs(struct amdgpu_device *adev);
  48 static int dce_virtual_connector_encoder_init(struct amdgpu_device *adev,
  49                                               int index);
  50 static int dce_virtual_pageflip(struct amdgpu_device *adev,
  51                                 unsigned crtc_id);
  52 static enum hrtimer_restart dce_virtual_vblank_timer_handle(struct hrtimer *vblank_timer);
  53 static void dce_virtual_set_crtc_vblank_interrupt_state(struct amdgpu_device *adev,
  54                                                         int crtc,
  55                                                         enum amdgpu_interrupt_state state);
  56
  57 static u32 dce_virtual_vblank_get_counter(struct amdgpu_device *adev, int crtc)
  58 {
  59         return 0;
  60 }
  61
  62 static void dce_virtual_page_flip(struct amdgpu_device *adev,
  63                               int crtc_id, u64 crtc_base, bool async)
  64 {
  65         return;
  66 }
  67
  68 static int dce_virtual_crtc_get_scanoutpos(struct amdgpu_device *adev, int crtc,
  69                                         u32 *vbl, u32 *position)
  70 {
  71         *vbl = 0;
  72         *position = 0;
  73
  74         return -EINVAL;
  75 }
  76
  77 static bool dce_virtual_hpd_sense(struct amdgpu_device *adev,
  78                                enum amdgpu_hpd_id hpd)
  79 {
  80         return true;
  81 }
  82
  83 static void dce_virtual_hpd_set_polarity(struct amdgpu_device *adev,
  84                                       enum amdgpu_hpd_id hpd)
  85 {
  86         return;
  87 }
  88
  89 static u32 dce_virtual_hpd_get_gpio_reg(struct amdgpu_device *adev)
  90 {
  91         return 0;
  92 }
  93
  94 /**
  95  * dce_virtual_bandwidth_update - program display watermarks
  96  *
  97  * @adev: amdgpu_device pointer
  98  *
  99  * Calculate and program the display watermarks and line
 100  * buffer allocation (CIK).
 101  */
 102 static void dce_virtual_bandwidth_update(struct amdgpu_device *adev)
 103 {
 104         return;
 105 }
 106
 107 static int dce_virtual_crtc_gamma_set(struct drm_crtc *crtc, u16 *red,
 108                                       u16 *green, u16 *blue, uint32_t size,
 109                                       struct drm_modeset_acquire_ctx *ctx)
 110 {
 111         return 0;
 112 }
 113
 114 static void dce_virtual_crtc_destroy(struct drm_crtc *crtc)
 115 {
 116         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
 117
 118         drm_crtc_cleanup(crtc);
 119         kfree(amdgpu_crtc);
 120 }
 121
 122 static const struct drm_crtc_funcs dce_virtual_crtc_funcs = {
 123         .cursor_set2 = NULL,
 124         .cursor_move = NULL,
 125         .gamma_set = dce_virtual_crtc_gamma_set,
 126         .set_config = amdgpu_display_crtc_set_config,
 127         .destroy = dce_virtual_crtc_destroy,
 128         .page_flip_target = amdgpu_display_crtc_page_flip_target,
 129         .get_vblank_counter = amdgpu_get_vblank_counter_kms,
 130         .enable_vblank = amdgpu_enable_vblank_kms,
 131         .disable_vblank = amdgpu_disable_vblank_kms,
 132         .get_vblank_timestamp = drm_crtc_vblank_helper_get_vblank_timestamp,
 133 };
 134
 135 static void dce_virtual_crtc_dpms(struct drm_crtc *crtc, int mode)
 136 {
 137         struct drm_device *dev = crtc->dev;
 138         struct amdgpu_device *adev = drm_to_adev(dev);
 139         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
 140         unsigned type;
 141
 142         switch (mode) {
 143         case DRM_MODE_DPMS_ON:
 144                 amdgpu_crtc->enabled = true;
 145                 /* Make sure VBLANK interrupts are still enabled */
 146                 type = amdgpu_display_crtc_idx_to_irq_type(adev,
 147                                                 amdgpu_crtc->crtc_id);
 148                 amdgpu_irq_update(adev, &adev->crtc_irq, type);
 149                 drm_crtc_vblank_on(crtc);
 150                 break;
 151         case DRM_MODE_DPMS_STANDBY:
 152         case DRM_MODE_DPMS_SUSPEND:
 153         case DRM_MODE_DPMS_OFF:
 154                 drm_crtc_vblank_off(crtc);
 155                 amdgpu_crtc->enabled = false;
 156                 break;
 157         }
 158 }
 159
 160
 161 static void dce_virtual_crtc_prepare(struct drm_crtc *crtc)
 162 {
 163         dce_virtual_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);
 164 }
 165
 166 static void dce_virtual_crtc_commit(struct drm_crtc *crtc)
 167 {
 168         dce_virtual_crtc_dpms(crtc, DRM_MODE_DPMS_ON);
 169 }
 170
 171 static void dce_virtual_crtc_disable(struct drm_crtc *crtc)
 172 {
 173         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
 174         struct drm_device *dev = crtc->dev;
 175
 176         if (dev->num_crtcs)
 177                 drm_crtc_vblank_off(crtc);
 178
 179         amdgpu_crtc->enabled = false;
 180         amdgpu_crtc->pll_id = ATOM_PPLL_INVALID;
 181         amdgpu_crtc->encoder = NULL;
 182         amdgpu_crtc->connector = NULL;
 183 }
 184
 185 static int dce_virtual_crtc_mode_set(struct drm_crtc *crtc,
 186                                   struct drm_display_mode *mode,
 187                                   struct drm_display_mode *adjusted_mode,
 188                                   int x, int y, struct drm_framebuffer *old_fb)
 189 {
 190         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
 191
 192         /* update the hw version fpr dpm */
 193         amdgpu_crtc->hw_mode = *adjusted_mode;
 194
 195         return 0;
 196 }
 197
 198 static bool dce_virtual_crtc_mode_fixup(struct drm_crtc *crtc,
 199                                      const struct drm_display_mode *mode,
 200                                      struct drm_display_mode *adjusted_mode)
 201 {
 202         return true;
 203 }
 204
 205
 206 static int dce_virtual_crtc_set_base(struct drm_crtc *crtc, int x, int y,
 207                                   struct drm_framebuffer *old_fb)
 208 {
 209         return 0;
 210 }
 211
 212 static int dce_virtual_crtc_set_base_atomic(struct drm_crtc *crtc,
 213                                          struct drm_framebuffer *fb,
 214                                          int x, int y, enum mode_set_atomic state)
 215 {
 216         return 0;
 217 }
 218
 219 static const struct drm_crtc_helper_funcs dce_virtual_crtc_helper_funcs = {
 220         .dpms = dce_virtual_crtc_dpms,
 221         .mode_fixup = dce_virtual_crtc_mode_fixup,
 222         .mode_set = dce_virtual_crtc_mode_set,
 223         .mode_set_base = dce_virtual_crtc_set_base,
 224         .mode_set_base_atomic = dce_virtual_crtc_set_base_atomic,
 225         .prepare = dce_virtual_crtc_prepare,
 226         .commit = dce_virtual_crtc_commit,
 227         .disable = dce_virtual_crtc_disable,
 228         .get_scanout_position = amdgpu_crtc_get_scanout_position,
 229 };
 230
 231 static int dce_virtual_crtc_init(struct amdgpu_device *adev, int index)
 232 {
 233         struct amdgpu_crtc *amdgpu_crtc;
 234
 235         amdgpu_crtc = kzalloc(sizeof(struct amdgpu_crtc) +
 236                               (AMDGPUFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
 237         if (amdgpu_crtc == NULL)
 238                 return -ENOMEM;
 239
 240         drm_crtc_init(adev_to_drm(adev), &amdgpu_crtc->base, &dce_virtual_crtc_funcs);
 241
 242         drm_mode_crtc_set_gamma_size(&amdgpu_crtc->base, 256);
 243         amdgpu_crtc->crtc_id = index;
 244         adev->mode_info.crtcs[index] = amdgpu_crtc;
 245
 246         amdgpu_crtc->pll_id = ATOM_PPLL_INVALID;
 247         amdgpu_crtc->encoder = NULL;
 248         amdgpu_crtc->connector = NULL;
 249         amdgpu_crtc->vsync_timer_enabled = AMDGPU_IRQ_STATE_DISABLE;
 250         drm_crtc_helper_add(&amdgpu_crtc->base, &dce_virtual_crtc_helper_funcs);
 251
 252         hrtimer_init(&amdgpu_crtc->vblank_timer, CLOCK_MONOTONIC, HRTIMER_MODE_REL);
 253         hrtimer_set_expires(&amdgpu_crtc->vblank_timer, DCE_VIRTUAL_VBLANK_PERIOD);
 254         amdgpu_crtc->vblank_timer.function = dce_virtual_vblank_timer_handle;
 255         hrtimer_start(&amdgpu_crtc->vblank_timer,
 256                       DCE_VIRTUAL_VBLANK_PERIOD, HRTIMER_MODE_REL);
 257         return 0;
 258 }
 259
 260 static int dce_virtual_early_init(void *handle)
 261 {
 262         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 263
 264         dce_virtual_set_display_funcs(adev);
 265         dce_virtual_set_irq_funcs(adev);
 266
 267         adev->mode_info.num_hpd = 1;
 268         adev->mode_info.num_dig = 1;
 269         return 0;
 270 }
 271
 272 static struct drm_encoder *
 273 dce_virtual_encoder(struct drm_connector *connector)
 274 {
 275         struct drm_encoder *encoder;
 276
 277         drm_connector_for_each_possible_encoder(connector, encoder) {
 278                 if (encoder->encoder_type == DRM_MODE_ENCODER_VIRTUAL)
 279                         return encoder;
 280         }
 281
 282         /* pick the first one */
 283         drm_connector_for_each_possible_encoder(connector, encoder)
 284                 return encoder;
 285
 286         return NULL;
 287 }
 288
 289 static int dce_virtual_get_modes(struct drm_connector *connector)
 290 {
 291         struct drm_device *dev = connector->dev;
 292         struct drm_display_mode *mode = NULL;
 293         unsigned i;
 294         static const struct mode_size {
 295                 int w;
 296                 int h;
 297         } common_modes[] = {
 298                 { 640,  480},
 299                 { 720,  480},
 300                 { 800,  600},
 301                 { 848,  480},
 302                 {1024,  768},
 303                 {1152,  768},
 304                 {1280,  720},
 305                 {1280,  800},
 306                 {1280,  854},
 307                 {1280,  960},
 308                 {1280, 1024},
 309                 {1440,  900},
 310                 {1400, 1050},
 311                 {1680, 1050},
 312                 {1600, 1200},
 313                 {1920, 1080},
 314                 {1920, 1200},
 315                 {2560, 1440},
 316                 {4096, 3112},
 317                 {3656, 2664},
 318                 {3840, 2160},
 319                 {4096, 2160},
 320         };
 321
 322         for (i = 0; i < ARRAY_SIZE(common_modes); i++) {
 323                 mode = drm_cvt_mode(dev, common_modes[i].w, common_modes[i].h, 60, false, false, false);
 324                 drm_mode_probed_add(connector, mode);
 325         }
 326
 327         return 0;
 328 }
 329
 330 static enum drm_mode_status dce_virtual_mode_valid(struct drm_connector *connector,
 331                                   struct drm_display_mode *mode)
 332 {
 333         return MODE_OK;
 334 }
 335
 336 static int
 337 dce_virtual_dpms(struct drm_connector *connector, int mode)
 338 {
 339         return 0;
 340 }
 341
 342 static int
 343 dce_virtual_set_property(struct drm_connector *connector,
 344                          struct drm_property *property,
 345                          uint64_t val)
 346 {
 347         return 0;
 348 }
 349
 350 static void dce_virtual_destroy(struct drm_connector *connector)
 351 {
 352         drm_connector_unregister(connector);
 353         drm_connector_cleanup(connector);
 354         kfree(connector);
 355 }
 356
 357 static void dce_virtual_force(struct drm_connector *connector)
 358 {
 359         return;
 360 }
 361
 362 static const struct drm_connector_helper_funcs dce_virtual_connector_helper_funcs = {
 363         .get_modes = dce_virtual_get_modes,
 364         .mode_valid = dce_virtual_mode_valid,
 365         .best_encoder = dce_virtual_encoder,
 366 };
 367
 368 static const struct drm_connector_funcs dce_virtual_connector_funcs = {
 369         .dpms = dce_virtual_dpms,
 370         .fill_modes = drm_helper_probe_single_connector_modes,
 371         .set_property = dce_virtual_set_property,
 372         .destroy = dce_virtual_destroy,
 373         .force = dce_virtual_force,
 374 };
 375
 376 static int dce_virtual_sw_init(void *handle)
 377 {
 378         int r, i;
 379         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 380
 381         r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, VISLANDS30_IV_SRCID_SMU_DISP_TIMER2_TRIGGER, &adev->crtc_irq);
 382         if (r)
 383                 return r;
 384
 385         adev_to_drm(adev)->max_vblank_count = 0;
 386
 387         adev_to_drm(adev)->mode_config.funcs = &amdgpu_mode_funcs;
 388
 389         adev_to_drm(adev)->mode_config.max_width = 16384;
 390         adev_to_drm(adev)->mode_config.max_height = 16384;
 391
 392         adev_to_drm(adev)->mode_config.preferred_depth = 24;
 393         adev_to_drm(adev)->mode_config.prefer_shadow = 1;
 394
 395         adev_to_drm(adev)->mode_config.fb_base = adev->gmc.aper_base;
 396
 397         r = amdgpu_display_modeset_create_props(adev);
 398         if (r)
 399                 return r;
 400
 401         adev_to_drm(adev)->mode_config.max_width = 16384;
 402         adev_to_drm(adev)->mode_config.max_height = 16384;
 403
 404         /* allocate crtcs, encoders, connectors */
 405         for (i = 0; i < adev->mode_info.num_crtc; i++) {
 406                 r = dce_virtual_crtc_init(adev, i);
 407                 if (r)
 408                         return r;
 409                 r = dce_virtual_connector_encoder_init(adev, i);
 410                 if (r)
 411                         return r;
 412         }
 413
 414         drm_kms_helper_poll_init(adev_to_drm(adev));
 415
 416         adev->mode_info.mode_config_initialized = true;
 417         return 0;
 418 }
 419
 420 static int dce_virtual_sw_fini(void *handle)
 421 {
 422         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 423
 424         kfree(adev->mode_info.bios_hardcoded_edid);
 425
 426         drm_kms_helper_poll_fini(adev_to_drm(adev));
 427
 428         drm_mode_config_cleanup(adev_to_drm(adev));
 429         /* clear crtcs pointer to avoid dce irq finish routine access freed data */
 430         memset(adev->mode_info.crtcs, 0, sizeof(adev->mode_info.crtcs[0]) * AMDGPU_MAX_CRTCS);
 431         adev->mode_info.mode_config_initialized = false;
 432         return 0;
 433 }
 434
 435 static int dce_virtual_hw_init(void *handle)
 436 {
 437         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 438
 439         switch (adev->asic_type) {
 440 #ifdef CONFIG_DRM_AMDGPU_SI
 441         case CHIP_TAHITI:
 442         case CHIP_PITCAIRN:
 443         case CHIP_VERDE:
 444         case CHIP_OLAND:
 445                 dce_v6_0_disable_dce(adev);
 446                 break;
 447 #endif
 448 #ifdef CONFIG_DRM_AMDGPU_CIK
 449         case CHIP_BONAIRE:
 450         case CHIP_HAWAII:
 451         case CHIP_KAVERI:
 452         case CHIP_KABINI:
 453         case CHIP_MULLINS:
 454                 dce_v8_0_disable_dce(adev);
 455                 break;
 456 #endif
 457         case CHIP_FIJI:
 458         case CHIP_TONGA:
 459                 dce_v10_0_disable_dce(adev);
 460                 break;
 461         case CHIP_CARRIZO:
 462         case CHIP_STONEY:
 463         case CHIP_POLARIS10:
 464         case CHIP_POLARIS11:
 465         case CHIP_VEGAM:
 466                 dce_v11_0_disable_dce(adev);
 467                 break;
 468         case CHIP_TOPAZ:
 469 #ifdef CONFIG_DRM_AMDGPU_SI
 470         case CHIP_HAINAN:
 471 #endif
 472                 /* no DCE */
 473                 break;
 474         default:
 475                 break;
 476         }
 477         return 0;
 478 }
 479
 480 static int dce_virtual_hw_fini(void *handle)
 481 {
 482         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 483         int i = 0;
 484
 485         for (i = 0; i<adev->mode_info.num_crtc; i++)
 486                 if (adev->mode_info.crtcs[i])
 487                         hrtimer_cancel(&adev->mode_info.crtcs[i]->vblank_timer);
 488
 489         return 0;
 490 }
 491
 492 static int dce_virtual_suspend(void *handle)
 493 {
 494         return dce_virtual_hw_fini(handle);
 495 }
 496
 497 static int dce_virtual_resume(void *handle)
 498 {
 499         return dce_virtual_hw_init(handle);
 500 }
 501
 502 static bool dce_virtual_is_idle(void *handle)
 503 {
 504         return true;
 505 }
 506
 507 static int dce_virtual_wait_for_idle(void *handle)
 508 {
 509         return 0;
 510 }
 511
 512 static int dce_virtual_soft_reset(void *handle)
 513 {
 514         return 0;
 515 }
 516
 517 static int dce_virtual_set_clockgating_state(void *handle,
 518                                           enum amd_clockgating_state state)
 519 {
 520         return 0;
 521 }
 522
 523 static int dce_virtual_set_powergating_state(void *handle,
 524                                           enum amd_powergating_state state)
 525 {
 526         return 0;
 527 }
 528
 529 static const struct amd_ip_funcs dce_virtual_ip_funcs = {
 530         .name = "dce_virtual",
 531         .early_init = dce_virtual_early_init,
 532         .late_init = NULL,
 533         .sw_init = dce_virtual_sw_init,
 534         .sw_fini = dce_virtual_sw_fini,
 535         .hw_init = dce_virtual_hw_init,
 536         .hw_fini = dce_virtual_hw_fini,
 537         .suspend = dce_virtual_suspend,
 538         .resume = dce_virtual_resume,
 539         .is_idle = dce_virtual_is_idle,
 540         .wait_for_idle = dce_virtual_wait_for_idle,
 541         .soft_reset = dce_virtual_soft_reset,
 542         .set_clockgating_state = dce_virtual_set_clockgating_state,
 543         .set_powergating_state = dce_virtual_set_powergating_state,
 544 };
 545
 546 /* these are handled by the primary encoders */
 547 static void dce_virtual_encoder_prepare(struct drm_encoder *encoder)
 548 {
 549         return;
 550 }
 551
 552 static void dce_virtual_encoder_commit(struct drm_encoder *encoder)
 553 {
 554         return;
 555 }
 556
 557 static void
 558 dce_virtual_encoder_mode_set(struct drm_encoder *encoder,
 559                              struct drm_display_mode *mode,
 560                              struct drm_display_mode *adjusted_mode)
 561 {
 562         return;
 563 }
 564
 565 static void dce_virtual_encoder_disable(struct drm_encoder *encoder)
 566 {
 567         return;
 568 }
 569
 570 static void
 571 dce_virtual_encoder_dpms(struct drm_encoder *encoder, int mode)
 572 {
 573         return;
 574 }
 575
 576 static bool dce_virtual_encoder_mode_fixup(struct drm_encoder *encoder,
 577                                     const struct drm_display_mode *mode,
 578                                     struct drm_display_mode *adjusted_mode)
 579 {
 580         return true;
 581 }
 582
 583 static const struct drm_encoder_helper_funcs dce_virtual_encoder_helper_funcs = {
 584         .dpms = dce_virtual_encoder_dpms,
 585         .mode_fixup = dce_virtual_encoder_mode_fixup,
 586         .prepare = dce_virtual_encoder_prepare,
 587         .mode_set = dce_virtual_encoder_mode_set,
 588         .commit = dce_virtual_encoder_commit,
 589         .disable = dce_virtual_encoder_disable,
 590 };
 591
 592 static void dce_virtual_encoder_destroy(struct drm_encoder *encoder)
 593 {
 594         drm_encoder_cleanup(encoder);
 595         kfree(encoder);
 596 }
 597
 598 static const struct drm_encoder_funcs dce_virtual_encoder_funcs = {
 599         .destroy = dce_virtual_encoder_destroy,
 600 };
 601
 602 static int dce_virtual_connector_encoder_init(struct amdgpu_device *adev,
 603                                               int index)
 604 {
 605         struct drm_encoder *encoder;
 606         struct drm_connector *connector;
 607
 608         /* add a new encoder */
 609         encoder = kzalloc(sizeof(struct drm_encoder), GFP_KERNEL);
 610         if (!encoder)
 611                 return -ENOMEM;
 612         encoder->possible_crtcs = 1 << index;
 613         drm_encoder_init(adev_to_drm(adev), encoder, &dce_virtual_encoder_funcs,
 614                          DRM_MODE_ENCODER_VIRTUAL, NULL);
 615         drm_encoder_helper_add(encoder, &dce_virtual_encoder_helper_funcs);
 616
 617         connector = kzalloc(sizeof(struct drm_connector), GFP_KERNEL);
 618         if (!connector) {
 619                 kfree(encoder);
 620                 return -ENOMEM;
 621         }
 622
 623         /* add a new connector */
 624         drm_connector_init(adev_to_drm(adev), connector, &dce_virtual_connector_funcs,
 625                            DRM_MODE_CONNECTOR_VIRTUAL);
 626         drm_connector_helper_add(connector, &dce_virtual_connector_helper_funcs);
 627         connector->display_info.subpixel_order = SubPixelHorizontalRGB;
 628         connector->interlace_allowed = false;
 629         connector->doublescan_allowed = false;
 630
 631         /* link them */
 632         drm_connector_attach_encoder(connector, encoder);
 633
 634         return 0;
 635 }
 636
 637 static const struct amdgpu_display_funcs dce_virtual_display_funcs = {
 638         .bandwidth_update = &dce_virtual_bandwidth_update,
 639         .vblank_get_counter = &dce_virtual_vblank_get_counter,
 640         .backlight_set_level = NULL,
 641         .backlight_get_level = NULL,
 642         .hpd_sense = &dce_virtual_hpd_sense,
 643         .hpd_set_polarity = &dce_virtual_hpd_set_polarity,
 644         .hpd_get_gpio_reg = &dce_virtual_hpd_get_gpio_reg,
 645         .page_flip = &dce_virtual_page_flip,
 646         .page_flip_get_scanoutpos = &dce_virtual_crtc_get_scanoutpos,
 647         .add_encoder = NULL,
 648         .add_connector = NULL,
 649 };
 650
 651 static void dce_virtual_set_display_funcs(struct amdgpu_device *adev)
 652 {
 653         adev->mode_info.funcs = &dce_virtual_display_funcs;
 654 }
 655
 656 static int dce_virtual_pageflip(struct amdgpu_device *adev,
 657                                 unsigned crtc_id)
 658 {
 659         unsigned long flags;
 660         struct amdgpu_crtc *amdgpu_crtc;
 661         struct amdgpu_flip_work *works;
 662
 663         amdgpu_crtc = adev->mode_info.crtcs[crtc_id];
 664
 665         if (crtc_id >= adev->mode_info.num_crtc) {
 666                 DRM_ERROR("invalid pageflip crtc %d\n", crtc_id);
 667                 return -EINVAL;
 668         }
 669
 670         /* IRQ could occur when in initial stage */
 671         if (amdgpu_crtc == NULL)
 672                 return 0;
 673
 674         spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags);
 675         works = amdgpu_crtc->pflip_works;
 676         if (amdgpu_crtc->pflip_status != AMDGPU_FLIP_SUBMITTED) {
 677                 DRM_DEBUG_DRIVER("amdgpu_crtc->pflip_status = %d != "
 678                         "AMDGPU_FLIP_SUBMITTED(%d)\n",
 679                         amdgpu_crtc->pflip_status,
 680                         AMDGPU_FLIP_SUBMITTED);
 681                 spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags);
 682                 return 0;
 683         }
 684
 685         /* page flip completed. clean up */
 686         amdgpu_crtc->pflip_status = AMDGPU_FLIP_NONE;
 687         amdgpu_crtc->pflip_works = NULL;
 688
 689         /* wakeup usersapce */
 690         if (works->event)
 691                 drm_crtc_send_vblank_event(&amdgpu_crtc->base, works->event);
 692
 693         spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags);
 694
 695         drm_crtc_vblank_put(&amdgpu_crtc->base);
 696         amdgpu_bo_unref(&works->old_abo);
 697         kfree(works->shared);
 698         kfree(works);
 699
 700         return 0;
 701 }
 702
 703 static enum hrtimer_restart dce_virtual_vblank_timer_handle(struct hrtimer *vblank_timer)
 704 {
 705         struct amdgpu_crtc *amdgpu_crtc = container_of(vblank_timer,
 706                                                        struct amdgpu_crtc, vblank_timer);
 707         struct drm_device *ddev = amdgpu_crtc->base.dev;
 708         struct amdgpu_device *adev = drm_to_adev(ddev);
 709         struct amdgpu_irq_src *source = adev->irq.client[AMDGPU_IRQ_CLIENTID_LEGACY].sources
 710                 [VISLANDS30_IV_SRCID_SMU_DISP_TIMER2_TRIGGER];
 711         int irq_type = amdgpu_display_crtc_idx_to_irq_type(adev,
 712                                                 amdgpu_crtc->crtc_id);
 713
 714         if (amdgpu_irq_enabled(adev, source, irq_type)) {
 715                 drm_handle_vblank(ddev, amdgpu_crtc->crtc_id);
 716                 dce_virtual_pageflip(adev, amdgpu_crtc->crtc_id);
 717         }
 718         hrtimer_start(vblank_timer, DCE_VIRTUAL_VBLANK_PERIOD,
 719                       HRTIMER_MODE_REL);
 720
 721         return HRTIMER_NORESTART;
 722 }
 723
 724 static void dce_virtual_set_crtc_vblank_interrupt_state(struct amdgpu_device *adev,
 725                                                         int crtc,
 726                                                         enum amdgpu_interrupt_state state)
 727 {
 728         if (crtc >= adev->mode_info.num_crtc || !adev->mode_info.crtcs[crtc]) {
 729                 DRM_DEBUG("invalid crtc %d\n", crtc);
 730                 return;
 731         }
 732
 733         adev->mode_info.crtcs[crtc]->vsync_timer_enabled = state;
 734         DRM_DEBUG("[FM]set crtc %d vblank interrupt state %d\n", crtc, state);
 735 }
 736
 737
 738 static int dce_virtual_set_crtc_irq_state(struct amdgpu_device *adev,
 739                                           struct amdgpu_irq_src *source,
 740                                           unsigned type,
 741                                           enum amdgpu_interrupt_state state)
 742 {
 743         if (type > AMDGPU_CRTC_IRQ_VBLANK6)
 744                 return -EINVAL;
 745
 746         dce_virtual_set_crtc_vblank_interrupt_state(adev, type, state);
 747
 748         return 0;
 749 }
 750
 751 static const struct amdgpu_irq_src_funcs dce_virtual_crtc_irq_funcs = {
 752         .set = dce_virtual_set_crtc_irq_state,
 753         .process = NULL,
 754 };
 755
 756 static void dce_virtual_set_irq_funcs(struct amdgpu_device *adev)
 757 {
 758         adev->crtc_irq.num_types = AMDGPU_CRTC_IRQ_VBLANK6 + 1;
 759         adev->crtc_irq.funcs = &dce_virtual_crtc_irq_funcs;
 760 }
 761
 762 const struct amdgpu_ip_block_version dce_virtual_ip_block =
 763 {
 764         .type = AMD_IP_BLOCK_TYPE_DCE,
 765         .major = 1,
 766         .minor = 0,
 767         .rev = 0,
 768         .funcs = &dce_virtual_ip_funcs,
 769 };