2 * Copyright 2015 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
25 #include "amdgpu_pm.h"
26 #include "amdgpu_i2c.h"
28 #include "amdgpu_atombios.h"
29 #include "atombios_crtc.h"
30 #include "atombios_encoders.h"
31 #include "amdgpu_pll.h"
32 #include "amdgpu_connectors.h"
34 #include "bif/bif_3_0_d.h"
35 #include "bif/bif_3_0_sh_mask.h"
36 #include "oss/oss_1_0_d.h"
37 #include "oss/oss_1_0_sh_mask.h"
38 #include "gca/gfx_6_0_d.h"
39 #include "gca/gfx_6_0_sh_mask.h"
40 #include "gmc/gmc_6_0_d.h"
41 #include "gmc/gmc_6_0_sh_mask.h"
42 #include "dce/dce_6_0_d.h"
43 #include "dce/dce_6_0_sh_mask.h"
44 #include "gca/gfx_7_2_enum.h"
47 static void dce_v6_0_set_display_funcs(struct amdgpu_device *adev);
48 static void dce_v6_0_set_irq_funcs(struct amdgpu_device *adev);
50 static const u32 crtc_offsets[6] =
52 SI_CRTC0_REGISTER_OFFSET,
53 SI_CRTC1_REGISTER_OFFSET,
54 SI_CRTC2_REGISTER_OFFSET,
55 SI_CRTC3_REGISTER_OFFSET,
56 SI_CRTC4_REGISTER_OFFSET,
57 SI_CRTC5_REGISTER_OFFSET
60 static const u32 hpd_offsets[] =
62 mmDC_HPD1_INT_STATUS - mmDC_HPD1_INT_STATUS,
63 mmDC_HPD2_INT_STATUS - mmDC_HPD1_INT_STATUS,
64 mmDC_HPD3_INT_STATUS - mmDC_HPD1_INT_STATUS,
65 mmDC_HPD4_INT_STATUS - mmDC_HPD1_INT_STATUS,
66 mmDC_HPD5_INT_STATUS - mmDC_HPD1_INT_STATUS,
67 mmDC_HPD6_INT_STATUS - mmDC_HPD1_INT_STATUS,
70 static const uint32_t dig_offsets[] = {
71 SI_CRTC0_REGISTER_OFFSET,
72 SI_CRTC1_REGISTER_OFFSET,
73 SI_CRTC2_REGISTER_OFFSET,
74 SI_CRTC3_REGISTER_OFFSET,
75 SI_CRTC4_REGISTER_OFFSET,
76 SI_CRTC5_REGISTER_OFFSET,
77 (0x13830 - 0x7030) >> 2,
86 } interrupt_status_offsets[6] = { {
87 .reg = mmDISP_INTERRUPT_STATUS,
88 .vblank = DISP_INTERRUPT_STATUS__LB_D1_VBLANK_INTERRUPT_MASK,
89 .vline = DISP_INTERRUPT_STATUS__LB_D1_VLINE_INTERRUPT_MASK,
90 .hpd = DISP_INTERRUPT_STATUS__DC_HPD1_INTERRUPT_MASK
92 .reg = mmDISP_INTERRUPT_STATUS_CONTINUE,
93 .vblank = DISP_INTERRUPT_STATUS_CONTINUE__LB_D2_VBLANK_INTERRUPT_MASK,
94 .vline = DISP_INTERRUPT_STATUS_CONTINUE__LB_D2_VLINE_INTERRUPT_MASK,
95 .hpd = DISP_INTERRUPT_STATUS_CONTINUE__DC_HPD2_INTERRUPT_MASK
97 .reg = mmDISP_INTERRUPT_STATUS_CONTINUE2,
98 .vblank = DISP_INTERRUPT_STATUS_CONTINUE2__LB_D3_VBLANK_INTERRUPT_MASK,
99 .vline = DISP_INTERRUPT_STATUS_CONTINUE2__LB_D3_VLINE_INTERRUPT_MASK,
100 .hpd = DISP_INTERRUPT_STATUS_CONTINUE2__DC_HPD3_INTERRUPT_MASK
102 .reg = mmDISP_INTERRUPT_STATUS_CONTINUE3,
103 .vblank = DISP_INTERRUPT_STATUS_CONTINUE3__LB_D4_VBLANK_INTERRUPT_MASK,
104 .vline = DISP_INTERRUPT_STATUS_CONTINUE3__LB_D4_VLINE_INTERRUPT_MASK,
105 .hpd = DISP_INTERRUPT_STATUS_CONTINUE3__DC_HPD4_INTERRUPT_MASK
107 .reg = mmDISP_INTERRUPT_STATUS_CONTINUE4,
108 .vblank = DISP_INTERRUPT_STATUS_CONTINUE4__LB_D5_VBLANK_INTERRUPT_MASK,
109 .vline = DISP_INTERRUPT_STATUS_CONTINUE4__LB_D5_VLINE_INTERRUPT_MASK,
110 .hpd = DISP_INTERRUPT_STATUS_CONTINUE4__DC_HPD5_INTERRUPT_MASK
112 .reg = mmDISP_INTERRUPT_STATUS_CONTINUE5,
113 .vblank = DISP_INTERRUPT_STATUS_CONTINUE5__LB_D6_VBLANK_INTERRUPT_MASK,
114 .vline = DISP_INTERRUPT_STATUS_CONTINUE5__LB_D6_VLINE_INTERRUPT_MASK,
115 .hpd = DISP_INTERRUPT_STATUS_CONTINUE5__DC_HPD6_INTERRUPT_MASK
118 static u32 dce_v6_0_audio_endpt_rreg(struct amdgpu_device *adev,
119 u32 block_offset, u32 reg)
124 spin_lock_irqsave(&adev->audio_endpt_idx_lock, flags);
125 WREG32(mmAZALIA_F0_CODEC_ENDPOINT_INDEX + block_offset, reg);
126 r = RREG32(mmAZALIA_F0_CODEC_ENDPOINT_DATA + block_offset);
127 spin_unlock_irqrestore(&adev->audio_endpt_idx_lock, flags);
132 static void dce_v6_0_audio_endpt_wreg(struct amdgpu_device *adev,
133 u32 block_offset, u32 reg, u32 v)
137 spin_lock_irqsave(&adev->audio_endpt_idx_lock, flags);
138 WREG32(mmAZALIA_F0_CODEC_ENDPOINT_INDEX + block_offset,
139 reg | AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_WRITE_EN_MASK);
140 WREG32(mmAZALIA_F0_CODEC_ENDPOINT_DATA + block_offset, v);
141 spin_unlock_irqrestore(&adev->audio_endpt_idx_lock, flags);
144 static bool dce_v6_0_is_in_vblank(struct amdgpu_device *adev, int crtc)
146 if (RREG32(mmCRTC_STATUS + crtc_offsets[crtc]) & CRTC_STATUS__CRTC_V_BLANK_MASK)
152 static bool dce_v6_0_is_counter_moving(struct amdgpu_device *adev, int crtc)
156 pos1 = RREG32(mmCRTC_STATUS_POSITION + crtc_offsets[crtc]);
157 pos2 = RREG32(mmCRTC_STATUS_POSITION + crtc_offsets[crtc]);
166 * dce_v6_0_wait_for_vblank - vblank wait asic callback.
168 * @crtc: crtc to wait for vblank on
170 * Wait for vblank on the requested crtc (evergreen+).
172 static void dce_v6_0_vblank_wait(struct amdgpu_device *adev, int crtc)
176 if (crtc >= adev->mode_info.num_crtc)
179 if (!(RREG32(mmCRTC_CONTROL + crtc_offsets[crtc]) & CRTC_CONTROL__CRTC_MASTER_EN_MASK))
182 /* depending on when we hit vblank, we may be close to active; if so,
183 * wait for another frame.
185 while (dce_v6_0_is_in_vblank(adev, crtc)) {
188 if (!dce_v6_0_is_counter_moving(adev, crtc))
193 while (!dce_v6_0_is_in_vblank(adev, crtc)) {
196 if (!dce_v6_0_is_counter_moving(adev, crtc))
202 static u32 dce_v6_0_vblank_get_counter(struct amdgpu_device *adev, int crtc)
204 if (crtc >= adev->mode_info.num_crtc)
207 return RREG32(mmCRTC_STATUS_FRAME_COUNT + crtc_offsets[crtc]);
210 static void dce_v6_0_pageflip_interrupt_init(struct amdgpu_device *adev)
214 /* Enable pflip interrupts */
215 for (i = 0; i < adev->mode_info.num_crtc; i++)
216 amdgpu_irq_get(adev, &adev->pageflip_irq, i);
219 static void dce_v6_0_pageflip_interrupt_fini(struct amdgpu_device *adev)
223 /* Disable pflip interrupts */
224 for (i = 0; i < adev->mode_info.num_crtc; i++)
225 amdgpu_irq_put(adev, &adev->pageflip_irq, i);
229 * dce_v6_0_page_flip - pageflip callback.
231 * @adev: amdgpu_device pointer
232 * @crtc_id: crtc to cleanup pageflip on
233 * @crtc_base: new address of the crtc (GPU MC address)
235 * Does the actual pageflip (evergreen+).
236 * During vblank we take the crtc lock and wait for the update_pending
237 * bit to go high, when it does, we release the lock, and allow the
238 * double buffered update to take place.
239 * Returns the current update pending status.
241 static void dce_v6_0_page_flip(struct amdgpu_device *adev,
242 int crtc_id, u64 crtc_base, bool async)
244 struct amdgpu_crtc *amdgpu_crtc = adev->mode_info.crtcs[crtc_id];
246 /* flip at hsync for async, default is vsync */
247 WREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset, async ?
248 GRPH_FLIP_CONTROL__GRPH_SURFACE_UPDATE_H_RETRACE_EN_MASK : 0);
249 /* update the scanout addresses */
250 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,
251 upper_32_bits(crtc_base));
252 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,
256 RREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset);
259 static int dce_v6_0_crtc_get_scanoutpos(struct amdgpu_device *adev, int crtc,
260 u32 *vbl, u32 *position)
262 if ((crtc < 0) || (crtc >= adev->mode_info.num_crtc))
264 *vbl = RREG32(mmCRTC_V_BLANK_START_END + crtc_offsets[crtc]);
265 *position = RREG32(mmCRTC_STATUS_POSITION + crtc_offsets[crtc]);
272 * dce_v6_0_hpd_sense - hpd sense callback.
274 * @adev: amdgpu_device pointer
275 * @hpd: hpd (hotplug detect) pin
277 * Checks if a digital monitor is connected (evergreen+).
278 * Returns true if connected, false if not connected.
280 static bool dce_v6_0_hpd_sense(struct amdgpu_device *adev,
281 enum amdgpu_hpd_id hpd)
283 bool connected = false;
285 if (hpd >= adev->mode_info.num_hpd)
288 if (RREG32(mmDC_HPD1_INT_STATUS + hpd_offsets[hpd]) & DC_HPD1_INT_STATUS__DC_HPD1_SENSE_MASK)
295 * dce_v6_0_hpd_set_polarity - hpd set polarity callback.
297 * @adev: amdgpu_device pointer
298 * @hpd: hpd (hotplug detect) pin
300 * Set the polarity of the hpd pin (evergreen+).
302 static void dce_v6_0_hpd_set_polarity(struct amdgpu_device *adev,
303 enum amdgpu_hpd_id hpd)
306 bool connected = dce_v6_0_hpd_sense(adev, hpd);
308 if (hpd >= adev->mode_info.num_hpd)
311 tmp = RREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[hpd]);
313 tmp &= ~DC_HPD1_INT_CONTROL__DC_HPD1_INT_POLARITY_MASK;
315 tmp |= DC_HPD1_INT_CONTROL__DC_HPD1_INT_POLARITY_MASK;
316 WREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[hpd], tmp);
320 * dce_v6_0_hpd_init - hpd setup callback.
322 * @adev: amdgpu_device pointer
324 * Setup the hpd pins used by the card (evergreen+).
325 * Enable the pin, set the polarity, and enable the hpd interrupts.
327 static void dce_v6_0_hpd_init(struct amdgpu_device *adev)
329 struct drm_device *dev = adev->ddev;
330 struct drm_connector *connector;
333 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
334 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
336 if (amdgpu_connector->hpd.hpd >= adev->mode_info.num_hpd)
339 tmp = RREG32(mmDC_HPD1_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd]);
340 tmp |= DC_HPD1_CONTROL__DC_HPD1_EN_MASK;
341 WREG32(mmDC_HPD1_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd], tmp);
343 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP ||
344 connector->connector_type == DRM_MODE_CONNECTOR_LVDS) {
345 /* don't try to enable hpd on eDP or LVDS avoid breaking the
346 * aux dp channel on imac and help (but not completely fix)
347 * https://bugzilla.redhat.com/show_bug.cgi?id=726143
348 * also avoid interrupt storms during dpms.
350 tmp = RREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd]);
351 tmp &= ~DC_HPD1_INT_CONTROL__DC_HPD1_INT_EN_MASK;
352 WREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd], tmp);
356 dce_v6_0_hpd_set_polarity(adev, amdgpu_connector->hpd.hpd);
357 amdgpu_irq_get(adev, &adev->hpd_irq, amdgpu_connector->hpd.hpd);
363 * dce_v6_0_hpd_fini - hpd tear down callback.
365 * @adev: amdgpu_device pointer
367 * Tear down the hpd pins used by the card (evergreen+).
368 * Disable the hpd interrupts.
370 static void dce_v6_0_hpd_fini(struct amdgpu_device *adev)
372 struct drm_device *dev = adev->ddev;
373 struct drm_connector *connector;
376 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
377 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
379 if (amdgpu_connector->hpd.hpd >= adev->mode_info.num_hpd)
382 tmp = RREG32(mmDC_HPD1_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd]);
383 tmp &= ~DC_HPD1_CONTROL__DC_HPD1_EN_MASK;
384 WREG32(mmDC_HPD1_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd], 0);
386 amdgpu_irq_put(adev, &adev->hpd_irq, amdgpu_connector->hpd.hpd);
390 static u32 dce_v6_0_hpd_get_gpio_reg(struct amdgpu_device *adev)
392 return mmDC_GPIO_HPD_A;
395 static u32 evergreen_get_vblank_counter(struct amdgpu_device* adev, int crtc)
397 if (crtc >= adev->mode_info.num_crtc)
400 return RREG32(mmCRTC_STATUS_FRAME_COUNT + crtc_offsets[crtc]);
403 static void dce_v6_0_stop_mc_access(struct amdgpu_device *adev,
404 struct amdgpu_mode_mc_save *save)
406 u32 crtc_enabled, tmp, frame_count;
409 save->vga_render_control = RREG32(mmVGA_RENDER_CONTROL);
410 save->vga_hdp_control = RREG32(mmVGA_HDP_CONTROL);
412 /* disable VGA render */
413 WREG32(mmVGA_RENDER_CONTROL, 0);
415 /* blank the display controllers */
416 for (i = 0; i < adev->mode_info.num_crtc; i++) {
417 crtc_enabled = RREG32(mmCRTC_CONTROL + crtc_offsets[i]) & CRTC_CONTROL__CRTC_MASTER_EN_MASK;
419 save->crtc_enabled[i] = true;
420 tmp = RREG32(mmCRTC_BLANK_CONTROL + crtc_offsets[i]);
422 if (!(tmp & CRTC_BLANK_CONTROL__CRTC_BLANK_DATA_EN_MASK)) {
423 dce_v6_0_vblank_wait(adev, i);
424 WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 1);
425 tmp |= CRTC_BLANK_CONTROL__CRTC_BLANK_DATA_EN_MASK;
426 WREG32(mmCRTC_BLANK_CONTROL + crtc_offsets[i], tmp);
427 WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 0);
429 /* wait for the next frame */
430 frame_count = evergreen_get_vblank_counter(adev, i);
431 for (j = 0; j < adev->usec_timeout; j++) {
432 if (evergreen_get_vblank_counter(adev, i) != frame_count)
437 /* XXX this is a hack to avoid strange behavior with EFI on certain systems */
438 WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 1);
439 tmp = RREG32(mmCRTC_CONTROL + crtc_offsets[i]);
440 tmp &= ~CRTC_CONTROL__CRTC_MASTER_EN_MASK;
441 WREG32(mmCRTC_CONTROL + crtc_offsets[i], tmp);
442 WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 0);
443 save->crtc_enabled[i] = false;
446 save->crtc_enabled[i] = false;
451 static void dce_v6_0_resume_mc_access(struct amdgpu_device *adev,
452 struct amdgpu_mode_mc_save *save)
457 /* update crtc base addresses */
458 for (i = 0; i < adev->mode_info.num_crtc; i++) {
459 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + crtc_offsets[i],
460 upper_32_bits(adev->mc.vram_start));
461 WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS_HIGH + crtc_offsets[i],
462 upper_32_bits(adev->mc.vram_start));
463 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + crtc_offsets[i],
464 (u32)adev->mc.vram_start);
465 WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS + crtc_offsets[i],
466 (u32)adev->mc.vram_start);
469 WREG32(mmVGA_MEMORY_BASE_ADDRESS_HIGH, upper_32_bits(adev->mc.vram_start));
470 WREG32(mmVGA_MEMORY_BASE_ADDRESS, (u32)adev->mc.vram_start);
472 /* unlock regs and wait for update */
473 for (i = 0; i < adev->mode_info.num_crtc; i++) {
474 if (save->crtc_enabled[i]) {
475 tmp = RREG32(mmMASTER_UPDATE_MODE + crtc_offsets[i]);
476 if ((tmp & 0x7) != 0) {
478 WREG32(mmMASTER_UPDATE_MODE + crtc_offsets[i], tmp);
480 tmp = RREG32(mmGRPH_UPDATE + crtc_offsets[i]);
481 if (tmp & GRPH_UPDATE__GRPH_UPDATE_LOCK_MASK) {
482 tmp &= ~GRPH_UPDATE__GRPH_UPDATE_LOCK_MASK;
483 WREG32(mmGRPH_UPDATE + crtc_offsets[i], tmp);
485 tmp = RREG32(mmMASTER_UPDATE_LOCK + crtc_offsets[i]);
488 WREG32(mmMASTER_UPDATE_LOCK + crtc_offsets[i], tmp);
490 for (j = 0; j < adev->usec_timeout; j++) {
491 tmp = RREG32(mmGRPH_UPDATE + crtc_offsets[i]);
492 if ((tmp & GRPH_UPDATE__GRPH_SURFACE_UPDATE_PENDING_MASK) == 0)
499 /* Unlock vga access */
500 WREG32(mmVGA_HDP_CONTROL, save->vga_hdp_control);
502 WREG32(mmVGA_RENDER_CONTROL, save->vga_render_control);
506 static void dce_v6_0_set_vga_render_state(struct amdgpu_device *adev,
510 WREG32(mmVGA_RENDER_CONTROL,
511 RREG32(mmVGA_RENDER_CONTROL) & VGA_VSTATUS_CNTL);
515 static int dce_v6_0_get_num_crtc(struct amdgpu_device *adev)
517 switch (adev->asic_type) {
529 void dce_v6_0_disable_dce(struct amdgpu_device *adev)
531 /*Disable VGA render and enabled crtc, if has DCE engine*/
532 if (amdgpu_atombios_has_dce_engine_info(adev)) {
536 dce_v6_0_set_vga_render_state(adev, false);
539 for (i = 0; i < dce_v6_0_get_num_crtc(adev); i++) {
540 crtc_enabled = RREG32(mmCRTC_CONTROL + crtc_offsets[i]) &
541 CRTC_CONTROL__CRTC_MASTER_EN_MASK;
543 WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 1);
544 tmp = RREG32(mmCRTC_CONTROL + crtc_offsets[i]);
545 tmp &= ~CRTC_CONTROL__CRTC_MASTER_EN_MASK;
546 WREG32(mmCRTC_CONTROL + crtc_offsets[i], tmp);
547 WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 0);
553 static void dce_v6_0_program_fmt(struct drm_encoder *encoder)
556 struct drm_device *dev = encoder->dev;
557 struct amdgpu_device *adev = dev->dev_private;
558 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
559 struct drm_connector *connector = amdgpu_get_connector_for_encoder(encoder);
560 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(encoder->crtc);
563 enum amdgpu_connector_dither dither = AMDGPU_FMT_DITHER_DISABLE;
566 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
567 bpc = amdgpu_connector_get_monitor_bpc(connector);
568 dither = amdgpu_connector->dither;
571 /* LVDS FMT is set up by atom */
572 if (amdgpu_encoder->devices & ATOM_DEVICE_LCD_SUPPORT)
581 if (dither == AMDGPU_FMT_DITHER_ENABLE)
582 /* XXX sort out optimal dither settings */
583 tmp |= (FMT_BIT_DEPTH_CONTROL__FMT_FRAME_RANDOM_ENABLE_MASK |
584 FMT_BIT_DEPTH_CONTROL__FMT_HIGHPASS_RANDOM_ENABLE_MASK |
585 FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_EN_MASK);
587 tmp |= FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_EN_MASK;
590 if (dither == AMDGPU_FMT_DITHER_ENABLE)
591 /* XXX sort out optimal dither settings */
592 tmp |= (FMT_BIT_DEPTH_CONTROL__FMT_FRAME_RANDOM_ENABLE_MASK |
593 FMT_BIT_DEPTH_CONTROL__FMT_HIGHPASS_RANDOM_ENABLE_MASK |
594 FMT_BIT_DEPTH_CONTROL__FMT_RGB_RANDOM_ENABLE_MASK |
595 FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_EN_MASK |
596 FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_DEPTH_MASK);
598 tmp |= (FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_EN_MASK |
599 FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_DEPTH_MASK);
607 WREG32(mmFMT_BIT_DEPTH_CONTROL + amdgpu_crtc->crtc_offset, tmp);
611 * cik_get_number_of_dram_channels - get the number of dram channels
613 * @adev: amdgpu_device pointer
615 * Look up the number of video ram channels (CIK).
616 * Used for display watermark bandwidth calculations
617 * Returns the number of dram channels
619 static u32 si_get_number_of_dram_channels(struct amdgpu_device *adev)
621 u32 tmp = RREG32(mmMC_SHARED_CHMAP);
623 switch ((tmp & MC_SHARED_CHMAP__NOOFCHAN_MASK) >> MC_SHARED_CHMAP__NOOFCHAN__SHIFT) {
646 struct dce6_wm_params {
647 u32 dram_channels; /* number of dram channels */
648 u32 yclk; /* bandwidth per dram data pin in kHz */
649 u32 sclk; /* engine clock in kHz */
650 u32 disp_clk; /* display clock in kHz */
651 u32 src_width; /* viewport width */
652 u32 active_time; /* active display time in ns */
653 u32 blank_time; /* blank time in ns */
654 bool interlaced; /* mode is interlaced */
655 fixed20_12 vsc; /* vertical scale ratio */
656 u32 num_heads; /* number of active crtcs */
657 u32 bytes_per_pixel; /* bytes per pixel display + overlay */
658 u32 lb_size; /* line buffer allocated to pipe */
659 u32 vtaps; /* vertical scaler taps */
663 * dce_v6_0_dram_bandwidth - get the dram bandwidth
665 * @wm: watermark calculation data
667 * Calculate the raw dram bandwidth (CIK).
668 * Used for display watermark bandwidth calculations
669 * Returns the dram bandwidth in MBytes/s
671 static u32 dce_v6_0_dram_bandwidth(struct dce6_wm_params *wm)
673 /* Calculate raw DRAM Bandwidth */
674 fixed20_12 dram_efficiency; /* 0.7 */
675 fixed20_12 yclk, dram_channels, bandwidth;
678 a.full = dfixed_const(1000);
679 yclk.full = dfixed_const(wm->yclk);
680 yclk.full = dfixed_div(yclk, a);
681 dram_channels.full = dfixed_const(wm->dram_channels * 4);
682 a.full = dfixed_const(10);
683 dram_efficiency.full = dfixed_const(7);
684 dram_efficiency.full = dfixed_div(dram_efficiency, a);
685 bandwidth.full = dfixed_mul(dram_channels, yclk);
686 bandwidth.full = dfixed_mul(bandwidth, dram_efficiency);
688 return dfixed_trunc(bandwidth);
692 * dce_v6_0_dram_bandwidth_for_display - get the dram bandwidth for display
694 * @wm: watermark calculation data
696 * Calculate the dram bandwidth used for display (CIK).
697 * Used for display watermark bandwidth calculations
698 * Returns the dram bandwidth for display in MBytes/s
700 static u32 dce_v6_0_dram_bandwidth_for_display(struct dce6_wm_params *wm)
702 /* Calculate DRAM Bandwidth and the part allocated to display. */
703 fixed20_12 disp_dram_allocation; /* 0.3 to 0.7 */
704 fixed20_12 yclk, dram_channels, bandwidth;
707 a.full = dfixed_const(1000);
708 yclk.full = dfixed_const(wm->yclk);
709 yclk.full = dfixed_div(yclk, a);
710 dram_channels.full = dfixed_const(wm->dram_channels * 4);
711 a.full = dfixed_const(10);
712 disp_dram_allocation.full = dfixed_const(3); /* XXX worse case value 0.3 */
713 disp_dram_allocation.full = dfixed_div(disp_dram_allocation, a);
714 bandwidth.full = dfixed_mul(dram_channels, yclk);
715 bandwidth.full = dfixed_mul(bandwidth, disp_dram_allocation);
717 return dfixed_trunc(bandwidth);
721 * dce_v6_0_data_return_bandwidth - get the data return bandwidth
723 * @wm: watermark calculation data
725 * Calculate the data return bandwidth used for display (CIK).
726 * Used for display watermark bandwidth calculations
727 * Returns the data return bandwidth in MBytes/s
729 static u32 dce_v6_0_data_return_bandwidth(struct dce6_wm_params *wm)
731 /* Calculate the display Data return Bandwidth */
732 fixed20_12 return_efficiency; /* 0.8 */
733 fixed20_12 sclk, bandwidth;
736 a.full = dfixed_const(1000);
737 sclk.full = dfixed_const(wm->sclk);
738 sclk.full = dfixed_div(sclk, a);
739 a.full = dfixed_const(10);
740 return_efficiency.full = dfixed_const(8);
741 return_efficiency.full = dfixed_div(return_efficiency, a);
742 a.full = dfixed_const(32);
743 bandwidth.full = dfixed_mul(a, sclk);
744 bandwidth.full = dfixed_mul(bandwidth, return_efficiency);
746 return dfixed_trunc(bandwidth);
750 * dce_v6_0_dmif_request_bandwidth - get the dmif bandwidth
752 * @wm: watermark calculation data
754 * Calculate the dmif bandwidth used for display (CIK).
755 * Used for display watermark bandwidth calculations
756 * Returns the dmif bandwidth in MBytes/s
758 static u32 dce_v6_0_dmif_request_bandwidth(struct dce6_wm_params *wm)
760 /* Calculate the DMIF Request Bandwidth */
761 fixed20_12 disp_clk_request_efficiency; /* 0.8 */
762 fixed20_12 disp_clk, bandwidth;
765 a.full = dfixed_const(1000);
766 disp_clk.full = dfixed_const(wm->disp_clk);
767 disp_clk.full = dfixed_div(disp_clk, a);
768 a.full = dfixed_const(32);
769 b.full = dfixed_mul(a, disp_clk);
771 a.full = dfixed_const(10);
772 disp_clk_request_efficiency.full = dfixed_const(8);
773 disp_clk_request_efficiency.full = dfixed_div(disp_clk_request_efficiency, a);
775 bandwidth.full = dfixed_mul(b, disp_clk_request_efficiency);
777 return dfixed_trunc(bandwidth);
781 * dce_v6_0_available_bandwidth - get the min available bandwidth
783 * @wm: watermark calculation data
785 * Calculate the min available bandwidth used for display (CIK).
786 * Used for display watermark bandwidth calculations
787 * Returns the min available bandwidth in MBytes/s
789 static u32 dce_v6_0_available_bandwidth(struct dce6_wm_params *wm)
791 /* Calculate the Available bandwidth. Display can use this temporarily but not in average. */
792 u32 dram_bandwidth = dce_v6_0_dram_bandwidth(wm);
793 u32 data_return_bandwidth = dce_v6_0_data_return_bandwidth(wm);
794 u32 dmif_req_bandwidth = dce_v6_0_dmif_request_bandwidth(wm);
796 return min(dram_bandwidth, min(data_return_bandwidth, dmif_req_bandwidth));
800 * dce_v6_0_average_bandwidth - get the average available bandwidth
802 * @wm: watermark calculation data
804 * Calculate the average available bandwidth used for display (CIK).
805 * Used for display watermark bandwidth calculations
806 * Returns the average available bandwidth in MBytes/s
808 static u32 dce_v6_0_average_bandwidth(struct dce6_wm_params *wm)
810 /* Calculate the display mode Average Bandwidth
811 * DisplayMode should contain the source and destination dimensions,
815 fixed20_12 line_time;
816 fixed20_12 src_width;
817 fixed20_12 bandwidth;
820 a.full = dfixed_const(1000);
821 line_time.full = dfixed_const(wm->active_time + wm->blank_time);
822 line_time.full = dfixed_div(line_time, a);
823 bpp.full = dfixed_const(wm->bytes_per_pixel);
824 src_width.full = dfixed_const(wm->src_width);
825 bandwidth.full = dfixed_mul(src_width, bpp);
826 bandwidth.full = dfixed_mul(bandwidth, wm->vsc);
827 bandwidth.full = dfixed_div(bandwidth, line_time);
829 return dfixed_trunc(bandwidth);
833 * dce_v6_0_latency_watermark - get the latency watermark
835 * @wm: watermark calculation data
837 * Calculate the latency watermark (CIK).
838 * Used for display watermark bandwidth calculations
839 * Returns the latency watermark in ns
841 static u32 dce_v6_0_latency_watermark(struct dce6_wm_params *wm)
843 /* First calculate the latency in ns */
844 u32 mc_latency = 2000; /* 2000 ns. */
845 u32 available_bandwidth = dce_v6_0_available_bandwidth(wm);
846 u32 worst_chunk_return_time = (512 * 8 * 1000) / available_bandwidth;
847 u32 cursor_line_pair_return_time = (128 * 4 * 1000) / available_bandwidth;
848 u32 dc_latency = 40000000 / wm->disp_clk; /* dc pipe latency */
849 u32 other_heads_data_return_time = ((wm->num_heads + 1) * worst_chunk_return_time) +
850 (wm->num_heads * cursor_line_pair_return_time);
851 u32 latency = mc_latency + other_heads_data_return_time + dc_latency;
852 u32 max_src_lines_per_dst_line, lb_fill_bw, line_fill_time;
853 u32 tmp, dmif_size = 12288;
856 if (wm->num_heads == 0)
859 a.full = dfixed_const(2);
860 b.full = dfixed_const(1);
861 if ((wm->vsc.full > a.full) ||
862 ((wm->vsc.full > b.full) && (wm->vtaps >= 3)) ||
864 ((wm->vsc.full >= a.full) && wm->interlaced))
865 max_src_lines_per_dst_line = 4;
867 max_src_lines_per_dst_line = 2;
869 a.full = dfixed_const(available_bandwidth);
870 b.full = dfixed_const(wm->num_heads);
871 a.full = dfixed_div(a, b);
872 tmp = div_u64((u64) dmif_size * (u64) wm->disp_clk, mc_latency + 512);
873 tmp = min(dfixed_trunc(a), tmp);
875 lb_fill_bw = min(tmp, wm->disp_clk * wm->bytes_per_pixel / 1000);
877 a.full = dfixed_const(max_src_lines_per_dst_line * wm->src_width * wm->bytes_per_pixel);
878 b.full = dfixed_const(1000);
879 c.full = dfixed_const(lb_fill_bw);
880 b.full = dfixed_div(c, b);
881 a.full = dfixed_div(a, b);
882 line_fill_time = dfixed_trunc(a);
884 if (line_fill_time < wm->active_time)
887 return latency + (line_fill_time - wm->active_time);
892 * dce_v6_0_average_bandwidth_vs_dram_bandwidth_for_display - check
893 * average and available dram bandwidth
895 * @wm: watermark calculation data
897 * Check if the display average bandwidth fits in the display
898 * dram bandwidth (CIK).
899 * Used for display watermark bandwidth calculations
900 * Returns true if the display fits, false if not.
902 static bool dce_v6_0_average_bandwidth_vs_dram_bandwidth_for_display(struct dce6_wm_params *wm)
904 if (dce_v6_0_average_bandwidth(wm) <=
905 (dce_v6_0_dram_bandwidth_for_display(wm) / wm->num_heads))
912 * dce_v6_0_average_bandwidth_vs_available_bandwidth - check
913 * average and available bandwidth
915 * @wm: watermark calculation data
917 * Check if the display average bandwidth fits in the display
918 * available bandwidth (CIK).
919 * Used for display watermark bandwidth calculations
920 * Returns true if the display fits, false if not.
922 static bool dce_v6_0_average_bandwidth_vs_available_bandwidth(struct dce6_wm_params *wm)
924 if (dce_v6_0_average_bandwidth(wm) <=
925 (dce_v6_0_available_bandwidth(wm) / wm->num_heads))
932 * dce_v6_0_check_latency_hiding - check latency hiding
934 * @wm: watermark calculation data
936 * Check latency hiding (CIK).
937 * Used for display watermark bandwidth calculations
938 * Returns true if the display fits, false if not.
940 static bool dce_v6_0_check_latency_hiding(struct dce6_wm_params *wm)
942 u32 lb_partitions = wm->lb_size / wm->src_width;
943 u32 line_time = wm->active_time + wm->blank_time;
944 u32 latency_tolerant_lines;
948 a.full = dfixed_const(1);
949 if (wm->vsc.full > a.full)
950 latency_tolerant_lines = 1;
952 if (lb_partitions <= (wm->vtaps + 1))
953 latency_tolerant_lines = 1;
955 latency_tolerant_lines = 2;
958 latency_hiding = (latency_tolerant_lines * line_time + wm->blank_time);
960 if (dce_v6_0_latency_watermark(wm) <= latency_hiding)
967 * dce_v6_0_program_watermarks - program display watermarks
969 * @adev: amdgpu_device pointer
970 * @amdgpu_crtc: the selected display controller
971 * @lb_size: line buffer size
972 * @num_heads: number of display controllers in use
974 * Calculate and program the display watermarks for the
975 * selected display controller (CIK).
977 static void dce_v6_0_program_watermarks(struct amdgpu_device *adev,
978 struct amdgpu_crtc *amdgpu_crtc,
979 u32 lb_size, u32 num_heads)
981 struct drm_display_mode *mode = &amdgpu_crtc->base.mode;
982 struct dce6_wm_params wm_low, wm_high;
986 u32 latency_watermark_a = 0, latency_watermark_b = 0;
987 u32 priority_a_mark = 0, priority_b_mark = 0;
988 u32 priority_a_cnt = PRIORITY_OFF;
989 u32 priority_b_cnt = PRIORITY_OFF;
990 u32 tmp, arb_control3, lb_vblank_lead_lines = 0;
993 if (amdgpu_crtc->base.enabled && num_heads && mode) {
994 active_time = (u32) div_u64((u64)mode->crtc_hdisplay * 1000000,
996 line_time = (u32) div_u64((u64)mode->crtc_htotal * 1000000,
998 line_time = min(line_time, (u32)65535);
1002 dram_channels = si_get_number_of_dram_channels(adev);
1004 /* watermark for high clocks */
1005 if (adev->pm.dpm_enabled) {
1007 amdgpu_dpm_get_mclk(adev, false) * 10;
1009 amdgpu_dpm_get_sclk(adev, false) * 10;
1011 wm_high.yclk = adev->pm.current_mclk * 10;
1012 wm_high.sclk = adev->pm.current_sclk * 10;
1015 wm_high.disp_clk = mode->clock;
1016 wm_high.src_width = mode->crtc_hdisplay;
1017 wm_high.active_time = active_time;
1018 wm_high.blank_time = line_time - wm_high.active_time;
1019 wm_high.interlaced = false;
1020 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
1021 wm_high.interlaced = true;
1022 wm_high.vsc = amdgpu_crtc->vsc;
1024 if (amdgpu_crtc->rmx_type != RMX_OFF)
1026 wm_high.bytes_per_pixel = 4; /* XXX: get this from fb config */
1027 wm_high.lb_size = lb_size;
1028 wm_high.dram_channels = dram_channels;
1029 wm_high.num_heads = num_heads;
1031 if (adev->pm.dpm_enabled) {
1032 /* watermark for low clocks */
1034 amdgpu_dpm_get_mclk(adev, true) * 10;
1036 amdgpu_dpm_get_sclk(adev, true) * 10;
1038 wm_low.yclk = adev->pm.current_mclk * 10;
1039 wm_low.sclk = adev->pm.current_sclk * 10;
1042 wm_low.disp_clk = mode->clock;
1043 wm_low.src_width = mode->crtc_hdisplay;
1044 wm_low.active_time = active_time;
1045 wm_low.blank_time = line_time - wm_low.active_time;
1046 wm_low.interlaced = false;
1047 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
1048 wm_low.interlaced = true;
1049 wm_low.vsc = amdgpu_crtc->vsc;
1051 if (amdgpu_crtc->rmx_type != RMX_OFF)
1053 wm_low.bytes_per_pixel = 4; /* XXX: get this from fb config */
1054 wm_low.lb_size = lb_size;
1055 wm_low.dram_channels = dram_channels;
1056 wm_low.num_heads = num_heads;
1058 /* set for high clocks */
1059 latency_watermark_a = min(dce_v6_0_latency_watermark(&wm_high), (u32)65535);
1060 /* set for low clocks */
1061 latency_watermark_b = min(dce_v6_0_latency_watermark(&wm_low), (u32)65535);
1063 /* possibly force display priority to high */
1064 /* should really do this at mode validation time... */
1065 if (!dce_v6_0_average_bandwidth_vs_dram_bandwidth_for_display(&wm_high) ||
1066 !dce_v6_0_average_bandwidth_vs_available_bandwidth(&wm_high) ||
1067 !dce_v6_0_check_latency_hiding(&wm_high) ||
1068 (adev->mode_info.disp_priority == 2)) {
1069 DRM_DEBUG_KMS("force priority to high\n");
1070 priority_a_cnt |= PRIORITY_ALWAYS_ON;
1071 priority_b_cnt |= PRIORITY_ALWAYS_ON;
1073 if (!dce_v6_0_average_bandwidth_vs_dram_bandwidth_for_display(&wm_low) ||
1074 !dce_v6_0_average_bandwidth_vs_available_bandwidth(&wm_low) ||
1075 !dce_v6_0_check_latency_hiding(&wm_low) ||
1076 (adev->mode_info.disp_priority == 2)) {
1077 DRM_DEBUG_KMS("force priority to high\n");
1078 priority_a_cnt |= PRIORITY_ALWAYS_ON;
1079 priority_b_cnt |= PRIORITY_ALWAYS_ON;
1082 a.full = dfixed_const(1000);
1083 b.full = dfixed_const(mode->clock);
1084 b.full = dfixed_div(b, a);
1085 c.full = dfixed_const(latency_watermark_a);
1086 c.full = dfixed_mul(c, b);
1087 c.full = dfixed_mul(c, amdgpu_crtc->hsc);
1088 c.full = dfixed_div(c, a);
1089 a.full = dfixed_const(16);
1090 c.full = dfixed_div(c, a);
1091 priority_a_mark = dfixed_trunc(c);
1092 priority_a_cnt |= priority_a_mark & PRIORITY_MARK_MASK;
1094 a.full = dfixed_const(1000);
1095 b.full = dfixed_const(mode->clock);
1096 b.full = dfixed_div(b, a);
1097 c.full = dfixed_const(latency_watermark_b);
1098 c.full = dfixed_mul(c, b);
1099 c.full = dfixed_mul(c, amdgpu_crtc->hsc);
1100 c.full = dfixed_div(c, a);
1101 a.full = dfixed_const(16);
1102 c.full = dfixed_div(c, a);
1103 priority_b_mark = dfixed_trunc(c);
1104 priority_b_cnt |= priority_b_mark & PRIORITY_MARK_MASK;
1106 lb_vblank_lead_lines = DIV_ROUND_UP(lb_size, mode->crtc_hdisplay);
1110 arb_control3 = RREG32(mmDPG_PIPE_ARBITRATION_CONTROL3 + amdgpu_crtc->crtc_offset);
1112 tmp &= ~LATENCY_WATERMARK_MASK(3);
1113 tmp |= LATENCY_WATERMARK_MASK(1);
1114 WREG32(mmDPG_PIPE_ARBITRATION_CONTROL3 + amdgpu_crtc->crtc_offset, tmp);
1115 WREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset,
1116 ((latency_watermark_a << DPG_PIPE_URGENCY_CONTROL__URGENCY_LOW_WATERMARK__SHIFT) |
1117 (line_time << DPG_PIPE_URGENCY_CONTROL__URGENCY_HIGH_WATERMARK__SHIFT)));
1119 tmp = RREG32(mmDPG_PIPE_ARBITRATION_CONTROL3 + amdgpu_crtc->crtc_offset);
1120 tmp &= ~LATENCY_WATERMARK_MASK(3);
1121 tmp |= LATENCY_WATERMARK_MASK(2);
1122 WREG32(mmDPG_PIPE_ARBITRATION_CONTROL3 + amdgpu_crtc->crtc_offset, tmp);
1123 WREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset,
1124 ((latency_watermark_b << DPG_PIPE_URGENCY_CONTROL__URGENCY_LOW_WATERMARK__SHIFT) |
1125 (line_time << DPG_PIPE_URGENCY_CONTROL__URGENCY_HIGH_WATERMARK__SHIFT)));
1126 /* restore original selection */
1127 WREG32(mmDPG_PIPE_ARBITRATION_CONTROL3 + amdgpu_crtc->crtc_offset, arb_control3);
1129 /* write the priority marks */
1130 WREG32(mmPRIORITY_A_CNT + amdgpu_crtc->crtc_offset, priority_a_cnt);
1131 WREG32(mmPRIORITY_B_CNT + amdgpu_crtc->crtc_offset, priority_b_cnt);
1133 /* save values for DPM */
1134 amdgpu_crtc->line_time = line_time;
1135 amdgpu_crtc->wm_high = latency_watermark_a;
1137 /* Save number of lines the linebuffer leads before the scanout */
1138 amdgpu_crtc->lb_vblank_lead_lines = lb_vblank_lead_lines;
1141 /* watermark setup */
1142 static u32 dce_v6_0_line_buffer_adjust(struct amdgpu_device *adev,
1143 struct amdgpu_crtc *amdgpu_crtc,
1144 struct drm_display_mode *mode,
1145 struct drm_display_mode *other_mode)
1147 u32 tmp, buffer_alloc, i;
1148 u32 pipe_offset = amdgpu_crtc->crtc_id * 0x8;
1151 * There are 3 line buffers, each one shared by 2 display controllers.
1152 * mmDC_LB_MEMORY_SPLIT controls how that line buffer is shared between
1153 * the display controllers. The paritioning is done via one of four
1154 * preset allocations specified in bits 21:20:
1156 * 2 - whole lb, other crtc must be disabled
1158 /* this can get tricky if we have two large displays on a paired group
1159 * of crtcs. Ideally for multiple large displays we'd assign them to
1160 * non-linked crtcs for maximum line buffer allocation.
1162 if (amdgpu_crtc->base.enabled && mode) {
1167 tmp = 2; /* whole */
1175 WREG32(mmDC_LB_MEMORY_SPLIT + amdgpu_crtc->crtc_offset,
1176 DC_LB_MEMORY_CONFIG(tmp));
1178 WREG32(mmPIPE0_DMIF_BUFFER_CONTROL + pipe_offset,
1179 (buffer_alloc << PIPE0_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATED__SHIFT));
1180 for (i = 0; i < adev->usec_timeout; i++) {
1181 if (RREG32(mmPIPE0_DMIF_BUFFER_CONTROL + pipe_offset) &
1182 PIPE0_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATION_COMPLETED_MASK)
1187 if (amdgpu_crtc->base.enabled && mode) {
1197 /* controller not enabled, so no lb used */
1204 * dce_v6_0_bandwidth_update - program display watermarks
1206 * @adev: amdgpu_device pointer
1208 * Calculate and program the display watermarks and line
1209 * buffer allocation (CIK).
1211 static void dce_v6_0_bandwidth_update(struct amdgpu_device *adev)
1213 struct drm_display_mode *mode0 = NULL;
1214 struct drm_display_mode *mode1 = NULL;
1215 u32 num_heads = 0, lb_size;
1218 if (!adev->mode_info.mode_config_initialized)
1221 amdgpu_update_display_priority(adev);
1223 for (i = 0; i < adev->mode_info.num_crtc; i++) {
1224 if (adev->mode_info.crtcs[i]->base.enabled)
1227 for (i = 0; i < adev->mode_info.num_crtc; i += 2) {
1228 mode0 = &adev->mode_info.crtcs[i]->base.mode;
1229 mode1 = &adev->mode_info.crtcs[i+1]->base.mode;
1230 lb_size = dce_v6_0_line_buffer_adjust(adev, adev->mode_info.crtcs[i], mode0, mode1);
1231 dce_v6_0_program_watermarks(adev, adev->mode_info.crtcs[i], lb_size, num_heads);
1232 lb_size = dce_v6_0_line_buffer_adjust(adev, adev->mode_info.crtcs[i+1], mode1, mode0);
1233 dce_v6_0_program_watermarks(adev, adev->mode_info.crtcs[i+1], lb_size, num_heads);
1237 static void dce_v6_0_audio_get_connected_pins(struct amdgpu_device *adev)
1242 for (i = 0; i < adev->mode_info.audio.num_pins; i++) {
1243 tmp = RREG32_AUDIO_ENDPT(adev->mode_info.audio.pin[i].offset,
1244 ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT);
1245 if (REG_GET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT,
1247 adev->mode_info.audio.pin[i].connected = false;
1249 adev->mode_info.audio.pin[i].connected = true;
1254 static struct amdgpu_audio_pin *dce_v6_0_audio_get_pin(struct amdgpu_device *adev)
1258 dce_v6_0_audio_get_connected_pins(adev);
1260 for (i = 0; i < adev->mode_info.audio.num_pins; i++) {
1261 if (adev->mode_info.audio.pin[i].connected)
1262 return &adev->mode_info.audio.pin[i];
1264 DRM_ERROR("No connected audio pins found!\n");
1268 static void dce_v6_0_audio_select_pin(struct drm_encoder *encoder)
1270 struct amdgpu_device *adev = encoder->dev->dev_private;
1271 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1272 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1274 if (!dig || !dig->afmt || !dig->afmt->pin)
1277 WREG32(mmAFMT_AUDIO_SRC_CONTROL + dig->afmt->offset,
1278 REG_SET_FIELD(0, AFMT_AUDIO_SRC_CONTROL, AFMT_AUDIO_SRC_SELECT,
1279 dig->afmt->pin->id));
1282 static void dce_v6_0_audio_write_latency_fields(struct drm_encoder *encoder,
1283 struct drm_display_mode *mode)
1285 struct amdgpu_device *adev = encoder->dev->dev_private;
1286 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1287 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1288 struct drm_connector *connector;
1289 struct amdgpu_connector *amdgpu_connector = NULL;
1293 list_for_each_entry(connector, &encoder->dev->mode_config.connector_list, head) {
1294 if (connector->encoder == encoder) {
1295 amdgpu_connector = to_amdgpu_connector(connector);
1300 if (!amdgpu_connector) {
1301 DRM_ERROR("Couldn't find encoder's connector\n");
1305 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
1308 if (connector->latency_present[interlace]) {
1309 tmp = REG_SET_FIELD(0, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC,
1310 VIDEO_LIPSYNC, connector->video_latency[interlace]);
1311 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC,
1312 AUDIO_LIPSYNC, connector->audio_latency[interlace]);
1314 tmp = REG_SET_FIELD(0, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC,
1316 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC,
1319 WREG32_AUDIO_ENDPT(dig->afmt->pin->offset,
1320 ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC, tmp);
1323 static void dce_v6_0_audio_write_speaker_allocation(struct drm_encoder *encoder)
1325 struct amdgpu_device *adev = encoder->dev->dev_private;
1326 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1327 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1328 struct drm_connector *connector;
1329 struct amdgpu_connector *amdgpu_connector = NULL;
1334 list_for_each_entry(connector, &encoder->dev->mode_config.connector_list, head) {
1335 if (connector->encoder == encoder) {
1336 amdgpu_connector = to_amdgpu_connector(connector);
1341 if (!amdgpu_connector) {
1342 DRM_ERROR("Couldn't find encoder's connector\n");
1346 sad_count = drm_edid_to_speaker_allocation(amdgpu_connector_edid(connector), &sadb);
1347 if (sad_count < 0) {
1348 DRM_ERROR("Couldn't read Speaker Allocation Data Block: %d\n", sad_count);
1352 /* program the speaker allocation */
1353 tmp = RREG32_AUDIO_ENDPT(dig->afmt->pin->offset,
1354 ixAZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER);
1355 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER,
1356 HDMI_CONNECTION, 0);
1357 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER,
1360 if (connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort)
1361 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER,
1364 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER,
1365 HDMI_CONNECTION, 1);
1368 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER,
1369 SPEAKER_ALLOCATION, sadb[0]);
1371 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER,
1372 SPEAKER_ALLOCATION, 5); /* stereo */
1374 WREG32_AUDIO_ENDPT(dig->afmt->pin->offset,
1375 ixAZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER, tmp);
1380 static void dce_v6_0_audio_write_sad_regs(struct drm_encoder *encoder)
1382 struct amdgpu_device *adev = encoder->dev->dev_private;
1383 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1384 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1385 struct drm_connector *connector;
1386 struct amdgpu_connector *amdgpu_connector = NULL;
1387 struct cea_sad *sads;
1390 static const u16 eld_reg_to_type[][2] = {
1391 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0, HDMI_AUDIO_CODING_TYPE_PCM },
1392 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1, HDMI_AUDIO_CODING_TYPE_AC3 },
1393 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2, HDMI_AUDIO_CODING_TYPE_MPEG1 },
1394 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3, HDMI_AUDIO_CODING_TYPE_MP3 },
1395 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4, HDMI_AUDIO_CODING_TYPE_MPEG2 },
1396 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5, HDMI_AUDIO_CODING_TYPE_AAC_LC },
1397 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6, HDMI_AUDIO_CODING_TYPE_DTS },
1398 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7, HDMI_AUDIO_CODING_TYPE_ATRAC },
1399 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9, HDMI_AUDIO_CODING_TYPE_EAC3 },
1400 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10, HDMI_AUDIO_CODING_TYPE_DTS_HD },
1401 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11, HDMI_AUDIO_CODING_TYPE_MLP },
1402 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13, HDMI_AUDIO_CODING_TYPE_WMA_PRO },
1405 list_for_each_entry(connector, &encoder->dev->mode_config.connector_list, head) {
1406 if (connector->encoder == encoder) {
1407 amdgpu_connector = to_amdgpu_connector(connector);
1412 if (!amdgpu_connector) {
1413 DRM_ERROR("Couldn't find encoder's connector\n");
1417 sad_count = drm_edid_to_sad(amdgpu_connector_edid(connector), &sads);
1418 if (sad_count <= 0) {
1419 DRM_ERROR("Couldn't read SADs: %d\n", sad_count);
1423 for (i = 0; i < ARRAY_SIZE(eld_reg_to_type); i++) {
1425 u8 stereo_freqs = 0;
1426 int max_channels = -1;
1429 for (j = 0; j < sad_count; j++) {
1430 struct cea_sad *sad = &sads[j];
1432 if (sad->format == eld_reg_to_type[i][1]) {
1433 if (sad->channels > max_channels) {
1434 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0,
1435 MAX_CHANNELS, sad->channels);
1436 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0,
1437 DESCRIPTOR_BYTE_2, sad->byte2);
1438 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0,
1439 SUPPORTED_FREQUENCIES, sad->freq);
1440 max_channels = sad->channels;
1443 if (sad->format == HDMI_AUDIO_CODING_TYPE_PCM)
1444 stereo_freqs |= sad->freq;
1450 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0,
1451 SUPPORTED_FREQUENCIES_STEREO, stereo_freqs);
1452 WREG32_AUDIO_ENDPT(dig->afmt->pin->offset, eld_reg_to_type[i][0], tmp);
1459 static void dce_v6_0_audio_enable(struct amdgpu_device *adev,
1460 struct amdgpu_audio_pin *pin,
1466 WREG32_AUDIO_ENDPT(pin->offset, ixAZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL,
1467 enable ? AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK : 0);
1470 static const u32 pin_offsets[7] =
1481 static int dce_v6_0_audio_init(struct amdgpu_device *adev)
1488 adev->mode_info.audio.enabled = true;
1490 switch (adev->asic_type) {
1495 adev->mode_info.audio.num_pins = 6;
1498 adev->mode_info.audio.num_pins = 2;
1502 for (i = 0; i < adev->mode_info.audio.num_pins; i++) {
1503 adev->mode_info.audio.pin[i].channels = -1;
1504 adev->mode_info.audio.pin[i].rate = -1;
1505 adev->mode_info.audio.pin[i].bits_per_sample = -1;
1506 adev->mode_info.audio.pin[i].status_bits = 0;
1507 adev->mode_info.audio.pin[i].category_code = 0;
1508 adev->mode_info.audio.pin[i].connected = false;
1509 adev->mode_info.audio.pin[i].offset = pin_offsets[i];
1510 adev->mode_info.audio.pin[i].id = i;
1511 dce_v6_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false);
1517 static void dce_v6_0_audio_fini(struct amdgpu_device *adev)
1524 if (!adev->mode_info.audio.enabled)
1527 for (i = 0; i < adev->mode_info.audio.num_pins; i++)
1528 dce_v6_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false);
1530 adev->mode_info.audio.enabled = false;
1533 static void dce_v6_0_audio_set_vbi_packet(struct drm_encoder *encoder)
1535 struct drm_device *dev = encoder->dev;
1536 struct amdgpu_device *adev = dev->dev_private;
1537 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1538 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1541 tmp = RREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset);
1542 tmp = REG_SET_FIELD(tmp, HDMI_VBI_PACKET_CONTROL, HDMI_NULL_SEND, 1);
1543 tmp = REG_SET_FIELD(tmp, HDMI_VBI_PACKET_CONTROL, HDMI_GC_SEND, 1);
1544 tmp = REG_SET_FIELD(tmp, HDMI_VBI_PACKET_CONTROL, HDMI_GC_CONT, 1);
1545 WREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset, tmp);
1548 static void dce_v6_0_audio_set_acr(struct drm_encoder *encoder,
1549 uint32_t clock, int bpc)
1551 struct drm_device *dev = encoder->dev;
1552 struct amdgpu_device *adev = dev->dev_private;
1553 struct amdgpu_afmt_acr acr = amdgpu_afmt_acr(clock);
1554 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1555 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1558 tmp = RREG32(mmHDMI_ACR_PACKET_CONTROL + dig->afmt->offset);
1559 tmp = REG_SET_FIELD(tmp, HDMI_ACR_PACKET_CONTROL, HDMI_ACR_AUTO_SEND, 1);
1560 tmp = REG_SET_FIELD(tmp, HDMI_ACR_PACKET_CONTROL, HDMI_ACR_SOURCE,
1562 WREG32(mmHDMI_ACR_PACKET_CONTROL + dig->afmt->offset, tmp);
1564 tmp = RREG32(mmHDMI_ACR_32_0 + dig->afmt->offset);
1565 tmp = REG_SET_FIELD(tmp, HDMI_ACR_32_0, HDMI_ACR_CTS_32, acr.cts_32khz);
1566 WREG32(mmHDMI_ACR_32_0 + dig->afmt->offset, tmp);
1567 tmp = RREG32(mmHDMI_ACR_32_1 + dig->afmt->offset);
1568 tmp = REG_SET_FIELD(tmp, HDMI_ACR_32_1, HDMI_ACR_N_32, acr.n_32khz);
1569 WREG32(mmHDMI_ACR_32_1 + dig->afmt->offset, tmp);
1571 tmp = RREG32(mmHDMI_ACR_44_0 + dig->afmt->offset);
1572 tmp = REG_SET_FIELD(tmp, HDMI_ACR_44_0, HDMI_ACR_CTS_44, acr.cts_44_1khz);
1573 WREG32(mmHDMI_ACR_44_0 + dig->afmt->offset, tmp);
1574 tmp = RREG32(mmHDMI_ACR_44_1 + dig->afmt->offset);
1575 tmp = REG_SET_FIELD(tmp, HDMI_ACR_44_1, HDMI_ACR_N_44, acr.n_44_1khz);
1576 WREG32(mmHDMI_ACR_44_1 + dig->afmt->offset, tmp);
1578 tmp = RREG32(mmHDMI_ACR_48_0 + dig->afmt->offset);
1579 tmp = REG_SET_FIELD(tmp, HDMI_ACR_48_0, HDMI_ACR_CTS_48, acr.cts_48khz);
1580 WREG32(mmHDMI_ACR_48_0 + dig->afmt->offset, tmp);
1581 tmp = RREG32(mmHDMI_ACR_48_1 + dig->afmt->offset);
1582 tmp = REG_SET_FIELD(tmp, HDMI_ACR_48_1, HDMI_ACR_N_48, acr.n_48khz);
1583 WREG32(mmHDMI_ACR_48_1 + dig->afmt->offset, tmp);
1586 static void dce_v6_0_audio_set_avi_infoframe(struct drm_encoder *encoder,
1587 struct drm_display_mode *mode)
1589 struct drm_device *dev = encoder->dev;
1590 struct amdgpu_device *adev = dev->dev_private;
1591 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1592 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1593 struct hdmi_avi_infoframe frame;
1594 u8 buffer[HDMI_INFOFRAME_HEADER_SIZE + HDMI_AVI_INFOFRAME_SIZE];
1595 uint8_t *payload = buffer + 3;
1596 uint8_t *header = buffer;
1600 err = drm_hdmi_avi_infoframe_from_display_mode(&frame, mode);
1602 DRM_ERROR("failed to setup AVI infoframe: %zd\n", err);
1606 err = hdmi_avi_infoframe_pack(&frame, buffer, sizeof(buffer));
1608 DRM_ERROR("failed to pack AVI infoframe: %zd\n", err);
1612 WREG32(mmAFMT_AVI_INFO0 + dig->afmt->offset,
1613 payload[0x0] | (payload[0x1] << 8) | (payload[0x2] << 16) | (payload[0x3] << 24));
1614 WREG32(mmAFMT_AVI_INFO1 + dig->afmt->offset,
1615 payload[0x4] | (payload[0x5] << 8) | (payload[0x6] << 16) | (payload[0x7] << 24));
1616 WREG32(mmAFMT_AVI_INFO2 + dig->afmt->offset,
1617 payload[0x8] | (payload[0x9] << 8) | (payload[0xA] << 16) | (payload[0xB] << 24));
1618 WREG32(mmAFMT_AVI_INFO3 + dig->afmt->offset,
1619 payload[0xC] | (payload[0xD] << 8) | (header[1] << 24));
1621 tmp = RREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset);
1622 /* anything other than 0 */
1623 tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL1,
1624 HDMI_AUDIO_INFO_LINE, 2);
1625 WREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset, tmp);
1628 static void dce_v6_0_audio_set_dto(struct drm_encoder *encoder, u32 clock)
1630 struct drm_device *dev = encoder->dev;
1631 struct amdgpu_device *adev = dev->dev_private;
1632 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(encoder->crtc);
1633 int em = amdgpu_atombios_encoder_get_encoder_mode(encoder);
1637 * Two dtos: generally use dto0 for hdmi, dto1 for dp.
1638 * Express [24MHz / target pixel clock] as an exact rational
1639 * number (coefficient of two integer numbers. DCCG_AUDIO_DTOx_PHASE
1640 * is the numerator, DCCG_AUDIO_DTOx_MODULE is the denominator
1642 tmp = RREG32(mmDCCG_AUDIO_DTO_SOURCE);
1643 tmp = REG_SET_FIELD(tmp, DCCG_AUDIO_DTO_SOURCE,
1644 DCCG_AUDIO_DTO0_SOURCE_SEL, amdgpu_crtc->crtc_id);
1645 if (em == ATOM_ENCODER_MODE_HDMI) {
1646 tmp = REG_SET_FIELD(tmp, DCCG_AUDIO_DTO_SOURCE,
1647 DCCG_AUDIO_DTO_SEL, 0);
1648 } else if (ENCODER_MODE_IS_DP(em)) {
1649 tmp = REG_SET_FIELD(tmp, DCCG_AUDIO_DTO_SOURCE,
1650 DCCG_AUDIO_DTO_SEL, 1);
1652 WREG32(mmDCCG_AUDIO_DTO_SOURCE, tmp);
1653 if (em == ATOM_ENCODER_MODE_HDMI) {
1654 WREG32(mmDCCG_AUDIO_DTO0_PHASE, 24000);
1655 WREG32(mmDCCG_AUDIO_DTO0_MODULE, clock);
1656 } else if (ENCODER_MODE_IS_DP(em)) {
1657 WREG32(mmDCCG_AUDIO_DTO1_PHASE, 24000);
1658 WREG32(mmDCCG_AUDIO_DTO1_MODULE, clock);
1662 static void dce_v6_0_audio_set_packet(struct drm_encoder *encoder)
1664 struct drm_device *dev = encoder->dev;
1665 struct amdgpu_device *adev = dev->dev_private;
1666 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1667 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1670 tmp = RREG32(mmAFMT_INFOFRAME_CONTROL0 + dig->afmt->offset);
1671 tmp = REG_SET_FIELD(tmp, AFMT_INFOFRAME_CONTROL0, AFMT_AUDIO_INFO_UPDATE, 1);
1672 WREG32(mmAFMT_INFOFRAME_CONTROL0 + dig->afmt->offset, tmp);
1674 tmp = RREG32(mmAFMT_60958_0 + dig->afmt->offset);
1675 tmp = REG_SET_FIELD(tmp, AFMT_60958_0, AFMT_60958_CS_CHANNEL_NUMBER_L, 1);
1676 WREG32(mmAFMT_60958_0 + dig->afmt->offset, tmp);
1678 tmp = RREG32(mmAFMT_60958_1 + dig->afmt->offset);
1679 tmp = REG_SET_FIELD(tmp, AFMT_60958_1, AFMT_60958_CS_CHANNEL_NUMBER_R, 2);
1680 WREG32(mmAFMT_60958_1 + dig->afmt->offset, tmp);
1682 tmp = RREG32(mmAFMT_60958_2 + dig->afmt->offset);
1683 tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_2, 3);
1684 tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_3, 4);
1685 tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_4, 5);
1686 tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_5, 6);
1687 tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_6, 7);
1688 tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_7, 8);
1689 WREG32(mmAFMT_60958_2 + dig->afmt->offset, tmp);
1691 tmp = RREG32(mmAFMT_AUDIO_PACKET_CONTROL2 + dig->afmt->offset);
1692 tmp = REG_SET_FIELD(tmp, AFMT_AUDIO_PACKET_CONTROL2, AFMT_AUDIO_CHANNEL_ENABLE, 0xff);
1693 WREG32(mmAFMT_AUDIO_PACKET_CONTROL2 + dig->afmt->offset, tmp);
1695 tmp = RREG32(mmHDMI_AUDIO_PACKET_CONTROL + dig->afmt->offset);
1696 tmp = REG_SET_FIELD(tmp, HDMI_AUDIO_PACKET_CONTROL, HDMI_AUDIO_DELAY_EN, 1);
1697 tmp = REG_SET_FIELD(tmp, HDMI_AUDIO_PACKET_CONTROL, HDMI_AUDIO_PACKETS_PER_LINE, 3);
1698 WREG32(mmHDMI_AUDIO_PACKET_CONTROL + dig->afmt->offset, tmp);
1700 tmp = RREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset);
1701 tmp = REG_SET_FIELD(tmp, AFMT_AUDIO_PACKET_CONTROL, AFMT_RESET_FIFO_WHEN_AUDIO_DIS, 1);
1702 tmp = REG_SET_FIELD(tmp, AFMT_AUDIO_PACKET_CONTROL, AFMT_60958_CS_UPDATE, 1);
1703 WREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset, tmp);
1706 static void dce_v6_0_audio_set_mute(struct drm_encoder *encoder, bool mute)
1708 struct drm_device *dev = encoder->dev;
1709 struct amdgpu_device *adev = dev->dev_private;
1710 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1711 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1714 tmp = RREG32(mmHDMI_GC + dig->afmt->offset);
1715 tmp = REG_SET_FIELD(tmp, HDMI_GC, HDMI_GC_AVMUTE, mute ? 1 : 0);
1716 WREG32(mmHDMI_GC + dig->afmt->offset, tmp);
1719 static void dce_v6_0_audio_hdmi_enable(struct drm_encoder *encoder, bool enable)
1721 struct drm_device *dev = encoder->dev;
1722 struct amdgpu_device *adev = dev->dev_private;
1723 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1724 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1728 tmp = RREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset);
1729 tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AVI_INFO_SEND, 1);
1730 tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AVI_INFO_CONT, 1);
1731 tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AUDIO_INFO_SEND, 1);
1732 tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AUDIO_INFO_CONT, 1);
1733 WREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset, tmp);
1735 tmp = RREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset);
1736 tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL1, HDMI_AVI_INFO_LINE, 2);
1737 WREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset, tmp);
1739 tmp = RREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset);
1740 tmp = REG_SET_FIELD(tmp, AFMT_AUDIO_PACKET_CONTROL, AFMT_AUDIO_SAMPLE_SEND, 1);
1741 WREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset, tmp);
1743 tmp = RREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset);
1744 tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AVI_INFO_SEND, 0);
1745 tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AVI_INFO_CONT, 0);
1746 tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AUDIO_INFO_SEND, 0);
1747 tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AUDIO_INFO_CONT, 0);
1748 WREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset, tmp);
1750 tmp = RREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset);
1751 tmp = REG_SET_FIELD(tmp, AFMT_AUDIO_PACKET_CONTROL, AFMT_AUDIO_SAMPLE_SEND, 0);
1752 WREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset, tmp);
1756 static void dce_v6_0_audio_dp_enable(struct drm_encoder *encoder, bool enable)
1758 struct drm_device *dev = encoder->dev;
1759 struct amdgpu_device *adev = dev->dev_private;
1760 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1761 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1765 tmp = RREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset);
1766 tmp = REG_SET_FIELD(tmp, AFMT_AUDIO_PACKET_CONTROL, AFMT_AUDIO_SAMPLE_SEND, 1);
1767 WREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset, tmp);
1769 tmp = RREG32(mmDP_SEC_TIMESTAMP + dig->afmt->offset);
1770 tmp = REG_SET_FIELD(tmp, DP_SEC_TIMESTAMP, DP_SEC_TIMESTAMP_MODE, 1);
1771 WREG32(mmDP_SEC_TIMESTAMP + dig->afmt->offset, tmp);
1773 tmp = RREG32(mmDP_SEC_CNTL + dig->afmt->offset);
1774 tmp = REG_SET_FIELD(tmp, DP_SEC_CNTL, DP_SEC_ASP_ENABLE, 1);
1775 tmp = REG_SET_FIELD(tmp, DP_SEC_CNTL, DP_SEC_ATP_ENABLE, 1);
1776 tmp = REG_SET_FIELD(tmp, DP_SEC_CNTL, DP_SEC_AIP_ENABLE, 1);
1777 tmp = REG_SET_FIELD(tmp, DP_SEC_CNTL, DP_SEC_STREAM_ENABLE, 1);
1778 WREG32(mmDP_SEC_CNTL + dig->afmt->offset, tmp);
1780 WREG32(mmDP_SEC_CNTL + dig->afmt->offset, 0);
1784 static void dce_v6_0_afmt_setmode(struct drm_encoder *encoder,
1785 struct drm_display_mode *mode)
1787 struct drm_device *dev = encoder->dev;
1788 struct amdgpu_device *adev = dev->dev_private;
1789 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1790 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1791 struct drm_connector *connector;
1792 struct amdgpu_connector *amdgpu_connector = NULL;
1793 int em = amdgpu_atombios_encoder_get_encoder_mode(encoder);
1796 if (!dig || !dig->afmt)
1799 list_for_each_entry(connector, &encoder->dev->mode_config.connector_list, head) {
1800 if (connector->encoder == encoder) {
1801 amdgpu_connector = to_amdgpu_connector(connector);
1806 if (!amdgpu_connector) {
1807 DRM_ERROR("Couldn't find encoder's connector\n");
1811 if (!dig->afmt->enabled)
1814 dig->afmt->pin = dce_v6_0_audio_get_pin(adev);
1815 if (!dig->afmt->pin)
1818 if (encoder->crtc) {
1819 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(encoder->crtc);
1820 bpc = amdgpu_crtc->bpc;
1823 /* disable audio before setting up hw */
1824 dce_v6_0_audio_enable(adev, dig->afmt->pin, false);
1826 dce_v6_0_audio_set_mute(encoder, true);
1827 dce_v6_0_audio_write_speaker_allocation(encoder);
1828 dce_v6_0_audio_write_sad_regs(encoder);
1829 dce_v6_0_audio_write_latency_fields(encoder, mode);
1830 if (em == ATOM_ENCODER_MODE_HDMI) {
1831 dce_v6_0_audio_set_dto(encoder, mode->clock);
1832 dce_v6_0_audio_set_vbi_packet(encoder);
1833 dce_v6_0_audio_set_acr(encoder, mode->clock, bpc);
1834 } else if (ENCODER_MODE_IS_DP(em)) {
1835 dce_v6_0_audio_set_dto(encoder, adev->clock.default_dispclk * 10);
1837 dce_v6_0_audio_set_packet(encoder);
1838 dce_v6_0_audio_select_pin(encoder);
1839 dce_v6_0_audio_set_avi_infoframe(encoder, mode);
1840 dce_v6_0_audio_set_mute(encoder, false);
1841 if (em == ATOM_ENCODER_MODE_HDMI) {
1842 dce_v6_0_audio_hdmi_enable(encoder, 1);
1843 } else if (ENCODER_MODE_IS_DP(em)) {
1844 dce_v6_0_audio_dp_enable(encoder, 1);
1847 /* enable audio after setting up hw */
1848 dce_v6_0_audio_enable(adev, dig->afmt->pin, true);
1851 static void dce_v6_0_afmt_enable(struct drm_encoder *encoder, bool enable)
1853 struct drm_device *dev = encoder->dev;
1854 struct amdgpu_device *adev = dev->dev_private;
1855 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1856 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1858 if (!dig || !dig->afmt)
1861 /* Silent, r600_hdmi_enable will raise WARN for us */
1862 if (enable && dig->afmt->enabled)
1865 if (!enable && !dig->afmt->enabled)
1868 if (!enable && dig->afmt->pin) {
1869 dce_v6_0_audio_enable(adev, dig->afmt->pin, false);
1870 dig->afmt->pin = NULL;
1873 dig->afmt->enabled = enable;
1875 DRM_DEBUG("%sabling AFMT interface @ 0x%04X for encoder 0x%x\n",
1876 enable ? "En" : "Dis", dig->afmt->offset, amdgpu_encoder->encoder_id);
1879 static int dce_v6_0_afmt_init(struct amdgpu_device *adev)
1883 for (i = 0; i < adev->mode_info.num_dig; i++)
1884 adev->mode_info.afmt[i] = NULL;
1886 /* DCE6 has audio blocks tied to DIG encoders */
1887 for (i = 0; i < adev->mode_info.num_dig; i++) {
1888 adev->mode_info.afmt[i] = kzalloc(sizeof(struct amdgpu_afmt), GFP_KERNEL);
1889 if (adev->mode_info.afmt[i]) {
1890 adev->mode_info.afmt[i]->offset = dig_offsets[i];
1891 adev->mode_info.afmt[i]->id = i;
1893 for (j = 0; j < i; j++) {
1894 kfree(adev->mode_info.afmt[j]);
1895 adev->mode_info.afmt[j] = NULL;
1897 DRM_ERROR("Out of memory allocating afmt table\n");
1904 static void dce_v6_0_afmt_fini(struct amdgpu_device *adev)
1908 for (i = 0; i < adev->mode_info.num_dig; i++) {
1909 kfree(adev->mode_info.afmt[i]);
1910 adev->mode_info.afmt[i] = NULL;
1914 static const u32 vga_control_regs[6] =
1924 static void dce_v6_0_vga_enable(struct drm_crtc *crtc, bool enable)
1926 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
1927 struct drm_device *dev = crtc->dev;
1928 struct amdgpu_device *adev = dev->dev_private;
1931 vga_control = RREG32(vga_control_regs[amdgpu_crtc->crtc_id]) & ~1;
1932 WREG32(vga_control_regs[amdgpu_crtc->crtc_id], vga_control | (enable ? 1 : 0));
1935 static void dce_v6_0_grph_enable(struct drm_crtc *crtc, bool enable)
1937 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
1938 struct drm_device *dev = crtc->dev;
1939 struct amdgpu_device *adev = dev->dev_private;
1941 WREG32(mmGRPH_ENABLE + amdgpu_crtc->crtc_offset, enable ? 1 : 0);
1944 static int dce_v6_0_crtc_do_set_base(struct drm_crtc *crtc,
1945 struct drm_framebuffer *fb,
1946 int x, int y, int atomic)
1948 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
1949 struct drm_device *dev = crtc->dev;
1950 struct amdgpu_device *adev = dev->dev_private;
1951 struct amdgpu_framebuffer *amdgpu_fb;
1952 struct drm_framebuffer *target_fb;
1953 struct drm_gem_object *obj;
1954 struct amdgpu_bo *abo;
1955 uint64_t fb_location, tiling_flags;
1956 uint32_t fb_format, fb_pitch_pixels, pipe_config;
1957 u32 fb_swap = GRPH_ENDIAN_SWAP(GRPH_ENDIAN_NONE);
1958 u32 viewport_w, viewport_h;
1960 bool bypass_lut = false;
1961 struct drm_format_name_buf format_name;
1964 if (!atomic && !crtc->primary->fb) {
1965 DRM_DEBUG_KMS("No FB bound\n");
1970 amdgpu_fb = to_amdgpu_framebuffer(fb);
1973 amdgpu_fb = to_amdgpu_framebuffer(crtc->primary->fb);
1974 target_fb = crtc->primary->fb;
1977 /* If atomic, assume fb object is pinned & idle & fenced and
1978 * just update base pointers
1980 obj = amdgpu_fb->obj;
1981 abo = gem_to_amdgpu_bo(obj);
1982 r = amdgpu_bo_reserve(abo, false);
1983 if (unlikely(r != 0))
1987 fb_location = amdgpu_bo_gpu_offset(abo);
1989 r = amdgpu_bo_pin(abo, AMDGPU_GEM_DOMAIN_VRAM, &fb_location);
1990 if (unlikely(r != 0)) {
1991 amdgpu_bo_unreserve(abo);
1996 amdgpu_bo_get_tiling_flags(abo, &tiling_flags);
1997 amdgpu_bo_unreserve(abo);
1999 switch (target_fb->format->format) {
2001 fb_format = (GRPH_DEPTH(GRPH_DEPTH_8BPP) |
2002 GRPH_FORMAT(GRPH_FORMAT_INDEXED));
2004 case DRM_FORMAT_XRGB4444:
2005 case DRM_FORMAT_ARGB4444:
2006 fb_format = (GRPH_DEPTH(GRPH_DEPTH_16BPP) |
2007 GRPH_FORMAT(GRPH_FORMAT_ARGB4444));
2009 fb_swap = GRPH_ENDIAN_SWAP(GRPH_ENDIAN_8IN16);
2012 case DRM_FORMAT_XRGB1555:
2013 case DRM_FORMAT_ARGB1555:
2014 fb_format = (GRPH_DEPTH(GRPH_DEPTH_16BPP) |
2015 GRPH_FORMAT(GRPH_FORMAT_ARGB1555));
2017 fb_swap = GRPH_ENDIAN_SWAP(GRPH_ENDIAN_8IN16);
2020 case DRM_FORMAT_BGRX5551:
2021 case DRM_FORMAT_BGRA5551:
2022 fb_format = (GRPH_DEPTH(GRPH_DEPTH_16BPP) |
2023 GRPH_FORMAT(GRPH_FORMAT_BGRA5551));
2025 fb_swap = GRPH_ENDIAN_SWAP(GRPH_ENDIAN_8IN16);
2028 case DRM_FORMAT_RGB565:
2029 fb_format = (GRPH_DEPTH(GRPH_DEPTH_16BPP) |
2030 GRPH_FORMAT(GRPH_FORMAT_ARGB565));
2032 fb_swap = GRPH_ENDIAN_SWAP(GRPH_ENDIAN_8IN16);
2035 case DRM_FORMAT_XRGB8888:
2036 case DRM_FORMAT_ARGB8888:
2037 fb_format = (GRPH_DEPTH(GRPH_DEPTH_32BPP) |
2038 GRPH_FORMAT(GRPH_FORMAT_ARGB8888));
2040 fb_swap = GRPH_ENDIAN_SWAP(GRPH_ENDIAN_8IN32);
2043 case DRM_FORMAT_XRGB2101010:
2044 case DRM_FORMAT_ARGB2101010:
2045 fb_format = (GRPH_DEPTH(GRPH_DEPTH_32BPP) |
2046 GRPH_FORMAT(GRPH_FORMAT_ARGB2101010));
2048 fb_swap = GRPH_ENDIAN_SWAP(GRPH_ENDIAN_8IN32);
2050 /* Greater 8 bpc fb needs to bypass hw-lut to retain precision */
2053 case DRM_FORMAT_BGRX1010102:
2054 case DRM_FORMAT_BGRA1010102:
2055 fb_format = (GRPH_DEPTH(GRPH_DEPTH_32BPP) |
2056 GRPH_FORMAT(GRPH_FORMAT_BGRA1010102));
2058 fb_swap = GRPH_ENDIAN_SWAP(GRPH_ENDIAN_8IN32);
2060 /* Greater 8 bpc fb needs to bypass hw-lut to retain precision */
2064 DRM_ERROR("Unsupported screen format %s\n",
2065 drm_get_format_name(target_fb->format->format, &format_name));
2069 if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == ARRAY_2D_TILED_THIN1) {
2070 unsigned bankw, bankh, mtaspect, tile_split, num_banks;
2072 bankw = AMDGPU_TILING_GET(tiling_flags, BANK_WIDTH);
2073 bankh = AMDGPU_TILING_GET(tiling_flags, BANK_HEIGHT);
2074 mtaspect = AMDGPU_TILING_GET(tiling_flags, MACRO_TILE_ASPECT);
2075 tile_split = AMDGPU_TILING_GET(tiling_flags, TILE_SPLIT);
2076 num_banks = AMDGPU_TILING_GET(tiling_flags, NUM_BANKS);
2078 fb_format |= GRPH_NUM_BANKS(num_banks);
2079 fb_format |= GRPH_ARRAY_MODE(GRPH_ARRAY_2D_TILED_THIN1);
2080 fb_format |= GRPH_TILE_SPLIT(tile_split);
2081 fb_format |= GRPH_BANK_WIDTH(bankw);
2082 fb_format |= GRPH_BANK_HEIGHT(bankh);
2083 fb_format |= GRPH_MACRO_TILE_ASPECT(mtaspect);
2084 } else if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == ARRAY_1D_TILED_THIN1) {
2085 fb_format |= GRPH_ARRAY_MODE(GRPH_ARRAY_1D_TILED_THIN1);
2088 pipe_config = AMDGPU_TILING_GET(tiling_flags, PIPE_CONFIG);
2089 fb_format |= GRPH_PIPE_CONFIG(pipe_config);
2091 dce_v6_0_vga_enable(crtc, false);
2093 /* Make sure surface address is updated at vertical blank rather than
2096 WREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset, 0);
2098 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,
2099 upper_32_bits(fb_location));
2100 WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,
2101 upper_32_bits(fb_location));
2102 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,
2103 (u32)fb_location & GRPH_PRIMARY_SURFACE_ADDRESS__GRPH_PRIMARY_SURFACE_ADDRESS_MASK);
2104 WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,
2105 (u32) fb_location & GRPH_PRIMARY_SURFACE_ADDRESS__GRPH_PRIMARY_SURFACE_ADDRESS_MASK);
2106 WREG32(mmGRPH_CONTROL + amdgpu_crtc->crtc_offset, fb_format);
2107 WREG32(mmGRPH_SWAP_CNTL + amdgpu_crtc->crtc_offset, fb_swap);
2110 * The LUT only has 256 slots for indexing by a 8 bpc fb. Bypass the LUT
2111 * for > 8 bpc scanout to avoid truncation of fb indices to 8 msb's, to
2112 * retain the full precision throughout the pipeline.
2114 WREG32_P(mmGRPH_LUT_10BIT_BYPASS + amdgpu_crtc->crtc_offset,
2115 (bypass_lut ? GRPH_LUT_10BIT_BYPASS__GRPH_LUT_10BIT_BYPASS_EN_MASK : 0),
2116 ~GRPH_LUT_10BIT_BYPASS__GRPH_LUT_10BIT_BYPASS_EN_MASK);
2119 DRM_DEBUG_KMS("Bypassing hardware LUT due to 10 bit fb scanout.\n");
2121 WREG32(mmGRPH_SURFACE_OFFSET_X + amdgpu_crtc->crtc_offset, 0);
2122 WREG32(mmGRPH_SURFACE_OFFSET_Y + amdgpu_crtc->crtc_offset, 0);
2123 WREG32(mmGRPH_X_START + amdgpu_crtc->crtc_offset, 0);
2124 WREG32(mmGRPH_Y_START + amdgpu_crtc->crtc_offset, 0);
2125 WREG32(mmGRPH_X_END + amdgpu_crtc->crtc_offset, target_fb->width);
2126 WREG32(mmGRPH_Y_END + amdgpu_crtc->crtc_offset, target_fb->height);
2128 fb_pitch_pixels = target_fb->pitches[0] / target_fb->format->cpp[0];
2129 WREG32(mmGRPH_PITCH + amdgpu_crtc->crtc_offset, fb_pitch_pixels);
2131 dce_v6_0_grph_enable(crtc, true);
2133 WREG32(mmDESKTOP_HEIGHT + amdgpu_crtc->crtc_offset,
2137 WREG32(mmVIEWPORT_START + amdgpu_crtc->crtc_offset,
2139 viewport_w = crtc->mode.hdisplay;
2140 viewport_h = (crtc->mode.vdisplay + 1) & ~1;
2142 WREG32(mmVIEWPORT_SIZE + amdgpu_crtc->crtc_offset,
2143 (viewport_w << 16) | viewport_h);
2145 /* set pageflip to happen anywhere in vblank interval */
2146 WREG32(mmMASTER_UPDATE_MODE + amdgpu_crtc->crtc_offset, 0);
2148 if (!atomic && fb && fb != crtc->primary->fb) {
2149 amdgpu_fb = to_amdgpu_framebuffer(fb);
2150 abo = gem_to_amdgpu_bo(amdgpu_fb->obj);
2151 r = amdgpu_bo_reserve(abo, true);
2152 if (unlikely(r != 0))
2154 amdgpu_bo_unpin(abo);
2155 amdgpu_bo_unreserve(abo);
2158 /* Bytes per pixel may have changed */
2159 dce_v6_0_bandwidth_update(adev);
2165 static void dce_v6_0_set_interleave(struct drm_crtc *crtc,
2166 struct drm_display_mode *mode)
2168 struct drm_device *dev = crtc->dev;
2169 struct amdgpu_device *adev = dev->dev_private;
2170 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2172 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
2173 WREG32(mmDATA_FORMAT + amdgpu_crtc->crtc_offset,
2176 WREG32(mmDATA_FORMAT + amdgpu_crtc->crtc_offset, 0);
2179 static void dce_v6_0_crtc_load_lut(struct drm_crtc *crtc)
2182 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2183 struct drm_device *dev = crtc->dev;
2184 struct amdgpu_device *adev = dev->dev_private;
2187 DRM_DEBUG_KMS("%d\n", amdgpu_crtc->crtc_id);
2189 WREG32(mmINPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset,
2190 ((0 << INPUT_CSC_CONTROL__INPUT_CSC_GRPH_MODE__SHIFT) |
2191 (0 << INPUT_CSC_CONTROL__INPUT_CSC_OVL_MODE__SHIFT)));
2192 WREG32(mmPRESCALE_GRPH_CONTROL + amdgpu_crtc->crtc_offset,
2193 PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_BYPASS_MASK);
2194 WREG32(mmPRESCALE_OVL_CONTROL + amdgpu_crtc->crtc_offset,
2195 PRESCALE_OVL_CONTROL__OVL_PRESCALE_BYPASS_MASK);
2196 WREG32(mmINPUT_GAMMA_CONTROL + amdgpu_crtc->crtc_offset,
2197 ((0 << INPUT_GAMMA_CONTROL__GRPH_INPUT_GAMMA_MODE__SHIFT) |
2198 (0 << INPUT_GAMMA_CONTROL__OVL_INPUT_GAMMA_MODE__SHIFT)));
2200 WREG32(mmDC_LUT_CONTROL + amdgpu_crtc->crtc_offset, 0);
2202 WREG32(mmDC_LUT_BLACK_OFFSET_BLUE + amdgpu_crtc->crtc_offset, 0);
2203 WREG32(mmDC_LUT_BLACK_OFFSET_GREEN + amdgpu_crtc->crtc_offset, 0);
2204 WREG32(mmDC_LUT_BLACK_OFFSET_RED + amdgpu_crtc->crtc_offset, 0);
2206 WREG32(mmDC_LUT_WHITE_OFFSET_BLUE + amdgpu_crtc->crtc_offset, 0xffff);
2207 WREG32(mmDC_LUT_WHITE_OFFSET_GREEN + amdgpu_crtc->crtc_offset, 0xffff);
2208 WREG32(mmDC_LUT_WHITE_OFFSET_RED + amdgpu_crtc->crtc_offset, 0xffff);
2210 WREG32(mmDC_LUT_RW_MODE + amdgpu_crtc->crtc_offset, 0);
2211 WREG32(mmDC_LUT_WRITE_EN_MASK + amdgpu_crtc->crtc_offset, 0x00000007);
2213 WREG32(mmDC_LUT_RW_INDEX + amdgpu_crtc->crtc_offset, 0);
2214 for (i = 0; i < 256; i++) {
2215 WREG32(mmDC_LUT_30_COLOR + amdgpu_crtc->crtc_offset,
2216 (amdgpu_crtc->lut_r[i] << 20) |
2217 (amdgpu_crtc->lut_g[i] << 10) |
2218 (amdgpu_crtc->lut_b[i] << 0));
2221 WREG32(mmDEGAMMA_CONTROL + amdgpu_crtc->crtc_offset,
2222 ((0 << DEGAMMA_CONTROL__GRPH_DEGAMMA_MODE__SHIFT) |
2223 (0 << DEGAMMA_CONTROL__OVL_DEGAMMA_MODE__SHIFT) |
2224 ICON_DEGAMMA_MODE(0) |
2225 (0 << DEGAMMA_CONTROL__CURSOR_DEGAMMA_MODE__SHIFT)));
2226 WREG32(mmGAMUT_REMAP_CONTROL + amdgpu_crtc->crtc_offset,
2227 ((0 << GAMUT_REMAP_CONTROL__GRPH_GAMUT_REMAP_MODE__SHIFT) |
2228 (0 << GAMUT_REMAP_CONTROL__OVL_GAMUT_REMAP_MODE__SHIFT)));
2229 WREG32(mmREGAMMA_CONTROL + amdgpu_crtc->crtc_offset,
2230 ((0 << REGAMMA_CONTROL__GRPH_REGAMMA_MODE__SHIFT) |
2231 (0 << REGAMMA_CONTROL__OVL_REGAMMA_MODE__SHIFT)));
2232 WREG32(mmOUTPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset,
2233 ((0 << OUTPUT_CSC_CONTROL__OUTPUT_CSC_GRPH_MODE__SHIFT) |
2234 (0 << OUTPUT_CSC_CONTROL__OUTPUT_CSC_OVL_MODE__SHIFT)));
2235 /* XXX match this to the depth of the crtc fmt block, move to modeset? */
2236 WREG32(0x1a50 + amdgpu_crtc->crtc_offset, 0);
2241 static int dce_v6_0_pick_dig_encoder(struct drm_encoder *encoder)
2243 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
2244 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
2246 switch (amdgpu_encoder->encoder_id) {
2247 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
2248 return dig->linkb ? 1 : 0;
2249 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
2250 return dig->linkb ? 3 : 2;
2251 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
2252 return dig->linkb ? 5 : 4;
2253 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
2256 DRM_ERROR("invalid encoder_id: 0x%x\n", amdgpu_encoder->encoder_id);
2262 * dce_v6_0_pick_pll - Allocate a PPLL for use by the crtc.
2266 * Returns the PPLL (Pixel PLL) to be used by the crtc. For DP monitors
2267 * a single PPLL can be used for all DP crtcs/encoders. For non-DP
2268 * monitors a dedicated PPLL must be used. If a particular board has
2269 * an external DP PLL, return ATOM_PPLL_INVALID to skip PLL programming
2270 * as there is no need to program the PLL itself. If we are not able to
2271 * allocate a PLL, return ATOM_PPLL_INVALID to skip PLL programming to
2272 * avoid messing up an existing monitor.
2276 static u32 dce_v6_0_pick_pll(struct drm_crtc *crtc)
2278 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2279 struct drm_device *dev = crtc->dev;
2280 struct amdgpu_device *adev = dev->dev_private;
2284 if (ENCODER_MODE_IS_DP(amdgpu_atombios_encoder_get_encoder_mode(amdgpu_crtc->encoder))) {
2285 if (adev->clock.dp_extclk)
2286 /* skip PPLL programming if using ext clock */
2287 return ATOM_PPLL_INVALID;
2291 /* use the same PPLL for all monitors with the same clock */
2292 pll = amdgpu_pll_get_shared_nondp_ppll(crtc);
2293 if (pll != ATOM_PPLL_INVALID)
2297 /* PPLL1, and PPLL2 */
2298 pll_in_use = amdgpu_pll_get_use_mask(crtc);
2299 if (!(pll_in_use & (1 << ATOM_PPLL2)))
2301 if (!(pll_in_use & (1 << ATOM_PPLL1)))
2303 DRM_ERROR("unable to allocate a PPLL\n");
2304 return ATOM_PPLL_INVALID;
2307 static void dce_v6_0_lock_cursor(struct drm_crtc *crtc, bool lock)
2309 struct amdgpu_device *adev = crtc->dev->dev_private;
2310 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2313 cur_lock = RREG32(mmCUR_UPDATE + amdgpu_crtc->crtc_offset);
2315 cur_lock |= CUR_UPDATE__CURSOR_UPDATE_LOCK_MASK;
2317 cur_lock &= ~CUR_UPDATE__CURSOR_UPDATE_LOCK_MASK;
2318 WREG32(mmCUR_UPDATE + amdgpu_crtc->crtc_offset, cur_lock);
2321 static void dce_v6_0_hide_cursor(struct drm_crtc *crtc)
2323 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2324 struct amdgpu_device *adev = crtc->dev->dev_private;
2326 WREG32_IDX(mmCUR_CONTROL + amdgpu_crtc->crtc_offset,
2327 (CURSOR_24_8_PRE_MULT << CUR_CONTROL__CURSOR_MODE__SHIFT) |
2328 (CURSOR_URGENT_1_2 << CUR_CONTROL__CURSOR_URGENT_CONTROL__SHIFT));
2333 static void dce_v6_0_show_cursor(struct drm_crtc *crtc)
2335 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2336 struct amdgpu_device *adev = crtc->dev->dev_private;
2338 WREG32(mmCUR_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,
2339 upper_32_bits(amdgpu_crtc->cursor_addr));
2340 WREG32(mmCUR_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,
2341 lower_32_bits(amdgpu_crtc->cursor_addr));
2343 WREG32_IDX(mmCUR_CONTROL + amdgpu_crtc->crtc_offset,
2344 CUR_CONTROL__CURSOR_EN_MASK |
2345 (CURSOR_24_8_PRE_MULT << CUR_CONTROL__CURSOR_MODE__SHIFT) |
2346 (CURSOR_URGENT_1_2 << CUR_CONTROL__CURSOR_URGENT_CONTROL__SHIFT));
2350 static int dce_v6_0_cursor_move_locked(struct drm_crtc *crtc,
2353 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2354 struct amdgpu_device *adev = crtc->dev->dev_private;
2355 int xorigin = 0, yorigin = 0;
2357 int w = amdgpu_crtc->cursor_width;
2359 amdgpu_crtc->cursor_x = x;
2360 amdgpu_crtc->cursor_y = y;
2362 /* avivo cursor are offset into the total surface */
2365 DRM_DEBUG("x %d y %d c->x %d c->y %d\n", x, y, crtc->x, crtc->y);
2368 xorigin = min(-x, amdgpu_crtc->max_cursor_width - 1);
2372 yorigin = min(-y, amdgpu_crtc->max_cursor_height - 1);
2376 WREG32(mmCUR_POSITION + amdgpu_crtc->crtc_offset, (x << 16) | y);
2377 WREG32(mmCUR_HOT_SPOT + amdgpu_crtc->crtc_offset, (xorigin << 16) | yorigin);
2378 WREG32(mmCUR_SIZE + amdgpu_crtc->crtc_offset,
2379 ((w - 1) << 16) | (amdgpu_crtc->cursor_height - 1));
2384 static int dce_v6_0_crtc_cursor_move(struct drm_crtc *crtc,
2389 dce_v6_0_lock_cursor(crtc, true);
2390 ret = dce_v6_0_cursor_move_locked(crtc, x, y);
2391 dce_v6_0_lock_cursor(crtc, false);
2396 static int dce_v6_0_crtc_cursor_set2(struct drm_crtc *crtc,
2397 struct drm_file *file_priv,
2404 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2405 struct drm_gem_object *obj;
2406 struct amdgpu_bo *aobj;
2410 /* turn off cursor */
2411 dce_v6_0_hide_cursor(crtc);
2416 if ((width > amdgpu_crtc->max_cursor_width) ||
2417 (height > amdgpu_crtc->max_cursor_height)) {
2418 DRM_ERROR("bad cursor width or height %d x %d\n", width, height);
2422 obj = drm_gem_object_lookup(file_priv, handle);
2424 DRM_ERROR("Cannot find cursor object %x for crtc %d\n", handle, amdgpu_crtc->crtc_id);
2428 aobj = gem_to_amdgpu_bo(obj);
2429 ret = amdgpu_bo_reserve(aobj, false);
2431 drm_gem_object_unreference_unlocked(obj);
2435 ret = amdgpu_bo_pin(aobj, AMDGPU_GEM_DOMAIN_VRAM, &amdgpu_crtc->cursor_addr);
2436 amdgpu_bo_unreserve(aobj);
2438 DRM_ERROR("Failed to pin new cursor BO (%d)\n", ret);
2439 drm_gem_object_unreference_unlocked(obj);
2443 dce_v6_0_lock_cursor(crtc, true);
2445 if (width != amdgpu_crtc->cursor_width ||
2446 height != amdgpu_crtc->cursor_height ||
2447 hot_x != amdgpu_crtc->cursor_hot_x ||
2448 hot_y != amdgpu_crtc->cursor_hot_y) {
2451 x = amdgpu_crtc->cursor_x + amdgpu_crtc->cursor_hot_x - hot_x;
2452 y = amdgpu_crtc->cursor_y + amdgpu_crtc->cursor_hot_y - hot_y;
2454 dce_v6_0_cursor_move_locked(crtc, x, y);
2456 amdgpu_crtc->cursor_width = width;
2457 amdgpu_crtc->cursor_height = height;
2458 amdgpu_crtc->cursor_hot_x = hot_x;
2459 amdgpu_crtc->cursor_hot_y = hot_y;
2462 dce_v6_0_show_cursor(crtc);
2463 dce_v6_0_lock_cursor(crtc, false);
2466 if (amdgpu_crtc->cursor_bo) {
2467 struct amdgpu_bo *aobj = gem_to_amdgpu_bo(amdgpu_crtc->cursor_bo);
2468 ret = amdgpu_bo_reserve(aobj, true);
2469 if (likely(ret == 0)) {
2470 amdgpu_bo_unpin(aobj);
2471 amdgpu_bo_unreserve(aobj);
2473 drm_gem_object_unreference_unlocked(amdgpu_crtc->cursor_bo);
2476 amdgpu_crtc->cursor_bo = obj;
2480 static void dce_v6_0_cursor_reset(struct drm_crtc *crtc)
2482 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2484 if (amdgpu_crtc->cursor_bo) {
2485 dce_v6_0_lock_cursor(crtc, true);
2487 dce_v6_0_cursor_move_locked(crtc, amdgpu_crtc->cursor_x,
2488 amdgpu_crtc->cursor_y);
2490 dce_v6_0_show_cursor(crtc);
2491 dce_v6_0_lock_cursor(crtc, false);
2495 static int dce_v6_0_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
2496 u16 *blue, uint32_t size,
2497 struct drm_modeset_acquire_ctx *ctx)
2499 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2502 /* userspace palettes are always correct as is */
2503 for (i = 0; i < size; i++) {
2504 amdgpu_crtc->lut_r[i] = red[i] >> 6;
2505 amdgpu_crtc->lut_g[i] = green[i] >> 6;
2506 amdgpu_crtc->lut_b[i] = blue[i] >> 6;
2508 dce_v6_0_crtc_load_lut(crtc);
2513 static void dce_v6_0_crtc_destroy(struct drm_crtc *crtc)
2515 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2517 drm_crtc_cleanup(crtc);
2521 static const struct drm_crtc_funcs dce_v6_0_crtc_funcs = {
2522 .cursor_set2 = dce_v6_0_crtc_cursor_set2,
2523 .cursor_move = dce_v6_0_crtc_cursor_move,
2524 .gamma_set = dce_v6_0_crtc_gamma_set,
2525 .set_config = amdgpu_crtc_set_config,
2526 .destroy = dce_v6_0_crtc_destroy,
2527 .page_flip_target = amdgpu_crtc_page_flip_target,
2530 static void dce_v6_0_crtc_dpms(struct drm_crtc *crtc, int mode)
2532 struct drm_device *dev = crtc->dev;
2533 struct amdgpu_device *adev = dev->dev_private;
2534 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2538 case DRM_MODE_DPMS_ON:
2539 amdgpu_crtc->enabled = true;
2540 amdgpu_atombios_crtc_enable(crtc, ATOM_ENABLE);
2541 amdgpu_atombios_crtc_blank(crtc, ATOM_DISABLE);
2542 /* Make sure VBLANK and PFLIP interrupts are still enabled */
2543 type = amdgpu_crtc_idx_to_irq_type(adev, amdgpu_crtc->crtc_id);
2544 amdgpu_irq_update(adev, &adev->crtc_irq, type);
2545 amdgpu_irq_update(adev, &adev->pageflip_irq, type);
2546 drm_crtc_vblank_on(crtc);
2547 dce_v6_0_crtc_load_lut(crtc);
2549 case DRM_MODE_DPMS_STANDBY:
2550 case DRM_MODE_DPMS_SUSPEND:
2551 case DRM_MODE_DPMS_OFF:
2552 drm_crtc_vblank_off(crtc);
2553 if (amdgpu_crtc->enabled)
2554 amdgpu_atombios_crtc_blank(crtc, ATOM_ENABLE);
2555 amdgpu_atombios_crtc_enable(crtc, ATOM_DISABLE);
2556 amdgpu_crtc->enabled = false;
2559 /* adjust pm to dpms */
2560 amdgpu_pm_compute_clocks(adev);
2563 static void dce_v6_0_crtc_prepare(struct drm_crtc *crtc)
2565 /* disable crtc pair power gating before programming */
2566 amdgpu_atombios_crtc_powergate(crtc, ATOM_DISABLE);
2567 amdgpu_atombios_crtc_lock(crtc, ATOM_ENABLE);
2568 dce_v6_0_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);
2571 static void dce_v6_0_crtc_commit(struct drm_crtc *crtc)
2573 dce_v6_0_crtc_dpms(crtc, DRM_MODE_DPMS_ON);
2574 amdgpu_atombios_crtc_lock(crtc, ATOM_DISABLE);
2577 static void dce_v6_0_crtc_disable(struct drm_crtc *crtc)
2580 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2581 struct drm_device *dev = crtc->dev;
2582 struct amdgpu_device *adev = dev->dev_private;
2583 struct amdgpu_atom_ss ss;
2586 dce_v6_0_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);
2587 if (crtc->primary->fb) {
2589 struct amdgpu_framebuffer *amdgpu_fb;
2590 struct amdgpu_bo *abo;
2592 amdgpu_fb = to_amdgpu_framebuffer(crtc->primary->fb);
2593 abo = gem_to_amdgpu_bo(amdgpu_fb->obj);
2594 r = amdgpu_bo_reserve(abo, true);
2596 DRM_ERROR("failed to reserve abo before unpin\n");
2598 amdgpu_bo_unpin(abo);
2599 amdgpu_bo_unreserve(abo);
2602 /* disable the GRPH */
2603 dce_v6_0_grph_enable(crtc, false);
2605 amdgpu_atombios_crtc_powergate(crtc, ATOM_ENABLE);
2607 for (i = 0; i < adev->mode_info.num_crtc; i++) {
2608 if (adev->mode_info.crtcs[i] &&
2609 adev->mode_info.crtcs[i]->enabled &&
2610 i != amdgpu_crtc->crtc_id &&
2611 amdgpu_crtc->pll_id == adev->mode_info.crtcs[i]->pll_id) {
2612 /* one other crtc is using this pll don't turn
2619 switch (amdgpu_crtc->pll_id) {
2622 /* disable the ppll */
2623 amdgpu_atombios_crtc_program_pll(crtc, amdgpu_crtc->crtc_id, amdgpu_crtc->pll_id,
2624 0, 0, ATOM_DISABLE, 0, 0, 0, 0, 0, false, &ss);
2630 amdgpu_crtc->pll_id = ATOM_PPLL_INVALID;
2631 amdgpu_crtc->adjusted_clock = 0;
2632 amdgpu_crtc->encoder = NULL;
2633 amdgpu_crtc->connector = NULL;
2636 static int dce_v6_0_crtc_mode_set(struct drm_crtc *crtc,
2637 struct drm_display_mode *mode,
2638 struct drm_display_mode *adjusted_mode,
2639 int x, int y, struct drm_framebuffer *old_fb)
2641 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2643 if (!amdgpu_crtc->adjusted_clock)
2646 amdgpu_atombios_crtc_set_pll(crtc, adjusted_mode);
2647 amdgpu_atombios_crtc_set_dtd_timing(crtc, adjusted_mode);
2648 dce_v6_0_crtc_do_set_base(crtc, old_fb, x, y, 0);
2649 amdgpu_atombios_crtc_overscan_setup(crtc, mode, adjusted_mode);
2650 amdgpu_atombios_crtc_scaler_setup(crtc);
2651 dce_v6_0_cursor_reset(crtc);
2652 /* update the hw version fpr dpm */
2653 amdgpu_crtc->hw_mode = *adjusted_mode;
2658 static bool dce_v6_0_crtc_mode_fixup(struct drm_crtc *crtc,
2659 const struct drm_display_mode *mode,
2660 struct drm_display_mode *adjusted_mode)
2663 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2664 struct drm_device *dev = crtc->dev;
2665 struct drm_encoder *encoder;
2667 /* assign the encoder to the amdgpu crtc to avoid repeated lookups later */
2668 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
2669 if (encoder->crtc == crtc) {
2670 amdgpu_crtc->encoder = encoder;
2671 amdgpu_crtc->connector = amdgpu_get_connector_for_encoder(encoder);
2675 if ((amdgpu_crtc->encoder == NULL) || (amdgpu_crtc->connector == NULL)) {
2676 amdgpu_crtc->encoder = NULL;
2677 amdgpu_crtc->connector = NULL;
2680 if (!amdgpu_crtc_scaling_mode_fixup(crtc, mode, adjusted_mode))
2682 if (amdgpu_atombios_crtc_prepare_pll(crtc, adjusted_mode))
2685 amdgpu_crtc->pll_id = dce_v6_0_pick_pll(crtc);
2686 /* if we can't get a PPLL for a non-DP encoder, fail */
2687 if ((amdgpu_crtc->pll_id == ATOM_PPLL_INVALID) &&
2688 !ENCODER_MODE_IS_DP(amdgpu_atombios_encoder_get_encoder_mode(amdgpu_crtc->encoder)))
2694 static int dce_v6_0_crtc_set_base(struct drm_crtc *crtc, int x, int y,
2695 struct drm_framebuffer *old_fb)
2697 return dce_v6_0_crtc_do_set_base(crtc, old_fb, x, y, 0);
2700 static int dce_v6_0_crtc_set_base_atomic(struct drm_crtc *crtc,
2701 struct drm_framebuffer *fb,
2702 int x, int y, enum mode_set_atomic state)
2704 return dce_v6_0_crtc_do_set_base(crtc, fb, x, y, 1);
2707 static const struct drm_crtc_helper_funcs dce_v6_0_crtc_helper_funcs = {
2708 .dpms = dce_v6_0_crtc_dpms,
2709 .mode_fixup = dce_v6_0_crtc_mode_fixup,
2710 .mode_set = dce_v6_0_crtc_mode_set,
2711 .mode_set_base = dce_v6_0_crtc_set_base,
2712 .mode_set_base_atomic = dce_v6_0_crtc_set_base_atomic,
2713 .prepare = dce_v6_0_crtc_prepare,
2714 .commit = dce_v6_0_crtc_commit,
2715 .load_lut = dce_v6_0_crtc_load_lut,
2716 .disable = dce_v6_0_crtc_disable,
2719 static int dce_v6_0_crtc_init(struct amdgpu_device *adev, int index)
2721 struct amdgpu_crtc *amdgpu_crtc;
2724 amdgpu_crtc = kzalloc(sizeof(struct amdgpu_crtc) +
2725 (AMDGPUFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
2726 if (amdgpu_crtc == NULL)
2729 drm_crtc_init(adev->ddev, &amdgpu_crtc->base, &dce_v6_0_crtc_funcs);
2731 drm_mode_crtc_set_gamma_size(&amdgpu_crtc->base, 256);
2732 amdgpu_crtc->crtc_id = index;
2733 adev->mode_info.crtcs[index] = amdgpu_crtc;
2735 amdgpu_crtc->max_cursor_width = CURSOR_WIDTH;
2736 amdgpu_crtc->max_cursor_height = CURSOR_HEIGHT;
2737 adev->ddev->mode_config.cursor_width = amdgpu_crtc->max_cursor_width;
2738 adev->ddev->mode_config.cursor_height = amdgpu_crtc->max_cursor_height;
2740 for (i = 0; i < 256; i++) {
2741 amdgpu_crtc->lut_r[i] = i << 2;
2742 amdgpu_crtc->lut_g[i] = i << 2;
2743 amdgpu_crtc->lut_b[i] = i << 2;
2746 amdgpu_crtc->crtc_offset = crtc_offsets[amdgpu_crtc->crtc_id];
2748 amdgpu_crtc->pll_id = ATOM_PPLL_INVALID;
2749 amdgpu_crtc->adjusted_clock = 0;
2750 amdgpu_crtc->encoder = NULL;
2751 amdgpu_crtc->connector = NULL;
2752 drm_crtc_helper_add(&amdgpu_crtc->base, &dce_v6_0_crtc_helper_funcs);
2757 static int dce_v6_0_early_init(void *handle)
2759 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2761 adev->audio_endpt_rreg = &dce_v6_0_audio_endpt_rreg;
2762 adev->audio_endpt_wreg = &dce_v6_0_audio_endpt_wreg;
2764 dce_v6_0_set_display_funcs(adev);
2765 dce_v6_0_set_irq_funcs(adev);
2767 adev->mode_info.num_crtc = dce_v6_0_get_num_crtc(adev);
2769 switch (adev->asic_type) {
2773 adev->mode_info.num_hpd = 6;
2774 adev->mode_info.num_dig = 6;
2777 adev->mode_info.num_hpd = 2;
2778 adev->mode_info.num_dig = 2;
2787 static int dce_v6_0_sw_init(void *handle)
2791 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2793 for (i = 0; i < adev->mode_info.num_crtc; i++) {
2794 r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, i + 1, &adev->crtc_irq);
2799 for (i = 8; i < 20; i += 2) {
2800 r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, i, &adev->pageflip_irq);
2806 r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, 42, &adev->hpd_irq);
2810 adev->mode_info.mode_config_initialized = true;
2812 adev->ddev->mode_config.funcs = &amdgpu_mode_funcs;
2813 adev->ddev->mode_config.async_page_flip = true;
2814 adev->ddev->mode_config.max_width = 16384;
2815 adev->ddev->mode_config.max_height = 16384;
2816 adev->ddev->mode_config.preferred_depth = 24;
2817 adev->ddev->mode_config.prefer_shadow = 1;
2818 adev->ddev->mode_config.fb_base = adev->mc.aper_base;
2820 r = amdgpu_modeset_create_props(adev);
2824 adev->ddev->mode_config.max_width = 16384;
2825 adev->ddev->mode_config.max_height = 16384;
2827 /* allocate crtcs */
2828 for (i = 0; i < adev->mode_info.num_crtc; i++) {
2829 r = dce_v6_0_crtc_init(adev, i);
2834 ret = amdgpu_atombios_get_connector_info_from_object_table(adev);
2836 amdgpu_print_display_setup(adev->ddev);
2841 r = dce_v6_0_afmt_init(adev);
2845 r = dce_v6_0_audio_init(adev);
2849 drm_kms_helper_poll_init(adev->ddev);
2854 static int dce_v6_0_sw_fini(void *handle)
2856 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2858 kfree(adev->mode_info.bios_hardcoded_edid);
2860 drm_kms_helper_poll_fini(adev->ddev);
2862 dce_v6_0_audio_fini(adev);
2863 dce_v6_0_afmt_fini(adev);
2865 drm_mode_config_cleanup(adev->ddev);
2866 adev->mode_info.mode_config_initialized = false;
2871 static int dce_v6_0_hw_init(void *handle)
2874 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2876 /* init dig PHYs, disp eng pll */
2877 amdgpu_atombios_encoder_init_dig(adev);
2878 amdgpu_atombios_crtc_set_disp_eng_pll(adev, adev->clock.default_dispclk);
2880 /* initialize hpd */
2881 dce_v6_0_hpd_init(adev);
2883 for (i = 0; i < adev->mode_info.audio.num_pins; i++) {
2884 dce_v6_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false);
2887 dce_v6_0_pageflip_interrupt_init(adev);
2892 static int dce_v6_0_hw_fini(void *handle)
2895 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2897 dce_v6_0_hpd_fini(adev);
2899 for (i = 0; i < adev->mode_info.audio.num_pins; i++) {
2900 dce_v6_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false);
2903 dce_v6_0_pageflip_interrupt_fini(adev);
2908 static int dce_v6_0_suspend(void *handle)
2910 return dce_v6_0_hw_fini(handle);
2913 static int dce_v6_0_resume(void *handle)
2915 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2918 ret = dce_v6_0_hw_init(handle);
2920 /* turn on the BL */
2921 if (adev->mode_info.bl_encoder) {
2922 u8 bl_level = amdgpu_display_backlight_get_level(adev,
2923 adev->mode_info.bl_encoder);
2924 amdgpu_display_backlight_set_level(adev, adev->mode_info.bl_encoder,
2931 static bool dce_v6_0_is_idle(void *handle)
2936 static int dce_v6_0_wait_for_idle(void *handle)
2941 static int dce_v6_0_soft_reset(void *handle)
2943 DRM_INFO("xxxx: dce_v6_0_soft_reset --- no impl!!\n");
2947 static void dce_v6_0_set_crtc_vblank_interrupt_state(struct amdgpu_device *adev,
2949 enum amdgpu_interrupt_state state)
2951 u32 reg_block, interrupt_mask;
2953 if (crtc >= adev->mode_info.num_crtc) {
2954 DRM_DEBUG("invalid crtc %d\n", crtc);
2960 reg_block = SI_CRTC0_REGISTER_OFFSET;
2963 reg_block = SI_CRTC1_REGISTER_OFFSET;
2966 reg_block = SI_CRTC2_REGISTER_OFFSET;
2969 reg_block = SI_CRTC3_REGISTER_OFFSET;
2972 reg_block = SI_CRTC4_REGISTER_OFFSET;
2975 reg_block = SI_CRTC5_REGISTER_OFFSET;
2978 DRM_DEBUG("invalid crtc %d\n", crtc);
2983 case AMDGPU_IRQ_STATE_DISABLE:
2984 interrupt_mask = RREG32(mmINT_MASK + reg_block);
2985 interrupt_mask &= ~VBLANK_INT_MASK;
2986 WREG32(mmINT_MASK + reg_block, interrupt_mask);
2988 case AMDGPU_IRQ_STATE_ENABLE:
2989 interrupt_mask = RREG32(mmINT_MASK + reg_block);
2990 interrupt_mask |= VBLANK_INT_MASK;
2991 WREG32(mmINT_MASK + reg_block, interrupt_mask);
2998 static void dce_v6_0_set_crtc_vline_interrupt_state(struct amdgpu_device *adev,
3000 enum amdgpu_interrupt_state state)
3005 static int dce_v6_0_set_hpd_interrupt_state(struct amdgpu_device *adev,
3006 struct amdgpu_irq_src *src,
3008 enum amdgpu_interrupt_state state)
3010 u32 dc_hpd_int_cntl;
3012 if (type >= adev->mode_info.num_hpd) {
3013 DRM_DEBUG("invalid hdp %d\n", type);
3018 case AMDGPU_IRQ_STATE_DISABLE:
3019 dc_hpd_int_cntl = RREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[type]);
3020 dc_hpd_int_cntl &= ~DC_HPDx_INT_EN;
3021 WREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[type], dc_hpd_int_cntl);
3023 case AMDGPU_IRQ_STATE_ENABLE:
3024 dc_hpd_int_cntl = RREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[type]);
3025 dc_hpd_int_cntl |= DC_HPDx_INT_EN;
3026 WREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[type], dc_hpd_int_cntl);
3035 static int dce_v6_0_set_crtc_interrupt_state(struct amdgpu_device *adev,
3036 struct amdgpu_irq_src *src,
3038 enum amdgpu_interrupt_state state)
3041 case AMDGPU_CRTC_IRQ_VBLANK1:
3042 dce_v6_0_set_crtc_vblank_interrupt_state(adev, 0, state);
3044 case AMDGPU_CRTC_IRQ_VBLANK2:
3045 dce_v6_0_set_crtc_vblank_interrupt_state(adev, 1, state);
3047 case AMDGPU_CRTC_IRQ_VBLANK3:
3048 dce_v6_0_set_crtc_vblank_interrupt_state(adev, 2, state);
3050 case AMDGPU_CRTC_IRQ_VBLANK4:
3051 dce_v6_0_set_crtc_vblank_interrupt_state(adev, 3, state);
3053 case AMDGPU_CRTC_IRQ_VBLANK5:
3054 dce_v6_0_set_crtc_vblank_interrupt_state(adev, 4, state);
3056 case AMDGPU_CRTC_IRQ_VBLANK6:
3057 dce_v6_0_set_crtc_vblank_interrupt_state(adev, 5, state);
3059 case AMDGPU_CRTC_IRQ_VLINE1:
3060 dce_v6_0_set_crtc_vline_interrupt_state(adev, 0, state);
3062 case AMDGPU_CRTC_IRQ_VLINE2:
3063 dce_v6_0_set_crtc_vline_interrupt_state(adev, 1, state);
3065 case AMDGPU_CRTC_IRQ_VLINE3:
3066 dce_v6_0_set_crtc_vline_interrupt_state(adev, 2, state);
3068 case AMDGPU_CRTC_IRQ_VLINE4:
3069 dce_v6_0_set_crtc_vline_interrupt_state(adev, 3, state);
3071 case AMDGPU_CRTC_IRQ_VLINE5:
3072 dce_v6_0_set_crtc_vline_interrupt_state(adev, 4, state);
3074 case AMDGPU_CRTC_IRQ_VLINE6:
3075 dce_v6_0_set_crtc_vline_interrupt_state(adev, 5, state);
3083 static int dce_v6_0_crtc_irq(struct amdgpu_device *adev,
3084 struct amdgpu_irq_src *source,
3085 struct amdgpu_iv_entry *entry)
3087 unsigned crtc = entry->src_id - 1;
3088 uint32_t disp_int = RREG32(interrupt_status_offsets[crtc].reg);
3089 unsigned irq_type = amdgpu_crtc_idx_to_irq_type(adev, crtc);
3091 switch (entry->src_data[0]) {
3092 case 0: /* vblank */
3093 if (disp_int & interrupt_status_offsets[crtc].vblank)
3094 WREG32(mmVBLANK_STATUS + crtc_offsets[crtc], VBLANK_ACK);
3096 DRM_DEBUG("IH: IH event w/o asserted irq bit?\n");
3098 if (amdgpu_irq_enabled(adev, source, irq_type)) {
3099 drm_handle_vblank(adev->ddev, crtc);
3101 DRM_DEBUG("IH: D%d vblank\n", crtc + 1);
3104 if (disp_int & interrupt_status_offsets[crtc].vline)
3105 WREG32(mmVLINE_STATUS + crtc_offsets[crtc], VLINE_ACK);
3107 DRM_DEBUG("IH: IH event w/o asserted irq bit?\n");
3109 DRM_DEBUG("IH: D%d vline\n", crtc + 1);
3112 DRM_DEBUG("Unhandled interrupt: %d %d\n", entry->src_id, entry->src_data[0]);
3119 static int dce_v6_0_set_pageflip_interrupt_state(struct amdgpu_device *adev,
3120 struct amdgpu_irq_src *src,
3122 enum amdgpu_interrupt_state state)
3126 if (type >= adev->mode_info.num_crtc) {
3127 DRM_ERROR("invalid pageflip crtc %d\n", type);
3131 reg = RREG32(mmGRPH_INTERRUPT_CONTROL + crtc_offsets[type]);
3132 if (state == AMDGPU_IRQ_STATE_DISABLE)
3133 WREG32(mmGRPH_INTERRUPT_CONTROL + crtc_offsets[type],
3134 reg & ~GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK);
3136 WREG32(mmGRPH_INTERRUPT_CONTROL + crtc_offsets[type],
3137 reg | GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK);
3142 static int dce_v6_0_pageflip_irq(struct amdgpu_device *adev,
3143 struct amdgpu_irq_src *source,
3144 struct amdgpu_iv_entry *entry)
3146 unsigned long flags;
3148 struct amdgpu_crtc *amdgpu_crtc;
3149 struct amdgpu_flip_work *works;
3151 crtc_id = (entry->src_id - 8) >> 1;
3152 amdgpu_crtc = adev->mode_info.crtcs[crtc_id];
3154 if (crtc_id >= adev->mode_info.num_crtc) {
3155 DRM_ERROR("invalid pageflip crtc %d\n", crtc_id);
3159 if (RREG32(mmGRPH_INTERRUPT_STATUS + crtc_offsets[crtc_id]) &
3160 GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_OCCURRED_MASK)
3161 WREG32(mmGRPH_INTERRUPT_STATUS + crtc_offsets[crtc_id],
3162 GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_CLEAR_MASK);
3164 /* IRQ could occur when in initial stage */
3165 if (amdgpu_crtc == NULL)
3168 spin_lock_irqsave(&adev->ddev->event_lock, flags);
3169 works = amdgpu_crtc->pflip_works;
3170 if (amdgpu_crtc->pflip_status != AMDGPU_FLIP_SUBMITTED){
3171 DRM_DEBUG_DRIVER("amdgpu_crtc->pflip_status = %d != "
3172 "AMDGPU_FLIP_SUBMITTED(%d)\n",
3173 amdgpu_crtc->pflip_status,
3174 AMDGPU_FLIP_SUBMITTED);
3175 spin_unlock_irqrestore(&adev->ddev->event_lock, flags);
3179 /* page flip completed. clean up */
3180 amdgpu_crtc->pflip_status = AMDGPU_FLIP_NONE;
3181 amdgpu_crtc->pflip_works = NULL;
3183 /* wakeup usersapce */
3185 drm_crtc_send_vblank_event(&amdgpu_crtc->base, works->event);
3187 spin_unlock_irqrestore(&adev->ddev->event_lock, flags);
3189 drm_crtc_vblank_put(&amdgpu_crtc->base);
3190 schedule_work(&works->unpin_work);
3195 static int dce_v6_0_hpd_irq(struct amdgpu_device *adev,
3196 struct amdgpu_irq_src *source,
3197 struct amdgpu_iv_entry *entry)
3199 uint32_t disp_int, mask, tmp;
3202 if (entry->src_data[0] >= adev->mode_info.num_hpd) {
3203 DRM_DEBUG("Unhandled interrupt: %d %d\n", entry->src_id, entry->src_data[0]);
3207 hpd = entry->src_data[0];
3208 disp_int = RREG32(interrupt_status_offsets[hpd].reg);
3209 mask = interrupt_status_offsets[hpd].hpd;
3211 if (disp_int & mask) {
3212 tmp = RREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[hpd]);
3213 tmp |= DC_HPD1_INT_CONTROL__DC_HPD1_INT_ACK_MASK;
3214 WREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[hpd], tmp);
3215 schedule_work(&adev->hotplug_work);
3216 DRM_INFO("IH: HPD%d\n", hpd + 1);
3223 static int dce_v6_0_set_clockgating_state(void *handle,
3224 enum amd_clockgating_state state)
3229 static int dce_v6_0_set_powergating_state(void *handle,
3230 enum amd_powergating_state state)
3235 static const struct amd_ip_funcs dce_v6_0_ip_funcs = {
3237 .early_init = dce_v6_0_early_init,
3239 .sw_init = dce_v6_0_sw_init,
3240 .sw_fini = dce_v6_0_sw_fini,
3241 .hw_init = dce_v6_0_hw_init,
3242 .hw_fini = dce_v6_0_hw_fini,
3243 .suspend = dce_v6_0_suspend,
3244 .resume = dce_v6_0_resume,
3245 .is_idle = dce_v6_0_is_idle,
3246 .wait_for_idle = dce_v6_0_wait_for_idle,
3247 .soft_reset = dce_v6_0_soft_reset,
3248 .set_clockgating_state = dce_v6_0_set_clockgating_state,
3249 .set_powergating_state = dce_v6_0_set_powergating_state,
3253 dce_v6_0_encoder_mode_set(struct drm_encoder *encoder,
3254 struct drm_display_mode *mode,
3255 struct drm_display_mode *adjusted_mode)
3258 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
3259 int em = amdgpu_atombios_encoder_get_encoder_mode(encoder);
3261 amdgpu_encoder->pixel_clock = adjusted_mode->clock;
3263 /* need to call this here rather than in prepare() since we need some crtc info */
3264 amdgpu_atombios_encoder_dpms(encoder, DRM_MODE_DPMS_OFF);
3266 /* set scaler clears this on some chips */
3267 dce_v6_0_set_interleave(encoder->crtc, mode);
3269 if (em == ATOM_ENCODER_MODE_HDMI || ENCODER_MODE_IS_DP(em)) {
3270 dce_v6_0_afmt_enable(encoder, true);
3271 dce_v6_0_afmt_setmode(encoder, adjusted_mode);
3275 static void dce_v6_0_encoder_prepare(struct drm_encoder *encoder)
3278 struct amdgpu_device *adev = encoder->dev->dev_private;
3279 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
3280 struct drm_connector *connector = amdgpu_get_connector_for_encoder(encoder);
3282 if ((amdgpu_encoder->active_device &
3283 (ATOM_DEVICE_DFP_SUPPORT | ATOM_DEVICE_LCD_SUPPORT)) ||
3284 (amdgpu_encoder_get_dp_bridge_encoder_id(encoder) !=
3285 ENCODER_OBJECT_ID_NONE)) {
3286 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
3288 dig->dig_encoder = dce_v6_0_pick_dig_encoder(encoder);
3289 if (amdgpu_encoder->active_device & ATOM_DEVICE_DFP_SUPPORT)
3290 dig->afmt = adev->mode_info.afmt[dig->dig_encoder];
3294 amdgpu_atombios_scratch_regs_lock(adev, true);
3297 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
3299 /* select the clock/data port if it uses a router */
3300 if (amdgpu_connector->router.cd_valid)
3301 amdgpu_i2c_router_select_cd_port(amdgpu_connector);
3303 /* turn eDP panel on for mode set */
3304 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP)
3305 amdgpu_atombios_encoder_set_edp_panel_power(connector,
3306 ATOM_TRANSMITTER_ACTION_POWER_ON);
3309 /* this is needed for the pll/ss setup to work correctly in some cases */
3310 amdgpu_atombios_encoder_set_crtc_source(encoder);
3311 /* set up the FMT blocks */
3312 dce_v6_0_program_fmt(encoder);
3315 static void dce_v6_0_encoder_commit(struct drm_encoder *encoder)
3318 struct drm_device *dev = encoder->dev;
3319 struct amdgpu_device *adev = dev->dev_private;
3321 /* need to call this here as we need the crtc set up */
3322 amdgpu_atombios_encoder_dpms(encoder, DRM_MODE_DPMS_ON);
3323 amdgpu_atombios_scratch_regs_lock(adev, false);
3326 static void dce_v6_0_encoder_disable(struct drm_encoder *encoder)
3329 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
3330 struct amdgpu_encoder_atom_dig *dig;
3331 int em = amdgpu_atombios_encoder_get_encoder_mode(encoder);
3333 amdgpu_atombios_encoder_dpms(encoder, DRM_MODE_DPMS_OFF);
3335 if (amdgpu_atombios_encoder_is_digital(encoder)) {
3336 if (em == ATOM_ENCODER_MODE_HDMI || ENCODER_MODE_IS_DP(em))
3337 dce_v6_0_afmt_enable(encoder, false);
3338 dig = amdgpu_encoder->enc_priv;
3339 dig->dig_encoder = -1;
3341 amdgpu_encoder->active_device = 0;
3344 /* these are handled by the primary encoders */
3345 static void dce_v6_0_ext_prepare(struct drm_encoder *encoder)
3350 static void dce_v6_0_ext_commit(struct drm_encoder *encoder)
3356 dce_v6_0_ext_mode_set(struct drm_encoder *encoder,
3357 struct drm_display_mode *mode,
3358 struct drm_display_mode *adjusted_mode)
3363 static void dce_v6_0_ext_disable(struct drm_encoder *encoder)
3369 dce_v6_0_ext_dpms(struct drm_encoder *encoder, int mode)
3374 static bool dce_v6_0_ext_mode_fixup(struct drm_encoder *encoder,
3375 const struct drm_display_mode *mode,
3376 struct drm_display_mode *adjusted_mode)
3381 static const struct drm_encoder_helper_funcs dce_v6_0_ext_helper_funcs = {
3382 .dpms = dce_v6_0_ext_dpms,
3383 .mode_fixup = dce_v6_0_ext_mode_fixup,
3384 .prepare = dce_v6_0_ext_prepare,
3385 .mode_set = dce_v6_0_ext_mode_set,
3386 .commit = dce_v6_0_ext_commit,
3387 .disable = dce_v6_0_ext_disable,
3388 /* no detect for TMDS/LVDS yet */
3391 static const struct drm_encoder_helper_funcs dce_v6_0_dig_helper_funcs = {
3392 .dpms = amdgpu_atombios_encoder_dpms,
3393 .mode_fixup = amdgpu_atombios_encoder_mode_fixup,
3394 .prepare = dce_v6_0_encoder_prepare,
3395 .mode_set = dce_v6_0_encoder_mode_set,
3396 .commit = dce_v6_0_encoder_commit,
3397 .disable = dce_v6_0_encoder_disable,
3398 .detect = amdgpu_atombios_encoder_dig_detect,
3401 static const struct drm_encoder_helper_funcs dce_v6_0_dac_helper_funcs = {
3402 .dpms = amdgpu_atombios_encoder_dpms,
3403 .mode_fixup = amdgpu_atombios_encoder_mode_fixup,
3404 .prepare = dce_v6_0_encoder_prepare,
3405 .mode_set = dce_v6_0_encoder_mode_set,
3406 .commit = dce_v6_0_encoder_commit,
3407 .detect = amdgpu_atombios_encoder_dac_detect,
3410 static void dce_v6_0_encoder_destroy(struct drm_encoder *encoder)
3412 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
3413 if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
3414 amdgpu_atombios_encoder_fini_backlight(amdgpu_encoder);
3415 kfree(amdgpu_encoder->enc_priv);
3416 drm_encoder_cleanup(encoder);
3417 kfree(amdgpu_encoder);
3420 static const struct drm_encoder_funcs dce_v6_0_encoder_funcs = {
3421 .destroy = dce_v6_0_encoder_destroy,
3424 static void dce_v6_0_encoder_add(struct amdgpu_device *adev,
3425 uint32_t encoder_enum,
3426 uint32_t supported_device,
3429 struct drm_device *dev = adev->ddev;
3430 struct drm_encoder *encoder;
3431 struct amdgpu_encoder *amdgpu_encoder;
3433 /* see if we already added it */
3434 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
3435 amdgpu_encoder = to_amdgpu_encoder(encoder);
3436 if (amdgpu_encoder->encoder_enum == encoder_enum) {
3437 amdgpu_encoder->devices |= supported_device;
3444 amdgpu_encoder = kzalloc(sizeof(struct amdgpu_encoder), GFP_KERNEL);
3445 if (!amdgpu_encoder)
3448 encoder = &amdgpu_encoder->base;
3449 switch (adev->mode_info.num_crtc) {
3451 encoder->possible_crtcs = 0x1;
3455 encoder->possible_crtcs = 0x3;
3458 encoder->possible_crtcs = 0xf;
3461 encoder->possible_crtcs = 0x3f;
3465 amdgpu_encoder->enc_priv = NULL;
3466 amdgpu_encoder->encoder_enum = encoder_enum;
3467 amdgpu_encoder->encoder_id = (encoder_enum & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT;
3468 amdgpu_encoder->devices = supported_device;
3469 amdgpu_encoder->rmx_type = RMX_OFF;
3470 amdgpu_encoder->underscan_type = UNDERSCAN_OFF;
3471 amdgpu_encoder->is_ext_encoder = false;
3472 amdgpu_encoder->caps = caps;
3474 switch (amdgpu_encoder->encoder_id) {
3475 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
3476 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
3477 drm_encoder_init(dev, encoder, &dce_v6_0_encoder_funcs,
3478 DRM_MODE_ENCODER_DAC, NULL);
3479 drm_encoder_helper_add(encoder, &dce_v6_0_dac_helper_funcs);
3481 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
3482 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
3483 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
3484 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
3485 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
3486 if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
3487 amdgpu_encoder->rmx_type = RMX_FULL;
3488 drm_encoder_init(dev, encoder, &dce_v6_0_encoder_funcs,
3489 DRM_MODE_ENCODER_LVDS, NULL);
3490 amdgpu_encoder->enc_priv = amdgpu_atombios_encoder_get_lcd_info(amdgpu_encoder);
3491 } else if (amdgpu_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT)) {
3492 drm_encoder_init(dev, encoder, &dce_v6_0_encoder_funcs,
3493 DRM_MODE_ENCODER_DAC, NULL);
3494 amdgpu_encoder->enc_priv = amdgpu_atombios_encoder_get_dig_info(amdgpu_encoder);
3496 drm_encoder_init(dev, encoder, &dce_v6_0_encoder_funcs,
3497 DRM_MODE_ENCODER_TMDS, NULL);
3498 amdgpu_encoder->enc_priv = amdgpu_atombios_encoder_get_dig_info(amdgpu_encoder);
3500 drm_encoder_helper_add(encoder, &dce_v6_0_dig_helper_funcs);
3502 case ENCODER_OBJECT_ID_SI170B:
3503 case ENCODER_OBJECT_ID_CH7303:
3504 case ENCODER_OBJECT_ID_EXTERNAL_SDVOA:
3505 case ENCODER_OBJECT_ID_EXTERNAL_SDVOB:
3506 case ENCODER_OBJECT_ID_TITFP513:
3507 case ENCODER_OBJECT_ID_VT1623:
3508 case ENCODER_OBJECT_ID_HDMI_SI1930:
3509 case ENCODER_OBJECT_ID_TRAVIS:
3510 case ENCODER_OBJECT_ID_NUTMEG:
3511 /* these are handled by the primary encoders */
3512 amdgpu_encoder->is_ext_encoder = true;
3513 if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
3514 drm_encoder_init(dev, encoder, &dce_v6_0_encoder_funcs,
3515 DRM_MODE_ENCODER_LVDS, NULL);
3516 else if (amdgpu_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT))
3517 drm_encoder_init(dev, encoder, &dce_v6_0_encoder_funcs,
3518 DRM_MODE_ENCODER_DAC, NULL);
3520 drm_encoder_init(dev, encoder, &dce_v6_0_encoder_funcs,
3521 DRM_MODE_ENCODER_TMDS, NULL);
3522 drm_encoder_helper_add(encoder, &dce_v6_0_ext_helper_funcs);
3527 static const struct amdgpu_display_funcs dce_v6_0_display_funcs = {
3528 .set_vga_render_state = &dce_v6_0_set_vga_render_state,
3529 .bandwidth_update = &dce_v6_0_bandwidth_update,
3530 .vblank_get_counter = &dce_v6_0_vblank_get_counter,
3531 .vblank_wait = &dce_v6_0_vblank_wait,
3532 .backlight_set_level = &amdgpu_atombios_encoder_set_backlight_level,
3533 .backlight_get_level = &amdgpu_atombios_encoder_get_backlight_level,
3534 .hpd_sense = &dce_v6_0_hpd_sense,
3535 .hpd_set_polarity = &dce_v6_0_hpd_set_polarity,
3536 .hpd_get_gpio_reg = &dce_v6_0_hpd_get_gpio_reg,
3537 .page_flip = &dce_v6_0_page_flip,
3538 .page_flip_get_scanoutpos = &dce_v6_0_crtc_get_scanoutpos,
3539 .add_encoder = &dce_v6_0_encoder_add,
3540 .add_connector = &amdgpu_connector_add,
3541 .stop_mc_access = &dce_v6_0_stop_mc_access,
3542 .resume_mc_access = &dce_v6_0_resume_mc_access,
3545 static void dce_v6_0_set_display_funcs(struct amdgpu_device *adev)
3547 if (adev->mode_info.funcs == NULL)
3548 adev->mode_info.funcs = &dce_v6_0_display_funcs;
3551 static const struct amdgpu_irq_src_funcs dce_v6_0_crtc_irq_funcs = {
3552 .set = dce_v6_0_set_crtc_interrupt_state,
3553 .process = dce_v6_0_crtc_irq,
3556 static const struct amdgpu_irq_src_funcs dce_v6_0_pageflip_irq_funcs = {
3557 .set = dce_v6_0_set_pageflip_interrupt_state,
3558 .process = dce_v6_0_pageflip_irq,
3561 static const struct amdgpu_irq_src_funcs dce_v6_0_hpd_irq_funcs = {
3562 .set = dce_v6_0_set_hpd_interrupt_state,
3563 .process = dce_v6_0_hpd_irq,
3566 static void dce_v6_0_set_irq_funcs(struct amdgpu_device *adev)
3568 adev->crtc_irq.num_types = AMDGPU_CRTC_IRQ_LAST;
3569 adev->crtc_irq.funcs = &dce_v6_0_crtc_irq_funcs;
3571 adev->pageflip_irq.num_types = AMDGPU_PAGEFLIP_IRQ_LAST;
3572 adev->pageflip_irq.funcs = &dce_v6_0_pageflip_irq_funcs;
3574 adev->hpd_irq.num_types = AMDGPU_HPD_LAST;
3575 adev->hpd_irq.funcs = &dce_v6_0_hpd_irq_funcs;
3578 const struct amdgpu_ip_block_version dce_v6_0_ip_block =
3580 .type = AMD_IP_BLOCK_TYPE_DCE,
3584 .funcs = &dce_v6_0_ip_funcs,
3587 const struct amdgpu_ip_block_version dce_v6_4_ip_block =
3589 .type = AMD_IP_BLOCK_TYPE_DCE,
3593 .funcs = &dce_v6_0_ip_funcs,