drivers/gpu/drm/amd/amdgpu/cik_sdma.c

   1 /*
   2  * Copyright 2013 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: Alex Deucher
  23  */
  24
  25 #include <linux/firmware.h>
  26 #include <linux/module.h>
  27
  28 #include "amdgpu.h"
  29 #include "amdgpu_ucode.h"
  30 #include "amdgpu_trace.h"
  31 #include "cikd.h"
  32 #include "cik.h"
  33
  34 #include "bif/bif_4_1_d.h"
  35 #include "bif/bif_4_1_sh_mask.h"
  36
  37 #include "gca/gfx_7_2_d.h"
  38 #include "gca/gfx_7_2_enum.h"
  39 #include "gca/gfx_7_2_sh_mask.h"
  40
  41 #include "gmc/gmc_7_1_d.h"
  42 #include "gmc/gmc_7_1_sh_mask.h"
  43
  44 #include "oss/oss_2_0_d.h"
  45 #include "oss/oss_2_0_sh_mask.h"
  46
  47 static const u32 sdma_offsets[SDMA_MAX_INSTANCE] =
  48 {
  49         SDMA0_REGISTER_OFFSET,
  50         SDMA1_REGISTER_OFFSET
  51 };
  52
  53 static void cik_sdma_set_ring_funcs(struct amdgpu_device *adev);
  54 static void cik_sdma_set_irq_funcs(struct amdgpu_device *adev);
  55 static void cik_sdma_set_buffer_funcs(struct amdgpu_device *adev);
  56 static void cik_sdma_set_vm_pte_funcs(struct amdgpu_device *adev);
  57 static int cik_sdma_soft_reset(void *handle);
  58
  59 MODULE_FIRMWARE("amdgpu/bonaire_sdma.bin");
  60 MODULE_FIRMWARE("amdgpu/bonaire_sdma1.bin");
  61 MODULE_FIRMWARE("amdgpu/hawaii_sdma.bin");
  62 MODULE_FIRMWARE("amdgpu/hawaii_sdma1.bin");
  63 MODULE_FIRMWARE("amdgpu/kaveri_sdma.bin");
  64 MODULE_FIRMWARE("amdgpu/kaveri_sdma1.bin");
  65 MODULE_FIRMWARE("amdgpu/kabini_sdma.bin");
  66 MODULE_FIRMWARE("amdgpu/kabini_sdma1.bin");
  67 MODULE_FIRMWARE("amdgpu/mullins_sdma.bin");
  68 MODULE_FIRMWARE("amdgpu/mullins_sdma1.bin");
  69
  70 u32 amdgpu_cik_gpu_check_soft_reset(struct amdgpu_device *adev);
  71
  72
  73 static void cik_sdma_free_microcode(struct amdgpu_device *adev)
  74 {
  75         int i;
  76
  77         for (i = 0; i < adev->sdma.num_instances; i++)
  78                 amdgpu_ucode_release(&adev->sdma.instance[i].fw);
  79 }
  80
  81 /*
  82  * sDMA - System DMA
  83  * Starting with CIK, the GPU has new asynchronous
  84  * DMA engines.  These engines are used for compute
  85  * and gfx.  There are two DMA engines (SDMA0, SDMA1)
  86  * and each one supports 1 ring buffer used for gfx
  87  * and 2 queues used for compute.
  88  *
  89  * The programming model is very similar to the CP
  90  * (ring buffer, IBs, etc.), but sDMA has it's own
  91  * packet format that is different from the PM4 format
  92  * used by the CP. sDMA supports copying data, writing
  93  * embedded data, solid fills, and a number of other
  94  * things.  It also has support for tiling/detiling of
  95  * buffers.
  96  */
  97
  98 /**
  99  * cik_sdma_init_microcode - load ucode images from disk
 100  *
 101  * @adev: amdgpu_device pointer
 102  *
 103  * Use the firmware interface to load the ucode images into
 104  * the driver (not loaded into hw).
 105  * Returns 0 on success, error on failure.
 106  */
 107 static int cik_sdma_init_microcode(struct amdgpu_device *adev)
 108 {
 109         const char *chip_name;
 110         char fw_name[30];
 111         int err = 0, i;
 112
 113         DRM_DEBUG("\n");
 114
 115         switch (adev->asic_type) {
 116         case CHIP_BONAIRE:
 117                 chip_name = "bonaire";
 118                 break;
 119         case CHIP_HAWAII:
 120                 chip_name = "hawaii";
 121                 break;
 122         case CHIP_KAVERI:
 123                 chip_name = "kaveri";
 124                 break;
 125         case CHIP_KABINI:
 126                 chip_name = "kabini";
 127                 break;
 128         case CHIP_MULLINS:
 129                 chip_name = "mullins";
 130                 break;
 131         default: BUG();
 132         }
 133
 134         for (i = 0; i < adev->sdma.num_instances; i++) {
 135                 if (i == 0)
 136                         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sdma.bin", chip_name);
 137                 else
 138                         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sdma1.bin", chip_name);
 139                 err = amdgpu_ucode_request(adev, &adev->sdma.instance[i].fw, fw_name);
 140                 if (err)
 141                         goto out;
 142         }
 143 out:
 144         if (err) {
 145                 pr_err("cik_sdma: Failed to load firmware \"%s\"\n", fw_name);
 146                 for (i = 0; i < adev->sdma.num_instances; i++)
 147                         amdgpu_ucode_release(&adev->sdma.instance[i].fw);
 148         }
 149         return err;
 150 }
 151
 152 /**
 153  * cik_sdma_ring_get_rptr - get the current read pointer
 154  *
 155  * @ring: amdgpu ring pointer
 156  *
 157  * Get the current rptr from the hardware (CIK+).
 158  */
 159 static uint64_t cik_sdma_ring_get_rptr(struct amdgpu_ring *ring)
 160 {
 161         u32 rptr;
 162
 163         rptr = *ring->rptr_cpu_addr;
 164
 165         return (rptr & 0x3fffc) >> 2;
 166 }
 167
 168 /**
 169  * cik_sdma_ring_get_wptr - get the current write pointer
 170  *
 171  * @ring: amdgpu ring pointer
 172  *
 173  * Get the current wptr from the hardware (CIK+).
 174  */
 175 static uint64_t cik_sdma_ring_get_wptr(struct amdgpu_ring *ring)
 176 {
 177         struct amdgpu_device *adev = ring->adev;
 178
 179         return (RREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[ring->me]) & 0x3fffc) >> 2;
 180 }
 181
 182 /**
 183  * cik_sdma_ring_set_wptr - commit the write pointer
 184  *
 185  * @ring: amdgpu ring pointer
 186  *
 187  * Write the wptr back to the hardware (CIK+).
 188  */
 189 static void cik_sdma_ring_set_wptr(struct amdgpu_ring *ring)
 190 {
 191         struct amdgpu_device *adev = ring->adev;
 192
 193         WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[ring->me],
 194                (ring->wptr << 2) & 0x3fffc);
 195 }
 196
 197 static void cik_sdma_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count)
 198 {
 199         struct amdgpu_sdma_instance *sdma = amdgpu_sdma_get_instance_from_ring(ring);
 200         int i;
 201
 202         for (i = 0; i < count; i++)
 203                 if (sdma && sdma->burst_nop && (i == 0))
 204                         amdgpu_ring_write(ring, ring->funcs->nop |
 205                                           SDMA_NOP_COUNT(count - 1));
 206                 else
 207                         amdgpu_ring_write(ring, ring->funcs->nop);
 208 }
 209
 210 /**
 211  * cik_sdma_ring_emit_ib - Schedule an IB on the DMA engine
 212  *
 213  * @ring: amdgpu ring pointer
 214  * @job: job to retrive vmid from
 215  * @ib: IB object to schedule
 216  * @flags: unused
 217  *
 218  * Schedule an IB in the DMA ring (CIK).
 219  */
 220 static void cik_sdma_ring_emit_ib(struct amdgpu_ring *ring,
 221                                   struct amdgpu_job *job,
 222                                   struct amdgpu_ib *ib,
 223                                   uint32_t flags)
 224 {
 225         unsigned vmid = AMDGPU_JOB_GET_VMID(job);
 226         u32 extra_bits = vmid & 0xf;
 227
 228         /* IB packet must end on a 8 DW boundary */
 229         cik_sdma_ring_insert_nop(ring, (4 - lower_32_bits(ring->wptr)) & 7);
 230
 231         amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_INDIRECT_BUFFER, 0, extra_bits));
 232         amdgpu_ring_write(ring, ib->gpu_addr & 0xffffffe0); /* base must be 32 byte aligned */
 233         amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xffffffff);
 234         amdgpu_ring_write(ring, ib->length_dw);
 235
 236 }
 237
 238 /**
 239  * cik_sdma_ring_emit_hdp_flush - emit an hdp flush on the DMA ring
 240  *
 241  * @ring: amdgpu ring pointer
 242  *
 243  * Emit an hdp flush packet on the requested DMA ring.
 244  */
 245 static void cik_sdma_ring_emit_hdp_flush(struct amdgpu_ring *ring)
 246 {
 247         u32 extra_bits = (SDMA_POLL_REG_MEM_EXTRA_OP(1) |
 248                           SDMA_POLL_REG_MEM_EXTRA_FUNC(3)); /* == */
 249         u32 ref_and_mask;
 250
 251         if (ring->me == 0)
 252                 ref_and_mask = GPU_HDP_FLUSH_DONE__SDMA0_MASK;
 253         else
 254                 ref_and_mask = GPU_HDP_FLUSH_DONE__SDMA1_MASK;
 255
 256         amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_POLL_REG_MEM, 0, extra_bits));
 257         amdgpu_ring_write(ring, mmGPU_HDP_FLUSH_DONE << 2);
 258         amdgpu_ring_write(ring, mmGPU_HDP_FLUSH_REQ << 2);
 259         amdgpu_ring_write(ring, ref_and_mask); /* reference */
 260         amdgpu_ring_write(ring, ref_and_mask); /* mask */
 261         amdgpu_ring_write(ring, (0xfff << 16) | 10); /* retry count, poll interval */
 262 }
 263
 264 /**
 265  * cik_sdma_ring_emit_fence - emit a fence on the DMA ring
 266  *
 267  * @ring: amdgpu ring pointer
 268  * @addr: address
 269  * @seq: sequence number
 270  * @flags: fence related flags
 271  *
 272  * Add a DMA fence packet to the ring to write
 273  * the fence seq number and DMA trap packet to generate
 274  * an interrupt if needed (CIK).
 275  */
 276 static void cik_sdma_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq,
 277                                      unsigned flags)
 278 {
 279         bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT;
 280         /* write the fence */
 281         amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_FENCE, 0, 0));
 282         amdgpu_ring_write(ring, lower_32_bits(addr));
 283         amdgpu_ring_write(ring, upper_32_bits(addr));
 284         amdgpu_ring_write(ring, lower_32_bits(seq));
 285
 286         /* optionally write high bits as well */
 287         if (write64bit) {
 288                 addr += 4;
 289                 amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_FENCE, 0, 0));
 290                 amdgpu_ring_write(ring, lower_32_bits(addr));
 291                 amdgpu_ring_write(ring, upper_32_bits(addr));
 292                 amdgpu_ring_write(ring, upper_32_bits(seq));
 293         }
 294
 295         /* generate an interrupt */
 296         amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_TRAP, 0, 0));
 297 }
 298
 299 /**
 300  * cik_sdma_gfx_stop - stop the gfx async dma engines
 301  *
 302  * @adev: amdgpu_device pointer
 303  *
 304  * Stop the gfx async dma ring buffers (CIK).
 305  */
 306 static void cik_sdma_gfx_stop(struct amdgpu_device *adev)
 307 {
 308         u32 rb_cntl;
 309         int i;
 310
 311         amdgpu_sdma_unset_buffer_funcs_helper(adev);
 312
 313         for (i = 0; i < adev->sdma.num_instances; i++) {
 314                 rb_cntl = RREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i]);
 315                 rb_cntl &= ~SDMA0_GFX_RB_CNTL__RB_ENABLE_MASK;
 316                 WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], rb_cntl);
 317                 WREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i], 0);
 318         }
 319 }
 320
 321 /**
 322  * cik_sdma_rlc_stop - stop the compute async dma engines
 323  *
 324  * @adev: amdgpu_device pointer
 325  *
 326  * Stop the compute async dma queues (CIK).
 327  */
 328 static void cik_sdma_rlc_stop(struct amdgpu_device *adev)
 329 {
 330         /* XXX todo */
 331 }
 332
 333 /**
 334  * cik_ctx_switch_enable - stop the async dma engines context switch
 335  *
 336  * @adev: amdgpu_device pointer
 337  * @enable: enable/disable the DMA MEs context switch.
 338  *
 339  * Halt or unhalt the async dma engines context switch (VI).
 340  */
 341 static void cik_ctx_switch_enable(struct amdgpu_device *adev, bool enable)
 342 {
 343         u32 f32_cntl, phase_quantum = 0;
 344         int i;
 345
 346         if (amdgpu_sdma_phase_quantum) {
 347                 unsigned value = amdgpu_sdma_phase_quantum;
 348                 unsigned unit = 0;
 349
 350                 while (value > (SDMA0_PHASE0_QUANTUM__VALUE_MASK >>
 351                                 SDMA0_PHASE0_QUANTUM__VALUE__SHIFT)) {
 352                         value = (value + 1) >> 1;
 353                         unit++;
 354                 }
 355                 if (unit > (SDMA0_PHASE0_QUANTUM__UNIT_MASK >>
 356                             SDMA0_PHASE0_QUANTUM__UNIT__SHIFT)) {
 357                         value = (SDMA0_PHASE0_QUANTUM__VALUE_MASK >>
 358                                  SDMA0_PHASE0_QUANTUM__VALUE__SHIFT);
 359                         unit = (SDMA0_PHASE0_QUANTUM__UNIT_MASK >>
 360                                 SDMA0_PHASE0_QUANTUM__UNIT__SHIFT);
 361                         WARN_ONCE(1,
 362                         "clamping sdma_phase_quantum to %uK clock cycles\n",
 363                                   value << unit);
 364                 }
 365                 phase_quantum =
 366                         value << SDMA0_PHASE0_QUANTUM__VALUE__SHIFT |
 367                         unit  << SDMA0_PHASE0_QUANTUM__UNIT__SHIFT;
 368         }
 369
 370         for (i = 0; i < adev->sdma.num_instances; i++) {
 371                 f32_cntl = RREG32(mmSDMA0_CNTL + sdma_offsets[i]);
 372                 if (enable) {
 373                         f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL,
 374                                         AUTO_CTXSW_ENABLE, 1);
 375                         if (amdgpu_sdma_phase_quantum) {
 376                                 WREG32(mmSDMA0_PHASE0_QUANTUM + sdma_offsets[i],
 377                                        phase_quantum);
 378                                 WREG32(mmSDMA0_PHASE1_QUANTUM + sdma_offsets[i],
 379                                        phase_quantum);
 380                         }
 381                 } else {
 382                         f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL,
 383                                         AUTO_CTXSW_ENABLE, 0);
 384                 }
 385
 386                 WREG32(mmSDMA0_CNTL + sdma_offsets[i], f32_cntl);
 387         }
 388 }
 389
 390 /**
 391  * cik_sdma_enable - stop the async dma engines
 392  *
 393  * @adev: amdgpu_device pointer
 394  * @enable: enable/disable the DMA MEs.
 395  *
 396  * Halt or unhalt the async dma engines (CIK).
 397  */
 398 static void cik_sdma_enable(struct amdgpu_device *adev, bool enable)
 399 {
 400         u32 me_cntl;
 401         int i;
 402
 403         if (!enable) {
 404                 cik_sdma_gfx_stop(adev);
 405                 cik_sdma_rlc_stop(adev);
 406         }
 407
 408         for (i = 0; i < adev->sdma.num_instances; i++) {
 409                 me_cntl = RREG32(mmSDMA0_F32_CNTL + sdma_offsets[i]);
 410                 if (enable)
 411                         me_cntl &= ~SDMA0_F32_CNTL__HALT_MASK;
 412                 else
 413                         me_cntl |= SDMA0_F32_CNTL__HALT_MASK;
 414                 WREG32(mmSDMA0_F32_CNTL + sdma_offsets[i], me_cntl);
 415         }
 416 }
 417
 418 /**
 419  * cik_sdma_gfx_resume - setup and start the async dma engines
 420  *
 421  * @adev: amdgpu_device pointer
 422  *
 423  * Set up the gfx DMA ring buffers and enable them (CIK).
 424  * Returns 0 for success, error for failure.
 425  */
 426 static int cik_sdma_gfx_resume(struct amdgpu_device *adev)
 427 {
 428         struct amdgpu_ring *ring;
 429         u32 rb_cntl, ib_cntl;
 430         u32 rb_bufsz;
 431         int i, j, r;
 432
 433         for (i = 0; i < adev->sdma.num_instances; i++) {
 434                 ring = &adev->sdma.instance[i].ring;
 435
 436                 mutex_lock(&adev->srbm_mutex);
 437                 for (j = 0; j < 16; j++) {
 438                         cik_srbm_select(adev, 0, 0, 0, j);
 439                         /* SDMA GFX */
 440                         WREG32(mmSDMA0_GFX_VIRTUAL_ADDR + sdma_offsets[i], 0);
 441                         WREG32(mmSDMA0_GFX_APE1_CNTL + sdma_offsets[i], 0);
 442                         /* XXX SDMA RLC - todo */
 443                 }
 444                 cik_srbm_select(adev, 0, 0, 0, 0);
 445                 mutex_unlock(&adev->srbm_mutex);
 446
 447                 WREG32(mmSDMA0_TILING_CONFIG + sdma_offsets[i],
 448                        adev->gfx.config.gb_addr_config & 0x70);
 449
 450                 WREG32(mmSDMA0_SEM_INCOMPLETE_TIMER_CNTL + sdma_offsets[i], 0);
 451                 WREG32(mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL + sdma_offsets[i], 0);
 452
 453                 /* Set ring buffer size in dwords */
 454                 rb_bufsz = order_base_2(ring->ring_size / 4);
 455                 rb_cntl = rb_bufsz << 1;
 456 #ifdef __BIG_ENDIAN
 457                 rb_cntl |= SDMA0_GFX_RB_CNTL__RB_SWAP_ENABLE_MASK |
 458                         SDMA0_GFX_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK;
 459 #endif
 460                 WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], rb_cntl);
 461
 462                 /* Initialize the ring buffer's read and write pointers */
 463                 WREG32(mmSDMA0_GFX_RB_RPTR + sdma_offsets[i], 0);
 464                 WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[i], 0);
 465                 WREG32(mmSDMA0_GFX_IB_RPTR + sdma_offsets[i], 0);
 466                 WREG32(mmSDMA0_GFX_IB_OFFSET + sdma_offsets[i], 0);
 467
 468                 /* set the wb address whether it's enabled or not */
 469                 WREG32(mmSDMA0_GFX_RB_RPTR_ADDR_HI + sdma_offsets[i],
 470                        upper_32_bits(ring->rptr_gpu_addr) & 0xFFFFFFFF);
 471                 WREG32(mmSDMA0_GFX_RB_RPTR_ADDR_LO + sdma_offsets[i],
 472                        ((ring->rptr_gpu_addr) & 0xFFFFFFFC));
 473
 474                 rb_cntl |= SDMA0_GFX_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK;
 475
 476                 WREG32(mmSDMA0_GFX_RB_BASE + sdma_offsets[i], ring->gpu_addr >> 8);
 477                 WREG32(mmSDMA0_GFX_RB_BASE_HI + sdma_offsets[i], ring->gpu_addr >> 40);
 478
 479                 ring->wptr = 0;
 480                 WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[i], ring->wptr << 2);
 481
 482                 /* enable DMA RB */
 483                 WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i],
 484                        rb_cntl | SDMA0_GFX_RB_CNTL__RB_ENABLE_MASK);
 485
 486                 ib_cntl = SDMA0_GFX_IB_CNTL__IB_ENABLE_MASK;
 487 #ifdef __BIG_ENDIAN
 488                 ib_cntl |= SDMA0_GFX_IB_CNTL__IB_SWAP_ENABLE_MASK;
 489 #endif
 490                 /* enable DMA IBs */
 491                 WREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i], ib_cntl);
 492         }
 493
 494         cik_sdma_enable(adev, true);
 495
 496         for (i = 0; i < adev->sdma.num_instances; i++) {
 497                 ring = &adev->sdma.instance[i].ring;
 498                 r = amdgpu_ring_test_helper(ring);
 499                 if (r)
 500                         return r;
 501
 502                 if (adev->mman.buffer_funcs_ring == ring)
 503                         amdgpu_ttm_set_buffer_funcs_status(adev, true);
 504         }
 505
 506         return 0;
 507 }
 508
 509 /**
 510  * cik_sdma_rlc_resume - setup and start the async dma engines
 511  *
 512  * @adev: amdgpu_device pointer
 513  *
 514  * Set up the compute DMA queues and enable them (CIK).
 515  * Returns 0 for success, error for failure.
 516  */
 517 static int cik_sdma_rlc_resume(struct amdgpu_device *adev)
 518 {
 519         /* XXX todo */
 520         return 0;
 521 }
 522
 523 /**
 524  * cik_sdma_load_microcode - load the sDMA ME ucode
 525  *
 526  * @adev: amdgpu_device pointer
 527  *
 528  * Loads the sDMA0/1 ucode.
 529  * Returns 0 for success, -EINVAL if the ucode is not available.
 530  */
 531 static int cik_sdma_load_microcode(struct amdgpu_device *adev)
 532 {
 533         const struct sdma_firmware_header_v1_0 *hdr;
 534         const __le32 *fw_data;
 535         u32 fw_size;
 536         int i, j;
 537
 538         /* halt the MEs */
 539         cik_sdma_enable(adev, false);
 540
 541         for (i = 0; i < adev->sdma.num_instances; i++) {
 542                 if (!adev->sdma.instance[i].fw)
 543                         return -EINVAL;
 544                 hdr = (const struct sdma_firmware_header_v1_0 *)adev->sdma.instance[i].fw->data;
 545                 amdgpu_ucode_print_sdma_hdr(&hdr->header);
 546                 fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
 547                 adev->sdma.instance[i].fw_version = le32_to_cpu(hdr->header.ucode_version);
 548                 adev->sdma.instance[i].feature_version = le32_to_cpu(hdr->ucode_feature_version);
 549                 if (adev->sdma.instance[i].feature_version >= 20)
 550                         adev->sdma.instance[i].burst_nop = true;
 551                 fw_data = (const __le32 *)
 552                         (adev->sdma.instance[i].fw->data + le32_to_cpu(hdr->header.ucode_array_offset_bytes));
 553                 WREG32(mmSDMA0_UCODE_ADDR + sdma_offsets[i], 0);
 554                 for (j = 0; j < fw_size; j++)
 555                         WREG32(mmSDMA0_UCODE_DATA + sdma_offsets[i], le32_to_cpup(fw_data++));
 556                 WREG32(mmSDMA0_UCODE_ADDR + sdma_offsets[i], adev->sdma.instance[i].fw_version);
 557         }
 558
 559         return 0;
 560 }
 561
 562 /**
 563  * cik_sdma_start - setup and start the async dma engines
 564  *
 565  * @adev: amdgpu_device pointer
 566  *
 567  * Set up the DMA engines and enable them (CIK).
 568  * Returns 0 for success, error for failure.
 569  */
 570 static int cik_sdma_start(struct amdgpu_device *adev)
 571 {
 572         int r;
 573
 574         r = cik_sdma_load_microcode(adev);
 575         if (r)
 576                 return r;
 577
 578         /* halt the engine before programing */
 579         cik_sdma_enable(adev, false);
 580         /* enable sdma ring preemption */
 581         cik_ctx_switch_enable(adev, true);
 582
 583         /* start the gfx rings and rlc compute queues */
 584         r = cik_sdma_gfx_resume(adev);
 585         if (r)
 586                 return r;
 587         r = cik_sdma_rlc_resume(adev);
 588         if (r)
 589                 return r;
 590
 591         return 0;
 592 }
 593
 594 /**
 595  * cik_sdma_ring_test_ring - simple async dma engine test
 596  *
 597  * @ring: amdgpu_ring structure holding ring information
 598  *
 599  * Test the DMA engine by writing using it to write an
 600  * value to memory. (CIK).
 601  * Returns 0 for success, error for failure.
 602  */
 603 static int cik_sdma_ring_test_ring(struct amdgpu_ring *ring)
 604 {
 605         struct amdgpu_device *adev = ring->adev;
 606         unsigned i;
 607         unsigned index;
 608         int r;
 609         u32 tmp;
 610         u64 gpu_addr;
 611
 612         r = amdgpu_device_wb_get(adev, &index);
 613         if (r)
 614                 return r;
 615
 616         gpu_addr = adev->wb.gpu_addr + (index * 4);
 617         tmp = 0xCAFEDEAD;
 618         adev->wb.wb[index] = cpu_to_le32(tmp);
 619
 620         r = amdgpu_ring_alloc(ring, 5);
 621         if (r)
 622                 goto error_free_wb;
 623
 624         amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_WRITE, SDMA_WRITE_SUB_OPCODE_LINEAR, 0));
 625         amdgpu_ring_write(ring, lower_32_bits(gpu_addr));
 626         amdgpu_ring_write(ring, upper_32_bits(gpu_addr));
 627         amdgpu_ring_write(ring, 1); /* number of DWs to follow */
 628         amdgpu_ring_write(ring, 0xDEADBEEF);
 629         amdgpu_ring_commit(ring);
 630
 631         for (i = 0; i < adev->usec_timeout; i++) {
 632                 tmp = le32_to_cpu(adev->wb.wb[index]);
 633                 if (tmp == 0xDEADBEEF)
 634                         break;
 635                 udelay(1);
 636         }
 637
 638         if (i >= adev->usec_timeout)
 639                 r = -ETIMEDOUT;
 640
 641 error_free_wb:
 642         amdgpu_device_wb_free(adev, index);
 643         return r;
 644 }
 645
 646 /**
 647  * cik_sdma_ring_test_ib - test an IB on the DMA engine
 648  *
 649  * @ring: amdgpu_ring structure holding ring information
 650  * @timeout: timeout value in jiffies, or MAX_SCHEDULE_TIMEOUT
 651  *
 652  * Test a simple IB in the DMA ring (CIK).
 653  * Returns 0 on success, error on failure.
 654  */
 655 static int cik_sdma_ring_test_ib(struct amdgpu_ring *ring, long timeout)
 656 {
 657         struct amdgpu_device *adev = ring->adev;
 658         struct amdgpu_ib ib;
 659         struct dma_fence *f = NULL;
 660         unsigned index;
 661         u32 tmp = 0;
 662         u64 gpu_addr;
 663         long r;
 664
 665         r = amdgpu_device_wb_get(adev, &index);
 666         if (r)
 667                 return r;
 668
 669         gpu_addr = adev->wb.gpu_addr + (index * 4);
 670         tmp = 0xCAFEDEAD;
 671         adev->wb.wb[index] = cpu_to_le32(tmp);
 672         memset(&ib, 0, sizeof(ib));
 673         r = amdgpu_ib_get(adev, NULL, 256,
 674                                         AMDGPU_IB_POOL_DIRECT, &ib);
 675         if (r)
 676                 goto err0;
 677
 678         ib.ptr[0] = SDMA_PACKET(SDMA_OPCODE_WRITE,
 679                                 SDMA_WRITE_SUB_OPCODE_LINEAR, 0);
 680         ib.ptr[1] = lower_32_bits(gpu_addr);
 681         ib.ptr[2] = upper_32_bits(gpu_addr);
 682         ib.ptr[3] = 1;
 683         ib.ptr[4] = 0xDEADBEEF;
 684         ib.length_dw = 5;
 685         r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f);
 686         if (r)
 687                 goto err1;
 688
 689         r = dma_fence_wait_timeout(f, false, timeout);
 690         if (r == 0) {
 691                 r = -ETIMEDOUT;
 692                 goto err1;
 693         } else if (r < 0) {
 694                 goto err1;
 695         }
 696         tmp = le32_to_cpu(adev->wb.wb[index]);
 697         if (tmp == 0xDEADBEEF)
 698                 r = 0;
 699         else
 700                 r = -EINVAL;
 701
 702 err1:
 703         amdgpu_ib_free(adev, &ib, NULL);
 704         dma_fence_put(f);
 705 err0:
 706         amdgpu_device_wb_free(adev, index);
 707         return r;
 708 }
 709
 710 /**
 711  * cik_sdma_vm_copy_pte - update PTEs by copying them from the GART
 712  *
 713  * @ib: indirect buffer to fill with commands
 714  * @pe: addr of the page entry
 715  * @src: src addr to copy from
 716  * @count: number of page entries to update
 717  *
 718  * Update PTEs by copying them from the GART using sDMA (CIK).
 719  */
 720 static void cik_sdma_vm_copy_pte(struct amdgpu_ib *ib,
 721                                  uint64_t pe, uint64_t src,
 722                                  unsigned count)
 723 {
 724         unsigned bytes = count * 8;
 725
 726         ib->ptr[ib->length_dw++] = SDMA_PACKET(SDMA_OPCODE_COPY,
 727                 SDMA_WRITE_SUB_OPCODE_LINEAR, 0);
 728         ib->ptr[ib->length_dw++] = bytes;
 729         ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */
 730         ib->ptr[ib->length_dw++] = lower_32_bits(src);
 731         ib->ptr[ib->length_dw++] = upper_32_bits(src);
 732         ib->ptr[ib->length_dw++] = lower_32_bits(pe);
 733         ib->ptr[ib->length_dw++] = upper_32_bits(pe);
 734 }
 735
 736 /**
 737  * cik_sdma_vm_write_pte - update PTEs by writing them manually
 738  *
 739  * @ib: indirect buffer to fill with commands
 740  * @pe: addr of the page entry
 741  * @value: dst addr to write into pe
 742  * @count: number of page entries to update
 743  * @incr: increase next addr by incr bytes
 744  *
 745  * Update PTEs by writing them manually using sDMA (CIK).
 746  */
 747 static void cik_sdma_vm_write_pte(struct amdgpu_ib *ib, uint64_t pe,
 748                                   uint64_t value, unsigned count,
 749                                   uint32_t incr)
 750 {
 751         unsigned ndw = count * 2;
 752
 753         ib->ptr[ib->length_dw++] = SDMA_PACKET(SDMA_OPCODE_WRITE,
 754                 SDMA_WRITE_SUB_OPCODE_LINEAR, 0);
 755         ib->ptr[ib->length_dw++] = lower_32_bits(pe);
 756         ib->ptr[ib->length_dw++] = upper_32_bits(pe);
 757         ib->ptr[ib->length_dw++] = ndw;
 758         for (; ndw > 0; ndw -= 2) {
 759                 ib->ptr[ib->length_dw++] = lower_32_bits(value);
 760                 ib->ptr[ib->length_dw++] = upper_32_bits(value);
 761                 value += incr;
 762         }
 763 }
 764
 765 /**
 766  * cik_sdma_vm_set_pte_pde - update the page tables using sDMA
 767  *
 768  * @ib: indirect buffer to fill with commands
 769  * @pe: addr of the page entry
 770  * @addr: dst addr to write into pe
 771  * @count: number of page entries to update
 772  * @incr: increase next addr by incr bytes
 773  * @flags: access flags
 774  *
 775  * Update the page tables using sDMA (CIK).
 776  */
 777 static void cik_sdma_vm_set_pte_pde(struct amdgpu_ib *ib, uint64_t pe,
 778                                     uint64_t addr, unsigned count,
 779                                     uint32_t incr, uint64_t flags)
 780 {
 781         /* for physically contiguous pages (vram) */
 782         ib->ptr[ib->length_dw++] = SDMA_PACKET(SDMA_OPCODE_GENERATE_PTE_PDE, 0, 0);
 783         ib->ptr[ib->length_dw++] = lower_32_bits(pe); /* dst addr */
 784         ib->ptr[ib->length_dw++] = upper_32_bits(pe);
 785         ib->ptr[ib->length_dw++] = lower_32_bits(flags); /* mask */
 786         ib->ptr[ib->length_dw++] = upper_32_bits(flags);
 787         ib->ptr[ib->length_dw++] = lower_32_bits(addr); /* value */
 788         ib->ptr[ib->length_dw++] = upper_32_bits(addr);
 789         ib->ptr[ib->length_dw++] = incr; /* increment size */
 790         ib->ptr[ib->length_dw++] = 0;
 791         ib->ptr[ib->length_dw++] = count; /* number of entries */
 792 }
 793
 794 /**
 795  * cik_sdma_ring_pad_ib - pad the IB to the required number of dw
 796  *
 797  * @ring: amdgpu_ring structure holding ring information
 798  * @ib: indirect buffer to fill with padding
 799  *
 800  */
 801 static void cik_sdma_ring_pad_ib(struct amdgpu_ring *ring, struct amdgpu_ib *ib)
 802 {
 803         struct amdgpu_sdma_instance *sdma = amdgpu_sdma_get_instance_from_ring(ring);
 804         u32 pad_count;
 805         int i;
 806
 807         pad_count = (-ib->length_dw) & 7;
 808         for (i = 0; i < pad_count; i++)
 809                 if (sdma && sdma->burst_nop && (i == 0))
 810                         ib->ptr[ib->length_dw++] =
 811                                         SDMA_PACKET(SDMA_OPCODE_NOP, 0, 0) |
 812                                         SDMA_NOP_COUNT(pad_count - 1);
 813                 else
 814                         ib->ptr[ib->length_dw++] =
 815                                         SDMA_PACKET(SDMA_OPCODE_NOP, 0, 0);
 816 }
 817
 818 /**
 819  * cik_sdma_ring_emit_pipeline_sync - sync the pipeline
 820  *
 821  * @ring: amdgpu_ring pointer
 822  *
 823  * Make sure all previous operations are completed (CIK).
 824  */
 825 static void cik_sdma_ring_emit_pipeline_sync(struct amdgpu_ring *ring)
 826 {
 827         uint32_t seq = ring->fence_drv.sync_seq;
 828         uint64_t addr = ring->fence_drv.gpu_addr;
 829
 830         /* wait for idle */
 831         amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_POLL_REG_MEM, 0,
 832                                             SDMA_POLL_REG_MEM_EXTRA_OP(0) |
 833                                             SDMA_POLL_REG_MEM_EXTRA_FUNC(3) | /* equal */
 834                                             SDMA_POLL_REG_MEM_EXTRA_M));
 835         amdgpu_ring_write(ring, addr & 0xfffffffc);
 836         amdgpu_ring_write(ring, upper_32_bits(addr) & 0xffffffff);
 837         amdgpu_ring_write(ring, seq); /* reference */
 838         amdgpu_ring_write(ring, 0xffffffff); /* mask */
 839         amdgpu_ring_write(ring, (0xfff << 16) | 4); /* retry count, poll interval */
 840 }
 841
 842 /**
 843  * cik_sdma_ring_emit_vm_flush - cik vm flush using sDMA
 844  *
 845  * @ring: amdgpu_ring pointer
 846  * @vmid: vmid number to use
 847  * @pd_addr: address
 848  *
 849  * Update the page table base and flush the VM TLB
 850  * using sDMA (CIK).
 851  */
 852 static void cik_sdma_ring_emit_vm_flush(struct amdgpu_ring *ring,
 853                                         unsigned vmid, uint64_t pd_addr)
 854 {
 855         u32 extra_bits = (SDMA_POLL_REG_MEM_EXTRA_OP(0) |
 856                           SDMA_POLL_REG_MEM_EXTRA_FUNC(0)); /* always */
 857
 858         amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr);
 859
 860         amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_POLL_REG_MEM, 0, extra_bits));
 861         amdgpu_ring_write(ring, mmVM_INVALIDATE_REQUEST << 2);
 862         amdgpu_ring_write(ring, 0);
 863         amdgpu_ring_write(ring, 0); /* reference */
 864         amdgpu_ring_write(ring, 0); /* mask */
 865         amdgpu_ring_write(ring, (0xfff << 16) | 10); /* retry count, poll interval */
 866 }
 867
 868 static void cik_sdma_ring_emit_wreg(struct amdgpu_ring *ring,
 869                                     uint32_t reg, uint32_t val)
 870 {
 871         amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_SRBM_WRITE, 0, 0xf000));
 872         amdgpu_ring_write(ring, reg);
 873         amdgpu_ring_write(ring, val);
 874 }
 875
 876 static void cik_enable_sdma_mgcg(struct amdgpu_device *adev,
 877                                  bool enable)
 878 {
 879         u32 orig, data;
 880
 881         if (enable && (adev->cg_flags & AMD_CG_SUPPORT_SDMA_MGCG)) {
 882                 WREG32(mmSDMA0_CLK_CTRL + SDMA0_REGISTER_OFFSET, 0x00000100);
 883                 WREG32(mmSDMA0_CLK_CTRL + SDMA1_REGISTER_OFFSET, 0x00000100);
 884         } else {
 885                 orig = data = RREG32(mmSDMA0_CLK_CTRL + SDMA0_REGISTER_OFFSET);
 886                 data |= 0xff000000;
 887                 if (data != orig)
 888                         WREG32(mmSDMA0_CLK_CTRL + SDMA0_REGISTER_OFFSET, data);
 889
 890                 orig = data = RREG32(mmSDMA0_CLK_CTRL + SDMA1_REGISTER_OFFSET);
 891                 data |= 0xff000000;
 892                 if (data != orig)
 893                         WREG32(mmSDMA0_CLK_CTRL + SDMA1_REGISTER_OFFSET, data);
 894         }
 895 }
 896
 897 static void cik_enable_sdma_mgls(struct amdgpu_device *adev,
 898                                  bool enable)
 899 {
 900         u32 orig, data;
 901
 902         if (enable && (adev->cg_flags & AMD_CG_SUPPORT_SDMA_LS)) {
 903                 orig = data = RREG32(mmSDMA0_POWER_CNTL + SDMA0_REGISTER_OFFSET);
 904                 data |= 0x100;
 905                 if (orig != data)
 906                         WREG32(mmSDMA0_POWER_CNTL + SDMA0_REGISTER_OFFSET, data);
 907
 908                 orig = data = RREG32(mmSDMA0_POWER_CNTL + SDMA1_REGISTER_OFFSET);
 909                 data |= 0x100;
 910                 if (orig != data)
 911                         WREG32(mmSDMA0_POWER_CNTL + SDMA1_REGISTER_OFFSET, data);
 912         } else {
 913                 orig = data = RREG32(mmSDMA0_POWER_CNTL + SDMA0_REGISTER_OFFSET);
 914                 data &= ~0x100;
 915                 if (orig != data)
 916                         WREG32(mmSDMA0_POWER_CNTL + SDMA0_REGISTER_OFFSET, data);
 917
 918                 orig = data = RREG32(mmSDMA0_POWER_CNTL + SDMA1_REGISTER_OFFSET);
 919                 data &= ~0x100;
 920                 if (orig != data)
 921                         WREG32(mmSDMA0_POWER_CNTL + SDMA1_REGISTER_OFFSET, data);
 922         }
 923 }
 924
 925 static int cik_sdma_early_init(void *handle)
 926 {
 927         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 928
 929         adev->sdma.num_instances = SDMA_MAX_INSTANCE;
 930
 931         cik_sdma_set_ring_funcs(adev);
 932         cik_sdma_set_irq_funcs(adev);
 933         cik_sdma_set_buffer_funcs(adev);
 934         cik_sdma_set_vm_pte_funcs(adev);
 935
 936         return 0;
 937 }
 938
 939 static int cik_sdma_sw_init(void *handle)
 940 {
 941         struct amdgpu_ring *ring;
 942         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 943         int r, i;
 944
 945         r = cik_sdma_init_microcode(adev);
 946         if (r) {
 947                 DRM_ERROR("Failed to load sdma firmware!\n");
 948                 return r;
 949         }
 950
 951         /* SDMA trap event */
 952         r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, 224,
 953                               &adev->sdma.trap_irq);
 954         if (r)
 955                 return r;
 956
 957         /* SDMA Privileged inst */
 958         r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, 241,
 959                               &adev->sdma.illegal_inst_irq);
 960         if (r)
 961                 return r;
 962
 963         /* SDMA Privileged inst */
 964         r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, 247,
 965                               &adev->sdma.illegal_inst_irq);
 966         if (r)
 967                 return r;
 968
 969         for (i = 0; i < adev->sdma.num_instances; i++) {
 970                 ring = &adev->sdma.instance[i].ring;
 971                 ring->ring_obj = NULL;
 972                 sprintf(ring->name, "sdma%d", i);
 973                 r = amdgpu_ring_init(adev, ring, 1024,
 974                                      &adev->sdma.trap_irq,
 975                                      (i == 0) ? AMDGPU_SDMA_IRQ_INSTANCE0 :
 976                                      AMDGPU_SDMA_IRQ_INSTANCE1,
 977                                      AMDGPU_RING_PRIO_DEFAULT, NULL);
 978                 if (r)
 979                         return r;
 980         }
 981
 982         return r;
 983 }
 984
 985 static int cik_sdma_sw_fini(void *handle)
 986 {
 987         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 988         int i;
 989
 990         for (i = 0; i < adev->sdma.num_instances; i++)
 991                 amdgpu_ring_fini(&adev->sdma.instance[i].ring);
 992
 993         cik_sdma_free_microcode(adev);
 994         return 0;
 995 }
 996
 997 static int cik_sdma_hw_init(void *handle)
 998 {
 999         int r;
1000         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1001
1002         r = cik_sdma_start(adev);
1003         if (r)
1004                 return r;
1005
1006         return r;
1007 }
1008
1009 static int cik_sdma_hw_fini(void *handle)
1010 {
1011         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1012
1013         cik_ctx_switch_enable(adev, false);
1014         cik_sdma_enable(adev, false);
1015
1016         return 0;
1017 }
1018
1019 static int cik_sdma_suspend(void *handle)
1020 {
1021         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1022
1023         return cik_sdma_hw_fini(adev);
1024 }
1025
1026 static int cik_sdma_resume(void *handle)
1027 {
1028         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1029
1030         cik_sdma_soft_reset(handle);
1031
1032         return cik_sdma_hw_init(adev);
1033 }
1034
1035 static bool cik_sdma_is_idle(void *handle)
1036 {
1037         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1038         u32 tmp = RREG32(mmSRBM_STATUS2);
1039
1040         if (tmp & (SRBM_STATUS2__SDMA_BUSY_MASK |
1041                                 SRBM_STATUS2__SDMA1_BUSY_MASK))
1042             return false;
1043
1044         return true;
1045 }
1046
1047 static int cik_sdma_wait_for_idle(void *handle)
1048 {
1049         unsigned i;
1050         u32 tmp;
1051         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1052
1053         for (i = 0; i < adev->usec_timeout; i++) {
1054                 tmp = RREG32(mmSRBM_STATUS2) & (SRBM_STATUS2__SDMA_BUSY_MASK |
1055                                 SRBM_STATUS2__SDMA1_BUSY_MASK);
1056
1057                 if (!tmp)
1058                         return 0;
1059                 udelay(1);
1060         }
1061         return -ETIMEDOUT;
1062 }
1063
1064 static int cik_sdma_soft_reset(void *handle)
1065 {
1066         u32 srbm_soft_reset = 0;
1067         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1068         u32 tmp;
1069
1070         /* sdma0 */
1071         tmp = RREG32(mmSDMA0_F32_CNTL + SDMA0_REGISTER_OFFSET);
1072         tmp |= SDMA0_F32_CNTL__HALT_MASK;
1073         WREG32(mmSDMA0_F32_CNTL + SDMA0_REGISTER_OFFSET, tmp);
1074         srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_SDMA_MASK;
1075
1076         /* sdma1 */
1077         tmp = RREG32(mmSDMA0_F32_CNTL + SDMA1_REGISTER_OFFSET);
1078         tmp |= SDMA0_F32_CNTL__HALT_MASK;
1079         WREG32(mmSDMA0_F32_CNTL + SDMA1_REGISTER_OFFSET, tmp);
1080         srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_SDMA1_MASK;
1081
1082         if (srbm_soft_reset) {
1083                 tmp = RREG32(mmSRBM_SOFT_RESET);
1084                 tmp |= srbm_soft_reset;
1085                 dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
1086                 WREG32(mmSRBM_SOFT_RESET, tmp);
1087                 tmp = RREG32(mmSRBM_SOFT_RESET);
1088
1089                 udelay(50);
1090
1091                 tmp &= ~srbm_soft_reset;
1092                 WREG32(mmSRBM_SOFT_RESET, tmp);
1093                 tmp = RREG32(mmSRBM_SOFT_RESET);
1094
1095                 /* Wait a little for things to settle down */
1096                 udelay(50);
1097         }
1098
1099         return 0;
1100 }
1101
1102 static int cik_sdma_set_trap_irq_state(struct amdgpu_device *adev,
1103                                        struct amdgpu_irq_src *src,
1104                                        unsigned type,
1105                                        enum amdgpu_interrupt_state state)
1106 {
1107         u32 sdma_cntl;
1108
1109         switch (type) {
1110         case AMDGPU_SDMA_IRQ_INSTANCE0:
1111                 switch (state) {
1112                 case AMDGPU_IRQ_STATE_DISABLE:
1113                         sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET);
1114                         sdma_cntl &= ~SDMA0_CNTL__TRAP_ENABLE_MASK;
1115                         WREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET, sdma_cntl);
1116                         break;
1117                 case AMDGPU_IRQ_STATE_ENABLE:
1118                         sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET);
1119                         sdma_cntl |= SDMA0_CNTL__TRAP_ENABLE_MASK;
1120                         WREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET, sdma_cntl);
1121                         break;
1122                 default:
1123                         break;
1124                 }
1125                 break;
1126         case AMDGPU_SDMA_IRQ_INSTANCE1:
1127                 switch (state) {
1128                 case AMDGPU_IRQ_STATE_DISABLE:
1129                         sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET);
1130                         sdma_cntl &= ~SDMA0_CNTL__TRAP_ENABLE_MASK;
1131                         WREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET, sdma_cntl);
1132                         break;
1133                 case AMDGPU_IRQ_STATE_ENABLE:
1134                         sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET);
1135                         sdma_cntl |= SDMA0_CNTL__TRAP_ENABLE_MASK;
1136                         WREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET, sdma_cntl);
1137                         break;
1138                 default:
1139                         break;
1140                 }
1141                 break;
1142         default:
1143                 break;
1144         }
1145         return 0;
1146 }
1147
1148 static int cik_sdma_process_trap_irq(struct amdgpu_device *adev,
1149                                      struct amdgpu_irq_src *source,
1150                                      struct amdgpu_iv_entry *entry)
1151 {
1152         u8 instance_id, queue_id;
1153
1154         instance_id = (entry->ring_id & 0x3) >> 0;
1155         queue_id = (entry->ring_id & 0xc) >> 2;
1156         DRM_DEBUG("IH: SDMA trap\n");
1157         switch (instance_id) {
1158         case 0:
1159                 switch (queue_id) {
1160                 case 0:
1161                         amdgpu_fence_process(&adev->sdma.instance[0].ring);
1162                         break;
1163                 case 1:
1164                         /* XXX compute */
1165                         break;
1166                 case 2:
1167                         /* XXX compute */
1168                         break;
1169                 }
1170                 break;
1171         case 1:
1172                 switch (queue_id) {
1173                 case 0:
1174                         amdgpu_fence_process(&adev->sdma.instance[1].ring);
1175                         break;
1176                 case 1:
1177                         /* XXX compute */
1178                         break;
1179                 case 2:
1180                         /* XXX compute */
1181                         break;
1182                 }
1183                 break;
1184         }
1185
1186         return 0;
1187 }
1188
1189 static int cik_sdma_process_illegal_inst_irq(struct amdgpu_device *adev,
1190                                              struct amdgpu_irq_src *source,
1191                                              struct amdgpu_iv_entry *entry)
1192 {
1193         u8 instance_id;
1194
1195         DRM_ERROR("Illegal instruction in SDMA command stream\n");
1196         instance_id = (entry->ring_id & 0x3) >> 0;
1197         drm_sched_fault(&adev->sdma.instance[instance_id].ring.sched);
1198         return 0;
1199 }
1200
1201 static int cik_sdma_set_clockgating_state(void *handle,
1202                                           enum amd_clockgating_state state)
1203 {
1204         bool gate = false;
1205         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1206
1207         if (state == AMD_CG_STATE_GATE)
1208                 gate = true;
1209
1210         cik_enable_sdma_mgcg(adev, gate);
1211         cik_enable_sdma_mgls(adev, gate);
1212
1213         return 0;
1214 }
1215
1216 static int cik_sdma_set_powergating_state(void *handle,
1217                                           enum amd_powergating_state state)
1218 {
1219         return 0;
1220 }
1221
1222 static const struct amd_ip_funcs cik_sdma_ip_funcs = {
1223         .name = "cik_sdma",
1224         .early_init = cik_sdma_early_init,
1225         .late_init = NULL,
1226         .sw_init = cik_sdma_sw_init,
1227         .sw_fini = cik_sdma_sw_fini,
1228         .hw_init = cik_sdma_hw_init,
1229         .hw_fini = cik_sdma_hw_fini,
1230         .suspend = cik_sdma_suspend,
1231         .resume = cik_sdma_resume,
1232         .is_idle = cik_sdma_is_idle,
1233         .wait_for_idle = cik_sdma_wait_for_idle,
1234         .soft_reset = cik_sdma_soft_reset,
1235         .set_clockgating_state = cik_sdma_set_clockgating_state,
1236         .set_powergating_state = cik_sdma_set_powergating_state,
1237 };
1238
1239 static const struct amdgpu_ring_funcs cik_sdma_ring_funcs = {
1240         .type = AMDGPU_RING_TYPE_SDMA,
1241         .align_mask = 0xf,
1242         .nop = SDMA_PACKET(SDMA_OPCODE_NOP, 0, 0),
1243         .support_64bit_ptrs = false,
1244         .get_rptr = cik_sdma_ring_get_rptr,
1245         .get_wptr = cik_sdma_ring_get_wptr,
1246         .set_wptr = cik_sdma_ring_set_wptr,
1247         .emit_frame_size =
1248                 6 + /* cik_sdma_ring_emit_hdp_flush */
1249                 3 + /* hdp invalidate */
1250                 6 + /* cik_sdma_ring_emit_pipeline_sync */
1251                 CIK_FLUSH_GPU_TLB_NUM_WREG * 3 + 6 + /* cik_sdma_ring_emit_vm_flush */
1252                 9 + 9 + 9, /* cik_sdma_ring_emit_fence x3 for user fence, vm fence */
1253         .emit_ib_size = 7 + 4, /* cik_sdma_ring_emit_ib */
1254         .emit_ib = cik_sdma_ring_emit_ib,
1255         .emit_fence = cik_sdma_ring_emit_fence,
1256         .emit_pipeline_sync = cik_sdma_ring_emit_pipeline_sync,
1257         .emit_vm_flush = cik_sdma_ring_emit_vm_flush,
1258         .emit_hdp_flush = cik_sdma_ring_emit_hdp_flush,
1259         .test_ring = cik_sdma_ring_test_ring,
1260         .test_ib = cik_sdma_ring_test_ib,
1261         .insert_nop = cik_sdma_ring_insert_nop,
1262         .pad_ib = cik_sdma_ring_pad_ib,
1263         .emit_wreg = cik_sdma_ring_emit_wreg,
1264 };
1265
1266 static void cik_sdma_set_ring_funcs(struct amdgpu_device *adev)
1267 {
1268         int i;
1269
1270         for (i = 0; i < adev->sdma.num_instances; i++) {
1271                 adev->sdma.instance[i].ring.funcs = &cik_sdma_ring_funcs;
1272                 adev->sdma.instance[i].ring.me = i;
1273         }
1274 }
1275
1276 static const struct amdgpu_irq_src_funcs cik_sdma_trap_irq_funcs = {
1277         .set = cik_sdma_set_trap_irq_state,
1278         .process = cik_sdma_process_trap_irq,
1279 };
1280
1281 static const struct amdgpu_irq_src_funcs cik_sdma_illegal_inst_irq_funcs = {
1282         .process = cik_sdma_process_illegal_inst_irq,
1283 };
1284
1285 static void cik_sdma_set_irq_funcs(struct amdgpu_device *adev)
1286 {
1287         adev->sdma.trap_irq.num_types = AMDGPU_SDMA_IRQ_LAST;
1288         adev->sdma.trap_irq.funcs = &cik_sdma_trap_irq_funcs;
1289         adev->sdma.illegal_inst_irq.funcs = &cik_sdma_illegal_inst_irq_funcs;
1290 }
1291
1292 /**
1293  * cik_sdma_emit_copy_buffer - copy buffer using the sDMA engine
1294  *
1295  * @ib: indirect buffer to copy to
1296  * @src_offset: src GPU address
1297  * @dst_offset: dst GPU address
1298  * @byte_count: number of bytes to xfer
1299  * @tmz: is this a secure operation
1300  *
1301  * Copy GPU buffers using the DMA engine (CIK).
1302  * Used by the amdgpu ttm implementation to move pages if
1303  * registered as the asic copy callback.
1304  */
1305 static void cik_sdma_emit_copy_buffer(struct amdgpu_ib *ib,
1306                                       uint64_t src_offset,
1307                                       uint64_t dst_offset,
1308                                       uint32_t byte_count,
1309                                       bool tmz)
1310 {
1311         ib->ptr[ib->length_dw++] = SDMA_PACKET(SDMA_OPCODE_COPY, SDMA_COPY_SUB_OPCODE_LINEAR, 0);
1312         ib->ptr[ib->length_dw++] = byte_count;
1313         ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */
1314         ib->ptr[ib->length_dw++] = lower_32_bits(src_offset);
1315         ib->ptr[ib->length_dw++] = upper_32_bits(src_offset);
1316         ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset);
1317         ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset);
1318 }
1319
1320 /**
1321  * cik_sdma_emit_fill_buffer - fill buffer using the sDMA engine
1322  *
1323  * @ib: indirect buffer to fill
1324  * @src_data: value to write to buffer
1325  * @dst_offset: dst GPU address
1326  * @byte_count: number of bytes to xfer
1327  *
1328  * Fill GPU buffers using the DMA engine (CIK).
1329  */
1330 static void cik_sdma_emit_fill_buffer(struct amdgpu_ib *ib,
1331                                       uint32_t src_data,
1332                                       uint64_t dst_offset,
1333                                       uint32_t byte_count)
1334 {
1335         ib->ptr[ib->length_dw++] = SDMA_PACKET(SDMA_OPCODE_CONSTANT_FILL, 0, 0);
1336         ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset);
1337         ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset);
1338         ib->ptr[ib->length_dw++] = src_data;
1339         ib->ptr[ib->length_dw++] = byte_count;
1340 }
1341
1342 static const struct amdgpu_buffer_funcs cik_sdma_buffer_funcs = {
1343         .copy_max_bytes = 0x1fffff,
1344         .copy_num_dw = 7,
1345         .emit_copy_buffer = cik_sdma_emit_copy_buffer,
1346
1347         .fill_max_bytes = 0x1fffff,
1348         .fill_num_dw = 5,
1349         .emit_fill_buffer = cik_sdma_emit_fill_buffer,
1350 };
1351
1352 static void cik_sdma_set_buffer_funcs(struct amdgpu_device *adev)
1353 {
1354         adev->mman.buffer_funcs = &cik_sdma_buffer_funcs;
1355         adev->mman.buffer_funcs_ring = &adev->sdma.instance[0].ring;
1356 }
1357
1358 static const struct amdgpu_vm_pte_funcs cik_sdma_vm_pte_funcs = {
1359         .copy_pte_num_dw = 7,
1360         .copy_pte = cik_sdma_vm_copy_pte,
1361
1362         .write_pte = cik_sdma_vm_write_pte,
1363         .set_pte_pde = cik_sdma_vm_set_pte_pde,
1364 };
1365
1366 static void cik_sdma_set_vm_pte_funcs(struct amdgpu_device *adev)
1367 {
1368         unsigned i;
1369
1370         adev->vm_manager.vm_pte_funcs = &cik_sdma_vm_pte_funcs;
1371         for (i = 0; i < adev->sdma.num_instances; i++) {
1372                 adev->vm_manager.vm_pte_scheds[i] =
1373                         &adev->sdma.instance[i].ring.sched;
1374         }
1375         adev->vm_manager.vm_pte_num_scheds = adev->sdma.num_instances;
1376 }
1377
1378 const struct amdgpu_ip_block_version cik_sdma_ip_block =
1379 {
1380         .type = AMD_IP_BLOCK_TYPE_SDMA,
1381         .major = 2,
1382         .minor = 0,
1383         .rev = 0,
1384         .funcs = &cik_sdma_ip_funcs,
1385 };