drivers/gpu/drm/amd/amdgpu/cik_sdma.c

   1 /*
   2  * Copyright 2013 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: Alex Deucher
  23  */
  24
  25 #include <linux/firmware.h>
  26 #include <linux/module.h>
  27
  28 #include "amdgpu.h"
  29 #include "amdgpu_ucode.h"
  30 #include "amdgpu_trace.h"
  31 #include "cikd.h"
  32 #include "cik.h"
  33
  34 #include "bif/bif_4_1_d.h"
  35 #include "bif/bif_4_1_sh_mask.h"
  36
  37 #include "gca/gfx_7_2_d.h"
  38 #include "gca/gfx_7_2_enum.h"
  39 #include "gca/gfx_7_2_sh_mask.h"
  40
  41 #include "gmc/gmc_7_1_d.h"
  42 #include "gmc/gmc_7_1_sh_mask.h"
  43
  44 #include "oss/oss_2_0_d.h"
  45 #include "oss/oss_2_0_sh_mask.h"
  46
  47 static const u32 sdma_offsets[SDMA_MAX_INSTANCE] =
  48 {
  49         SDMA0_REGISTER_OFFSET,
  50         SDMA1_REGISTER_OFFSET
  51 };
  52
  53 static void cik_sdma_set_ring_funcs(struct amdgpu_device *adev);
  54 static void cik_sdma_set_irq_funcs(struct amdgpu_device *adev);
  55 static void cik_sdma_set_buffer_funcs(struct amdgpu_device *adev);
  56 static void cik_sdma_set_vm_pte_funcs(struct amdgpu_device *adev);
  57 static int cik_sdma_soft_reset(void *handle);
  58
  59 MODULE_FIRMWARE("amdgpu/bonaire_sdma.bin");
  60 MODULE_FIRMWARE("amdgpu/bonaire_sdma1.bin");
  61 MODULE_FIRMWARE("amdgpu/hawaii_sdma.bin");
  62 MODULE_FIRMWARE("amdgpu/hawaii_sdma1.bin");
  63 MODULE_FIRMWARE("amdgpu/kaveri_sdma.bin");
  64 MODULE_FIRMWARE("amdgpu/kaveri_sdma1.bin");
  65 MODULE_FIRMWARE("amdgpu/kabini_sdma.bin");
  66 MODULE_FIRMWARE("amdgpu/kabini_sdma1.bin");
  67 MODULE_FIRMWARE("amdgpu/mullins_sdma.bin");
  68 MODULE_FIRMWARE("amdgpu/mullins_sdma1.bin");
  69
  70 u32 amdgpu_cik_gpu_check_soft_reset(struct amdgpu_device *adev);
  71
  72
  73 static void cik_sdma_free_microcode(struct amdgpu_device *adev)
  74 {
  75         int i;
  76         for (i = 0; i < adev->sdma.num_instances; i++) {
  77                         release_firmware(adev->sdma.instance[i].fw);
  78                         adev->sdma.instance[i].fw = NULL;
  79         }
  80 }
  81
  82 /*
  83  * sDMA - System DMA
  84  * Starting with CIK, the GPU has new asynchronous
  85  * DMA engines.  These engines are used for compute
  86  * and gfx.  There are two DMA engines (SDMA0, SDMA1)
  87  * and each one supports 1 ring buffer used for gfx
  88  * and 2 queues used for compute.
  89  *
  90  * The programming model is very similar to the CP
  91  * (ring buffer, IBs, etc.), but sDMA has it's own
  92  * packet format that is different from the PM4 format
  93  * used by the CP. sDMA supports copying data, writing
  94  * embedded data, solid fills, and a number of other
  95  * things.  It also has support for tiling/detiling of
  96  * buffers.
  97  */
  98
  99 /**
 100  * cik_sdma_init_microcode - load ucode images from disk
 101  *
 102  * @adev: amdgpu_device pointer
 103  *
 104  * Use the firmware interface to load the ucode images into
 105  * the driver (not loaded into hw).
 106  * Returns 0 on success, error on failure.
 107  */
 108 static int cik_sdma_init_microcode(struct amdgpu_device *adev)
 109 {
 110         const char *chip_name;
 111         char fw_name[30];
 112         int err = 0, i;
 113
 114         DRM_DEBUG("\n");
 115
 116         switch (adev->asic_type) {
 117         case CHIP_BONAIRE:
 118                 chip_name = "bonaire";
 119                 break;
 120         case CHIP_HAWAII:
 121                 chip_name = "hawaii";
 122                 break;
 123         case CHIP_KAVERI:
 124                 chip_name = "kaveri";
 125                 break;
 126         case CHIP_KABINI:
 127                 chip_name = "kabini";
 128                 break;
 129         case CHIP_MULLINS:
 130                 chip_name = "mullins";
 131                 break;
 132         default: BUG();
 133         }
 134
 135         for (i = 0; i < adev->sdma.num_instances; i++) {
 136                 if (i == 0)
 137                         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sdma.bin", chip_name);
 138                 else
 139                         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sdma1.bin", chip_name);
 140                 err = request_firmware(&adev->sdma.instance[i].fw, fw_name, adev->dev);
 141                 if (err)
 142                         goto out;
 143                 err = amdgpu_ucode_validate(adev->sdma.instance[i].fw);
 144         }
 145 out:
 146         if (err) {
 147                 pr_err("cik_sdma: Failed to load firmware \"%s\"\n", fw_name);
 148                 for (i = 0; i < adev->sdma.num_instances; i++) {
 149                         release_firmware(adev->sdma.instance[i].fw);
 150                         adev->sdma.instance[i].fw = NULL;
 151                 }
 152         }
 153         return err;
 154 }
 155
 156 /**
 157  * cik_sdma_ring_get_rptr - get the current read pointer
 158  *
 159  * @ring: amdgpu ring pointer
 160  *
 161  * Get the current rptr from the hardware (CIK+).
 162  */
 163 static uint64_t cik_sdma_ring_get_rptr(struct amdgpu_ring *ring)
 164 {
 165         u32 rptr;
 166
 167         rptr = ring->adev->wb.wb[ring->rptr_offs];
 168
 169         return (rptr & 0x3fffc) >> 2;
 170 }
 171
 172 /**
 173  * cik_sdma_ring_get_wptr - get the current write pointer
 174  *
 175  * @ring: amdgpu ring pointer
 176  *
 177  * Get the current wptr from the hardware (CIK+).
 178  */
 179 static uint64_t cik_sdma_ring_get_wptr(struct amdgpu_ring *ring)
 180 {
 181         struct amdgpu_device *adev = ring->adev;
 182
 183         return (RREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[ring->me]) & 0x3fffc) >> 2;
 184 }
 185
 186 /**
 187  * cik_sdma_ring_set_wptr - commit the write pointer
 188  *
 189  * @ring: amdgpu ring pointer
 190  *
 191  * Write the wptr back to the hardware (CIK+).
 192  */
 193 static void cik_sdma_ring_set_wptr(struct amdgpu_ring *ring)
 194 {
 195         struct amdgpu_device *adev = ring->adev;
 196
 197         WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[ring->me],
 198                (lower_32_bits(ring->wptr) << 2) & 0x3fffc);
 199 }
 200
 201 static void cik_sdma_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count)
 202 {
 203         struct amdgpu_sdma_instance *sdma = amdgpu_sdma_get_instance_from_ring(ring);
 204         int i;
 205
 206         for (i = 0; i < count; i++)
 207                 if (sdma && sdma->burst_nop && (i == 0))
 208                         amdgpu_ring_write(ring, ring->funcs->nop |
 209                                           SDMA_NOP_COUNT(count - 1));
 210                 else
 211                         amdgpu_ring_write(ring, ring->funcs->nop);
 212 }
 213
 214 /**
 215  * cik_sdma_ring_emit_ib - Schedule an IB on the DMA engine
 216  *
 217  * @ring: amdgpu ring pointer
 218  * @job: job to retrive vmid from
 219  * @ib: IB object to schedule
 220  * @flags: unused
 221  *
 222  * Schedule an IB in the DMA ring (CIK).
 223  */
 224 static void cik_sdma_ring_emit_ib(struct amdgpu_ring *ring,
 225                                   struct amdgpu_job *job,
 226                                   struct amdgpu_ib *ib,
 227                                   uint32_t flags)
 228 {
 229         unsigned vmid = AMDGPU_JOB_GET_VMID(job);
 230         u32 extra_bits = vmid & 0xf;
 231
 232         /* IB packet must end on a 8 DW boundary */
 233         cik_sdma_ring_insert_nop(ring, (4 - lower_32_bits(ring->wptr)) & 7);
 234
 235         amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_INDIRECT_BUFFER, 0, extra_bits));
 236         amdgpu_ring_write(ring, ib->gpu_addr & 0xffffffe0); /* base must be 32 byte aligned */
 237         amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xffffffff);
 238         amdgpu_ring_write(ring, ib->length_dw);
 239
 240 }
 241
 242 /**
 243  * cik_sdma_ring_emit_hdp_flush - emit an hdp flush on the DMA ring
 244  *
 245  * @ring: amdgpu ring pointer
 246  *
 247  * Emit an hdp flush packet on the requested DMA ring.
 248  */
 249 static void cik_sdma_ring_emit_hdp_flush(struct amdgpu_ring *ring)
 250 {
 251         u32 extra_bits = (SDMA_POLL_REG_MEM_EXTRA_OP(1) |
 252                           SDMA_POLL_REG_MEM_EXTRA_FUNC(3)); /* == */
 253         u32 ref_and_mask;
 254
 255         if (ring->me == 0)
 256                 ref_and_mask = GPU_HDP_FLUSH_DONE__SDMA0_MASK;
 257         else
 258                 ref_and_mask = GPU_HDP_FLUSH_DONE__SDMA1_MASK;
 259
 260         amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_POLL_REG_MEM, 0, extra_bits));
 261         amdgpu_ring_write(ring, mmGPU_HDP_FLUSH_DONE << 2);
 262         amdgpu_ring_write(ring, mmGPU_HDP_FLUSH_REQ << 2);
 263         amdgpu_ring_write(ring, ref_and_mask); /* reference */
 264         amdgpu_ring_write(ring, ref_and_mask); /* mask */
 265         amdgpu_ring_write(ring, (0xfff << 16) | 10); /* retry count, poll interval */
 266 }
 267
 268 /**
 269  * cik_sdma_ring_emit_fence - emit a fence on the DMA ring
 270  *
 271  * @ring: amdgpu ring pointer
 272  * @addr: address
 273  * @seq: sequence number
 274  * @flags: fence related flags
 275  *
 276  * Add a DMA fence packet to the ring to write
 277  * the fence seq number and DMA trap packet to generate
 278  * an interrupt if needed (CIK).
 279  */
 280 static void cik_sdma_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq,
 281                                      unsigned flags)
 282 {
 283         bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT;
 284         /* write the fence */
 285         amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_FENCE, 0, 0));
 286         amdgpu_ring_write(ring, lower_32_bits(addr));
 287         amdgpu_ring_write(ring, upper_32_bits(addr));
 288         amdgpu_ring_write(ring, lower_32_bits(seq));
 289
 290         /* optionally write high bits as well */
 291         if (write64bit) {
 292                 addr += 4;
 293                 amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_FENCE, 0, 0));
 294                 amdgpu_ring_write(ring, lower_32_bits(addr));
 295                 amdgpu_ring_write(ring, upper_32_bits(addr));
 296                 amdgpu_ring_write(ring, upper_32_bits(seq));
 297         }
 298
 299         /* generate an interrupt */
 300         amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_TRAP, 0, 0));
 301 }
 302
 303 /**
 304  * cik_sdma_gfx_stop - stop the gfx async dma engines
 305  *
 306  * @adev: amdgpu_device pointer
 307  *
 308  * Stop the gfx async dma ring buffers (CIK).
 309  */
 310 static void cik_sdma_gfx_stop(struct amdgpu_device *adev)
 311 {
 312         struct amdgpu_ring *sdma0 = &adev->sdma.instance[0].ring;
 313         struct amdgpu_ring *sdma1 = &adev->sdma.instance[1].ring;
 314         u32 rb_cntl;
 315         int i;
 316
 317         if ((adev->mman.buffer_funcs_ring == sdma0) ||
 318             (adev->mman.buffer_funcs_ring == sdma1))
 319                         amdgpu_ttm_set_buffer_funcs_status(adev, false);
 320
 321         for (i = 0; i < adev->sdma.num_instances; i++) {
 322                 rb_cntl = RREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i]);
 323                 rb_cntl &= ~SDMA0_GFX_RB_CNTL__RB_ENABLE_MASK;
 324                 WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], rb_cntl);
 325                 WREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i], 0);
 326         }
 327 }
 328
 329 /**
 330  * cik_sdma_rlc_stop - stop the compute async dma engines
 331  *
 332  * @adev: amdgpu_device pointer
 333  *
 334  * Stop the compute async dma queues (CIK).
 335  */
 336 static void cik_sdma_rlc_stop(struct amdgpu_device *adev)
 337 {
 338         /* XXX todo */
 339 }
 340
 341 /**
 342  * cik_ctx_switch_enable - stop the async dma engines context switch
 343  *
 344  * @adev: amdgpu_device pointer
 345  * @enable: enable/disable the DMA MEs context switch.
 346  *
 347  * Halt or unhalt the async dma engines context switch (VI).
 348  */
 349 static void cik_ctx_switch_enable(struct amdgpu_device *adev, bool enable)
 350 {
 351         u32 f32_cntl, phase_quantum = 0;
 352         int i;
 353
 354         if (amdgpu_sdma_phase_quantum) {
 355                 unsigned value = amdgpu_sdma_phase_quantum;
 356                 unsigned unit = 0;
 357
 358                 while (value > (SDMA0_PHASE0_QUANTUM__VALUE_MASK >>
 359                                 SDMA0_PHASE0_QUANTUM__VALUE__SHIFT)) {
 360                         value = (value + 1) >> 1;
 361                         unit++;
 362                 }
 363                 if (unit > (SDMA0_PHASE0_QUANTUM__UNIT_MASK >>
 364                             SDMA0_PHASE0_QUANTUM__UNIT__SHIFT)) {
 365                         value = (SDMA0_PHASE0_QUANTUM__VALUE_MASK >>
 366                                  SDMA0_PHASE0_QUANTUM__VALUE__SHIFT);
 367                         unit = (SDMA0_PHASE0_QUANTUM__UNIT_MASK >>
 368                                 SDMA0_PHASE0_QUANTUM__UNIT__SHIFT);
 369                         WARN_ONCE(1,
 370                         "clamping sdma_phase_quantum to %uK clock cycles\n",
 371                                   value << unit);
 372                 }
 373                 phase_quantum =
 374                         value << SDMA0_PHASE0_QUANTUM__VALUE__SHIFT |
 375                         unit  << SDMA0_PHASE0_QUANTUM__UNIT__SHIFT;
 376         }
 377
 378         for (i = 0; i < adev->sdma.num_instances; i++) {
 379                 f32_cntl = RREG32(mmSDMA0_CNTL + sdma_offsets[i]);
 380                 if (enable) {
 381                         f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL,
 382                                         AUTO_CTXSW_ENABLE, 1);
 383                         if (amdgpu_sdma_phase_quantum) {
 384                                 WREG32(mmSDMA0_PHASE0_QUANTUM + sdma_offsets[i],
 385                                        phase_quantum);
 386                                 WREG32(mmSDMA0_PHASE1_QUANTUM + sdma_offsets[i],
 387                                        phase_quantum);
 388                         }
 389                 } else {
 390                         f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL,
 391                                         AUTO_CTXSW_ENABLE, 0);
 392                 }
 393
 394                 WREG32(mmSDMA0_CNTL + sdma_offsets[i], f32_cntl);
 395         }
 396 }
 397
 398 /**
 399  * cik_sdma_enable - stop the async dma engines
 400  *
 401  * @adev: amdgpu_device pointer
 402  * @enable: enable/disable the DMA MEs.
 403  *
 404  * Halt or unhalt the async dma engines (CIK).
 405  */
 406 static void cik_sdma_enable(struct amdgpu_device *adev, bool enable)
 407 {
 408         u32 me_cntl;
 409         int i;
 410
 411         if (!enable) {
 412                 cik_sdma_gfx_stop(adev);
 413                 cik_sdma_rlc_stop(adev);
 414         }
 415
 416         for (i = 0; i < adev->sdma.num_instances; i++) {
 417                 me_cntl = RREG32(mmSDMA0_F32_CNTL + sdma_offsets[i]);
 418                 if (enable)
 419                         me_cntl &= ~SDMA0_F32_CNTL__HALT_MASK;
 420                 else
 421                         me_cntl |= SDMA0_F32_CNTL__HALT_MASK;
 422                 WREG32(mmSDMA0_F32_CNTL + sdma_offsets[i], me_cntl);
 423         }
 424 }
 425
 426 /**
 427  * cik_sdma_gfx_resume - setup and start the async dma engines
 428  *
 429  * @adev: amdgpu_device pointer
 430  *
 431  * Set up the gfx DMA ring buffers and enable them (CIK).
 432  * Returns 0 for success, error for failure.
 433  */
 434 static int cik_sdma_gfx_resume(struct amdgpu_device *adev)
 435 {
 436         struct amdgpu_ring *ring;
 437         u32 rb_cntl, ib_cntl;
 438         u32 rb_bufsz;
 439         u32 wb_offset;
 440         int i, j, r;
 441
 442         for (i = 0; i < adev->sdma.num_instances; i++) {
 443                 ring = &adev->sdma.instance[i].ring;
 444                 wb_offset = (ring->rptr_offs * 4);
 445
 446                 mutex_lock(&adev->srbm_mutex);
 447                 for (j = 0; j < 16; j++) {
 448                         cik_srbm_select(adev, 0, 0, 0, j);
 449                         /* SDMA GFX */
 450                         WREG32(mmSDMA0_GFX_VIRTUAL_ADDR + sdma_offsets[i], 0);
 451                         WREG32(mmSDMA0_GFX_APE1_CNTL + sdma_offsets[i], 0);
 452                         /* XXX SDMA RLC - todo */
 453                 }
 454                 cik_srbm_select(adev, 0, 0, 0, 0);
 455                 mutex_unlock(&adev->srbm_mutex);
 456
 457                 WREG32(mmSDMA0_TILING_CONFIG + sdma_offsets[i],
 458                        adev->gfx.config.gb_addr_config & 0x70);
 459
 460                 WREG32(mmSDMA0_SEM_INCOMPLETE_TIMER_CNTL + sdma_offsets[i], 0);
 461                 WREG32(mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL + sdma_offsets[i], 0);
 462
 463                 /* Set ring buffer size in dwords */
 464                 rb_bufsz = order_base_2(ring->ring_size / 4);
 465                 rb_cntl = rb_bufsz << 1;
 466 #ifdef __BIG_ENDIAN
 467                 rb_cntl |= SDMA0_GFX_RB_CNTL__RB_SWAP_ENABLE_MASK |
 468                         SDMA0_GFX_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK;
 469 #endif
 470                 WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], rb_cntl);
 471
 472                 /* Initialize the ring buffer's read and write pointers */
 473                 WREG32(mmSDMA0_GFX_RB_RPTR + sdma_offsets[i], 0);
 474                 WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[i], 0);
 475                 WREG32(mmSDMA0_GFX_IB_RPTR + sdma_offsets[i], 0);
 476                 WREG32(mmSDMA0_GFX_IB_OFFSET + sdma_offsets[i], 0);
 477
 478                 /* set the wb address whether it's enabled or not */
 479                 WREG32(mmSDMA0_GFX_RB_RPTR_ADDR_HI + sdma_offsets[i],
 480                        upper_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFF);
 481                 WREG32(mmSDMA0_GFX_RB_RPTR_ADDR_LO + sdma_offsets[i],
 482                        ((adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFC));
 483
 484                 rb_cntl |= SDMA0_GFX_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK;
 485
 486                 WREG32(mmSDMA0_GFX_RB_BASE + sdma_offsets[i], ring->gpu_addr >> 8);
 487                 WREG32(mmSDMA0_GFX_RB_BASE_HI + sdma_offsets[i], ring->gpu_addr >> 40);
 488
 489                 ring->wptr = 0;
 490                 WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[i], lower_32_bits(ring->wptr) << 2);
 491
 492                 /* enable DMA RB */
 493                 WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i],
 494                        rb_cntl | SDMA0_GFX_RB_CNTL__RB_ENABLE_MASK);
 495
 496                 ib_cntl = SDMA0_GFX_IB_CNTL__IB_ENABLE_MASK;
 497 #ifdef __BIG_ENDIAN
 498                 ib_cntl |= SDMA0_GFX_IB_CNTL__IB_SWAP_ENABLE_MASK;
 499 #endif
 500                 /* enable DMA IBs */
 501                 WREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i], ib_cntl);
 502
 503                 ring->sched.ready = true;
 504         }
 505
 506         cik_sdma_enable(adev, true);
 507
 508         for (i = 0; i < adev->sdma.num_instances; i++) {
 509                 ring = &adev->sdma.instance[i].ring;
 510                 r = amdgpu_ring_test_helper(ring);
 511                 if (r)
 512                         return r;
 513
 514                 if (adev->mman.buffer_funcs_ring == ring)
 515                         amdgpu_ttm_set_buffer_funcs_status(adev, true);
 516         }
 517
 518         return 0;
 519 }
 520
 521 /**
 522  * cik_sdma_rlc_resume - setup and start the async dma engines
 523  *
 524  * @adev: amdgpu_device pointer
 525  *
 526  * Set up the compute DMA queues and enable them (CIK).
 527  * Returns 0 for success, error for failure.
 528  */
 529 static int cik_sdma_rlc_resume(struct amdgpu_device *adev)
 530 {
 531         /* XXX todo */
 532         return 0;
 533 }
 534
 535 /**
 536  * cik_sdma_load_microcode - load the sDMA ME ucode
 537  *
 538  * @adev: amdgpu_device pointer
 539  *
 540  * Loads the sDMA0/1 ucode.
 541  * Returns 0 for success, -EINVAL if the ucode is not available.
 542  */
 543 static int cik_sdma_load_microcode(struct amdgpu_device *adev)
 544 {
 545         const struct sdma_firmware_header_v1_0 *hdr;
 546         const __le32 *fw_data;
 547         u32 fw_size;
 548         int i, j;
 549
 550         /* halt the MEs */
 551         cik_sdma_enable(adev, false);
 552
 553         for (i = 0; i < adev->sdma.num_instances; i++) {
 554                 if (!adev->sdma.instance[i].fw)
 555                         return -EINVAL;
 556                 hdr = (const struct sdma_firmware_header_v1_0 *)adev->sdma.instance[i].fw->data;
 557                 amdgpu_ucode_print_sdma_hdr(&hdr->header);
 558                 fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
 559                 adev->sdma.instance[i].fw_version = le32_to_cpu(hdr->header.ucode_version);
 560                 adev->sdma.instance[i].feature_version = le32_to_cpu(hdr->ucode_feature_version);
 561                 if (adev->sdma.instance[i].feature_version >= 20)
 562                         adev->sdma.instance[i].burst_nop = true;
 563                 fw_data = (const __le32 *)
 564                         (adev->sdma.instance[i].fw->data + le32_to_cpu(hdr->header.ucode_array_offset_bytes));
 565                 WREG32(mmSDMA0_UCODE_ADDR + sdma_offsets[i], 0);
 566                 for (j = 0; j < fw_size; j++)
 567                         WREG32(mmSDMA0_UCODE_DATA + sdma_offsets[i], le32_to_cpup(fw_data++));
 568                 WREG32(mmSDMA0_UCODE_ADDR + sdma_offsets[i], adev->sdma.instance[i].fw_version);
 569         }
 570
 571         return 0;
 572 }
 573
 574 /**
 575  * cik_sdma_start - setup and start the async dma engines
 576  *
 577  * @adev: amdgpu_device pointer
 578  *
 579  * Set up the DMA engines and enable them (CIK).
 580  * Returns 0 for success, error for failure.
 581  */
 582 static int cik_sdma_start(struct amdgpu_device *adev)
 583 {
 584         int r;
 585
 586         r = cik_sdma_load_microcode(adev);
 587         if (r)
 588                 return r;
 589
 590         /* halt the engine before programing */
 591         cik_sdma_enable(adev, false);
 592         /* enable sdma ring preemption */
 593         cik_ctx_switch_enable(adev, true);
 594
 595         /* start the gfx rings and rlc compute queues */
 596         r = cik_sdma_gfx_resume(adev);
 597         if (r)
 598                 return r;
 599         r = cik_sdma_rlc_resume(adev);
 600         if (r)
 601                 return r;
 602
 603         return 0;
 604 }
 605
 606 /**
 607  * cik_sdma_ring_test_ring - simple async dma engine test
 608  *
 609  * @ring: amdgpu_ring structure holding ring information
 610  *
 611  * Test the DMA engine by writing using it to write an
 612  * value to memory. (CIK).
 613  * Returns 0 for success, error for failure.
 614  */
 615 static int cik_sdma_ring_test_ring(struct amdgpu_ring *ring)
 616 {
 617         struct amdgpu_device *adev = ring->adev;
 618         unsigned i;
 619         unsigned index;
 620         int r;
 621         u32 tmp;
 622         u64 gpu_addr;
 623
 624         r = amdgpu_device_wb_get(adev, &index);
 625         if (r)
 626                 return r;
 627
 628         gpu_addr = adev->wb.gpu_addr + (index * 4);
 629         tmp = 0xCAFEDEAD;
 630         adev->wb.wb[index] = cpu_to_le32(tmp);
 631
 632         r = amdgpu_ring_alloc(ring, 5);
 633         if (r)
 634                 goto error_free_wb;
 635
 636         amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_WRITE, SDMA_WRITE_SUB_OPCODE_LINEAR, 0));
 637         amdgpu_ring_write(ring, lower_32_bits(gpu_addr));
 638         amdgpu_ring_write(ring, upper_32_bits(gpu_addr));
 639         amdgpu_ring_write(ring, 1); /* number of DWs to follow */
 640         amdgpu_ring_write(ring, 0xDEADBEEF);
 641         amdgpu_ring_commit(ring);
 642
 643         for (i = 0; i < adev->usec_timeout; i++) {
 644                 tmp = le32_to_cpu(adev->wb.wb[index]);
 645                 if (tmp == 0xDEADBEEF)
 646                         break;
 647                 udelay(1);
 648         }
 649
 650         if (i >= adev->usec_timeout)
 651                 r = -ETIMEDOUT;
 652
 653 error_free_wb:
 654         amdgpu_device_wb_free(adev, index);
 655         return r;
 656 }
 657
 658 /**
 659  * cik_sdma_ring_test_ib - test an IB on the DMA engine
 660  *
 661  * @ring: amdgpu_ring structure holding ring information
 662  * @timeout: timeout value in jiffies, or MAX_SCHEDULE_TIMEOUT
 663  *
 664  * Test a simple IB in the DMA ring (CIK).
 665  * Returns 0 on success, error on failure.
 666  */
 667 static int cik_sdma_ring_test_ib(struct amdgpu_ring *ring, long timeout)
 668 {
 669         struct amdgpu_device *adev = ring->adev;
 670         struct amdgpu_ib ib;
 671         struct dma_fence *f = NULL;
 672         unsigned index;
 673         u32 tmp = 0;
 674         u64 gpu_addr;
 675         long r;
 676
 677         r = amdgpu_device_wb_get(adev, &index);
 678         if (r)
 679                 return r;
 680
 681         gpu_addr = adev->wb.gpu_addr + (index * 4);
 682         tmp = 0xCAFEDEAD;
 683         adev->wb.wb[index] = cpu_to_le32(tmp);
 684         memset(&ib, 0, sizeof(ib));
 685         r = amdgpu_ib_get(adev, NULL, 256,
 686                                         AMDGPU_IB_POOL_DIRECT, &ib);
 687         if (r)
 688                 goto err0;
 689
 690         ib.ptr[0] = SDMA_PACKET(SDMA_OPCODE_WRITE,
 691                                 SDMA_WRITE_SUB_OPCODE_LINEAR, 0);
 692         ib.ptr[1] = lower_32_bits(gpu_addr);
 693         ib.ptr[2] = upper_32_bits(gpu_addr);
 694         ib.ptr[3] = 1;
 695         ib.ptr[4] = 0xDEADBEEF;
 696         ib.length_dw = 5;
 697         r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f);
 698         if (r)
 699                 goto err1;
 700
 701         r = dma_fence_wait_timeout(f, false, timeout);
 702         if (r == 0) {
 703                 r = -ETIMEDOUT;
 704                 goto err1;
 705         } else if (r < 0) {
 706                 goto err1;
 707         }
 708         tmp = le32_to_cpu(adev->wb.wb[index]);
 709         if (tmp == 0xDEADBEEF)
 710                 r = 0;
 711         else
 712                 r = -EINVAL;
 713
 714 err1:
 715         amdgpu_ib_free(adev, &ib, NULL);
 716         dma_fence_put(f);
 717 err0:
 718         amdgpu_device_wb_free(adev, index);
 719         return r;
 720 }
 721
 722 /**
 723  * cik_sdma_vm_copy_pte - update PTEs by copying them from the GART
 724  *
 725  * @ib: indirect buffer to fill with commands
 726  * @pe: addr of the page entry
 727  * @src: src addr to copy from
 728  * @count: number of page entries to update
 729  *
 730  * Update PTEs by copying them from the GART using sDMA (CIK).
 731  */
 732 static void cik_sdma_vm_copy_pte(struct amdgpu_ib *ib,
 733                                  uint64_t pe, uint64_t src,
 734                                  unsigned count)
 735 {
 736         unsigned bytes = count * 8;
 737
 738         ib->ptr[ib->length_dw++] = SDMA_PACKET(SDMA_OPCODE_COPY,
 739                 SDMA_WRITE_SUB_OPCODE_LINEAR, 0);
 740         ib->ptr[ib->length_dw++] = bytes;
 741         ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */
 742         ib->ptr[ib->length_dw++] = lower_32_bits(src);
 743         ib->ptr[ib->length_dw++] = upper_32_bits(src);
 744         ib->ptr[ib->length_dw++] = lower_32_bits(pe);
 745         ib->ptr[ib->length_dw++] = upper_32_bits(pe);
 746 }
 747
 748 /**
 749  * cik_sdma_vm_write_pte - update PTEs by writing them manually
 750  *
 751  * @ib: indirect buffer to fill with commands
 752  * @pe: addr of the page entry
 753  * @value: dst addr to write into pe
 754  * @count: number of page entries to update
 755  * @incr: increase next addr by incr bytes
 756  *
 757  * Update PTEs by writing them manually using sDMA (CIK).
 758  */
 759 static void cik_sdma_vm_write_pte(struct amdgpu_ib *ib, uint64_t pe,
 760                                   uint64_t value, unsigned count,
 761                                   uint32_t incr)
 762 {
 763         unsigned ndw = count * 2;
 764
 765         ib->ptr[ib->length_dw++] = SDMA_PACKET(SDMA_OPCODE_WRITE,
 766                 SDMA_WRITE_SUB_OPCODE_LINEAR, 0);
 767         ib->ptr[ib->length_dw++] = lower_32_bits(pe);
 768         ib->ptr[ib->length_dw++] = upper_32_bits(pe);
 769         ib->ptr[ib->length_dw++] = ndw;
 770         for (; ndw > 0; ndw -= 2) {
 771                 ib->ptr[ib->length_dw++] = lower_32_bits(value);
 772                 ib->ptr[ib->length_dw++] = upper_32_bits(value);
 773                 value += incr;
 774         }
 775 }
 776
 777 /**
 778  * cik_sdma_vm_set_pte_pde - update the page tables using sDMA
 779  *
 780  * @ib: indirect buffer to fill with commands
 781  * @pe: addr of the page entry
 782  * @addr: dst addr to write into pe
 783  * @count: number of page entries to update
 784  * @incr: increase next addr by incr bytes
 785  * @flags: access flags
 786  *
 787  * Update the page tables using sDMA (CIK).
 788  */
 789 static void cik_sdma_vm_set_pte_pde(struct amdgpu_ib *ib, uint64_t pe,
 790                                     uint64_t addr, unsigned count,
 791                                     uint32_t incr, uint64_t flags)
 792 {
 793         /* for physically contiguous pages (vram) */
 794         ib->ptr[ib->length_dw++] = SDMA_PACKET(SDMA_OPCODE_GENERATE_PTE_PDE, 0, 0);
 795         ib->ptr[ib->length_dw++] = lower_32_bits(pe); /* dst addr */
 796         ib->ptr[ib->length_dw++] = upper_32_bits(pe);
 797         ib->ptr[ib->length_dw++] = lower_32_bits(flags); /* mask */
 798         ib->ptr[ib->length_dw++] = upper_32_bits(flags);
 799         ib->ptr[ib->length_dw++] = lower_32_bits(addr); /* value */
 800         ib->ptr[ib->length_dw++] = upper_32_bits(addr);
 801         ib->ptr[ib->length_dw++] = incr; /* increment size */
 802         ib->ptr[ib->length_dw++] = 0;
 803         ib->ptr[ib->length_dw++] = count; /* number of entries */
 804 }
 805
 806 /**
 807  * cik_sdma_ring_pad_ib - pad the IB to the required number of dw
 808  *
 809  * @ring: amdgpu_ring structure holding ring information
 810  * @ib: indirect buffer to fill with padding
 811  *
 812  */
 813 static void cik_sdma_ring_pad_ib(struct amdgpu_ring *ring, struct amdgpu_ib *ib)
 814 {
 815         struct amdgpu_sdma_instance *sdma = amdgpu_sdma_get_instance_from_ring(ring);
 816         u32 pad_count;
 817         int i;
 818
 819         pad_count = (-ib->length_dw) & 7;
 820         for (i = 0; i < pad_count; i++)
 821                 if (sdma && sdma->burst_nop && (i == 0))
 822                         ib->ptr[ib->length_dw++] =
 823                                         SDMA_PACKET(SDMA_OPCODE_NOP, 0, 0) |
 824                                         SDMA_NOP_COUNT(pad_count - 1);
 825                 else
 826                         ib->ptr[ib->length_dw++] =
 827                                         SDMA_PACKET(SDMA_OPCODE_NOP, 0, 0);
 828 }
 829
 830 /**
 831  * cik_sdma_ring_emit_pipeline_sync - sync the pipeline
 832  *
 833  * @ring: amdgpu_ring pointer
 834  *
 835  * Make sure all previous operations are completed (CIK).
 836  */
 837 static void cik_sdma_ring_emit_pipeline_sync(struct amdgpu_ring *ring)
 838 {
 839         uint32_t seq = ring->fence_drv.sync_seq;
 840         uint64_t addr = ring->fence_drv.gpu_addr;
 841
 842         /* wait for idle */
 843         amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_POLL_REG_MEM, 0,
 844                                             SDMA_POLL_REG_MEM_EXTRA_OP(0) |
 845                                             SDMA_POLL_REG_MEM_EXTRA_FUNC(3) | /* equal */
 846                                             SDMA_POLL_REG_MEM_EXTRA_M));
 847         amdgpu_ring_write(ring, addr & 0xfffffffc);
 848         amdgpu_ring_write(ring, upper_32_bits(addr) & 0xffffffff);
 849         amdgpu_ring_write(ring, seq); /* reference */
 850         amdgpu_ring_write(ring, 0xffffffff); /* mask */
 851         amdgpu_ring_write(ring, (0xfff << 16) | 4); /* retry count, poll interval */
 852 }
 853
 854 /**
 855  * cik_sdma_ring_emit_vm_flush - cik vm flush using sDMA
 856  *
 857  * @ring: amdgpu_ring pointer
 858  * @vmid: vmid number to use
 859  * @pd_addr: address
 860  *
 861  * Update the page table base and flush the VM TLB
 862  * using sDMA (CIK).
 863  */
 864 static void cik_sdma_ring_emit_vm_flush(struct amdgpu_ring *ring,
 865                                         unsigned vmid, uint64_t pd_addr)
 866 {
 867         u32 extra_bits = (SDMA_POLL_REG_MEM_EXTRA_OP(0) |
 868                           SDMA_POLL_REG_MEM_EXTRA_FUNC(0)); /* always */
 869
 870         amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr);
 871
 872         amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_POLL_REG_MEM, 0, extra_bits));
 873         amdgpu_ring_write(ring, mmVM_INVALIDATE_REQUEST << 2);
 874         amdgpu_ring_write(ring, 0);
 875         amdgpu_ring_write(ring, 0); /* reference */
 876         amdgpu_ring_write(ring, 0); /* mask */
 877         amdgpu_ring_write(ring, (0xfff << 16) | 10); /* retry count, poll interval */
 878 }
 879
 880 static void cik_sdma_ring_emit_wreg(struct amdgpu_ring *ring,
 881                                     uint32_t reg, uint32_t val)
 882 {
 883         amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_SRBM_WRITE, 0, 0xf000));
 884         amdgpu_ring_write(ring, reg);
 885         amdgpu_ring_write(ring, val);
 886 }
 887
 888 static void cik_enable_sdma_mgcg(struct amdgpu_device *adev,
 889                                  bool enable)
 890 {
 891         u32 orig, data;
 892
 893         if (enable && (adev->cg_flags & AMD_CG_SUPPORT_SDMA_MGCG)) {
 894                 WREG32(mmSDMA0_CLK_CTRL + SDMA0_REGISTER_OFFSET, 0x00000100);
 895                 WREG32(mmSDMA0_CLK_CTRL + SDMA1_REGISTER_OFFSET, 0x00000100);
 896         } else {
 897                 orig = data = RREG32(mmSDMA0_CLK_CTRL + SDMA0_REGISTER_OFFSET);
 898                 data |= 0xff000000;
 899                 if (data != orig)
 900                         WREG32(mmSDMA0_CLK_CTRL + SDMA0_REGISTER_OFFSET, data);
 901
 902                 orig = data = RREG32(mmSDMA0_CLK_CTRL + SDMA1_REGISTER_OFFSET);
 903                 data |= 0xff000000;
 904                 if (data != orig)
 905                         WREG32(mmSDMA0_CLK_CTRL + SDMA1_REGISTER_OFFSET, data);
 906         }
 907 }
 908
 909 static void cik_enable_sdma_mgls(struct amdgpu_device *adev,
 910                                  bool enable)
 911 {
 912         u32 orig, data;
 913
 914         if (enable && (adev->cg_flags & AMD_CG_SUPPORT_SDMA_LS)) {
 915                 orig = data = RREG32(mmSDMA0_POWER_CNTL + SDMA0_REGISTER_OFFSET);
 916                 data |= 0x100;
 917                 if (orig != data)
 918                         WREG32(mmSDMA0_POWER_CNTL + SDMA0_REGISTER_OFFSET, data);
 919
 920                 orig = data = RREG32(mmSDMA0_POWER_CNTL + SDMA1_REGISTER_OFFSET);
 921                 data |= 0x100;
 922                 if (orig != data)
 923                         WREG32(mmSDMA0_POWER_CNTL + SDMA1_REGISTER_OFFSET, data);
 924         } else {
 925                 orig = data = RREG32(mmSDMA0_POWER_CNTL + SDMA0_REGISTER_OFFSET);
 926                 data &= ~0x100;
 927                 if (orig != data)
 928                         WREG32(mmSDMA0_POWER_CNTL + SDMA0_REGISTER_OFFSET, data);
 929
 930                 orig = data = RREG32(mmSDMA0_POWER_CNTL + SDMA1_REGISTER_OFFSET);
 931                 data &= ~0x100;
 932                 if (orig != data)
 933                         WREG32(mmSDMA0_POWER_CNTL + SDMA1_REGISTER_OFFSET, data);
 934         }
 935 }
 936
 937 static int cik_sdma_early_init(void *handle)
 938 {
 939         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 940
 941         adev->sdma.num_instances = SDMA_MAX_INSTANCE;
 942
 943         cik_sdma_set_ring_funcs(adev);
 944         cik_sdma_set_irq_funcs(adev);
 945         cik_sdma_set_buffer_funcs(adev);
 946         cik_sdma_set_vm_pte_funcs(adev);
 947
 948         return 0;
 949 }
 950
 951 static int cik_sdma_sw_init(void *handle)
 952 {
 953         struct amdgpu_ring *ring;
 954         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 955         int r, i;
 956
 957         r = cik_sdma_init_microcode(adev);
 958         if (r) {
 959                 DRM_ERROR("Failed to load sdma firmware!\n");
 960                 return r;
 961         }
 962
 963         /* SDMA trap event */
 964         r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, 224,
 965                               &adev->sdma.trap_irq);
 966         if (r)
 967                 return r;
 968
 969         /* SDMA Privileged inst */
 970         r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, 241,
 971                               &adev->sdma.illegal_inst_irq);
 972         if (r)
 973                 return r;
 974
 975         /* SDMA Privileged inst */
 976         r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, 247,
 977                               &adev->sdma.illegal_inst_irq);
 978         if (r)
 979                 return r;
 980
 981         for (i = 0; i < adev->sdma.num_instances; i++) {
 982                 ring = &adev->sdma.instance[i].ring;
 983                 ring->ring_obj = NULL;
 984                 sprintf(ring->name, "sdma%d", i);
 985                 r = amdgpu_ring_init(adev, ring, 1024,
 986                                      &adev->sdma.trap_irq,
 987                                      (i == 0) ? AMDGPU_SDMA_IRQ_INSTANCE0 :
 988                                      AMDGPU_SDMA_IRQ_INSTANCE1,
 989                                      AMDGPU_RING_PRIO_DEFAULT, NULL);
 990                 if (r)
 991                         return r;
 992         }
 993
 994         return r;
 995 }
 996
 997 static int cik_sdma_sw_fini(void *handle)
 998 {
 999         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1000         int i;
1001
1002         for (i = 0; i < adev->sdma.num_instances; i++)
1003                 amdgpu_ring_fini(&adev->sdma.instance[i].ring);
1004
1005         cik_sdma_free_microcode(adev);
1006         return 0;
1007 }
1008
1009 static int cik_sdma_hw_init(void *handle)
1010 {
1011         int r;
1012         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1013
1014         r = cik_sdma_start(adev);
1015         if (r)
1016                 return r;
1017
1018         return r;
1019 }
1020
1021 static int cik_sdma_hw_fini(void *handle)
1022 {
1023         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1024
1025         cik_ctx_switch_enable(adev, false);
1026         cik_sdma_enable(adev, false);
1027
1028         return 0;
1029 }
1030
1031 static int cik_sdma_suspend(void *handle)
1032 {
1033         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1034
1035         return cik_sdma_hw_fini(adev);
1036 }
1037
1038 static int cik_sdma_resume(void *handle)
1039 {
1040         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1041
1042         cik_sdma_soft_reset(handle);
1043
1044         return cik_sdma_hw_init(adev);
1045 }
1046
1047 static bool cik_sdma_is_idle(void *handle)
1048 {
1049         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1050         u32 tmp = RREG32(mmSRBM_STATUS2);
1051
1052         if (tmp & (SRBM_STATUS2__SDMA_BUSY_MASK |
1053                                 SRBM_STATUS2__SDMA1_BUSY_MASK))
1054             return false;
1055
1056         return true;
1057 }
1058
1059 static int cik_sdma_wait_for_idle(void *handle)
1060 {
1061         unsigned i;
1062         u32 tmp;
1063         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1064
1065         for (i = 0; i < adev->usec_timeout; i++) {
1066                 tmp = RREG32(mmSRBM_STATUS2) & (SRBM_STATUS2__SDMA_BUSY_MASK |
1067                                 SRBM_STATUS2__SDMA1_BUSY_MASK);
1068
1069                 if (!tmp)
1070                         return 0;
1071                 udelay(1);
1072         }
1073         return -ETIMEDOUT;
1074 }
1075
1076 static int cik_sdma_soft_reset(void *handle)
1077 {
1078         u32 srbm_soft_reset = 0;
1079         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1080         u32 tmp;
1081
1082         /* sdma0 */
1083         tmp = RREG32(mmSDMA0_F32_CNTL + SDMA0_REGISTER_OFFSET);
1084         tmp |= SDMA0_F32_CNTL__HALT_MASK;
1085         WREG32(mmSDMA0_F32_CNTL + SDMA0_REGISTER_OFFSET, tmp);
1086         srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_SDMA_MASK;
1087
1088         /* sdma1 */
1089         tmp = RREG32(mmSDMA0_F32_CNTL + SDMA1_REGISTER_OFFSET);
1090         tmp |= SDMA0_F32_CNTL__HALT_MASK;
1091         WREG32(mmSDMA0_F32_CNTL + SDMA1_REGISTER_OFFSET, tmp);
1092         srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_SDMA1_MASK;
1093
1094         if (srbm_soft_reset) {
1095                 tmp = RREG32(mmSRBM_SOFT_RESET);
1096                 tmp |= srbm_soft_reset;
1097                 dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
1098                 WREG32(mmSRBM_SOFT_RESET, tmp);
1099                 tmp = RREG32(mmSRBM_SOFT_RESET);
1100
1101                 udelay(50);
1102
1103                 tmp &= ~srbm_soft_reset;
1104                 WREG32(mmSRBM_SOFT_RESET, tmp);
1105                 tmp = RREG32(mmSRBM_SOFT_RESET);
1106
1107                 /* Wait a little for things to settle down */
1108                 udelay(50);
1109         }
1110
1111         return 0;
1112 }
1113
1114 static int cik_sdma_set_trap_irq_state(struct amdgpu_device *adev,
1115                                        struct amdgpu_irq_src *src,
1116                                        unsigned type,
1117                                        enum amdgpu_interrupt_state state)
1118 {
1119         u32 sdma_cntl;
1120
1121         switch (type) {
1122         case AMDGPU_SDMA_IRQ_INSTANCE0:
1123                 switch (state) {
1124                 case AMDGPU_IRQ_STATE_DISABLE:
1125                         sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET);
1126                         sdma_cntl &= ~SDMA0_CNTL__TRAP_ENABLE_MASK;
1127                         WREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET, sdma_cntl);
1128                         break;
1129                 case AMDGPU_IRQ_STATE_ENABLE:
1130                         sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET);
1131                         sdma_cntl |= SDMA0_CNTL__TRAP_ENABLE_MASK;
1132                         WREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET, sdma_cntl);
1133                         break;
1134                 default:
1135                         break;
1136                 }
1137                 break;
1138         case AMDGPU_SDMA_IRQ_INSTANCE1:
1139                 switch (state) {
1140                 case AMDGPU_IRQ_STATE_DISABLE:
1141                         sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET);
1142                         sdma_cntl &= ~SDMA0_CNTL__TRAP_ENABLE_MASK;
1143                         WREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET, sdma_cntl);
1144                         break;
1145                 case AMDGPU_IRQ_STATE_ENABLE:
1146                         sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET);
1147                         sdma_cntl |= SDMA0_CNTL__TRAP_ENABLE_MASK;
1148                         WREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET, sdma_cntl);
1149                         break;
1150                 default:
1151                         break;
1152                 }
1153                 break;
1154         default:
1155                 break;
1156         }
1157         return 0;
1158 }
1159
1160 static int cik_sdma_process_trap_irq(struct amdgpu_device *adev,
1161                                      struct amdgpu_irq_src *source,
1162                                      struct amdgpu_iv_entry *entry)
1163 {
1164         u8 instance_id, queue_id;
1165
1166         instance_id = (entry->ring_id & 0x3) >> 0;
1167         queue_id = (entry->ring_id & 0xc) >> 2;
1168         DRM_DEBUG("IH: SDMA trap\n");
1169         switch (instance_id) {
1170         case 0:
1171                 switch (queue_id) {
1172                 case 0:
1173                         amdgpu_fence_process(&adev->sdma.instance[0].ring);
1174                         break;
1175                 case 1:
1176                         /* XXX compute */
1177                         break;
1178                 case 2:
1179                         /* XXX compute */
1180                         break;
1181                 }
1182                 break;
1183         case 1:
1184                 switch (queue_id) {
1185                 case 0:
1186                         amdgpu_fence_process(&adev->sdma.instance[1].ring);
1187                         break;
1188                 case 1:
1189                         /* XXX compute */
1190                         break;
1191                 case 2:
1192                         /* XXX compute */
1193                         break;
1194                 }
1195                 break;
1196         }
1197
1198         return 0;
1199 }
1200
1201 static int cik_sdma_process_illegal_inst_irq(struct amdgpu_device *adev,
1202                                              struct amdgpu_irq_src *source,
1203                                              struct amdgpu_iv_entry *entry)
1204 {
1205         u8 instance_id;
1206
1207         DRM_ERROR("Illegal instruction in SDMA command stream\n");
1208         instance_id = (entry->ring_id & 0x3) >> 0;
1209         drm_sched_fault(&adev->sdma.instance[instance_id].ring.sched);
1210         return 0;
1211 }
1212
1213 static int cik_sdma_set_clockgating_state(void *handle,
1214                                           enum amd_clockgating_state state)
1215 {
1216         bool gate = false;
1217         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1218
1219         if (state == AMD_CG_STATE_GATE)
1220                 gate = true;
1221
1222         cik_enable_sdma_mgcg(adev, gate);
1223         cik_enable_sdma_mgls(adev, gate);
1224
1225         return 0;
1226 }
1227
1228 static int cik_sdma_set_powergating_state(void *handle,
1229                                           enum amd_powergating_state state)
1230 {
1231         return 0;
1232 }
1233
1234 static const struct amd_ip_funcs cik_sdma_ip_funcs = {
1235         .name = "cik_sdma",
1236         .early_init = cik_sdma_early_init,
1237         .late_init = NULL,
1238         .sw_init = cik_sdma_sw_init,
1239         .sw_fini = cik_sdma_sw_fini,
1240         .hw_init = cik_sdma_hw_init,
1241         .hw_fini = cik_sdma_hw_fini,
1242         .suspend = cik_sdma_suspend,
1243         .resume = cik_sdma_resume,
1244         .is_idle = cik_sdma_is_idle,
1245         .wait_for_idle = cik_sdma_wait_for_idle,
1246         .soft_reset = cik_sdma_soft_reset,
1247         .set_clockgating_state = cik_sdma_set_clockgating_state,
1248         .set_powergating_state = cik_sdma_set_powergating_state,
1249 };
1250
1251 static const struct amdgpu_ring_funcs cik_sdma_ring_funcs = {
1252         .type = AMDGPU_RING_TYPE_SDMA,
1253         .align_mask = 0xf,
1254         .nop = SDMA_PACKET(SDMA_OPCODE_NOP, 0, 0),
1255         .support_64bit_ptrs = false,
1256         .get_rptr = cik_sdma_ring_get_rptr,
1257         .get_wptr = cik_sdma_ring_get_wptr,
1258         .set_wptr = cik_sdma_ring_set_wptr,
1259         .emit_frame_size =
1260                 6 + /* cik_sdma_ring_emit_hdp_flush */
1261                 3 + /* hdp invalidate */
1262                 6 + /* cik_sdma_ring_emit_pipeline_sync */
1263                 CIK_FLUSH_GPU_TLB_NUM_WREG * 3 + 6 + /* cik_sdma_ring_emit_vm_flush */
1264                 9 + 9 + 9, /* cik_sdma_ring_emit_fence x3 for user fence, vm fence */
1265         .emit_ib_size = 7 + 4, /* cik_sdma_ring_emit_ib */
1266         .emit_ib = cik_sdma_ring_emit_ib,
1267         .emit_fence = cik_sdma_ring_emit_fence,
1268         .emit_pipeline_sync = cik_sdma_ring_emit_pipeline_sync,
1269         .emit_vm_flush = cik_sdma_ring_emit_vm_flush,
1270         .emit_hdp_flush = cik_sdma_ring_emit_hdp_flush,
1271         .test_ring = cik_sdma_ring_test_ring,
1272         .test_ib = cik_sdma_ring_test_ib,
1273         .insert_nop = cik_sdma_ring_insert_nop,
1274         .pad_ib = cik_sdma_ring_pad_ib,
1275         .emit_wreg = cik_sdma_ring_emit_wreg,
1276 };
1277
1278 static void cik_sdma_set_ring_funcs(struct amdgpu_device *adev)
1279 {
1280         int i;
1281
1282         for (i = 0; i < adev->sdma.num_instances; i++) {
1283                 adev->sdma.instance[i].ring.funcs = &cik_sdma_ring_funcs;
1284                 adev->sdma.instance[i].ring.me = i;
1285         }
1286 }
1287
1288 static const struct amdgpu_irq_src_funcs cik_sdma_trap_irq_funcs = {
1289         .set = cik_sdma_set_trap_irq_state,
1290         .process = cik_sdma_process_trap_irq,
1291 };
1292
1293 static const struct amdgpu_irq_src_funcs cik_sdma_illegal_inst_irq_funcs = {
1294         .process = cik_sdma_process_illegal_inst_irq,
1295 };
1296
1297 static void cik_sdma_set_irq_funcs(struct amdgpu_device *adev)
1298 {
1299         adev->sdma.trap_irq.num_types = AMDGPU_SDMA_IRQ_LAST;
1300         adev->sdma.trap_irq.funcs = &cik_sdma_trap_irq_funcs;
1301         adev->sdma.illegal_inst_irq.funcs = &cik_sdma_illegal_inst_irq_funcs;
1302 }
1303
1304 /**
1305  * cik_sdma_emit_copy_buffer - copy buffer using the sDMA engine
1306  *
1307  * @ib: indirect buffer to copy to
1308  * @src_offset: src GPU address
1309  * @dst_offset: dst GPU address
1310  * @byte_count: number of bytes to xfer
1311  * @tmz: is this a secure operation
1312  *
1313  * Copy GPU buffers using the DMA engine (CIK).
1314  * Used by the amdgpu ttm implementation to move pages if
1315  * registered as the asic copy callback.
1316  */
1317 static void cik_sdma_emit_copy_buffer(struct amdgpu_ib *ib,
1318                                       uint64_t src_offset,
1319                                       uint64_t dst_offset,
1320                                       uint32_t byte_count,
1321                                       bool tmz)
1322 {
1323         ib->ptr[ib->length_dw++] = SDMA_PACKET(SDMA_OPCODE_COPY, SDMA_COPY_SUB_OPCODE_LINEAR, 0);
1324         ib->ptr[ib->length_dw++] = byte_count;
1325         ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */
1326         ib->ptr[ib->length_dw++] = lower_32_bits(src_offset);
1327         ib->ptr[ib->length_dw++] = upper_32_bits(src_offset);
1328         ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset);
1329         ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset);
1330 }
1331
1332 /**
1333  * cik_sdma_emit_fill_buffer - fill buffer using the sDMA engine
1334  *
1335  * @ib: indirect buffer to fill
1336  * @src_data: value to write to buffer
1337  * @dst_offset: dst GPU address
1338  * @byte_count: number of bytes to xfer
1339  *
1340  * Fill GPU buffers using the DMA engine (CIK).
1341  */
1342 static void cik_sdma_emit_fill_buffer(struct amdgpu_ib *ib,
1343                                       uint32_t src_data,
1344                                       uint64_t dst_offset,
1345                                       uint32_t byte_count)
1346 {
1347         ib->ptr[ib->length_dw++] = SDMA_PACKET(SDMA_OPCODE_CONSTANT_FILL, 0, 0);
1348         ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset);
1349         ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset);
1350         ib->ptr[ib->length_dw++] = src_data;
1351         ib->ptr[ib->length_dw++] = byte_count;
1352 }
1353
1354 static const struct amdgpu_buffer_funcs cik_sdma_buffer_funcs = {
1355         .copy_max_bytes = 0x1fffff,
1356         .copy_num_dw = 7,
1357         .emit_copy_buffer = cik_sdma_emit_copy_buffer,
1358
1359         .fill_max_bytes = 0x1fffff,
1360         .fill_num_dw = 5,
1361         .emit_fill_buffer = cik_sdma_emit_fill_buffer,
1362 };
1363
1364 static void cik_sdma_set_buffer_funcs(struct amdgpu_device *adev)
1365 {
1366         adev->mman.buffer_funcs = &cik_sdma_buffer_funcs;
1367         adev->mman.buffer_funcs_ring = &adev->sdma.instance[0].ring;
1368 }
1369
1370 static const struct amdgpu_vm_pte_funcs cik_sdma_vm_pte_funcs = {
1371         .copy_pte_num_dw = 7,
1372         .copy_pte = cik_sdma_vm_copy_pte,
1373
1374         .write_pte = cik_sdma_vm_write_pte,
1375         .set_pte_pde = cik_sdma_vm_set_pte_pde,
1376 };
1377
1378 static void cik_sdma_set_vm_pte_funcs(struct amdgpu_device *adev)
1379 {
1380         unsigned i;
1381
1382         adev->vm_manager.vm_pte_funcs = &cik_sdma_vm_pte_funcs;
1383         for (i = 0; i < adev->sdma.num_instances; i++) {
1384                 adev->vm_manager.vm_pte_scheds[i] =
1385                         &adev->sdma.instance[i].ring.sched;
1386         }
1387         adev->vm_manager.vm_pte_num_scheds = adev->sdma.num_instances;
1388 }
1389
1390 const struct amdgpu_ip_block_version cik_sdma_ip_block =
1391 {
1392         .type = AMD_IP_BLOCK_TYPE_SDMA,
1393         .major = 2,
1394         .minor = 0,
1395         .rev = 0,
1396         .funcs = &cik_sdma_ip_funcs,
1397 };