drivers/gpu/drm/amd/amdgpu/cik_sdma.c

   1 /*
   2  * Copyright 2013 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: Alex Deucher
  23  */
  24
  25 #include <linux/firmware.h>
  26 #include <linux/module.h>
  27
  28 #include "amdgpu.h"
  29 #include "amdgpu_ucode.h"
  30 #include "amdgpu_trace.h"
  31 #include "cikd.h"
  32 #include "cik.h"
  33
  34 #include "bif/bif_4_1_d.h"
  35 #include "bif/bif_4_1_sh_mask.h"
  36
  37 #include "gca/gfx_7_2_d.h"
  38 #include "gca/gfx_7_2_enum.h"
  39 #include "gca/gfx_7_2_sh_mask.h"
  40
  41 #include "gmc/gmc_7_1_d.h"
  42 #include "gmc/gmc_7_1_sh_mask.h"
  43
  44 #include "oss/oss_2_0_d.h"
  45 #include "oss/oss_2_0_sh_mask.h"
  46
  47 static const u32 sdma_offsets[SDMA_MAX_INSTANCE] =
  48 {
  49         SDMA0_REGISTER_OFFSET,
  50         SDMA1_REGISTER_OFFSET
  51 };
  52
  53 static void cik_sdma_set_ring_funcs(struct amdgpu_device *adev);
  54 static void cik_sdma_set_irq_funcs(struct amdgpu_device *adev);
  55 static void cik_sdma_set_buffer_funcs(struct amdgpu_device *adev);
  56 static void cik_sdma_set_vm_pte_funcs(struct amdgpu_device *adev);
  57 static int cik_sdma_soft_reset(void *handle);
  58
  59 MODULE_FIRMWARE("amdgpu/bonaire_sdma.bin");
  60 MODULE_FIRMWARE("amdgpu/bonaire_sdma1.bin");
  61 MODULE_FIRMWARE("amdgpu/hawaii_sdma.bin");
  62 MODULE_FIRMWARE("amdgpu/hawaii_sdma1.bin");
  63 MODULE_FIRMWARE("amdgpu/kaveri_sdma.bin");
  64 MODULE_FIRMWARE("amdgpu/kaveri_sdma1.bin");
  65 MODULE_FIRMWARE("amdgpu/kabini_sdma.bin");
  66 MODULE_FIRMWARE("amdgpu/kabini_sdma1.bin");
  67 MODULE_FIRMWARE("amdgpu/mullins_sdma.bin");
  68 MODULE_FIRMWARE("amdgpu/mullins_sdma1.bin");
  69
  70 u32 amdgpu_cik_gpu_check_soft_reset(struct amdgpu_device *adev);
  71
  72
  73 static void cik_sdma_free_microcode(struct amdgpu_device *adev)
  74 {
  75         int i;
  76         for (i = 0; i < adev->sdma.num_instances; i++) {
  77                         release_firmware(adev->sdma.instance[i].fw);
  78                         adev->sdma.instance[i].fw = NULL;
  79         }
  80 }
  81
  82 /*
  83  * sDMA - System DMA
  84  * Starting with CIK, the GPU has new asynchronous
  85  * DMA engines.  These engines are used for compute
  86  * and gfx.  There are two DMA engines (SDMA0, SDMA1)
  87  * and each one supports 1 ring buffer used for gfx
  88  * and 2 queues used for compute.
  89  *
  90  * The programming model is very similar to the CP
  91  * (ring buffer, IBs, etc.), but sDMA has it's own
  92  * packet format that is different from the PM4 format
  93  * used by the CP. sDMA supports copying data, writing
  94  * embedded data, solid fills, and a number of other
  95  * things.  It also has support for tiling/detiling of
  96  * buffers.
  97  */
  98
  99 /**
 100  * cik_sdma_init_microcode - load ucode images from disk
 101  *
 102  * @adev: amdgpu_device pointer
 103  *
 104  * Use the firmware interface to load the ucode images into
 105  * the driver (not loaded into hw).
 106  * Returns 0 on success, error on failure.
 107  */
 108 static int cik_sdma_init_microcode(struct amdgpu_device *adev)
 109 {
 110         const char *chip_name;
 111         char fw_name[30];
 112         int err = 0, i;
 113
 114         DRM_DEBUG("\n");
 115
 116         switch (adev->asic_type) {
 117         case CHIP_BONAIRE:
 118                 chip_name = "bonaire";
 119                 break;
 120         case CHIP_HAWAII:
 121                 chip_name = "hawaii";
 122                 break;
 123         case CHIP_KAVERI:
 124                 chip_name = "kaveri";
 125                 break;
 126         case CHIP_KABINI:
 127                 chip_name = "kabini";
 128                 break;
 129         case CHIP_MULLINS:
 130                 chip_name = "mullins";
 131                 break;
 132         default: BUG();
 133         }
 134
 135         for (i = 0; i < adev->sdma.num_instances; i++) {
 136                 if (i == 0)
 137                         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sdma.bin", chip_name);
 138                 else
 139                         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sdma1.bin", chip_name);
 140                 err = request_firmware(&adev->sdma.instance[i].fw, fw_name, adev->dev);
 141                 if (err)
 142                         goto out;
 143                 err = amdgpu_ucode_validate(adev->sdma.instance[i].fw);
 144         }
 145 out:
 146         if (err) {
 147                 pr_err("cik_sdma: Failed to load firmware \"%s\"\n", fw_name);
 148                 for (i = 0; i < adev->sdma.num_instances; i++) {
 149                         release_firmware(adev->sdma.instance[i].fw);
 150                         adev->sdma.instance[i].fw = NULL;
 151                 }
 152         }
 153         return err;
 154 }
 155
 156 /**
 157  * cik_sdma_ring_get_rptr - get the current read pointer
 158  *
 159  * @ring: amdgpu ring pointer
 160  *
 161  * Get the current rptr from the hardware (CIK+).
 162  */
 163 static uint64_t cik_sdma_ring_get_rptr(struct amdgpu_ring *ring)
 164 {
 165         u32 rptr;
 166
 167         rptr = *ring->rptr_cpu_addr;
 168
 169         return (rptr & 0x3fffc) >> 2;
 170 }
 171
 172 /**
 173  * cik_sdma_ring_get_wptr - get the current write pointer
 174  *
 175  * @ring: amdgpu ring pointer
 176  *
 177  * Get the current wptr from the hardware (CIK+).
 178  */
 179 static uint64_t cik_sdma_ring_get_wptr(struct amdgpu_ring *ring)
 180 {
 181         struct amdgpu_device *adev = ring->adev;
 182
 183         return (RREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[ring->me]) & 0x3fffc) >> 2;
 184 }
 185
 186 /**
 187  * cik_sdma_ring_set_wptr - commit the write pointer
 188  *
 189  * @ring: amdgpu ring pointer
 190  *
 191  * Write the wptr back to the hardware (CIK+).
 192  */
 193 static void cik_sdma_ring_set_wptr(struct amdgpu_ring *ring)
 194 {
 195         struct amdgpu_device *adev = ring->adev;
 196
 197         WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[ring->me],
 198                (ring->wptr << 2) & 0x3fffc);
 199 }
 200
 201 static void cik_sdma_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count)
 202 {
 203         struct amdgpu_sdma_instance *sdma = amdgpu_sdma_get_instance_from_ring(ring);
 204         int i;
 205
 206         for (i = 0; i < count; i++)
 207                 if (sdma && sdma->burst_nop && (i == 0))
 208                         amdgpu_ring_write(ring, ring->funcs->nop |
 209                                           SDMA_NOP_COUNT(count - 1));
 210                 else
 211                         amdgpu_ring_write(ring, ring->funcs->nop);
 212 }
 213
 214 /**
 215  * cik_sdma_ring_emit_ib - Schedule an IB on the DMA engine
 216  *
 217  * @ring: amdgpu ring pointer
 218  * @job: job to retrive vmid from
 219  * @ib: IB object to schedule
 220  * @flags: unused
 221  *
 222  * Schedule an IB in the DMA ring (CIK).
 223  */
 224 static void cik_sdma_ring_emit_ib(struct amdgpu_ring *ring,
 225                                   struct amdgpu_job *job,
 226                                   struct amdgpu_ib *ib,
 227                                   uint32_t flags)
 228 {
 229         unsigned vmid = AMDGPU_JOB_GET_VMID(job);
 230         u32 extra_bits = vmid & 0xf;
 231
 232         /* IB packet must end on a 8 DW boundary */
 233         cik_sdma_ring_insert_nop(ring, (4 - lower_32_bits(ring->wptr)) & 7);
 234
 235         amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_INDIRECT_BUFFER, 0, extra_bits));
 236         amdgpu_ring_write(ring, ib->gpu_addr & 0xffffffe0); /* base must be 32 byte aligned */
 237         amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xffffffff);
 238         amdgpu_ring_write(ring, ib->length_dw);
 239
 240 }
 241
 242 /**
 243  * cik_sdma_ring_emit_hdp_flush - emit an hdp flush on the DMA ring
 244  *
 245  * @ring: amdgpu ring pointer
 246  *
 247  * Emit an hdp flush packet on the requested DMA ring.
 248  */
 249 static void cik_sdma_ring_emit_hdp_flush(struct amdgpu_ring *ring)
 250 {
 251         u32 extra_bits = (SDMA_POLL_REG_MEM_EXTRA_OP(1) |
 252                           SDMA_POLL_REG_MEM_EXTRA_FUNC(3)); /* == */
 253         u32 ref_and_mask;
 254
 255         if (ring->me == 0)
 256                 ref_and_mask = GPU_HDP_FLUSH_DONE__SDMA0_MASK;
 257         else
 258                 ref_and_mask = GPU_HDP_FLUSH_DONE__SDMA1_MASK;
 259
 260         amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_POLL_REG_MEM, 0, extra_bits));
 261         amdgpu_ring_write(ring, mmGPU_HDP_FLUSH_DONE << 2);
 262         amdgpu_ring_write(ring, mmGPU_HDP_FLUSH_REQ << 2);
 263         amdgpu_ring_write(ring, ref_and_mask); /* reference */
 264         amdgpu_ring_write(ring, ref_and_mask); /* mask */
 265         amdgpu_ring_write(ring, (0xfff << 16) | 10); /* retry count, poll interval */
 266 }
 267
 268 /**
 269  * cik_sdma_ring_emit_fence - emit a fence on the DMA ring
 270  *
 271  * @ring: amdgpu ring pointer
 272  * @addr: address
 273  * @seq: sequence number
 274  * @flags: fence related flags
 275  *
 276  * Add a DMA fence packet to the ring to write
 277  * the fence seq number and DMA trap packet to generate
 278  * an interrupt if needed (CIK).
 279  */
 280 static void cik_sdma_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq,
 281                                      unsigned flags)
 282 {
 283         bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT;
 284         /* write the fence */
 285         amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_FENCE, 0, 0));
 286         amdgpu_ring_write(ring, lower_32_bits(addr));
 287         amdgpu_ring_write(ring, upper_32_bits(addr));
 288         amdgpu_ring_write(ring, lower_32_bits(seq));
 289
 290         /* optionally write high bits as well */
 291         if (write64bit) {
 292                 addr += 4;
 293                 amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_FENCE, 0, 0));
 294                 amdgpu_ring_write(ring, lower_32_bits(addr));
 295                 amdgpu_ring_write(ring, upper_32_bits(addr));
 296                 amdgpu_ring_write(ring, upper_32_bits(seq));
 297         }
 298
 299         /* generate an interrupt */
 300         amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_TRAP, 0, 0));
 301 }
 302
 303 /**
 304  * cik_sdma_gfx_stop - stop the gfx async dma engines
 305  *
 306  * @adev: amdgpu_device pointer
 307  *
 308  * Stop the gfx async dma ring buffers (CIK).
 309  */
 310 static void cik_sdma_gfx_stop(struct amdgpu_device *adev)
 311 {
 312         struct amdgpu_ring *sdma0 = &adev->sdma.instance[0].ring;
 313         struct amdgpu_ring *sdma1 = &adev->sdma.instance[1].ring;
 314         u32 rb_cntl;
 315         int i;
 316
 317         if ((adev->mman.buffer_funcs_ring == sdma0) ||
 318             (adev->mman.buffer_funcs_ring == sdma1))
 319                         amdgpu_ttm_set_buffer_funcs_status(adev, false);
 320
 321         for (i = 0; i < adev->sdma.num_instances; i++) {
 322                 rb_cntl = RREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i]);
 323                 rb_cntl &= ~SDMA0_GFX_RB_CNTL__RB_ENABLE_MASK;
 324                 WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], rb_cntl);
 325                 WREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i], 0);
 326         }
 327 }
 328
 329 /**
 330  * cik_sdma_rlc_stop - stop the compute async dma engines
 331  *
 332  * @adev: amdgpu_device pointer
 333  *
 334  * Stop the compute async dma queues (CIK).
 335  */
 336 static void cik_sdma_rlc_stop(struct amdgpu_device *adev)
 337 {
 338         /* XXX todo */
 339 }
 340
 341 /**
 342  * cik_ctx_switch_enable - stop the async dma engines context switch
 343  *
 344  * @adev: amdgpu_device pointer
 345  * @enable: enable/disable the DMA MEs context switch.
 346  *
 347  * Halt or unhalt the async dma engines context switch (VI).
 348  */
 349 static void cik_ctx_switch_enable(struct amdgpu_device *adev, bool enable)
 350 {
 351         u32 f32_cntl, phase_quantum = 0;
 352         int i;
 353
 354         if (amdgpu_sdma_phase_quantum) {
 355                 unsigned value = amdgpu_sdma_phase_quantum;
 356                 unsigned unit = 0;
 357
 358                 while (value > (SDMA0_PHASE0_QUANTUM__VALUE_MASK >>
 359                                 SDMA0_PHASE0_QUANTUM__VALUE__SHIFT)) {
 360                         value = (value + 1) >> 1;
 361                         unit++;
 362                 }
 363                 if (unit > (SDMA0_PHASE0_QUANTUM__UNIT_MASK >>
 364                             SDMA0_PHASE0_QUANTUM__UNIT__SHIFT)) {
 365                         value = (SDMA0_PHASE0_QUANTUM__VALUE_MASK >>
 366                                  SDMA0_PHASE0_QUANTUM__VALUE__SHIFT);
 367                         unit = (SDMA0_PHASE0_QUANTUM__UNIT_MASK >>
 368                                 SDMA0_PHASE0_QUANTUM__UNIT__SHIFT);
 369                         WARN_ONCE(1,
 370                         "clamping sdma_phase_quantum to %uK clock cycles\n",
 371                                   value << unit);
 372                 }
 373                 phase_quantum =
 374                         value << SDMA0_PHASE0_QUANTUM__VALUE__SHIFT |
 375                         unit  << SDMA0_PHASE0_QUANTUM__UNIT__SHIFT;
 376         }
 377
 378         for (i = 0; i < adev->sdma.num_instances; i++) {
 379                 f32_cntl = RREG32(mmSDMA0_CNTL + sdma_offsets[i]);
 380                 if (enable) {
 381                         f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL,
 382                                         AUTO_CTXSW_ENABLE, 1);
 383                         if (amdgpu_sdma_phase_quantum) {
 384                                 WREG32(mmSDMA0_PHASE0_QUANTUM + sdma_offsets[i],
 385                                        phase_quantum);
 386                                 WREG32(mmSDMA0_PHASE1_QUANTUM + sdma_offsets[i],
 387                                        phase_quantum);
 388                         }
 389                 } else {
 390                         f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL,
 391                                         AUTO_CTXSW_ENABLE, 0);
 392                 }
 393
 394                 WREG32(mmSDMA0_CNTL + sdma_offsets[i], f32_cntl);
 395         }
 396 }
 397
 398 /**
 399  * cik_sdma_enable - stop the async dma engines
 400  *
 401  * @adev: amdgpu_device pointer
 402  * @enable: enable/disable the DMA MEs.
 403  *
 404  * Halt or unhalt the async dma engines (CIK).
 405  */
 406 static void cik_sdma_enable(struct amdgpu_device *adev, bool enable)
 407 {
 408         u32 me_cntl;
 409         int i;
 410
 411         if (!enable) {
 412                 cik_sdma_gfx_stop(adev);
 413                 cik_sdma_rlc_stop(adev);
 414         }
 415
 416         for (i = 0; i < adev->sdma.num_instances; i++) {
 417                 me_cntl = RREG32(mmSDMA0_F32_CNTL + sdma_offsets[i]);
 418                 if (enable)
 419                         me_cntl &= ~SDMA0_F32_CNTL__HALT_MASK;
 420                 else
 421                         me_cntl |= SDMA0_F32_CNTL__HALT_MASK;
 422                 WREG32(mmSDMA0_F32_CNTL + sdma_offsets[i], me_cntl);
 423         }
 424 }
 425
 426 /**
 427  * cik_sdma_gfx_resume - setup and start the async dma engines
 428  *
 429  * @adev: amdgpu_device pointer
 430  *
 431  * Set up the gfx DMA ring buffers and enable them (CIK).
 432  * Returns 0 for success, error for failure.
 433  */
 434 static int cik_sdma_gfx_resume(struct amdgpu_device *adev)
 435 {
 436         struct amdgpu_ring *ring;
 437         u32 rb_cntl, ib_cntl;
 438         u32 rb_bufsz;
 439         int i, j, r;
 440
 441         for (i = 0; i < adev->sdma.num_instances; i++) {
 442                 ring = &adev->sdma.instance[i].ring;
 443
 444                 mutex_lock(&adev->srbm_mutex);
 445                 for (j = 0; j < 16; j++) {
 446                         cik_srbm_select(adev, 0, 0, 0, j);
 447                         /* SDMA GFX */
 448                         WREG32(mmSDMA0_GFX_VIRTUAL_ADDR + sdma_offsets[i], 0);
 449                         WREG32(mmSDMA0_GFX_APE1_CNTL + sdma_offsets[i], 0);
 450                         /* XXX SDMA RLC - todo */
 451                 }
 452                 cik_srbm_select(adev, 0, 0, 0, 0);
 453                 mutex_unlock(&adev->srbm_mutex);
 454
 455                 WREG32(mmSDMA0_TILING_CONFIG + sdma_offsets[i],
 456                        adev->gfx.config.gb_addr_config & 0x70);
 457
 458                 WREG32(mmSDMA0_SEM_INCOMPLETE_TIMER_CNTL + sdma_offsets[i], 0);
 459                 WREG32(mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL + sdma_offsets[i], 0);
 460
 461                 /* Set ring buffer size in dwords */
 462                 rb_bufsz = order_base_2(ring->ring_size / 4);
 463                 rb_cntl = rb_bufsz << 1;
 464 #ifdef __BIG_ENDIAN
 465                 rb_cntl |= SDMA0_GFX_RB_CNTL__RB_SWAP_ENABLE_MASK |
 466                         SDMA0_GFX_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK;
 467 #endif
 468                 WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], rb_cntl);
 469
 470                 /* Initialize the ring buffer's read and write pointers */
 471                 WREG32(mmSDMA0_GFX_RB_RPTR + sdma_offsets[i], 0);
 472                 WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[i], 0);
 473                 WREG32(mmSDMA0_GFX_IB_RPTR + sdma_offsets[i], 0);
 474                 WREG32(mmSDMA0_GFX_IB_OFFSET + sdma_offsets[i], 0);
 475
 476                 /* set the wb address whether it's enabled or not */
 477                 WREG32(mmSDMA0_GFX_RB_RPTR_ADDR_HI + sdma_offsets[i],
 478                        upper_32_bits(ring->rptr_gpu_addr) & 0xFFFFFFFF);
 479                 WREG32(mmSDMA0_GFX_RB_RPTR_ADDR_LO + sdma_offsets[i],
 480                        ((ring->rptr_gpu_addr) & 0xFFFFFFFC));
 481
 482                 rb_cntl |= SDMA0_GFX_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK;
 483
 484                 WREG32(mmSDMA0_GFX_RB_BASE + sdma_offsets[i], ring->gpu_addr >> 8);
 485                 WREG32(mmSDMA0_GFX_RB_BASE_HI + sdma_offsets[i], ring->gpu_addr >> 40);
 486
 487                 ring->wptr = 0;
 488                 WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[i], ring->wptr << 2);
 489
 490                 /* enable DMA RB */
 491                 WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i],
 492                        rb_cntl | SDMA0_GFX_RB_CNTL__RB_ENABLE_MASK);
 493
 494                 ib_cntl = SDMA0_GFX_IB_CNTL__IB_ENABLE_MASK;
 495 #ifdef __BIG_ENDIAN
 496                 ib_cntl |= SDMA0_GFX_IB_CNTL__IB_SWAP_ENABLE_MASK;
 497 #endif
 498                 /* enable DMA IBs */
 499                 WREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i], ib_cntl);
 500
 501                 ring->sched.ready = true;
 502         }
 503
 504         cik_sdma_enable(adev, true);
 505
 506         for (i = 0; i < adev->sdma.num_instances; i++) {
 507                 ring = &adev->sdma.instance[i].ring;
 508                 r = amdgpu_ring_test_helper(ring);
 509                 if (r)
 510                         return r;
 511
 512                 if (adev->mman.buffer_funcs_ring == ring)
 513                         amdgpu_ttm_set_buffer_funcs_status(adev, true);
 514         }
 515
 516         return 0;
 517 }
 518
 519 /**
 520  * cik_sdma_rlc_resume - setup and start the async dma engines
 521  *
 522  * @adev: amdgpu_device pointer
 523  *
 524  * Set up the compute DMA queues and enable them (CIK).
 525  * Returns 0 for success, error for failure.
 526  */
 527 static int cik_sdma_rlc_resume(struct amdgpu_device *adev)
 528 {
 529         /* XXX todo */
 530         return 0;
 531 }
 532
 533 /**
 534  * cik_sdma_load_microcode - load the sDMA ME ucode
 535  *
 536  * @adev: amdgpu_device pointer
 537  *
 538  * Loads the sDMA0/1 ucode.
 539  * Returns 0 for success, -EINVAL if the ucode is not available.
 540  */
 541 static int cik_sdma_load_microcode(struct amdgpu_device *adev)
 542 {
 543         const struct sdma_firmware_header_v1_0 *hdr;
 544         const __le32 *fw_data;
 545         u32 fw_size;
 546         int i, j;
 547
 548         /* halt the MEs */
 549         cik_sdma_enable(adev, false);
 550
 551         for (i = 0; i < adev->sdma.num_instances; i++) {
 552                 if (!adev->sdma.instance[i].fw)
 553                         return -EINVAL;
 554                 hdr = (const struct sdma_firmware_header_v1_0 *)adev->sdma.instance[i].fw->data;
 555                 amdgpu_ucode_print_sdma_hdr(&hdr->header);
 556                 fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
 557                 adev->sdma.instance[i].fw_version = le32_to_cpu(hdr->header.ucode_version);
 558                 adev->sdma.instance[i].feature_version = le32_to_cpu(hdr->ucode_feature_version);
 559                 if (adev->sdma.instance[i].feature_version >= 20)
 560                         adev->sdma.instance[i].burst_nop = true;
 561                 fw_data = (const __le32 *)
 562                         (adev->sdma.instance[i].fw->data + le32_to_cpu(hdr->header.ucode_array_offset_bytes));
 563                 WREG32(mmSDMA0_UCODE_ADDR + sdma_offsets[i], 0);
 564                 for (j = 0; j < fw_size; j++)
 565                         WREG32(mmSDMA0_UCODE_DATA + sdma_offsets[i], le32_to_cpup(fw_data++));
 566                 WREG32(mmSDMA0_UCODE_ADDR + sdma_offsets[i], adev->sdma.instance[i].fw_version);
 567         }
 568
 569         return 0;
 570 }
 571
 572 /**
 573  * cik_sdma_start - setup and start the async dma engines
 574  *
 575  * @adev: amdgpu_device pointer
 576  *
 577  * Set up the DMA engines and enable them (CIK).
 578  * Returns 0 for success, error for failure.
 579  */
 580 static int cik_sdma_start(struct amdgpu_device *adev)
 581 {
 582         int r;
 583
 584         r = cik_sdma_load_microcode(adev);
 585         if (r)
 586                 return r;
 587
 588         /* halt the engine before programing */
 589         cik_sdma_enable(adev, false);
 590         /* enable sdma ring preemption */
 591         cik_ctx_switch_enable(adev, true);
 592
 593         /* start the gfx rings and rlc compute queues */
 594         r = cik_sdma_gfx_resume(adev);
 595         if (r)
 596                 return r;
 597         r = cik_sdma_rlc_resume(adev);
 598         if (r)
 599                 return r;
 600
 601         return 0;
 602 }
 603
 604 /**
 605  * cik_sdma_ring_test_ring - simple async dma engine test
 606  *
 607  * @ring: amdgpu_ring structure holding ring information
 608  *
 609  * Test the DMA engine by writing using it to write an
 610  * value to memory. (CIK).
 611  * Returns 0 for success, error for failure.
 612  */
 613 static int cik_sdma_ring_test_ring(struct amdgpu_ring *ring)
 614 {
 615         struct amdgpu_device *adev = ring->adev;
 616         unsigned i;
 617         unsigned index;
 618         int r;
 619         u32 tmp;
 620         u64 gpu_addr;
 621
 622         r = amdgpu_device_wb_get(adev, &index);
 623         if (r)
 624                 return r;
 625
 626         gpu_addr = adev->wb.gpu_addr + (index * 4);
 627         tmp = 0xCAFEDEAD;
 628         adev->wb.wb[index] = cpu_to_le32(tmp);
 629
 630         r = amdgpu_ring_alloc(ring, 5);
 631         if (r)
 632                 goto error_free_wb;
 633
 634         amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_WRITE, SDMA_WRITE_SUB_OPCODE_LINEAR, 0));
 635         amdgpu_ring_write(ring, lower_32_bits(gpu_addr));
 636         amdgpu_ring_write(ring, upper_32_bits(gpu_addr));
 637         amdgpu_ring_write(ring, 1); /* number of DWs to follow */
 638         amdgpu_ring_write(ring, 0xDEADBEEF);
 639         amdgpu_ring_commit(ring);
 640
 641         for (i = 0; i < adev->usec_timeout; i++) {
 642                 tmp = le32_to_cpu(adev->wb.wb[index]);
 643                 if (tmp == 0xDEADBEEF)
 644                         break;
 645                 udelay(1);
 646         }
 647
 648         if (i >= adev->usec_timeout)
 649                 r = -ETIMEDOUT;
 650
 651 error_free_wb:
 652         amdgpu_device_wb_free(adev, index);
 653         return r;
 654 }
 655
 656 /**
 657  * cik_sdma_ring_test_ib - test an IB on the DMA engine
 658  *
 659  * @ring: amdgpu_ring structure holding ring information
 660  * @timeout: timeout value in jiffies, or MAX_SCHEDULE_TIMEOUT
 661  *
 662  * Test a simple IB in the DMA ring (CIK).
 663  * Returns 0 on success, error on failure.
 664  */
 665 static int cik_sdma_ring_test_ib(struct amdgpu_ring *ring, long timeout)
 666 {
 667         struct amdgpu_device *adev = ring->adev;
 668         struct amdgpu_ib ib;
 669         struct dma_fence *f = NULL;
 670         unsigned index;
 671         u32 tmp = 0;
 672         u64 gpu_addr;
 673         long r;
 674
 675         r = amdgpu_device_wb_get(adev, &index);
 676         if (r)
 677                 return r;
 678
 679         gpu_addr = adev->wb.gpu_addr + (index * 4);
 680         tmp = 0xCAFEDEAD;
 681         adev->wb.wb[index] = cpu_to_le32(tmp);
 682         memset(&ib, 0, sizeof(ib));
 683         r = amdgpu_ib_get(adev, NULL, 256,
 684                                         AMDGPU_IB_POOL_DIRECT, &ib);
 685         if (r)
 686                 goto err0;
 687
 688         ib.ptr[0] = SDMA_PACKET(SDMA_OPCODE_WRITE,
 689                                 SDMA_WRITE_SUB_OPCODE_LINEAR, 0);
 690         ib.ptr[1] = lower_32_bits(gpu_addr);
 691         ib.ptr[2] = upper_32_bits(gpu_addr);
 692         ib.ptr[3] = 1;
 693         ib.ptr[4] = 0xDEADBEEF;
 694         ib.length_dw = 5;
 695         r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f);
 696         if (r)
 697                 goto err1;
 698
 699         r = dma_fence_wait_timeout(f, false, timeout);
 700         if (r == 0) {
 701                 r = -ETIMEDOUT;
 702                 goto err1;
 703         } else if (r < 0) {
 704                 goto err1;
 705         }
 706         tmp = le32_to_cpu(adev->wb.wb[index]);
 707         if (tmp == 0xDEADBEEF)
 708                 r = 0;
 709         else
 710                 r = -EINVAL;
 711
 712 err1:
 713         amdgpu_ib_free(adev, &ib, NULL);
 714         dma_fence_put(f);
 715 err0:
 716         amdgpu_device_wb_free(adev, index);
 717         return r;
 718 }
 719
 720 /**
 721  * cik_sdma_vm_copy_pte - update PTEs by copying them from the GART
 722  *
 723  * @ib: indirect buffer to fill with commands
 724  * @pe: addr of the page entry
 725  * @src: src addr to copy from
 726  * @count: number of page entries to update
 727  *
 728  * Update PTEs by copying them from the GART using sDMA (CIK).
 729  */
 730 static void cik_sdma_vm_copy_pte(struct amdgpu_ib *ib,
 731                                  uint64_t pe, uint64_t src,
 732                                  unsigned count)
 733 {
 734         unsigned bytes = count * 8;
 735
 736         ib->ptr[ib->length_dw++] = SDMA_PACKET(SDMA_OPCODE_COPY,
 737                 SDMA_WRITE_SUB_OPCODE_LINEAR, 0);
 738         ib->ptr[ib->length_dw++] = bytes;
 739         ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */
 740         ib->ptr[ib->length_dw++] = lower_32_bits(src);
 741         ib->ptr[ib->length_dw++] = upper_32_bits(src);
 742         ib->ptr[ib->length_dw++] = lower_32_bits(pe);
 743         ib->ptr[ib->length_dw++] = upper_32_bits(pe);
 744 }
 745
 746 /**
 747  * cik_sdma_vm_write_pte - update PTEs by writing them manually
 748  *
 749  * @ib: indirect buffer to fill with commands
 750  * @pe: addr of the page entry
 751  * @value: dst addr to write into pe
 752  * @count: number of page entries to update
 753  * @incr: increase next addr by incr bytes
 754  *
 755  * Update PTEs by writing them manually using sDMA (CIK).
 756  */
 757 static void cik_sdma_vm_write_pte(struct amdgpu_ib *ib, uint64_t pe,
 758                                   uint64_t value, unsigned count,
 759                                   uint32_t incr)
 760 {
 761         unsigned ndw = count * 2;
 762
 763         ib->ptr[ib->length_dw++] = SDMA_PACKET(SDMA_OPCODE_WRITE,
 764                 SDMA_WRITE_SUB_OPCODE_LINEAR, 0);
 765         ib->ptr[ib->length_dw++] = lower_32_bits(pe);
 766         ib->ptr[ib->length_dw++] = upper_32_bits(pe);
 767         ib->ptr[ib->length_dw++] = ndw;
 768         for (; ndw > 0; ndw -= 2) {
 769                 ib->ptr[ib->length_dw++] = lower_32_bits(value);
 770                 ib->ptr[ib->length_dw++] = upper_32_bits(value);
 771                 value += incr;
 772         }
 773 }
 774
 775 /**
 776  * cik_sdma_vm_set_pte_pde - update the page tables using sDMA
 777  *
 778  * @ib: indirect buffer to fill with commands
 779  * @pe: addr of the page entry
 780  * @addr: dst addr to write into pe
 781  * @count: number of page entries to update
 782  * @incr: increase next addr by incr bytes
 783  * @flags: access flags
 784  *
 785  * Update the page tables using sDMA (CIK).
 786  */
 787 static void cik_sdma_vm_set_pte_pde(struct amdgpu_ib *ib, uint64_t pe,
 788                                     uint64_t addr, unsigned count,
 789                                     uint32_t incr, uint64_t flags)
 790 {
 791         /* for physically contiguous pages (vram) */
 792         ib->ptr[ib->length_dw++] = SDMA_PACKET(SDMA_OPCODE_GENERATE_PTE_PDE, 0, 0);
 793         ib->ptr[ib->length_dw++] = lower_32_bits(pe); /* dst addr */
 794         ib->ptr[ib->length_dw++] = upper_32_bits(pe);
 795         ib->ptr[ib->length_dw++] = lower_32_bits(flags); /* mask */
 796         ib->ptr[ib->length_dw++] = upper_32_bits(flags);
 797         ib->ptr[ib->length_dw++] = lower_32_bits(addr); /* value */
 798         ib->ptr[ib->length_dw++] = upper_32_bits(addr);
 799         ib->ptr[ib->length_dw++] = incr; /* increment size */
 800         ib->ptr[ib->length_dw++] = 0;
 801         ib->ptr[ib->length_dw++] = count; /* number of entries */
 802 }
 803
 804 /**
 805  * cik_sdma_ring_pad_ib - pad the IB to the required number of dw
 806  *
 807  * @ring: amdgpu_ring structure holding ring information
 808  * @ib: indirect buffer to fill with padding
 809  *
 810  */
 811 static void cik_sdma_ring_pad_ib(struct amdgpu_ring *ring, struct amdgpu_ib *ib)
 812 {
 813         struct amdgpu_sdma_instance *sdma = amdgpu_sdma_get_instance_from_ring(ring);
 814         u32 pad_count;
 815         int i;
 816
 817         pad_count = (-ib->length_dw) & 7;
 818         for (i = 0; i < pad_count; i++)
 819                 if (sdma && sdma->burst_nop && (i == 0))
 820                         ib->ptr[ib->length_dw++] =
 821                                         SDMA_PACKET(SDMA_OPCODE_NOP, 0, 0) |
 822                                         SDMA_NOP_COUNT(pad_count - 1);
 823                 else
 824                         ib->ptr[ib->length_dw++] =
 825                                         SDMA_PACKET(SDMA_OPCODE_NOP, 0, 0);
 826 }
 827
 828 /**
 829  * cik_sdma_ring_emit_pipeline_sync - sync the pipeline
 830  *
 831  * @ring: amdgpu_ring pointer
 832  *
 833  * Make sure all previous operations are completed (CIK).
 834  */
 835 static void cik_sdma_ring_emit_pipeline_sync(struct amdgpu_ring *ring)
 836 {
 837         uint32_t seq = ring->fence_drv.sync_seq;
 838         uint64_t addr = ring->fence_drv.gpu_addr;
 839
 840         /* wait for idle */
 841         amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_POLL_REG_MEM, 0,
 842                                             SDMA_POLL_REG_MEM_EXTRA_OP(0) |
 843                                             SDMA_POLL_REG_MEM_EXTRA_FUNC(3) | /* equal */
 844                                             SDMA_POLL_REG_MEM_EXTRA_M));
 845         amdgpu_ring_write(ring, addr & 0xfffffffc);
 846         amdgpu_ring_write(ring, upper_32_bits(addr) & 0xffffffff);
 847         amdgpu_ring_write(ring, seq); /* reference */
 848         amdgpu_ring_write(ring, 0xffffffff); /* mask */
 849         amdgpu_ring_write(ring, (0xfff << 16) | 4); /* retry count, poll interval */
 850 }
 851
 852 /**
 853  * cik_sdma_ring_emit_vm_flush - cik vm flush using sDMA
 854  *
 855  * @ring: amdgpu_ring pointer
 856  * @vmid: vmid number to use
 857  * @pd_addr: address
 858  *
 859  * Update the page table base and flush the VM TLB
 860  * using sDMA (CIK).
 861  */
 862 static void cik_sdma_ring_emit_vm_flush(struct amdgpu_ring *ring,
 863                                         unsigned vmid, uint64_t pd_addr)
 864 {
 865         u32 extra_bits = (SDMA_POLL_REG_MEM_EXTRA_OP(0) |
 866                           SDMA_POLL_REG_MEM_EXTRA_FUNC(0)); /* always */
 867
 868         amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr);
 869
 870         amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_POLL_REG_MEM, 0, extra_bits));
 871         amdgpu_ring_write(ring, mmVM_INVALIDATE_REQUEST << 2);
 872         amdgpu_ring_write(ring, 0);
 873         amdgpu_ring_write(ring, 0); /* reference */
 874         amdgpu_ring_write(ring, 0); /* mask */
 875         amdgpu_ring_write(ring, (0xfff << 16) | 10); /* retry count, poll interval */
 876 }
 877
 878 static void cik_sdma_ring_emit_wreg(struct amdgpu_ring *ring,
 879                                     uint32_t reg, uint32_t val)
 880 {
 881         amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_SRBM_WRITE, 0, 0xf000));
 882         amdgpu_ring_write(ring, reg);
 883         amdgpu_ring_write(ring, val);
 884 }
 885
 886 static void cik_enable_sdma_mgcg(struct amdgpu_device *adev,
 887                                  bool enable)
 888 {
 889         u32 orig, data;
 890
 891         if (enable && (adev->cg_flags & AMD_CG_SUPPORT_SDMA_MGCG)) {
 892                 WREG32(mmSDMA0_CLK_CTRL + SDMA0_REGISTER_OFFSET, 0x00000100);
 893                 WREG32(mmSDMA0_CLK_CTRL + SDMA1_REGISTER_OFFSET, 0x00000100);
 894         } else {
 895                 orig = data = RREG32(mmSDMA0_CLK_CTRL + SDMA0_REGISTER_OFFSET);
 896                 data |= 0xff000000;
 897                 if (data != orig)
 898                         WREG32(mmSDMA0_CLK_CTRL + SDMA0_REGISTER_OFFSET, data);
 899
 900                 orig = data = RREG32(mmSDMA0_CLK_CTRL + SDMA1_REGISTER_OFFSET);
 901                 data |= 0xff000000;
 902                 if (data != orig)
 903                         WREG32(mmSDMA0_CLK_CTRL + SDMA1_REGISTER_OFFSET, data);
 904         }
 905 }
 906
 907 static void cik_enable_sdma_mgls(struct amdgpu_device *adev,
 908                                  bool enable)
 909 {
 910         u32 orig, data;
 911
 912         if (enable && (adev->cg_flags & AMD_CG_SUPPORT_SDMA_LS)) {
 913                 orig = data = RREG32(mmSDMA0_POWER_CNTL + SDMA0_REGISTER_OFFSET);
 914                 data |= 0x100;
 915                 if (orig != data)
 916                         WREG32(mmSDMA0_POWER_CNTL + SDMA0_REGISTER_OFFSET, data);
 917
 918                 orig = data = RREG32(mmSDMA0_POWER_CNTL + SDMA1_REGISTER_OFFSET);
 919                 data |= 0x100;
 920                 if (orig != data)
 921                         WREG32(mmSDMA0_POWER_CNTL + SDMA1_REGISTER_OFFSET, data);
 922         } else {
 923                 orig = data = RREG32(mmSDMA0_POWER_CNTL + SDMA0_REGISTER_OFFSET);
 924                 data &= ~0x100;
 925                 if (orig != data)
 926                         WREG32(mmSDMA0_POWER_CNTL + SDMA0_REGISTER_OFFSET, data);
 927
 928                 orig = data = RREG32(mmSDMA0_POWER_CNTL + SDMA1_REGISTER_OFFSET);
 929                 data &= ~0x100;
 930                 if (orig != data)
 931                         WREG32(mmSDMA0_POWER_CNTL + SDMA1_REGISTER_OFFSET, data);
 932         }
 933 }
 934
 935 static int cik_sdma_early_init(void *handle)
 936 {
 937         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 938
 939         adev->sdma.num_instances = SDMA_MAX_INSTANCE;
 940
 941         cik_sdma_set_ring_funcs(adev);
 942         cik_sdma_set_irq_funcs(adev);
 943         cik_sdma_set_buffer_funcs(adev);
 944         cik_sdma_set_vm_pte_funcs(adev);
 945
 946         return 0;
 947 }
 948
 949 static int cik_sdma_sw_init(void *handle)
 950 {
 951         struct amdgpu_ring *ring;
 952         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 953         int r, i;
 954
 955         r = cik_sdma_init_microcode(adev);
 956         if (r) {
 957                 DRM_ERROR("Failed to load sdma firmware!\n");
 958                 return r;
 959         }
 960
 961         /* SDMA trap event */
 962         r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, 224,
 963                               &adev->sdma.trap_irq);
 964         if (r)
 965                 return r;
 966
 967         /* SDMA Privileged inst */
 968         r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, 241,
 969                               &adev->sdma.illegal_inst_irq);
 970         if (r)
 971                 return r;
 972
 973         /* SDMA Privileged inst */
 974         r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, 247,
 975                               &adev->sdma.illegal_inst_irq);
 976         if (r)
 977                 return r;
 978
 979         for (i = 0; i < adev->sdma.num_instances; i++) {
 980                 ring = &adev->sdma.instance[i].ring;
 981                 ring->ring_obj = NULL;
 982                 sprintf(ring->name, "sdma%d", i);
 983                 r = amdgpu_ring_init(adev, ring, 1024,
 984                                      &adev->sdma.trap_irq,
 985                                      (i == 0) ? AMDGPU_SDMA_IRQ_INSTANCE0 :
 986                                      AMDGPU_SDMA_IRQ_INSTANCE1,
 987                                      AMDGPU_RING_PRIO_DEFAULT, NULL);
 988                 if (r)
 989                         return r;
 990         }
 991
 992         return r;
 993 }
 994
 995 static int cik_sdma_sw_fini(void *handle)
 996 {
 997         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 998         int i;
 999
1000         for (i = 0; i < adev->sdma.num_instances; i++)
1001                 amdgpu_ring_fini(&adev->sdma.instance[i].ring);
1002
1003         cik_sdma_free_microcode(adev);
1004         return 0;
1005 }
1006
1007 static int cik_sdma_hw_init(void *handle)
1008 {
1009         int r;
1010         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1011
1012         r = cik_sdma_start(adev);
1013         if (r)
1014                 return r;
1015
1016         return r;
1017 }
1018
1019 static int cik_sdma_hw_fini(void *handle)
1020 {
1021         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1022
1023         cik_ctx_switch_enable(adev, false);
1024         cik_sdma_enable(adev, false);
1025
1026         return 0;
1027 }
1028
1029 static int cik_sdma_suspend(void *handle)
1030 {
1031         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1032
1033         return cik_sdma_hw_fini(adev);
1034 }
1035
1036 static int cik_sdma_resume(void *handle)
1037 {
1038         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1039
1040         cik_sdma_soft_reset(handle);
1041
1042         return cik_sdma_hw_init(adev);
1043 }
1044
1045 static bool cik_sdma_is_idle(void *handle)
1046 {
1047         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1048         u32 tmp = RREG32(mmSRBM_STATUS2);
1049
1050         if (tmp & (SRBM_STATUS2__SDMA_BUSY_MASK |
1051                                 SRBM_STATUS2__SDMA1_BUSY_MASK))
1052             return false;
1053
1054         return true;
1055 }
1056
1057 static int cik_sdma_wait_for_idle(void *handle)
1058 {
1059         unsigned i;
1060         u32 tmp;
1061         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1062
1063         for (i = 0; i < adev->usec_timeout; i++) {
1064                 tmp = RREG32(mmSRBM_STATUS2) & (SRBM_STATUS2__SDMA_BUSY_MASK |
1065                                 SRBM_STATUS2__SDMA1_BUSY_MASK);
1066
1067                 if (!tmp)
1068                         return 0;
1069                 udelay(1);
1070         }
1071         return -ETIMEDOUT;
1072 }
1073
1074 static int cik_sdma_soft_reset(void *handle)
1075 {
1076         u32 srbm_soft_reset = 0;
1077         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1078         u32 tmp;
1079
1080         /* sdma0 */
1081         tmp = RREG32(mmSDMA0_F32_CNTL + SDMA0_REGISTER_OFFSET);
1082         tmp |= SDMA0_F32_CNTL__HALT_MASK;
1083         WREG32(mmSDMA0_F32_CNTL + SDMA0_REGISTER_OFFSET, tmp);
1084         srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_SDMA_MASK;
1085
1086         /* sdma1 */
1087         tmp = RREG32(mmSDMA0_F32_CNTL + SDMA1_REGISTER_OFFSET);
1088         tmp |= SDMA0_F32_CNTL__HALT_MASK;
1089         WREG32(mmSDMA0_F32_CNTL + SDMA1_REGISTER_OFFSET, tmp);
1090         srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_SDMA1_MASK;
1091
1092         if (srbm_soft_reset) {
1093                 tmp = RREG32(mmSRBM_SOFT_RESET);
1094                 tmp |= srbm_soft_reset;
1095                 dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
1096                 WREG32(mmSRBM_SOFT_RESET, tmp);
1097                 tmp = RREG32(mmSRBM_SOFT_RESET);
1098
1099                 udelay(50);
1100
1101                 tmp &= ~srbm_soft_reset;
1102                 WREG32(mmSRBM_SOFT_RESET, tmp);
1103                 tmp = RREG32(mmSRBM_SOFT_RESET);
1104
1105                 /* Wait a little for things to settle down */
1106                 udelay(50);
1107         }
1108
1109         return 0;
1110 }
1111
1112 static int cik_sdma_set_trap_irq_state(struct amdgpu_device *adev,
1113                                        struct amdgpu_irq_src *src,
1114                                        unsigned type,
1115                                        enum amdgpu_interrupt_state state)
1116 {
1117         u32 sdma_cntl;
1118
1119         switch (type) {
1120         case AMDGPU_SDMA_IRQ_INSTANCE0:
1121                 switch (state) {
1122                 case AMDGPU_IRQ_STATE_DISABLE:
1123                         sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET);
1124                         sdma_cntl &= ~SDMA0_CNTL__TRAP_ENABLE_MASK;
1125                         WREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET, sdma_cntl);
1126                         break;
1127                 case AMDGPU_IRQ_STATE_ENABLE:
1128                         sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET);
1129                         sdma_cntl |= SDMA0_CNTL__TRAP_ENABLE_MASK;
1130                         WREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET, sdma_cntl);
1131                         break;
1132                 default:
1133                         break;
1134                 }
1135                 break;
1136         case AMDGPU_SDMA_IRQ_INSTANCE1:
1137                 switch (state) {
1138                 case AMDGPU_IRQ_STATE_DISABLE:
1139                         sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET);
1140                         sdma_cntl &= ~SDMA0_CNTL__TRAP_ENABLE_MASK;
1141                         WREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET, sdma_cntl);
1142                         break;
1143                 case AMDGPU_IRQ_STATE_ENABLE:
1144                         sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET);
1145                         sdma_cntl |= SDMA0_CNTL__TRAP_ENABLE_MASK;
1146                         WREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET, sdma_cntl);
1147                         break;
1148                 default:
1149                         break;
1150                 }
1151                 break;
1152         default:
1153                 break;
1154         }
1155         return 0;
1156 }
1157
1158 static int cik_sdma_process_trap_irq(struct amdgpu_device *adev,
1159                                      struct amdgpu_irq_src *source,
1160                                      struct amdgpu_iv_entry *entry)
1161 {
1162         u8 instance_id, queue_id;
1163
1164         instance_id = (entry->ring_id & 0x3) >> 0;
1165         queue_id = (entry->ring_id & 0xc) >> 2;
1166         DRM_DEBUG("IH: SDMA trap\n");
1167         switch (instance_id) {
1168         case 0:
1169                 switch (queue_id) {
1170                 case 0:
1171                         amdgpu_fence_process(&adev->sdma.instance[0].ring);
1172                         break;
1173                 case 1:
1174                         /* XXX compute */
1175                         break;
1176                 case 2:
1177                         /* XXX compute */
1178                         break;
1179                 }
1180                 break;
1181         case 1:
1182                 switch (queue_id) {
1183                 case 0:
1184                         amdgpu_fence_process(&adev->sdma.instance[1].ring);
1185                         break;
1186                 case 1:
1187                         /* XXX compute */
1188                         break;
1189                 case 2:
1190                         /* XXX compute */
1191                         break;
1192                 }
1193                 break;
1194         }
1195
1196         return 0;
1197 }
1198
1199 static int cik_sdma_process_illegal_inst_irq(struct amdgpu_device *adev,
1200                                              struct amdgpu_irq_src *source,
1201                                              struct amdgpu_iv_entry *entry)
1202 {
1203         u8 instance_id;
1204
1205         DRM_ERROR("Illegal instruction in SDMA command stream\n");
1206         instance_id = (entry->ring_id & 0x3) >> 0;
1207         drm_sched_fault(&adev->sdma.instance[instance_id].ring.sched);
1208         return 0;
1209 }
1210
1211 static int cik_sdma_set_clockgating_state(void *handle,
1212                                           enum amd_clockgating_state state)
1213 {
1214         bool gate = false;
1215         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1216
1217         if (state == AMD_CG_STATE_GATE)
1218                 gate = true;
1219
1220         cik_enable_sdma_mgcg(adev, gate);
1221         cik_enable_sdma_mgls(adev, gate);
1222
1223         return 0;
1224 }
1225
1226 static int cik_sdma_set_powergating_state(void *handle,
1227                                           enum amd_powergating_state state)
1228 {
1229         return 0;
1230 }
1231
1232 static const struct amd_ip_funcs cik_sdma_ip_funcs = {
1233         .name = "cik_sdma",
1234         .early_init = cik_sdma_early_init,
1235         .late_init = NULL,
1236         .sw_init = cik_sdma_sw_init,
1237         .sw_fini = cik_sdma_sw_fini,
1238         .hw_init = cik_sdma_hw_init,
1239         .hw_fini = cik_sdma_hw_fini,
1240         .suspend = cik_sdma_suspend,
1241         .resume = cik_sdma_resume,
1242         .is_idle = cik_sdma_is_idle,
1243         .wait_for_idle = cik_sdma_wait_for_idle,
1244         .soft_reset = cik_sdma_soft_reset,
1245         .set_clockgating_state = cik_sdma_set_clockgating_state,
1246         .set_powergating_state = cik_sdma_set_powergating_state,
1247 };
1248
1249 static const struct amdgpu_ring_funcs cik_sdma_ring_funcs = {
1250         .type = AMDGPU_RING_TYPE_SDMA,
1251         .align_mask = 0xf,
1252         .nop = SDMA_PACKET(SDMA_OPCODE_NOP, 0, 0),
1253         .support_64bit_ptrs = false,
1254         .get_rptr = cik_sdma_ring_get_rptr,
1255         .get_wptr = cik_sdma_ring_get_wptr,
1256         .set_wptr = cik_sdma_ring_set_wptr,
1257         .emit_frame_size =
1258                 6 + /* cik_sdma_ring_emit_hdp_flush */
1259                 3 + /* hdp invalidate */
1260                 6 + /* cik_sdma_ring_emit_pipeline_sync */
1261                 CIK_FLUSH_GPU_TLB_NUM_WREG * 3 + 6 + /* cik_sdma_ring_emit_vm_flush */
1262                 9 + 9 + 9, /* cik_sdma_ring_emit_fence x3 for user fence, vm fence */
1263         .emit_ib_size = 7 + 4, /* cik_sdma_ring_emit_ib */
1264         .emit_ib = cik_sdma_ring_emit_ib,
1265         .emit_fence = cik_sdma_ring_emit_fence,
1266         .emit_pipeline_sync = cik_sdma_ring_emit_pipeline_sync,
1267         .emit_vm_flush = cik_sdma_ring_emit_vm_flush,
1268         .emit_hdp_flush = cik_sdma_ring_emit_hdp_flush,
1269         .test_ring = cik_sdma_ring_test_ring,
1270         .test_ib = cik_sdma_ring_test_ib,
1271         .insert_nop = cik_sdma_ring_insert_nop,
1272         .pad_ib = cik_sdma_ring_pad_ib,
1273         .emit_wreg = cik_sdma_ring_emit_wreg,
1274 };
1275
1276 static void cik_sdma_set_ring_funcs(struct amdgpu_device *adev)
1277 {
1278         int i;
1279
1280         for (i = 0; i < adev->sdma.num_instances; i++) {
1281                 adev->sdma.instance[i].ring.funcs = &cik_sdma_ring_funcs;
1282                 adev->sdma.instance[i].ring.me = i;
1283         }
1284 }
1285
1286 static const struct amdgpu_irq_src_funcs cik_sdma_trap_irq_funcs = {
1287         .set = cik_sdma_set_trap_irq_state,
1288         .process = cik_sdma_process_trap_irq,
1289 };
1290
1291 static const struct amdgpu_irq_src_funcs cik_sdma_illegal_inst_irq_funcs = {
1292         .process = cik_sdma_process_illegal_inst_irq,
1293 };
1294
1295 static void cik_sdma_set_irq_funcs(struct amdgpu_device *adev)
1296 {
1297         adev->sdma.trap_irq.num_types = AMDGPU_SDMA_IRQ_LAST;
1298         adev->sdma.trap_irq.funcs = &cik_sdma_trap_irq_funcs;
1299         adev->sdma.illegal_inst_irq.funcs = &cik_sdma_illegal_inst_irq_funcs;
1300 }
1301
1302 /**
1303  * cik_sdma_emit_copy_buffer - copy buffer using the sDMA engine
1304  *
1305  * @ib: indirect buffer to copy to
1306  * @src_offset: src GPU address
1307  * @dst_offset: dst GPU address
1308  * @byte_count: number of bytes to xfer
1309  * @tmz: is this a secure operation
1310  *
1311  * Copy GPU buffers using the DMA engine (CIK).
1312  * Used by the amdgpu ttm implementation to move pages if
1313  * registered as the asic copy callback.
1314  */
1315 static void cik_sdma_emit_copy_buffer(struct amdgpu_ib *ib,
1316                                       uint64_t src_offset,
1317                                       uint64_t dst_offset,
1318                                       uint32_t byte_count,
1319                                       bool tmz)
1320 {
1321         ib->ptr[ib->length_dw++] = SDMA_PACKET(SDMA_OPCODE_COPY, SDMA_COPY_SUB_OPCODE_LINEAR, 0);
1322         ib->ptr[ib->length_dw++] = byte_count;
1323         ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */
1324         ib->ptr[ib->length_dw++] = lower_32_bits(src_offset);
1325         ib->ptr[ib->length_dw++] = upper_32_bits(src_offset);
1326         ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset);
1327         ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset);
1328 }
1329
1330 /**
1331  * cik_sdma_emit_fill_buffer - fill buffer using the sDMA engine
1332  *
1333  * @ib: indirect buffer to fill
1334  * @src_data: value to write to buffer
1335  * @dst_offset: dst GPU address
1336  * @byte_count: number of bytes to xfer
1337  *
1338  * Fill GPU buffers using the DMA engine (CIK).
1339  */
1340 static void cik_sdma_emit_fill_buffer(struct amdgpu_ib *ib,
1341                                       uint32_t src_data,
1342                                       uint64_t dst_offset,
1343                                       uint32_t byte_count)
1344 {
1345         ib->ptr[ib->length_dw++] = SDMA_PACKET(SDMA_OPCODE_CONSTANT_FILL, 0, 0);
1346         ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset);
1347         ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset);
1348         ib->ptr[ib->length_dw++] = src_data;
1349         ib->ptr[ib->length_dw++] = byte_count;
1350 }
1351
1352 static const struct amdgpu_buffer_funcs cik_sdma_buffer_funcs = {
1353         .copy_max_bytes = 0x1fffff,
1354         .copy_num_dw = 7,
1355         .emit_copy_buffer = cik_sdma_emit_copy_buffer,
1356
1357         .fill_max_bytes = 0x1fffff,
1358         .fill_num_dw = 5,
1359         .emit_fill_buffer = cik_sdma_emit_fill_buffer,
1360 };
1361
1362 static void cik_sdma_set_buffer_funcs(struct amdgpu_device *adev)
1363 {
1364         adev->mman.buffer_funcs = &cik_sdma_buffer_funcs;
1365         adev->mman.buffer_funcs_ring = &adev->sdma.instance[0].ring;
1366 }
1367
1368 static const struct amdgpu_vm_pte_funcs cik_sdma_vm_pte_funcs = {
1369         .copy_pte_num_dw = 7,
1370         .copy_pte = cik_sdma_vm_copy_pte,
1371
1372         .write_pte = cik_sdma_vm_write_pte,
1373         .set_pte_pde = cik_sdma_vm_set_pte_pde,
1374 };
1375
1376 static void cik_sdma_set_vm_pte_funcs(struct amdgpu_device *adev)
1377 {
1378         unsigned i;
1379
1380         adev->vm_manager.vm_pte_funcs = &cik_sdma_vm_pte_funcs;
1381         for (i = 0; i < adev->sdma.num_instances; i++) {
1382                 adev->vm_manager.vm_pte_scheds[i] =
1383                         &adev->sdma.instance[i].ring.sched;
1384         }
1385         adev->vm_manager.vm_pte_num_scheds = adev->sdma.num_instances;
1386 }
1387
1388 const struct amdgpu_ip_block_version cik_sdma_ip_block =
1389 {
1390         .type = AMD_IP_BLOCK_TYPE_SDMA,
1391         .major = 2,
1392         .minor = 0,
1393         .rev = 0,
1394         .funcs = &cik_sdma_ip_funcs,
1395 };