drivers/gpu/drm/amd/amdgpu/atombios_dp.c

   1 /*
   2  * Copyright 2007-8 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice shall be included in
  13  * all copies or substantial portions of the Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  19  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  20  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  21  * OTHER DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors: Dave Airlie
  24  *          Alex Deucher
  25  *          Jerome Glisse
  26  */
  27
  28 #include <drm/amdgpu_drm.h>
  29 #include "amdgpu.h"
  30
  31 #include "atom.h"
  32 #include "atom-bits.h"
  33 #include "atombios_encoders.h"
  34 #include "atombios_dp.h"
  35 #include "amdgpu_connectors.h"
  36 #include "amdgpu_atombios.h"
  37 #include <drm/drm_dp_helper.h>
  38
  39 /* move these to drm_dp_helper.c/h */
  40 #define DP_LINK_CONFIGURATION_SIZE 9
  41 #define DP_DPCD_SIZE DP_RECEIVER_CAP_SIZE
  42
  43 static char *voltage_names[] = {
  44         "0.4V", "0.6V", "0.8V", "1.2V"
  45 };
  46 static char *pre_emph_names[] = {
  47         "0dB", "3.5dB", "6dB", "9.5dB"
  48 };
  49
  50 /***** amdgpu AUX functions *****/
  51
  52 union aux_channel_transaction {
  53         PROCESS_AUX_CHANNEL_TRANSACTION_PS_ALLOCATION v1;
  54         PROCESS_AUX_CHANNEL_TRANSACTION_PARAMETERS_V2 v2;
  55 };
  56
  57 static int amdgpu_atombios_dp_process_aux_ch(struct amdgpu_i2c_chan *chan,
  58                                       u8 *send, int send_bytes,
  59                                       u8 *recv, int recv_size,
  60                                       u8 delay, u8 *ack)
  61 {
  62         struct drm_device *dev = chan->dev;
  63         struct amdgpu_device *adev = dev->dev_private;
  64         union aux_channel_transaction args;
  65         int index = GetIndexIntoMasterTable(COMMAND, ProcessAuxChannelTransaction);
  66         unsigned char *base;
  67         int recv_bytes;
  68         int r = 0;
  69
  70         memset(&args, 0, sizeof(args));
  71
  72         mutex_lock(&chan->mutex);
  73
  74         base = (unsigned char *)(adev->mode_info.atom_context->scratch + 1);
  75
  76         amdgpu_atombios_copy_swap(base, send, send_bytes, true);
  77
  78         args.v2.lpAuxRequest = cpu_to_le16((u16)(0 + 4));
  79         args.v2.lpDataOut = cpu_to_le16((u16)(16 + 4));
  80         args.v2.ucDataOutLen = 0;
  81         args.v2.ucChannelID = chan->rec.i2c_id;
  82         args.v2.ucDelay = delay / 10;
  83         args.v2.ucHPD_ID = chan->rec.hpd;
  84
  85         amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args);
  86
  87         *ack = args.v2.ucReplyStatus;
  88
  89         /* timeout */
  90         if (args.v2.ucReplyStatus == 1) {
  91                 r = -ETIMEDOUT;
  92                 goto done;
  93         }
  94
  95         /* flags not zero */
  96         if (args.v2.ucReplyStatus == 2) {
  97                 DRM_DEBUG_KMS("dp_aux_ch flags not zero\n");
  98                 r = -EIO;
  99                 goto done;
 100         }
 101
 102         /* error */
 103         if (args.v2.ucReplyStatus == 3) {
 104                 DRM_DEBUG_KMS("dp_aux_ch error\n");
 105                 r = -EIO;
 106                 goto done;
 107         }
 108
 109         recv_bytes = args.v1.ucDataOutLen;
 110         if (recv_bytes > recv_size)
 111                 recv_bytes = recv_size;
 112
 113         if (recv && recv_size)
 114                 amdgpu_atombios_copy_swap(recv, base + 16, recv_bytes, false);
 115
 116         r = recv_bytes;
 117 done:
 118         mutex_unlock(&chan->mutex);
 119
 120         return r;
 121 }
 122
 123 #define BARE_ADDRESS_SIZE 3
 124 #define HEADER_SIZE (BARE_ADDRESS_SIZE + 1)
 125
 126 static ssize_t
 127 amdgpu_atombios_dp_aux_transfer(struct drm_dp_aux *aux, struct drm_dp_aux_msg *msg)
 128 {
 129         struct amdgpu_i2c_chan *chan =
 130                 container_of(aux, struct amdgpu_i2c_chan, aux);
 131         int ret;
 132         u8 tx_buf[20];
 133         size_t tx_size;
 134         u8 ack, delay = 0;
 135
 136         if (WARN_ON(msg->size > 16))
 137                 return -E2BIG;
 138
 139         tx_buf[0] = msg->address & 0xff;
 140         tx_buf[1] = msg->address >> 8;
 141         tx_buf[2] = (msg->request << 4) |
 142                 ((msg->address >> 16) & 0xf);
 143         tx_buf[3] = msg->size ? (msg->size - 1) : 0;
 144
 145         switch (msg->request & ~DP_AUX_I2C_MOT) {
 146         case DP_AUX_NATIVE_WRITE:
 147         case DP_AUX_I2C_WRITE:
 148                 /* tx_size needs to be 4 even for bare address packets since the atom
 149                  * table needs the info in tx_buf[3].
 150                  */
 151                 tx_size = HEADER_SIZE + msg->size;
 152                 if (msg->size == 0)
 153                         tx_buf[3] |= BARE_ADDRESS_SIZE << 4;
 154                 else
 155                         tx_buf[3] |= tx_size << 4;
 156                 memcpy(tx_buf + HEADER_SIZE, msg->buffer, msg->size);
 157                 ret = amdgpu_atombios_dp_process_aux_ch(chan,
 158                                                  tx_buf, tx_size, NULL, 0, delay, &ack);
 159                 if (ret >= 0)
 160                         /* Return payload size. */
 161                         ret = msg->size;
 162                 break;
 163         case DP_AUX_NATIVE_READ:
 164         case DP_AUX_I2C_READ:
 165                 /* tx_size needs to be 4 even for bare address packets since the atom
 166                  * table needs the info in tx_buf[3].
 167                  */
 168                 tx_size = HEADER_SIZE;
 169                 if (msg->size == 0)
 170                         tx_buf[3] |= BARE_ADDRESS_SIZE << 4;
 171                 else
 172                         tx_buf[3] |= tx_size << 4;
 173                 ret = amdgpu_atombios_dp_process_aux_ch(chan,
 174                                                  tx_buf, tx_size, msg->buffer, msg->size, delay, &ack);
 175                 break;
 176         default:
 177                 ret = -EINVAL;
 178                 break;
 179         }
 180
 181         if (ret >= 0)
 182                 msg->reply = ack >> 4;
 183
 184         return ret;
 185 }
 186
 187 void amdgpu_atombios_dp_aux_init(struct amdgpu_connector *amdgpu_connector)
 188 {
 189         amdgpu_connector->ddc_bus->rec.hpd = amdgpu_connector->hpd.hpd;
 190         amdgpu_connector->ddc_bus->aux.transfer = amdgpu_atombios_dp_aux_transfer;
 191         drm_dp_aux_init(&amdgpu_connector->ddc_bus->aux);
 192         amdgpu_connector->ddc_bus->has_aux = true;
 193 }
 194
 195 /***** general DP utility functions *****/
 196
 197 #define DP_VOLTAGE_MAX         DP_TRAIN_VOLTAGE_SWING_LEVEL_3
 198 #define DP_PRE_EMPHASIS_MAX    DP_TRAIN_PRE_EMPH_LEVEL_3
 199
 200 static void amdgpu_atombios_dp_get_adjust_train(const u8 link_status[DP_LINK_STATUS_SIZE],
 201                                                 int lane_count,
 202                                                 u8 train_set[4])
 203 {
 204         u8 v = 0;
 205         u8 p = 0;
 206         int lane;
 207
 208         for (lane = 0; lane < lane_count; lane++) {
 209                 u8 this_v = drm_dp_get_adjust_request_voltage(link_status, lane);
 210                 u8 this_p = drm_dp_get_adjust_request_pre_emphasis(link_status, lane);
 211
 212                 DRM_DEBUG_KMS("requested signal parameters: lane %d voltage %s pre_emph %s\n",
 213                           lane,
 214                           voltage_names[this_v >> DP_TRAIN_VOLTAGE_SWING_SHIFT],
 215                           pre_emph_names[this_p >> DP_TRAIN_PRE_EMPHASIS_SHIFT]);
 216
 217                 if (this_v > v)
 218                         v = this_v;
 219                 if (this_p > p)
 220                         p = this_p;
 221         }
 222
 223         if (v >= DP_VOLTAGE_MAX)
 224                 v |= DP_TRAIN_MAX_SWING_REACHED;
 225
 226         if (p >= DP_PRE_EMPHASIS_MAX)
 227                 p |= DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
 228
 229         DRM_DEBUG_KMS("using signal parameters: voltage %s pre_emph %s\n",
 230                   voltage_names[(v & DP_TRAIN_VOLTAGE_SWING_MASK) >> DP_TRAIN_VOLTAGE_SWING_SHIFT],
 231                   pre_emph_names[(p & DP_TRAIN_PRE_EMPHASIS_MASK) >> DP_TRAIN_PRE_EMPHASIS_SHIFT]);
 232
 233         for (lane = 0; lane < 4; lane++)
 234                 train_set[lane] = v | p;
 235 }
 236
 237 /* convert bits per color to bits per pixel */
 238 /* get bpc from the EDID */
 239 static unsigned amdgpu_atombios_dp_convert_bpc_to_bpp(int bpc)
 240 {
 241         if (bpc == 0)
 242                 return 24;
 243         else
 244                 return bpc * 3;
 245 }
 246
 247 /***** amdgpu specific DP functions *****/
 248
 249 static int amdgpu_atombios_dp_get_dp_link_config(struct drm_connector *connector,
 250                                                  const u8 dpcd[DP_DPCD_SIZE],
 251                                                  unsigned pix_clock,
 252                                                  unsigned *dp_lanes, unsigned *dp_rate)
 253 {
 254         unsigned bpp =
 255                 amdgpu_atombios_dp_convert_bpc_to_bpp(amdgpu_connector_get_monitor_bpc(connector));
 256         static const unsigned link_rates[3] = { 162000, 270000, 540000 };
 257         unsigned max_link_rate = drm_dp_max_link_rate(dpcd);
 258         unsigned max_lane_num = drm_dp_max_lane_count(dpcd);
 259         unsigned lane_num, i, max_pix_clock;
 260
 261         if (amdgpu_connector_encoder_get_dp_bridge_encoder_id(connector) ==
 262             ENCODER_OBJECT_ID_NUTMEG) {
 263                 for (lane_num = 1; lane_num <= max_lane_num; lane_num <<= 1) {
 264                         max_pix_clock = (lane_num * 270000 * 8) / bpp;
 265                         if (max_pix_clock >= pix_clock) {
 266                                 *dp_lanes = lane_num;
 267                                 *dp_rate = 270000;
 268                                 return 0;
 269                         }
 270                 }
 271         } else {
 272                 for (i = 0; i < ARRAY_SIZE(link_rates) && link_rates[i] <= max_link_rate; i++) {
 273                         for (lane_num = 1; lane_num <= max_lane_num; lane_num <<= 1) {
 274                                 max_pix_clock = (lane_num * link_rates[i] * 8) / bpp;
 275                                 if (max_pix_clock >= pix_clock) {
 276                                         *dp_lanes = lane_num;
 277                                         *dp_rate = link_rates[i];
 278                                         return 0;
 279                                 }
 280                         }
 281                 }
 282         }
 283
 284         return -EINVAL;
 285 }
 286
 287 static u8 amdgpu_atombios_dp_encoder_service(struct amdgpu_device *adev,
 288                                       int action, int dp_clock,
 289                                       u8 ucconfig, u8 lane_num)
 290 {
 291         DP_ENCODER_SERVICE_PARAMETERS args;
 292         int index = GetIndexIntoMasterTable(COMMAND, DPEncoderService);
 293
 294         memset(&args, 0, sizeof(args));
 295         args.ucLinkClock = dp_clock / 10;
 296         args.ucConfig = ucconfig;
 297         args.ucAction = action;
 298         args.ucLaneNum = lane_num;
 299         args.ucStatus = 0;
 300
 301         amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args);
 302         return args.ucStatus;
 303 }
 304
 305 u8 amdgpu_atombios_dp_get_sinktype(struct amdgpu_connector *amdgpu_connector)
 306 {
 307         struct drm_device *dev = amdgpu_connector->base.dev;
 308         struct amdgpu_device *adev = dev->dev_private;
 309
 310         return amdgpu_atombios_dp_encoder_service(adev, ATOM_DP_ACTION_GET_SINK_TYPE, 0,
 311                                            amdgpu_connector->ddc_bus->rec.i2c_id, 0);
 312 }
 313
 314 static void amdgpu_atombios_dp_probe_oui(struct amdgpu_connector *amdgpu_connector)
 315 {
 316         struct amdgpu_connector_atom_dig *dig_connector = amdgpu_connector->con_priv;
 317         u8 buf[3];
 318
 319         if (!(dig_connector->dpcd[DP_DOWN_STREAM_PORT_COUNT] & DP_OUI_SUPPORT))
 320                 return;
 321
 322         if (drm_dp_dpcd_read(&amdgpu_connector->ddc_bus->aux, DP_SINK_OUI, buf, 3) == 3)
 323                 DRM_DEBUG_KMS("Sink OUI: %02hx%02hx%02hx\n",
 324                               buf[0], buf[1], buf[2]);
 325
 326         if (drm_dp_dpcd_read(&amdgpu_connector->ddc_bus->aux, DP_BRANCH_OUI, buf, 3) == 3)
 327                 DRM_DEBUG_KMS("Branch OUI: %02hx%02hx%02hx\n",
 328                               buf[0], buf[1], buf[2]);
 329 }
 330
 331 int amdgpu_atombios_dp_get_dpcd(struct amdgpu_connector *amdgpu_connector)
 332 {
 333         struct amdgpu_connector_atom_dig *dig_connector = amdgpu_connector->con_priv;
 334         u8 msg[DP_DPCD_SIZE];
 335         int ret;
 336
 337         ret = drm_dp_dpcd_read(&amdgpu_connector->ddc_bus->aux, DP_DPCD_REV,
 338                                msg, DP_DPCD_SIZE);
 339         if (ret == DP_DPCD_SIZE) {
 340                 memcpy(dig_connector->dpcd, msg, DP_DPCD_SIZE);
 341
 342                 DRM_DEBUG_KMS("DPCD: %*ph\n", (int)sizeof(dig_connector->dpcd),
 343                               dig_connector->dpcd);
 344
 345                 amdgpu_atombios_dp_probe_oui(amdgpu_connector);
 346
 347                 return 0;
 348         }
 349
 350         dig_connector->dpcd[0] = 0;
 351         return -EINVAL;
 352 }
 353
 354 int amdgpu_atombios_dp_get_panel_mode(struct drm_encoder *encoder,
 355                                struct drm_connector *connector)
 356 {
 357         struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
 358         int panel_mode = DP_PANEL_MODE_EXTERNAL_DP_MODE;
 359         u16 dp_bridge = amdgpu_connector_encoder_get_dp_bridge_encoder_id(connector);
 360         u8 tmp;
 361
 362         if (!amdgpu_connector->con_priv)
 363                 return panel_mode;
 364
 365         if (dp_bridge != ENCODER_OBJECT_ID_NONE) {
 366                 /* DP bridge chips */
 367                 if (drm_dp_dpcd_readb(&amdgpu_connector->ddc_bus->aux,
 368                                       DP_EDP_CONFIGURATION_CAP, &tmp) == 1) {
 369                         if (tmp & 1)
 370                                 panel_mode = DP_PANEL_MODE_INTERNAL_DP2_MODE;
 371                         else if ((dp_bridge == ENCODER_OBJECT_ID_NUTMEG) ||
 372                                  (dp_bridge == ENCODER_OBJECT_ID_TRAVIS))
 373                                 panel_mode = DP_PANEL_MODE_INTERNAL_DP1_MODE;
 374                         else
 375                                 panel_mode = DP_PANEL_MODE_EXTERNAL_DP_MODE;
 376                 }
 377         } else if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) {
 378                 /* eDP */
 379                 if (drm_dp_dpcd_readb(&amdgpu_connector->ddc_bus->aux,
 380                                       DP_EDP_CONFIGURATION_CAP, &tmp) == 1) {
 381                         if (tmp & 1)
 382                                 panel_mode = DP_PANEL_MODE_INTERNAL_DP2_MODE;
 383                 }
 384         }
 385
 386         return panel_mode;
 387 }
 388
 389 void amdgpu_atombios_dp_set_link_config(struct drm_connector *connector,
 390                                  const struct drm_display_mode *mode)
 391 {
 392         struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
 393         struct amdgpu_connector_atom_dig *dig_connector;
 394         int ret;
 395
 396         if (!amdgpu_connector->con_priv)
 397                 return;
 398         dig_connector = amdgpu_connector->con_priv;
 399
 400         if ((dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) ||
 401             (dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_eDP)) {
 402                 ret = amdgpu_atombios_dp_get_dp_link_config(connector, dig_connector->dpcd,
 403                                                             mode->clock,
 404                                                             &dig_connector->dp_lane_count,
 405                                                             &dig_connector->dp_clock);
 406                 if (ret) {
 407                         dig_connector->dp_clock = 0;
 408                         dig_connector->dp_lane_count = 0;
 409                 }
 410         }
 411 }
 412
 413 int amdgpu_atombios_dp_mode_valid_helper(struct drm_connector *connector,
 414                                   struct drm_display_mode *mode)
 415 {
 416         struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
 417         struct amdgpu_connector_atom_dig *dig_connector;
 418         unsigned dp_lanes, dp_clock;
 419         int ret;
 420
 421         if (!amdgpu_connector->con_priv)
 422                 return MODE_CLOCK_HIGH;
 423         dig_connector = amdgpu_connector->con_priv;
 424
 425         ret = amdgpu_atombios_dp_get_dp_link_config(connector, dig_connector->dpcd,
 426                                                     mode->clock, &dp_lanes, &dp_clock);
 427         if (ret)
 428                 return MODE_CLOCK_HIGH;
 429
 430         if ((dp_clock == 540000) &&
 431             (!amdgpu_connector_is_dp12_capable(connector)))
 432                 return MODE_CLOCK_HIGH;
 433
 434         return MODE_OK;
 435 }
 436
 437 bool amdgpu_atombios_dp_needs_link_train(struct amdgpu_connector *amdgpu_connector)
 438 {
 439         u8 link_status[DP_LINK_STATUS_SIZE];
 440         struct amdgpu_connector_atom_dig *dig = amdgpu_connector->con_priv;
 441
 442         if (drm_dp_dpcd_read_link_status(&amdgpu_connector->ddc_bus->aux, link_status)
 443             <= 0)
 444                 return false;
 445         if (drm_dp_channel_eq_ok(link_status, dig->dp_lane_count))
 446                 return false;
 447         return true;
 448 }
 449
 450 void amdgpu_atombios_dp_set_rx_power_state(struct drm_connector *connector,
 451                                     u8 power_state)
 452 {
 453         struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
 454         struct amdgpu_connector_atom_dig *dig_connector;
 455
 456         if (!amdgpu_connector->con_priv)
 457                 return;
 458
 459         dig_connector = amdgpu_connector->con_priv;
 460
 461         /* power up/down the sink */
 462         if (dig_connector->dpcd[0] >= 0x11) {
 463                 drm_dp_dpcd_writeb(&amdgpu_connector->ddc_bus->aux,
 464                                    DP_SET_POWER, power_state);
 465                 usleep_range(1000, 2000);
 466         }
 467 }
 468
 469 struct amdgpu_atombios_dp_link_train_info {
 470         struct amdgpu_device *adev;
 471         struct drm_encoder *encoder;
 472         struct drm_connector *connector;
 473         int dp_clock;
 474         int dp_lane_count;
 475         bool tp3_supported;
 476         u8 dpcd[DP_RECEIVER_CAP_SIZE];
 477         u8 train_set[4];
 478         u8 link_status[DP_LINK_STATUS_SIZE];
 479         u8 tries;
 480         struct drm_dp_aux *aux;
 481 };
 482
 483 static void
 484 amdgpu_atombios_dp_update_vs_emph(struct amdgpu_atombios_dp_link_train_info *dp_info)
 485 {
 486         /* set the initial vs/emph on the source */
 487         amdgpu_atombios_encoder_setup_dig_transmitter(dp_info->encoder,
 488                                                ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH,
 489                                                0, dp_info->train_set[0]); /* sets all lanes at once */
 490
 491         /* set the vs/emph on the sink */
 492         drm_dp_dpcd_write(dp_info->aux, DP_TRAINING_LANE0_SET,
 493                           dp_info->train_set, dp_info->dp_lane_count);
 494 }
 495
 496 static void
 497 amdgpu_atombios_dp_set_tp(struct amdgpu_atombios_dp_link_train_info *dp_info, int tp)
 498 {
 499         int rtp = 0;
 500
 501         /* set training pattern on the source */
 502         switch (tp) {
 503         case DP_TRAINING_PATTERN_1:
 504                 rtp = ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN1;
 505                 break;
 506         case DP_TRAINING_PATTERN_2:
 507                 rtp = ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN2;
 508                 break;
 509         case DP_TRAINING_PATTERN_3:
 510                 rtp = ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN3;
 511                         break;
 512         }
 513         amdgpu_atombios_encoder_setup_dig_encoder(dp_info->encoder, rtp, 0);
 514
 515         /* enable training pattern on the sink */
 516         drm_dp_dpcd_writeb(dp_info->aux, DP_TRAINING_PATTERN_SET, tp);
 517 }
 518
 519 static int
 520 amdgpu_atombios_dp_link_train_init(struct amdgpu_atombios_dp_link_train_info *dp_info)
 521 {
 522         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(dp_info->encoder);
 523         struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
 524         u8 tmp;
 525
 526         /* power up the sink */
 527         amdgpu_atombios_dp_set_rx_power_state(dp_info->connector, DP_SET_POWER_D0);
 528
 529         /* possibly enable downspread on the sink */
 530         if (dp_info->dpcd[3] & 0x1)
 531                 drm_dp_dpcd_writeb(dp_info->aux,
 532                                    DP_DOWNSPREAD_CTRL, DP_SPREAD_AMP_0_5);
 533         else
 534                 drm_dp_dpcd_writeb(dp_info->aux,
 535                                    DP_DOWNSPREAD_CTRL, 0);
 536
 537         if (dig->panel_mode == DP_PANEL_MODE_INTERNAL_DP2_MODE)
 538                 drm_dp_dpcd_writeb(dp_info->aux, DP_EDP_CONFIGURATION_SET, 1);
 539
 540         /* set the lane count on the sink */
 541         tmp = dp_info->dp_lane_count;
 542         if (drm_dp_enhanced_frame_cap(dp_info->dpcd))
 543                 tmp |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
 544         drm_dp_dpcd_writeb(dp_info->aux, DP_LANE_COUNT_SET, tmp);
 545
 546         /* set the link rate on the sink */
 547         tmp = drm_dp_link_rate_to_bw_code(dp_info->dp_clock);
 548         drm_dp_dpcd_writeb(dp_info->aux, DP_LINK_BW_SET, tmp);
 549
 550         /* start training on the source */
 551         amdgpu_atombios_encoder_setup_dig_encoder(dp_info->encoder,
 552                                            ATOM_ENCODER_CMD_DP_LINK_TRAINING_START, 0);
 553
 554         /* disable the training pattern on the sink */
 555         drm_dp_dpcd_writeb(dp_info->aux,
 556                            DP_TRAINING_PATTERN_SET,
 557                            DP_TRAINING_PATTERN_DISABLE);
 558
 559         return 0;
 560 }
 561
 562 static int
 563 amdgpu_atombios_dp_link_train_finish(struct amdgpu_atombios_dp_link_train_info *dp_info)
 564 {
 565         udelay(400);
 566
 567         /* disable the training pattern on the sink */
 568         drm_dp_dpcd_writeb(dp_info->aux,
 569                            DP_TRAINING_PATTERN_SET,
 570                            DP_TRAINING_PATTERN_DISABLE);
 571
 572         /* disable the training pattern on the source */
 573         amdgpu_atombios_encoder_setup_dig_encoder(dp_info->encoder,
 574                                            ATOM_ENCODER_CMD_DP_LINK_TRAINING_COMPLETE, 0);
 575
 576         return 0;
 577 }
 578
 579 static int
 580 amdgpu_atombios_dp_link_train_cr(struct amdgpu_atombios_dp_link_train_info *dp_info)
 581 {
 582         bool clock_recovery;
 583         u8 voltage;
 584         int i;
 585
 586         amdgpu_atombios_dp_set_tp(dp_info, DP_TRAINING_PATTERN_1);
 587         memset(dp_info->train_set, 0, 4);
 588         amdgpu_atombios_dp_update_vs_emph(dp_info);
 589
 590         udelay(400);
 591
 592         /* clock recovery loop */
 593         clock_recovery = false;
 594         dp_info->tries = 0;
 595         voltage = 0xff;
 596         while (1) {
 597                 drm_dp_link_train_clock_recovery_delay(dp_info->dpcd);
 598
 599                 if (drm_dp_dpcd_read_link_status(dp_info->aux,
 600                                                  dp_info->link_status) <= 0) {
 601                         DRM_ERROR("displayport link status failed\n");
 602                         break;
 603                 }
 604
 605                 if (drm_dp_clock_recovery_ok(dp_info->link_status, dp_info->dp_lane_count)) {
 606                         clock_recovery = true;
 607                         break;
 608                 }
 609
 610                 for (i = 0; i < dp_info->dp_lane_count; i++) {
 611                         if ((dp_info->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0)
 612                                 break;
 613                 }
 614                 if (i == dp_info->dp_lane_count) {
 615                         DRM_ERROR("clock recovery reached max voltage\n");
 616                         break;
 617                 }
 618
 619                 if ((dp_info->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) {
 620                         ++dp_info->tries;
 621                         if (dp_info->tries == 5) {
 622                                 DRM_ERROR("clock recovery tried 5 times\n");
 623                                 break;
 624                         }
 625                 } else
 626                         dp_info->tries = 0;
 627
 628                 voltage = dp_info->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
 629
 630                 /* Compute new train_set as requested by sink */
 631                 amdgpu_atombios_dp_get_adjust_train(dp_info->link_status, dp_info->dp_lane_count,
 632                                              dp_info->train_set);
 633
 634                 amdgpu_atombios_dp_update_vs_emph(dp_info);
 635         }
 636         if (!clock_recovery) {
 637                 DRM_ERROR("clock recovery failed\n");
 638                 return -1;
 639         } else {
 640                 DRM_DEBUG_KMS("clock recovery at voltage %d pre-emphasis %d\n",
 641                           dp_info->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK,
 642                           (dp_info->train_set[0] & DP_TRAIN_PRE_EMPHASIS_MASK) >>
 643                           DP_TRAIN_PRE_EMPHASIS_SHIFT);
 644                 return 0;
 645         }
 646 }
 647
 648 static int
 649 amdgpu_atombios_dp_link_train_ce(struct amdgpu_atombios_dp_link_train_info *dp_info)
 650 {
 651         bool channel_eq;
 652
 653         if (dp_info->tp3_supported)
 654                 amdgpu_atombios_dp_set_tp(dp_info, DP_TRAINING_PATTERN_3);
 655         else
 656                 amdgpu_atombios_dp_set_tp(dp_info, DP_TRAINING_PATTERN_2);
 657
 658         /* channel equalization loop */
 659         dp_info->tries = 0;
 660         channel_eq = false;
 661         while (1) {
 662                 drm_dp_link_train_channel_eq_delay(dp_info->dpcd);
 663
 664                 if (drm_dp_dpcd_read_link_status(dp_info->aux,
 665                                                  dp_info->link_status) <= 0) {
 666                         DRM_ERROR("displayport link status failed\n");
 667                         break;
 668                 }
 669
 670                 if (drm_dp_channel_eq_ok(dp_info->link_status, dp_info->dp_lane_count)) {
 671                         channel_eq = true;
 672                         break;
 673                 }
 674
 675                 /* Try 5 times */
 676                 if (dp_info->tries > 5) {
 677                         DRM_ERROR("channel eq failed: 5 tries\n");
 678                         break;
 679                 }
 680
 681                 /* Compute new train_set as requested by sink */
 682                 amdgpu_atombios_dp_get_adjust_train(dp_info->link_status, dp_info->dp_lane_count,
 683                                              dp_info->train_set);
 684
 685                 amdgpu_atombios_dp_update_vs_emph(dp_info);
 686                 dp_info->tries++;
 687         }
 688
 689         if (!channel_eq) {
 690                 DRM_ERROR("channel eq failed\n");
 691                 return -1;
 692         } else {
 693                 DRM_DEBUG_KMS("channel eq at voltage %d pre-emphasis %d\n",
 694                           dp_info->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK,
 695                           (dp_info->train_set[0] & DP_TRAIN_PRE_EMPHASIS_MASK)
 696                           >> DP_TRAIN_PRE_EMPHASIS_SHIFT);
 697                 return 0;
 698         }
 699 }
 700
 701 void amdgpu_atombios_dp_link_train(struct drm_encoder *encoder,
 702                             struct drm_connector *connector)
 703 {
 704         struct drm_device *dev = encoder->dev;
 705         struct amdgpu_device *adev = dev->dev_private;
 706         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
 707         struct amdgpu_connector *amdgpu_connector;
 708         struct amdgpu_connector_atom_dig *dig_connector;
 709         struct amdgpu_atombios_dp_link_train_info dp_info;
 710         u8 tmp;
 711
 712         if (!amdgpu_encoder->enc_priv)
 713                 return;
 714
 715         amdgpu_connector = to_amdgpu_connector(connector);
 716         if (!amdgpu_connector->con_priv)
 717                 return;
 718         dig_connector = amdgpu_connector->con_priv;
 719
 720         if ((dig_connector->dp_sink_type != CONNECTOR_OBJECT_ID_DISPLAYPORT) &&
 721             (dig_connector->dp_sink_type != CONNECTOR_OBJECT_ID_eDP))
 722                 return;
 723
 724         if (drm_dp_dpcd_readb(&amdgpu_connector->ddc_bus->aux, DP_MAX_LANE_COUNT, &tmp)
 725             == 1) {
 726                 if (tmp & DP_TPS3_SUPPORTED)
 727                         dp_info.tp3_supported = true;
 728                 else
 729                         dp_info.tp3_supported = false;
 730         } else {
 731                 dp_info.tp3_supported = false;
 732         }
 733
 734         memcpy(dp_info.dpcd, dig_connector->dpcd, DP_RECEIVER_CAP_SIZE);
 735         dp_info.adev = adev;
 736         dp_info.encoder = encoder;
 737         dp_info.connector = connector;
 738         dp_info.dp_lane_count = dig_connector->dp_lane_count;
 739         dp_info.dp_clock = dig_connector->dp_clock;
 740         dp_info.aux = &amdgpu_connector->ddc_bus->aux;
 741
 742         if (amdgpu_atombios_dp_link_train_init(&dp_info))
 743                 goto done;
 744         if (amdgpu_atombios_dp_link_train_cr(&dp_info))
 745                 goto done;
 746         if (amdgpu_atombios_dp_link_train_ce(&dp_info))
 747                 goto done;
 748 done:
 749         if (amdgpu_atombios_dp_link_train_finish(&dp_info))
 750                 return;
 751 }