2 * Copyright 2008 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
22 * Author: Stanislaw Skowronek
25 #include <linux/module.h>
26 #include <linux/sched.h>
27 #include <linux/slab.h>
28 #include <asm/unaligned.h>
30 #include <drm/drm_util.h>
35 #include "atom-names.h"
36 #include "atom-bits.h"
39 #define ATOM_COND_ABOVE 0
40 #define ATOM_COND_ABOVEOREQUAL 1
41 #define ATOM_COND_ALWAYS 2
42 #define ATOM_COND_BELOW 3
43 #define ATOM_COND_BELOWOREQUAL 4
44 #define ATOM_COND_EQUAL 5
45 #define ATOM_COND_NOTEQUAL 6
47 #define ATOM_PORT_ATI 0
48 #define ATOM_PORT_PCI 1
49 #define ATOM_PORT_SYSIO 2
51 #define ATOM_UNIT_MICROSEC 0
52 #define ATOM_UNIT_MILLISEC 1
58 struct atom_context *ctx;
63 unsigned long last_jump_jiffies;
67 int amdgpu_atom_debug = 0;
68 static int amdgpu_atom_execute_table_locked(struct atom_context *ctx, int index, uint32_t * params);
69 int amdgpu_atom_execute_table(struct atom_context *ctx, int index, uint32_t * params);
71 static uint32_t atom_arg_mask[8] =
72 { 0xFFFFFFFF, 0xFFFF, 0xFFFF00, 0xFFFF0000, 0xFF, 0xFF00, 0xFF0000,
74 static int atom_arg_shift[8] = { 0, 0, 8, 16, 0, 8, 16, 24 };
76 static int atom_dst_to_src[8][4] = {
77 /* translate destination alignment field to the source alignment encoding */
87 static int atom_def_dst[8] = { 0, 0, 1, 2, 0, 1, 2, 3 };
89 static int debug_depth = 0;
91 static void debug_print_spaces(int n)
97 #define DEBUG(...) do if (amdgpu_atom_debug) { printk(KERN_DEBUG __VA_ARGS__); } while (0)
98 #define SDEBUG(...) do if (amdgpu_atom_debug) { printk(KERN_DEBUG); debug_print_spaces(debug_depth); printk(__VA_ARGS__); } while (0)
100 #define DEBUG(...) do { } while (0)
101 #define SDEBUG(...) do { } while (0)
104 static uint32_t atom_iio_execute(struct atom_context *ctx, int base,
105 uint32_t index, uint32_t data)
107 uint32_t temp = 0xCDCDCDCD;
115 temp = ctx->card->ioreg_read(ctx->card, CU16(base + 1));
119 ctx->card->ioreg_write(ctx->card, CU16(base + 1), temp);
124 ~((0xFFFFFFFF >> (32 - CU8(base + 1))) <<
130 (0xFFFFFFFF >> (32 - CU8(base + 1))) << CU8(base +
134 case ATOM_IIO_MOVE_INDEX:
136 ~((0xFFFFFFFF >> (32 - CU8(base + 1))) <<
139 ((index >> CU8(base + 2)) &
140 (0xFFFFFFFF >> (32 - CU8(base + 1)))) << CU8(base +
144 case ATOM_IIO_MOVE_DATA:
146 ~((0xFFFFFFFF >> (32 - CU8(base + 1))) <<
149 ((data >> CU8(base + 2)) &
150 (0xFFFFFFFF >> (32 - CU8(base + 1)))) << CU8(base +
154 case ATOM_IIO_MOVE_ATTR:
156 ~((0xFFFFFFFF >> (32 - CU8(base + 1))) <<
160 io_attr >> CU8(base + 2)) & (0xFFFFFFFF >> (32 -
171 pr_info("Unknown IIO opcode\n");
176 static uint32_t atom_get_src_int(atom_exec_context *ctx, uint8_t attr,
177 int *ptr, uint32_t *saved, int print)
179 uint32_t idx, val = 0xCDCDCDCD, align, arg;
180 struct atom_context *gctx = ctx->ctx;
182 align = (attr >> 3) & 7;
188 DEBUG("REG[0x%04X]", idx);
189 idx += gctx->reg_block;
190 switch (gctx->io_mode) {
192 val = gctx->card->reg_read(gctx->card, idx);
195 pr_info("PCI registers are not implemented\n");
198 pr_info("SYSIO registers are not implemented\n");
201 if (!(gctx->io_mode & 0x80)) {
202 pr_info("Bad IO mode\n");
205 if (!gctx->iio[gctx->io_mode & 0x7F]) {
206 pr_info("Undefined indirect IO read method %d\n",
207 gctx->io_mode & 0x7F);
211 atom_iio_execute(gctx,
212 gctx->iio[gctx->io_mode & 0x7F],
219 /* get_unaligned_le32 avoids unaligned accesses from atombios
220 * tables, noticed on a DEC Alpha. */
221 val = get_unaligned_le32((u32 *)&ctx->ps[idx]);
223 DEBUG("PS[0x%02X,0x%04X]", idx, val);
229 DEBUG("WS[0x%02X]", idx);
231 case ATOM_WS_QUOTIENT:
232 val = gctx->divmul[0];
234 case ATOM_WS_REMAINDER:
235 val = gctx->divmul[1];
237 case ATOM_WS_DATAPTR:
238 val = gctx->data_block;
243 case ATOM_WS_OR_MASK:
244 val = 1 << gctx->shift;
246 case ATOM_WS_AND_MASK:
247 val = ~(1 << gctx->shift);
249 case ATOM_WS_FB_WINDOW:
252 case ATOM_WS_ATTRIBUTES:
256 val = gctx->reg_block;
266 if (gctx->data_block)
267 DEBUG("ID[0x%04X+%04X]", idx, gctx->data_block);
269 DEBUG("ID[0x%04X]", idx);
271 val = U32(idx + gctx->data_block);
276 if ((gctx->fb_base + (idx * 4)) > gctx->scratch_size_bytes) {
277 DRM_ERROR("ATOM: fb read beyond scratch region: %d vs. %d\n",
278 gctx->fb_base + (idx * 4), gctx->scratch_size_bytes);
281 val = gctx->scratch[(gctx->fb_base / 4) + idx];
283 DEBUG("FB[0x%02X]", idx);
291 DEBUG("IMM 0x%08X\n", val);
295 case ATOM_SRC_WORD16:
299 DEBUG("IMM 0x%04X\n", val);
303 case ATOM_SRC_BYTE16:
304 case ATOM_SRC_BYTE24:
308 DEBUG("IMM 0x%02X\n", val);
316 DEBUG("PLL[0x%02X]", idx);
317 val = gctx->card->pll_read(gctx->card, idx);
323 DEBUG("MC[0x%02X]", idx);
324 val = gctx->card->mc_read(gctx->card, idx);
329 val &= atom_arg_mask[align];
330 val >>= atom_arg_shift[align];
334 DEBUG(".[31:0] -> 0x%08X\n", val);
337 DEBUG(".[15:0] -> 0x%04X\n", val);
340 DEBUG(".[23:8] -> 0x%04X\n", val);
342 case ATOM_SRC_WORD16:
343 DEBUG(".[31:16] -> 0x%04X\n", val);
346 DEBUG(".[7:0] -> 0x%02X\n", val);
349 DEBUG(".[15:8] -> 0x%02X\n", val);
351 case ATOM_SRC_BYTE16:
352 DEBUG(".[23:16] -> 0x%02X\n", val);
354 case ATOM_SRC_BYTE24:
355 DEBUG(".[31:24] -> 0x%02X\n", val);
361 static void atom_skip_src_int(atom_exec_context *ctx, uint8_t attr, int *ptr)
363 uint32_t align = (attr >> 3) & 7, arg = attr & 7;
383 case ATOM_SRC_WORD16:
388 case ATOM_SRC_BYTE16:
389 case ATOM_SRC_BYTE24:
397 static uint32_t atom_get_src(atom_exec_context *ctx, uint8_t attr, int *ptr)
399 return atom_get_src_int(ctx, attr, ptr, NULL, 1);
402 static uint32_t atom_get_src_direct(atom_exec_context *ctx, uint8_t align, int *ptr)
404 uint32_t val = 0xCDCDCDCD;
413 case ATOM_SRC_WORD16:
419 case ATOM_SRC_BYTE16:
420 case ATOM_SRC_BYTE24:
428 static uint32_t atom_get_dst(atom_exec_context *ctx, int arg, uint8_t attr,
429 int *ptr, uint32_t *saved, int print)
431 return atom_get_src_int(ctx,
432 arg | atom_dst_to_src[(attr >> 3) &
433 7][(attr >> 6) & 3] << 3,
437 static void atom_skip_dst(atom_exec_context *ctx, int arg, uint8_t attr, int *ptr)
439 atom_skip_src_int(ctx,
440 arg | atom_dst_to_src[(attr >> 3) & 7][(attr >> 6) &
444 static void atom_put_dst(atom_exec_context *ctx, int arg, uint8_t attr,
445 int *ptr, uint32_t val, uint32_t saved)
448 atom_dst_to_src[(attr >> 3) & 7][(attr >> 6) & 3], old_val =
450 struct atom_context *gctx = ctx->ctx;
451 old_val &= atom_arg_mask[align] >> atom_arg_shift[align];
452 val <<= atom_arg_shift[align];
453 val &= atom_arg_mask[align];
454 saved &= ~atom_arg_mask[align];
460 DEBUG("REG[0x%04X]", idx);
461 idx += gctx->reg_block;
462 switch (gctx->io_mode) {
465 gctx->card->reg_write(gctx->card, idx,
468 gctx->card->reg_write(gctx->card, idx, val);
471 pr_info("PCI registers are not implemented\n");
474 pr_info("SYSIO registers are not implemented\n");
477 if (!(gctx->io_mode & 0x80)) {
478 pr_info("Bad IO mode\n");
481 if (!gctx->iio[gctx->io_mode & 0xFF]) {
482 pr_info("Undefined indirect IO write method %d\n",
483 gctx->io_mode & 0x7F);
486 atom_iio_execute(gctx, gctx->iio[gctx->io_mode & 0xFF],
493 DEBUG("PS[0x%02X]", idx);
494 ctx->ps[idx] = cpu_to_le32(val);
499 DEBUG("WS[0x%02X]", idx);
501 case ATOM_WS_QUOTIENT:
502 gctx->divmul[0] = val;
504 case ATOM_WS_REMAINDER:
505 gctx->divmul[1] = val;
507 case ATOM_WS_DATAPTR:
508 gctx->data_block = val;
513 case ATOM_WS_OR_MASK:
514 case ATOM_WS_AND_MASK:
516 case ATOM_WS_FB_WINDOW:
519 case ATOM_WS_ATTRIBUTES:
523 gctx->reg_block = val;
532 if ((gctx->fb_base + (idx * 4)) > gctx->scratch_size_bytes) {
533 DRM_ERROR("ATOM: fb write beyond scratch region: %d vs. %d\n",
534 gctx->fb_base + (idx * 4), gctx->scratch_size_bytes);
536 gctx->scratch[(gctx->fb_base / 4) + idx] = val;
537 DEBUG("FB[0x%02X]", idx);
542 DEBUG("PLL[0x%02X]", idx);
543 gctx->card->pll_write(gctx->card, idx, val);
548 DEBUG("MC[0x%02X]", idx);
549 gctx->card->mc_write(gctx->card, idx, val);
554 DEBUG(".[31:0] <- 0x%08X\n", old_val);
557 DEBUG(".[15:0] <- 0x%04X\n", old_val);
560 DEBUG(".[23:8] <- 0x%04X\n", old_val);
562 case ATOM_SRC_WORD16:
563 DEBUG(".[31:16] <- 0x%04X\n", old_val);
566 DEBUG(".[7:0] <- 0x%02X\n", old_val);
569 DEBUG(".[15:8] <- 0x%02X\n", old_val);
571 case ATOM_SRC_BYTE16:
572 DEBUG(".[23:16] <- 0x%02X\n", old_val);
574 case ATOM_SRC_BYTE24:
575 DEBUG(".[31:24] <- 0x%02X\n", old_val);
580 static void atom_op_add(atom_exec_context *ctx, int *ptr, int arg)
582 uint8_t attr = U8((*ptr)++);
583 uint32_t dst, src, saved;
586 dst = atom_get_dst(ctx, arg, attr, ptr, &saved, 1);
588 src = atom_get_src(ctx, attr, ptr);
591 atom_put_dst(ctx, arg, attr, &dptr, dst, saved);
594 static void atom_op_and(atom_exec_context *ctx, int *ptr, int arg)
596 uint8_t attr = U8((*ptr)++);
597 uint32_t dst, src, saved;
600 dst = atom_get_dst(ctx, arg, attr, ptr, &saved, 1);
602 src = atom_get_src(ctx, attr, ptr);
605 atom_put_dst(ctx, arg, attr, &dptr, dst, saved);
608 static void atom_op_beep(atom_exec_context *ctx, int *ptr, int arg)
610 printk("ATOM BIOS beeped!\n");
613 static void atom_op_calltable(atom_exec_context *ctx, int *ptr, int arg)
615 int idx = U8((*ptr)++);
618 if (idx < ATOM_TABLE_NAMES_CNT)
619 SDEBUG(" table: %d (%s)\n", idx, atom_table_names[idx]);
621 SDEBUG(" table: %d\n", idx);
622 if (U16(ctx->ctx->cmd_table + 4 + 2 * idx))
623 r = amdgpu_atom_execute_table_locked(ctx->ctx, idx, ctx->ps + ctx->ps_shift);
629 static void atom_op_clear(atom_exec_context *ctx, int *ptr, int arg)
631 uint8_t attr = U8((*ptr)++);
635 attr |= atom_def_dst[attr >> 3] << 6;
636 atom_get_dst(ctx, arg, attr, ptr, &saved, 0);
638 atom_put_dst(ctx, arg, attr, &dptr, 0, saved);
641 static void atom_op_compare(atom_exec_context *ctx, int *ptr, int arg)
643 uint8_t attr = U8((*ptr)++);
646 dst = atom_get_dst(ctx, arg, attr, ptr, NULL, 1);
648 src = atom_get_src(ctx, attr, ptr);
649 ctx->ctx->cs_equal = (dst == src);
650 ctx->ctx->cs_above = (dst > src);
651 SDEBUG(" result: %s %s\n", ctx->ctx->cs_equal ? "EQ" : "NE",
652 ctx->ctx->cs_above ? "GT" : "LE");
655 static void atom_op_delay(atom_exec_context *ctx, int *ptr, int arg)
657 unsigned count = U8((*ptr)++);
658 SDEBUG(" count: %d\n", count);
659 if (arg == ATOM_UNIT_MICROSEC)
661 else if (!drm_can_sleep())
667 static void atom_op_div(atom_exec_context *ctx, int *ptr, int arg)
669 uint8_t attr = U8((*ptr)++);
672 dst = atom_get_dst(ctx, arg, attr, ptr, NULL, 1);
674 src = atom_get_src(ctx, attr, ptr);
676 ctx->ctx->divmul[0] = dst / src;
677 ctx->ctx->divmul[1] = dst % src;
679 ctx->ctx->divmul[0] = 0;
680 ctx->ctx->divmul[1] = 0;
684 static void atom_op_div32(atom_exec_context *ctx, int *ptr, int arg)
687 uint8_t attr = U8((*ptr)++);
690 dst = atom_get_dst(ctx, arg, attr, ptr, NULL, 1);
692 src = atom_get_src(ctx, attr, ptr);
695 val64 |= ((uint64_t)ctx->ctx->divmul[1]) << 32;
697 ctx->ctx->divmul[0] = lower_32_bits(val64);
698 ctx->ctx->divmul[1] = upper_32_bits(val64);
700 ctx->ctx->divmul[0] = 0;
701 ctx->ctx->divmul[1] = 0;
705 static void atom_op_eot(atom_exec_context *ctx, int *ptr, int arg)
707 /* functionally, a nop */
710 static void atom_op_jump(atom_exec_context *ctx, int *ptr, int arg)
712 int execute = 0, target = U16(*ptr);
713 unsigned long cjiffies;
717 case ATOM_COND_ABOVE:
718 execute = ctx->ctx->cs_above;
720 case ATOM_COND_ABOVEOREQUAL:
721 execute = ctx->ctx->cs_above || ctx->ctx->cs_equal;
723 case ATOM_COND_ALWAYS:
726 case ATOM_COND_BELOW:
727 execute = !(ctx->ctx->cs_above || ctx->ctx->cs_equal);
729 case ATOM_COND_BELOWOREQUAL:
730 execute = !ctx->ctx->cs_above;
732 case ATOM_COND_EQUAL:
733 execute = ctx->ctx->cs_equal;
735 case ATOM_COND_NOTEQUAL:
736 execute = !ctx->ctx->cs_equal;
739 if (arg != ATOM_COND_ALWAYS)
740 SDEBUG(" taken: %s\n", execute ? "yes" : "no");
741 SDEBUG(" target: 0x%04X\n", target);
743 if (ctx->last_jump == (ctx->start + target)) {
745 if (time_after(cjiffies, ctx->last_jump_jiffies)) {
746 cjiffies -= ctx->last_jump_jiffies;
747 if ((jiffies_to_msecs(cjiffies) > 5000)) {
748 DRM_ERROR("atombios stuck in loop for more than 5secs aborting\n");
752 /* jiffies wrap around we will just wait a little longer */
753 ctx->last_jump_jiffies = jiffies;
756 ctx->last_jump = ctx->start + target;
757 ctx->last_jump_jiffies = jiffies;
759 *ptr = ctx->start + target;
763 static void atom_op_mask(atom_exec_context *ctx, int *ptr, int arg)
765 uint8_t attr = U8((*ptr)++);
766 uint32_t dst, mask, src, saved;
769 dst = atom_get_dst(ctx, arg, attr, ptr, &saved, 1);
770 mask = atom_get_src_direct(ctx, ((attr >> 3) & 7), ptr);
771 SDEBUG(" mask: 0x%08x", mask);
773 src = atom_get_src(ctx, attr, ptr);
777 atom_put_dst(ctx, arg, attr, &dptr, dst, saved);
780 static void atom_op_move(atom_exec_context *ctx, int *ptr, int arg)
782 uint8_t attr = U8((*ptr)++);
785 if (((attr >> 3) & 7) != ATOM_SRC_DWORD)
786 atom_get_dst(ctx, arg, attr, ptr, &saved, 0);
788 atom_skip_dst(ctx, arg, attr, ptr);
792 src = atom_get_src(ctx, attr, ptr);
794 atom_put_dst(ctx, arg, attr, &dptr, src, saved);
797 static void atom_op_mul(atom_exec_context *ctx, int *ptr, int arg)
799 uint8_t attr = U8((*ptr)++);
802 dst = atom_get_dst(ctx, arg, attr, ptr, NULL, 1);
804 src = atom_get_src(ctx, attr, ptr);
805 ctx->ctx->divmul[0] = dst * src;
808 static void atom_op_mul32(atom_exec_context *ctx, int *ptr, int arg)
811 uint8_t attr = U8((*ptr)++);
814 dst = atom_get_dst(ctx, arg, attr, ptr, NULL, 1);
816 src = atom_get_src(ctx, attr, ptr);
817 val64 = (uint64_t)dst * (uint64_t)src;
818 ctx->ctx->divmul[0] = lower_32_bits(val64);
819 ctx->ctx->divmul[1] = upper_32_bits(val64);
822 static void atom_op_nop(atom_exec_context *ctx, int *ptr, int arg)
827 static void atom_op_or(atom_exec_context *ctx, int *ptr, int arg)
829 uint8_t attr = U8((*ptr)++);
830 uint32_t dst, src, saved;
833 dst = atom_get_dst(ctx, arg, attr, ptr, &saved, 1);
835 src = atom_get_src(ctx, attr, ptr);
838 atom_put_dst(ctx, arg, attr, &dptr, dst, saved);
841 static void atom_op_postcard(atom_exec_context *ctx, int *ptr, int arg)
843 uint8_t val = U8((*ptr)++);
844 SDEBUG("POST card output: 0x%02X\n", val);
847 static void atom_op_repeat(atom_exec_context *ctx, int *ptr, int arg)
849 pr_info("unimplemented!\n");
852 static void atom_op_restorereg(atom_exec_context *ctx, int *ptr, int arg)
854 pr_info("unimplemented!\n");
857 static void atom_op_savereg(atom_exec_context *ctx, int *ptr, int arg)
859 pr_info("unimplemented!\n");
862 static void atom_op_setdatablock(atom_exec_context *ctx, int *ptr, int arg)
866 SDEBUG(" block: %d\n", idx);
868 ctx->ctx->data_block = 0;
870 ctx->ctx->data_block = ctx->start;
872 ctx->ctx->data_block = U16(ctx->ctx->data_table + 4 + 2 * idx);
873 SDEBUG(" base: 0x%04X\n", ctx->ctx->data_block);
876 static void atom_op_setfbbase(atom_exec_context *ctx, int *ptr, int arg)
878 uint8_t attr = U8((*ptr)++);
879 SDEBUG(" fb_base: ");
880 ctx->ctx->fb_base = atom_get_src(ctx, attr, ptr);
883 static void atom_op_setport(atom_exec_context *ctx, int *ptr, int arg)
889 if (port < ATOM_IO_NAMES_CNT)
890 SDEBUG(" port: %d (%s)\n", port, atom_io_names[port]);
892 SDEBUG(" port: %d\n", port);
894 ctx->ctx->io_mode = ATOM_IO_MM;
896 ctx->ctx->io_mode = ATOM_IO_IIO | port;
900 ctx->ctx->io_mode = ATOM_IO_PCI;
903 case ATOM_PORT_SYSIO:
904 ctx->ctx->io_mode = ATOM_IO_SYSIO;
910 static void atom_op_setregblock(atom_exec_context *ctx, int *ptr, int arg)
912 ctx->ctx->reg_block = U16(*ptr);
914 SDEBUG(" base: 0x%04X\n", ctx->ctx->reg_block);
917 static void atom_op_shift_left(atom_exec_context *ctx, int *ptr, int arg)
919 uint8_t attr = U8((*ptr)++), shift;
923 attr |= atom_def_dst[attr >> 3] << 6;
925 dst = atom_get_dst(ctx, arg, attr, ptr, &saved, 1);
926 shift = atom_get_src_direct(ctx, ATOM_SRC_BYTE0, ptr);
927 SDEBUG(" shift: %d\n", shift);
930 atom_put_dst(ctx, arg, attr, &dptr, dst, saved);
933 static void atom_op_shift_right(atom_exec_context *ctx, int *ptr, int arg)
935 uint8_t attr = U8((*ptr)++), shift;
939 attr |= atom_def_dst[attr >> 3] << 6;
941 dst = atom_get_dst(ctx, arg, attr, ptr, &saved, 1);
942 shift = atom_get_src_direct(ctx, ATOM_SRC_BYTE0, ptr);
943 SDEBUG(" shift: %d\n", shift);
946 atom_put_dst(ctx, arg, attr, &dptr, dst, saved);
949 static void atom_op_shl(atom_exec_context *ctx, int *ptr, int arg)
951 uint8_t attr = U8((*ptr)++), shift;
954 uint32_t dst_align = atom_dst_to_src[(attr >> 3) & 7][(attr >> 6) & 3];
956 dst = atom_get_dst(ctx, arg, attr, ptr, &saved, 1);
957 /* op needs to full dst value */
959 shift = atom_get_src(ctx, attr, ptr);
960 SDEBUG(" shift: %d\n", shift);
962 dst &= atom_arg_mask[dst_align];
963 dst >>= atom_arg_shift[dst_align];
965 atom_put_dst(ctx, arg, attr, &dptr, dst, saved);
968 static void atom_op_shr(atom_exec_context *ctx, int *ptr, int arg)
970 uint8_t attr = U8((*ptr)++), shift;
973 uint32_t dst_align = atom_dst_to_src[(attr >> 3) & 7][(attr >> 6) & 3];
975 dst = atom_get_dst(ctx, arg, attr, ptr, &saved, 1);
976 /* op needs to full dst value */
978 shift = atom_get_src(ctx, attr, ptr);
979 SDEBUG(" shift: %d\n", shift);
981 dst &= atom_arg_mask[dst_align];
982 dst >>= atom_arg_shift[dst_align];
984 atom_put_dst(ctx, arg, attr, &dptr, dst, saved);
987 static void atom_op_sub(atom_exec_context *ctx, int *ptr, int arg)
989 uint8_t attr = U8((*ptr)++);
990 uint32_t dst, src, saved;
993 dst = atom_get_dst(ctx, arg, attr, ptr, &saved, 1);
995 src = atom_get_src(ctx, attr, ptr);
998 atom_put_dst(ctx, arg, attr, &dptr, dst, saved);
1001 static void atom_op_switch(atom_exec_context *ctx, int *ptr, int arg)
1003 uint8_t attr = U8((*ptr)++);
1004 uint32_t src, val, target;
1005 SDEBUG(" switch: ");
1006 src = atom_get_src(ctx, attr, ptr);
1007 while (U16(*ptr) != ATOM_CASE_END)
1008 if (U8(*ptr) == ATOM_CASE_MAGIC) {
1012 atom_get_src(ctx, (attr & 0x38) | ATOM_ARG_IMM,
1016 SDEBUG(" target: %04X\n", target);
1017 *ptr = ctx->start + target;
1022 pr_info("Bad case\n");
1028 static void atom_op_test(atom_exec_context *ctx, int *ptr, int arg)
1030 uint8_t attr = U8((*ptr)++);
1033 dst = atom_get_dst(ctx, arg, attr, ptr, NULL, 1);
1035 src = atom_get_src(ctx, attr, ptr);
1036 ctx->ctx->cs_equal = ((dst & src) == 0);
1037 SDEBUG(" result: %s\n", ctx->ctx->cs_equal ? "EQ" : "NE");
1040 static void atom_op_xor(atom_exec_context *ctx, int *ptr, int arg)
1042 uint8_t attr = U8((*ptr)++);
1043 uint32_t dst, src, saved;
1046 dst = atom_get_dst(ctx, arg, attr, ptr, &saved, 1);
1048 src = atom_get_src(ctx, attr, ptr);
1051 atom_put_dst(ctx, arg, attr, &dptr, dst, saved);
1054 static void atom_op_debug(atom_exec_context *ctx, int *ptr, int arg)
1056 uint8_t val = U8((*ptr)++);
1057 SDEBUG("DEBUG output: 0x%02X\n", val);
1060 static void atom_op_processds(atom_exec_context *ctx, int *ptr, int arg)
1062 uint16_t val = U16(*ptr);
1064 SDEBUG("PROCESSDS output: 0x%02X\n", val);
1068 void (*func) (atom_exec_context *, int *, int);
1070 } opcode_table[ATOM_OP_CNT] = {
1073 atom_op_move, ATOM_ARG_REG}, {
1074 atom_op_move, ATOM_ARG_PS}, {
1075 atom_op_move, ATOM_ARG_WS}, {
1076 atom_op_move, ATOM_ARG_FB}, {
1077 atom_op_move, ATOM_ARG_PLL}, {
1078 atom_op_move, ATOM_ARG_MC}, {
1079 atom_op_and, ATOM_ARG_REG}, {
1080 atom_op_and, ATOM_ARG_PS}, {
1081 atom_op_and, ATOM_ARG_WS}, {
1082 atom_op_and, ATOM_ARG_FB}, {
1083 atom_op_and, ATOM_ARG_PLL}, {
1084 atom_op_and, ATOM_ARG_MC}, {
1085 atom_op_or, ATOM_ARG_REG}, {
1086 atom_op_or, ATOM_ARG_PS}, {
1087 atom_op_or, ATOM_ARG_WS}, {
1088 atom_op_or, ATOM_ARG_FB}, {
1089 atom_op_or, ATOM_ARG_PLL}, {
1090 atom_op_or, ATOM_ARG_MC}, {
1091 atom_op_shift_left, ATOM_ARG_REG}, {
1092 atom_op_shift_left, ATOM_ARG_PS}, {
1093 atom_op_shift_left, ATOM_ARG_WS}, {
1094 atom_op_shift_left, ATOM_ARG_FB}, {
1095 atom_op_shift_left, ATOM_ARG_PLL}, {
1096 atom_op_shift_left, ATOM_ARG_MC}, {
1097 atom_op_shift_right, ATOM_ARG_REG}, {
1098 atom_op_shift_right, ATOM_ARG_PS}, {
1099 atom_op_shift_right, ATOM_ARG_WS}, {
1100 atom_op_shift_right, ATOM_ARG_FB}, {
1101 atom_op_shift_right, ATOM_ARG_PLL}, {
1102 atom_op_shift_right, ATOM_ARG_MC}, {
1103 atom_op_mul, ATOM_ARG_REG}, {
1104 atom_op_mul, ATOM_ARG_PS}, {
1105 atom_op_mul, ATOM_ARG_WS}, {
1106 atom_op_mul, ATOM_ARG_FB}, {
1107 atom_op_mul, ATOM_ARG_PLL}, {
1108 atom_op_mul, ATOM_ARG_MC}, {
1109 atom_op_div, ATOM_ARG_REG}, {
1110 atom_op_div, ATOM_ARG_PS}, {
1111 atom_op_div, ATOM_ARG_WS}, {
1112 atom_op_div, ATOM_ARG_FB}, {
1113 atom_op_div, ATOM_ARG_PLL}, {
1114 atom_op_div, ATOM_ARG_MC}, {
1115 atom_op_add, ATOM_ARG_REG}, {
1116 atom_op_add, ATOM_ARG_PS}, {
1117 atom_op_add, ATOM_ARG_WS}, {
1118 atom_op_add, ATOM_ARG_FB}, {
1119 atom_op_add, ATOM_ARG_PLL}, {
1120 atom_op_add, ATOM_ARG_MC}, {
1121 atom_op_sub, ATOM_ARG_REG}, {
1122 atom_op_sub, ATOM_ARG_PS}, {
1123 atom_op_sub, ATOM_ARG_WS}, {
1124 atom_op_sub, ATOM_ARG_FB}, {
1125 atom_op_sub, ATOM_ARG_PLL}, {
1126 atom_op_sub, ATOM_ARG_MC}, {
1127 atom_op_setport, ATOM_PORT_ATI}, {
1128 atom_op_setport, ATOM_PORT_PCI}, {
1129 atom_op_setport, ATOM_PORT_SYSIO}, {
1130 atom_op_setregblock, 0}, {
1131 atom_op_setfbbase, 0}, {
1132 atom_op_compare, ATOM_ARG_REG}, {
1133 atom_op_compare, ATOM_ARG_PS}, {
1134 atom_op_compare, ATOM_ARG_WS}, {
1135 atom_op_compare, ATOM_ARG_FB}, {
1136 atom_op_compare, ATOM_ARG_PLL}, {
1137 atom_op_compare, ATOM_ARG_MC}, {
1138 atom_op_switch, 0}, {
1139 atom_op_jump, ATOM_COND_ALWAYS}, {
1140 atom_op_jump, ATOM_COND_EQUAL}, {
1141 atom_op_jump, ATOM_COND_BELOW}, {
1142 atom_op_jump, ATOM_COND_ABOVE}, {
1143 atom_op_jump, ATOM_COND_BELOWOREQUAL}, {
1144 atom_op_jump, ATOM_COND_ABOVEOREQUAL}, {
1145 atom_op_jump, ATOM_COND_NOTEQUAL}, {
1146 atom_op_test, ATOM_ARG_REG}, {
1147 atom_op_test, ATOM_ARG_PS}, {
1148 atom_op_test, ATOM_ARG_WS}, {
1149 atom_op_test, ATOM_ARG_FB}, {
1150 atom_op_test, ATOM_ARG_PLL}, {
1151 atom_op_test, ATOM_ARG_MC}, {
1152 atom_op_delay, ATOM_UNIT_MILLISEC}, {
1153 atom_op_delay, ATOM_UNIT_MICROSEC}, {
1154 atom_op_calltable, 0}, {
1155 atom_op_repeat, 0}, {
1156 atom_op_clear, ATOM_ARG_REG}, {
1157 atom_op_clear, ATOM_ARG_PS}, {
1158 atom_op_clear, ATOM_ARG_WS}, {
1159 atom_op_clear, ATOM_ARG_FB}, {
1160 atom_op_clear, ATOM_ARG_PLL}, {
1161 atom_op_clear, ATOM_ARG_MC}, {
1164 atom_op_mask, ATOM_ARG_REG}, {
1165 atom_op_mask, ATOM_ARG_PS}, {
1166 atom_op_mask, ATOM_ARG_WS}, {
1167 atom_op_mask, ATOM_ARG_FB}, {
1168 atom_op_mask, ATOM_ARG_PLL}, {
1169 atom_op_mask, ATOM_ARG_MC}, {
1170 atom_op_postcard, 0}, {
1172 atom_op_savereg, 0}, {
1173 atom_op_restorereg, 0}, {
1174 atom_op_setdatablock, 0}, {
1175 atom_op_xor, ATOM_ARG_REG}, {
1176 atom_op_xor, ATOM_ARG_PS}, {
1177 atom_op_xor, ATOM_ARG_WS}, {
1178 atom_op_xor, ATOM_ARG_FB}, {
1179 atom_op_xor, ATOM_ARG_PLL}, {
1180 atom_op_xor, ATOM_ARG_MC}, {
1181 atom_op_shl, ATOM_ARG_REG}, {
1182 atom_op_shl, ATOM_ARG_PS}, {
1183 atom_op_shl, ATOM_ARG_WS}, {
1184 atom_op_shl, ATOM_ARG_FB}, {
1185 atom_op_shl, ATOM_ARG_PLL}, {
1186 atom_op_shl, ATOM_ARG_MC}, {
1187 atom_op_shr, ATOM_ARG_REG}, {
1188 atom_op_shr, ATOM_ARG_PS}, {
1189 atom_op_shr, ATOM_ARG_WS}, {
1190 atom_op_shr, ATOM_ARG_FB}, {
1191 atom_op_shr, ATOM_ARG_PLL}, {
1192 atom_op_shr, ATOM_ARG_MC}, {
1193 atom_op_debug, 0}, {
1194 atom_op_processds, 0}, {
1195 atom_op_mul32, ATOM_ARG_PS}, {
1196 atom_op_mul32, ATOM_ARG_WS}, {
1197 atom_op_div32, ATOM_ARG_PS}, {
1198 atom_op_div32, ATOM_ARG_WS},
1201 static int amdgpu_atom_execute_table_locked(struct atom_context *ctx, int index, uint32_t * params)
1203 int base = CU16(ctx->cmd_table + 4 + 2 * index);
1204 int len, ws, ps, ptr;
1206 atom_exec_context ectx;
1212 len = CU16(base + ATOM_CT_SIZE_PTR);
1213 ws = CU8(base + ATOM_CT_WS_PTR);
1214 ps = CU8(base + ATOM_CT_PS_PTR) & ATOM_CT_PS_MASK;
1215 ptr = base + ATOM_CT_CODE_PTR;
1217 SDEBUG(">> execute %04X (len %d, WS %d, PS %d)\n", base, len, ws, ps);
1220 ectx.ps_shift = ps / 4;
1226 ectx.ws = kcalloc(4, ws, GFP_KERNEL);
1233 if (op < ATOM_OP_NAMES_CNT)
1234 SDEBUG("%s @ 0x%04X\n", atom_op_names[op], ptr - 1);
1236 SDEBUG("[%d] @ 0x%04X\n", op, ptr - 1);
1238 DRM_ERROR("atombios stuck executing %04X (len %d, WS %d, PS %d) @ 0x%04X\n",
1239 base, len, ws, ps, ptr - 1);
1244 if (op < ATOM_OP_CNT && op > 0)
1245 opcode_table[op].func(&ectx, &ptr,
1246 opcode_table[op].arg);
1250 if (op == ATOM_OP_EOT)
1262 int amdgpu_atom_execute_table(struct atom_context *ctx, int index, uint32_t * params)
1266 mutex_lock(&ctx->mutex);
1267 /* reset data block */
1268 ctx->data_block = 0;
1269 /* reset reg block */
1271 /* reset fb window */
1274 ctx->io_mode = ATOM_IO_MM;
1278 r = amdgpu_atom_execute_table_locked(ctx, index, params);
1279 mutex_unlock(&ctx->mutex);
1283 static int atom_iio_len[] = { 1, 2, 3, 3, 3, 3, 4, 4, 4, 3 };
1285 static void atom_index_iio(struct atom_context *ctx, int base)
1287 ctx->iio = kzalloc(2 * 256, GFP_KERNEL);
1290 while (CU8(base) == ATOM_IIO_START) {
1291 ctx->iio[CU8(base + 1)] = base + 2;
1293 while (CU8(base) != ATOM_IIO_END)
1294 base += atom_iio_len[CU8(base)];
1299 struct atom_context *amdgpu_atom_parse(struct card_info *card, void *bios)
1302 struct atom_context *ctx =
1303 kzalloc(sizeof(struct atom_context), GFP_KERNEL);
1313 if (CU16(0) != ATOM_BIOS_MAGIC) {
1314 pr_info("Invalid BIOS magic\n");
1319 (CSTR(ATOM_ATI_MAGIC_PTR), ATOM_ATI_MAGIC,
1320 strlen(ATOM_ATI_MAGIC))) {
1321 pr_info("Invalid ATI magic\n");
1326 base = CU16(ATOM_ROM_TABLE_PTR);
1328 (CSTR(base + ATOM_ROM_MAGIC_PTR), ATOM_ROM_MAGIC,
1329 strlen(ATOM_ROM_MAGIC))) {
1330 pr_info("Invalid ATOM magic\n");
1335 ctx->cmd_table = CU16(base + ATOM_ROM_CMD_PTR);
1336 ctx->data_table = CU16(base + ATOM_ROM_DATA_PTR);
1337 atom_index_iio(ctx, CU16(ctx->data_table + ATOM_DATA_IIO_PTR) + 4);
1339 amdgpu_atom_destroy(ctx);
1343 idx = CU16(ATOM_ROM_PART_NUMBER_PTR);
1349 pr_info("ATOM BIOS: %s\n", str);
1350 strlcpy(ctx->vbios_version, str, sizeof(ctx->vbios_version));
1357 int amdgpu_atom_asic_init(struct atom_context *ctx)
1359 int hwi = CU16(ctx->data_table + ATOM_DATA_FWI_PTR);
1365 ps[0] = cpu_to_le32(CU32(hwi + ATOM_FWI_DEFSCLK_PTR));
1366 ps[1] = cpu_to_le32(CU32(hwi + ATOM_FWI_DEFMCLK_PTR));
1367 if (!ps[0] || !ps[1])
1370 if (!CU16(ctx->cmd_table + 4 + 2 * ATOM_CMD_INIT))
1372 ret = amdgpu_atom_execute_table(ctx, ATOM_CMD_INIT, ps);
1381 void amdgpu_atom_destroy(struct atom_context *ctx)
1387 bool amdgpu_atom_parse_data_header(struct atom_context *ctx, int index,
1388 uint16_t * size, uint8_t * frev, uint8_t * crev,
1389 uint16_t * data_start)
1391 int offset = index * 2 + 4;
1392 int idx = CU16(ctx->data_table + offset);
1393 u16 *mdt = (u16 *)(ctx->bios + ctx->data_table + 4);
1401 *frev = CU8(idx + 2);
1403 *crev = CU8(idx + 3);
1408 bool amdgpu_atom_parse_cmd_header(struct atom_context *ctx, int index, uint8_t * frev,
1411 int offset = index * 2 + 4;
1412 int idx = CU16(ctx->cmd_table + offset);
1413 u16 *mct = (u16 *)(ctx->bios + ctx->cmd_table + 4);
1419 *frev = CU8(idx + 2);
1421 *crev = CU8(idx + 3);