2 * Copyright 2008 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
22 * Author: Stanislaw Skowronek
25 #include <linux/module.h>
26 #include <linux/sched.h>
27 #include <linux/slab.h>
28 #include <asm/unaligned.h>
30 #include <drm/drm_util.h>
34 #include "atomfirmware.h"
36 #include "atom-names.h"
37 #include "atom-bits.h"
40 #define ATOM_COND_ABOVE 0
41 #define ATOM_COND_ABOVEOREQUAL 1
42 #define ATOM_COND_ALWAYS 2
43 #define ATOM_COND_BELOW 3
44 #define ATOM_COND_BELOWOREQUAL 4
45 #define ATOM_COND_EQUAL 5
46 #define ATOM_COND_NOTEQUAL 6
48 #define ATOM_PORT_ATI 0
49 #define ATOM_PORT_PCI 1
50 #define ATOM_PORT_SYSIO 2
52 #define ATOM_UNIT_MICROSEC 0
53 #define ATOM_UNIT_MILLISEC 1
58 #define ATOM_CMD_TIMEOUT_SEC 20
61 struct atom_context *ctx;
66 unsigned long last_jump_jiffies;
70 int amdgpu_atom_debug;
71 static int amdgpu_atom_execute_table_locked(struct atom_context *ctx, int index, uint32_t *params);
72 int amdgpu_atom_execute_table(struct atom_context *ctx, int index, uint32_t *params);
74 static uint32_t atom_arg_mask[8] =
75 { 0xFFFFFFFF, 0xFFFF, 0xFFFF00, 0xFFFF0000, 0xFF, 0xFF00, 0xFF0000,
77 static int atom_arg_shift[8] = { 0, 0, 8, 16, 0, 8, 16, 24 };
79 static int atom_dst_to_src[8][4] = {
80 /* translate destination alignment field to the source alignment encoding */
90 static int atom_def_dst[8] = { 0, 0, 1, 2, 0, 1, 2, 3 };
92 static int debug_depth;
94 static void debug_print_spaces(int n)
100 #define DEBUG(...) do if (amdgpu_atom_debug) { printk(KERN_DEBUG __VA_ARGS__); } while (0)
101 #define SDEBUG(...) do if (amdgpu_atom_debug) { printk(KERN_DEBUG); debug_print_spaces(debug_depth); printk(__VA_ARGS__); } while (0)
103 #define DEBUG(...) do { } while (0)
104 #define SDEBUG(...) do { } while (0)
107 static uint32_t atom_iio_execute(struct atom_context *ctx, int base,
108 uint32_t index, uint32_t data)
110 uint32_t temp = 0xCDCDCDCD;
118 temp = ctx->card->reg_read(ctx->card, CU16(base + 1));
122 ctx->card->reg_write(ctx->card, CU16(base + 1), temp);
127 ~((0xFFFFFFFF >> (32 - CU8(base + 1))) <<
133 (0xFFFFFFFF >> (32 - CU8(base + 1))) << CU8(base +
137 case ATOM_IIO_MOVE_INDEX:
139 ~((0xFFFFFFFF >> (32 - CU8(base + 1))) <<
142 ((index >> CU8(base + 2)) &
143 (0xFFFFFFFF >> (32 - CU8(base + 1)))) << CU8(base +
147 case ATOM_IIO_MOVE_DATA:
149 ~((0xFFFFFFFF >> (32 - CU8(base + 1))) <<
152 ((data >> CU8(base + 2)) &
153 (0xFFFFFFFF >> (32 - CU8(base + 1)))) << CU8(base +
157 case ATOM_IIO_MOVE_ATTR:
159 ~((0xFFFFFFFF >> (32 - CU8(base + 1))) <<
163 io_attr >> CU8(base + 2)) & (0xFFFFFFFF >> (32 -
174 pr_info("Unknown IIO opcode\n");
179 static uint32_t atom_get_src_int(atom_exec_context *ctx, uint8_t attr,
180 int *ptr, uint32_t *saved, int print)
182 uint32_t idx, val = 0xCDCDCDCD, align, arg;
183 struct atom_context *gctx = ctx->ctx;
185 align = (attr >> 3) & 7;
191 DEBUG("REG[0x%04X]", idx);
192 idx += gctx->reg_block;
193 switch (gctx->io_mode) {
195 val = gctx->card->reg_read(gctx->card, idx);
198 pr_info("PCI registers are not implemented\n");
201 pr_info("SYSIO registers are not implemented\n");
204 if (!(gctx->io_mode & 0x80)) {
205 pr_info("Bad IO mode\n");
208 if (!gctx->iio[gctx->io_mode & 0x7F]) {
209 pr_info("Undefined indirect IO read method %d\n",
210 gctx->io_mode & 0x7F);
214 atom_iio_execute(gctx,
215 gctx->iio[gctx->io_mode & 0x7F],
222 /* get_unaligned_le32 avoids unaligned accesses from atombios
223 * tables, noticed on a DEC Alpha. */
224 val = get_unaligned_le32((u32 *)&ctx->ps[idx]);
226 DEBUG("PS[0x%02X,0x%04X]", idx, val);
232 DEBUG("WS[0x%02X]", idx);
234 case ATOM_WS_QUOTIENT:
235 val = gctx->divmul[0];
237 case ATOM_WS_REMAINDER:
238 val = gctx->divmul[1];
240 case ATOM_WS_DATAPTR:
241 val = gctx->data_block;
246 case ATOM_WS_OR_MASK:
247 val = 1 << gctx->shift;
249 case ATOM_WS_AND_MASK:
250 val = ~(1 << gctx->shift);
252 case ATOM_WS_FB_WINDOW:
255 case ATOM_WS_ATTRIBUTES:
259 val = gctx->reg_block;
269 if (gctx->data_block)
270 DEBUG("ID[0x%04X+%04X]", idx, gctx->data_block);
272 DEBUG("ID[0x%04X]", idx);
274 val = U32(idx + gctx->data_block);
279 if ((gctx->fb_base + (idx * 4)) > gctx->scratch_size_bytes) {
280 DRM_ERROR("ATOM: fb read beyond scratch region: %d vs. %d\n",
281 gctx->fb_base + (idx * 4), gctx->scratch_size_bytes);
284 val = gctx->scratch[(gctx->fb_base / 4) + idx];
286 DEBUG("FB[0x%02X]", idx);
294 DEBUG("IMM 0x%08X\n", val);
298 case ATOM_SRC_WORD16:
302 DEBUG("IMM 0x%04X\n", val);
306 case ATOM_SRC_BYTE16:
307 case ATOM_SRC_BYTE24:
311 DEBUG("IMM 0x%02X\n", val);
319 DEBUG("PLL[0x%02X]", idx);
320 val = gctx->card->pll_read(gctx->card, idx);
326 DEBUG("MC[0x%02X]", idx);
327 val = gctx->card->mc_read(gctx->card, idx);
332 val &= atom_arg_mask[align];
333 val >>= atom_arg_shift[align];
337 DEBUG(".[31:0] -> 0x%08X\n", val);
340 DEBUG(".[15:0] -> 0x%04X\n", val);
343 DEBUG(".[23:8] -> 0x%04X\n", val);
345 case ATOM_SRC_WORD16:
346 DEBUG(".[31:16] -> 0x%04X\n", val);
349 DEBUG(".[7:0] -> 0x%02X\n", val);
352 DEBUG(".[15:8] -> 0x%02X\n", val);
354 case ATOM_SRC_BYTE16:
355 DEBUG(".[23:16] -> 0x%02X\n", val);
357 case ATOM_SRC_BYTE24:
358 DEBUG(".[31:24] -> 0x%02X\n", val);
364 static void atom_skip_src_int(atom_exec_context *ctx, uint8_t attr, int *ptr)
366 uint32_t align = (attr >> 3) & 7, arg = attr & 7;
386 case ATOM_SRC_WORD16:
391 case ATOM_SRC_BYTE16:
392 case ATOM_SRC_BYTE24:
400 static uint32_t atom_get_src(atom_exec_context *ctx, uint8_t attr, int *ptr)
402 return atom_get_src_int(ctx, attr, ptr, NULL, 1);
405 static uint32_t atom_get_src_direct(atom_exec_context *ctx, uint8_t align, int *ptr)
407 uint32_t val = 0xCDCDCDCD;
416 case ATOM_SRC_WORD16:
422 case ATOM_SRC_BYTE16:
423 case ATOM_SRC_BYTE24:
431 static uint32_t atom_get_dst(atom_exec_context *ctx, int arg, uint8_t attr,
432 int *ptr, uint32_t *saved, int print)
434 return atom_get_src_int(ctx,
435 arg | atom_dst_to_src[(attr >> 3) &
436 7][(attr >> 6) & 3] << 3,
440 static void atom_skip_dst(atom_exec_context *ctx, int arg, uint8_t attr, int *ptr)
442 atom_skip_src_int(ctx,
443 arg | atom_dst_to_src[(attr >> 3) & 7][(attr >> 6) &
447 static void atom_put_dst(atom_exec_context *ctx, int arg, uint8_t attr,
448 int *ptr, uint32_t val, uint32_t saved)
451 atom_dst_to_src[(attr >> 3) & 7][(attr >> 6) & 3], old_val =
453 struct atom_context *gctx = ctx->ctx;
454 old_val &= atom_arg_mask[align] >> atom_arg_shift[align];
455 val <<= atom_arg_shift[align];
456 val &= atom_arg_mask[align];
457 saved &= ~atom_arg_mask[align];
463 DEBUG("REG[0x%04X]", idx);
464 idx += gctx->reg_block;
465 switch (gctx->io_mode) {
468 gctx->card->reg_write(gctx->card, idx,
471 gctx->card->reg_write(gctx->card, idx, val);
474 pr_info("PCI registers are not implemented\n");
477 pr_info("SYSIO registers are not implemented\n");
480 if (!(gctx->io_mode & 0x80)) {
481 pr_info("Bad IO mode\n");
484 if (!gctx->iio[gctx->io_mode & 0xFF]) {
485 pr_info("Undefined indirect IO write method %d\n",
486 gctx->io_mode & 0x7F);
489 atom_iio_execute(gctx, gctx->iio[gctx->io_mode & 0xFF],
496 DEBUG("PS[0x%02X]", idx);
497 ctx->ps[idx] = cpu_to_le32(val);
502 DEBUG("WS[0x%02X]", idx);
504 case ATOM_WS_QUOTIENT:
505 gctx->divmul[0] = val;
507 case ATOM_WS_REMAINDER:
508 gctx->divmul[1] = val;
510 case ATOM_WS_DATAPTR:
511 gctx->data_block = val;
516 case ATOM_WS_OR_MASK:
517 case ATOM_WS_AND_MASK:
519 case ATOM_WS_FB_WINDOW:
522 case ATOM_WS_ATTRIBUTES:
526 gctx->reg_block = val;
535 if ((gctx->fb_base + (idx * 4)) > gctx->scratch_size_bytes) {
536 DRM_ERROR("ATOM: fb write beyond scratch region: %d vs. %d\n",
537 gctx->fb_base + (idx * 4), gctx->scratch_size_bytes);
539 gctx->scratch[(gctx->fb_base / 4) + idx] = val;
540 DEBUG("FB[0x%02X]", idx);
545 DEBUG("PLL[0x%02X]", idx);
546 gctx->card->pll_write(gctx->card, idx, val);
551 DEBUG("MC[0x%02X]", idx);
552 gctx->card->mc_write(gctx->card, idx, val);
557 DEBUG(".[31:0] <- 0x%08X\n", old_val);
560 DEBUG(".[15:0] <- 0x%04X\n", old_val);
563 DEBUG(".[23:8] <- 0x%04X\n", old_val);
565 case ATOM_SRC_WORD16:
566 DEBUG(".[31:16] <- 0x%04X\n", old_val);
569 DEBUG(".[7:0] <- 0x%02X\n", old_val);
572 DEBUG(".[15:8] <- 0x%02X\n", old_val);
574 case ATOM_SRC_BYTE16:
575 DEBUG(".[23:16] <- 0x%02X\n", old_val);
577 case ATOM_SRC_BYTE24:
578 DEBUG(".[31:24] <- 0x%02X\n", old_val);
583 static void atom_op_add(atom_exec_context *ctx, int *ptr, int arg)
585 uint8_t attr = U8((*ptr)++);
586 uint32_t dst, src, saved;
589 dst = atom_get_dst(ctx, arg, attr, ptr, &saved, 1);
591 src = atom_get_src(ctx, attr, ptr);
594 atom_put_dst(ctx, arg, attr, &dptr, dst, saved);
597 static void atom_op_and(atom_exec_context *ctx, int *ptr, int arg)
599 uint8_t attr = U8((*ptr)++);
600 uint32_t dst, src, saved;
603 dst = atom_get_dst(ctx, arg, attr, ptr, &saved, 1);
605 src = atom_get_src(ctx, attr, ptr);
608 atom_put_dst(ctx, arg, attr, &dptr, dst, saved);
611 static void atom_op_beep(atom_exec_context *ctx, int *ptr, int arg)
613 printk("ATOM BIOS beeped!\n");
616 static void atom_op_calltable(atom_exec_context *ctx, int *ptr, int arg)
618 int idx = U8((*ptr)++);
621 if (idx < ATOM_TABLE_NAMES_CNT)
622 SDEBUG(" table: %d (%s)\n", idx, atom_table_names[idx]);
624 SDEBUG(" table: %d\n", idx);
625 if (U16(ctx->ctx->cmd_table + 4 + 2 * idx))
626 r = amdgpu_atom_execute_table_locked(ctx->ctx, idx, ctx->ps + ctx->ps_shift);
632 static void atom_op_clear(atom_exec_context *ctx, int *ptr, int arg)
634 uint8_t attr = U8((*ptr)++);
638 attr |= atom_def_dst[attr >> 3] << 6;
639 atom_get_dst(ctx, arg, attr, ptr, &saved, 0);
641 atom_put_dst(ctx, arg, attr, &dptr, 0, saved);
644 static void atom_op_compare(atom_exec_context *ctx, int *ptr, int arg)
646 uint8_t attr = U8((*ptr)++);
649 dst = atom_get_dst(ctx, arg, attr, ptr, NULL, 1);
651 src = atom_get_src(ctx, attr, ptr);
652 ctx->ctx->cs_equal = (dst == src);
653 ctx->ctx->cs_above = (dst > src);
654 SDEBUG(" result: %s %s\n", ctx->ctx->cs_equal ? "EQ" : "NE",
655 ctx->ctx->cs_above ? "GT" : "LE");
658 static void atom_op_delay(atom_exec_context *ctx, int *ptr, int arg)
660 unsigned count = U8((*ptr)++);
661 SDEBUG(" count: %d\n", count);
662 if (arg == ATOM_UNIT_MICROSEC)
664 else if (!drm_can_sleep())
670 static void atom_op_div(atom_exec_context *ctx, int *ptr, int arg)
672 uint8_t attr = U8((*ptr)++);
675 dst = atom_get_dst(ctx, arg, attr, ptr, NULL, 1);
677 src = atom_get_src(ctx, attr, ptr);
679 ctx->ctx->divmul[0] = dst / src;
680 ctx->ctx->divmul[1] = dst % src;
682 ctx->ctx->divmul[0] = 0;
683 ctx->ctx->divmul[1] = 0;
687 static void atom_op_div32(atom_exec_context *ctx, int *ptr, int arg)
690 uint8_t attr = U8((*ptr)++);
693 dst = atom_get_dst(ctx, arg, attr, ptr, NULL, 1);
695 src = atom_get_src(ctx, attr, ptr);
698 val64 |= ((uint64_t)ctx->ctx->divmul[1]) << 32;
700 ctx->ctx->divmul[0] = lower_32_bits(val64);
701 ctx->ctx->divmul[1] = upper_32_bits(val64);
703 ctx->ctx->divmul[0] = 0;
704 ctx->ctx->divmul[1] = 0;
708 static void atom_op_eot(atom_exec_context *ctx, int *ptr, int arg)
710 /* functionally, a nop */
713 static void atom_op_jump(atom_exec_context *ctx, int *ptr, int arg)
715 int execute = 0, target = U16(*ptr);
716 unsigned long cjiffies;
720 case ATOM_COND_ABOVE:
721 execute = ctx->ctx->cs_above;
723 case ATOM_COND_ABOVEOREQUAL:
724 execute = ctx->ctx->cs_above || ctx->ctx->cs_equal;
726 case ATOM_COND_ALWAYS:
729 case ATOM_COND_BELOW:
730 execute = !(ctx->ctx->cs_above || ctx->ctx->cs_equal);
732 case ATOM_COND_BELOWOREQUAL:
733 execute = !ctx->ctx->cs_above;
735 case ATOM_COND_EQUAL:
736 execute = ctx->ctx->cs_equal;
738 case ATOM_COND_NOTEQUAL:
739 execute = !ctx->ctx->cs_equal;
742 if (arg != ATOM_COND_ALWAYS)
743 SDEBUG(" taken: %s\n", execute ? "yes" : "no");
744 SDEBUG(" target: 0x%04X\n", target);
746 if (ctx->last_jump == (ctx->start + target)) {
748 if (time_after(cjiffies, ctx->last_jump_jiffies)) {
749 cjiffies -= ctx->last_jump_jiffies;
750 if ((jiffies_to_msecs(cjiffies) > ATOM_CMD_TIMEOUT_SEC*1000)) {
751 DRM_ERROR("atombios stuck in loop for more than %dsecs aborting\n",
752 ATOM_CMD_TIMEOUT_SEC);
756 /* jiffies wrap around we will just wait a little longer */
757 ctx->last_jump_jiffies = jiffies;
760 ctx->last_jump = ctx->start + target;
761 ctx->last_jump_jiffies = jiffies;
763 *ptr = ctx->start + target;
767 static void atom_op_mask(atom_exec_context *ctx, int *ptr, int arg)
769 uint8_t attr = U8((*ptr)++);
770 uint32_t dst, mask, src, saved;
773 dst = atom_get_dst(ctx, arg, attr, ptr, &saved, 1);
774 mask = atom_get_src_direct(ctx, ((attr >> 3) & 7), ptr);
775 SDEBUG(" mask: 0x%08x", mask);
777 src = atom_get_src(ctx, attr, ptr);
781 atom_put_dst(ctx, arg, attr, &dptr, dst, saved);
784 static void atom_op_move(atom_exec_context *ctx, int *ptr, int arg)
786 uint8_t attr = U8((*ptr)++);
789 if (((attr >> 3) & 7) != ATOM_SRC_DWORD)
790 atom_get_dst(ctx, arg, attr, ptr, &saved, 0);
792 atom_skip_dst(ctx, arg, attr, ptr);
796 src = atom_get_src(ctx, attr, ptr);
798 atom_put_dst(ctx, arg, attr, &dptr, src, saved);
801 static void atom_op_mul(atom_exec_context *ctx, int *ptr, int arg)
803 uint8_t attr = U8((*ptr)++);
806 dst = atom_get_dst(ctx, arg, attr, ptr, NULL, 1);
808 src = atom_get_src(ctx, attr, ptr);
809 ctx->ctx->divmul[0] = dst * src;
812 static void atom_op_mul32(atom_exec_context *ctx, int *ptr, int arg)
815 uint8_t attr = U8((*ptr)++);
818 dst = atom_get_dst(ctx, arg, attr, ptr, NULL, 1);
820 src = atom_get_src(ctx, attr, ptr);
821 val64 = (uint64_t)dst * (uint64_t)src;
822 ctx->ctx->divmul[0] = lower_32_bits(val64);
823 ctx->ctx->divmul[1] = upper_32_bits(val64);
826 static void atom_op_nop(atom_exec_context *ctx, int *ptr, int arg)
831 static void atom_op_or(atom_exec_context *ctx, int *ptr, int arg)
833 uint8_t attr = U8((*ptr)++);
834 uint32_t dst, src, saved;
837 dst = atom_get_dst(ctx, arg, attr, ptr, &saved, 1);
839 src = atom_get_src(ctx, attr, ptr);
842 atom_put_dst(ctx, arg, attr, &dptr, dst, saved);
845 static void atom_op_postcard(atom_exec_context *ctx, int *ptr, int arg)
847 uint8_t val = U8((*ptr)++);
848 SDEBUG("POST card output: 0x%02X\n", val);
851 static void atom_op_repeat(atom_exec_context *ctx, int *ptr, int arg)
853 pr_info("unimplemented!\n");
856 static void atom_op_restorereg(atom_exec_context *ctx, int *ptr, int arg)
858 pr_info("unimplemented!\n");
861 static void atom_op_savereg(atom_exec_context *ctx, int *ptr, int arg)
863 pr_info("unimplemented!\n");
866 static void atom_op_setdatablock(atom_exec_context *ctx, int *ptr, int arg)
870 SDEBUG(" block: %d\n", idx);
872 ctx->ctx->data_block = 0;
874 ctx->ctx->data_block = ctx->start;
876 ctx->ctx->data_block = U16(ctx->ctx->data_table + 4 + 2 * idx);
877 SDEBUG(" base: 0x%04X\n", ctx->ctx->data_block);
880 static void atom_op_setfbbase(atom_exec_context *ctx, int *ptr, int arg)
882 uint8_t attr = U8((*ptr)++);
883 SDEBUG(" fb_base: ");
884 ctx->ctx->fb_base = atom_get_src(ctx, attr, ptr);
887 static void atom_op_setport(atom_exec_context *ctx, int *ptr, int arg)
893 if (port < ATOM_IO_NAMES_CNT)
894 SDEBUG(" port: %d (%s)\n", port, atom_io_names[port]);
896 SDEBUG(" port: %d\n", port);
898 ctx->ctx->io_mode = ATOM_IO_MM;
900 ctx->ctx->io_mode = ATOM_IO_IIO | port;
904 ctx->ctx->io_mode = ATOM_IO_PCI;
907 case ATOM_PORT_SYSIO:
908 ctx->ctx->io_mode = ATOM_IO_SYSIO;
914 static void atom_op_setregblock(atom_exec_context *ctx, int *ptr, int arg)
916 ctx->ctx->reg_block = U16(*ptr);
918 SDEBUG(" base: 0x%04X\n", ctx->ctx->reg_block);
921 static void atom_op_shift_left(atom_exec_context *ctx, int *ptr, int arg)
923 uint8_t attr = U8((*ptr)++), shift;
927 attr |= atom_def_dst[attr >> 3] << 6;
929 dst = atom_get_dst(ctx, arg, attr, ptr, &saved, 1);
930 shift = atom_get_src_direct(ctx, ATOM_SRC_BYTE0, ptr);
931 SDEBUG(" shift: %d\n", shift);
934 atom_put_dst(ctx, arg, attr, &dptr, dst, saved);
937 static void atom_op_shift_right(atom_exec_context *ctx, int *ptr, int arg)
939 uint8_t attr = U8((*ptr)++), shift;
943 attr |= atom_def_dst[attr >> 3] << 6;
945 dst = atom_get_dst(ctx, arg, attr, ptr, &saved, 1);
946 shift = atom_get_src_direct(ctx, ATOM_SRC_BYTE0, ptr);
947 SDEBUG(" shift: %d\n", shift);
950 atom_put_dst(ctx, arg, attr, &dptr, dst, saved);
953 static void atom_op_shl(atom_exec_context *ctx, int *ptr, int arg)
955 uint8_t attr = U8((*ptr)++), shift;
958 uint32_t dst_align = atom_dst_to_src[(attr >> 3) & 7][(attr >> 6) & 3];
960 dst = atom_get_dst(ctx, arg, attr, ptr, &saved, 1);
961 /* op needs to full dst value */
963 shift = atom_get_src(ctx, attr, ptr);
964 SDEBUG(" shift: %d\n", shift);
966 dst &= atom_arg_mask[dst_align];
967 dst >>= atom_arg_shift[dst_align];
969 atom_put_dst(ctx, arg, attr, &dptr, dst, saved);
972 static void atom_op_shr(atom_exec_context *ctx, int *ptr, int arg)
974 uint8_t attr = U8((*ptr)++), shift;
977 uint32_t dst_align = atom_dst_to_src[(attr >> 3) & 7][(attr >> 6) & 3];
979 dst = atom_get_dst(ctx, arg, attr, ptr, &saved, 1);
980 /* op needs to full dst value */
982 shift = atom_get_src(ctx, attr, ptr);
983 SDEBUG(" shift: %d\n", shift);
985 dst &= atom_arg_mask[dst_align];
986 dst >>= atom_arg_shift[dst_align];
988 atom_put_dst(ctx, arg, attr, &dptr, dst, saved);
991 static void atom_op_sub(atom_exec_context *ctx, int *ptr, int arg)
993 uint8_t attr = U8((*ptr)++);
994 uint32_t dst, src, saved;
997 dst = atom_get_dst(ctx, arg, attr, ptr, &saved, 1);
999 src = atom_get_src(ctx, attr, ptr);
1002 atom_put_dst(ctx, arg, attr, &dptr, dst, saved);
1005 static void atom_op_switch(atom_exec_context *ctx, int *ptr, int arg)
1007 uint8_t attr = U8((*ptr)++);
1008 uint32_t src, val, target;
1009 SDEBUG(" switch: ");
1010 src = atom_get_src(ctx, attr, ptr);
1011 while (U16(*ptr) != ATOM_CASE_END)
1012 if (U8(*ptr) == ATOM_CASE_MAGIC) {
1016 atom_get_src(ctx, (attr & 0x38) | ATOM_ARG_IMM,
1020 SDEBUG(" target: %04X\n", target);
1021 *ptr = ctx->start + target;
1026 pr_info("Bad case\n");
1032 static void atom_op_test(atom_exec_context *ctx, int *ptr, int arg)
1034 uint8_t attr = U8((*ptr)++);
1037 dst = atom_get_dst(ctx, arg, attr, ptr, NULL, 1);
1039 src = atom_get_src(ctx, attr, ptr);
1040 ctx->ctx->cs_equal = ((dst & src) == 0);
1041 SDEBUG(" result: %s\n", ctx->ctx->cs_equal ? "EQ" : "NE");
1044 static void atom_op_xor(atom_exec_context *ctx, int *ptr, int arg)
1046 uint8_t attr = U8((*ptr)++);
1047 uint32_t dst, src, saved;
1050 dst = atom_get_dst(ctx, arg, attr, ptr, &saved, 1);
1052 src = atom_get_src(ctx, attr, ptr);
1055 atom_put_dst(ctx, arg, attr, &dptr, dst, saved);
1058 static void atom_op_debug(atom_exec_context *ctx, int *ptr, int arg)
1060 uint8_t val = U8((*ptr)++);
1061 SDEBUG("DEBUG output: 0x%02X\n", val);
1064 static void atom_op_processds(atom_exec_context *ctx, int *ptr, int arg)
1066 uint16_t val = U16(*ptr);
1068 SDEBUG("PROCESSDS output: 0x%02X\n", val);
1072 void (*func) (atom_exec_context *, int *, int);
1074 } opcode_table[ATOM_OP_CNT] = {
1077 atom_op_move, ATOM_ARG_REG}, {
1078 atom_op_move, ATOM_ARG_PS}, {
1079 atom_op_move, ATOM_ARG_WS}, {
1080 atom_op_move, ATOM_ARG_FB}, {
1081 atom_op_move, ATOM_ARG_PLL}, {
1082 atom_op_move, ATOM_ARG_MC}, {
1083 atom_op_and, ATOM_ARG_REG}, {
1084 atom_op_and, ATOM_ARG_PS}, {
1085 atom_op_and, ATOM_ARG_WS}, {
1086 atom_op_and, ATOM_ARG_FB}, {
1087 atom_op_and, ATOM_ARG_PLL}, {
1088 atom_op_and, ATOM_ARG_MC}, {
1089 atom_op_or, ATOM_ARG_REG}, {
1090 atom_op_or, ATOM_ARG_PS}, {
1091 atom_op_or, ATOM_ARG_WS}, {
1092 atom_op_or, ATOM_ARG_FB}, {
1093 atom_op_or, ATOM_ARG_PLL}, {
1094 atom_op_or, ATOM_ARG_MC}, {
1095 atom_op_shift_left, ATOM_ARG_REG}, {
1096 atom_op_shift_left, ATOM_ARG_PS}, {
1097 atom_op_shift_left, ATOM_ARG_WS}, {
1098 atom_op_shift_left, ATOM_ARG_FB}, {
1099 atom_op_shift_left, ATOM_ARG_PLL}, {
1100 atom_op_shift_left, ATOM_ARG_MC}, {
1101 atom_op_shift_right, ATOM_ARG_REG}, {
1102 atom_op_shift_right, ATOM_ARG_PS}, {
1103 atom_op_shift_right, ATOM_ARG_WS}, {
1104 atom_op_shift_right, ATOM_ARG_FB}, {
1105 atom_op_shift_right, ATOM_ARG_PLL}, {
1106 atom_op_shift_right, ATOM_ARG_MC}, {
1107 atom_op_mul, ATOM_ARG_REG}, {
1108 atom_op_mul, ATOM_ARG_PS}, {
1109 atom_op_mul, ATOM_ARG_WS}, {
1110 atom_op_mul, ATOM_ARG_FB}, {
1111 atom_op_mul, ATOM_ARG_PLL}, {
1112 atom_op_mul, ATOM_ARG_MC}, {
1113 atom_op_div, ATOM_ARG_REG}, {
1114 atom_op_div, ATOM_ARG_PS}, {
1115 atom_op_div, ATOM_ARG_WS}, {
1116 atom_op_div, ATOM_ARG_FB}, {
1117 atom_op_div, ATOM_ARG_PLL}, {
1118 atom_op_div, ATOM_ARG_MC}, {
1119 atom_op_add, ATOM_ARG_REG}, {
1120 atom_op_add, ATOM_ARG_PS}, {
1121 atom_op_add, ATOM_ARG_WS}, {
1122 atom_op_add, ATOM_ARG_FB}, {
1123 atom_op_add, ATOM_ARG_PLL}, {
1124 atom_op_add, ATOM_ARG_MC}, {
1125 atom_op_sub, ATOM_ARG_REG}, {
1126 atom_op_sub, ATOM_ARG_PS}, {
1127 atom_op_sub, ATOM_ARG_WS}, {
1128 atom_op_sub, ATOM_ARG_FB}, {
1129 atom_op_sub, ATOM_ARG_PLL}, {
1130 atom_op_sub, ATOM_ARG_MC}, {
1131 atom_op_setport, ATOM_PORT_ATI}, {
1132 atom_op_setport, ATOM_PORT_PCI}, {
1133 atom_op_setport, ATOM_PORT_SYSIO}, {
1134 atom_op_setregblock, 0}, {
1135 atom_op_setfbbase, 0}, {
1136 atom_op_compare, ATOM_ARG_REG}, {
1137 atom_op_compare, ATOM_ARG_PS}, {
1138 atom_op_compare, ATOM_ARG_WS}, {
1139 atom_op_compare, ATOM_ARG_FB}, {
1140 atom_op_compare, ATOM_ARG_PLL}, {
1141 atom_op_compare, ATOM_ARG_MC}, {
1142 atom_op_switch, 0}, {
1143 atom_op_jump, ATOM_COND_ALWAYS}, {
1144 atom_op_jump, ATOM_COND_EQUAL}, {
1145 atom_op_jump, ATOM_COND_BELOW}, {
1146 atom_op_jump, ATOM_COND_ABOVE}, {
1147 atom_op_jump, ATOM_COND_BELOWOREQUAL}, {
1148 atom_op_jump, ATOM_COND_ABOVEOREQUAL}, {
1149 atom_op_jump, ATOM_COND_NOTEQUAL}, {
1150 atom_op_test, ATOM_ARG_REG}, {
1151 atom_op_test, ATOM_ARG_PS}, {
1152 atom_op_test, ATOM_ARG_WS}, {
1153 atom_op_test, ATOM_ARG_FB}, {
1154 atom_op_test, ATOM_ARG_PLL}, {
1155 atom_op_test, ATOM_ARG_MC}, {
1156 atom_op_delay, ATOM_UNIT_MILLISEC}, {
1157 atom_op_delay, ATOM_UNIT_MICROSEC}, {
1158 atom_op_calltable, 0}, {
1159 atom_op_repeat, 0}, {
1160 atom_op_clear, ATOM_ARG_REG}, {
1161 atom_op_clear, ATOM_ARG_PS}, {
1162 atom_op_clear, ATOM_ARG_WS}, {
1163 atom_op_clear, ATOM_ARG_FB}, {
1164 atom_op_clear, ATOM_ARG_PLL}, {
1165 atom_op_clear, ATOM_ARG_MC}, {
1168 atom_op_mask, ATOM_ARG_REG}, {
1169 atom_op_mask, ATOM_ARG_PS}, {
1170 atom_op_mask, ATOM_ARG_WS}, {
1171 atom_op_mask, ATOM_ARG_FB}, {
1172 atom_op_mask, ATOM_ARG_PLL}, {
1173 atom_op_mask, ATOM_ARG_MC}, {
1174 atom_op_postcard, 0}, {
1176 atom_op_savereg, 0}, {
1177 atom_op_restorereg, 0}, {
1178 atom_op_setdatablock, 0}, {
1179 atom_op_xor, ATOM_ARG_REG}, {
1180 atom_op_xor, ATOM_ARG_PS}, {
1181 atom_op_xor, ATOM_ARG_WS}, {
1182 atom_op_xor, ATOM_ARG_FB}, {
1183 atom_op_xor, ATOM_ARG_PLL}, {
1184 atom_op_xor, ATOM_ARG_MC}, {
1185 atom_op_shl, ATOM_ARG_REG}, {
1186 atom_op_shl, ATOM_ARG_PS}, {
1187 atom_op_shl, ATOM_ARG_WS}, {
1188 atom_op_shl, ATOM_ARG_FB}, {
1189 atom_op_shl, ATOM_ARG_PLL}, {
1190 atom_op_shl, ATOM_ARG_MC}, {
1191 atom_op_shr, ATOM_ARG_REG}, {
1192 atom_op_shr, ATOM_ARG_PS}, {
1193 atom_op_shr, ATOM_ARG_WS}, {
1194 atom_op_shr, ATOM_ARG_FB}, {
1195 atom_op_shr, ATOM_ARG_PLL}, {
1196 atom_op_shr, ATOM_ARG_MC}, {
1197 atom_op_debug, 0}, {
1198 atom_op_processds, 0}, {
1199 atom_op_mul32, ATOM_ARG_PS}, {
1200 atom_op_mul32, ATOM_ARG_WS}, {
1201 atom_op_div32, ATOM_ARG_PS}, {
1202 atom_op_div32, ATOM_ARG_WS},
1205 static int amdgpu_atom_execute_table_locked(struct atom_context *ctx, int index, uint32_t *params)
1207 int base = CU16(ctx->cmd_table + 4 + 2 * index);
1208 int len, ws, ps, ptr;
1210 atom_exec_context ectx;
1216 len = CU16(base + ATOM_CT_SIZE_PTR);
1217 ws = CU8(base + ATOM_CT_WS_PTR);
1218 ps = CU8(base + ATOM_CT_PS_PTR) & ATOM_CT_PS_MASK;
1219 ptr = base + ATOM_CT_CODE_PTR;
1221 SDEBUG(">> execute %04X (len %d, WS %d, PS %d)\n", base, len, ws, ps);
1224 ectx.ps_shift = ps / 4;
1230 ectx.ws = kcalloc(4, ws, GFP_KERNEL);
1237 if (op < ATOM_OP_NAMES_CNT)
1238 SDEBUG("%s @ 0x%04X\n", atom_op_names[op], ptr - 1);
1240 SDEBUG("[%d] @ 0x%04X\n", op, ptr - 1);
1242 DRM_ERROR("atombios stuck executing %04X (len %d, WS %d, PS %d) @ 0x%04X\n",
1243 base, len, ws, ps, ptr - 1);
1248 if (op < ATOM_OP_CNT && op > 0)
1249 opcode_table[op].func(&ectx, &ptr,
1250 opcode_table[op].arg);
1254 if (op == ATOM_OP_EOT)
1266 int amdgpu_atom_execute_table(struct atom_context *ctx, int index, uint32_t *params)
1270 mutex_lock(&ctx->mutex);
1271 /* reset data block */
1272 ctx->data_block = 0;
1273 /* reset reg block */
1275 /* reset fb window */
1278 ctx->io_mode = ATOM_IO_MM;
1282 r = amdgpu_atom_execute_table_locked(ctx, index, params);
1283 mutex_unlock(&ctx->mutex);
1287 static int atom_iio_len[] = { 1, 2, 3, 3, 3, 3, 4, 4, 4, 3 };
1289 static void atom_index_iio(struct atom_context *ctx, int base)
1291 ctx->iio = kzalloc(2 * 256, GFP_KERNEL);
1294 while (CU8(base) == ATOM_IIO_START) {
1295 ctx->iio[CU8(base + 1)] = base + 2;
1297 while (CU8(base) != ATOM_IIO_END)
1298 base += atom_iio_len[CU8(base)];
1303 static void atom_get_vbios_name(struct atom_context *ctx)
1305 unsigned char *p_rom;
1306 unsigned char str_num;
1307 unsigned short off_to_vbios_str;
1308 unsigned char *c_ptr;
1312 const char *na = "--N/A--";
1317 str_num = *(p_rom + OFFSET_TO_GET_ATOMBIOS_NUMBER_OF_STRINGS);
1320 *(unsigned short *)(p_rom + OFFSET_TO_GET_ATOMBIOS_STRING_START);
1322 c_ptr = (unsigned char *)(p_rom + off_to_vbios_str);
1324 /* do not know where to find name */
1325 memcpy(ctx->name, na, 7);
1331 * skip the atombios strings, usually 4
1332 * 1st is P/N, 2nd is ASIC, 3rd is PCI type, 4th is Memory type
1334 for (i = 0; i < str_num; i++) {
1340 /* skip the following 2 chars: 0x0D 0x0A */
1343 name_size = strnlen(c_ptr, STRLEN_LONG - 1);
1344 memcpy(ctx->name, c_ptr, name_size);
1345 back = ctx->name + name_size;
1346 while ((*--back) == ' ')
1351 static void atom_get_vbios_date(struct atom_context *ctx)
1353 unsigned char *p_rom;
1354 unsigned char *date_in_rom;
1358 date_in_rom = p_rom + OFFSET_TO_VBIOS_DATE;
1362 ctx->date[2] = date_in_rom[6];
1363 ctx->date[3] = date_in_rom[7];
1365 ctx->date[5] = date_in_rom[0];
1366 ctx->date[6] = date_in_rom[1];
1368 ctx->date[8] = date_in_rom[3];
1369 ctx->date[9] = date_in_rom[4];
1370 ctx->date[10] = ' ';
1371 ctx->date[11] = date_in_rom[9];
1372 ctx->date[12] = date_in_rom[10];
1373 ctx->date[13] = date_in_rom[11];
1374 ctx->date[14] = date_in_rom[12];
1375 ctx->date[15] = date_in_rom[13];
1376 ctx->date[16] = '\0';
1379 static unsigned char *atom_find_str_in_rom(struct atom_context *ctx, char *str, int start,
1380 int end, int maxlen)
1382 unsigned long str_off;
1383 unsigned char *p_rom;
1384 unsigned short str_len;
1387 str_len = strnlen(str, maxlen);
1390 for (; start <= end; ++start) {
1391 for (str_off = 0; str_off < str_len; ++str_off) {
1392 if (str[str_off] != *(p_rom + start + str_off))
1396 if (str_off == str_len || str[str_off] == 0)
1397 return p_rom + start;
1402 static void atom_get_vbios_pn(struct atom_context *ctx)
1404 unsigned char *p_rom;
1405 unsigned short off_to_vbios_str;
1406 unsigned char *vbios_str;
1409 off_to_vbios_str = 0;
1412 if (*(p_rom + OFFSET_TO_GET_ATOMBIOS_NUMBER_OF_STRINGS) != 0) {
1414 *(unsigned short *)(p_rom + OFFSET_TO_GET_ATOMBIOS_STRING_START);
1416 vbios_str = (unsigned char *)(p_rom + off_to_vbios_str);
1418 vbios_str = p_rom + OFFSET_TO_VBIOS_PART_NUMBER;
1421 if (*vbios_str == 0) {
1422 vbios_str = atom_find_str_in_rom(ctx, BIOS_ATOM_PREFIX, 3, 1024, 64);
1423 if (vbios_str == NULL)
1424 vbios_str += sizeof(BIOS_ATOM_PREFIX) - 1;
1426 if (vbios_str != NULL && *vbios_str == 0)
1429 if (vbios_str != NULL) {
1431 while ((count < BIOS_STRING_LENGTH) && vbios_str[count] >= ' ' &&
1432 vbios_str[count] <= 'z') {
1433 ctx->vbios_pn[count] = vbios_str[count];
1437 ctx->vbios_pn[count] = 0;
1441 static void atom_get_vbios_version(struct atom_context *ctx)
1443 unsigned char *vbios_ver;
1445 /* find anchor ATOMBIOSBK-AMD */
1446 vbios_ver = atom_find_str_in_rom(ctx, BIOS_VERSION_PREFIX, 3, 1024, 64);
1447 if (vbios_ver != NULL) {
1448 /* skip ATOMBIOSBK-AMD VER */
1450 memcpy(ctx->vbios_ver_str, vbios_ver, STRLEN_NORMAL);
1452 ctx->vbios_ver_str[0] = '\0';
1456 struct atom_context *amdgpu_atom_parse(struct card_info *card, void *bios)
1459 struct atom_context *ctx =
1460 kzalloc(sizeof(struct atom_context), GFP_KERNEL);
1462 struct _ATOM_ROM_HEADER *atom_rom_header;
1463 struct _ATOM_MASTER_DATA_TABLE *master_table;
1464 struct _ATOM_FIRMWARE_INFO *atom_fw_info;
1473 if (CU16(0) != ATOM_BIOS_MAGIC) {
1474 pr_info("Invalid BIOS magic\n");
1479 (CSTR(ATOM_ATI_MAGIC_PTR), ATOM_ATI_MAGIC,
1480 strlen(ATOM_ATI_MAGIC))) {
1481 pr_info("Invalid ATI magic\n");
1486 base = CU16(ATOM_ROM_TABLE_PTR);
1488 (CSTR(base + ATOM_ROM_MAGIC_PTR), ATOM_ROM_MAGIC,
1489 strlen(ATOM_ROM_MAGIC))) {
1490 pr_info("Invalid ATOM magic\n");
1495 ctx->cmd_table = CU16(base + ATOM_ROM_CMD_PTR);
1496 ctx->data_table = CU16(base + ATOM_ROM_DATA_PTR);
1497 atom_index_iio(ctx, CU16(ctx->data_table + ATOM_DATA_IIO_PTR) + 4);
1499 amdgpu_atom_destroy(ctx);
1503 idx = CU16(ATOM_ROM_PART_NUMBER_PTR);
1509 pr_info("ATOM BIOS: %s\n", str);
1510 strlcpy(ctx->vbios_version, str, sizeof(ctx->vbios_version));
1513 atom_rom_header = (struct _ATOM_ROM_HEADER *)CSTR(base);
1514 if (atom_rom_header->usMasterDataTableOffset != 0) {
1515 master_table = (struct _ATOM_MASTER_DATA_TABLE *)
1516 CSTR(atom_rom_header->usMasterDataTableOffset);
1517 if (master_table->ListOfDataTables.FirmwareInfo != 0) {
1518 atom_fw_info = (struct _ATOM_FIRMWARE_INFO *)
1519 CSTR(master_table->ListOfDataTables.FirmwareInfo);
1520 ctx->version = atom_fw_info->ulFirmwareRevision;
1524 atom_get_vbios_name(ctx);
1525 atom_get_vbios_pn(ctx);
1526 atom_get_vbios_date(ctx);
1527 atom_get_vbios_version(ctx);
1532 int amdgpu_atom_asic_init(struct atom_context *ctx)
1534 int hwi = CU16(ctx->data_table + ATOM_DATA_FWI_PTR);
1540 ps[0] = cpu_to_le32(CU32(hwi + ATOM_FWI_DEFSCLK_PTR));
1541 ps[1] = cpu_to_le32(CU32(hwi + ATOM_FWI_DEFMCLK_PTR));
1542 if (!ps[0] || !ps[1])
1545 if (!CU16(ctx->cmd_table + 4 + 2 * ATOM_CMD_INIT))
1547 ret = amdgpu_atom_execute_table(ctx, ATOM_CMD_INIT, ps);
1556 void amdgpu_atom_destroy(struct atom_context *ctx)
1562 bool amdgpu_atom_parse_data_header(struct atom_context *ctx, int index,
1563 uint16_t *size, uint8_t *frev, uint8_t *crev,
1564 uint16_t *data_start)
1566 int offset = index * 2 + 4;
1567 int idx = CU16(ctx->data_table + offset);
1568 u16 *mdt = (u16 *)(ctx->bios + ctx->data_table + 4);
1576 *frev = CU8(idx + 2);
1578 *crev = CU8(idx + 3);
1583 bool amdgpu_atom_parse_cmd_header(struct atom_context *ctx, int index, uint8_t *frev,
1586 int offset = index * 2 + 4;
1587 int idx = CU16(ctx->cmd_table + offset);
1588 u16 *mct = (u16 *)(ctx->bios + ctx->cmd_table + 4);
1594 *frev = CU8(idx + 2);
1596 *crev = CU8(idx + 3);