2 * Copyright 2008 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
22 * Author: Stanislaw Skowronek
25 #include <linux/module.h>
26 #include <linux/sched.h>
27 #include <linux/slab.h>
28 #include <asm/unaligned.h>
30 #include <drm/drm_util.h>
35 #include "atom-names.h"
36 #include "atom-bits.h"
39 #define ATOM_COND_ABOVE 0
40 #define ATOM_COND_ABOVEOREQUAL 1
41 #define ATOM_COND_ALWAYS 2
42 #define ATOM_COND_BELOW 3
43 #define ATOM_COND_BELOWOREQUAL 4
44 #define ATOM_COND_EQUAL 5
45 #define ATOM_COND_NOTEQUAL 6
47 #define ATOM_PORT_ATI 0
48 #define ATOM_PORT_PCI 1
49 #define ATOM_PORT_SYSIO 2
51 #define ATOM_UNIT_MICROSEC 0
52 #define ATOM_UNIT_MILLISEC 1
57 #define ATOM_CMD_TIMEOUT_SEC 20
60 struct atom_context *ctx;
65 unsigned long last_jump_jiffies;
69 int amdgpu_atom_debug;
70 static int amdgpu_atom_execute_table_locked(struct atom_context *ctx, int index, uint32_t *params);
71 int amdgpu_atom_execute_table(struct atom_context *ctx, int index, uint32_t *params);
73 static uint32_t atom_arg_mask[8] =
74 { 0xFFFFFFFF, 0xFFFF, 0xFFFF00, 0xFFFF0000, 0xFF, 0xFF00, 0xFF0000,
76 static int atom_arg_shift[8] = { 0, 0, 8, 16, 0, 8, 16, 24 };
78 static int atom_dst_to_src[8][4] = {
79 /* translate destination alignment field to the source alignment encoding */
89 static int atom_def_dst[8] = { 0, 0, 1, 2, 0, 1, 2, 3 };
91 static int debug_depth;
93 static void debug_print_spaces(int n)
99 #define DEBUG(...) do if (amdgpu_atom_debug) { printk(KERN_DEBUG __VA_ARGS__); } while (0)
100 #define SDEBUG(...) do if (amdgpu_atom_debug) { printk(KERN_DEBUG); debug_print_spaces(debug_depth); printk(__VA_ARGS__); } while (0)
102 #define DEBUG(...) do { } while (0)
103 #define SDEBUG(...) do { } while (0)
106 static uint32_t atom_iio_execute(struct atom_context *ctx, int base,
107 uint32_t index, uint32_t data)
109 uint32_t temp = 0xCDCDCDCD;
117 temp = ctx->card->ioreg_read(ctx->card, CU16(base + 1));
121 ctx->card->ioreg_write(ctx->card, CU16(base + 1), temp);
126 ~((0xFFFFFFFF >> (32 - CU8(base + 1))) <<
132 (0xFFFFFFFF >> (32 - CU8(base + 1))) << CU8(base +
136 case ATOM_IIO_MOVE_INDEX:
138 ~((0xFFFFFFFF >> (32 - CU8(base + 1))) <<
141 ((index >> CU8(base + 2)) &
142 (0xFFFFFFFF >> (32 - CU8(base + 1)))) << CU8(base +
146 case ATOM_IIO_MOVE_DATA:
148 ~((0xFFFFFFFF >> (32 - CU8(base + 1))) <<
151 ((data >> CU8(base + 2)) &
152 (0xFFFFFFFF >> (32 - CU8(base + 1)))) << CU8(base +
156 case ATOM_IIO_MOVE_ATTR:
158 ~((0xFFFFFFFF >> (32 - CU8(base + 1))) <<
162 io_attr >> CU8(base + 2)) & (0xFFFFFFFF >> (32 -
173 pr_info("Unknown IIO opcode\n");
178 static uint32_t atom_get_src_int(atom_exec_context *ctx, uint8_t attr,
179 int *ptr, uint32_t *saved, int print)
181 uint32_t idx, val = 0xCDCDCDCD, align, arg;
182 struct atom_context *gctx = ctx->ctx;
184 align = (attr >> 3) & 7;
190 DEBUG("REG[0x%04X]", idx);
191 idx += gctx->reg_block;
192 switch (gctx->io_mode) {
194 val = gctx->card->reg_read(gctx->card, idx);
197 pr_info("PCI registers are not implemented\n");
200 pr_info("SYSIO registers are not implemented\n");
203 if (!(gctx->io_mode & 0x80)) {
204 pr_info("Bad IO mode\n");
207 if (!gctx->iio[gctx->io_mode & 0x7F]) {
208 pr_info("Undefined indirect IO read method %d\n",
209 gctx->io_mode & 0x7F);
213 atom_iio_execute(gctx,
214 gctx->iio[gctx->io_mode & 0x7F],
221 /* get_unaligned_le32 avoids unaligned accesses from atombios
222 * tables, noticed on a DEC Alpha. */
223 val = get_unaligned_le32((u32 *)&ctx->ps[idx]);
225 DEBUG("PS[0x%02X,0x%04X]", idx, val);
231 DEBUG("WS[0x%02X]", idx);
233 case ATOM_WS_QUOTIENT:
234 val = gctx->divmul[0];
236 case ATOM_WS_REMAINDER:
237 val = gctx->divmul[1];
239 case ATOM_WS_DATAPTR:
240 val = gctx->data_block;
245 case ATOM_WS_OR_MASK:
246 val = 1 << gctx->shift;
248 case ATOM_WS_AND_MASK:
249 val = ~(1 << gctx->shift);
251 case ATOM_WS_FB_WINDOW:
254 case ATOM_WS_ATTRIBUTES:
258 val = gctx->reg_block;
268 if (gctx->data_block)
269 DEBUG("ID[0x%04X+%04X]", idx, gctx->data_block);
271 DEBUG("ID[0x%04X]", idx);
273 val = U32(idx + gctx->data_block);
278 if ((gctx->fb_base + (idx * 4)) > gctx->scratch_size_bytes) {
279 DRM_ERROR("ATOM: fb read beyond scratch region: %d vs. %d\n",
280 gctx->fb_base + (idx * 4), gctx->scratch_size_bytes);
283 val = gctx->scratch[(gctx->fb_base / 4) + idx];
285 DEBUG("FB[0x%02X]", idx);
293 DEBUG("IMM 0x%08X\n", val);
297 case ATOM_SRC_WORD16:
301 DEBUG("IMM 0x%04X\n", val);
305 case ATOM_SRC_BYTE16:
306 case ATOM_SRC_BYTE24:
310 DEBUG("IMM 0x%02X\n", val);
318 DEBUG("PLL[0x%02X]", idx);
319 val = gctx->card->pll_read(gctx->card, idx);
325 DEBUG("MC[0x%02X]", idx);
326 val = gctx->card->mc_read(gctx->card, idx);
331 val &= atom_arg_mask[align];
332 val >>= atom_arg_shift[align];
336 DEBUG(".[31:0] -> 0x%08X\n", val);
339 DEBUG(".[15:0] -> 0x%04X\n", val);
342 DEBUG(".[23:8] -> 0x%04X\n", val);
344 case ATOM_SRC_WORD16:
345 DEBUG(".[31:16] -> 0x%04X\n", val);
348 DEBUG(".[7:0] -> 0x%02X\n", val);
351 DEBUG(".[15:8] -> 0x%02X\n", val);
353 case ATOM_SRC_BYTE16:
354 DEBUG(".[23:16] -> 0x%02X\n", val);
356 case ATOM_SRC_BYTE24:
357 DEBUG(".[31:24] -> 0x%02X\n", val);
363 static void atom_skip_src_int(atom_exec_context *ctx, uint8_t attr, int *ptr)
365 uint32_t align = (attr >> 3) & 7, arg = attr & 7;
385 case ATOM_SRC_WORD16:
390 case ATOM_SRC_BYTE16:
391 case ATOM_SRC_BYTE24:
399 static uint32_t atom_get_src(atom_exec_context *ctx, uint8_t attr, int *ptr)
401 return atom_get_src_int(ctx, attr, ptr, NULL, 1);
404 static uint32_t atom_get_src_direct(atom_exec_context *ctx, uint8_t align, int *ptr)
406 uint32_t val = 0xCDCDCDCD;
415 case ATOM_SRC_WORD16:
421 case ATOM_SRC_BYTE16:
422 case ATOM_SRC_BYTE24:
430 static uint32_t atom_get_dst(atom_exec_context *ctx, int arg, uint8_t attr,
431 int *ptr, uint32_t *saved, int print)
433 return atom_get_src_int(ctx,
434 arg | atom_dst_to_src[(attr >> 3) &
435 7][(attr >> 6) & 3] << 3,
439 static void atom_skip_dst(atom_exec_context *ctx, int arg, uint8_t attr, int *ptr)
441 atom_skip_src_int(ctx,
442 arg | atom_dst_to_src[(attr >> 3) & 7][(attr >> 6) &
446 static void atom_put_dst(atom_exec_context *ctx, int arg, uint8_t attr,
447 int *ptr, uint32_t val, uint32_t saved)
450 atom_dst_to_src[(attr >> 3) & 7][(attr >> 6) & 3], old_val =
452 struct atom_context *gctx = ctx->ctx;
453 old_val &= atom_arg_mask[align] >> atom_arg_shift[align];
454 val <<= atom_arg_shift[align];
455 val &= atom_arg_mask[align];
456 saved &= ~atom_arg_mask[align];
462 DEBUG("REG[0x%04X]", idx);
463 idx += gctx->reg_block;
464 switch (gctx->io_mode) {
467 gctx->card->reg_write(gctx->card, idx,
470 gctx->card->reg_write(gctx->card, idx, val);
473 pr_info("PCI registers are not implemented\n");
476 pr_info("SYSIO registers are not implemented\n");
479 if (!(gctx->io_mode & 0x80)) {
480 pr_info("Bad IO mode\n");
483 if (!gctx->iio[gctx->io_mode & 0xFF]) {
484 pr_info("Undefined indirect IO write method %d\n",
485 gctx->io_mode & 0x7F);
488 atom_iio_execute(gctx, gctx->iio[gctx->io_mode & 0xFF],
495 DEBUG("PS[0x%02X]", idx);
496 ctx->ps[idx] = cpu_to_le32(val);
501 DEBUG("WS[0x%02X]", idx);
503 case ATOM_WS_QUOTIENT:
504 gctx->divmul[0] = val;
506 case ATOM_WS_REMAINDER:
507 gctx->divmul[1] = val;
509 case ATOM_WS_DATAPTR:
510 gctx->data_block = val;
515 case ATOM_WS_OR_MASK:
516 case ATOM_WS_AND_MASK:
518 case ATOM_WS_FB_WINDOW:
521 case ATOM_WS_ATTRIBUTES:
525 gctx->reg_block = val;
534 if ((gctx->fb_base + (idx * 4)) > gctx->scratch_size_bytes) {
535 DRM_ERROR("ATOM: fb write beyond scratch region: %d vs. %d\n",
536 gctx->fb_base + (idx * 4), gctx->scratch_size_bytes);
538 gctx->scratch[(gctx->fb_base / 4) + idx] = val;
539 DEBUG("FB[0x%02X]", idx);
544 DEBUG("PLL[0x%02X]", idx);
545 gctx->card->pll_write(gctx->card, idx, val);
550 DEBUG("MC[0x%02X]", idx);
551 gctx->card->mc_write(gctx->card, idx, val);
556 DEBUG(".[31:0] <- 0x%08X\n", old_val);
559 DEBUG(".[15:0] <- 0x%04X\n", old_val);
562 DEBUG(".[23:8] <- 0x%04X\n", old_val);
564 case ATOM_SRC_WORD16:
565 DEBUG(".[31:16] <- 0x%04X\n", old_val);
568 DEBUG(".[7:0] <- 0x%02X\n", old_val);
571 DEBUG(".[15:8] <- 0x%02X\n", old_val);
573 case ATOM_SRC_BYTE16:
574 DEBUG(".[23:16] <- 0x%02X\n", old_val);
576 case ATOM_SRC_BYTE24:
577 DEBUG(".[31:24] <- 0x%02X\n", old_val);
582 static void atom_op_add(atom_exec_context *ctx, int *ptr, int arg)
584 uint8_t attr = U8((*ptr)++);
585 uint32_t dst, src, saved;
588 dst = atom_get_dst(ctx, arg, attr, ptr, &saved, 1);
590 src = atom_get_src(ctx, attr, ptr);
593 atom_put_dst(ctx, arg, attr, &dptr, dst, saved);
596 static void atom_op_and(atom_exec_context *ctx, int *ptr, int arg)
598 uint8_t attr = U8((*ptr)++);
599 uint32_t dst, src, saved;
602 dst = atom_get_dst(ctx, arg, attr, ptr, &saved, 1);
604 src = atom_get_src(ctx, attr, ptr);
607 atom_put_dst(ctx, arg, attr, &dptr, dst, saved);
610 static void atom_op_beep(atom_exec_context *ctx, int *ptr, int arg)
612 printk("ATOM BIOS beeped!\n");
615 static void atom_op_calltable(atom_exec_context *ctx, int *ptr, int arg)
617 int idx = U8((*ptr)++);
620 if (idx < ATOM_TABLE_NAMES_CNT)
621 SDEBUG(" table: %d (%s)\n", idx, atom_table_names[idx]);
623 SDEBUG(" table: %d\n", idx);
624 if (U16(ctx->ctx->cmd_table + 4 + 2 * idx))
625 r = amdgpu_atom_execute_table_locked(ctx->ctx, idx, ctx->ps + ctx->ps_shift);
631 static void atom_op_clear(atom_exec_context *ctx, int *ptr, int arg)
633 uint8_t attr = U8((*ptr)++);
637 attr |= atom_def_dst[attr >> 3] << 6;
638 atom_get_dst(ctx, arg, attr, ptr, &saved, 0);
640 atom_put_dst(ctx, arg, attr, &dptr, 0, saved);
643 static void atom_op_compare(atom_exec_context *ctx, int *ptr, int arg)
645 uint8_t attr = U8((*ptr)++);
648 dst = atom_get_dst(ctx, arg, attr, ptr, NULL, 1);
650 src = atom_get_src(ctx, attr, ptr);
651 ctx->ctx->cs_equal = (dst == src);
652 ctx->ctx->cs_above = (dst > src);
653 SDEBUG(" result: %s %s\n", ctx->ctx->cs_equal ? "EQ" : "NE",
654 ctx->ctx->cs_above ? "GT" : "LE");
657 static void atom_op_delay(atom_exec_context *ctx, int *ptr, int arg)
659 unsigned count = U8((*ptr)++);
660 SDEBUG(" count: %d\n", count);
661 if (arg == ATOM_UNIT_MICROSEC)
663 else if (!drm_can_sleep())
669 static void atom_op_div(atom_exec_context *ctx, int *ptr, int arg)
671 uint8_t attr = U8((*ptr)++);
674 dst = atom_get_dst(ctx, arg, attr, ptr, NULL, 1);
676 src = atom_get_src(ctx, attr, ptr);
678 ctx->ctx->divmul[0] = dst / src;
679 ctx->ctx->divmul[1] = dst % src;
681 ctx->ctx->divmul[0] = 0;
682 ctx->ctx->divmul[1] = 0;
686 static void atom_op_div32(atom_exec_context *ctx, int *ptr, int arg)
689 uint8_t attr = U8((*ptr)++);
692 dst = atom_get_dst(ctx, arg, attr, ptr, NULL, 1);
694 src = atom_get_src(ctx, attr, ptr);
697 val64 |= ((uint64_t)ctx->ctx->divmul[1]) << 32;
699 ctx->ctx->divmul[0] = lower_32_bits(val64);
700 ctx->ctx->divmul[1] = upper_32_bits(val64);
702 ctx->ctx->divmul[0] = 0;
703 ctx->ctx->divmul[1] = 0;
707 static void atom_op_eot(atom_exec_context *ctx, int *ptr, int arg)
709 /* functionally, a nop */
712 static void atom_op_jump(atom_exec_context *ctx, int *ptr, int arg)
714 int execute = 0, target = U16(*ptr);
715 unsigned long cjiffies;
719 case ATOM_COND_ABOVE:
720 execute = ctx->ctx->cs_above;
722 case ATOM_COND_ABOVEOREQUAL:
723 execute = ctx->ctx->cs_above || ctx->ctx->cs_equal;
725 case ATOM_COND_ALWAYS:
728 case ATOM_COND_BELOW:
729 execute = !(ctx->ctx->cs_above || ctx->ctx->cs_equal);
731 case ATOM_COND_BELOWOREQUAL:
732 execute = !ctx->ctx->cs_above;
734 case ATOM_COND_EQUAL:
735 execute = ctx->ctx->cs_equal;
737 case ATOM_COND_NOTEQUAL:
738 execute = !ctx->ctx->cs_equal;
741 if (arg != ATOM_COND_ALWAYS)
742 SDEBUG(" taken: %s\n", execute ? "yes" : "no");
743 SDEBUG(" target: 0x%04X\n", target);
745 if (ctx->last_jump == (ctx->start + target)) {
747 if (time_after(cjiffies, ctx->last_jump_jiffies)) {
748 cjiffies -= ctx->last_jump_jiffies;
749 if ((jiffies_to_msecs(cjiffies) > ATOM_CMD_TIMEOUT_SEC*1000)) {
750 DRM_ERROR("atombios stuck in loop for more than %dsecs aborting\n",
751 ATOM_CMD_TIMEOUT_SEC);
755 /* jiffies wrap around we will just wait a little longer */
756 ctx->last_jump_jiffies = jiffies;
759 ctx->last_jump = ctx->start + target;
760 ctx->last_jump_jiffies = jiffies;
762 *ptr = ctx->start + target;
766 static void atom_op_mask(atom_exec_context *ctx, int *ptr, int arg)
768 uint8_t attr = U8((*ptr)++);
769 uint32_t dst, mask, src, saved;
772 dst = atom_get_dst(ctx, arg, attr, ptr, &saved, 1);
773 mask = atom_get_src_direct(ctx, ((attr >> 3) & 7), ptr);
774 SDEBUG(" mask: 0x%08x", mask);
776 src = atom_get_src(ctx, attr, ptr);
780 atom_put_dst(ctx, arg, attr, &dptr, dst, saved);
783 static void atom_op_move(atom_exec_context *ctx, int *ptr, int arg)
785 uint8_t attr = U8((*ptr)++);
788 if (((attr >> 3) & 7) != ATOM_SRC_DWORD)
789 atom_get_dst(ctx, arg, attr, ptr, &saved, 0);
791 atom_skip_dst(ctx, arg, attr, ptr);
795 src = atom_get_src(ctx, attr, ptr);
797 atom_put_dst(ctx, arg, attr, &dptr, src, saved);
800 static void atom_op_mul(atom_exec_context *ctx, int *ptr, int arg)
802 uint8_t attr = U8((*ptr)++);
805 dst = atom_get_dst(ctx, arg, attr, ptr, NULL, 1);
807 src = atom_get_src(ctx, attr, ptr);
808 ctx->ctx->divmul[0] = dst * src;
811 static void atom_op_mul32(atom_exec_context *ctx, int *ptr, int arg)
814 uint8_t attr = U8((*ptr)++);
817 dst = atom_get_dst(ctx, arg, attr, ptr, NULL, 1);
819 src = atom_get_src(ctx, attr, ptr);
820 val64 = (uint64_t)dst * (uint64_t)src;
821 ctx->ctx->divmul[0] = lower_32_bits(val64);
822 ctx->ctx->divmul[1] = upper_32_bits(val64);
825 static void atom_op_nop(atom_exec_context *ctx, int *ptr, int arg)
830 static void atom_op_or(atom_exec_context *ctx, int *ptr, int arg)
832 uint8_t attr = U8((*ptr)++);
833 uint32_t dst, src, saved;
836 dst = atom_get_dst(ctx, arg, attr, ptr, &saved, 1);
838 src = atom_get_src(ctx, attr, ptr);
841 atom_put_dst(ctx, arg, attr, &dptr, dst, saved);
844 static void atom_op_postcard(atom_exec_context *ctx, int *ptr, int arg)
846 uint8_t val = U8((*ptr)++);
847 SDEBUG("POST card output: 0x%02X\n", val);
850 static void atom_op_repeat(atom_exec_context *ctx, int *ptr, int arg)
852 pr_info("unimplemented!\n");
855 static void atom_op_restorereg(atom_exec_context *ctx, int *ptr, int arg)
857 pr_info("unimplemented!\n");
860 static void atom_op_savereg(atom_exec_context *ctx, int *ptr, int arg)
862 pr_info("unimplemented!\n");
865 static void atom_op_setdatablock(atom_exec_context *ctx, int *ptr, int arg)
869 SDEBUG(" block: %d\n", idx);
871 ctx->ctx->data_block = 0;
873 ctx->ctx->data_block = ctx->start;
875 ctx->ctx->data_block = U16(ctx->ctx->data_table + 4 + 2 * idx);
876 SDEBUG(" base: 0x%04X\n", ctx->ctx->data_block);
879 static void atom_op_setfbbase(atom_exec_context *ctx, int *ptr, int arg)
881 uint8_t attr = U8((*ptr)++);
882 SDEBUG(" fb_base: ");
883 ctx->ctx->fb_base = atom_get_src(ctx, attr, ptr);
886 static void atom_op_setport(atom_exec_context *ctx, int *ptr, int arg)
892 if (port < ATOM_IO_NAMES_CNT)
893 SDEBUG(" port: %d (%s)\n", port, atom_io_names[port]);
895 SDEBUG(" port: %d\n", port);
897 ctx->ctx->io_mode = ATOM_IO_MM;
899 ctx->ctx->io_mode = ATOM_IO_IIO | port;
903 ctx->ctx->io_mode = ATOM_IO_PCI;
906 case ATOM_PORT_SYSIO:
907 ctx->ctx->io_mode = ATOM_IO_SYSIO;
913 static void atom_op_setregblock(atom_exec_context *ctx, int *ptr, int arg)
915 ctx->ctx->reg_block = U16(*ptr);
917 SDEBUG(" base: 0x%04X\n", ctx->ctx->reg_block);
920 static void atom_op_shift_left(atom_exec_context *ctx, int *ptr, int arg)
922 uint8_t attr = U8((*ptr)++), shift;
926 attr |= atom_def_dst[attr >> 3] << 6;
928 dst = atom_get_dst(ctx, arg, attr, ptr, &saved, 1);
929 shift = atom_get_src_direct(ctx, ATOM_SRC_BYTE0, ptr);
930 SDEBUG(" shift: %d\n", shift);
933 atom_put_dst(ctx, arg, attr, &dptr, dst, saved);
936 static void atom_op_shift_right(atom_exec_context *ctx, int *ptr, int arg)
938 uint8_t attr = U8((*ptr)++), shift;
942 attr |= atom_def_dst[attr >> 3] << 6;
944 dst = atom_get_dst(ctx, arg, attr, ptr, &saved, 1);
945 shift = atom_get_src_direct(ctx, ATOM_SRC_BYTE0, ptr);
946 SDEBUG(" shift: %d\n", shift);
949 atom_put_dst(ctx, arg, attr, &dptr, dst, saved);
952 static void atom_op_shl(atom_exec_context *ctx, int *ptr, int arg)
954 uint8_t attr = U8((*ptr)++), shift;
957 uint32_t dst_align = atom_dst_to_src[(attr >> 3) & 7][(attr >> 6) & 3];
959 dst = atom_get_dst(ctx, arg, attr, ptr, &saved, 1);
960 /* op needs to full dst value */
962 shift = atom_get_src(ctx, attr, ptr);
963 SDEBUG(" shift: %d\n", shift);
965 dst &= atom_arg_mask[dst_align];
966 dst >>= atom_arg_shift[dst_align];
968 atom_put_dst(ctx, arg, attr, &dptr, dst, saved);
971 static void atom_op_shr(atom_exec_context *ctx, int *ptr, int arg)
973 uint8_t attr = U8((*ptr)++), shift;
976 uint32_t dst_align = atom_dst_to_src[(attr >> 3) & 7][(attr >> 6) & 3];
978 dst = atom_get_dst(ctx, arg, attr, ptr, &saved, 1);
979 /* op needs to full dst value */
981 shift = atom_get_src(ctx, attr, ptr);
982 SDEBUG(" shift: %d\n", shift);
984 dst &= atom_arg_mask[dst_align];
985 dst >>= atom_arg_shift[dst_align];
987 atom_put_dst(ctx, arg, attr, &dptr, dst, saved);
990 static void atom_op_sub(atom_exec_context *ctx, int *ptr, int arg)
992 uint8_t attr = U8((*ptr)++);
993 uint32_t dst, src, saved;
996 dst = atom_get_dst(ctx, arg, attr, ptr, &saved, 1);
998 src = atom_get_src(ctx, attr, ptr);
1001 atom_put_dst(ctx, arg, attr, &dptr, dst, saved);
1004 static void atom_op_switch(atom_exec_context *ctx, int *ptr, int arg)
1006 uint8_t attr = U8((*ptr)++);
1007 uint32_t src, val, target;
1008 SDEBUG(" switch: ");
1009 src = atom_get_src(ctx, attr, ptr);
1010 while (U16(*ptr) != ATOM_CASE_END)
1011 if (U8(*ptr) == ATOM_CASE_MAGIC) {
1015 atom_get_src(ctx, (attr & 0x38) | ATOM_ARG_IMM,
1019 SDEBUG(" target: %04X\n", target);
1020 *ptr = ctx->start + target;
1025 pr_info("Bad case\n");
1031 static void atom_op_test(atom_exec_context *ctx, int *ptr, int arg)
1033 uint8_t attr = U8((*ptr)++);
1036 dst = atom_get_dst(ctx, arg, attr, ptr, NULL, 1);
1038 src = atom_get_src(ctx, attr, ptr);
1039 ctx->ctx->cs_equal = ((dst & src) == 0);
1040 SDEBUG(" result: %s\n", ctx->ctx->cs_equal ? "EQ" : "NE");
1043 static void atom_op_xor(atom_exec_context *ctx, int *ptr, int arg)
1045 uint8_t attr = U8((*ptr)++);
1046 uint32_t dst, src, saved;
1049 dst = atom_get_dst(ctx, arg, attr, ptr, &saved, 1);
1051 src = atom_get_src(ctx, attr, ptr);
1054 atom_put_dst(ctx, arg, attr, &dptr, dst, saved);
1057 static void atom_op_debug(atom_exec_context *ctx, int *ptr, int arg)
1059 uint8_t val = U8((*ptr)++);
1060 SDEBUG("DEBUG output: 0x%02X\n", val);
1063 static void atom_op_processds(atom_exec_context *ctx, int *ptr, int arg)
1065 uint16_t val = U16(*ptr);
1067 SDEBUG("PROCESSDS output: 0x%02X\n", val);
1071 void (*func) (atom_exec_context *, int *, int);
1073 } opcode_table[ATOM_OP_CNT] = {
1076 atom_op_move, ATOM_ARG_REG}, {
1077 atom_op_move, ATOM_ARG_PS}, {
1078 atom_op_move, ATOM_ARG_WS}, {
1079 atom_op_move, ATOM_ARG_FB}, {
1080 atom_op_move, ATOM_ARG_PLL}, {
1081 atom_op_move, ATOM_ARG_MC}, {
1082 atom_op_and, ATOM_ARG_REG}, {
1083 atom_op_and, ATOM_ARG_PS}, {
1084 atom_op_and, ATOM_ARG_WS}, {
1085 atom_op_and, ATOM_ARG_FB}, {
1086 atom_op_and, ATOM_ARG_PLL}, {
1087 atom_op_and, ATOM_ARG_MC}, {
1088 atom_op_or, ATOM_ARG_REG}, {
1089 atom_op_or, ATOM_ARG_PS}, {
1090 atom_op_or, ATOM_ARG_WS}, {
1091 atom_op_or, ATOM_ARG_FB}, {
1092 atom_op_or, ATOM_ARG_PLL}, {
1093 atom_op_or, ATOM_ARG_MC}, {
1094 atom_op_shift_left, ATOM_ARG_REG}, {
1095 atom_op_shift_left, ATOM_ARG_PS}, {
1096 atom_op_shift_left, ATOM_ARG_WS}, {
1097 atom_op_shift_left, ATOM_ARG_FB}, {
1098 atom_op_shift_left, ATOM_ARG_PLL}, {
1099 atom_op_shift_left, ATOM_ARG_MC}, {
1100 atom_op_shift_right, ATOM_ARG_REG}, {
1101 atom_op_shift_right, ATOM_ARG_PS}, {
1102 atom_op_shift_right, ATOM_ARG_WS}, {
1103 atom_op_shift_right, ATOM_ARG_FB}, {
1104 atom_op_shift_right, ATOM_ARG_PLL}, {
1105 atom_op_shift_right, ATOM_ARG_MC}, {
1106 atom_op_mul, ATOM_ARG_REG}, {
1107 atom_op_mul, ATOM_ARG_PS}, {
1108 atom_op_mul, ATOM_ARG_WS}, {
1109 atom_op_mul, ATOM_ARG_FB}, {
1110 atom_op_mul, ATOM_ARG_PLL}, {
1111 atom_op_mul, ATOM_ARG_MC}, {
1112 atom_op_div, ATOM_ARG_REG}, {
1113 atom_op_div, ATOM_ARG_PS}, {
1114 atom_op_div, ATOM_ARG_WS}, {
1115 atom_op_div, ATOM_ARG_FB}, {
1116 atom_op_div, ATOM_ARG_PLL}, {
1117 atom_op_div, ATOM_ARG_MC}, {
1118 atom_op_add, ATOM_ARG_REG}, {
1119 atom_op_add, ATOM_ARG_PS}, {
1120 atom_op_add, ATOM_ARG_WS}, {
1121 atom_op_add, ATOM_ARG_FB}, {
1122 atom_op_add, ATOM_ARG_PLL}, {
1123 atom_op_add, ATOM_ARG_MC}, {
1124 atom_op_sub, ATOM_ARG_REG}, {
1125 atom_op_sub, ATOM_ARG_PS}, {
1126 atom_op_sub, ATOM_ARG_WS}, {
1127 atom_op_sub, ATOM_ARG_FB}, {
1128 atom_op_sub, ATOM_ARG_PLL}, {
1129 atom_op_sub, ATOM_ARG_MC}, {
1130 atom_op_setport, ATOM_PORT_ATI}, {
1131 atom_op_setport, ATOM_PORT_PCI}, {
1132 atom_op_setport, ATOM_PORT_SYSIO}, {
1133 atom_op_setregblock, 0}, {
1134 atom_op_setfbbase, 0}, {
1135 atom_op_compare, ATOM_ARG_REG}, {
1136 atom_op_compare, ATOM_ARG_PS}, {
1137 atom_op_compare, ATOM_ARG_WS}, {
1138 atom_op_compare, ATOM_ARG_FB}, {
1139 atom_op_compare, ATOM_ARG_PLL}, {
1140 atom_op_compare, ATOM_ARG_MC}, {
1141 atom_op_switch, 0}, {
1142 atom_op_jump, ATOM_COND_ALWAYS}, {
1143 atom_op_jump, ATOM_COND_EQUAL}, {
1144 atom_op_jump, ATOM_COND_BELOW}, {
1145 atom_op_jump, ATOM_COND_ABOVE}, {
1146 atom_op_jump, ATOM_COND_BELOWOREQUAL}, {
1147 atom_op_jump, ATOM_COND_ABOVEOREQUAL}, {
1148 atom_op_jump, ATOM_COND_NOTEQUAL}, {
1149 atom_op_test, ATOM_ARG_REG}, {
1150 atom_op_test, ATOM_ARG_PS}, {
1151 atom_op_test, ATOM_ARG_WS}, {
1152 atom_op_test, ATOM_ARG_FB}, {
1153 atom_op_test, ATOM_ARG_PLL}, {
1154 atom_op_test, ATOM_ARG_MC}, {
1155 atom_op_delay, ATOM_UNIT_MILLISEC}, {
1156 atom_op_delay, ATOM_UNIT_MICROSEC}, {
1157 atom_op_calltable, 0}, {
1158 atom_op_repeat, 0}, {
1159 atom_op_clear, ATOM_ARG_REG}, {
1160 atom_op_clear, ATOM_ARG_PS}, {
1161 atom_op_clear, ATOM_ARG_WS}, {
1162 atom_op_clear, ATOM_ARG_FB}, {
1163 atom_op_clear, ATOM_ARG_PLL}, {
1164 atom_op_clear, ATOM_ARG_MC}, {
1167 atom_op_mask, ATOM_ARG_REG}, {
1168 atom_op_mask, ATOM_ARG_PS}, {
1169 atom_op_mask, ATOM_ARG_WS}, {
1170 atom_op_mask, ATOM_ARG_FB}, {
1171 atom_op_mask, ATOM_ARG_PLL}, {
1172 atom_op_mask, ATOM_ARG_MC}, {
1173 atom_op_postcard, 0}, {
1175 atom_op_savereg, 0}, {
1176 atom_op_restorereg, 0}, {
1177 atom_op_setdatablock, 0}, {
1178 atom_op_xor, ATOM_ARG_REG}, {
1179 atom_op_xor, ATOM_ARG_PS}, {
1180 atom_op_xor, ATOM_ARG_WS}, {
1181 atom_op_xor, ATOM_ARG_FB}, {
1182 atom_op_xor, ATOM_ARG_PLL}, {
1183 atom_op_xor, ATOM_ARG_MC}, {
1184 atom_op_shl, ATOM_ARG_REG}, {
1185 atom_op_shl, ATOM_ARG_PS}, {
1186 atom_op_shl, ATOM_ARG_WS}, {
1187 atom_op_shl, ATOM_ARG_FB}, {
1188 atom_op_shl, ATOM_ARG_PLL}, {
1189 atom_op_shl, ATOM_ARG_MC}, {
1190 atom_op_shr, ATOM_ARG_REG}, {
1191 atom_op_shr, ATOM_ARG_PS}, {
1192 atom_op_shr, ATOM_ARG_WS}, {
1193 atom_op_shr, ATOM_ARG_FB}, {
1194 atom_op_shr, ATOM_ARG_PLL}, {
1195 atom_op_shr, ATOM_ARG_MC}, {
1196 atom_op_debug, 0}, {
1197 atom_op_processds, 0}, {
1198 atom_op_mul32, ATOM_ARG_PS}, {
1199 atom_op_mul32, ATOM_ARG_WS}, {
1200 atom_op_div32, ATOM_ARG_PS}, {
1201 atom_op_div32, ATOM_ARG_WS},
1204 static int amdgpu_atom_execute_table_locked(struct atom_context *ctx, int index, uint32_t *params)
1206 int base = CU16(ctx->cmd_table + 4 + 2 * index);
1207 int len, ws, ps, ptr;
1209 atom_exec_context ectx;
1215 len = CU16(base + ATOM_CT_SIZE_PTR);
1216 ws = CU8(base + ATOM_CT_WS_PTR);
1217 ps = CU8(base + ATOM_CT_PS_PTR) & ATOM_CT_PS_MASK;
1218 ptr = base + ATOM_CT_CODE_PTR;
1220 SDEBUG(">> execute %04X (len %d, WS %d, PS %d)\n", base, len, ws, ps);
1223 ectx.ps_shift = ps / 4;
1229 ectx.ws = kcalloc(4, ws, GFP_KERNEL);
1236 if (op < ATOM_OP_NAMES_CNT)
1237 SDEBUG("%s @ 0x%04X\n", atom_op_names[op], ptr - 1);
1239 SDEBUG("[%d] @ 0x%04X\n", op, ptr - 1);
1241 DRM_ERROR("atombios stuck executing %04X (len %d, WS %d, PS %d) @ 0x%04X\n",
1242 base, len, ws, ps, ptr - 1);
1247 if (op < ATOM_OP_CNT && op > 0)
1248 opcode_table[op].func(&ectx, &ptr,
1249 opcode_table[op].arg);
1253 if (op == ATOM_OP_EOT)
1265 int amdgpu_atom_execute_table(struct atom_context *ctx, int index, uint32_t *params)
1269 mutex_lock(&ctx->mutex);
1270 /* reset data block */
1271 ctx->data_block = 0;
1272 /* reset reg block */
1274 /* reset fb window */
1277 ctx->io_mode = ATOM_IO_MM;
1281 r = amdgpu_atom_execute_table_locked(ctx, index, params);
1282 mutex_unlock(&ctx->mutex);
1286 static int atom_iio_len[] = { 1, 2, 3, 3, 3, 3, 4, 4, 4, 3 };
1288 static void atom_index_iio(struct atom_context *ctx, int base)
1290 ctx->iio = kzalloc(2 * 256, GFP_KERNEL);
1293 while (CU8(base) == ATOM_IIO_START) {
1294 ctx->iio[CU8(base + 1)] = base + 2;
1296 while (CU8(base) != ATOM_IIO_END)
1297 base += atom_iio_len[CU8(base)];
1302 struct atom_context *amdgpu_atom_parse(struct card_info *card, void *bios)
1305 struct atom_context *ctx =
1306 kzalloc(sizeof(struct atom_context), GFP_KERNEL);
1316 if (CU16(0) != ATOM_BIOS_MAGIC) {
1317 pr_info("Invalid BIOS magic\n");
1322 (CSTR(ATOM_ATI_MAGIC_PTR), ATOM_ATI_MAGIC,
1323 strlen(ATOM_ATI_MAGIC))) {
1324 pr_info("Invalid ATI magic\n");
1329 base = CU16(ATOM_ROM_TABLE_PTR);
1331 (CSTR(base + ATOM_ROM_MAGIC_PTR), ATOM_ROM_MAGIC,
1332 strlen(ATOM_ROM_MAGIC))) {
1333 pr_info("Invalid ATOM magic\n");
1338 ctx->cmd_table = CU16(base + ATOM_ROM_CMD_PTR);
1339 ctx->data_table = CU16(base + ATOM_ROM_DATA_PTR);
1340 atom_index_iio(ctx, CU16(ctx->data_table + ATOM_DATA_IIO_PTR) + 4);
1342 amdgpu_atom_destroy(ctx);
1346 idx = CU16(ATOM_ROM_PART_NUMBER_PTR);
1352 pr_info("ATOM BIOS: %s\n", str);
1353 strlcpy(ctx->vbios_version, str, sizeof(ctx->vbios_version));
1360 int amdgpu_atom_asic_init(struct atom_context *ctx)
1362 int hwi = CU16(ctx->data_table + ATOM_DATA_FWI_PTR);
1368 ps[0] = cpu_to_le32(CU32(hwi + ATOM_FWI_DEFSCLK_PTR));
1369 ps[1] = cpu_to_le32(CU32(hwi + ATOM_FWI_DEFMCLK_PTR));
1370 if (!ps[0] || !ps[1])
1373 if (!CU16(ctx->cmd_table + 4 + 2 * ATOM_CMD_INIT))
1375 ret = amdgpu_atom_execute_table(ctx, ATOM_CMD_INIT, ps);
1384 void amdgpu_atom_destroy(struct atom_context *ctx)
1390 bool amdgpu_atom_parse_data_header(struct atom_context *ctx, int index,
1391 uint16_t *size, uint8_t *frev, uint8_t *crev,
1392 uint16_t *data_start)
1394 int offset = index * 2 + 4;
1395 int idx = CU16(ctx->data_table + offset);
1396 u16 *mdt = (u16 *)(ctx->bios + ctx->data_table + 4);
1404 *frev = CU8(idx + 2);
1406 *crev = CU8(idx + 3);
1411 bool amdgpu_atom_parse_cmd_header(struct atom_context *ctx, int index, uint8_t *frev,
1414 int offset = index * 2 + 4;
1415 int idx = CU16(ctx->cmd_table + offset);
1416 u16 *mct = (u16 *)(ctx->bios + ctx->cmd_table + 4);
1422 *frev = CU8(idx + 2);
1424 *crev = CU8(idx + 3);