2 * Copyright 2021 Advanced Micro Devices, Inc.
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9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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25 #include "athub_v3_0.h"
26 #include "athub/athub_3_0_0_offset.h"
27 #include "athub/athub_3_0_0_sh_mask.h"
28 #include "navi10_enum.h"
29 #include "soc15_common.h"
31 #define regATHUB_MISC_CNTL_V3_0_1 0x00d7
32 #define regATHUB_MISC_CNTL_V3_0_1_BASE_IDX 0
33 #define regATHUB_MISC_CNTL_V3_3_0 0x00d8
34 #define regATHUB_MISC_CNTL_V3_3_0_BASE_IDX 0
37 static uint32_t athub_v3_0_get_cg_cntl(struct amdgpu_device *adev)
41 switch (amdgpu_ip_version(adev, ATHUB_HWIP, 0)) {
42 case IP_VERSION(3, 0, 1):
43 data = RREG32_SOC15(ATHUB, 0, regATHUB_MISC_CNTL_V3_0_1);
45 case IP_VERSION(3, 3, 0):
46 data = RREG32_SOC15(ATHUB, 0, regATHUB_MISC_CNTL_V3_3_0);
49 data = RREG32_SOC15(ATHUB, 0, regATHUB_MISC_CNTL);
55 static void athub_v3_0_set_cg_cntl(struct amdgpu_device *adev, uint32_t data)
57 switch (amdgpu_ip_version(adev, ATHUB_HWIP, 0)) {
58 case IP_VERSION(3, 0, 1):
59 WREG32_SOC15(ATHUB, 0, regATHUB_MISC_CNTL_V3_0_1, data);
61 case IP_VERSION(3, 3, 0):
62 WREG32_SOC15(ATHUB, 0, regATHUB_MISC_CNTL_V3_3_0, data);
65 WREG32_SOC15(ATHUB, 0, regATHUB_MISC_CNTL, data);
71 athub_v3_0_update_medium_grain_clock_gating(struct amdgpu_device *adev,
76 def = data = athub_v3_0_get_cg_cntl(adev);
78 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_ATHUB_MGCG))
79 data |= ATHUB_MISC_CNTL__CG_ENABLE_MASK;
81 data &= ~ATHUB_MISC_CNTL__CG_ENABLE_MASK;
84 athub_v3_0_set_cg_cntl(adev, data);
88 athub_v3_0_update_medium_grain_light_sleep(struct amdgpu_device *adev,
93 def = data = athub_v3_0_get_cg_cntl(adev);
95 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_ATHUB_LS))
96 data |= ATHUB_MISC_CNTL__CG_MEM_LS_ENABLE_MASK;
98 data &= ~ATHUB_MISC_CNTL__CG_MEM_LS_ENABLE_MASK;
101 athub_v3_0_set_cg_cntl(adev, data);
104 int athub_v3_0_set_clockgating(struct amdgpu_device *adev,
105 enum amd_clockgating_state state)
107 if (amdgpu_sriov_vf(adev))
110 switch (amdgpu_ip_version(adev, ATHUB_HWIP, 0)) {
111 case IP_VERSION(3, 0, 0):
112 case IP_VERSION(3, 0, 1):
113 case IP_VERSION(3, 0, 2):
114 case IP_VERSION(3, 3, 0):
115 athub_v3_0_update_medium_grain_clock_gating(adev,
116 state == AMD_CG_STATE_GATE);
117 athub_v3_0_update_medium_grain_light_sleep(adev,
118 state == AMD_CG_STATE_GATE);
127 void athub_v3_0_get_clockgating(struct amdgpu_device *adev, u64 *flags)
131 /* AMD_CG_SUPPORT_ATHUB_MGCG */
132 data = athub_v3_0_get_cg_cntl(adev);
133 if (data & ATHUB_MISC_CNTL__CG_ENABLE_MASK)
134 *flags |= AMD_CG_SUPPORT_ATHUB_MGCG;
136 /* AMD_CG_SUPPORT_ATHUB_LS */
137 if (data & ATHUB_MISC_CNTL__CG_MEM_LS_ENABLE_MASK)
138 *flags |= AMD_CG_SUPPORT_ATHUB_LS;