2 * Copyright 2018-2019 Advanced Micro Devices, Inc.
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5 * copy of this software and associated documentation files (the "Software"),
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9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
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24 #ifndef AMDGV_SRIOV_MSG__H_
25 #define AMDGV_SRIOV_MSG__H_
27 /* unit in kilobytes */
28 #define AMD_SRIOV_MSG_VBIOS_OFFSET 0
29 #define AMD_SRIOV_MSG_VBIOS_SIZE_KB 64
30 #define AMD_SRIOV_MSG_DATAEXCHANGE_OFFSET_KB AMD_SRIOV_MSG_VBIOS_SIZE_KB
31 #define AMD_SRIOV_MSG_DATAEXCHANGE_SIZE_KB 4
36 * | VBIOS | PF2VF | VF2PF | Bad Page | ...
37 * | 64KB | 1KB | 1KB |
39 #define AMD_SRIOV_MSG_SIZE_KB 1
40 #define AMD_SRIOV_MSG_PF2VF_OFFSET_KB AMD_SRIOV_MSG_DATAEXCHANGE_OFFSET_KB
41 #define AMD_SRIOV_MSG_VF2PF_OFFSET_KB (AMD_SRIOV_MSG_PF2VF_OFFSET_KB + AMD_SRIOV_MSG_SIZE_KB)
42 #define AMD_SRIOV_MSG_BAD_PAGE_OFFSET_KB (AMD_SRIOV_MSG_VF2PF_OFFSET_KB + AMD_SRIOV_MSG_SIZE_KB)
46 * v1 defined in amdgim
50 * v1 defined in amdgim
51 * v2 defined in amdgim
54 #define AMD_SRIOV_MSG_FW_VRAM_PF2VF_VER 2
55 #define AMD_SRIOV_MSG_FW_VRAM_VF2PF_VER 3
57 #define AMD_SRIOV_MSG_RESERVE_UCODE 24
59 enum amd_sriov_ucode_engine_id {
60 AMD_SRIOV_UCODE_ID_VCE = 0,
61 AMD_SRIOV_UCODE_ID_UVD,
62 AMD_SRIOV_UCODE_ID_MC,
63 AMD_SRIOV_UCODE_ID_ME,
64 AMD_SRIOV_UCODE_ID_PFP,
65 AMD_SRIOV_UCODE_ID_CE,
66 AMD_SRIOV_UCODE_ID_RLC,
67 AMD_SRIOV_UCODE_ID_RLC_SRLC,
68 AMD_SRIOV_UCODE_ID_RLC_SRLG,
69 AMD_SRIOV_UCODE_ID_RLC_SRLS,
70 AMD_SRIOV_UCODE_ID_MEC,
71 AMD_SRIOV_UCODE_ID_MEC2,
72 AMD_SRIOV_UCODE_ID_SOS,
73 AMD_SRIOV_UCODE_ID_ASD,
74 AMD_SRIOV_UCODE_ID_TA_RAS,
75 AMD_SRIOV_UCODE_ID_TA_XGMI,
76 AMD_SRIOV_UCODE_ID_SMC,
77 AMD_SRIOV_UCODE_ID_SDMA,
78 AMD_SRIOV_UCODE_ID_SDMA2,
79 AMD_SRIOV_UCODE_ID_VCN,
80 AMD_SRIOV_UCODE_ID_DMCU,
81 AMD_SRIOV_UCODE_ID__MAX
84 #pragma pack(push, 1) // PF2VF / VF2PF data areas are byte packed
86 union amd_sriov_msg_feature_flags {
88 uint32_t error_log_collect : 1;
89 uint32_t host_load_ucodes : 1;
90 uint32_t host_flr_vramlost : 1;
91 uint32_t mm_bw_management : 1;
92 uint32_t pp_one_vf_mode : 1;
93 uint32_t reg_indirect_acc : 1;
94 uint32_t reserved : 26;
99 union amd_sriov_reg_access_flags {
101 uint32_t vf_reg_access_ih : 1;
102 uint32_t vf_reg_access_mmhub : 1;
103 uint32_t vf_reg_access_gc : 1;
104 uint32_t reserved : 29;
109 union amd_sriov_msg_os_info {
111 uint32_t windows : 1;
112 uint32_t reserved : 31;
117 struct amd_sriov_msg_pf2vf_info_header {
118 /* the total structure size in byte */
120 /* version of this structure, written by the HOST */
123 uint32_t reserved[2];
126 struct amd_sriov_msg_pf2vf_info {
127 /* header contains size and version */
128 struct amd_sriov_msg_pf2vf_info_header header;
129 /* use private key from mailbox 2 to create checksum */
131 /* The features flags of the HOST driver supports */
132 union amd_sriov_msg_feature_flags feature_flags;
133 /* (max_width * max_height * fps) / (16 * 16) */
134 uint32_t hevc_enc_max_mb_per_second;
135 /* (max_width * max_height) / (16 * 16) */
136 uint32_t hevc_enc_max_mb_per_frame;
137 /* (max_width * max_height * fps) / (16 * 16) */
138 uint32_t avc_enc_max_mb_per_second;
139 /* (max_width * max_height) / (16 * 16) */
140 uint32_t avc_enc_max_mb_per_frame;
141 /* MEC FW position in BYTE from the start of VF visible frame buffer */
142 uint64_t mecfw_offset;
143 /* MEC FW size in BYTE */
145 /* UVD FW position in BYTE from the start of VF visible frame buffer */
146 uint64_t uvdfw_offset;
147 /* UVD FW size in BYTE */
149 /* VCE FW position in BYTE from the start of VF visible frame buffer */
150 uint64_t vcefw_offset;
151 /* VCE FW size in BYTE */
153 /* Bad pages block position in BYTE */
154 uint32_t bp_block_offset_low;
155 uint32_t bp_block_offset_high;
156 /* Bad pages block size in BYTE */
157 uint32_t bp_block_size;
158 /* frequency for VF to update the VF2PF area in msec, 0 = manual */
159 uint32_t vf2pf_update_interval_ms;
160 /* identification in ROCm SMI */
163 /* flags which indicate the register access method VF should use */
164 union amd_sriov_reg_access_flags reg_access_flags;
166 uint32_t reserved[256-27];
169 struct amd_sriov_msg_vf2pf_info_header {
170 /* the total structure size in byte */
172 /* version of this structure, written by the guest */
175 uint32_t reserved[2];
178 struct amd_sriov_msg_vf2pf_info {
179 /* header contains size and version */
180 struct amd_sriov_msg_vf2pf_info_header header;
183 uint8_t driver_version[64];
184 /* driver certification, 1=WHQL, 0=None */
185 uint32_t driver_cert;
186 /* guest OS type and version */
187 union amd_sriov_msg_os_info os_info;
188 /* guest fb information in the unit of MB */
190 /* guest gfx engine usage percentage */
192 /* guest gfx engine health percentage */
194 /* guest compute engine usage percentage */
195 uint32_t compute_usage;
196 /* guest compute engine health percentage */
197 uint32_t compute_health;
198 /* guest avc engine usage percentage. 0xffff means N/A */
199 uint32_t avc_enc_usage;
200 /* guest avc engine health percentage. 0xffff means N/A */
201 uint32_t avc_enc_health;
202 /* guest hevc engine usage percentage. 0xffff means N/A */
203 uint32_t hevc_enc_usage;
204 /* guest hevc engine usage percentage. 0xffff means N/A */
205 uint32_t hevc_enc_health;
206 /* combined encode/decode usage */
207 uint32_t encode_usage;
208 uint32_t decode_usage;
209 /* Version of PF2VF that VF understands */
210 uint32_t pf2vf_version_required;
211 /* additional FB usage */
212 uint32_t fb_vis_usage;
213 uint32_t fb_vis_size;
215 /* guest ucode data, each one is 1.25 Dword */
219 } ucode_info[AMD_SRIOV_MSG_RESERVE_UCODE];
222 uint32_t reserved[256-68];
225 /* mailbox message send from guest to host */
226 enum amd_sriov_mailbox_request_message {
227 MB_REQ_MSG_REQ_GPU_INIT_ACCESS = 1,
228 MB_REQ_MSG_REL_GPU_INIT_ACCESS,
229 MB_REQ_MSG_REQ_GPU_FINI_ACCESS,
230 MB_REQ_MSG_REL_GPU_FINI_ACCESS,
231 MB_REQ_MSG_REQ_GPU_RESET_ACCESS,
232 MB_REQ_MSG_REQ_GPU_INIT_DATA,
234 MB_REQ_MSG_LOG_VF_ERROR = 200,
237 /* mailbox message send from host to guest */
238 enum amd_sriov_mailbox_response_message {
239 MB_RES_MSG_CLR_MSG_BUF = 0,
240 MB_RES_MSG_READY_TO_ACCESS_GPU = 1,
241 MB_RES_MSG_FLR_NOTIFICATION,
242 MB_RES_MSG_FLR_NOTIFICATION_COMPLETION,
245 MB_RES_MSG_QUERY_ALIVE,
246 MB_RES_MSG_GPU_INIT_DATA_READY,
248 MB_RES_MSG_TEXT_MESSAGE = 255
251 /* version data stored in MAILBOX_MSGBUF_RCV_DW1 for future expansion */
252 enum amd_sriov_gpu_init_data_version {
253 GPU_INIT_DATA_READY_V1 = 1,
256 #pragma pack(pop) // Restore previous packing option
258 /* checksum function between host and guest */
259 unsigned int amd_sriov_msg_checksum(void *obj,
260 unsigned long obj_size,
262 unsigned int checksum);
264 /* assertion at compile time */
266 #define stringification(s) _stringification(s)
267 #define _stringification(s) #s
270 sizeof(struct amd_sriov_msg_vf2pf_info) == AMD_SRIOV_MSG_SIZE_KB << 10,
271 "amd_sriov_msg_vf2pf_info must be " stringification(AMD_SRIOV_MSG_SIZE_KB) " KB");
274 sizeof(struct amd_sriov_msg_pf2vf_info) == AMD_SRIOV_MSG_SIZE_KB << 10,
275 "amd_sriov_msg_pf2vf_info must be " stringification(AMD_SRIOV_MSG_SIZE_KB) " KB");
278 AMD_SRIOV_MSG_RESERVE_UCODE % 4 == 0,
279 "AMD_SRIOV_MSG_RESERVE_UCODE must be multiple of 4");
282 AMD_SRIOV_MSG_RESERVE_UCODE > AMD_SRIOV_UCODE_ID__MAX,
283 "AMD_SRIOV_MSG_RESERVE_UCODE must be bigger than AMD_SRIOV_UCODE_ID__MAX");
285 #undef _stringification
286 #undef stringification
289 #endif /* AMDGV_SRIOV_MSG__H_ */