drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.c

   1 /*
   2  * Copyright 2018 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  *
  23  */
  24 #include <linux/list.h>
  25 #include "amdgpu.h"
  26 #include "amdgpu_xgmi.h"
  27 #include "amdgpu_smu.h"
  28 #include "amdgpu_ras.h"
  29 #include "soc15.h"
  30 #include "df/df_3_6_offset.h"
  31 #include "xgmi/xgmi_4_0_0_smn.h"
  32 #include "xgmi/xgmi_4_0_0_sh_mask.h"
  33 #include "wafl/wafl2_4_0_0_smn.h"
  34 #include "wafl/wafl2_4_0_0_sh_mask.h"
  35
  36 static DEFINE_MUTEX(xgmi_mutex);
  37
  38 #define AMDGPU_MAX_XGMI_HIVE                    8
  39 #define AMDGPU_MAX_XGMI_DEVICE_PER_HIVE         4
  40
  41 static struct amdgpu_hive_info xgmi_hives[AMDGPU_MAX_XGMI_HIVE];
  42 static unsigned hive_count = 0;
  43
  44 static const int xgmi_pcs_err_status_reg_vg20[] = {
  45         smnXGMI0_PCS_GOPX16_PCS_ERROR_STATUS,
  46         smnXGMI0_PCS_GOPX16_PCS_ERROR_STATUS + 0x100000,
  47 };
  48
  49 static const int wafl_pcs_err_status_reg_vg20[] = {
  50         smnPCS_GOPX1_0_PCS_GOPX1_PCS_ERROR_STATUS,
  51         smnPCS_GOPX1_0_PCS_GOPX1_PCS_ERROR_STATUS + 0x100000,
  52 };
  53
  54 static const int xgmi_pcs_err_status_reg_arct[] = {
  55         smnXGMI0_PCS_GOPX16_PCS_ERROR_STATUS,
  56         smnXGMI0_PCS_GOPX16_PCS_ERROR_STATUS + 0x100000,
  57         smnXGMI0_PCS_GOPX16_PCS_ERROR_STATUS + 0x500000,
  58         smnXGMI0_PCS_GOPX16_PCS_ERROR_STATUS + 0x600000,
  59         smnXGMI0_PCS_GOPX16_PCS_ERROR_STATUS + 0x700000,
  60         smnXGMI0_PCS_GOPX16_PCS_ERROR_STATUS + 0x800000,
  61 };
  62
  63 /* same as vg20*/
  64 static const int wafl_pcs_err_status_reg_arct[] = {
  65         smnPCS_GOPX1_0_PCS_GOPX1_PCS_ERROR_STATUS,
  66         smnPCS_GOPX1_0_PCS_GOPX1_PCS_ERROR_STATUS + 0x100000,
  67 };
  68
  69 static const struct amdgpu_pcs_ras_field xgmi_pcs_ras_fields[] = {
  70         {"XGMI PCS DataLossErr",
  71          SOC15_REG_FIELD(XGMI0_PCS_GOPX16_PCS_ERROR_STATUS, DataLossErr)},
  72         {"XGMI PCS TrainingErr",
  73          SOC15_REG_FIELD(XGMI0_PCS_GOPX16_PCS_ERROR_STATUS, TrainingErr)},
  74         {"XGMI PCS CRCErr",
  75          SOC15_REG_FIELD(XGMI0_PCS_GOPX16_PCS_ERROR_STATUS, CRCErr)},
  76         {"XGMI PCS BERExceededErr",
  77          SOC15_REG_FIELD(XGMI0_PCS_GOPX16_PCS_ERROR_STATUS, BERExceededErr)},
  78         {"XGMI PCS TxMetaDataErr",
  79          SOC15_REG_FIELD(XGMI0_PCS_GOPX16_PCS_ERROR_STATUS, TxMetaDataErr)},
  80         {"XGMI PCS ReplayBufParityErr",
  81          SOC15_REG_FIELD(XGMI0_PCS_GOPX16_PCS_ERROR_STATUS, ReplayBufParityErr)},
  82         {"XGMI PCS DataParityErr",
  83          SOC15_REG_FIELD(XGMI0_PCS_GOPX16_PCS_ERROR_STATUS, DataParityErr)},
  84         {"XGMI PCS ReplayFifoOverflowErr",
  85          SOC15_REG_FIELD(XGMI0_PCS_GOPX16_PCS_ERROR_STATUS, ReplayFifoOverflowErr)},
  86         {"XGMI PCS ReplayFifoUnderflowErr",
  87          SOC15_REG_FIELD(XGMI0_PCS_GOPX16_PCS_ERROR_STATUS, ReplayFifoUnderflowErr)},
  88         {"XGMI PCS ElasticFifoOverflowErr",
  89          SOC15_REG_FIELD(XGMI0_PCS_GOPX16_PCS_ERROR_STATUS, ElasticFifoOverflowErr)},
  90         {"XGMI PCS DeskewErr",
  91          SOC15_REG_FIELD(XGMI0_PCS_GOPX16_PCS_ERROR_STATUS, DeskewErr)},
  92         {"XGMI PCS DataStartupLimitErr",
  93          SOC15_REG_FIELD(XGMI0_PCS_GOPX16_PCS_ERROR_STATUS, DataStartupLimitErr)},
  94         {"XGMI PCS FCInitTimeoutErr",
  95          SOC15_REG_FIELD(XGMI0_PCS_GOPX16_PCS_ERROR_STATUS, FCInitTimeoutErr)},
  96         {"XGMI PCS RecoveryTimeoutErr",
  97          SOC15_REG_FIELD(XGMI0_PCS_GOPX16_PCS_ERROR_STATUS, RecoveryTimeoutErr)},
  98         {"XGMI PCS ReadySerialTimeoutErr",
  99          SOC15_REG_FIELD(XGMI0_PCS_GOPX16_PCS_ERROR_STATUS, ReadySerialTimeoutErr)},
 100         {"XGMI PCS ReadySerialAttemptErr",
 101          SOC15_REG_FIELD(XGMI0_PCS_GOPX16_PCS_ERROR_STATUS, ReadySerialAttemptErr)},
 102         {"XGMI PCS RecoveryAttemptErr",
 103          SOC15_REG_FIELD(XGMI0_PCS_GOPX16_PCS_ERROR_STATUS, RecoveryAttemptErr)},
 104         {"XGMI PCS RecoveryRelockAttemptErr",
 105          SOC15_REG_FIELD(XGMI0_PCS_GOPX16_PCS_ERROR_STATUS, RecoveryRelockAttemptErr)},
 106 };
 107
 108 static const struct amdgpu_pcs_ras_field wafl_pcs_ras_fields[] = {
 109         {"WAFL PCS DataLossErr",
 110          SOC15_REG_FIELD(PCS_GOPX1_0_PCS_GOPX1_PCS_ERROR_STATUS, DataLossErr)},
 111         {"WAFL PCS TrainingErr",
 112          SOC15_REG_FIELD(PCS_GOPX1_0_PCS_GOPX1_PCS_ERROR_STATUS, TrainingErr)},
 113         {"WAFL PCS CRCErr",
 114          SOC15_REG_FIELD(PCS_GOPX1_0_PCS_GOPX1_PCS_ERROR_STATUS, CRCErr)},
 115         {"WAFL PCS BERExceededErr",
 116          SOC15_REG_FIELD(PCS_GOPX1_0_PCS_GOPX1_PCS_ERROR_STATUS, BERExceededErr)},
 117         {"WAFL PCS TxMetaDataErr",
 118          SOC15_REG_FIELD(PCS_GOPX1_0_PCS_GOPX1_PCS_ERROR_STATUS, TxMetaDataErr)},
 119         {"WAFL PCS ReplayBufParityErr",
 120          SOC15_REG_FIELD(PCS_GOPX1_0_PCS_GOPX1_PCS_ERROR_STATUS, ReplayBufParityErr)},
 121         {"WAFL PCS DataParityErr",
 122          SOC15_REG_FIELD(PCS_GOPX1_0_PCS_GOPX1_PCS_ERROR_STATUS, DataParityErr)},
 123         {"WAFL PCS ReplayFifoOverflowErr",
 124          SOC15_REG_FIELD(PCS_GOPX1_0_PCS_GOPX1_PCS_ERROR_STATUS, ReplayFifoOverflowErr)},
 125         {"WAFL PCS ReplayFifoUnderflowErr",
 126          SOC15_REG_FIELD(PCS_GOPX1_0_PCS_GOPX1_PCS_ERROR_STATUS, ReplayFifoUnderflowErr)},
 127         {"WAFL PCS ElasticFifoOverflowErr",
 128          SOC15_REG_FIELD(PCS_GOPX1_0_PCS_GOPX1_PCS_ERROR_STATUS, ElasticFifoOverflowErr)},
 129         {"WAFL PCS DeskewErr",
 130          SOC15_REG_FIELD(PCS_GOPX1_0_PCS_GOPX1_PCS_ERROR_STATUS, DeskewErr)},
 131         {"WAFL PCS DataStartupLimitErr",
 132          SOC15_REG_FIELD(PCS_GOPX1_0_PCS_GOPX1_PCS_ERROR_STATUS, DataStartupLimitErr)},
 133         {"WAFL PCS FCInitTimeoutErr",
 134          SOC15_REG_FIELD(PCS_GOPX1_0_PCS_GOPX1_PCS_ERROR_STATUS, FCInitTimeoutErr)},
 135         {"WAFL PCS RecoveryTimeoutErr",
 136          SOC15_REG_FIELD(PCS_GOPX1_0_PCS_GOPX1_PCS_ERROR_STATUS, RecoveryTimeoutErr)},
 137         {"WAFL PCS ReadySerialTimeoutErr",
 138          SOC15_REG_FIELD(PCS_GOPX1_0_PCS_GOPX1_PCS_ERROR_STATUS, ReadySerialTimeoutErr)},
 139         {"WAFL PCS ReadySerialAttemptErr",
 140          SOC15_REG_FIELD(PCS_GOPX1_0_PCS_GOPX1_PCS_ERROR_STATUS, ReadySerialAttemptErr)},
 141         {"WAFL PCS RecoveryAttemptErr",
 142          SOC15_REG_FIELD(PCS_GOPX1_0_PCS_GOPX1_PCS_ERROR_STATUS, RecoveryAttemptErr)},
 143         {"WAFL PCS RecoveryRelockAttemptErr",
 144          SOC15_REG_FIELD(PCS_GOPX1_0_PCS_GOPX1_PCS_ERROR_STATUS, RecoveryRelockAttemptErr)},
 145 };
 146
 147 void *amdgpu_xgmi_hive_try_lock(struct amdgpu_hive_info *hive)
 148 {
 149         return &hive->device_list;
 150 }
 151
 152 /**
 153  * DOC: AMDGPU XGMI Support
 154  *
 155  * XGMI is a high speed interconnect that joins multiple GPU cards
 156  * into a homogeneous memory space that is organized by a collective
 157  * hive ID and individual node IDs, both of which are 64-bit numbers.
 158  *
 159  * The file xgmi_device_id contains the unique per GPU device ID and
 160  * is stored in the /sys/class/drm/card${cardno}/device/ directory.
 161  *
 162  * Inside the device directory a sub-directory 'xgmi_hive_info' is
 163  * created which contains the hive ID and the list of nodes.
 164  *
 165  * The hive ID is stored in:
 166  *   /sys/class/drm/card${cardno}/device/xgmi_hive_info/xgmi_hive_id
 167  *
 168  * The node information is stored in numbered directories:
 169  *   /sys/class/drm/card${cardno}/device/xgmi_hive_info/node${nodeno}/xgmi_device_id
 170  *
 171  * Each device has their own xgmi_hive_info direction with a mirror
 172  * set of node sub-directories.
 173  *
 174  * The XGMI memory space is built by contiguously adding the power of
 175  * two padded VRAM space from each node to each other.
 176  *
 177  */
 178
 179
 180 static ssize_t amdgpu_xgmi_show_hive_id(struct device *dev,
 181                 struct device_attribute *attr, char *buf)
 182 {
 183         struct amdgpu_hive_info *hive =
 184                         container_of(attr, struct amdgpu_hive_info, dev_attr);
 185
 186         return snprintf(buf, PAGE_SIZE, "%llu\n", hive->hive_id);
 187 }
 188
 189 static int amdgpu_xgmi_sysfs_create(struct amdgpu_device *adev,
 190                                     struct amdgpu_hive_info *hive)
 191 {
 192         int ret = 0;
 193
 194         if (WARN_ON(hive->kobj))
 195                 return -EINVAL;
 196
 197         hive->kobj = kobject_create_and_add("xgmi_hive_info", &adev->dev->kobj);
 198         if (!hive->kobj) {
 199                 dev_err(adev->dev, "XGMI: Failed to allocate sysfs entry!\n");
 200                 return -EINVAL;
 201         }
 202
 203         hive->dev_attr = (struct device_attribute) {
 204                 .attr = {
 205                         .name = "xgmi_hive_id",
 206                         .mode = S_IRUGO,
 207
 208                 },
 209                 .show = amdgpu_xgmi_show_hive_id,
 210         };
 211
 212         ret = sysfs_create_file(hive->kobj, &hive->dev_attr.attr);
 213         if (ret) {
 214                 dev_err(adev->dev, "XGMI: Failed to create device file xgmi_hive_id\n");
 215                 kobject_del(hive->kobj);
 216                 kobject_put(hive->kobj);
 217                 hive->kobj = NULL;
 218         }
 219
 220         return ret;
 221 }
 222
 223 static void amdgpu_xgmi_sysfs_destroy(struct amdgpu_device *adev,
 224                                     struct amdgpu_hive_info *hive)
 225 {
 226         sysfs_remove_file(hive->kobj, &hive->dev_attr.attr);
 227         kobject_del(hive->kobj);
 228         kobject_put(hive->kobj);
 229         hive->kobj = NULL;
 230 }
 231
 232 static ssize_t amdgpu_xgmi_show_device_id(struct device *dev,
 233                                      struct device_attribute *attr,
 234                                      char *buf)
 235 {
 236         struct drm_device *ddev = dev_get_drvdata(dev);
 237         struct amdgpu_device *adev = ddev->dev_private;
 238
 239         return snprintf(buf, PAGE_SIZE, "%llu\n", adev->gmc.xgmi.node_id);
 240
 241 }
 242
 243 #define AMDGPU_XGMI_SET_FICAA(o)        ((o) | 0x456801)
 244 static ssize_t amdgpu_xgmi_show_error(struct device *dev,
 245                                       struct device_attribute *attr,
 246                                       char *buf)
 247 {
 248         struct drm_device *ddev = dev_get_drvdata(dev);
 249         struct amdgpu_device *adev = ddev->dev_private;
 250         uint32_t ficaa_pie_ctl_in, ficaa_pie_status_in;
 251         uint64_t fica_out;
 252         unsigned int error_count = 0;
 253
 254         ficaa_pie_ctl_in = AMDGPU_XGMI_SET_FICAA(0x200);
 255         ficaa_pie_status_in = AMDGPU_XGMI_SET_FICAA(0x208);
 256
 257         fica_out = adev->df.funcs->get_fica(adev, ficaa_pie_ctl_in);
 258         if (fica_out != 0x1f)
 259                 pr_err("xGMI error counters not enabled!\n");
 260
 261         fica_out = adev->df.funcs->get_fica(adev, ficaa_pie_status_in);
 262
 263         if ((fica_out & 0xffff) == 2)
 264                 error_count = ((fica_out >> 62) & 0x1) + (fica_out >> 63);
 265
 266         adev->df.funcs->set_fica(adev, ficaa_pie_status_in, 0, 0);
 267
 268         return snprintf(buf, PAGE_SIZE, "%d\n", error_count);
 269 }
 270
 271
 272 static DEVICE_ATTR(xgmi_device_id, S_IRUGO, amdgpu_xgmi_show_device_id, NULL);
 273 static DEVICE_ATTR(xgmi_error, S_IRUGO, amdgpu_xgmi_show_error, NULL);
 274
 275 static int amdgpu_xgmi_sysfs_add_dev_info(struct amdgpu_device *adev,
 276                                          struct amdgpu_hive_info *hive)
 277 {
 278         int ret = 0;
 279         char node[10] = { 0 };
 280
 281         /* Create xgmi device id file */
 282         ret = device_create_file(adev->dev, &dev_attr_xgmi_device_id);
 283         if (ret) {
 284                 dev_err(adev->dev, "XGMI: Failed to create device file xgmi_device_id\n");
 285                 return ret;
 286         }
 287
 288         /* Create xgmi error file */
 289         ret = device_create_file(adev->dev, &dev_attr_xgmi_error);
 290         if (ret)
 291                 pr_err("failed to create xgmi_error\n");
 292
 293
 294         /* Create sysfs link to hive info folder on the first device */
 295         if (adev != hive->adev) {
 296                 ret = sysfs_create_link(&adev->dev->kobj, hive->kobj,
 297                                         "xgmi_hive_info");
 298                 if (ret) {
 299                         dev_err(adev->dev, "XGMI: Failed to create link to hive info");
 300                         goto remove_file;
 301                 }
 302         }
 303
 304         sprintf(node, "node%d", hive->number_devices);
 305         /* Create sysfs link form the hive folder to yourself */
 306         ret = sysfs_create_link(hive->kobj, &adev->dev->kobj, node);
 307         if (ret) {
 308                 dev_err(adev->dev, "XGMI: Failed to create link from hive info");
 309                 goto remove_link;
 310         }
 311
 312         goto success;
 313
 314
 315 remove_link:
 316         sysfs_remove_link(&adev->dev->kobj, adev->ddev->unique);
 317
 318 remove_file:
 319         device_remove_file(adev->dev, &dev_attr_xgmi_device_id);
 320
 321 success:
 322         return ret;
 323 }
 324
 325 static void amdgpu_xgmi_sysfs_rem_dev_info(struct amdgpu_device *adev,
 326                                           struct amdgpu_hive_info *hive)
 327 {
 328         device_remove_file(adev->dev, &dev_attr_xgmi_device_id);
 329         sysfs_remove_link(&adev->dev->kobj, adev->ddev->unique);
 330         sysfs_remove_link(hive->kobj, adev->ddev->unique);
 331 }
 332
 333
 334
 335 struct amdgpu_hive_info *amdgpu_get_xgmi_hive(struct amdgpu_device *adev, int lock)
 336 {
 337         int i;
 338         struct amdgpu_hive_info *tmp;
 339
 340         if (!adev->gmc.xgmi.hive_id)
 341                 return NULL;
 342
 343         mutex_lock(&xgmi_mutex);
 344
 345         for (i = 0 ; i < hive_count; ++i) {
 346                 tmp = &xgmi_hives[i];
 347                 if (tmp->hive_id == adev->gmc.xgmi.hive_id) {
 348                         if (lock)
 349                                 mutex_lock(&tmp->hive_lock);
 350                         mutex_unlock(&xgmi_mutex);
 351                         return tmp;
 352                 }
 353         }
 354         if (i >= AMDGPU_MAX_XGMI_HIVE) {
 355                 mutex_unlock(&xgmi_mutex);
 356                 return NULL;
 357         }
 358
 359         /* initialize new hive if not exist */
 360         tmp = &xgmi_hives[hive_count++];
 361
 362         if (amdgpu_xgmi_sysfs_create(adev, tmp)) {
 363                 mutex_unlock(&xgmi_mutex);
 364                 return NULL;
 365         }
 366
 367         tmp->adev = adev;
 368         tmp->hive_id = adev->gmc.xgmi.hive_id;
 369         INIT_LIST_HEAD(&tmp->device_list);
 370         mutex_init(&tmp->hive_lock);
 371         mutex_init(&tmp->reset_lock);
 372         task_barrier_init(&tmp->tb);
 373
 374         if (lock)
 375                 mutex_lock(&tmp->hive_lock);
 376         tmp->pstate = AMDGPU_XGMI_PSTATE_UNKNOWN;
 377         tmp->hi_req_gpu = NULL;
 378         /*
 379          * hive pstate on boot is high in vega20 so we have to go to low
 380          * pstate on after boot.
 381          */
 382         tmp->hi_req_count = AMDGPU_MAX_XGMI_DEVICE_PER_HIVE;
 383         mutex_unlock(&xgmi_mutex);
 384
 385         return tmp;
 386 }
 387
 388 int amdgpu_xgmi_set_pstate(struct amdgpu_device *adev, int pstate)
 389 {
 390         int ret = 0;
 391         struct amdgpu_hive_info *hive = amdgpu_get_xgmi_hive(adev, 0);
 392         struct amdgpu_device *request_adev = hive->hi_req_gpu ?
 393                                                 hive->hi_req_gpu : adev;
 394         bool is_hi_req = pstate == AMDGPU_XGMI_PSTATE_MAX_VEGA20;
 395         bool init_low = hive->pstate == AMDGPU_XGMI_PSTATE_UNKNOWN;
 396
 397         /* fw bug so temporarily disable pstate switching */
 398         return 0;
 399
 400         if (!hive || adev->asic_type != CHIP_VEGA20)
 401                 return 0;
 402
 403         mutex_lock(&hive->hive_lock);
 404
 405         if (is_hi_req)
 406                 hive->hi_req_count++;
 407         else
 408                 hive->hi_req_count--;
 409
 410         /*
 411          * Vega20 only needs single peer to request pstate high for the hive to
 412          * go high but all peers must request pstate low for the hive to go low
 413          */
 414         if (hive->pstate == pstate ||
 415                         (!is_hi_req && hive->hi_req_count && !init_low))
 416                 goto out;
 417
 418         dev_dbg(request_adev->dev, "Set xgmi pstate %d.\n", pstate);
 419
 420         ret = amdgpu_dpm_set_xgmi_pstate(request_adev, pstate);
 421         if (ret) {
 422                 dev_err(request_adev->dev,
 423                         "XGMI: Set pstate failure on device %llx, hive %llx, ret %d",
 424                         request_adev->gmc.xgmi.node_id,
 425                         request_adev->gmc.xgmi.hive_id, ret);
 426                 goto out;
 427         }
 428
 429         if (init_low)
 430                 hive->pstate = hive->hi_req_count ?
 431                                         hive->pstate : AMDGPU_XGMI_PSTATE_MIN;
 432         else {
 433                 hive->pstate = pstate;
 434                 hive->hi_req_gpu = pstate != AMDGPU_XGMI_PSTATE_MIN ?
 435                                                         adev : NULL;
 436         }
 437 out:
 438         mutex_unlock(&hive->hive_lock);
 439         return ret;
 440 }
 441
 442 int amdgpu_xgmi_update_topology(struct amdgpu_hive_info *hive, struct amdgpu_device *adev)
 443 {
 444         int ret = -EINVAL;
 445
 446         /* Each psp need to set the latest topology */
 447         ret = psp_xgmi_set_topology_info(&adev->psp,
 448                                          hive->number_devices,
 449                                          &adev->psp.xgmi_context.top_info);
 450         if (ret)
 451                 dev_err(adev->dev,
 452                         "XGMI: Set topology failure on device %llx, hive %llx, ret %d",
 453                         adev->gmc.xgmi.node_id,
 454                         adev->gmc.xgmi.hive_id, ret);
 455
 456         return ret;
 457 }
 458
 459
 460 int amdgpu_xgmi_get_hops_count(struct amdgpu_device *adev,
 461                 struct amdgpu_device *peer_adev)
 462 {
 463         struct psp_xgmi_topology_info *top = &adev->psp.xgmi_context.top_info;
 464         int i;
 465
 466         for (i = 0 ; i < top->num_nodes; ++i)
 467                 if (top->nodes[i].node_id == peer_adev->gmc.xgmi.node_id)
 468                         return top->nodes[i].num_hops;
 469         return  -EINVAL;
 470 }
 471
 472 int amdgpu_xgmi_add_device(struct amdgpu_device *adev)
 473 {
 474         struct psp_xgmi_topology_info *top_info;
 475         struct amdgpu_hive_info *hive;
 476         struct amdgpu_xgmi      *entry;
 477         struct amdgpu_device *tmp_adev = NULL;
 478
 479         int count = 0, ret = 0;
 480
 481         if (!adev->gmc.xgmi.supported)
 482                 return 0;
 483
 484         if (amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_PSP)) {
 485                 ret = psp_xgmi_initialize(&adev->psp);
 486                 if (ret) {
 487                         dev_err(adev->dev,
 488                                 "XGMI: Failed to initialize xgmi session\n");
 489                         return ret;
 490                 }
 491
 492                 ret = psp_xgmi_get_hive_id(&adev->psp, &adev->gmc.xgmi.hive_id);
 493                 if (ret) {
 494                         dev_err(adev->dev,
 495                                 "XGMI: Failed to get hive id\n");
 496                         return ret;
 497                 }
 498
 499                 ret = psp_xgmi_get_node_id(&adev->psp, &adev->gmc.xgmi.node_id);
 500                 if (ret) {
 501                         dev_err(adev->dev,
 502                                 "XGMI: Failed to get node id\n");
 503                         return ret;
 504                 }
 505         } else {
 506                 adev->gmc.xgmi.hive_id = 16;
 507                 adev->gmc.xgmi.node_id = adev->gmc.xgmi.physical_node_id + 16;
 508         }
 509
 510         hive = amdgpu_get_xgmi_hive(adev, 1);
 511         if (!hive) {
 512                 ret = -EINVAL;
 513                 dev_err(adev->dev,
 514                         "XGMI: node 0x%llx, can not match hive 0x%llx in the hive list.\n",
 515                         adev->gmc.xgmi.node_id, adev->gmc.xgmi.hive_id);
 516                 goto exit;
 517         }
 518
 519         top_info = &adev->psp.xgmi_context.top_info;
 520
 521         list_add_tail(&adev->gmc.xgmi.head, &hive->device_list);
 522         list_for_each_entry(entry, &hive->device_list, head)
 523                 top_info->nodes[count++].node_id = entry->node_id;
 524         top_info->num_nodes = count;
 525         hive->number_devices = count;
 526
 527         task_barrier_add_task(&hive->tb);
 528
 529         if (amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_PSP)) {
 530                 list_for_each_entry(tmp_adev, &hive->device_list, gmc.xgmi.head) {
 531                         /* update node list for other device in the hive */
 532                         if (tmp_adev != adev) {
 533                                 top_info = &tmp_adev->psp.xgmi_context.top_info;
 534                                 top_info->nodes[count - 1].node_id =
 535                                         adev->gmc.xgmi.node_id;
 536                                 top_info->num_nodes = count;
 537                         }
 538                         ret = amdgpu_xgmi_update_topology(hive, tmp_adev);
 539                         if (ret)
 540                                 goto exit;
 541                 }
 542
 543                 /* get latest topology info for each device from psp */
 544                 list_for_each_entry(tmp_adev, &hive->device_list, gmc.xgmi.head) {
 545                         ret = psp_xgmi_get_topology_info(&tmp_adev->psp, count,
 546                                         &tmp_adev->psp.xgmi_context.top_info);
 547                         if (ret) {
 548                                 dev_err(tmp_adev->dev,
 549                                         "XGMI: Get topology failure on device %llx, hive %llx, ret %d",
 550                                         tmp_adev->gmc.xgmi.node_id,
 551                                         tmp_adev->gmc.xgmi.hive_id, ret);
 552                                 /* To do : continue with some node failed or disable the whole hive */
 553                                 goto exit;
 554                         }
 555                 }
 556         }
 557
 558         if (!ret)
 559                 ret = amdgpu_xgmi_sysfs_add_dev_info(adev, hive);
 560
 561
 562         mutex_unlock(&hive->hive_lock);
 563 exit:
 564         if (!ret)
 565                 dev_info(adev->dev, "XGMI: Add node %d, hive 0x%llx.\n",
 566                          adev->gmc.xgmi.physical_node_id, adev->gmc.xgmi.hive_id);
 567         else
 568                 dev_err(adev->dev, "XGMI: Failed to add node %d, hive 0x%llx ret: %d\n",
 569                         adev->gmc.xgmi.physical_node_id, adev->gmc.xgmi.hive_id,
 570                         ret);
 571
 572         return ret;
 573 }
 574
 575 int amdgpu_xgmi_remove_device(struct amdgpu_device *adev)
 576 {
 577         struct amdgpu_hive_info *hive;
 578
 579         if (!adev->gmc.xgmi.supported)
 580                 return -EINVAL;
 581
 582         hive = amdgpu_get_xgmi_hive(adev, 1);
 583         if (!hive)
 584                 return -EINVAL;
 585
 586         if (!(hive->number_devices--)) {
 587                 amdgpu_xgmi_sysfs_destroy(adev, hive);
 588                 mutex_destroy(&hive->hive_lock);
 589                 mutex_destroy(&hive->reset_lock);
 590         } else {
 591                 task_barrier_rem_task(&hive->tb);
 592                 amdgpu_xgmi_sysfs_rem_dev_info(adev, hive);
 593                 mutex_unlock(&hive->hive_lock);
 594         }
 595
 596         return psp_xgmi_terminate(&adev->psp);
 597 }
 598
 599 int amdgpu_xgmi_ras_late_init(struct amdgpu_device *adev)
 600 {
 601         int r;
 602         struct ras_ih_if ih_info = {
 603                 .cb = NULL,
 604         };
 605         struct ras_fs_if fs_info = {
 606                 .sysfs_name = "xgmi_wafl_err_count",
 607         };
 608
 609         if (!adev->gmc.xgmi.supported ||
 610             adev->gmc.xgmi.num_physical_nodes == 0)
 611                 return 0;
 612
 613         amdgpu_xgmi_reset_ras_error_count(adev);
 614
 615         if (!adev->gmc.xgmi.ras_if) {
 616                 adev->gmc.xgmi.ras_if = kmalloc(sizeof(struct ras_common_if), GFP_KERNEL);
 617                 if (!adev->gmc.xgmi.ras_if)
 618                         return -ENOMEM;
 619                 adev->gmc.xgmi.ras_if->block = AMDGPU_RAS_BLOCK__XGMI_WAFL;
 620                 adev->gmc.xgmi.ras_if->type = AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE;
 621                 adev->gmc.xgmi.ras_if->sub_block_index = 0;
 622                 strcpy(adev->gmc.xgmi.ras_if->name, "xgmi_wafl");
 623         }
 624         ih_info.head = fs_info.head = *adev->gmc.xgmi.ras_if;
 625         r = amdgpu_ras_late_init(adev, adev->gmc.xgmi.ras_if,
 626                                  &fs_info, &ih_info);
 627         if (r || !amdgpu_ras_is_supported(adev, adev->gmc.xgmi.ras_if->block)) {
 628                 kfree(adev->gmc.xgmi.ras_if);
 629                 adev->gmc.xgmi.ras_if = NULL;
 630         }
 631
 632         return r;
 633 }
 634
 635 void amdgpu_xgmi_ras_fini(struct amdgpu_device *adev)
 636 {
 637         if (amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__XGMI_WAFL) &&
 638                         adev->gmc.xgmi.ras_if) {
 639                 struct ras_common_if *ras_if = adev->gmc.xgmi.ras_if;
 640                 struct ras_ih_if ih_info = {
 641                         .cb = NULL,
 642                 };
 643
 644                 amdgpu_ras_late_fini(adev, ras_if, &ih_info);
 645                 kfree(ras_if);
 646         }
 647 }
 648
 649 uint64_t amdgpu_xgmi_get_relative_phy_addr(struct amdgpu_device *adev,
 650                                            uint64_t addr)
 651 {
 652         uint32_t df_inst_id;
 653         uint64_t dram_base_addr = 0;
 654         const struct amdgpu_df_funcs *df_funcs = adev->df.funcs;
 655
 656         if ((!df_funcs)                 ||
 657             (!df_funcs->get_df_inst_id) ||
 658             (!df_funcs->get_dram_base_addr)) {
 659                 dev_warn(adev->dev,
 660                          "XGMI: relative phy_addr algorithm is not supported\n");
 661                 return addr;
 662         }
 663
 664         if (amdgpu_dpm_set_df_cstate(adev, DF_CSTATE_DISALLOW)) {
 665                 dev_warn(adev->dev,
 666                          "failed to disable DF-Cstate, DF register may not be accessible\n");
 667                 return addr;
 668         }
 669
 670         df_inst_id = df_funcs->get_df_inst_id(adev);
 671         dram_base_addr = df_funcs->get_dram_base_addr(adev, df_inst_id);
 672
 673         if (amdgpu_dpm_set_df_cstate(adev, DF_CSTATE_ALLOW))
 674                 dev_warn(adev->dev, "failed to enable DF-Cstate\n");
 675
 676         return addr + dram_base_addr;
 677 }
 678
 679 static void pcs_clear_status(struct amdgpu_device *adev, uint32_t pcs_status_reg)
 680 {
 681         WREG32_PCIE(pcs_status_reg, 0xFFFFFFFF);
 682         WREG32_PCIE(pcs_status_reg, 0);
 683 }
 684
 685 void amdgpu_xgmi_reset_ras_error_count(struct amdgpu_device *adev)
 686 {
 687         uint32_t i;
 688
 689         switch (adev->asic_type) {
 690         case CHIP_ARCTURUS:
 691                 for (i = 0; i < ARRAY_SIZE(xgmi_pcs_err_status_reg_arct); i++)
 692                         pcs_clear_status(adev,
 693                                          xgmi_pcs_err_status_reg_arct[i]);
 694                 break;
 695         case CHIP_VEGA20:
 696                 for (i = 0; i < ARRAY_SIZE(xgmi_pcs_err_status_reg_vg20); i++)
 697                         pcs_clear_status(adev,
 698                                          xgmi_pcs_err_status_reg_vg20[i]);
 699                 break;
 700         default:
 701                 break;
 702         }
 703 }
 704
 705 static int amdgpu_xgmi_query_pcs_error_status(struct amdgpu_device *adev,
 706                                               uint32_t value,
 707                                               uint32_t *ue_count,
 708                                               uint32_t *ce_count,
 709                                               bool is_xgmi_pcs)
 710 {
 711         int i;
 712         int ue_cnt;
 713
 714         if (is_xgmi_pcs) {
 715                 /* query xgmi pcs error status,
 716                  * only ue is supported */
 717                 for (i = 0; i < ARRAY_SIZE(xgmi_pcs_ras_fields); i ++) {
 718                         ue_cnt = (value &
 719                                   xgmi_pcs_ras_fields[i].pcs_err_mask) >>
 720                                   xgmi_pcs_ras_fields[i].pcs_err_shift;
 721                         if (ue_cnt) {
 722                                 dev_info(adev->dev, "%s detected\n",
 723                                          xgmi_pcs_ras_fields[i].err_name);
 724                                 *ue_count += ue_cnt;
 725                         }
 726                 }
 727         } else {
 728                 /* query wafl pcs error status,
 729                  * only ue is supported */
 730                 for (i = 0; i < ARRAY_SIZE(wafl_pcs_ras_fields); i++) {
 731                         ue_cnt = (value &
 732                                   wafl_pcs_ras_fields[i].pcs_err_mask) >>
 733                                   wafl_pcs_ras_fields[i].pcs_err_shift;
 734                         if (ue_cnt) {
 735                                 dev_info(adev->dev, "%s detected\n",
 736                                          wafl_pcs_ras_fields[i].err_name);
 737                                 *ue_count += ue_cnt;
 738                         }
 739                 }
 740         }
 741
 742         return 0;
 743 }
 744
 745 int amdgpu_xgmi_query_ras_error_count(struct amdgpu_device *adev,
 746                                       void *ras_error_status)
 747 {
 748         struct ras_err_data *err_data = (struct ras_err_data *)ras_error_status;
 749         int i;
 750         uint32_t data;
 751         uint32_t ue_cnt = 0, ce_cnt = 0;
 752
 753         if (!amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__XGMI_WAFL))
 754                 return -EINVAL;
 755
 756         err_data->ue_count = 0;
 757         err_data->ce_count = 0;
 758
 759         switch (adev->asic_type) {
 760         case CHIP_ARCTURUS:
 761                 /* check xgmi pcs error */
 762                 for (i = 0; i < ARRAY_SIZE(xgmi_pcs_err_status_reg_arct); i++) {
 763                         data = RREG32_PCIE(xgmi_pcs_err_status_reg_arct[i]);
 764                         if (data)
 765                                 amdgpu_xgmi_query_pcs_error_status(adev,
 766                                                 data, &ue_cnt, &ce_cnt, true);
 767                 }
 768                 /* check wafl pcs error */
 769                 for (i = 0; i < ARRAY_SIZE(wafl_pcs_err_status_reg_arct); i++) {
 770                         data = RREG32_PCIE(wafl_pcs_err_status_reg_arct[i]);
 771                         if (data)
 772                                 amdgpu_xgmi_query_pcs_error_status(adev,
 773                                                 data, &ue_cnt, &ce_cnt, false);
 774                 }
 775                 break;
 776         case CHIP_VEGA20:
 777         default:
 778                 /* check xgmi pcs error */
 779                 for (i = 0; i < ARRAY_SIZE(xgmi_pcs_err_status_reg_vg20); i++) {
 780                         data = RREG32_PCIE(xgmi_pcs_err_status_reg_vg20[i]);
 781                         if (data)
 782                                 amdgpu_xgmi_query_pcs_error_status(adev,
 783                                                 data, &ue_cnt, &ce_cnt, true);
 784                 }
 785                 /* check wafl pcs error */
 786                 for (i = 0; i < ARRAY_SIZE(wafl_pcs_err_status_reg_vg20); i++) {
 787                         data = RREG32_PCIE(wafl_pcs_err_status_reg_vg20[i]);
 788                         if (data)
 789                                 amdgpu_xgmi_query_pcs_error_status(adev,
 790                                                 data, &ue_cnt, &ce_cnt, false);
 791                 }
 792                 break;
 793         }
 794
 795         amdgpu_xgmi_reset_ras_error_count(adev);
 796
 797         err_data->ue_count += ue_cnt;
 798         err_data->ce_count += ce_cnt;
 799
 800         return 0;
 801 }