2 * Copyright 2019 Advanced Micro Devices, Inc.
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23 #include "amdgpu_vm.h"
24 #include "amdgpu_job.h"
25 #include "amdgpu_object.h"
26 #include "amdgpu_trace.h"
28 #define AMDGPU_VM_SDMA_MIN_NUM_DW 256u
29 #define AMDGPU_VM_SDMA_MAX_NUM_DW (16u * 1024u)
32 * amdgpu_vm_sdma_map_table - make sure new PDs/PTs are GTT mapped
34 * @table: newly allocated or validated PD/PT
36 static int amdgpu_vm_sdma_map_table(struct amdgpu_bo_vm *table)
40 r = amdgpu_ttm_alloc_gart(&table->bo.tbo);
45 r = amdgpu_ttm_alloc_gart(&table->shadow->tbo);
51 * amdgpu_vm_sdma_prepare - prepare SDMA command submission
53 * @p: see amdgpu_vm_update_params definition
54 * @resv: reservation object with embedded fence
55 * @sync_mode: synchronization mode
58 * Negativ errno, 0 for success.
60 static int amdgpu_vm_sdma_prepare(struct amdgpu_vm_update_params *p,
61 struct dma_resv *resv,
62 enum amdgpu_sync_mode sync_mode)
64 enum amdgpu_ib_pool_type pool = p->immediate ? AMDGPU_IB_POOL_IMMEDIATE
65 : AMDGPU_IB_POOL_DELAYED;
66 unsigned int ndw = AMDGPU_VM_SDMA_MIN_NUM_DW;
69 r = amdgpu_job_alloc_with_ib(p->adev, ndw * 4, pool, &p->job);
78 return amdgpu_sync_resv(p->adev, &p->job->sync, resv, sync_mode, p->vm);
82 * amdgpu_vm_sdma_commit - commit SDMA command submission
84 * @p: see amdgpu_vm_update_params definition
85 * @fence: resulting fence
88 * Negativ errno, 0 for success.
90 static int amdgpu_vm_sdma_commit(struct amdgpu_vm_update_params *p,
91 struct dma_fence **fence)
93 struct amdgpu_ib *ib = p->job->ibs;
94 struct drm_sched_entity *entity;
95 struct amdgpu_ring *ring;
99 entity = p->immediate ? &p->vm->immediate : &p->vm->delayed;
100 ring = container_of(entity->rq->sched, struct amdgpu_ring, sched);
102 WARN_ON(ib->length_dw == 0);
103 amdgpu_ring_pad_ib(ring, ib);
104 WARN_ON(ib->length_dw > p->num_dw_left);
105 r = amdgpu_job_submit(p->job, entity, AMDGPU_FENCE_OWNER_VM, &f);
110 struct dma_fence *tmp = dma_fence_get(f);
112 swap(p->vm->last_unlocked, tmp);
115 dma_resv_add_fence(p->vm->root.bo->tbo.base.resv, f,
116 DMA_RESV_USAGE_BOOKKEEP);
119 if (fence && !p->immediate)
125 amdgpu_job_free(p->job);
130 * amdgpu_vm_sdma_copy_ptes - copy the PTEs from mapping
132 * @p: see amdgpu_vm_update_params definition
133 * @bo: PD/PT to update
134 * @pe: addr of the page entry
135 * @count: number of page entries to copy
137 * Traces the parameters and calls the DMA function to copy the PTEs.
139 static void amdgpu_vm_sdma_copy_ptes(struct amdgpu_vm_update_params *p,
140 struct amdgpu_bo *bo, uint64_t pe,
143 struct amdgpu_ib *ib = p->job->ibs;
144 uint64_t src = ib->gpu_addr;
146 src += p->num_dw_left * 4;
148 pe += amdgpu_gmc_sign_extend(amdgpu_bo_gpu_offset_no_check(bo));
149 trace_amdgpu_vm_copy_ptes(pe, src, count, p->immediate);
151 amdgpu_vm_copy_pte(p->adev, ib, pe, src, count);
155 * amdgpu_vm_sdma_set_ptes - helper to call the right asic function
157 * @p: see amdgpu_vm_update_params definition
158 * @bo: PD/PT to update
159 * @pe: byte offset of the PDE/PTE, relative to start of PDB/PTB
160 * @addr: dst addr to write into pe
161 * @count: number of page entries to update
162 * @incr: increase next addr by incr bytes
163 * @flags: hw access flags
165 * Traces the parameters and calls the right asic functions
166 * to setup the page table using the DMA.
168 static void amdgpu_vm_sdma_set_ptes(struct amdgpu_vm_update_params *p,
169 struct amdgpu_bo *bo, uint64_t pe,
170 uint64_t addr, unsigned count,
171 uint32_t incr, uint64_t flags)
173 struct amdgpu_ib *ib = p->job->ibs;
175 pe += amdgpu_gmc_sign_extend(amdgpu_bo_gpu_offset_no_check(bo));
176 trace_amdgpu_vm_set_ptes(pe, addr, count, incr, flags, p->immediate);
178 amdgpu_vm_write_pte(p->adev, ib, pe, addr | flags,
181 amdgpu_vm_set_pte_pde(p->adev, ib, pe, addr,
187 * amdgpu_vm_sdma_update - execute VM update
189 * @p: see amdgpu_vm_update_params definition
190 * @vmbo: PD/PT to update
191 * @pe: byte offset of the PDE/PTE, relative to start of PDB/PTB
192 * @addr: dst addr to write into pe
193 * @count: number of page entries to update
194 * @incr: increase next addr by incr bytes
195 * @flags: hw access flags
197 * Reserve space in the IB, setup mapping buffer on demand and write commands to
200 static int amdgpu_vm_sdma_update(struct amdgpu_vm_update_params *p,
201 struct amdgpu_bo_vm *vmbo, uint64_t pe,
202 uint64_t addr, unsigned count, uint32_t incr,
205 struct amdgpu_bo *bo = &vmbo->bo;
206 enum amdgpu_ib_pool_type pool = p->immediate ? AMDGPU_IB_POOL_IMMEDIATE
207 : AMDGPU_IB_POOL_DELAYED;
208 struct dma_resv_iter cursor;
209 unsigned int i, ndw, nptes;
210 struct dma_fence *fence;
214 /* Wait for PD/PT moves to be completed */
215 dma_resv_for_each_fence(&cursor, bo->tbo.base.resv,
216 DMA_RESV_USAGE_KERNEL, fence) {
217 r = amdgpu_sync_fence(&p->job->sync, fence);
223 ndw = p->num_dw_left;
224 ndw -= p->job->ibs->length_dw;
227 r = amdgpu_vm_sdma_commit(p, NULL);
231 /* estimate how many dw we need */
235 ndw = max(ndw, AMDGPU_VM_SDMA_MIN_NUM_DW);
236 ndw = min(ndw, AMDGPU_VM_SDMA_MAX_NUM_DW);
238 r = amdgpu_job_alloc_with_ib(p->adev, ndw * 4, pool,
243 p->num_dw_left = ndw;
246 if (!p->pages_addr) {
247 /* set page commands needed */
249 amdgpu_vm_sdma_set_ptes(p, vmbo->shadow, pe, addr,
251 amdgpu_vm_sdma_set_ptes(p, bo, pe, addr, count,
256 /* copy commands needed */
257 ndw -= p->adev->vm_manager.vm_pte_funcs->copy_pte_num_dw *
258 (vmbo->shadow ? 2 : 1);
263 nptes = min(count, ndw / 2);
265 /* Put the PTEs at the end of the IB. */
266 p->num_dw_left -= nptes * 2;
267 pte = (uint64_t *)&(p->job->ibs->ptr[p->num_dw_left]);
268 for (i = 0; i < nptes; ++i, addr += incr) {
269 pte[i] = amdgpu_vm_map_gart(p->pages_addr, addr);
274 amdgpu_vm_sdma_copy_ptes(p, vmbo->shadow, pe, nptes);
275 amdgpu_vm_sdma_copy_ptes(p, bo, pe, nptes);
284 const struct amdgpu_vm_update_funcs amdgpu_vm_sdma_funcs = {
285 .map_table = amdgpu_vm_sdma_map_table,
286 .prepare = amdgpu_vm_sdma_prepare,
287 .update = amdgpu_vm_sdma_update,
288 .commit = amdgpu_vm_sdma_commit