2 * Copyright 2016 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
22 * Authors: Christian König
24 #ifndef __AMDGPU_VM_H__
25 #define __AMDGPU_VM_H__
27 #include <linux/idr.h>
28 #include <linux/kfifo.h>
29 #include <linux/rbtree.h>
30 #include <drm/gpu_scheduler.h>
31 #include <drm/drm_file.h>
32 #include <drm/ttm/ttm_bo_driver.h>
33 #include <linux/sched/mm.h>
35 #include "amdgpu_sync.h"
36 #include "amdgpu_ring.h"
37 #include "amdgpu_ids.h"
41 struct amdgpu_bo_list_entry;
47 /* Maximum number of PTEs the hardware can write with one command */
48 #define AMDGPU_VM_MAX_UPDATE_SIZE 0x3FFFF
50 /* number of entries in page table */
51 #define AMDGPU_VM_PTE_COUNT(adev) (1 << (adev)->vm_manager.block_size)
53 #define AMDGPU_PTE_VALID (1ULL << 0)
54 #define AMDGPU_PTE_SYSTEM (1ULL << 1)
55 #define AMDGPU_PTE_SNOOPED (1ULL << 2)
58 #define AMDGPU_PTE_TMZ (1ULL << 3)
61 #define AMDGPU_PTE_EXECUTABLE (1ULL << 4)
63 #define AMDGPU_PTE_READABLE (1ULL << 5)
64 #define AMDGPU_PTE_WRITEABLE (1ULL << 6)
66 #define AMDGPU_PTE_FRAG(x) ((x & 0x1fULL) << 7)
68 /* TILED for VEGA10, reserved for older ASICs */
69 #define AMDGPU_PTE_PRT (1ULL << 51)
71 /* PDE is handled as PTE for VEGA10 */
72 #define AMDGPU_PDE_PTE (1ULL << 54)
74 #define AMDGPU_PTE_LOG (1ULL << 55)
76 /* PTE is handled as PDE for VEGA10 (Translate Further) */
77 #define AMDGPU_PTE_TF (1ULL << 56)
79 /* MALL noalloc for sienna_cichlid, reserved for older ASICs */
80 #define AMDGPU_PTE_NOALLOC (1ULL << 58)
82 /* PDE Block Fragment Size for VEGA10 */
83 #define AMDGPU_PDE_BFS(a) ((uint64_t)a << 59)
87 #define AMDGPU_PTE_MTYPE_VG10(a) ((uint64_t)(a) << 57)
88 #define AMDGPU_PTE_MTYPE_VG10_MASK AMDGPU_PTE_MTYPE_VG10(3ULL)
90 #define AMDGPU_MTYPE_NC 0
91 #define AMDGPU_MTYPE_CC 2
93 #define AMDGPU_PTE_DEFAULT_ATC (AMDGPU_PTE_SYSTEM \
94 | AMDGPU_PTE_SNOOPED \
95 | AMDGPU_PTE_EXECUTABLE \
96 | AMDGPU_PTE_READABLE \
97 | AMDGPU_PTE_WRITEABLE \
98 | AMDGPU_PTE_MTYPE_VG10(AMDGPU_MTYPE_CC))
101 #define AMDGPU_PTE_MTYPE_NV10(a) ((uint64_t)(a) << 48)
102 #define AMDGPU_PTE_MTYPE_NV10_MASK AMDGPU_PTE_MTYPE_NV10(7ULL)
104 /* How to program VM fault handling */
105 #define AMDGPU_VM_FAULT_STOP_NEVER 0
106 #define AMDGPU_VM_FAULT_STOP_FIRST 1
107 #define AMDGPU_VM_FAULT_STOP_ALWAYS 2
109 /* Reserve 4MB VRAM for page tables */
110 #define AMDGPU_VM_RESERVED_VRAM (8ULL << 20)
112 /* max number of VMHUB */
113 #define AMDGPU_MAX_VMHUBS 3
114 #define AMDGPU_GFXHUB_0 0
115 #define AMDGPU_MMHUB_0 1
116 #define AMDGPU_MMHUB_1 2
118 /* Reserve 2MB at top/bottom of address space for kernel use */
119 #define AMDGPU_VA_RESERVED_SIZE (2ULL << 20)
121 /* max vmids dedicated for process */
122 #define AMDGPU_VM_MAX_RESERVED_VMID 1
124 /* See vm_update_mode */
125 #define AMDGPU_VM_USE_CPU_FOR_GFX (1 << 0)
126 #define AMDGPU_VM_USE_CPU_FOR_COMPUTE (1 << 1)
128 /* VMPT level enumerate, and the hiberachy is:
129 * PDB2->PDB1->PDB0->PTB
131 enum amdgpu_vm_level {
138 /* base structure for tracking BO usage in a VM */
139 struct amdgpu_vm_bo_base {
140 /* constant after initialization */
141 struct amdgpu_vm *vm;
142 struct amdgpu_bo *bo;
144 /* protected by bo being reserved */
145 struct amdgpu_vm_bo_base *next;
147 /* protected by spinlock */
148 struct list_head vm_status;
150 /* protected by the BO being reserved */
154 struct amdgpu_vm_pt {
155 struct amdgpu_vm_bo_base base;
157 /* array of page tables, one for each directory entry */
158 struct amdgpu_vm_pt *entries;
161 /* provided by hw blocks that can write ptes, e.g., sdma */
162 struct amdgpu_vm_pte_funcs {
163 /* number of dw to reserve per operation */
164 unsigned copy_pte_num_dw;
166 /* copy pte entries from GART */
167 void (*copy_pte)(struct amdgpu_ib *ib,
168 uint64_t pe, uint64_t src,
171 /* write pte one entry at a time with addr mapping */
172 void (*write_pte)(struct amdgpu_ib *ib, uint64_t pe,
173 uint64_t value, unsigned count,
175 /* for linear pte/pde updates without addr mapping */
176 void (*set_pte_pde)(struct amdgpu_ib *ib,
178 uint64_t addr, unsigned count,
179 uint32_t incr, uint64_t flags);
182 struct amdgpu_task_info {
183 char process_name[TASK_COMM_LEN];
184 char task_name[TASK_COMM_LEN];
190 * struct amdgpu_vm_update_params
192 * Encapsulate some VM table update parameters to reduce
193 * the number of function parameters
196 struct amdgpu_vm_update_params {
199 * @adev: amdgpu device we do this update for
201 struct amdgpu_device *adev;
204 * @vm: optional amdgpu_vm we do this update for
206 struct amdgpu_vm *vm;
209 * @immediate: if changes should be made immediately
214 * @unlocked: true if the root BO is not locked
221 * DMA addresses to use for mapping
223 dma_addr_t *pages_addr;
226 * @job: job to used for hw submission
228 struct amdgpu_job *job;
231 * @num_dw_left: number of dw left for the IB
233 unsigned int num_dw_left;
236 struct amdgpu_vm_update_funcs {
237 int (*map_table)(struct amdgpu_bo *bo);
238 int (*prepare)(struct amdgpu_vm_update_params *p, struct dma_resv *resv,
239 enum amdgpu_sync_mode sync_mode);
240 int (*update)(struct amdgpu_vm_update_params *p,
241 struct amdgpu_bo *bo, uint64_t pe, uint64_t addr,
242 unsigned count, uint32_t incr, uint64_t flags);
243 int (*commit)(struct amdgpu_vm_update_params *p,
244 struct dma_fence **fence);
248 /* tree of virtual addresses mapped */
249 struct rb_root_cached va;
251 /* Lock to prevent eviction while we are updating page tables
252 * use vm_eviction_lock/unlock(vm)
254 struct mutex eviction_lock;
256 unsigned int saved_flags;
258 /* BOs who needs a validation */
259 struct list_head evicted;
261 /* PT BOs which relocated and their parent need an update */
262 struct list_head relocated;
264 /* per VM BOs moved, but not yet updated in the PT */
265 struct list_head moved;
267 /* All BOs of this VM not currently in the state machine */
268 struct list_head idle;
270 /* regular invalidated BOs, but not yet updated in the PT */
271 struct list_head invalidated;
272 spinlock_t invalidated_lock;
274 /* BO mappings freed, but not yet updated in the PT */
275 struct list_head freed;
277 /* BOs which are invalidated, has been updated in the PTs */
278 struct list_head done;
280 /* contains the page directory */
281 struct amdgpu_vm_pt root;
282 struct dma_fence *last_update;
284 /* Scheduler entities for page table updates */
285 struct drm_sched_entity immediate;
286 struct drm_sched_entity delayed;
288 /* Last unlocked submission to the scheduler entities */
289 struct dma_fence *last_unlocked;
292 /* dedicated to vm */
293 struct amdgpu_vmid *reserved_vmid[AMDGPU_MAX_VMHUBS];
295 /* Flag to indicate if VM tables are updated by CPU or GPU (SDMA) */
296 bool use_cpu_for_update;
298 /* Functions to use for VM table updates */
299 const struct amdgpu_vm_update_funcs *update_funcs;
301 /* Flag to indicate ATS support from PTE for GFX9 */
302 bool pte_support_ats;
304 /* Up to 128 pending retry page faults */
305 DECLARE_KFIFO(faults, u64, 128);
307 /* Points to the KFD process VM info */
308 struct amdkfd_process_info *process_info;
310 /* List node in amdkfd_process_info.vm_list_head */
311 struct list_head vm_list_node;
313 /* Valid while the PD is reserved or fenced */
314 uint64_t pd_phys_addr;
316 /* Some basic info about the task */
317 struct amdgpu_task_info task_info;
319 /* Store positions of group of BOs */
320 struct ttm_lru_bulk_move lru_bulk_move;
321 /* mark whether can do the bulk move */
323 /* Flag to indicate if VM is used for compute */
324 bool is_compute_context;
327 struct amdgpu_vm_manager {
328 /* Handling of VMIDs */
329 struct amdgpu_vmid_mgr id_mgr[AMDGPU_MAX_VMHUBS];
330 unsigned int first_kfd_vmid;
331 bool concurrent_flush;
333 /* Handling of VM fences */
335 unsigned seqno[AMDGPU_MAX_RINGS];
340 uint32_t fragment_size;
341 enum amdgpu_vm_level root_level;
342 /* vram base address for page table entry */
343 u64 vram_base_offset;
344 /* vm pte handling */
345 const struct amdgpu_vm_pte_funcs *vm_pte_funcs;
346 struct drm_gpu_scheduler *vm_pte_scheds[AMDGPU_MAX_RINGS];
347 unsigned vm_pte_num_scheds;
348 struct amdgpu_ring *page_fault;
350 /* partial resident texture handling */
352 atomic_t num_prt_users;
354 /* controls how VM page tables are updated for Graphics and Compute.
355 * BIT0[= 0] Graphics updated by SDMA [= 1] by CPU
356 * BIT1[= 0] Compute updated by SDMA [= 1] by CPU
360 /* PASID to VM mapping, will be used in interrupt context to
361 * look up VM of a page fault
363 struct idr pasid_idr;
364 spinlock_t pasid_lock;
367 struct amdgpu_bo_va_mapping;
369 #define amdgpu_vm_copy_pte(adev, ib, pe, src, count) ((adev)->vm_manager.vm_pte_funcs->copy_pte((ib), (pe), (src), (count)))
370 #define amdgpu_vm_write_pte(adev, ib, pe, value, count, incr) ((adev)->vm_manager.vm_pte_funcs->write_pte((ib), (pe), (value), (count), (incr)))
371 #define amdgpu_vm_set_pte_pde(adev, ib, pe, addr, count, incr, flags) ((adev)->vm_manager.vm_pte_funcs->set_pte_pde((ib), (pe), (addr), (count), (incr), (flags)))
373 extern const struct amdgpu_vm_update_funcs amdgpu_vm_cpu_funcs;
374 extern const struct amdgpu_vm_update_funcs amdgpu_vm_sdma_funcs;
376 void amdgpu_vm_manager_init(struct amdgpu_device *adev);
377 void amdgpu_vm_manager_fini(struct amdgpu_device *adev);
379 long amdgpu_vm_wait_idle(struct amdgpu_vm *vm, long timeout);
380 int amdgpu_vm_init(struct amdgpu_device *adev, struct amdgpu_vm *vm, u32 pasid);
381 int amdgpu_vm_make_compute(struct amdgpu_device *adev, struct amdgpu_vm *vm, u32 pasid);
382 void amdgpu_vm_release_compute(struct amdgpu_device *adev, struct amdgpu_vm *vm);
383 void amdgpu_vm_fini(struct amdgpu_device *adev, struct amdgpu_vm *vm);
384 void amdgpu_vm_get_pd_bo(struct amdgpu_vm *vm,
385 struct list_head *validated,
386 struct amdgpu_bo_list_entry *entry);
387 bool amdgpu_vm_ready(struct amdgpu_vm *vm);
388 int amdgpu_vm_validate_pt_bos(struct amdgpu_device *adev, struct amdgpu_vm *vm,
389 int (*callback)(void *p, struct amdgpu_bo *bo),
391 int amdgpu_vm_flush(struct amdgpu_ring *ring, struct amdgpu_job *job, bool need_pipe_sync);
392 int amdgpu_vm_update_pdes(struct amdgpu_device *adev,
393 struct amdgpu_vm *vm, bool immediate);
394 int amdgpu_vm_clear_freed(struct amdgpu_device *adev,
395 struct amdgpu_vm *vm,
396 struct dma_fence **fence);
397 int amdgpu_vm_handle_moved(struct amdgpu_device *adev,
398 struct amdgpu_vm *vm);
399 int amdgpu_vm_bo_update_mapping(struct amdgpu_device *adev,
400 struct amdgpu_device *bo_adev,
401 struct amdgpu_vm *vm, bool immediate,
402 bool unlocked, struct dma_resv *resv,
403 uint64_t start, uint64_t last,
404 uint64_t flags, uint64_t offset,
405 struct drm_mm_node *nodes,
406 dma_addr_t *pages_addr,
407 struct dma_fence **fence);
408 int amdgpu_vm_bo_update(struct amdgpu_device *adev,
409 struct amdgpu_bo_va *bo_va,
411 bool amdgpu_vm_evictable(struct amdgpu_bo *bo);
412 void amdgpu_vm_bo_invalidate(struct amdgpu_device *adev,
413 struct amdgpu_bo *bo, bool evicted);
414 uint64_t amdgpu_vm_map_gart(const dma_addr_t *pages_addr, uint64_t addr);
415 struct amdgpu_bo_va *amdgpu_vm_bo_find(struct amdgpu_vm *vm,
416 struct amdgpu_bo *bo);
417 struct amdgpu_bo_va *amdgpu_vm_bo_add(struct amdgpu_device *adev,
418 struct amdgpu_vm *vm,
419 struct amdgpu_bo *bo);
420 int amdgpu_vm_bo_map(struct amdgpu_device *adev,
421 struct amdgpu_bo_va *bo_va,
422 uint64_t addr, uint64_t offset,
423 uint64_t size, uint64_t flags);
424 int amdgpu_vm_bo_replace_map(struct amdgpu_device *adev,
425 struct amdgpu_bo_va *bo_va,
426 uint64_t addr, uint64_t offset,
427 uint64_t size, uint64_t flags);
428 int amdgpu_vm_bo_unmap(struct amdgpu_device *adev,
429 struct amdgpu_bo_va *bo_va,
431 int amdgpu_vm_bo_clear_mappings(struct amdgpu_device *adev,
432 struct amdgpu_vm *vm,
433 uint64_t saddr, uint64_t size);
434 struct amdgpu_bo_va_mapping *amdgpu_vm_bo_lookup_mapping(struct amdgpu_vm *vm,
436 void amdgpu_vm_bo_trace_cs(struct amdgpu_vm *vm, struct ww_acquire_ctx *ticket);
437 void amdgpu_vm_bo_rmv(struct amdgpu_device *adev,
438 struct amdgpu_bo_va *bo_va);
439 void amdgpu_vm_adjust_size(struct amdgpu_device *adev, uint32_t min_vm_size,
440 uint32_t fragment_size_default, unsigned max_level,
442 int amdgpu_vm_ioctl(struct drm_device *dev, void *data, struct drm_file *filp);
443 bool amdgpu_vm_need_pipeline_sync(struct amdgpu_ring *ring,
444 struct amdgpu_job *job);
445 void amdgpu_vm_check_compute_bug(struct amdgpu_device *adev);
447 void amdgpu_vm_get_task_info(struct amdgpu_device *adev, u32 pasid,
448 struct amdgpu_task_info *task_info);
449 bool amdgpu_vm_handle_fault(struct amdgpu_device *adev, u32 pasid,
452 void amdgpu_vm_set_task_info(struct amdgpu_vm *vm);
454 void amdgpu_vm_move_to_lru_tail(struct amdgpu_device *adev,
455 struct amdgpu_vm *vm);
456 void amdgpu_vm_del_from_lru_notify(struct ttm_buffer_object *bo);
458 #if defined(CONFIG_DEBUG_FS)
459 void amdgpu_debugfs_vm_bo_info(struct amdgpu_vm *vm, struct seq_file *m);