2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
24 * Authors: Dave Airlie
29 #include <linux/dma-fence-array.h>
30 #include <linux/interval_tree_generic.h>
31 #include <linux/idr.h>
32 #include <linux/dma-buf.h>
34 #include <drm/amdgpu_drm.h>
35 #include <drm/drm_drv.h>
36 #include <drm/ttm/ttm_tt.h>
37 #include <drm/drm_exec.h>
39 #include "amdgpu_trace.h"
40 #include "amdgpu_amdkfd.h"
41 #include "amdgpu_gmc.h"
42 #include "amdgpu_xgmi.h"
43 #include "amdgpu_dma_buf.h"
44 #include "amdgpu_res_cursor.h"
50 * GPUVM is the MMU functionality provided on the GPU.
51 * GPUVM is similar to the legacy GART on older asics, however
52 * rather than there being a single global GART table
53 * for the entire GPU, there can be multiple GPUVM page tables active
54 * at any given time. The GPUVM page tables can contain a mix
55 * VRAM pages and system pages (both memory and MMIO) and system pages
56 * can be mapped as snooped (cached system pages) or unsnooped
57 * (uncached system pages).
59 * Each active GPUVM has an ID associated with it and there is a page table
60 * linked with each VMID. When executing a command buffer,
61 * the kernel tells the engine what VMID to use for that command
62 * buffer. VMIDs are allocated dynamically as commands are submitted.
63 * The userspace drivers maintain their own address space and the kernel
64 * sets up their pages tables accordingly when they submit their
65 * command buffers and a VMID is assigned.
66 * The hardware supports up to 16 active GPUVMs at any given time.
68 * Each GPUVM is represented by a 1-2 or 1-5 level page table, depending
69 * on the ASIC family. GPUVM supports RWX attributes on each page as well
70 * as other features such as encryption and caching attributes.
72 * VMID 0 is special. It is the GPUVM used for the kernel driver. In
73 * addition to an aperture managed by a page table, VMID 0 also has
74 * several other apertures. There is an aperture for direct access to VRAM
75 * and there is a legacy AGP aperture which just forwards accesses directly
76 * to the matching system physical addresses (or IOVAs when an IOMMU is
77 * present). These apertures provide direct access to these memories without
78 * incurring the overhead of a page table. VMID 0 is used by the kernel
79 * driver for tasks like memory management.
81 * GPU clients (i.e., engines on the GPU) use GPUVM VMIDs to access memory.
82 * For user applications, each application can have their own unique GPUVM
83 * address space. The application manages the address space and the kernel
84 * driver manages the GPUVM page tables for each process. If an GPU client
85 * accesses an invalid page, it will generate a GPU page fault, similar to
86 * accessing an invalid page on a CPU.
89 #define START(node) ((node)->start)
90 #define LAST(node) ((node)->last)
92 INTERVAL_TREE_DEFINE(struct amdgpu_bo_va_mapping, rb, uint64_t, __subtree_last,
93 START, LAST, static, amdgpu_vm_it)
99 * struct amdgpu_prt_cb - Helper to disable partial resident texture feature from a fence callback
101 struct amdgpu_prt_cb {
104 * @adev: amdgpu device
106 struct amdgpu_device *adev;
111 struct dma_fence_cb cb;
115 * struct amdgpu_vm_tlb_seq_struct - Helper to increment the TLB flush sequence
117 struct amdgpu_vm_tlb_seq_struct {
119 * @vm: pointer to the amdgpu_vm structure to set the fence sequence on
121 struct amdgpu_vm *vm;
126 struct dma_fence_cb cb;
130 * amdgpu_vm_set_pasid - manage pasid and vm ptr mapping
132 * @adev: amdgpu_device pointer
133 * @vm: amdgpu_vm pointer
134 * @pasid: the pasid the VM is using on this GPU
136 * Set the pasid this VM is using on this GPU, can also be used to remove the
137 * pasid by passing in zero.
140 int amdgpu_vm_set_pasid(struct amdgpu_device *adev, struct amdgpu_vm *vm,
145 if (vm->pasid == pasid)
149 r = xa_err(xa_erase_irq(&adev->vm_manager.pasids, vm->pasid));
157 r = xa_err(xa_store_irq(&adev->vm_manager.pasids, pasid, vm,
170 * amdgpu_vm_bo_evicted - vm_bo is evicted
172 * @vm_bo: vm_bo which is evicted
174 * State for PDs/PTs and per VM BOs which are not at the location they should
177 static void amdgpu_vm_bo_evicted(struct amdgpu_vm_bo_base *vm_bo)
179 struct amdgpu_vm *vm = vm_bo->vm;
180 struct amdgpu_bo *bo = vm_bo->bo;
183 spin_lock(&vm_bo->vm->status_lock);
184 if (bo->tbo.type == ttm_bo_type_kernel)
185 list_move(&vm_bo->vm_status, &vm->evicted);
187 list_move_tail(&vm_bo->vm_status, &vm->evicted);
188 spin_unlock(&vm_bo->vm->status_lock);
191 * amdgpu_vm_bo_moved - vm_bo is moved
193 * @vm_bo: vm_bo which is moved
195 * State for per VM BOs which are moved, but that change is not yet reflected
196 * in the page tables.
198 static void amdgpu_vm_bo_moved(struct amdgpu_vm_bo_base *vm_bo)
200 spin_lock(&vm_bo->vm->status_lock);
201 list_move(&vm_bo->vm_status, &vm_bo->vm->moved);
202 spin_unlock(&vm_bo->vm->status_lock);
206 * amdgpu_vm_bo_idle - vm_bo is idle
208 * @vm_bo: vm_bo which is now idle
210 * State for PDs/PTs and per VM BOs which have gone through the state machine
213 static void amdgpu_vm_bo_idle(struct amdgpu_vm_bo_base *vm_bo)
215 spin_lock(&vm_bo->vm->status_lock);
216 list_move(&vm_bo->vm_status, &vm_bo->vm->idle);
217 spin_unlock(&vm_bo->vm->status_lock);
218 vm_bo->moved = false;
222 * amdgpu_vm_bo_invalidated - vm_bo is invalidated
224 * @vm_bo: vm_bo which is now invalidated
226 * State for normal BOs which are invalidated and that change not yet reflected
229 static void amdgpu_vm_bo_invalidated(struct amdgpu_vm_bo_base *vm_bo)
231 spin_lock(&vm_bo->vm->status_lock);
232 list_move(&vm_bo->vm_status, &vm_bo->vm->invalidated);
233 spin_unlock(&vm_bo->vm->status_lock);
237 * amdgpu_vm_bo_evicted_user - vm_bo is evicted
239 * @vm_bo: vm_bo which is evicted
241 * State for BOs used by user mode queues which are not at the location they
244 static void amdgpu_vm_bo_evicted_user(struct amdgpu_vm_bo_base *vm_bo)
247 spin_lock(&vm_bo->vm->status_lock);
248 list_move(&vm_bo->vm_status, &vm_bo->vm->evicted_user);
249 spin_unlock(&vm_bo->vm->status_lock);
253 * amdgpu_vm_bo_relocated - vm_bo is reloacted
255 * @vm_bo: vm_bo which is relocated
257 * State for PDs/PTs which needs to update their parent PD.
258 * For the root PD, just move to idle state.
260 static void amdgpu_vm_bo_relocated(struct amdgpu_vm_bo_base *vm_bo)
262 if (vm_bo->bo->parent) {
263 spin_lock(&vm_bo->vm->status_lock);
264 list_move(&vm_bo->vm_status, &vm_bo->vm->relocated);
265 spin_unlock(&vm_bo->vm->status_lock);
267 amdgpu_vm_bo_idle(vm_bo);
272 * amdgpu_vm_bo_done - vm_bo is done
274 * @vm_bo: vm_bo which is now done
276 * State for normal BOs which are invalidated and that change has been updated
279 static void amdgpu_vm_bo_done(struct amdgpu_vm_bo_base *vm_bo)
281 spin_lock(&vm_bo->vm->status_lock);
282 list_move(&vm_bo->vm_status, &vm_bo->vm->done);
283 spin_unlock(&vm_bo->vm->status_lock);
287 * amdgpu_vm_bo_reset_state_machine - reset the vm_bo state machine
288 * @vm: the VM which state machine to reset
290 * Move all vm_bo object in the VM into a state where they will be updated
291 * again during validation.
293 static void amdgpu_vm_bo_reset_state_machine(struct amdgpu_vm *vm)
295 struct amdgpu_vm_bo_base *vm_bo, *tmp;
297 spin_lock(&vm->status_lock);
298 list_splice_init(&vm->done, &vm->invalidated);
299 list_for_each_entry(vm_bo, &vm->invalidated, vm_status)
301 list_for_each_entry_safe(vm_bo, tmp, &vm->idle, vm_status) {
302 struct amdgpu_bo *bo = vm_bo->bo;
305 if (!bo || bo->tbo.type != ttm_bo_type_kernel)
306 list_move(&vm_bo->vm_status, &vm_bo->vm->moved);
308 list_move(&vm_bo->vm_status, &vm_bo->vm->relocated);
310 spin_unlock(&vm->status_lock);
314 * amdgpu_vm_bo_base_init - Adds bo to the list of bos associated with the vm
316 * @base: base structure for tracking BO usage in a VM
317 * @vm: vm to which bo is to be added
318 * @bo: amdgpu buffer object
320 * Initialize a bo_va_base structure and add it to the appropriate lists
323 void amdgpu_vm_bo_base_init(struct amdgpu_vm_bo_base *base,
324 struct amdgpu_vm *vm, struct amdgpu_bo *bo)
329 INIT_LIST_HEAD(&base->vm_status);
333 base->next = bo->vm_bo;
336 if (bo->tbo.base.resv != vm->root.bo->tbo.base.resv)
339 dma_resv_assert_held(vm->root.bo->tbo.base.resv);
341 ttm_bo_set_bulk_move(&bo->tbo, &vm->lru_bulk_move);
342 if (bo->tbo.type == ttm_bo_type_kernel && bo->parent)
343 amdgpu_vm_bo_relocated(base);
345 amdgpu_vm_bo_idle(base);
347 if (bo->preferred_domains &
348 amdgpu_mem_type_to_domain(bo->tbo.resource->mem_type))
352 * we checked all the prerequisites, but it looks like this per vm bo
353 * is currently evicted. add the bo to the evicted list to make sure it
354 * is validated on next vm use to avoid fault.
356 amdgpu_vm_bo_evicted(base);
360 * amdgpu_vm_lock_pd - lock PD in drm_exec
362 * @vm: vm providing the BOs
363 * @exec: drm execution context
364 * @num_fences: number of extra fences to reserve
366 * Lock the VM root PD in the DRM execution context.
368 int amdgpu_vm_lock_pd(struct amdgpu_vm *vm, struct drm_exec *exec,
369 unsigned int num_fences)
371 /* We need at least two fences for the VM PD/PT updates */
372 return drm_exec_prepare_obj(exec, &vm->root.bo->tbo.base,
377 * amdgpu_vm_move_to_lru_tail - move all BOs to the end of LRU
379 * @adev: amdgpu device pointer
380 * @vm: vm providing the BOs
382 * Move all BOs to the end of LRU and remember their positions to put them
385 void amdgpu_vm_move_to_lru_tail(struct amdgpu_device *adev,
386 struct amdgpu_vm *vm)
388 spin_lock(&adev->mman.bdev.lru_lock);
389 ttm_lru_bulk_move_tail(&vm->lru_bulk_move);
390 spin_unlock(&adev->mman.bdev.lru_lock);
393 /* Create scheduler entities for page table updates */
394 static int amdgpu_vm_init_entities(struct amdgpu_device *adev,
395 struct amdgpu_vm *vm)
399 r = drm_sched_entity_init(&vm->immediate, DRM_SCHED_PRIORITY_NORMAL,
400 adev->vm_manager.vm_pte_scheds,
401 adev->vm_manager.vm_pte_num_scheds, NULL);
405 return drm_sched_entity_init(&vm->delayed, DRM_SCHED_PRIORITY_NORMAL,
406 adev->vm_manager.vm_pte_scheds,
407 adev->vm_manager.vm_pte_num_scheds, NULL);
410 drm_sched_entity_destroy(&vm->immediate);
414 /* Destroy the entities for page table updates again */
415 static void amdgpu_vm_fini_entities(struct amdgpu_vm *vm)
417 drm_sched_entity_destroy(&vm->immediate);
418 drm_sched_entity_destroy(&vm->delayed);
422 * amdgpu_vm_generation - return the page table re-generation counter
423 * @adev: the amdgpu_device
424 * @vm: optional VM to check, might be NULL
426 * Returns a page table re-generation token to allow checking if submissions
427 * are still valid to use this VM. The VM parameter might be NULL in which case
428 * just the VRAM lost counter will be used.
430 uint64_t amdgpu_vm_generation(struct amdgpu_device *adev, struct amdgpu_vm *vm)
432 uint64_t result = (u64)atomic_read(&adev->vram_lost_counter) << 32;
437 result += vm->generation;
438 /* Add one if the page tables will be re-generated on next CS */
439 if (drm_sched_entity_error(&vm->delayed))
446 * amdgpu_vm_validate - validate evicted BOs tracked in the VM
448 * @adev: amdgpu device pointer
449 * @vm: vm providing the BOs
450 * @ticket: optional reservation ticket used to reserve the VM
451 * @validate: callback to do the validation
452 * @param: parameter for the validation callback
454 * Validate the page table BOs and per-VM BOs on command submission if
455 * necessary. If a ticket is given, also try to validate evicted user queue
456 * BOs. They must already be reserved with the given ticket.
461 int amdgpu_vm_validate(struct amdgpu_device *adev, struct amdgpu_vm *vm,
462 struct ww_acquire_ctx *ticket,
463 int (*validate)(void *p, struct amdgpu_bo *bo),
466 struct amdgpu_vm_bo_base *bo_base;
467 struct amdgpu_bo *shadow;
468 struct amdgpu_bo *bo;
471 if (drm_sched_entity_error(&vm->delayed)) {
473 amdgpu_vm_bo_reset_state_machine(vm);
474 amdgpu_vm_fini_entities(vm);
475 r = amdgpu_vm_init_entities(adev, vm);
480 spin_lock(&vm->status_lock);
481 while (!list_empty(&vm->evicted)) {
482 bo_base = list_first_entry(&vm->evicted,
483 struct amdgpu_vm_bo_base,
485 spin_unlock(&vm->status_lock);
488 shadow = amdgpu_bo_shadowed(bo);
490 r = validate(param, bo);
494 r = validate(param, shadow);
499 if (bo->tbo.type != ttm_bo_type_kernel) {
500 amdgpu_vm_bo_moved(bo_base);
502 vm->update_funcs->map_table(to_amdgpu_bo_vm(bo));
503 amdgpu_vm_bo_relocated(bo_base);
505 spin_lock(&vm->status_lock);
507 while (ticket && !list_empty(&vm->evicted_user)) {
508 bo_base = list_first_entry(&vm->evicted_user,
509 struct amdgpu_vm_bo_base,
511 spin_unlock(&vm->status_lock);
515 if (dma_resv_locking_ctx(bo->tbo.base.resv) != ticket) {
516 struct amdgpu_task_info *ti = amdgpu_vm_get_task_info_vm(vm);
518 pr_warn_ratelimited("Evicted user BO is not reserved\n");
520 pr_warn_ratelimited("pid %d\n", ti->pid);
521 amdgpu_vm_put_task_info(ti);
527 r = validate(param, bo);
531 amdgpu_vm_bo_invalidated(bo_base);
533 spin_lock(&vm->status_lock);
535 spin_unlock(&vm->status_lock);
537 amdgpu_vm_eviction_lock(vm);
538 vm->evicting = false;
539 amdgpu_vm_eviction_unlock(vm);
545 * amdgpu_vm_ready - check VM is ready for updates
549 * Check if all VM PDs/PTs are ready for updates
552 * True if VM is not evicting.
554 bool amdgpu_vm_ready(struct amdgpu_vm *vm)
559 amdgpu_vm_eviction_lock(vm);
561 amdgpu_vm_eviction_unlock(vm);
563 spin_lock(&vm->status_lock);
564 empty = list_empty(&vm->evicted);
565 spin_unlock(&vm->status_lock);
571 * amdgpu_vm_check_compute_bug - check whether asic has compute vm bug
573 * @adev: amdgpu_device pointer
575 void amdgpu_vm_check_compute_bug(struct amdgpu_device *adev)
577 const struct amdgpu_ip_block *ip_block;
578 bool has_compute_vm_bug;
579 struct amdgpu_ring *ring;
582 has_compute_vm_bug = false;
584 ip_block = amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_GFX);
586 /* Compute has a VM bug for GFX version < 7.
587 Compute has a VM bug for GFX 8 MEC firmware version < 673.*/
588 if (ip_block->version->major <= 7)
589 has_compute_vm_bug = true;
590 else if (ip_block->version->major == 8)
591 if (adev->gfx.mec_fw_version < 673)
592 has_compute_vm_bug = true;
595 for (i = 0; i < adev->num_rings; i++) {
596 ring = adev->rings[i];
597 if (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE)
598 /* only compute rings */
599 ring->has_compute_vm_bug = has_compute_vm_bug;
601 ring->has_compute_vm_bug = false;
606 * amdgpu_vm_need_pipeline_sync - Check if pipe sync is needed for job.
608 * @ring: ring on which the job will be submitted
609 * @job: job to submit
612 * True if sync is needed.
614 bool amdgpu_vm_need_pipeline_sync(struct amdgpu_ring *ring,
615 struct amdgpu_job *job)
617 struct amdgpu_device *adev = ring->adev;
618 unsigned vmhub = ring->vm_hub;
619 struct amdgpu_vmid_mgr *id_mgr = &adev->vm_manager.id_mgr[vmhub];
624 if (job->vm_needs_flush || ring->has_compute_vm_bug)
627 if (ring->funcs->emit_gds_switch && job->gds_switch_needed)
630 if (amdgpu_vmid_had_gpu_reset(adev, &id_mgr->ids[job->vmid]))
637 * amdgpu_vm_flush - hardware flush the vm
639 * @ring: ring to use for flush
641 * @need_pipe_sync: is pipe sync needed
643 * Emit a VM flush when it is necessary.
646 * 0 on success, errno otherwise.
648 int amdgpu_vm_flush(struct amdgpu_ring *ring, struct amdgpu_job *job,
651 struct amdgpu_device *adev = ring->adev;
652 unsigned vmhub = ring->vm_hub;
653 struct amdgpu_vmid_mgr *id_mgr = &adev->vm_manager.id_mgr[vmhub];
654 struct amdgpu_vmid *id = &id_mgr->ids[job->vmid];
655 bool spm_update_needed = job->spm_update_needed;
656 bool gds_switch_needed = ring->funcs->emit_gds_switch &&
657 job->gds_switch_needed;
658 bool vm_flush_needed = job->vm_needs_flush;
659 struct dma_fence *fence = NULL;
660 bool pasid_mapping_needed = false;
664 if (amdgpu_vmid_had_gpu_reset(adev, id)) {
665 gds_switch_needed = true;
666 vm_flush_needed = true;
667 pasid_mapping_needed = true;
668 spm_update_needed = true;
671 mutex_lock(&id_mgr->lock);
672 if (id->pasid != job->pasid || !id->pasid_mapping ||
673 !dma_fence_is_signaled(id->pasid_mapping))
674 pasid_mapping_needed = true;
675 mutex_unlock(&id_mgr->lock);
677 gds_switch_needed &= !!ring->funcs->emit_gds_switch;
678 vm_flush_needed &= !!ring->funcs->emit_vm_flush &&
679 job->vm_pd_addr != AMDGPU_BO_INVALID_OFFSET;
680 pasid_mapping_needed &= adev->gmc.gmc_funcs->emit_pasid_mapping &&
681 ring->funcs->emit_wreg;
683 if (!vm_flush_needed && !gds_switch_needed && !need_pipe_sync)
686 amdgpu_ring_ib_begin(ring);
687 if (ring->funcs->init_cond_exec)
688 patch = amdgpu_ring_init_cond_exec(ring,
689 ring->cond_exe_gpu_addr);
692 amdgpu_ring_emit_pipeline_sync(ring);
694 if (vm_flush_needed) {
695 trace_amdgpu_vm_flush(ring, job->vmid, job->vm_pd_addr);
696 amdgpu_ring_emit_vm_flush(ring, job->vmid, job->vm_pd_addr);
699 if (pasid_mapping_needed)
700 amdgpu_gmc_emit_pasid_mapping(ring, job->vmid, job->pasid);
702 if (spm_update_needed && adev->gfx.rlc.funcs->update_spm_vmid)
703 adev->gfx.rlc.funcs->update_spm_vmid(adev, ring, job->vmid);
705 if (!ring->is_mes_queue && ring->funcs->emit_gds_switch &&
707 amdgpu_ring_emit_gds_switch(ring, job->vmid, job->gds_base,
708 job->gds_size, job->gws_base,
709 job->gws_size, job->oa_base,
713 if (vm_flush_needed || pasid_mapping_needed) {
714 r = amdgpu_fence_emit(ring, &fence, NULL, 0);
719 if (vm_flush_needed) {
720 mutex_lock(&id_mgr->lock);
721 dma_fence_put(id->last_flush);
722 id->last_flush = dma_fence_get(fence);
723 id->current_gpu_reset_count =
724 atomic_read(&adev->gpu_reset_counter);
725 mutex_unlock(&id_mgr->lock);
728 if (pasid_mapping_needed) {
729 mutex_lock(&id_mgr->lock);
730 id->pasid = job->pasid;
731 dma_fence_put(id->pasid_mapping);
732 id->pasid_mapping = dma_fence_get(fence);
733 mutex_unlock(&id_mgr->lock);
735 dma_fence_put(fence);
737 amdgpu_ring_patch_cond_exec(ring, patch);
739 /* the double SWITCH_BUFFER here *cannot* be skipped by COND_EXEC */
740 if (ring->funcs->emit_switch_buffer) {
741 amdgpu_ring_emit_switch_buffer(ring);
742 amdgpu_ring_emit_switch_buffer(ring);
744 amdgpu_ring_ib_end(ring);
749 * amdgpu_vm_bo_find - find the bo_va for a specific vm & bo
752 * @bo: requested buffer object
754 * Find @bo inside the requested vm.
755 * Search inside the @bos vm list for the requested vm
756 * Returns the found bo_va or NULL if none is found
758 * Object has to be reserved!
761 * Found bo_va or NULL.
763 struct amdgpu_bo_va *amdgpu_vm_bo_find(struct amdgpu_vm *vm,
764 struct amdgpu_bo *bo)
766 struct amdgpu_vm_bo_base *base;
768 for (base = bo->vm_bo; base; base = base->next) {
772 return container_of(base, struct amdgpu_bo_va, base);
778 * amdgpu_vm_map_gart - Resolve gart mapping of addr
780 * @pages_addr: optional DMA address to use for lookup
781 * @addr: the unmapped addr
783 * Look up the physical address of the page that the pte resolves
787 * The pointer for the page table entry.
789 uint64_t amdgpu_vm_map_gart(const dma_addr_t *pages_addr, uint64_t addr)
793 /* page table offset */
794 result = pages_addr[addr >> PAGE_SHIFT];
796 /* in case cpu page size != gpu page size*/
797 result |= addr & (~PAGE_MASK);
799 result &= 0xFFFFFFFFFFFFF000ULL;
805 * amdgpu_vm_update_pdes - make sure that all directories are valid
807 * @adev: amdgpu_device pointer
809 * @immediate: submit immediately to the paging queue
811 * Makes sure all directories are up to date.
814 * 0 for success, error for failure.
816 int amdgpu_vm_update_pdes(struct amdgpu_device *adev,
817 struct amdgpu_vm *vm, bool immediate)
819 struct amdgpu_vm_update_params params;
820 struct amdgpu_vm_bo_base *entry;
821 bool flush_tlb_needed = false;
822 LIST_HEAD(relocated);
825 spin_lock(&vm->status_lock);
826 list_splice_init(&vm->relocated, &relocated);
827 spin_unlock(&vm->status_lock);
829 if (list_empty(&relocated))
832 if (!drm_dev_enter(adev_to_drm(adev), &idx))
835 memset(¶ms, 0, sizeof(params));
838 params.immediate = immediate;
840 r = vm->update_funcs->prepare(¶ms, NULL, AMDGPU_SYNC_EXPLICIT);
844 list_for_each_entry(entry, &relocated, vm_status) {
845 /* vm_flush_needed after updating moved PDEs */
846 flush_tlb_needed |= entry->moved;
848 r = amdgpu_vm_pde_update(¶ms, entry);
853 r = vm->update_funcs->commit(¶ms, &vm->last_update);
857 if (flush_tlb_needed)
858 atomic64_inc(&vm->tlb_seq);
860 while (!list_empty(&relocated)) {
861 entry = list_first_entry(&relocated, struct amdgpu_vm_bo_base,
863 amdgpu_vm_bo_idle(entry);
872 * amdgpu_vm_tlb_seq_cb - make sure to increment tlb sequence
874 * @cb: the callback structure
876 * Increments the tlb sequence to make sure that future CS execute a VM flush.
878 static void amdgpu_vm_tlb_seq_cb(struct dma_fence *fence,
879 struct dma_fence_cb *cb)
881 struct amdgpu_vm_tlb_seq_struct *tlb_cb;
883 tlb_cb = container_of(cb, typeof(*tlb_cb), cb);
884 atomic64_inc(&tlb_cb->vm->tlb_seq);
889 * amdgpu_vm_update_range - update a range in the vm page table
891 * @adev: amdgpu_device pointer to use for commands
892 * @vm: the VM to update the range
893 * @immediate: immediate submission in a page fault
894 * @unlocked: unlocked invalidation during MM callback
895 * @flush_tlb: trigger tlb invalidation after update completed
896 * @allow_override: change MTYPE for local NUMA nodes
897 * @resv: fences we need to sync to
898 * @start: start of mapped range
899 * @last: last mapped entry
900 * @flags: flags for the entries
901 * @offset: offset into nodes and pages_addr
902 * @vram_base: base for vram mappings
903 * @res: ttm_resource to map
904 * @pages_addr: DMA addresses to use for mapping
905 * @fence: optional resulting fence
907 * Fill in the page table entries between @start and @last.
910 * 0 for success, negative erro code for failure.
912 int amdgpu_vm_update_range(struct amdgpu_device *adev, struct amdgpu_vm *vm,
913 bool immediate, bool unlocked, bool flush_tlb, bool allow_override,
914 struct dma_resv *resv, uint64_t start, uint64_t last,
915 uint64_t flags, uint64_t offset, uint64_t vram_base,
916 struct ttm_resource *res, dma_addr_t *pages_addr,
917 struct dma_fence **fence)
919 struct amdgpu_vm_update_params params;
920 struct amdgpu_vm_tlb_seq_struct *tlb_cb;
921 struct amdgpu_res_cursor cursor;
922 enum amdgpu_sync_mode sync_mode;
925 if (!drm_dev_enter(adev_to_drm(adev), &idx))
928 tlb_cb = kmalloc(sizeof(*tlb_cb), GFP_KERNEL);
934 /* Vega20+XGMI where PTEs get inadvertently cached in L2 texture cache,
935 * heavy-weight flush TLB unconditionally.
937 flush_tlb |= adev->gmc.xgmi.num_physical_nodes &&
938 amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 0);
941 * On GFX8 and older any 8 PTE block with a valid bit set enters the TLB
943 flush_tlb |= amdgpu_ip_version(adev, GC_HWIP, 0) < IP_VERSION(9, 0, 0);
945 memset(¶ms, 0, sizeof(params));
948 params.immediate = immediate;
949 params.pages_addr = pages_addr;
950 params.unlocked = unlocked;
951 params.allow_override = allow_override;
953 /* Implicitly sync to command submissions in the same VM before
954 * unmapping. Sync to moving fences before mapping.
956 if (!(flags & AMDGPU_PTE_VALID))
957 sync_mode = AMDGPU_SYNC_EQ_OWNER;
959 sync_mode = AMDGPU_SYNC_EXPLICIT;
961 amdgpu_vm_eviction_lock(vm);
967 if (!unlocked && !dma_fence_is_signaled(vm->last_unlocked)) {
968 struct dma_fence *tmp = dma_fence_get_stub();
970 amdgpu_bo_fence(vm->root.bo, vm->last_unlocked, true);
971 swap(vm->last_unlocked, tmp);
975 r = vm->update_funcs->prepare(¶ms, resv, sync_mode);
979 amdgpu_res_first(pages_addr ? NULL : res, offset,
980 (last - start + 1) * AMDGPU_GPU_PAGE_SIZE, &cursor);
981 while (cursor.remaining) {
982 uint64_t tmp, num_entries, addr;
984 num_entries = cursor.size >> AMDGPU_GPU_PAGE_SHIFT;
986 bool contiguous = true;
988 if (num_entries > AMDGPU_GPU_PAGES_IN_CPU_PAGE) {
989 uint64_t pfn = cursor.start >> PAGE_SHIFT;
992 contiguous = pages_addr[pfn + 1] ==
993 pages_addr[pfn] + PAGE_SIZE;
996 AMDGPU_GPU_PAGES_IN_CPU_PAGE;
997 for (count = 2; count < tmp; ++count) {
998 uint64_t idx = pfn + count;
1000 if (contiguous != (pages_addr[idx] ==
1001 pages_addr[idx - 1] + PAGE_SIZE))
1006 num_entries = count *
1007 AMDGPU_GPU_PAGES_IN_CPU_PAGE;
1011 addr = cursor.start;
1012 params.pages_addr = pages_addr;
1014 addr = pages_addr[cursor.start >> PAGE_SHIFT];
1015 params.pages_addr = NULL;
1018 } else if (flags & (AMDGPU_PTE_VALID | AMDGPU_PTE_PRT)) {
1019 addr = vram_base + cursor.start;
1024 tmp = start + num_entries;
1025 r = amdgpu_vm_ptes_update(¶ms, start, tmp, addr, flags);
1029 amdgpu_res_next(&cursor, num_entries * AMDGPU_GPU_PAGE_SIZE);
1033 r = vm->update_funcs->commit(¶ms, fence);
1035 if (flush_tlb || params.table_freed) {
1037 if (fence && *fence &&
1038 !dma_fence_add_callback(*fence, &tlb_cb->cb,
1039 amdgpu_vm_tlb_seq_cb)) {
1040 dma_fence_put(vm->last_tlb_flush);
1041 vm->last_tlb_flush = dma_fence_get(*fence);
1043 amdgpu_vm_tlb_seq_cb(NULL, &tlb_cb->cb);
1052 amdgpu_vm_eviction_unlock(vm);
1057 static void amdgpu_vm_bo_get_memory(struct amdgpu_bo_va *bo_va,
1058 struct amdgpu_mem_stats *stats)
1060 struct amdgpu_vm *vm = bo_va->base.vm;
1061 struct amdgpu_bo *bo = bo_va->base.bo;
1067 * For now ignore BOs which are currently locked and potentially
1068 * changing their location.
1070 if (bo->tbo.base.resv != vm->root.bo->tbo.base.resv &&
1071 !dma_resv_trylock(bo->tbo.base.resv))
1074 amdgpu_bo_get_memory(bo, stats);
1075 if (bo->tbo.base.resv != vm->root.bo->tbo.base.resv)
1076 dma_resv_unlock(bo->tbo.base.resv);
1079 void amdgpu_vm_get_memory(struct amdgpu_vm *vm,
1080 struct amdgpu_mem_stats *stats)
1082 struct amdgpu_bo_va *bo_va, *tmp;
1084 spin_lock(&vm->status_lock);
1085 list_for_each_entry_safe(bo_va, tmp, &vm->idle, base.vm_status)
1086 amdgpu_vm_bo_get_memory(bo_va, stats);
1088 list_for_each_entry_safe(bo_va, tmp, &vm->evicted, base.vm_status)
1089 amdgpu_vm_bo_get_memory(bo_va, stats);
1091 list_for_each_entry_safe(bo_va, tmp, &vm->relocated, base.vm_status)
1092 amdgpu_vm_bo_get_memory(bo_va, stats);
1094 list_for_each_entry_safe(bo_va, tmp, &vm->moved, base.vm_status)
1095 amdgpu_vm_bo_get_memory(bo_va, stats);
1097 list_for_each_entry_safe(bo_va, tmp, &vm->invalidated, base.vm_status)
1098 amdgpu_vm_bo_get_memory(bo_va, stats);
1100 list_for_each_entry_safe(bo_va, tmp, &vm->done, base.vm_status)
1101 amdgpu_vm_bo_get_memory(bo_va, stats);
1102 spin_unlock(&vm->status_lock);
1106 * amdgpu_vm_bo_update - update all BO mappings in the vm page table
1108 * @adev: amdgpu_device pointer
1109 * @bo_va: requested BO and VM object
1110 * @clear: if true clear the entries
1112 * Fill in the page table entries for @bo_va.
1115 * 0 for success, -EINVAL for failure.
1117 int amdgpu_vm_bo_update(struct amdgpu_device *adev, struct amdgpu_bo_va *bo_va,
1120 struct amdgpu_bo *bo = bo_va->base.bo;
1121 struct amdgpu_vm *vm = bo_va->base.vm;
1122 struct amdgpu_bo_va_mapping *mapping;
1123 dma_addr_t *pages_addr = NULL;
1124 struct ttm_resource *mem;
1125 struct dma_fence **last_update;
1126 bool flush_tlb = clear;
1128 struct dma_resv *resv;
1135 resv = vm->root.bo->tbo.base.resv;
1137 struct drm_gem_object *obj = &bo->tbo.base;
1139 resv = bo->tbo.base.resv;
1140 if (obj->import_attach && bo_va->is_xgmi) {
1141 struct dma_buf *dma_buf = obj->import_attach->dmabuf;
1142 struct drm_gem_object *gobj = dma_buf->priv;
1143 struct amdgpu_bo *abo = gem_to_amdgpu_bo(gobj);
1145 if (abo->tbo.resource &&
1146 abo->tbo.resource->mem_type == TTM_PL_VRAM)
1147 bo = gem_to_amdgpu_bo(gobj);
1149 mem = bo->tbo.resource;
1150 if (mem && (mem->mem_type == TTM_PL_TT ||
1151 mem->mem_type == AMDGPU_PL_PREEMPT))
1152 pages_addr = bo->tbo.ttm->dma_address;
1156 struct amdgpu_device *bo_adev;
1158 flags = amdgpu_ttm_tt_pte_flags(adev, bo->tbo.ttm, mem);
1160 if (amdgpu_bo_encrypted(bo))
1161 flags |= AMDGPU_PTE_TMZ;
1163 bo_adev = amdgpu_ttm_adev(bo->tbo.bdev);
1164 vram_base = bo_adev->vm_manager.vram_base_offset;
1165 uncached = (bo->flags & AMDGPU_GEM_CREATE_UNCACHED) != 0;
1172 if (clear || (bo && bo->tbo.base.resv ==
1173 vm->root.bo->tbo.base.resv))
1174 last_update = &vm->last_update;
1176 last_update = &bo_va->last_pt_update;
1178 if (!clear && bo_va->base.moved) {
1180 list_splice_init(&bo_va->valids, &bo_va->invalids);
1182 } else if (bo_va->cleared != clear) {
1183 list_splice_init(&bo_va->valids, &bo_va->invalids);
1186 list_for_each_entry(mapping, &bo_va->invalids, list) {
1187 uint64_t update_flags = flags;
1189 /* normally,bo_va->flags only contians READABLE and WIRTEABLE bit go here
1190 * but in case of something, we filter the flags in first place
1192 if (!(mapping->flags & AMDGPU_PTE_READABLE))
1193 update_flags &= ~AMDGPU_PTE_READABLE;
1194 if (!(mapping->flags & AMDGPU_PTE_WRITEABLE))
1195 update_flags &= ~AMDGPU_PTE_WRITEABLE;
1197 /* Apply ASIC specific mapping flags */
1198 amdgpu_gmc_get_vm_pte(adev, mapping, &update_flags);
1200 trace_amdgpu_vm_bo_update(mapping);
1202 r = amdgpu_vm_update_range(adev, vm, false, false, flush_tlb,
1203 !uncached, resv, mapping->start, mapping->last,
1204 update_flags, mapping->offset,
1205 vram_base, mem, pages_addr,
1211 /* If the BO is not in its preferred location add it back to
1212 * the evicted list so that it gets validated again on the
1213 * next command submission.
1215 if (bo && bo->tbo.base.resv == vm->root.bo->tbo.base.resv) {
1216 uint32_t mem_type = bo->tbo.resource->mem_type;
1218 if (!(bo->preferred_domains &
1219 amdgpu_mem_type_to_domain(mem_type)))
1220 amdgpu_vm_bo_evicted(&bo_va->base);
1222 amdgpu_vm_bo_idle(&bo_va->base);
1224 amdgpu_vm_bo_done(&bo_va->base);
1227 list_splice_init(&bo_va->invalids, &bo_va->valids);
1228 bo_va->cleared = clear;
1229 bo_va->base.moved = false;
1231 if (trace_amdgpu_vm_bo_mapping_enabled()) {
1232 list_for_each_entry(mapping, &bo_va->valids, list)
1233 trace_amdgpu_vm_bo_mapping(mapping);
1240 * amdgpu_vm_update_prt_state - update the global PRT state
1242 * @adev: amdgpu_device pointer
1244 static void amdgpu_vm_update_prt_state(struct amdgpu_device *adev)
1246 unsigned long flags;
1249 spin_lock_irqsave(&adev->vm_manager.prt_lock, flags);
1250 enable = !!atomic_read(&adev->vm_manager.num_prt_users);
1251 adev->gmc.gmc_funcs->set_prt(adev, enable);
1252 spin_unlock_irqrestore(&adev->vm_manager.prt_lock, flags);
1256 * amdgpu_vm_prt_get - add a PRT user
1258 * @adev: amdgpu_device pointer
1260 static void amdgpu_vm_prt_get(struct amdgpu_device *adev)
1262 if (!adev->gmc.gmc_funcs->set_prt)
1265 if (atomic_inc_return(&adev->vm_manager.num_prt_users) == 1)
1266 amdgpu_vm_update_prt_state(adev);
1270 * amdgpu_vm_prt_put - drop a PRT user
1272 * @adev: amdgpu_device pointer
1274 static void amdgpu_vm_prt_put(struct amdgpu_device *adev)
1276 if (atomic_dec_return(&adev->vm_manager.num_prt_users) == 0)
1277 amdgpu_vm_update_prt_state(adev);
1281 * amdgpu_vm_prt_cb - callback for updating the PRT status
1283 * @fence: fence for the callback
1284 * @_cb: the callback function
1286 static void amdgpu_vm_prt_cb(struct dma_fence *fence, struct dma_fence_cb *_cb)
1288 struct amdgpu_prt_cb *cb = container_of(_cb, struct amdgpu_prt_cb, cb);
1290 amdgpu_vm_prt_put(cb->adev);
1295 * amdgpu_vm_add_prt_cb - add callback for updating the PRT status
1297 * @adev: amdgpu_device pointer
1298 * @fence: fence for the callback
1300 static void amdgpu_vm_add_prt_cb(struct amdgpu_device *adev,
1301 struct dma_fence *fence)
1303 struct amdgpu_prt_cb *cb;
1305 if (!adev->gmc.gmc_funcs->set_prt)
1308 cb = kmalloc(sizeof(struct amdgpu_prt_cb), GFP_KERNEL);
1310 /* Last resort when we are OOM */
1312 dma_fence_wait(fence, false);
1314 amdgpu_vm_prt_put(adev);
1317 if (!fence || dma_fence_add_callback(fence, &cb->cb,
1319 amdgpu_vm_prt_cb(fence, &cb->cb);
1324 * amdgpu_vm_free_mapping - free a mapping
1326 * @adev: amdgpu_device pointer
1328 * @mapping: mapping to be freed
1329 * @fence: fence of the unmap operation
1331 * Free a mapping and make sure we decrease the PRT usage count if applicable.
1333 static void amdgpu_vm_free_mapping(struct amdgpu_device *adev,
1334 struct amdgpu_vm *vm,
1335 struct amdgpu_bo_va_mapping *mapping,
1336 struct dma_fence *fence)
1338 if (mapping->flags & AMDGPU_PTE_PRT)
1339 amdgpu_vm_add_prt_cb(adev, fence);
1344 * amdgpu_vm_prt_fini - finish all prt mappings
1346 * @adev: amdgpu_device pointer
1349 * Register a cleanup callback to disable PRT support after VM dies.
1351 static void amdgpu_vm_prt_fini(struct amdgpu_device *adev, struct amdgpu_vm *vm)
1353 struct dma_resv *resv = vm->root.bo->tbo.base.resv;
1354 struct dma_resv_iter cursor;
1355 struct dma_fence *fence;
1357 dma_resv_for_each_fence(&cursor, resv, DMA_RESV_USAGE_BOOKKEEP, fence) {
1358 /* Add a callback for each fence in the reservation object */
1359 amdgpu_vm_prt_get(adev);
1360 amdgpu_vm_add_prt_cb(adev, fence);
1365 * amdgpu_vm_clear_freed - clear freed BOs in the PT
1367 * @adev: amdgpu_device pointer
1369 * @fence: optional resulting fence (unchanged if no work needed to be done
1370 * or if an error occurred)
1372 * Make sure all freed BOs are cleared in the PT.
1373 * PTs have to be reserved and mutex must be locked!
1379 int amdgpu_vm_clear_freed(struct amdgpu_device *adev,
1380 struct amdgpu_vm *vm,
1381 struct dma_fence **fence)
1383 struct dma_resv *resv = vm->root.bo->tbo.base.resv;
1384 struct amdgpu_bo_va_mapping *mapping;
1385 uint64_t init_pte_value = 0;
1386 struct dma_fence *f = NULL;
1389 while (!list_empty(&vm->freed)) {
1390 mapping = list_first_entry(&vm->freed,
1391 struct amdgpu_bo_va_mapping, list);
1392 list_del(&mapping->list);
1394 r = amdgpu_vm_update_range(adev, vm, false, false, true, false,
1395 resv, mapping->start, mapping->last,
1396 init_pte_value, 0, 0, NULL, NULL,
1398 amdgpu_vm_free_mapping(adev, vm, mapping, f);
1406 dma_fence_put(*fence);
1417 * amdgpu_vm_handle_moved - handle moved BOs in the PT
1419 * @adev: amdgpu_device pointer
1421 * @ticket: optional reservation ticket used to reserve the VM
1423 * Make sure all BOs which are moved are updated in the PTs.
1428 * PTs have to be reserved!
1430 int amdgpu_vm_handle_moved(struct amdgpu_device *adev,
1431 struct amdgpu_vm *vm,
1432 struct ww_acquire_ctx *ticket)
1434 struct amdgpu_bo_va *bo_va;
1435 struct dma_resv *resv;
1439 spin_lock(&vm->status_lock);
1440 while (!list_empty(&vm->moved)) {
1441 bo_va = list_first_entry(&vm->moved, struct amdgpu_bo_va,
1443 spin_unlock(&vm->status_lock);
1445 /* Per VM BOs never need to bo cleared in the page tables */
1446 r = amdgpu_vm_bo_update(adev, bo_va, false);
1449 spin_lock(&vm->status_lock);
1452 while (!list_empty(&vm->invalidated)) {
1453 bo_va = list_first_entry(&vm->invalidated, struct amdgpu_bo_va,
1455 resv = bo_va->base.bo->tbo.base.resv;
1456 spin_unlock(&vm->status_lock);
1458 /* Try to reserve the BO to avoid clearing its ptes */
1459 if (!adev->debug_vm && dma_resv_trylock(resv)) {
1462 /* The caller is already holding the reservation lock */
1463 } else if (ticket && dma_resv_locking_ctx(resv) == ticket) {
1466 /* Somebody else is using the BO right now */
1472 r = amdgpu_vm_bo_update(adev, bo_va, clear);
1475 dma_resv_unlock(resv);
1479 /* Remember evicted DMABuf imports in compute VMs for later
1482 if (vm->is_compute_context &&
1483 bo_va->base.bo->tbo.base.import_attach &&
1484 (!bo_va->base.bo->tbo.resource ||
1485 bo_va->base.bo->tbo.resource->mem_type == TTM_PL_SYSTEM))
1486 amdgpu_vm_bo_evicted_user(&bo_va->base);
1488 spin_lock(&vm->status_lock);
1490 spin_unlock(&vm->status_lock);
1496 * amdgpu_vm_flush_compute_tlb - Flush TLB on compute VM
1498 * @adev: amdgpu_device pointer
1500 * @flush_type: flush type
1501 * @xcc_mask: mask of XCCs that belong to the compute partition in need of a TLB flush.
1503 * Flush TLB if needed for a compute VM.
1508 int amdgpu_vm_flush_compute_tlb(struct amdgpu_device *adev,
1509 struct amdgpu_vm *vm,
1510 uint32_t flush_type,
1513 uint64_t tlb_seq = amdgpu_vm_tlb_seq(vm);
1514 bool all_hub = false;
1517 WARN_ON_ONCE(!vm->is_compute_context);
1520 * It can be that we race and lose here, but that is extremely unlikely
1521 * and the worst thing which could happen is that we flush the changes
1522 * into the TLB once more which is harmless.
1524 if (atomic64_xchg(&vm->kfd_last_flushed_seq, tlb_seq) == tlb_seq)
1527 if (adev->family == AMDGPU_FAMILY_AI ||
1528 adev->family == AMDGPU_FAMILY_RV)
1531 for_each_inst(xcc, xcc_mask) {
1532 r = amdgpu_gmc_flush_gpu_tlb_pasid(adev, vm->pasid, flush_type,
1541 * amdgpu_vm_bo_add - add a bo to a specific vm
1543 * @adev: amdgpu_device pointer
1545 * @bo: amdgpu buffer object
1547 * Add @bo into the requested vm.
1548 * Add @bo to the list of bos associated with the vm
1551 * Newly added bo_va or NULL for failure
1553 * Object has to be reserved!
1555 struct amdgpu_bo_va *amdgpu_vm_bo_add(struct amdgpu_device *adev,
1556 struct amdgpu_vm *vm,
1557 struct amdgpu_bo *bo)
1559 struct amdgpu_bo_va *bo_va;
1561 bo_va = kzalloc(sizeof(struct amdgpu_bo_va), GFP_KERNEL);
1562 if (bo_va == NULL) {
1565 amdgpu_vm_bo_base_init(&bo_va->base, vm, bo);
1567 bo_va->ref_count = 1;
1568 bo_va->last_pt_update = dma_fence_get_stub();
1569 INIT_LIST_HEAD(&bo_va->valids);
1570 INIT_LIST_HEAD(&bo_va->invalids);
1575 dma_resv_assert_held(bo->tbo.base.resv);
1576 if (amdgpu_dmabuf_is_xgmi_accessible(adev, bo)) {
1577 bo_va->is_xgmi = true;
1578 /* Power up XGMI if it can be potentially used */
1579 amdgpu_xgmi_set_pstate(adev, AMDGPU_XGMI_PSTATE_MAX_VEGA20);
1587 * amdgpu_vm_bo_insert_map - insert a new mapping
1589 * @adev: amdgpu_device pointer
1590 * @bo_va: bo_va to store the address
1591 * @mapping: the mapping to insert
1593 * Insert a new mapping into all structures.
1595 static void amdgpu_vm_bo_insert_map(struct amdgpu_device *adev,
1596 struct amdgpu_bo_va *bo_va,
1597 struct amdgpu_bo_va_mapping *mapping)
1599 struct amdgpu_vm *vm = bo_va->base.vm;
1600 struct amdgpu_bo *bo = bo_va->base.bo;
1602 mapping->bo_va = bo_va;
1603 list_add(&mapping->list, &bo_va->invalids);
1604 amdgpu_vm_it_insert(mapping, &vm->va);
1606 if (mapping->flags & AMDGPU_PTE_PRT)
1607 amdgpu_vm_prt_get(adev);
1609 if (bo && bo->tbo.base.resv == vm->root.bo->tbo.base.resv &&
1610 !bo_va->base.moved) {
1611 amdgpu_vm_bo_moved(&bo_va->base);
1613 trace_amdgpu_vm_bo_map(bo_va, mapping);
1617 * amdgpu_vm_bo_map - map bo inside a vm
1619 * @adev: amdgpu_device pointer
1620 * @bo_va: bo_va to store the address
1621 * @saddr: where to map the BO
1622 * @offset: requested offset in the BO
1623 * @size: BO size in bytes
1624 * @flags: attributes of pages (read/write/valid/etc.)
1626 * Add a mapping of the BO at the specefied addr into the VM.
1629 * 0 for success, error for failure.
1631 * Object has to be reserved and unreserved outside!
1633 int amdgpu_vm_bo_map(struct amdgpu_device *adev,
1634 struct amdgpu_bo_va *bo_va,
1635 uint64_t saddr, uint64_t offset,
1636 uint64_t size, uint64_t flags)
1638 struct amdgpu_bo_va_mapping *mapping, *tmp;
1639 struct amdgpu_bo *bo = bo_va->base.bo;
1640 struct amdgpu_vm *vm = bo_va->base.vm;
1643 /* validate the parameters */
1644 if (saddr & ~PAGE_MASK || offset & ~PAGE_MASK || size & ~PAGE_MASK)
1646 if (saddr + size <= saddr || offset + size <= offset)
1649 /* make sure object fit at this offset */
1650 eaddr = saddr + size - 1;
1651 if ((bo && offset + size > amdgpu_bo_size(bo)) ||
1652 (eaddr >= adev->vm_manager.max_pfn << AMDGPU_GPU_PAGE_SHIFT))
1655 saddr /= AMDGPU_GPU_PAGE_SIZE;
1656 eaddr /= AMDGPU_GPU_PAGE_SIZE;
1658 tmp = amdgpu_vm_it_iter_first(&vm->va, saddr, eaddr);
1660 /* bo and tmp overlap, invalid addr */
1661 dev_err(adev->dev, "bo %p va 0x%010Lx-0x%010Lx conflict with "
1662 "0x%010Lx-0x%010Lx\n", bo, saddr, eaddr,
1663 tmp->start, tmp->last + 1);
1667 mapping = kmalloc(sizeof(*mapping), GFP_KERNEL);
1671 mapping->start = saddr;
1672 mapping->last = eaddr;
1673 mapping->offset = offset;
1674 mapping->flags = flags;
1676 amdgpu_vm_bo_insert_map(adev, bo_va, mapping);
1682 * amdgpu_vm_bo_replace_map - map bo inside a vm, replacing existing mappings
1684 * @adev: amdgpu_device pointer
1685 * @bo_va: bo_va to store the address
1686 * @saddr: where to map the BO
1687 * @offset: requested offset in the BO
1688 * @size: BO size in bytes
1689 * @flags: attributes of pages (read/write/valid/etc.)
1691 * Add a mapping of the BO at the specefied addr into the VM. Replace existing
1692 * mappings as we do so.
1695 * 0 for success, error for failure.
1697 * Object has to be reserved and unreserved outside!
1699 int amdgpu_vm_bo_replace_map(struct amdgpu_device *adev,
1700 struct amdgpu_bo_va *bo_va,
1701 uint64_t saddr, uint64_t offset,
1702 uint64_t size, uint64_t flags)
1704 struct amdgpu_bo_va_mapping *mapping;
1705 struct amdgpu_bo *bo = bo_va->base.bo;
1709 /* validate the parameters */
1710 if (saddr & ~PAGE_MASK || offset & ~PAGE_MASK || size & ~PAGE_MASK)
1712 if (saddr + size <= saddr || offset + size <= offset)
1715 /* make sure object fit at this offset */
1716 eaddr = saddr + size - 1;
1717 if ((bo && offset + size > amdgpu_bo_size(bo)) ||
1718 (eaddr >= adev->vm_manager.max_pfn << AMDGPU_GPU_PAGE_SHIFT))
1721 /* Allocate all the needed memory */
1722 mapping = kmalloc(sizeof(*mapping), GFP_KERNEL);
1726 r = amdgpu_vm_bo_clear_mappings(adev, bo_va->base.vm, saddr, size);
1732 saddr /= AMDGPU_GPU_PAGE_SIZE;
1733 eaddr /= AMDGPU_GPU_PAGE_SIZE;
1735 mapping->start = saddr;
1736 mapping->last = eaddr;
1737 mapping->offset = offset;
1738 mapping->flags = flags;
1740 amdgpu_vm_bo_insert_map(adev, bo_va, mapping);
1746 * amdgpu_vm_bo_unmap - remove bo mapping from vm
1748 * @adev: amdgpu_device pointer
1749 * @bo_va: bo_va to remove the address from
1750 * @saddr: where to the BO is mapped
1752 * Remove a mapping of the BO at the specefied addr from the VM.
1755 * 0 for success, error for failure.
1757 * Object has to be reserved and unreserved outside!
1759 int amdgpu_vm_bo_unmap(struct amdgpu_device *adev,
1760 struct amdgpu_bo_va *bo_va,
1763 struct amdgpu_bo_va_mapping *mapping;
1764 struct amdgpu_vm *vm = bo_va->base.vm;
1767 saddr /= AMDGPU_GPU_PAGE_SIZE;
1769 list_for_each_entry(mapping, &bo_va->valids, list) {
1770 if (mapping->start == saddr)
1774 if (&mapping->list == &bo_va->valids) {
1777 list_for_each_entry(mapping, &bo_va->invalids, list) {
1778 if (mapping->start == saddr)
1782 if (&mapping->list == &bo_va->invalids)
1786 list_del(&mapping->list);
1787 amdgpu_vm_it_remove(mapping, &vm->va);
1788 mapping->bo_va = NULL;
1789 trace_amdgpu_vm_bo_unmap(bo_va, mapping);
1792 list_add(&mapping->list, &vm->freed);
1794 amdgpu_vm_free_mapping(adev, vm, mapping,
1795 bo_va->last_pt_update);
1801 * amdgpu_vm_bo_clear_mappings - remove all mappings in a specific range
1803 * @adev: amdgpu_device pointer
1804 * @vm: VM structure to use
1805 * @saddr: start of the range
1806 * @size: size of the range
1808 * Remove all mappings in a range, split them as appropriate.
1811 * 0 for success, error for failure.
1813 int amdgpu_vm_bo_clear_mappings(struct amdgpu_device *adev,
1814 struct amdgpu_vm *vm,
1815 uint64_t saddr, uint64_t size)
1817 struct amdgpu_bo_va_mapping *before, *after, *tmp, *next;
1821 eaddr = saddr + size - 1;
1822 saddr /= AMDGPU_GPU_PAGE_SIZE;
1823 eaddr /= AMDGPU_GPU_PAGE_SIZE;
1825 /* Allocate all the needed memory */
1826 before = kzalloc(sizeof(*before), GFP_KERNEL);
1829 INIT_LIST_HEAD(&before->list);
1831 after = kzalloc(sizeof(*after), GFP_KERNEL);
1836 INIT_LIST_HEAD(&after->list);
1838 /* Now gather all removed mappings */
1839 tmp = amdgpu_vm_it_iter_first(&vm->va, saddr, eaddr);
1841 /* Remember mapping split at the start */
1842 if (tmp->start < saddr) {
1843 before->start = tmp->start;
1844 before->last = saddr - 1;
1845 before->offset = tmp->offset;
1846 before->flags = tmp->flags;
1847 before->bo_va = tmp->bo_va;
1848 list_add(&before->list, &tmp->bo_va->invalids);
1851 /* Remember mapping split at the end */
1852 if (tmp->last > eaddr) {
1853 after->start = eaddr + 1;
1854 after->last = tmp->last;
1855 after->offset = tmp->offset;
1856 after->offset += (after->start - tmp->start) << PAGE_SHIFT;
1857 after->flags = tmp->flags;
1858 after->bo_va = tmp->bo_va;
1859 list_add(&after->list, &tmp->bo_va->invalids);
1862 list_del(&tmp->list);
1863 list_add(&tmp->list, &removed);
1865 tmp = amdgpu_vm_it_iter_next(tmp, saddr, eaddr);
1868 /* And free them up */
1869 list_for_each_entry_safe(tmp, next, &removed, list) {
1870 amdgpu_vm_it_remove(tmp, &vm->va);
1871 list_del(&tmp->list);
1873 if (tmp->start < saddr)
1875 if (tmp->last > eaddr)
1879 list_add(&tmp->list, &vm->freed);
1880 trace_amdgpu_vm_bo_unmap(NULL, tmp);
1883 /* Insert partial mapping before the range */
1884 if (!list_empty(&before->list)) {
1885 struct amdgpu_bo *bo = before->bo_va->base.bo;
1887 amdgpu_vm_it_insert(before, &vm->va);
1888 if (before->flags & AMDGPU_PTE_PRT)
1889 amdgpu_vm_prt_get(adev);
1891 if (bo && bo->tbo.base.resv == vm->root.bo->tbo.base.resv &&
1892 !before->bo_va->base.moved)
1893 amdgpu_vm_bo_moved(&before->bo_va->base);
1898 /* Insert partial mapping after the range */
1899 if (!list_empty(&after->list)) {
1900 struct amdgpu_bo *bo = after->bo_va->base.bo;
1902 amdgpu_vm_it_insert(after, &vm->va);
1903 if (after->flags & AMDGPU_PTE_PRT)
1904 amdgpu_vm_prt_get(adev);
1906 if (bo && bo->tbo.base.resv == vm->root.bo->tbo.base.resv &&
1907 !after->bo_va->base.moved)
1908 amdgpu_vm_bo_moved(&after->bo_va->base);
1917 * amdgpu_vm_bo_lookup_mapping - find mapping by address
1919 * @vm: the requested VM
1920 * @addr: the address
1922 * Find a mapping by it's address.
1925 * The amdgpu_bo_va_mapping matching for addr or NULL
1928 struct amdgpu_bo_va_mapping *amdgpu_vm_bo_lookup_mapping(struct amdgpu_vm *vm,
1931 return amdgpu_vm_it_iter_first(&vm->va, addr, addr);
1935 * amdgpu_vm_bo_trace_cs - trace all reserved mappings
1937 * @vm: the requested vm
1938 * @ticket: CS ticket
1940 * Trace all mappings of BOs reserved during a command submission.
1942 void amdgpu_vm_bo_trace_cs(struct amdgpu_vm *vm, struct ww_acquire_ctx *ticket)
1944 struct amdgpu_bo_va_mapping *mapping;
1946 if (!trace_amdgpu_vm_bo_cs_enabled())
1949 for (mapping = amdgpu_vm_it_iter_first(&vm->va, 0, U64_MAX); mapping;
1950 mapping = amdgpu_vm_it_iter_next(mapping, 0, U64_MAX)) {
1951 if (mapping->bo_va && mapping->bo_va->base.bo) {
1952 struct amdgpu_bo *bo;
1954 bo = mapping->bo_va->base.bo;
1955 if (dma_resv_locking_ctx(bo->tbo.base.resv) !=
1960 trace_amdgpu_vm_bo_cs(mapping);
1965 * amdgpu_vm_bo_del - remove a bo from a specific vm
1967 * @adev: amdgpu_device pointer
1968 * @bo_va: requested bo_va
1970 * Remove @bo_va->bo from the requested vm.
1972 * Object have to be reserved!
1974 void amdgpu_vm_bo_del(struct amdgpu_device *adev,
1975 struct amdgpu_bo_va *bo_va)
1977 struct amdgpu_bo_va_mapping *mapping, *next;
1978 struct amdgpu_bo *bo = bo_va->base.bo;
1979 struct amdgpu_vm *vm = bo_va->base.vm;
1980 struct amdgpu_vm_bo_base **base;
1982 dma_resv_assert_held(vm->root.bo->tbo.base.resv);
1985 dma_resv_assert_held(bo->tbo.base.resv);
1986 if (bo->tbo.base.resv == vm->root.bo->tbo.base.resv)
1987 ttm_bo_set_bulk_move(&bo->tbo, NULL);
1989 for (base = &bo_va->base.bo->vm_bo; *base;
1990 base = &(*base)->next) {
1991 if (*base != &bo_va->base)
1994 *base = bo_va->base.next;
1999 spin_lock(&vm->status_lock);
2000 list_del(&bo_va->base.vm_status);
2001 spin_unlock(&vm->status_lock);
2003 list_for_each_entry_safe(mapping, next, &bo_va->valids, list) {
2004 list_del(&mapping->list);
2005 amdgpu_vm_it_remove(mapping, &vm->va);
2006 mapping->bo_va = NULL;
2007 trace_amdgpu_vm_bo_unmap(bo_va, mapping);
2008 list_add(&mapping->list, &vm->freed);
2010 list_for_each_entry_safe(mapping, next, &bo_va->invalids, list) {
2011 list_del(&mapping->list);
2012 amdgpu_vm_it_remove(mapping, &vm->va);
2013 amdgpu_vm_free_mapping(adev, vm, mapping,
2014 bo_va->last_pt_update);
2017 dma_fence_put(bo_va->last_pt_update);
2019 if (bo && bo_va->is_xgmi)
2020 amdgpu_xgmi_set_pstate(adev, AMDGPU_XGMI_PSTATE_MIN);
2026 * amdgpu_vm_evictable - check if we can evict a VM
2028 * @bo: A page table of the VM.
2030 * Check if it is possible to evict a VM.
2032 bool amdgpu_vm_evictable(struct amdgpu_bo *bo)
2034 struct amdgpu_vm_bo_base *bo_base = bo->vm_bo;
2036 /* Page tables of a destroyed VM can go away immediately */
2037 if (!bo_base || !bo_base->vm)
2040 /* Don't evict VM page tables while they are busy */
2041 if (!dma_resv_test_signaled(bo->tbo.base.resv, DMA_RESV_USAGE_BOOKKEEP))
2044 /* Try to block ongoing updates */
2045 if (!amdgpu_vm_eviction_trylock(bo_base->vm))
2048 /* Don't evict VM page tables while they are updated */
2049 if (!dma_fence_is_signaled(bo_base->vm->last_unlocked)) {
2050 amdgpu_vm_eviction_unlock(bo_base->vm);
2054 bo_base->vm->evicting = true;
2055 amdgpu_vm_eviction_unlock(bo_base->vm);
2060 * amdgpu_vm_bo_invalidate - mark the bo as invalid
2062 * @adev: amdgpu_device pointer
2063 * @bo: amdgpu buffer object
2064 * @evicted: is the BO evicted
2066 * Mark @bo as invalid.
2068 void amdgpu_vm_bo_invalidate(struct amdgpu_device *adev,
2069 struct amdgpu_bo *bo, bool evicted)
2071 struct amdgpu_vm_bo_base *bo_base;
2073 /* shadow bo doesn't have bo base, its validation needs its parent */
2074 if (bo->parent && (amdgpu_bo_shadowed(bo->parent) == bo))
2077 for (bo_base = bo->vm_bo; bo_base; bo_base = bo_base->next) {
2078 struct amdgpu_vm *vm = bo_base->vm;
2080 if (evicted && bo->tbo.base.resv == vm->root.bo->tbo.base.resv) {
2081 amdgpu_vm_bo_evicted(bo_base);
2087 bo_base->moved = true;
2089 if (bo->tbo.type == ttm_bo_type_kernel)
2090 amdgpu_vm_bo_relocated(bo_base);
2091 else if (bo->tbo.base.resv == vm->root.bo->tbo.base.resv)
2092 amdgpu_vm_bo_moved(bo_base);
2094 amdgpu_vm_bo_invalidated(bo_base);
2099 * amdgpu_vm_get_block_size - calculate VM page table size as power of two
2104 * VM page table as power of two
2106 static uint32_t amdgpu_vm_get_block_size(uint64_t vm_size)
2108 /* Total bits covered by PD + PTs */
2109 unsigned bits = ilog2(vm_size) + 18;
2111 /* Make sure the PD is 4K in size up to 8GB address space.
2112 Above that split equal between PD and PTs */
2116 return ((bits + 3) / 2);
2120 * amdgpu_vm_adjust_size - adjust vm size, block size and fragment size
2122 * @adev: amdgpu_device pointer
2123 * @min_vm_size: the minimum vm size in GB if it's set auto
2124 * @fragment_size_default: Default PTE fragment size
2125 * @max_level: max VMPT level
2126 * @max_bits: max address space size in bits
2129 void amdgpu_vm_adjust_size(struct amdgpu_device *adev, uint32_t min_vm_size,
2130 uint32_t fragment_size_default, unsigned max_level,
2133 unsigned int max_size = 1 << (max_bits - 30);
2134 unsigned int vm_size;
2137 /* adjust vm size first */
2138 if (amdgpu_vm_size != -1) {
2139 vm_size = amdgpu_vm_size;
2140 if (vm_size > max_size) {
2141 dev_warn(adev->dev, "VM size (%d) too large, max is %u GB\n",
2142 amdgpu_vm_size, max_size);
2147 unsigned int phys_ram_gb;
2149 /* Optimal VM size depends on the amount of physical
2150 * RAM available. Underlying requirements and
2153 * - Need to map system memory and VRAM from all GPUs
2154 * - VRAM from other GPUs not known here
2155 * - Assume VRAM <= system memory
2156 * - On GFX8 and older, VM space can be segmented for
2158 * - Need to allow room for fragmentation, guard pages etc.
2160 * This adds up to a rough guess of system memory x3.
2161 * Round up to power of two to maximize the available
2162 * VM size with the given page table size.
2165 phys_ram_gb = ((uint64_t)si.totalram * si.mem_unit +
2166 (1 << 30) - 1) >> 30;
2167 vm_size = roundup_pow_of_two(
2168 min(max(phys_ram_gb * 3, min_vm_size), max_size));
2171 adev->vm_manager.max_pfn = (uint64_t)vm_size << 18;
2173 tmp = roundup_pow_of_two(adev->vm_manager.max_pfn);
2174 if (amdgpu_vm_block_size != -1)
2175 tmp >>= amdgpu_vm_block_size - 9;
2176 tmp = DIV_ROUND_UP(fls64(tmp) - 1, 9) - 1;
2177 adev->vm_manager.num_level = min_t(unsigned int, max_level, tmp);
2178 switch (adev->vm_manager.num_level) {
2180 adev->vm_manager.root_level = AMDGPU_VM_PDB2;
2183 adev->vm_manager.root_level = AMDGPU_VM_PDB1;
2186 adev->vm_manager.root_level = AMDGPU_VM_PDB0;
2189 dev_err(adev->dev, "VMPT only supports 2~4+1 levels\n");
2191 /* block size depends on vm size and hw setup*/
2192 if (amdgpu_vm_block_size != -1)
2193 adev->vm_manager.block_size =
2194 min((unsigned)amdgpu_vm_block_size, max_bits
2195 - AMDGPU_GPU_PAGE_SHIFT
2196 - 9 * adev->vm_manager.num_level);
2197 else if (adev->vm_manager.num_level > 1)
2198 adev->vm_manager.block_size = 9;
2200 adev->vm_manager.block_size = amdgpu_vm_get_block_size(tmp);
2202 if (amdgpu_vm_fragment_size == -1)
2203 adev->vm_manager.fragment_size = fragment_size_default;
2205 adev->vm_manager.fragment_size = amdgpu_vm_fragment_size;
2207 DRM_INFO("vm size is %u GB, %u levels, block size is %u-bit, fragment size is %u-bit\n",
2208 vm_size, adev->vm_manager.num_level + 1,
2209 adev->vm_manager.block_size,
2210 adev->vm_manager.fragment_size);
2214 * amdgpu_vm_wait_idle - wait for the VM to become idle
2216 * @vm: VM object to wait for
2217 * @timeout: timeout to wait for VM to become idle
2219 long amdgpu_vm_wait_idle(struct amdgpu_vm *vm, long timeout)
2221 timeout = dma_resv_wait_timeout(vm->root.bo->tbo.base.resv,
2222 DMA_RESV_USAGE_BOOKKEEP,
2227 return dma_fence_wait_timeout(vm->last_unlocked, true, timeout);
2230 static void amdgpu_vm_destroy_task_info(struct kref *kref)
2232 struct amdgpu_task_info *ti = container_of(kref, struct amdgpu_task_info, refcount);
2237 static inline struct amdgpu_vm *
2238 amdgpu_vm_get_vm_from_pasid(struct amdgpu_device *adev, u32 pasid)
2240 struct amdgpu_vm *vm;
2241 unsigned long flags;
2243 xa_lock_irqsave(&adev->vm_manager.pasids, flags);
2244 vm = xa_load(&adev->vm_manager.pasids, pasid);
2245 xa_unlock_irqrestore(&adev->vm_manager.pasids, flags);
2251 * amdgpu_vm_put_task_info - reference down the vm task_info ptr
2253 * @task_info: task_info struct under discussion.
2255 * frees the vm task_info ptr at the last put
2257 void amdgpu_vm_put_task_info(struct amdgpu_task_info *task_info)
2259 kref_put(&task_info->refcount, amdgpu_vm_destroy_task_info);
2263 * amdgpu_vm_get_task_info_vm - Extracts task info for a vm.
2265 * @vm: VM to get info from
2267 * Returns the reference counted task_info structure, which must be
2268 * referenced down with amdgpu_vm_put_task_info.
2270 struct amdgpu_task_info *
2271 amdgpu_vm_get_task_info_vm(struct amdgpu_vm *vm)
2273 struct amdgpu_task_info *ti = NULL;
2277 kref_get(&vm->task_info->refcount);
2284 * amdgpu_vm_get_task_info_pasid - Extracts task info for a PASID.
2286 * @adev: drm device pointer
2287 * @pasid: PASID identifier for VM
2289 * Returns the reference counted task_info structure, which must be
2290 * referenced down with amdgpu_vm_put_task_info.
2292 struct amdgpu_task_info *
2293 amdgpu_vm_get_task_info_pasid(struct amdgpu_device *adev, u32 pasid)
2295 return amdgpu_vm_get_task_info_vm(
2296 amdgpu_vm_get_vm_from_pasid(adev, pasid));
2299 static int amdgpu_vm_create_task_info(struct amdgpu_vm *vm)
2301 vm->task_info = kzalloc(sizeof(struct amdgpu_task_info), GFP_KERNEL);
2305 kref_init(&vm->task_info->refcount);
2310 * amdgpu_vm_set_task_info - Sets VMs task info.
2312 * @vm: vm for which to set the info
2314 void amdgpu_vm_set_task_info(struct amdgpu_vm *vm)
2319 if (vm->task_info->pid == current->pid)
2322 vm->task_info->pid = current->pid;
2323 get_task_comm(vm->task_info->task_name, current);
2325 if (current->group_leader->mm != current->mm)
2328 vm->task_info->tgid = current->group_leader->pid;
2329 get_task_comm(vm->task_info->process_name, current->group_leader);
2333 * amdgpu_vm_init - initialize a vm instance
2335 * @adev: amdgpu_device pointer
2337 * @xcp_id: GPU partition selection id
2342 * 0 for success, error for failure.
2344 int amdgpu_vm_init(struct amdgpu_device *adev, struct amdgpu_vm *vm,
2347 struct amdgpu_bo *root_bo;
2348 struct amdgpu_bo_vm *root;
2351 vm->va = RB_ROOT_CACHED;
2352 for (i = 0; i < AMDGPU_MAX_VMHUBS; i++)
2353 vm->reserved_vmid[i] = NULL;
2354 INIT_LIST_HEAD(&vm->evicted);
2355 INIT_LIST_HEAD(&vm->evicted_user);
2356 INIT_LIST_HEAD(&vm->relocated);
2357 INIT_LIST_HEAD(&vm->moved);
2358 INIT_LIST_HEAD(&vm->idle);
2359 INIT_LIST_HEAD(&vm->invalidated);
2360 spin_lock_init(&vm->status_lock);
2361 INIT_LIST_HEAD(&vm->freed);
2362 INIT_LIST_HEAD(&vm->done);
2363 INIT_LIST_HEAD(&vm->pt_freed);
2364 INIT_WORK(&vm->pt_free_work, amdgpu_vm_pt_free_work);
2365 INIT_KFIFO(vm->faults);
2367 r = amdgpu_vm_init_entities(adev, vm);
2371 vm->is_compute_context = false;
2373 vm->use_cpu_for_update = !!(adev->vm_manager.vm_update_mode &
2374 AMDGPU_VM_USE_CPU_FOR_GFX);
2376 DRM_DEBUG_DRIVER("VM update mode is %s\n",
2377 vm->use_cpu_for_update ? "CPU" : "SDMA");
2378 WARN_ONCE((vm->use_cpu_for_update &&
2379 !amdgpu_gmc_vram_full_visible(&adev->gmc)),
2380 "CPU update of VM recommended only for large BAR system\n");
2382 if (vm->use_cpu_for_update)
2383 vm->update_funcs = &amdgpu_vm_cpu_funcs;
2385 vm->update_funcs = &amdgpu_vm_sdma_funcs;
2387 vm->last_update = dma_fence_get_stub();
2388 vm->last_unlocked = dma_fence_get_stub();
2389 vm->last_tlb_flush = dma_fence_get_stub();
2392 mutex_init(&vm->eviction_lock);
2393 vm->evicting = false;
2395 r = amdgpu_vm_pt_create(adev, vm, adev->vm_manager.root_level,
2396 false, &root, xcp_id);
2398 goto error_free_delayed;
2400 root_bo = amdgpu_bo_ref(&root->bo);
2401 r = amdgpu_bo_reserve(root_bo, true);
2403 amdgpu_bo_unref(&root->shadow);
2404 amdgpu_bo_unref(&root_bo);
2405 goto error_free_delayed;
2408 amdgpu_vm_bo_base_init(&vm->root, vm, root_bo);
2409 r = dma_resv_reserve_fences(root_bo->tbo.base.resv, 1);
2411 goto error_free_root;
2413 r = amdgpu_vm_pt_clear(adev, vm, root, false);
2415 goto error_free_root;
2417 r = amdgpu_vm_create_task_info(vm);
2419 DRM_DEBUG("Failed to create task info for VM\n");
2421 amdgpu_bo_unreserve(vm->root.bo);
2422 amdgpu_bo_unref(&root_bo);
2427 amdgpu_vm_pt_free_root(adev, vm);
2428 amdgpu_bo_unreserve(vm->root.bo);
2429 amdgpu_bo_unref(&root_bo);
2432 dma_fence_put(vm->last_tlb_flush);
2433 dma_fence_put(vm->last_unlocked);
2434 amdgpu_vm_fini_entities(vm);
2440 * amdgpu_vm_make_compute - Turn a GFX VM into a compute VM
2442 * @adev: amdgpu_device pointer
2445 * This only works on GFX VMs that don't have any BOs added and no
2446 * page tables allocated yet.
2448 * Changes the following VM parameters:
2449 * - use_cpu_for_update
2450 * - pte_supports_ats
2452 * Reinitializes the page directory to reflect the changed ATS
2456 * 0 for success, -errno for errors.
2458 int amdgpu_vm_make_compute(struct amdgpu_device *adev, struct amdgpu_vm *vm)
2462 r = amdgpu_bo_reserve(vm->root.bo, true);
2466 /* Update VM state */
2467 vm->use_cpu_for_update = !!(adev->vm_manager.vm_update_mode &
2468 AMDGPU_VM_USE_CPU_FOR_COMPUTE);
2469 DRM_DEBUG_DRIVER("VM update mode is %s\n",
2470 vm->use_cpu_for_update ? "CPU" : "SDMA");
2471 WARN_ONCE((vm->use_cpu_for_update &&
2472 !amdgpu_gmc_vram_full_visible(&adev->gmc)),
2473 "CPU update of VM recommended only for large BAR system\n");
2475 if (vm->use_cpu_for_update) {
2476 /* Sync with last SDMA update/clear before switching to CPU */
2477 r = amdgpu_bo_sync_wait(vm->root.bo,
2478 AMDGPU_FENCE_OWNER_UNDEFINED, true);
2482 vm->update_funcs = &amdgpu_vm_cpu_funcs;
2483 r = amdgpu_vm_pt_map_tables(adev, vm);
2488 vm->update_funcs = &amdgpu_vm_sdma_funcs;
2491 dma_fence_put(vm->last_update);
2492 vm->last_update = dma_fence_get_stub();
2493 vm->is_compute_context = true;
2495 /* Free the shadow bo for compute VM */
2496 amdgpu_bo_unref(&to_amdgpu_bo_vm(vm->root.bo)->shadow);
2501 amdgpu_bo_unreserve(vm->root.bo);
2506 * amdgpu_vm_release_compute - release a compute vm
2507 * @adev: amdgpu_device pointer
2508 * @vm: a vm turned into compute vm by calling amdgpu_vm_make_compute
2510 * This is a correspondant of amdgpu_vm_make_compute. It decouples compute
2511 * pasid from vm. Compute should stop use of vm after this call.
2513 void amdgpu_vm_release_compute(struct amdgpu_device *adev, struct amdgpu_vm *vm)
2515 amdgpu_vm_set_pasid(adev, vm, 0);
2516 vm->is_compute_context = false;
2520 * amdgpu_vm_fini - tear down a vm instance
2522 * @adev: amdgpu_device pointer
2526 * Unbind the VM and remove all bos from the vm bo list
2528 void amdgpu_vm_fini(struct amdgpu_device *adev, struct amdgpu_vm *vm)
2530 struct amdgpu_bo_va_mapping *mapping, *tmp;
2531 bool prt_fini_needed = !!adev->gmc.gmc_funcs->set_prt;
2532 struct amdgpu_bo *root;
2533 unsigned long flags;
2536 amdgpu_amdkfd_gpuvm_destroy_cb(adev, vm);
2538 flush_work(&vm->pt_free_work);
2540 root = amdgpu_bo_ref(vm->root.bo);
2541 amdgpu_bo_reserve(root, true);
2542 amdgpu_vm_put_task_info(vm->task_info);
2543 amdgpu_vm_set_pasid(adev, vm, 0);
2544 dma_fence_wait(vm->last_unlocked, false);
2545 dma_fence_put(vm->last_unlocked);
2546 dma_fence_wait(vm->last_tlb_flush, false);
2547 /* Make sure that all fence callbacks have completed */
2548 spin_lock_irqsave(vm->last_tlb_flush->lock, flags);
2549 spin_unlock_irqrestore(vm->last_tlb_flush->lock, flags);
2550 dma_fence_put(vm->last_tlb_flush);
2552 list_for_each_entry_safe(mapping, tmp, &vm->freed, list) {
2553 if (mapping->flags & AMDGPU_PTE_PRT && prt_fini_needed) {
2554 amdgpu_vm_prt_fini(adev, vm);
2555 prt_fini_needed = false;
2558 list_del(&mapping->list);
2559 amdgpu_vm_free_mapping(adev, vm, mapping, NULL);
2562 amdgpu_vm_pt_free_root(adev, vm);
2563 amdgpu_bo_unreserve(root);
2564 amdgpu_bo_unref(&root);
2565 WARN_ON(vm->root.bo);
2567 amdgpu_vm_fini_entities(vm);
2569 if (!RB_EMPTY_ROOT(&vm->va.rb_root)) {
2570 dev_err(adev->dev, "still active bo inside vm\n");
2572 rbtree_postorder_for_each_entry_safe(mapping, tmp,
2573 &vm->va.rb_root, rb) {
2574 /* Don't remove the mapping here, we don't want to trigger a
2575 * rebalance and the tree is about to be destroyed anyway.
2577 list_del(&mapping->list);
2581 dma_fence_put(vm->last_update);
2583 for (i = 0; i < AMDGPU_MAX_VMHUBS; i++) {
2584 if (vm->reserved_vmid[i]) {
2585 amdgpu_vmid_free_reserved(adev, i);
2586 vm->reserved_vmid[i] = false;
2593 * amdgpu_vm_manager_init - init the VM manager
2595 * @adev: amdgpu_device pointer
2597 * Initialize the VM manager structures
2599 void amdgpu_vm_manager_init(struct amdgpu_device *adev)
2603 /* Concurrent flushes are only possible starting with Vega10 and
2604 * are broken on Navi10 and Navi14.
2606 adev->vm_manager.concurrent_flush = !(adev->asic_type < CHIP_VEGA10 ||
2607 adev->asic_type == CHIP_NAVI10 ||
2608 adev->asic_type == CHIP_NAVI14);
2609 amdgpu_vmid_mgr_init(adev);
2611 adev->vm_manager.fence_context =
2612 dma_fence_context_alloc(AMDGPU_MAX_RINGS);
2613 for (i = 0; i < AMDGPU_MAX_RINGS; ++i)
2614 adev->vm_manager.seqno[i] = 0;
2616 spin_lock_init(&adev->vm_manager.prt_lock);
2617 atomic_set(&adev->vm_manager.num_prt_users, 0);
2619 /* If not overridden by the user, by default, only in large BAR systems
2620 * Compute VM tables will be updated by CPU
2622 #ifdef CONFIG_X86_64
2623 if (amdgpu_vm_update_mode == -1) {
2624 /* For asic with VF MMIO access protection
2625 * avoid using CPU for VM table updates
2627 if (amdgpu_gmc_vram_full_visible(&adev->gmc) &&
2628 !amdgpu_sriov_vf_mmio_access_protection(adev))
2629 adev->vm_manager.vm_update_mode =
2630 AMDGPU_VM_USE_CPU_FOR_COMPUTE;
2632 adev->vm_manager.vm_update_mode = 0;
2634 adev->vm_manager.vm_update_mode = amdgpu_vm_update_mode;
2636 adev->vm_manager.vm_update_mode = 0;
2639 xa_init_flags(&adev->vm_manager.pasids, XA_FLAGS_LOCK_IRQ);
2643 * amdgpu_vm_manager_fini - cleanup VM manager
2645 * @adev: amdgpu_device pointer
2647 * Cleanup the VM manager and free resources.
2649 void amdgpu_vm_manager_fini(struct amdgpu_device *adev)
2651 WARN_ON(!xa_empty(&adev->vm_manager.pasids));
2652 xa_destroy(&adev->vm_manager.pasids);
2654 amdgpu_vmid_mgr_fini(adev);
2658 * amdgpu_vm_ioctl - Manages VMID reservation for vm hubs.
2660 * @dev: drm device pointer
2661 * @data: drm_amdgpu_vm
2662 * @filp: drm file pointer
2665 * 0 for success, -errno for errors.
2667 int amdgpu_vm_ioctl(struct drm_device *dev, void *data, struct drm_file *filp)
2669 union drm_amdgpu_vm *args = data;
2670 struct amdgpu_device *adev = drm_to_adev(dev);
2671 struct amdgpu_fpriv *fpriv = filp->driver_priv;
2673 /* No valid flags defined yet */
2677 switch (args->in.op) {
2678 case AMDGPU_VM_OP_RESERVE_VMID:
2679 /* We only have requirement to reserve vmid from gfxhub */
2680 if (!fpriv->vm.reserved_vmid[AMDGPU_GFXHUB(0)]) {
2681 amdgpu_vmid_alloc_reserved(adev, AMDGPU_GFXHUB(0));
2682 fpriv->vm.reserved_vmid[AMDGPU_GFXHUB(0)] = true;
2686 case AMDGPU_VM_OP_UNRESERVE_VMID:
2687 if (fpriv->vm.reserved_vmid[AMDGPU_GFXHUB(0)]) {
2688 amdgpu_vmid_free_reserved(adev, AMDGPU_GFXHUB(0));
2689 fpriv->vm.reserved_vmid[AMDGPU_GFXHUB(0)] = false;
2700 * amdgpu_vm_handle_fault - graceful handling of VM faults.
2701 * @adev: amdgpu device pointer
2702 * @pasid: PASID of the VM
2703 * @vmid: VMID, only used for GFX 9.4.3.
2704 * @node_id: Node_id received in IH cookie. Only applicable for
2706 * @addr: Address of the fault
2707 * @write_fault: true is write fault, false is read fault
2709 * Try to gracefully handle a VM fault. Return true if the fault was handled and
2710 * shouldn't be reported any more.
2712 bool amdgpu_vm_handle_fault(struct amdgpu_device *adev, u32 pasid,
2713 u32 vmid, u32 node_id, uint64_t addr,
2716 bool is_compute_context = false;
2717 struct amdgpu_bo *root;
2718 unsigned long irqflags;
2719 uint64_t value, flags;
2720 struct amdgpu_vm *vm;
2723 xa_lock_irqsave(&adev->vm_manager.pasids, irqflags);
2724 vm = xa_load(&adev->vm_manager.pasids, pasid);
2726 root = amdgpu_bo_ref(vm->root.bo);
2727 is_compute_context = vm->is_compute_context;
2731 xa_unlock_irqrestore(&adev->vm_manager.pasids, irqflags);
2736 addr /= AMDGPU_GPU_PAGE_SIZE;
2738 if (is_compute_context && !svm_range_restore_pages(adev, pasid, vmid,
2739 node_id, addr, write_fault)) {
2740 amdgpu_bo_unref(&root);
2744 r = amdgpu_bo_reserve(root, true);
2748 /* Double check that the VM still exists */
2749 xa_lock_irqsave(&adev->vm_manager.pasids, irqflags);
2750 vm = xa_load(&adev->vm_manager.pasids, pasid);
2751 if (vm && vm->root.bo != root)
2753 xa_unlock_irqrestore(&adev->vm_manager.pasids, irqflags);
2757 flags = AMDGPU_PTE_VALID | AMDGPU_PTE_SNOOPED |
2760 if (is_compute_context) {
2761 /* Intentionally setting invalid PTE flag
2762 * combination to force a no-retry-fault
2764 flags = AMDGPU_VM_NORETRY_FLAGS;
2766 } else if (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_NEVER) {
2767 /* Redirect the access to the dummy page */
2768 value = adev->dummy_page_addr;
2769 flags |= AMDGPU_PTE_EXECUTABLE | AMDGPU_PTE_READABLE |
2770 AMDGPU_PTE_WRITEABLE;
2773 /* Let the hw retry silently on the PTE */
2777 r = dma_resv_reserve_fences(root->tbo.base.resv, 1);
2779 pr_debug("failed %d to reserve fence slot\n", r);
2783 r = amdgpu_vm_update_range(adev, vm, true, false, false, false,
2784 NULL, addr, addr, flags, value, 0, NULL, NULL, NULL);
2788 r = amdgpu_vm_update_pdes(adev, vm, true);
2791 amdgpu_bo_unreserve(root);
2793 DRM_ERROR("Can't handle page fault (%d)\n", r);
2796 amdgpu_bo_unref(&root);
2801 #if defined(CONFIG_DEBUG_FS)
2803 * amdgpu_debugfs_vm_bo_info - print BO info for the VM
2805 * @vm: Requested VM for printing BO info
2808 * Print BO information in debugfs file for the VM
2810 void amdgpu_debugfs_vm_bo_info(struct amdgpu_vm *vm, struct seq_file *m)
2812 struct amdgpu_bo_va *bo_va, *tmp;
2814 u64 total_evicted = 0;
2815 u64 total_relocated = 0;
2816 u64 total_moved = 0;
2817 u64 total_invalidated = 0;
2819 unsigned int total_idle_objs = 0;
2820 unsigned int total_evicted_objs = 0;
2821 unsigned int total_relocated_objs = 0;
2822 unsigned int total_moved_objs = 0;
2823 unsigned int total_invalidated_objs = 0;
2824 unsigned int total_done_objs = 0;
2825 unsigned int id = 0;
2827 spin_lock(&vm->status_lock);
2828 seq_puts(m, "\tIdle BOs:\n");
2829 list_for_each_entry_safe(bo_va, tmp, &vm->idle, base.vm_status) {
2830 if (!bo_va->base.bo)
2832 total_idle += amdgpu_bo_print_info(id++, bo_va->base.bo, m);
2834 total_idle_objs = id;
2837 seq_puts(m, "\tEvicted BOs:\n");
2838 list_for_each_entry_safe(bo_va, tmp, &vm->evicted, base.vm_status) {
2839 if (!bo_va->base.bo)
2841 total_evicted += amdgpu_bo_print_info(id++, bo_va->base.bo, m);
2843 total_evicted_objs = id;
2846 seq_puts(m, "\tRelocated BOs:\n");
2847 list_for_each_entry_safe(bo_va, tmp, &vm->relocated, base.vm_status) {
2848 if (!bo_va->base.bo)
2850 total_relocated += amdgpu_bo_print_info(id++, bo_va->base.bo, m);
2852 total_relocated_objs = id;
2855 seq_puts(m, "\tMoved BOs:\n");
2856 list_for_each_entry_safe(bo_va, tmp, &vm->moved, base.vm_status) {
2857 if (!bo_va->base.bo)
2859 total_moved += amdgpu_bo_print_info(id++, bo_va->base.bo, m);
2861 total_moved_objs = id;
2864 seq_puts(m, "\tInvalidated BOs:\n");
2865 list_for_each_entry_safe(bo_va, tmp, &vm->invalidated, base.vm_status) {
2866 if (!bo_va->base.bo)
2868 total_invalidated += amdgpu_bo_print_info(id++, bo_va->base.bo, m);
2870 total_invalidated_objs = id;
2873 seq_puts(m, "\tDone BOs:\n");
2874 list_for_each_entry_safe(bo_va, tmp, &vm->done, base.vm_status) {
2875 if (!bo_va->base.bo)
2877 total_done += amdgpu_bo_print_info(id++, bo_va->base.bo, m);
2879 spin_unlock(&vm->status_lock);
2880 total_done_objs = id;
2882 seq_printf(m, "\tTotal idle size: %12lld\tobjs:\t%d\n", total_idle,
2884 seq_printf(m, "\tTotal evicted size: %12lld\tobjs:\t%d\n", total_evicted,
2885 total_evicted_objs);
2886 seq_printf(m, "\tTotal relocated size: %12lld\tobjs:\t%d\n", total_relocated,
2887 total_relocated_objs);
2888 seq_printf(m, "\tTotal moved size: %12lld\tobjs:\t%d\n", total_moved,
2890 seq_printf(m, "\tTotal invalidated size: %12lld\tobjs:\t%d\n", total_invalidated,
2891 total_invalidated_objs);
2892 seq_printf(m, "\tTotal done size: %12lld\tobjs:\t%d\n", total_done,
2898 * amdgpu_vm_update_fault_cache - update cached fault into.
2899 * @adev: amdgpu device pointer
2900 * @pasid: PASID of the VM
2901 * @addr: Address of the fault
2902 * @status: GPUVM fault status register
2903 * @vmhub: which vmhub got the fault
2905 * Cache the fault info for later use by userspace in debugging.
2907 void amdgpu_vm_update_fault_cache(struct amdgpu_device *adev,
2913 struct amdgpu_vm *vm;
2914 unsigned long flags;
2916 xa_lock_irqsave(&adev->vm_manager.pasids, flags);
2918 vm = xa_load(&adev->vm_manager.pasids, pasid);
2919 /* Don't update the fault cache if status is 0. In the multiple
2920 * fault case, subsequent faults will return a 0 status which is
2921 * useless for userspace and replaces the useful fault status, so
2922 * only update if status is non-0.
2925 vm->fault_info.addr = addr;
2926 vm->fault_info.status = status;
2927 if (AMDGPU_IS_GFXHUB(vmhub)) {
2928 vm->fault_info.vmhub = AMDGPU_VMHUB_TYPE_GFX;
2929 vm->fault_info.vmhub |=
2930 (vmhub - AMDGPU_GFXHUB_START) << AMDGPU_VMHUB_IDX_SHIFT;
2931 } else if (AMDGPU_IS_MMHUB0(vmhub)) {
2932 vm->fault_info.vmhub = AMDGPU_VMHUB_TYPE_MM0;
2933 vm->fault_info.vmhub |=
2934 (vmhub - AMDGPU_MMHUB0_START) << AMDGPU_VMHUB_IDX_SHIFT;
2935 } else if (AMDGPU_IS_MMHUB1(vmhub)) {
2936 vm->fault_info.vmhub = AMDGPU_VMHUB_TYPE_MM1;
2937 vm->fault_info.vmhub |=
2938 (vmhub - AMDGPU_MMHUB1_START) << AMDGPU_VMHUB_IDX_SHIFT;
2940 WARN_ONCE(1, "Invalid vmhub %u\n", vmhub);
2943 xa_unlock_irqrestore(&adev->vm_manager.pasids, flags);