2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
24 * Authors: Dave Airlie
28 #include <linux/dma-fence-array.h>
29 #include <linux/interval_tree_generic.h>
31 #include <drm/amdgpu_drm.h>
33 #include "amdgpu_trace.h"
37 * GPUVM is similar to the legacy gart on older asics, however
38 * rather than there being a single global gart table
39 * for the entire GPU, there are multiple VM page tables active
40 * at any given time. The VM page tables can contain a mix
41 * vram pages and system memory pages and system memory pages
42 * can be mapped as snooped (cached system pages) or unsnooped
43 * (uncached system pages).
44 * Each VM has an ID associated with it and there is a page table
45 * associated with each VMID. When execting a command buffer,
46 * the kernel tells the the ring what VMID to use for that command
47 * buffer. VMIDs are allocated dynamically as commands are submitted.
48 * The userspace drivers maintain their own address space and the kernel
49 * sets up their pages tables accordingly when they submit their
50 * command buffers and a VMID is assigned.
51 * Cayman/Trinity support up to 8 active VMs at any given time;
55 #define START(node) ((node)->start)
56 #define LAST(node) ((node)->last)
58 INTERVAL_TREE_DEFINE(struct amdgpu_bo_va_mapping, rb, uint64_t, __subtree_last,
59 START, LAST, static, amdgpu_vm_it)
64 /* Local structure. Encapsulate some VM table update parameters to reduce
65 * the number of function parameters
67 struct amdgpu_pte_update_params {
68 /* amdgpu device we do this update for */
69 struct amdgpu_device *adev;
70 /* optional amdgpu_vm we do this update for */
72 /* address where to copy page table entries from */
74 /* indirect buffer to fill with commands */
76 /* Function which actually does the update */
77 void (*func)(struct amdgpu_pte_update_params *params, uint64_t pe,
78 uint64_t addr, unsigned count, uint32_t incr,
80 /* The next two are used during VM update by CPU
81 * DMA addresses to use for mapping
82 * Kernel pointer of PD/PT BO that needs to be updated
84 dma_addr_t *pages_addr;
88 /* Helper to disable partial resident texture feature from a fence callback */
89 struct amdgpu_prt_cb {
90 struct amdgpu_device *adev;
91 struct dma_fence_cb cb;
95 * amdgpu_vm_num_entries - return the number of entries in a PD/PT
97 * @adev: amdgpu_device pointer
99 * Calculate the number of entries in a page directory or page table.
101 static unsigned amdgpu_vm_num_entries(struct amdgpu_device *adev,
105 /* For the root directory */
106 return adev->vm_manager.max_pfn >>
107 (adev->vm_manager.block_size *
108 adev->vm_manager.num_level);
109 else if (level == adev->vm_manager.num_level)
110 /* For the page tables on the leaves */
111 return AMDGPU_VM_PTE_COUNT(adev);
113 /* Everything in between */
114 return 1 << adev->vm_manager.block_size;
118 * amdgpu_vm_bo_size - returns the size of the BOs in bytes
120 * @adev: amdgpu_device pointer
122 * Calculate the size of the BO for a page directory or page table in bytes.
124 static unsigned amdgpu_vm_bo_size(struct amdgpu_device *adev, unsigned level)
126 return AMDGPU_GPU_PAGE_ALIGN(amdgpu_vm_num_entries(adev, level) * 8);
130 * amdgpu_vm_get_pd_bo - add the VM PD to a validation list
132 * @vm: vm providing the BOs
133 * @validated: head of validation list
134 * @entry: entry to add
136 * Add the page directory to the list of BOs to
137 * validate for command submission.
139 void amdgpu_vm_get_pd_bo(struct amdgpu_vm *vm,
140 struct list_head *validated,
141 struct amdgpu_bo_list_entry *entry)
143 entry->robj = vm->root.bo;
145 entry->tv.bo = &entry->robj->tbo;
146 entry->tv.shared = true;
147 entry->user_pages = NULL;
148 list_add(&entry->tv.head, validated);
152 * amdgpu_vm_validate_layer - validate a single page table level
154 * @parent: parent page table level
155 * @validate: callback to do the validation
156 * @param: parameter for the validation callback
158 * Validate the page table BOs on command submission if neccessary.
160 static int amdgpu_vm_validate_level(struct amdgpu_vm_pt *parent,
161 int (*validate)(void *, struct amdgpu_bo *),
167 if (!parent->entries)
170 for (i = 0; i <= parent->last_entry_used; ++i) {
171 struct amdgpu_vm_pt *entry = &parent->entries[i];
176 r = validate(param, entry->bo);
181 * Recurse into the sub directory. This is harmless because we
182 * have only a maximum of 5 layers.
184 r = amdgpu_vm_validate_level(entry, validate, param);
193 * amdgpu_vm_validate_pt_bos - validate the page table BOs
195 * @adev: amdgpu device pointer
196 * @vm: vm providing the BOs
197 * @validate: callback to do the validation
198 * @param: parameter for the validation callback
200 * Validate the page table BOs on command submission if neccessary.
202 int amdgpu_vm_validate_pt_bos(struct amdgpu_device *adev, struct amdgpu_vm *vm,
203 int (*validate)(void *p, struct amdgpu_bo *bo),
206 uint64_t num_evictions;
208 /* We only need to validate the page tables
209 * if they aren't already valid.
211 num_evictions = atomic64_read(&adev->num_evictions);
212 if (num_evictions == vm->last_eviction_counter)
215 return amdgpu_vm_validate_level(&vm->root, validate, param);
219 * amdgpu_vm_move_level_in_lru - move one level of PT BOs to the LRU tail
221 * @adev: amdgpu device instance
222 * @vm: vm providing the BOs
224 * Move the PT BOs to the tail of the LRU.
226 static void amdgpu_vm_move_level_in_lru(struct amdgpu_vm_pt *parent)
230 if (!parent->entries)
233 for (i = 0; i <= parent->last_entry_used; ++i) {
234 struct amdgpu_vm_pt *entry = &parent->entries[i];
239 ttm_bo_move_to_lru_tail(&entry->bo->tbo);
240 amdgpu_vm_move_level_in_lru(entry);
245 * amdgpu_vm_move_pt_bos_in_lru - move the PT BOs to the LRU tail
247 * @adev: amdgpu device instance
248 * @vm: vm providing the BOs
250 * Move the PT BOs to the tail of the LRU.
252 void amdgpu_vm_move_pt_bos_in_lru(struct amdgpu_device *adev,
253 struct amdgpu_vm *vm)
255 struct ttm_bo_global *glob = adev->mman.bdev.glob;
257 spin_lock(&glob->lru_lock);
258 amdgpu_vm_move_level_in_lru(&vm->root);
259 spin_unlock(&glob->lru_lock);
263 * amdgpu_vm_alloc_levels - allocate the PD/PT levels
265 * @adev: amdgpu_device pointer
267 * @saddr: start of the address range
268 * @eaddr: end of the address range
270 * Make sure the page directories and page tables are allocated
272 static int amdgpu_vm_alloc_levels(struct amdgpu_device *adev,
273 struct amdgpu_vm *vm,
274 struct amdgpu_vm_pt *parent,
275 uint64_t saddr, uint64_t eaddr,
278 unsigned shift = (adev->vm_manager.num_level - level) *
279 adev->vm_manager.block_size;
280 unsigned pt_idx, from, to;
284 if (!parent->entries) {
285 unsigned num_entries = amdgpu_vm_num_entries(adev, level);
287 parent->entries = kvmalloc_array(num_entries,
288 sizeof(struct amdgpu_vm_pt),
289 GFP_KERNEL | __GFP_ZERO);
290 if (!parent->entries)
292 memset(parent->entries, 0 , sizeof(struct amdgpu_vm_pt));
295 from = saddr >> shift;
297 if (from >= amdgpu_vm_num_entries(adev, level) ||
298 to >= amdgpu_vm_num_entries(adev, level))
301 if (to > parent->last_entry_used)
302 parent->last_entry_used = to;
305 saddr = saddr & ((1 << shift) - 1);
306 eaddr = eaddr & ((1 << shift) - 1);
308 flags = AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS |
309 AMDGPU_GEM_CREATE_VRAM_CLEARED;
310 if (vm->use_cpu_for_update)
311 flags |= AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED;
313 flags |= (AMDGPU_GEM_CREATE_NO_CPU_ACCESS |
314 AMDGPU_GEM_CREATE_SHADOW);
316 /* walk over the address space and allocate the page tables */
317 for (pt_idx = from; pt_idx <= to; ++pt_idx) {
318 struct reservation_object *resv = vm->root.bo->tbo.resv;
319 struct amdgpu_vm_pt *entry = &parent->entries[pt_idx];
320 struct amdgpu_bo *pt;
323 r = amdgpu_bo_create(adev,
324 amdgpu_vm_bo_size(adev, level),
325 AMDGPU_GPU_PAGE_SIZE, true,
326 AMDGPU_GEM_DOMAIN_VRAM,
332 /* Keep a reference to the root directory to avoid
333 * freeing them up in the wrong order.
335 pt->parent = amdgpu_bo_ref(vm->root.bo);
341 if (level < adev->vm_manager.num_level) {
342 uint64_t sub_saddr = (pt_idx == from) ? saddr : 0;
343 uint64_t sub_eaddr = (pt_idx == to) ? eaddr :
345 r = amdgpu_vm_alloc_levels(adev, vm, entry, sub_saddr,
356 * amdgpu_vm_alloc_pts - Allocate page tables.
358 * @adev: amdgpu_device pointer
359 * @vm: VM to allocate page tables for
360 * @saddr: Start address which needs to be allocated
361 * @size: Size from start address we need.
363 * Make sure the page tables are allocated.
365 int amdgpu_vm_alloc_pts(struct amdgpu_device *adev,
366 struct amdgpu_vm *vm,
367 uint64_t saddr, uint64_t size)
372 /* validate the parameters */
373 if (saddr & AMDGPU_GPU_PAGE_MASK || size & AMDGPU_GPU_PAGE_MASK)
376 eaddr = saddr + size - 1;
377 last_pfn = eaddr / AMDGPU_GPU_PAGE_SIZE;
378 if (last_pfn >= adev->vm_manager.max_pfn) {
379 dev_err(adev->dev, "va above limit (0x%08llX >= 0x%08llX)\n",
380 last_pfn, adev->vm_manager.max_pfn);
384 saddr /= AMDGPU_GPU_PAGE_SIZE;
385 eaddr /= AMDGPU_GPU_PAGE_SIZE;
387 return amdgpu_vm_alloc_levels(adev, vm, &vm->root, saddr, eaddr, 0);
391 * amdgpu_vm_had_gpu_reset - check if reset occured since last use
393 * @adev: amdgpu_device pointer
394 * @id: VMID structure
396 * Check if GPU reset occured since last use of the VMID.
398 static bool amdgpu_vm_had_gpu_reset(struct amdgpu_device *adev,
399 struct amdgpu_vm_id *id)
401 return id->current_gpu_reset_count !=
402 atomic_read(&adev->gpu_reset_counter);
405 static bool amdgpu_vm_reserved_vmid_ready(struct amdgpu_vm *vm, unsigned vmhub)
407 return !!vm->reserved_vmid[vmhub];
410 /* idr_mgr->lock must be held */
411 static int amdgpu_vm_grab_reserved_vmid_locked(struct amdgpu_vm *vm,
412 struct amdgpu_ring *ring,
413 struct amdgpu_sync *sync,
414 struct dma_fence *fence,
415 struct amdgpu_job *job)
417 struct amdgpu_device *adev = ring->adev;
418 unsigned vmhub = ring->funcs->vmhub;
419 uint64_t fence_context = adev->fence_context + ring->idx;
420 struct amdgpu_vm_id *id = vm->reserved_vmid[vmhub];
421 struct amdgpu_vm_id_manager *id_mgr = &adev->vm_manager.id_mgr[vmhub];
422 struct dma_fence *updates = sync->last_vm_update;
424 struct dma_fence *flushed, *tmp;
425 bool needs_flush = vm->use_cpu_for_update;
427 flushed = id->flushed_updates;
428 if ((amdgpu_vm_had_gpu_reset(adev, id)) ||
429 (atomic64_read(&id->owner) != vm->client_id) ||
430 (job->vm_pd_addr != id->pd_gpu_addr) ||
431 (updates && (!flushed || updates->context != flushed->context ||
432 dma_fence_is_later(updates, flushed))) ||
433 (!id->last_flush || (id->last_flush->context != fence_context &&
434 !dma_fence_is_signaled(id->last_flush)))) {
436 /* to prevent one context starved by another context */
438 tmp = amdgpu_sync_peek_fence(&id->active, ring);
440 r = amdgpu_sync_fence(adev, sync, tmp);
445 /* Good we can use this VMID. Remember this submission as
448 r = amdgpu_sync_fence(ring->adev, &id->active, fence);
452 if (updates && (!flushed || updates->context != flushed->context ||
453 dma_fence_is_later(updates, flushed))) {
454 dma_fence_put(id->flushed_updates);
455 id->flushed_updates = dma_fence_get(updates);
457 id->pd_gpu_addr = job->vm_pd_addr;
458 atomic64_set(&id->owner, vm->client_id);
459 job->vm_needs_flush = needs_flush;
461 dma_fence_put(id->last_flush);
462 id->last_flush = NULL;
464 job->vm_id = id - id_mgr->ids;
465 trace_amdgpu_vm_grab_id(vm, ring, job);
471 * amdgpu_vm_grab_id - allocate the next free VMID
473 * @vm: vm to allocate id for
474 * @ring: ring we want to submit job to
475 * @sync: sync object where we add dependencies
476 * @fence: fence protecting ID from reuse
478 * Allocate an id for the vm, adding fences to the sync obj as necessary.
480 int amdgpu_vm_grab_id(struct amdgpu_vm *vm, struct amdgpu_ring *ring,
481 struct amdgpu_sync *sync, struct dma_fence *fence,
482 struct amdgpu_job *job)
484 struct amdgpu_device *adev = ring->adev;
485 unsigned vmhub = ring->funcs->vmhub;
486 struct amdgpu_vm_id_manager *id_mgr = &adev->vm_manager.id_mgr[vmhub];
487 uint64_t fence_context = adev->fence_context + ring->idx;
488 struct dma_fence *updates = sync->last_vm_update;
489 struct amdgpu_vm_id *id, *idle;
490 struct dma_fence **fences;
494 mutex_lock(&id_mgr->lock);
495 if (amdgpu_vm_reserved_vmid_ready(vm, vmhub)) {
496 r = amdgpu_vm_grab_reserved_vmid_locked(vm, ring, sync, fence, job);
497 mutex_unlock(&id_mgr->lock);
500 fences = kmalloc_array(sizeof(void *), id_mgr->num_ids, GFP_KERNEL);
502 mutex_unlock(&id_mgr->lock);
505 /* Check if we have an idle VMID */
507 list_for_each_entry(idle, &id_mgr->ids_lru, list) {
508 fences[i] = amdgpu_sync_peek_fence(&idle->active, ring);
514 /* If we can't find a idle VMID to use, wait till one becomes available */
515 if (&idle->list == &id_mgr->ids_lru) {
516 u64 fence_context = adev->vm_manager.fence_context + ring->idx;
517 unsigned seqno = ++adev->vm_manager.seqno[ring->idx];
518 struct dma_fence_array *array;
521 for (j = 0; j < i; ++j)
522 dma_fence_get(fences[j]);
524 array = dma_fence_array_create(i, fences, fence_context,
527 for (j = 0; j < i; ++j)
528 dma_fence_put(fences[j]);
535 r = amdgpu_sync_fence(ring->adev, sync, &array->base);
536 dma_fence_put(&array->base);
540 mutex_unlock(&id_mgr->lock);
546 job->vm_needs_flush = vm->use_cpu_for_update;
547 /* Check if we can use a VMID already assigned to this VM */
548 list_for_each_entry_reverse(id, &id_mgr->ids_lru, list) {
549 struct dma_fence *flushed;
550 bool needs_flush = vm->use_cpu_for_update;
552 /* Check all the prerequisites to using this VMID */
553 if (amdgpu_vm_had_gpu_reset(adev, id))
556 if (atomic64_read(&id->owner) != vm->client_id)
559 if (job->vm_pd_addr != id->pd_gpu_addr)
562 if (!id->last_flush ||
563 (id->last_flush->context != fence_context &&
564 !dma_fence_is_signaled(id->last_flush)))
567 flushed = id->flushed_updates;
568 if (updates && (!flushed || dma_fence_is_later(updates, flushed)))
571 /* Concurrent flushes are only possible starting with Vega10 */
572 if (adev->asic_type < CHIP_VEGA10 && needs_flush)
575 /* Good we can use this VMID. Remember this submission as
578 r = amdgpu_sync_fence(ring->adev, &id->active, fence);
582 if (updates && (!flushed || dma_fence_is_later(updates, flushed))) {
583 dma_fence_put(id->flushed_updates);
584 id->flushed_updates = dma_fence_get(updates);
590 goto no_flush_needed;
594 /* Still no ID to use? Then use the idle one found earlier */
597 /* Remember this submission as user of the VMID */
598 r = amdgpu_sync_fence(ring->adev, &id->active, fence);
602 id->pd_gpu_addr = job->vm_pd_addr;
603 dma_fence_put(id->flushed_updates);
604 id->flushed_updates = dma_fence_get(updates);
605 atomic64_set(&id->owner, vm->client_id);
608 job->vm_needs_flush = true;
609 dma_fence_put(id->last_flush);
610 id->last_flush = NULL;
613 list_move_tail(&id->list, &id_mgr->ids_lru);
615 job->vm_id = id - id_mgr->ids;
616 trace_amdgpu_vm_grab_id(vm, ring, job);
619 mutex_unlock(&id_mgr->lock);
623 static void amdgpu_vm_free_reserved_vmid(struct amdgpu_device *adev,
624 struct amdgpu_vm *vm,
627 struct amdgpu_vm_id_manager *id_mgr = &adev->vm_manager.id_mgr[vmhub];
629 mutex_lock(&id_mgr->lock);
630 if (vm->reserved_vmid[vmhub]) {
631 list_add(&vm->reserved_vmid[vmhub]->list,
633 vm->reserved_vmid[vmhub] = NULL;
634 atomic_dec(&id_mgr->reserved_vmid_num);
636 mutex_unlock(&id_mgr->lock);
639 static int amdgpu_vm_alloc_reserved_vmid(struct amdgpu_device *adev,
640 struct amdgpu_vm *vm,
643 struct amdgpu_vm_id_manager *id_mgr;
644 struct amdgpu_vm_id *idle;
647 id_mgr = &adev->vm_manager.id_mgr[vmhub];
648 mutex_lock(&id_mgr->lock);
649 if (vm->reserved_vmid[vmhub])
651 if (atomic_inc_return(&id_mgr->reserved_vmid_num) >
652 AMDGPU_VM_MAX_RESERVED_VMID) {
653 DRM_ERROR("Over limitation of reserved vmid\n");
654 atomic_dec(&id_mgr->reserved_vmid_num);
658 /* Select the first entry VMID */
659 idle = list_first_entry(&id_mgr->ids_lru, struct amdgpu_vm_id, list);
660 list_del_init(&idle->list);
661 vm->reserved_vmid[vmhub] = idle;
662 mutex_unlock(&id_mgr->lock);
666 mutex_unlock(&id_mgr->lock);
671 * amdgpu_vm_check_compute_bug - check whether asic has compute vm bug
673 * @adev: amdgpu_device pointer
675 void amdgpu_vm_check_compute_bug(struct amdgpu_device *adev)
677 const struct amdgpu_ip_block *ip_block;
678 bool has_compute_vm_bug;
679 struct amdgpu_ring *ring;
682 has_compute_vm_bug = false;
684 ip_block = amdgpu_get_ip_block(adev, AMD_IP_BLOCK_TYPE_GFX);
686 /* Compute has a VM bug for GFX version < 7.
687 Compute has a VM bug for GFX 8 MEC firmware version < 673.*/
688 if (ip_block->version->major <= 7)
689 has_compute_vm_bug = true;
690 else if (ip_block->version->major == 8)
691 if (adev->gfx.mec_fw_version < 673)
692 has_compute_vm_bug = true;
695 for (i = 0; i < adev->num_rings; i++) {
696 ring = adev->rings[i];
697 if (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE)
698 /* only compute rings */
699 ring->has_compute_vm_bug = has_compute_vm_bug;
701 ring->has_compute_vm_bug = false;
705 bool amdgpu_vm_need_pipeline_sync(struct amdgpu_ring *ring,
706 struct amdgpu_job *job)
708 struct amdgpu_device *adev = ring->adev;
709 unsigned vmhub = ring->funcs->vmhub;
710 struct amdgpu_vm_id_manager *id_mgr = &adev->vm_manager.id_mgr[vmhub];
711 struct amdgpu_vm_id *id;
712 bool gds_switch_needed;
713 bool vm_flush_needed = job->vm_needs_flush || ring->has_compute_vm_bug;
717 id = &id_mgr->ids[job->vm_id];
718 gds_switch_needed = ring->funcs->emit_gds_switch && (
719 id->gds_base != job->gds_base ||
720 id->gds_size != job->gds_size ||
721 id->gws_base != job->gws_base ||
722 id->gws_size != job->gws_size ||
723 id->oa_base != job->oa_base ||
724 id->oa_size != job->oa_size);
726 if (amdgpu_vm_had_gpu_reset(adev, id))
729 return vm_flush_needed || gds_switch_needed;
732 static bool amdgpu_vm_is_large_bar(struct amdgpu_device *adev)
734 return (adev->mc.real_vram_size == adev->mc.visible_vram_size);
738 * amdgpu_vm_flush - hardware flush the vm
740 * @ring: ring to use for flush
741 * @vm_id: vmid number to use
742 * @pd_addr: address of the page directory
744 * Emit a VM flush when it is necessary.
746 int amdgpu_vm_flush(struct amdgpu_ring *ring, struct amdgpu_job *job, bool need_pipe_sync)
748 struct amdgpu_device *adev = ring->adev;
749 unsigned vmhub = ring->funcs->vmhub;
750 struct amdgpu_vm_id_manager *id_mgr = &adev->vm_manager.id_mgr[vmhub];
751 struct amdgpu_vm_id *id = &id_mgr->ids[job->vm_id];
752 bool gds_switch_needed = ring->funcs->emit_gds_switch && (
753 id->gds_base != job->gds_base ||
754 id->gds_size != job->gds_size ||
755 id->gws_base != job->gws_base ||
756 id->gws_size != job->gws_size ||
757 id->oa_base != job->oa_base ||
758 id->oa_size != job->oa_size);
759 bool vm_flush_needed = job->vm_needs_flush;
760 unsigned patch_offset = 0;
763 if (amdgpu_vm_had_gpu_reset(adev, id)) {
764 gds_switch_needed = true;
765 vm_flush_needed = true;
768 if (!vm_flush_needed && !gds_switch_needed && !need_pipe_sync)
771 if (ring->funcs->init_cond_exec)
772 patch_offset = amdgpu_ring_init_cond_exec(ring);
775 amdgpu_ring_emit_pipeline_sync(ring);
777 if (ring->funcs->emit_vm_flush && vm_flush_needed) {
778 struct dma_fence *fence;
780 trace_amdgpu_vm_flush(ring, job->vm_id, job->vm_pd_addr);
781 amdgpu_ring_emit_vm_flush(ring, job->vm_id, job->vm_pd_addr);
783 r = amdgpu_fence_emit(ring, &fence);
787 mutex_lock(&id_mgr->lock);
788 dma_fence_put(id->last_flush);
789 id->last_flush = fence;
790 id->current_gpu_reset_count = atomic_read(&adev->gpu_reset_counter);
791 mutex_unlock(&id_mgr->lock);
794 if (ring->funcs->emit_gds_switch && gds_switch_needed) {
795 id->gds_base = job->gds_base;
796 id->gds_size = job->gds_size;
797 id->gws_base = job->gws_base;
798 id->gws_size = job->gws_size;
799 id->oa_base = job->oa_base;
800 id->oa_size = job->oa_size;
801 amdgpu_ring_emit_gds_switch(ring, job->vm_id, job->gds_base,
802 job->gds_size, job->gws_base,
803 job->gws_size, job->oa_base,
807 if (ring->funcs->patch_cond_exec)
808 amdgpu_ring_patch_cond_exec(ring, patch_offset);
810 /* the double SWITCH_BUFFER here *cannot* be skipped by COND_EXEC */
811 if (ring->funcs->emit_switch_buffer) {
812 amdgpu_ring_emit_switch_buffer(ring);
813 amdgpu_ring_emit_switch_buffer(ring);
819 * amdgpu_vm_reset_id - reset VMID to zero
821 * @adev: amdgpu device structure
822 * @vm_id: vmid number to use
824 * Reset saved GDW, GWS and OA to force switch on next flush.
826 void amdgpu_vm_reset_id(struct amdgpu_device *adev, unsigned vmhub,
829 struct amdgpu_vm_id_manager *id_mgr = &adev->vm_manager.id_mgr[vmhub];
830 struct amdgpu_vm_id *id = &id_mgr->ids[vmid];
832 atomic64_set(&id->owner, 0);
842 * amdgpu_vm_reset_all_id - reset VMID to zero
844 * @adev: amdgpu device structure
846 * Reset VMID to force flush on next use
848 void amdgpu_vm_reset_all_ids(struct amdgpu_device *adev)
852 for (i = 0; i < AMDGPU_MAX_VMHUBS; ++i) {
853 struct amdgpu_vm_id_manager *id_mgr =
854 &adev->vm_manager.id_mgr[i];
856 for (j = 1; j < id_mgr->num_ids; ++j)
857 amdgpu_vm_reset_id(adev, i, j);
862 * amdgpu_vm_bo_find - find the bo_va for a specific vm & bo
865 * @bo: requested buffer object
867 * Find @bo inside the requested vm.
868 * Search inside the @bos vm list for the requested vm
869 * Returns the found bo_va or NULL if none is found
871 * Object has to be reserved!
873 struct amdgpu_bo_va *amdgpu_vm_bo_find(struct amdgpu_vm *vm,
874 struct amdgpu_bo *bo)
876 struct amdgpu_bo_va *bo_va;
878 list_for_each_entry(bo_va, &bo->va, bo_list) {
879 if (bo_va->vm == vm) {
887 * amdgpu_vm_do_set_ptes - helper to call the right asic function
889 * @params: see amdgpu_pte_update_params definition
890 * @pe: addr of the page entry
891 * @addr: dst addr to write into pe
892 * @count: number of page entries to update
893 * @incr: increase next addr by incr bytes
894 * @flags: hw access flags
896 * Traces the parameters and calls the right asic functions
897 * to setup the page table using the DMA.
899 static void amdgpu_vm_do_set_ptes(struct amdgpu_pte_update_params *params,
900 uint64_t pe, uint64_t addr,
901 unsigned count, uint32_t incr,
904 trace_amdgpu_vm_set_ptes(pe, addr, count, incr, flags);
907 amdgpu_vm_write_pte(params->adev, params->ib, pe,
908 addr | flags, count, incr);
911 amdgpu_vm_set_pte_pde(params->adev, params->ib, pe, addr,
917 * amdgpu_vm_do_copy_ptes - copy the PTEs from the GART
919 * @params: see amdgpu_pte_update_params definition
920 * @pe: addr of the page entry
921 * @addr: dst addr to write into pe
922 * @count: number of page entries to update
923 * @incr: increase next addr by incr bytes
924 * @flags: hw access flags
926 * Traces the parameters and calls the DMA function to copy the PTEs.
928 static void amdgpu_vm_do_copy_ptes(struct amdgpu_pte_update_params *params,
929 uint64_t pe, uint64_t addr,
930 unsigned count, uint32_t incr,
933 uint64_t src = (params->src + (addr >> 12) * 8);
936 trace_amdgpu_vm_copy_ptes(pe, src, count);
938 amdgpu_vm_copy_pte(params->adev, params->ib, pe, src, count);
942 * amdgpu_vm_map_gart - Resolve gart mapping of addr
944 * @pages_addr: optional DMA address to use for lookup
945 * @addr: the unmapped addr
947 * Look up the physical address of the page that the pte resolves
948 * to and return the pointer for the page table entry.
950 static uint64_t amdgpu_vm_map_gart(const dma_addr_t *pages_addr, uint64_t addr)
954 /* page table offset */
955 result = pages_addr[addr >> PAGE_SHIFT];
957 /* in case cpu page size != gpu page size*/
958 result |= addr & (~PAGE_MASK);
960 result &= 0xFFFFFFFFFFFFF000ULL;
966 * amdgpu_vm_cpu_set_ptes - helper to update page tables via CPU
968 * @params: see amdgpu_pte_update_params definition
969 * @pe: kmap addr of the page entry
970 * @addr: dst addr to write into pe
971 * @count: number of page entries to update
972 * @incr: increase next addr by incr bytes
973 * @flags: hw access flags
975 * Write count number of PT/PD entries directly.
977 static void amdgpu_vm_cpu_set_ptes(struct amdgpu_pte_update_params *params,
978 uint64_t pe, uint64_t addr,
979 unsigned count, uint32_t incr,
985 for (i = 0; i < count; i++) {
986 value = params->pages_addr ?
987 amdgpu_vm_map_gart(params->pages_addr, addr) :
989 amdgpu_gart_set_pte_pde(params->adev, (void *)(uintptr_t)pe,
996 amdgpu_gart_flush_gpu_tlb(params->adev, 0);
999 static int amdgpu_vm_wait_pd(struct amdgpu_device *adev, struct amdgpu_vm *vm,
1002 struct amdgpu_sync sync;
1005 amdgpu_sync_create(&sync);
1006 amdgpu_sync_resv(adev, &sync, vm->root.bo->tbo.resv, owner);
1007 r = amdgpu_sync_wait(&sync, true);
1008 amdgpu_sync_free(&sync);
1014 * amdgpu_vm_update_level - update a single level in the hierarchy
1016 * @adev: amdgpu_device pointer
1018 * @parent: parent directory
1020 * Makes sure all entries in @parent are up to date.
1021 * Returns 0 for success, error for failure.
1023 static int amdgpu_vm_update_level(struct amdgpu_device *adev,
1024 struct amdgpu_vm *vm,
1025 struct amdgpu_vm_pt *parent,
1028 struct amdgpu_bo *shadow;
1029 struct amdgpu_ring *ring = NULL;
1030 uint64_t pd_addr, shadow_addr = 0;
1031 uint32_t incr = amdgpu_vm_bo_size(adev, level + 1);
1032 uint64_t last_pde = ~0, last_pt = ~0, last_shadow = ~0;
1033 unsigned count = 0, pt_idx, ndw = 0;
1034 struct amdgpu_job *job;
1035 struct amdgpu_pte_update_params params;
1036 struct dma_fence *fence = NULL;
1040 if (!parent->entries)
1043 memset(¶ms, 0, sizeof(params));
1045 shadow = parent->bo->shadow;
1047 if (vm->use_cpu_for_update) {
1048 r = amdgpu_bo_kmap(parent->bo, (void **)&pd_addr);
1051 r = amdgpu_vm_wait_pd(adev, vm, AMDGPU_FENCE_OWNER_VM);
1053 amdgpu_bo_kunmap(parent->bo);
1056 params.func = amdgpu_vm_cpu_set_ptes;
1059 r = amdgpu_ttm_bind(&shadow->tbo, &shadow->tbo.mem);
1063 ring = container_of(vm->entity.sched, struct amdgpu_ring,
1069 /* assume the worst case */
1070 ndw += parent->last_entry_used * 6;
1072 pd_addr = amdgpu_bo_gpu_offset(parent->bo);
1075 shadow_addr = amdgpu_bo_gpu_offset(shadow);
1081 r = amdgpu_job_alloc_with_ib(adev, ndw * 4, &job);
1085 params.ib = &job->ibs[0];
1086 params.func = amdgpu_vm_do_set_ptes;
1090 /* walk over the address space and update the directory */
1091 for (pt_idx = 0; pt_idx <= parent->last_entry_used; ++pt_idx) {
1092 struct amdgpu_bo *bo = parent->entries[pt_idx].bo;
1099 struct amdgpu_bo *pt_shadow = bo->shadow;
1101 r = amdgpu_ttm_bind(&pt_shadow->tbo,
1102 &pt_shadow->tbo.mem);
1107 pt = amdgpu_bo_gpu_offset(bo);
1108 pt = amdgpu_gart_get_vm_pde(adev, pt);
1109 if (parent->entries[pt_idx].addr == pt)
1112 parent->entries[pt_idx].addr = pt;
1114 pde = pd_addr + pt_idx * 8;
1115 if (((last_pde + 8 * count) != pde) ||
1116 ((last_pt + incr * count) != pt) ||
1117 (count == AMDGPU_VM_MAX_UPDATE_SIZE)) {
1121 params.func(¶ms,
1127 params.func(¶ms, last_pde,
1128 last_pt, count, incr,
1134 last_shadow = shadow_addr + pt_idx * 8;
1142 if (vm->root.bo->shadow)
1143 params.func(¶ms, last_shadow, last_pt,
1144 count, incr, AMDGPU_PTE_VALID);
1146 params.func(¶ms, last_pde, last_pt,
1147 count, incr, AMDGPU_PTE_VALID);
1150 if (params.func == amdgpu_vm_cpu_set_ptes)
1151 amdgpu_bo_kunmap(parent->bo);
1152 else if (params.ib->length_dw == 0) {
1153 amdgpu_job_free(job);
1155 amdgpu_ring_pad_ib(ring, params.ib);
1156 amdgpu_sync_resv(adev, &job->sync, parent->bo->tbo.resv,
1157 AMDGPU_FENCE_OWNER_VM);
1159 amdgpu_sync_resv(adev, &job->sync, shadow->tbo.resv,
1160 AMDGPU_FENCE_OWNER_VM);
1162 WARN_ON(params.ib->length_dw > ndw);
1163 r = amdgpu_job_submit(job, ring, &vm->entity,
1164 AMDGPU_FENCE_OWNER_VM, &fence);
1168 amdgpu_bo_fence(parent->bo, fence, true);
1169 dma_fence_put(vm->last_dir_update);
1170 vm->last_dir_update = dma_fence_get(fence);
1171 dma_fence_put(fence);
1174 * Recurse into the subdirectories. This recursion is harmless because
1175 * we only have a maximum of 5 layers.
1177 for (pt_idx = 0; pt_idx <= parent->last_entry_used; ++pt_idx) {
1178 struct amdgpu_vm_pt *entry = &parent->entries[pt_idx];
1183 r = amdgpu_vm_update_level(adev, vm, entry, level + 1);
1191 amdgpu_job_free(job);
1196 * amdgpu_vm_invalidate_level - mark all PD levels as invalid
1198 * @parent: parent PD
1200 * Mark all PD level as invalid after an error.
1202 static void amdgpu_vm_invalidate_level(struct amdgpu_vm_pt *parent)
1207 * Recurse into the subdirectories. This recursion is harmless because
1208 * we only have a maximum of 5 layers.
1210 for (pt_idx = 0; pt_idx <= parent->last_entry_used; ++pt_idx) {
1211 struct amdgpu_vm_pt *entry = &parent->entries[pt_idx];
1216 entry->addr = ~0ULL;
1217 amdgpu_vm_invalidate_level(entry);
1222 * amdgpu_vm_update_directories - make sure that all directories are valid
1224 * @adev: amdgpu_device pointer
1227 * Makes sure all directories are up to date.
1228 * Returns 0 for success, error for failure.
1230 int amdgpu_vm_update_directories(struct amdgpu_device *adev,
1231 struct amdgpu_vm *vm)
1235 r = amdgpu_vm_update_level(adev, vm, &vm->root, 0);
1237 amdgpu_vm_invalidate_level(&vm->root);
1243 * amdgpu_vm_find_pt - find the page table for an address
1245 * @p: see amdgpu_pte_update_params definition
1246 * @addr: virtual address in question
1248 * Find the page table BO for a virtual address, return NULL when none found.
1250 static struct amdgpu_bo *amdgpu_vm_get_pt(struct amdgpu_pte_update_params *p,
1253 struct amdgpu_vm_pt *entry = &p->vm->root;
1254 unsigned idx, level = p->adev->vm_manager.num_level;
1256 while (entry->entries) {
1257 idx = addr >> (p->adev->vm_manager.block_size * level--);
1258 idx %= amdgpu_bo_size(entry->bo) / 8;
1259 entry = &entry->entries[idx];
1269 * amdgpu_vm_update_ptes - make sure that page tables are valid
1271 * @params: see amdgpu_pte_update_params definition
1273 * @start: start of GPU address range
1274 * @end: end of GPU address range
1275 * @dst: destination address to map to, the next dst inside the function
1276 * @flags: mapping flags
1278 * Update the page tables in the range @start - @end.
1279 * Returns 0 for success, -EINVAL for failure.
1281 static int amdgpu_vm_update_ptes(struct amdgpu_pte_update_params *params,
1282 uint64_t start, uint64_t end,
1283 uint64_t dst, uint64_t flags)
1285 struct amdgpu_device *adev = params->adev;
1286 const uint64_t mask = AMDGPU_VM_PTE_COUNT(adev) - 1;
1288 uint64_t addr, pe_start;
1289 struct amdgpu_bo *pt;
1292 bool use_cpu_update = (params->func == amdgpu_vm_cpu_set_ptes);
1295 /* walk over the address space and update the page tables */
1296 for (addr = start; addr < end; addr += nptes) {
1297 pt = amdgpu_vm_get_pt(params, addr);
1299 pr_err("PT not found, aborting update_ptes\n");
1303 if ((addr & ~mask) == (end & ~mask))
1306 nptes = AMDGPU_VM_PTE_COUNT(adev) - (addr & mask);
1308 if (use_cpu_update) {
1309 r = amdgpu_bo_kmap(pt, (void *)&pe_start);
1314 pe_start = amdgpu_bo_gpu_offset(pt->shadow);
1315 pe_start += (addr & mask) * 8;
1316 params->func(params, pe_start, dst, nptes,
1317 AMDGPU_GPU_PAGE_SIZE, flags);
1319 pe_start = amdgpu_bo_gpu_offset(pt);
1322 pe_start += (addr & mask) * 8;
1323 params->func(params, pe_start, dst, nptes,
1324 AMDGPU_GPU_PAGE_SIZE, flags);
1326 dst += nptes * AMDGPU_GPU_PAGE_SIZE;
1329 amdgpu_bo_kunmap(pt);
1336 * amdgpu_vm_frag_ptes - add fragment information to PTEs
1338 * @params: see amdgpu_pte_update_params definition
1340 * @start: first PTE to handle
1341 * @end: last PTE to handle
1342 * @dst: addr those PTEs should point to
1343 * @flags: hw mapping flags
1344 * Returns 0 for success, -EINVAL for failure.
1346 static int amdgpu_vm_frag_ptes(struct amdgpu_pte_update_params *params,
1347 uint64_t start, uint64_t end,
1348 uint64_t dst, uint64_t flags)
1353 * The MC L1 TLB supports variable sized pages, based on a fragment
1354 * field in the PTE. When this field is set to a non-zero value, page
1355 * granularity is increased from 4KB to (1 << (12 + frag)). The PTE
1356 * flags are considered valid for all PTEs within the fragment range
1357 * and corresponding mappings are assumed to be physically contiguous.
1359 * The L1 TLB can store a single PTE for the whole fragment,
1360 * significantly increasing the space available for translation
1361 * caching. This leads to large improvements in throughput when the
1362 * TLB is under pressure.
1364 * The L2 TLB distributes small and large fragments into two
1365 * asymmetric partitions. The large fragment cache is significantly
1366 * larger. Thus, we try to use large fragments wherever possible.
1367 * Userspace can support this by aligning virtual base address and
1368 * allocation size to the fragment size.
1371 /* SI and newer are optimized for 64KB */
1372 uint64_t frag_flags = AMDGPU_PTE_FRAG(AMDGPU_LOG2_PAGES_PER_FRAG);
1373 uint64_t frag_align = 1 << AMDGPU_LOG2_PAGES_PER_FRAG;
1375 uint64_t frag_start = ALIGN(start, frag_align);
1376 uint64_t frag_end = end & ~(frag_align - 1);
1378 /* system pages are non continuously */
1379 if (params->src || !(flags & AMDGPU_PTE_VALID) ||
1380 (frag_start >= frag_end))
1381 return amdgpu_vm_update_ptes(params, start, end, dst, flags);
1383 /* handle the 4K area at the beginning */
1384 if (start != frag_start) {
1385 r = amdgpu_vm_update_ptes(params, start, frag_start,
1389 dst += (frag_start - start) * AMDGPU_GPU_PAGE_SIZE;
1392 /* handle the area in the middle */
1393 r = amdgpu_vm_update_ptes(params, frag_start, frag_end, dst,
1394 flags | frag_flags);
1398 /* handle the 4K area at the end */
1399 if (frag_end != end) {
1400 dst += (frag_end - frag_start) * AMDGPU_GPU_PAGE_SIZE;
1401 r = amdgpu_vm_update_ptes(params, frag_end, end, dst, flags);
1407 * amdgpu_vm_bo_update_mapping - update a mapping in the vm page table
1409 * @adev: amdgpu_device pointer
1410 * @exclusive: fence we need to sync to
1411 * @src: address where to copy page table entries from
1412 * @pages_addr: DMA addresses to use for mapping
1414 * @start: start of mapped range
1415 * @last: last mapped entry
1416 * @flags: flags for the entries
1417 * @addr: addr to set the area to
1418 * @fence: optional resulting fence
1420 * Fill in the page table entries between @start and @last.
1421 * Returns 0 for success, -EINVAL for failure.
1423 static int amdgpu_vm_bo_update_mapping(struct amdgpu_device *adev,
1424 struct dma_fence *exclusive,
1426 dma_addr_t *pages_addr,
1427 struct amdgpu_vm *vm,
1428 uint64_t start, uint64_t last,
1429 uint64_t flags, uint64_t addr,
1430 struct dma_fence **fence)
1432 struct amdgpu_ring *ring;
1433 void *owner = AMDGPU_FENCE_OWNER_VM;
1434 unsigned nptes, ncmds, ndw;
1435 struct amdgpu_job *job;
1436 struct amdgpu_pte_update_params params;
1437 struct dma_fence *f = NULL;
1440 memset(¶ms, 0, sizeof(params));
1445 /* sync to everything on unmapping */
1446 if (!(flags & AMDGPU_PTE_VALID))
1447 owner = AMDGPU_FENCE_OWNER_UNDEFINED;
1449 if (vm->use_cpu_for_update) {
1450 /* params.src is used as flag to indicate system Memory */
1454 /* Wait for PT BOs to be free. PTs share the same resv. object
1457 r = amdgpu_vm_wait_pd(adev, vm, owner);
1461 params.func = amdgpu_vm_cpu_set_ptes;
1462 params.pages_addr = pages_addr;
1463 return amdgpu_vm_frag_ptes(¶ms, start, last + 1,
1467 ring = container_of(vm->entity.sched, struct amdgpu_ring, sched);
1469 nptes = last - start + 1;
1472 * reserve space for one command every (1 << BLOCK_SIZE)
1473 * entries or 2k dwords (whatever is smaller)
1475 ncmds = (nptes >> min(adev->vm_manager.block_size, 11u)) + 1;
1481 /* only copy commands needed */
1484 params.func = amdgpu_vm_do_copy_ptes;
1486 } else if (pages_addr) {
1487 /* copy commands needed */
1493 params.func = amdgpu_vm_do_copy_ptes;
1496 /* set page commands needed */
1499 /* two extra commands for begin/end of fragment */
1502 params.func = amdgpu_vm_do_set_ptes;
1505 r = amdgpu_job_alloc_with_ib(adev, ndw * 4, &job);
1509 params.ib = &job->ibs[0];
1511 if (!src && pages_addr) {
1515 /* Put the PTEs at the end of the IB. */
1516 i = ndw - nptes * 2;
1517 pte= (uint64_t *)&(job->ibs->ptr[i]);
1518 params.src = job->ibs->gpu_addr + i * 4;
1520 for (i = 0; i < nptes; ++i) {
1521 pte[i] = amdgpu_vm_map_gart(pages_addr, addr + i *
1522 AMDGPU_GPU_PAGE_SIZE);
1528 r = amdgpu_sync_fence(adev, &job->sync, exclusive);
1532 r = amdgpu_sync_resv(adev, &job->sync, vm->root.bo->tbo.resv,
1537 r = reservation_object_reserve_shared(vm->root.bo->tbo.resv);
1541 r = amdgpu_vm_frag_ptes(¶ms, start, last + 1, addr, flags);
1545 amdgpu_ring_pad_ib(ring, params.ib);
1546 WARN_ON(params.ib->length_dw > ndw);
1547 r = amdgpu_job_submit(job, ring, &vm->entity,
1548 AMDGPU_FENCE_OWNER_VM, &f);
1552 amdgpu_bo_fence(vm->root.bo, f, true);
1553 dma_fence_put(*fence);
1558 amdgpu_job_free(job);
1563 * amdgpu_vm_bo_split_mapping - split a mapping into smaller chunks
1565 * @adev: amdgpu_device pointer
1566 * @exclusive: fence we need to sync to
1567 * @gtt_flags: flags as they are used for GTT
1568 * @pages_addr: DMA addresses to use for mapping
1570 * @mapping: mapped range and flags to use for the update
1571 * @flags: HW flags for the mapping
1572 * @nodes: array of drm_mm_nodes with the MC addresses
1573 * @fence: optional resulting fence
1575 * Split the mapping into smaller chunks so that each update fits
1577 * Returns 0 for success, -EINVAL for failure.
1579 static int amdgpu_vm_bo_split_mapping(struct amdgpu_device *adev,
1580 struct dma_fence *exclusive,
1582 dma_addr_t *pages_addr,
1583 struct amdgpu_vm *vm,
1584 struct amdgpu_bo_va_mapping *mapping,
1586 struct drm_mm_node *nodes,
1587 struct dma_fence **fence)
1589 uint64_t pfn, src = 0, start = mapping->start;
1592 /* normally,bo_va->flags only contians READABLE and WIRTEABLE bit go here
1593 * but in case of something, we filter the flags in first place
1595 if (!(mapping->flags & AMDGPU_PTE_READABLE))
1596 flags &= ~AMDGPU_PTE_READABLE;
1597 if (!(mapping->flags & AMDGPU_PTE_WRITEABLE))
1598 flags &= ~AMDGPU_PTE_WRITEABLE;
1600 flags &= ~AMDGPU_PTE_EXECUTABLE;
1601 flags |= mapping->flags & AMDGPU_PTE_EXECUTABLE;
1603 flags &= ~AMDGPU_PTE_MTYPE_MASK;
1604 flags |= (mapping->flags & AMDGPU_PTE_MTYPE_MASK);
1606 if ((mapping->flags & AMDGPU_PTE_PRT) &&
1607 (adev->asic_type >= CHIP_VEGA10)) {
1608 flags |= AMDGPU_PTE_PRT;
1609 flags &= ~AMDGPU_PTE_VALID;
1612 trace_amdgpu_vm_bo_update(mapping);
1614 pfn = mapping->offset >> PAGE_SHIFT;
1616 while (pfn >= nodes->size) {
1623 uint64_t max_entries;
1624 uint64_t addr, last;
1627 addr = nodes->start << PAGE_SHIFT;
1628 max_entries = (nodes->size - pfn) *
1629 (PAGE_SIZE / AMDGPU_GPU_PAGE_SIZE);
1632 max_entries = S64_MAX;
1636 if (flags == gtt_flags)
1637 src = adev->gart.table_addr +
1638 (addr >> AMDGPU_GPU_PAGE_SHIFT) * 8;
1640 max_entries = min(max_entries, 16ull * 1024ull);
1642 } else if (flags & AMDGPU_PTE_VALID) {
1643 addr += adev->vm_manager.vram_base_offset;
1645 addr += pfn << PAGE_SHIFT;
1647 last = min((uint64_t)mapping->last, start + max_entries - 1);
1648 r = amdgpu_vm_bo_update_mapping(adev, exclusive,
1649 src, pages_addr, vm,
1650 start, last, flags, addr,
1655 pfn += last - start + 1;
1656 if (nodes && nodes->size == pfn) {
1662 } while (unlikely(start != mapping->last + 1));
1668 * amdgpu_vm_bo_update - update all BO mappings in the vm page table
1670 * @adev: amdgpu_device pointer
1671 * @bo_va: requested BO and VM object
1672 * @clear: if true clear the entries
1674 * Fill in the page table entries for @bo_va.
1675 * Returns 0 for success, -EINVAL for failure.
1677 int amdgpu_vm_bo_update(struct amdgpu_device *adev,
1678 struct amdgpu_bo_va *bo_va,
1681 struct amdgpu_vm *vm = bo_va->vm;
1682 struct amdgpu_bo_va_mapping *mapping;
1683 dma_addr_t *pages_addr = NULL;
1684 uint64_t gtt_flags, flags;
1685 struct ttm_mem_reg *mem;
1686 struct drm_mm_node *nodes;
1687 struct dma_fence *exclusive;
1690 if (clear || !bo_va->bo) {
1695 struct ttm_dma_tt *ttm;
1697 mem = &bo_va->bo->tbo.mem;
1698 nodes = mem->mm_node;
1699 if (mem->mem_type == TTM_PL_TT) {
1700 ttm = container_of(bo_va->bo->tbo.ttm, struct
1702 pages_addr = ttm->dma_address;
1704 exclusive = reservation_object_get_excl(bo_va->bo->tbo.resv);
1708 flags = amdgpu_ttm_tt_pte_flags(adev, bo_va->bo->tbo.ttm, mem);
1709 gtt_flags = (amdgpu_ttm_is_bound(bo_va->bo->tbo.ttm) &&
1710 adev == amdgpu_ttm_adev(bo_va->bo->tbo.bdev)) ?
1717 spin_lock(&vm->status_lock);
1718 if (!list_empty(&bo_va->vm_status))
1719 list_splice_init(&bo_va->valids, &bo_va->invalids);
1720 spin_unlock(&vm->status_lock);
1722 list_for_each_entry(mapping, &bo_va->invalids, list) {
1723 r = amdgpu_vm_bo_split_mapping(adev, exclusive,
1724 gtt_flags, pages_addr, vm,
1725 mapping, flags, nodes,
1726 &bo_va->last_pt_update);
1731 if (trace_amdgpu_vm_bo_mapping_enabled()) {
1732 list_for_each_entry(mapping, &bo_va->valids, list)
1733 trace_amdgpu_vm_bo_mapping(mapping);
1735 list_for_each_entry(mapping, &bo_va->invalids, list)
1736 trace_amdgpu_vm_bo_mapping(mapping);
1739 spin_lock(&vm->status_lock);
1740 list_splice_init(&bo_va->invalids, &bo_va->valids);
1741 list_del_init(&bo_va->vm_status);
1743 list_add(&bo_va->vm_status, &vm->cleared);
1744 spin_unlock(&vm->status_lock);
1750 * amdgpu_vm_update_prt_state - update the global PRT state
1752 static void amdgpu_vm_update_prt_state(struct amdgpu_device *adev)
1754 unsigned long flags;
1757 spin_lock_irqsave(&adev->vm_manager.prt_lock, flags);
1758 enable = !!atomic_read(&adev->vm_manager.num_prt_users);
1759 adev->gart.gart_funcs->set_prt(adev, enable);
1760 spin_unlock_irqrestore(&adev->vm_manager.prt_lock, flags);
1764 * amdgpu_vm_prt_get - add a PRT user
1766 static void amdgpu_vm_prt_get(struct amdgpu_device *adev)
1768 if (!adev->gart.gart_funcs->set_prt)
1771 if (atomic_inc_return(&adev->vm_manager.num_prt_users) == 1)
1772 amdgpu_vm_update_prt_state(adev);
1776 * amdgpu_vm_prt_put - drop a PRT user
1778 static void amdgpu_vm_prt_put(struct amdgpu_device *adev)
1780 if (atomic_dec_return(&adev->vm_manager.num_prt_users) == 0)
1781 amdgpu_vm_update_prt_state(adev);
1785 * amdgpu_vm_prt_cb - callback for updating the PRT status
1787 static void amdgpu_vm_prt_cb(struct dma_fence *fence, struct dma_fence_cb *_cb)
1789 struct amdgpu_prt_cb *cb = container_of(_cb, struct amdgpu_prt_cb, cb);
1791 amdgpu_vm_prt_put(cb->adev);
1796 * amdgpu_vm_add_prt_cb - add callback for updating the PRT status
1798 static void amdgpu_vm_add_prt_cb(struct amdgpu_device *adev,
1799 struct dma_fence *fence)
1801 struct amdgpu_prt_cb *cb;
1803 if (!adev->gart.gart_funcs->set_prt)
1806 cb = kmalloc(sizeof(struct amdgpu_prt_cb), GFP_KERNEL);
1808 /* Last resort when we are OOM */
1810 dma_fence_wait(fence, false);
1812 amdgpu_vm_prt_put(adev);
1815 if (!fence || dma_fence_add_callback(fence, &cb->cb,
1817 amdgpu_vm_prt_cb(fence, &cb->cb);
1822 * amdgpu_vm_free_mapping - free a mapping
1824 * @adev: amdgpu_device pointer
1826 * @mapping: mapping to be freed
1827 * @fence: fence of the unmap operation
1829 * Free a mapping and make sure we decrease the PRT usage count if applicable.
1831 static void amdgpu_vm_free_mapping(struct amdgpu_device *adev,
1832 struct amdgpu_vm *vm,
1833 struct amdgpu_bo_va_mapping *mapping,
1834 struct dma_fence *fence)
1836 if (mapping->flags & AMDGPU_PTE_PRT)
1837 amdgpu_vm_add_prt_cb(adev, fence);
1842 * amdgpu_vm_prt_fini - finish all prt mappings
1844 * @adev: amdgpu_device pointer
1847 * Register a cleanup callback to disable PRT support after VM dies.
1849 static void amdgpu_vm_prt_fini(struct amdgpu_device *adev, struct amdgpu_vm *vm)
1851 struct reservation_object *resv = vm->root.bo->tbo.resv;
1852 struct dma_fence *excl, **shared;
1853 unsigned i, shared_count;
1856 r = reservation_object_get_fences_rcu(resv, &excl,
1857 &shared_count, &shared);
1859 /* Not enough memory to grab the fence list, as last resort
1860 * block for all the fences to complete.
1862 reservation_object_wait_timeout_rcu(resv, true, false,
1863 MAX_SCHEDULE_TIMEOUT);
1867 /* Add a callback for each fence in the reservation object */
1868 amdgpu_vm_prt_get(adev);
1869 amdgpu_vm_add_prt_cb(adev, excl);
1871 for (i = 0; i < shared_count; ++i) {
1872 amdgpu_vm_prt_get(adev);
1873 amdgpu_vm_add_prt_cb(adev, shared[i]);
1880 * amdgpu_vm_clear_freed - clear freed BOs in the PT
1882 * @adev: amdgpu_device pointer
1884 * @fence: optional resulting fence (unchanged if no work needed to be done
1885 * or if an error occurred)
1887 * Make sure all freed BOs are cleared in the PT.
1888 * Returns 0 for success.
1890 * PTs have to be reserved and mutex must be locked!
1892 int amdgpu_vm_clear_freed(struct amdgpu_device *adev,
1893 struct amdgpu_vm *vm,
1894 struct dma_fence **fence)
1896 struct amdgpu_bo_va_mapping *mapping;
1897 struct dma_fence *f = NULL;
1900 while (!list_empty(&vm->freed)) {
1901 mapping = list_first_entry(&vm->freed,
1902 struct amdgpu_bo_va_mapping, list);
1903 list_del(&mapping->list);
1905 r = amdgpu_vm_bo_update_mapping(adev, NULL, 0, NULL, vm,
1906 mapping->start, mapping->last,
1908 amdgpu_vm_free_mapping(adev, vm, mapping, f);
1916 dma_fence_put(*fence);
1927 * amdgpu_vm_clear_invalids - clear invalidated BOs in the PT
1929 * @adev: amdgpu_device pointer
1932 * Make sure all invalidated BOs are cleared in the PT.
1933 * Returns 0 for success.
1935 * PTs have to be reserved and mutex must be locked!
1937 int amdgpu_vm_clear_invalids(struct amdgpu_device *adev,
1938 struct amdgpu_vm *vm, struct amdgpu_sync *sync)
1940 struct amdgpu_bo_va *bo_va = NULL;
1943 spin_lock(&vm->status_lock);
1944 while (!list_empty(&vm->invalidated)) {
1945 bo_va = list_first_entry(&vm->invalidated,
1946 struct amdgpu_bo_va, vm_status);
1947 spin_unlock(&vm->status_lock);
1949 r = amdgpu_vm_bo_update(adev, bo_va, true);
1953 spin_lock(&vm->status_lock);
1955 spin_unlock(&vm->status_lock);
1958 r = amdgpu_sync_fence(adev, sync, bo_va->last_pt_update);
1964 * amdgpu_vm_bo_add - add a bo to a specific vm
1966 * @adev: amdgpu_device pointer
1968 * @bo: amdgpu buffer object
1970 * Add @bo into the requested vm.
1971 * Add @bo to the list of bos associated with the vm
1972 * Returns newly added bo_va or NULL for failure
1974 * Object has to be reserved!
1976 struct amdgpu_bo_va *amdgpu_vm_bo_add(struct amdgpu_device *adev,
1977 struct amdgpu_vm *vm,
1978 struct amdgpu_bo *bo)
1980 struct amdgpu_bo_va *bo_va;
1982 bo_va = kzalloc(sizeof(struct amdgpu_bo_va), GFP_KERNEL);
1983 if (bo_va == NULL) {
1988 bo_va->ref_count = 1;
1989 INIT_LIST_HEAD(&bo_va->bo_list);
1990 INIT_LIST_HEAD(&bo_va->valids);
1991 INIT_LIST_HEAD(&bo_va->invalids);
1992 INIT_LIST_HEAD(&bo_va->vm_status);
1995 list_add_tail(&bo_va->bo_list, &bo->va);
2001 * amdgpu_vm_bo_map - map bo inside a vm
2003 * @adev: amdgpu_device pointer
2004 * @bo_va: bo_va to store the address
2005 * @saddr: where to map the BO
2006 * @offset: requested offset in the BO
2007 * @flags: attributes of pages (read/write/valid/etc.)
2009 * Add a mapping of the BO at the specefied addr into the VM.
2010 * Returns 0 for success, error for failure.
2012 * Object has to be reserved and unreserved outside!
2014 int amdgpu_vm_bo_map(struct amdgpu_device *adev,
2015 struct amdgpu_bo_va *bo_va,
2016 uint64_t saddr, uint64_t offset,
2017 uint64_t size, uint64_t flags)
2019 struct amdgpu_bo_va_mapping *mapping, *tmp;
2020 struct amdgpu_vm *vm = bo_va->vm;
2023 /* validate the parameters */
2024 if (saddr & AMDGPU_GPU_PAGE_MASK || offset & AMDGPU_GPU_PAGE_MASK ||
2025 size == 0 || size & AMDGPU_GPU_PAGE_MASK)
2028 /* make sure object fit at this offset */
2029 eaddr = saddr + size - 1;
2030 if (saddr >= eaddr ||
2031 (bo_va->bo && offset + size > amdgpu_bo_size(bo_va->bo)))
2034 saddr /= AMDGPU_GPU_PAGE_SIZE;
2035 eaddr /= AMDGPU_GPU_PAGE_SIZE;
2037 tmp = amdgpu_vm_it_iter_first(&vm->va, saddr, eaddr);
2039 /* bo and tmp overlap, invalid addr */
2040 dev_err(adev->dev, "bo %p va 0x%010Lx-0x%010Lx conflict with "
2041 "0x%010Lx-0x%010Lx\n", bo_va->bo, saddr, eaddr,
2042 tmp->start, tmp->last + 1);
2046 mapping = kmalloc(sizeof(*mapping), GFP_KERNEL);
2050 INIT_LIST_HEAD(&mapping->list);
2051 mapping->start = saddr;
2052 mapping->last = eaddr;
2053 mapping->offset = offset;
2054 mapping->flags = flags;
2056 list_add(&mapping->list, &bo_va->invalids);
2057 amdgpu_vm_it_insert(mapping, &vm->va);
2059 if (flags & AMDGPU_PTE_PRT)
2060 amdgpu_vm_prt_get(adev);
2066 * amdgpu_vm_bo_replace_map - map bo inside a vm, replacing existing mappings
2068 * @adev: amdgpu_device pointer
2069 * @bo_va: bo_va to store the address
2070 * @saddr: where to map the BO
2071 * @offset: requested offset in the BO
2072 * @flags: attributes of pages (read/write/valid/etc.)
2074 * Add a mapping of the BO at the specefied addr into the VM. Replace existing
2075 * mappings as we do so.
2076 * Returns 0 for success, error for failure.
2078 * Object has to be reserved and unreserved outside!
2080 int amdgpu_vm_bo_replace_map(struct amdgpu_device *adev,
2081 struct amdgpu_bo_va *bo_va,
2082 uint64_t saddr, uint64_t offset,
2083 uint64_t size, uint64_t flags)
2085 struct amdgpu_bo_va_mapping *mapping;
2086 struct amdgpu_vm *vm = bo_va->vm;
2090 /* validate the parameters */
2091 if (saddr & AMDGPU_GPU_PAGE_MASK || offset & AMDGPU_GPU_PAGE_MASK ||
2092 size == 0 || size & AMDGPU_GPU_PAGE_MASK)
2095 /* make sure object fit at this offset */
2096 eaddr = saddr + size - 1;
2097 if (saddr >= eaddr ||
2098 (bo_va->bo && offset + size > amdgpu_bo_size(bo_va->bo)))
2101 /* Allocate all the needed memory */
2102 mapping = kmalloc(sizeof(*mapping), GFP_KERNEL);
2106 r = amdgpu_vm_bo_clear_mappings(adev, bo_va->vm, saddr, size);
2112 saddr /= AMDGPU_GPU_PAGE_SIZE;
2113 eaddr /= AMDGPU_GPU_PAGE_SIZE;
2115 mapping->start = saddr;
2116 mapping->last = eaddr;
2117 mapping->offset = offset;
2118 mapping->flags = flags;
2120 list_add(&mapping->list, &bo_va->invalids);
2121 amdgpu_vm_it_insert(mapping, &vm->va);
2123 if (flags & AMDGPU_PTE_PRT)
2124 amdgpu_vm_prt_get(adev);
2130 * amdgpu_vm_bo_unmap - remove bo mapping from vm
2132 * @adev: amdgpu_device pointer
2133 * @bo_va: bo_va to remove the address from
2134 * @saddr: where to the BO is mapped
2136 * Remove a mapping of the BO at the specefied addr from the VM.
2137 * Returns 0 for success, error for failure.
2139 * Object has to be reserved and unreserved outside!
2141 int amdgpu_vm_bo_unmap(struct amdgpu_device *adev,
2142 struct amdgpu_bo_va *bo_va,
2145 struct amdgpu_bo_va_mapping *mapping;
2146 struct amdgpu_vm *vm = bo_va->vm;
2149 saddr /= AMDGPU_GPU_PAGE_SIZE;
2151 list_for_each_entry(mapping, &bo_va->valids, list) {
2152 if (mapping->start == saddr)
2156 if (&mapping->list == &bo_va->valids) {
2159 list_for_each_entry(mapping, &bo_va->invalids, list) {
2160 if (mapping->start == saddr)
2164 if (&mapping->list == &bo_va->invalids)
2168 list_del(&mapping->list);
2169 amdgpu_vm_it_remove(mapping, &vm->va);
2170 trace_amdgpu_vm_bo_unmap(bo_va, mapping);
2173 list_add(&mapping->list, &vm->freed);
2175 amdgpu_vm_free_mapping(adev, vm, mapping,
2176 bo_va->last_pt_update);
2182 * amdgpu_vm_bo_clear_mappings - remove all mappings in a specific range
2184 * @adev: amdgpu_device pointer
2185 * @vm: VM structure to use
2186 * @saddr: start of the range
2187 * @size: size of the range
2189 * Remove all mappings in a range, split them as appropriate.
2190 * Returns 0 for success, error for failure.
2192 int amdgpu_vm_bo_clear_mappings(struct amdgpu_device *adev,
2193 struct amdgpu_vm *vm,
2194 uint64_t saddr, uint64_t size)
2196 struct amdgpu_bo_va_mapping *before, *after, *tmp, *next;
2200 eaddr = saddr + size - 1;
2201 saddr /= AMDGPU_GPU_PAGE_SIZE;
2202 eaddr /= AMDGPU_GPU_PAGE_SIZE;
2204 /* Allocate all the needed memory */
2205 before = kzalloc(sizeof(*before), GFP_KERNEL);
2208 INIT_LIST_HEAD(&before->list);
2210 after = kzalloc(sizeof(*after), GFP_KERNEL);
2215 INIT_LIST_HEAD(&after->list);
2217 /* Now gather all removed mappings */
2218 tmp = amdgpu_vm_it_iter_first(&vm->va, saddr, eaddr);
2220 /* Remember mapping split at the start */
2221 if (tmp->start < saddr) {
2222 before->start = tmp->start;
2223 before->last = saddr - 1;
2224 before->offset = tmp->offset;
2225 before->flags = tmp->flags;
2226 list_add(&before->list, &tmp->list);
2229 /* Remember mapping split at the end */
2230 if (tmp->last > eaddr) {
2231 after->start = eaddr + 1;
2232 after->last = tmp->last;
2233 after->offset = tmp->offset;
2234 after->offset += after->start - tmp->start;
2235 after->flags = tmp->flags;
2236 list_add(&after->list, &tmp->list);
2239 list_del(&tmp->list);
2240 list_add(&tmp->list, &removed);
2242 tmp = amdgpu_vm_it_iter_next(tmp, saddr, eaddr);
2245 /* And free them up */
2246 list_for_each_entry_safe(tmp, next, &removed, list) {
2247 amdgpu_vm_it_remove(tmp, &vm->va);
2248 list_del(&tmp->list);
2250 if (tmp->start < saddr)
2252 if (tmp->last > eaddr)
2255 list_add(&tmp->list, &vm->freed);
2256 trace_amdgpu_vm_bo_unmap(NULL, tmp);
2259 /* Insert partial mapping before the range */
2260 if (!list_empty(&before->list)) {
2261 amdgpu_vm_it_insert(before, &vm->va);
2262 if (before->flags & AMDGPU_PTE_PRT)
2263 amdgpu_vm_prt_get(adev);
2268 /* Insert partial mapping after the range */
2269 if (!list_empty(&after->list)) {
2270 amdgpu_vm_it_insert(after, &vm->va);
2271 if (after->flags & AMDGPU_PTE_PRT)
2272 amdgpu_vm_prt_get(adev);
2281 * amdgpu_vm_bo_rmv - remove a bo to a specific vm
2283 * @adev: amdgpu_device pointer
2284 * @bo_va: requested bo_va
2286 * Remove @bo_va->bo from the requested vm.
2288 * Object have to be reserved!
2290 void amdgpu_vm_bo_rmv(struct amdgpu_device *adev,
2291 struct amdgpu_bo_va *bo_va)
2293 struct amdgpu_bo_va_mapping *mapping, *next;
2294 struct amdgpu_vm *vm = bo_va->vm;
2296 list_del(&bo_va->bo_list);
2298 spin_lock(&vm->status_lock);
2299 list_del(&bo_va->vm_status);
2300 spin_unlock(&vm->status_lock);
2302 list_for_each_entry_safe(mapping, next, &bo_va->valids, list) {
2303 list_del(&mapping->list);
2304 amdgpu_vm_it_remove(mapping, &vm->va);
2305 trace_amdgpu_vm_bo_unmap(bo_va, mapping);
2306 list_add(&mapping->list, &vm->freed);
2308 list_for_each_entry_safe(mapping, next, &bo_va->invalids, list) {
2309 list_del(&mapping->list);
2310 amdgpu_vm_it_remove(mapping, &vm->va);
2311 amdgpu_vm_free_mapping(adev, vm, mapping,
2312 bo_va->last_pt_update);
2315 dma_fence_put(bo_va->last_pt_update);
2320 * amdgpu_vm_bo_invalidate - mark the bo as invalid
2322 * @adev: amdgpu_device pointer
2324 * @bo: amdgpu buffer object
2326 * Mark @bo as invalid.
2328 void amdgpu_vm_bo_invalidate(struct amdgpu_device *adev,
2329 struct amdgpu_bo *bo)
2331 struct amdgpu_bo_va *bo_va;
2333 list_for_each_entry(bo_va, &bo->va, bo_list) {
2334 spin_lock(&bo_va->vm->status_lock);
2335 if (list_empty(&bo_va->vm_status))
2336 list_add(&bo_va->vm_status, &bo_va->vm->invalidated);
2337 spin_unlock(&bo_va->vm->status_lock);
2341 static uint32_t amdgpu_vm_get_block_size(uint64_t vm_size)
2343 /* Total bits covered by PD + PTs */
2344 unsigned bits = ilog2(vm_size) + 18;
2346 /* Make sure the PD is 4K in size up to 8GB address space.
2347 Above that split equal between PD and PTs */
2351 return ((bits + 3) / 2);
2355 * amdgpu_vm_adjust_size - adjust vm size and block size
2357 * @adev: amdgpu_device pointer
2358 * @vm_size: the default vm size if it's set auto
2360 void amdgpu_vm_adjust_size(struct amdgpu_device *adev, uint64_t vm_size)
2362 /* adjust vm size firstly */
2363 if (amdgpu_vm_size == -1)
2364 adev->vm_manager.vm_size = vm_size;
2366 adev->vm_manager.vm_size = amdgpu_vm_size;
2368 /* block size depends on vm size */
2369 if (amdgpu_vm_block_size == -1)
2370 adev->vm_manager.block_size =
2371 amdgpu_vm_get_block_size(adev->vm_manager.vm_size);
2373 adev->vm_manager.block_size = amdgpu_vm_block_size;
2375 DRM_INFO("vm size is %llu GB, block size is %u-bit\n",
2376 adev->vm_manager.vm_size, adev->vm_manager.block_size);
2380 * amdgpu_vm_init - initialize a vm instance
2382 * @adev: amdgpu_device pointer
2384 * @vm_context: Indicates if it GFX or Compute context
2388 int amdgpu_vm_init(struct amdgpu_device *adev, struct amdgpu_vm *vm,
2391 const unsigned align = min(AMDGPU_VM_PTB_ALIGN_SIZE,
2392 AMDGPU_VM_PTE_COUNT(adev) * 8);
2393 unsigned ring_instance;
2394 struct amdgpu_ring *ring;
2395 struct amd_sched_rq *rq;
2400 vm->client_id = atomic64_inc_return(&adev->vm_manager.client_counter);
2401 for (i = 0; i < AMDGPU_MAX_VMHUBS; i++)
2402 vm->reserved_vmid[i] = NULL;
2403 spin_lock_init(&vm->status_lock);
2404 INIT_LIST_HEAD(&vm->invalidated);
2405 INIT_LIST_HEAD(&vm->cleared);
2406 INIT_LIST_HEAD(&vm->freed);
2408 /* create scheduler entity for page table updates */
2410 ring_instance = atomic_inc_return(&adev->vm_manager.vm_pte_next_ring);
2411 ring_instance %= adev->vm_manager.vm_pte_num_rings;
2412 ring = adev->vm_manager.vm_pte_rings[ring_instance];
2413 rq = &ring->sched.sched_rq[AMD_SCHED_PRIORITY_KERNEL];
2414 r = amd_sched_entity_init(&ring->sched, &vm->entity,
2415 rq, amdgpu_sched_jobs);
2419 if (vm_context == AMDGPU_VM_CONTEXT_COMPUTE)
2420 vm->use_cpu_for_update = !!(adev->vm_manager.vm_update_mode &
2421 AMDGPU_VM_USE_CPU_FOR_COMPUTE);
2423 vm->use_cpu_for_update = !!(adev->vm_manager.vm_update_mode &
2424 AMDGPU_VM_USE_CPU_FOR_GFX);
2425 DRM_DEBUG_DRIVER("VM update mode is %s\n",
2426 vm->use_cpu_for_update ? "CPU" : "SDMA");
2427 WARN_ONCE((vm->use_cpu_for_update & !amdgpu_vm_is_large_bar(adev)),
2428 "CPU update of VM recommended only for large BAR system\n");
2429 vm->last_dir_update = NULL;
2431 flags = AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS |
2432 AMDGPU_GEM_CREATE_VRAM_CLEARED;
2433 if (vm->use_cpu_for_update)
2434 flags |= AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED;
2436 flags |= (AMDGPU_GEM_CREATE_NO_CPU_ACCESS |
2437 AMDGPU_GEM_CREATE_SHADOW);
2439 r = amdgpu_bo_create(adev, amdgpu_vm_bo_size(adev, 0), align, true,
2440 AMDGPU_GEM_DOMAIN_VRAM,
2442 NULL, NULL, &vm->root.bo);
2444 goto error_free_sched_entity;
2446 r = amdgpu_bo_reserve(vm->root.bo, false);
2448 goto error_free_root;
2450 vm->last_eviction_counter = atomic64_read(&adev->num_evictions);
2451 amdgpu_bo_unreserve(vm->root.bo);
2456 amdgpu_bo_unref(&vm->root.bo->shadow);
2457 amdgpu_bo_unref(&vm->root.bo);
2460 error_free_sched_entity:
2461 amd_sched_entity_fini(&ring->sched, &vm->entity);
2467 * amdgpu_vm_free_levels - free PD/PT levels
2469 * @level: PD/PT starting level to free
2471 * Free the page directory or page table level and all sub levels.
2473 static void amdgpu_vm_free_levels(struct amdgpu_vm_pt *level)
2478 amdgpu_bo_unref(&level->bo->shadow);
2479 amdgpu_bo_unref(&level->bo);
2483 for (i = 0; i <= level->last_entry_used; i++)
2484 amdgpu_vm_free_levels(&level->entries[i]);
2486 kvfree(level->entries);
2490 * amdgpu_vm_fini - tear down a vm instance
2492 * @adev: amdgpu_device pointer
2496 * Unbind the VM and remove all bos from the vm bo list
2498 void amdgpu_vm_fini(struct amdgpu_device *adev, struct amdgpu_vm *vm)
2500 struct amdgpu_bo_va_mapping *mapping, *tmp;
2501 bool prt_fini_needed = !!adev->gart.gart_funcs->set_prt;
2504 amd_sched_entity_fini(vm->entity.sched, &vm->entity);
2506 if (!RB_EMPTY_ROOT(&vm->va)) {
2507 dev_err(adev->dev, "still active bo inside vm\n");
2509 rbtree_postorder_for_each_entry_safe(mapping, tmp, &vm->va, rb) {
2510 list_del(&mapping->list);
2511 amdgpu_vm_it_remove(mapping, &vm->va);
2514 list_for_each_entry_safe(mapping, tmp, &vm->freed, list) {
2515 if (mapping->flags & AMDGPU_PTE_PRT && prt_fini_needed) {
2516 amdgpu_vm_prt_fini(adev, vm);
2517 prt_fini_needed = false;
2520 list_del(&mapping->list);
2521 amdgpu_vm_free_mapping(adev, vm, mapping, NULL);
2524 amdgpu_vm_free_levels(&vm->root);
2525 dma_fence_put(vm->last_dir_update);
2526 for (i = 0; i < AMDGPU_MAX_VMHUBS; i++)
2527 amdgpu_vm_free_reserved_vmid(adev, vm, i);
2531 * amdgpu_vm_manager_init - init the VM manager
2533 * @adev: amdgpu_device pointer
2535 * Initialize the VM manager structures
2537 void amdgpu_vm_manager_init(struct amdgpu_device *adev)
2541 for (i = 0; i < AMDGPU_MAX_VMHUBS; ++i) {
2542 struct amdgpu_vm_id_manager *id_mgr =
2543 &adev->vm_manager.id_mgr[i];
2545 mutex_init(&id_mgr->lock);
2546 INIT_LIST_HEAD(&id_mgr->ids_lru);
2547 atomic_set(&id_mgr->reserved_vmid_num, 0);
2549 /* skip over VMID 0, since it is the system VM */
2550 for (j = 1; j < id_mgr->num_ids; ++j) {
2551 amdgpu_vm_reset_id(adev, i, j);
2552 amdgpu_sync_create(&id_mgr->ids[i].active);
2553 list_add_tail(&id_mgr->ids[j].list, &id_mgr->ids_lru);
2557 adev->vm_manager.fence_context =
2558 dma_fence_context_alloc(AMDGPU_MAX_RINGS);
2559 for (i = 0; i < AMDGPU_MAX_RINGS; ++i)
2560 adev->vm_manager.seqno[i] = 0;
2562 atomic_set(&adev->vm_manager.vm_pte_next_ring, 0);
2563 atomic64_set(&adev->vm_manager.client_counter, 0);
2564 spin_lock_init(&adev->vm_manager.prt_lock);
2565 atomic_set(&adev->vm_manager.num_prt_users, 0);
2567 /* If not overridden by the user, by default, only in large BAR systems
2568 * Compute VM tables will be updated by CPU
2570 #ifdef CONFIG_X86_64
2571 if (amdgpu_vm_update_mode == -1) {
2572 if (amdgpu_vm_is_large_bar(adev))
2573 adev->vm_manager.vm_update_mode =
2574 AMDGPU_VM_USE_CPU_FOR_COMPUTE;
2576 adev->vm_manager.vm_update_mode = 0;
2578 adev->vm_manager.vm_update_mode = amdgpu_vm_update_mode;
2580 adev->vm_manager.vm_update_mode = 0;
2586 * amdgpu_vm_manager_fini - cleanup VM manager
2588 * @adev: amdgpu_device pointer
2590 * Cleanup the VM manager and free resources.
2592 void amdgpu_vm_manager_fini(struct amdgpu_device *adev)
2596 for (i = 0; i < AMDGPU_MAX_VMHUBS; ++i) {
2597 struct amdgpu_vm_id_manager *id_mgr =
2598 &adev->vm_manager.id_mgr[i];
2600 mutex_destroy(&id_mgr->lock);
2601 for (j = 0; j < AMDGPU_NUM_VM; ++j) {
2602 struct amdgpu_vm_id *id = &id_mgr->ids[j];
2604 amdgpu_sync_free(&id->active);
2605 dma_fence_put(id->flushed_updates);
2606 dma_fence_put(id->last_flush);
2611 int amdgpu_vm_ioctl(struct drm_device *dev, void *data, struct drm_file *filp)
2613 union drm_amdgpu_vm *args = data;
2614 struct amdgpu_device *adev = dev->dev_private;
2615 struct amdgpu_fpriv *fpriv = filp->driver_priv;
2618 switch (args->in.op) {
2619 case AMDGPU_VM_OP_RESERVE_VMID:
2620 /* current, we only have requirement to reserve vmid from gfxhub */
2621 r = amdgpu_vm_alloc_reserved_vmid(adev, &fpriv->vm,
2626 case AMDGPU_VM_OP_UNRESERVE_VMID:
2627 amdgpu_vm_free_reserved_vmid(adev, &fpriv->vm, AMDGPU_GFXHUB);