2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
24 * Authors: Dave Airlie
29 #include <linux/dma-fence-array.h>
30 #include <linux/interval_tree_generic.h>
31 #include <linux/idr.h>
32 #include <linux/dma-buf.h>
34 #include <drm/amdgpu_drm.h>
35 #include <drm/drm_drv.h>
37 #include "amdgpu_trace.h"
38 #include "amdgpu_amdkfd.h"
39 #include "amdgpu_gmc.h"
40 #include "amdgpu_xgmi.h"
41 #include "amdgpu_dma_buf.h"
42 #include "amdgpu_res_cursor.h"
48 * GPUVM is similar to the legacy gart on older asics, however
49 * rather than there being a single global gart table
50 * for the entire GPU, there are multiple VM page tables active
51 * at any given time. The VM page tables can contain a mix
52 * vram pages and system memory pages and system memory pages
53 * can be mapped as snooped (cached system pages) or unsnooped
54 * (uncached system pages).
55 * Each VM has an ID associated with it and there is a page table
56 * associated with each VMID. When execting a command buffer,
57 * the kernel tells the the ring what VMID to use for that command
58 * buffer. VMIDs are allocated dynamically as commands are submitted.
59 * The userspace drivers maintain their own address space and the kernel
60 * sets up their pages tables accordingly when they submit their
61 * command buffers and a VMID is assigned.
62 * Cayman/Trinity support up to 8 active VMs at any given time;
66 #define START(node) ((node)->start)
67 #define LAST(node) ((node)->last)
69 INTERVAL_TREE_DEFINE(struct amdgpu_bo_va_mapping, rb, uint64_t, __subtree_last,
70 START, LAST, static, amdgpu_vm_it)
76 * struct amdgpu_prt_cb - Helper to disable partial resident texture feature from a fence callback
78 struct amdgpu_prt_cb {
81 * @adev: amdgpu device
83 struct amdgpu_device *adev;
88 struct dma_fence_cb cb;
92 * vm eviction_lock can be taken in MMU notifiers. Make sure no reclaim-FS
93 * happens while holding this lock anywhere to prevent deadlocks when
94 * an MMU notifier runs in reclaim-FS context.
96 static inline void amdgpu_vm_eviction_lock(struct amdgpu_vm *vm)
98 mutex_lock(&vm->eviction_lock);
99 vm->saved_flags = memalloc_noreclaim_save();
102 static inline int amdgpu_vm_eviction_trylock(struct amdgpu_vm *vm)
104 if (mutex_trylock(&vm->eviction_lock)) {
105 vm->saved_flags = memalloc_noreclaim_save();
111 static inline void amdgpu_vm_eviction_unlock(struct amdgpu_vm *vm)
113 memalloc_noreclaim_restore(vm->saved_flags);
114 mutex_unlock(&vm->eviction_lock);
118 * amdgpu_vm_level_shift - return the addr shift for each level
120 * @adev: amdgpu_device pointer
124 * The number of bits the pfn needs to be right shifted for a level.
126 static unsigned amdgpu_vm_level_shift(struct amdgpu_device *adev,
133 return 9 * (AMDGPU_VM_PDB0 - level) +
134 adev->vm_manager.block_size;
143 * amdgpu_vm_num_entries - return the number of entries in a PD/PT
145 * @adev: amdgpu_device pointer
149 * The number of entries in a page directory or page table.
151 static unsigned amdgpu_vm_num_entries(struct amdgpu_device *adev,
154 unsigned shift = amdgpu_vm_level_shift(adev,
155 adev->vm_manager.root_level);
157 if (level == adev->vm_manager.root_level)
158 /* For the root directory */
159 return round_up(adev->vm_manager.max_pfn, 1ULL << shift)
161 else if (level != AMDGPU_VM_PTB)
162 /* Everything in between */
165 /* For the page tables on the leaves */
166 return AMDGPU_VM_PTE_COUNT(adev);
170 * amdgpu_vm_num_ats_entries - return the number of ATS entries in the root PD
172 * @adev: amdgpu_device pointer
175 * The number of entries in the root page directory which needs the ATS setting.
177 static unsigned amdgpu_vm_num_ats_entries(struct amdgpu_device *adev)
181 shift = amdgpu_vm_level_shift(adev, adev->vm_manager.root_level);
182 return AMDGPU_GMC_HOLE_START >> (shift + AMDGPU_GPU_PAGE_SHIFT);
186 * amdgpu_vm_entries_mask - the mask to get the entry number of a PD/PT
188 * @adev: amdgpu_device pointer
192 * The mask to extract the entry number of a PD/PT from an address.
194 static uint32_t amdgpu_vm_entries_mask(struct amdgpu_device *adev,
197 if (level <= adev->vm_manager.root_level)
199 else if (level != AMDGPU_VM_PTB)
202 return AMDGPU_VM_PTE_COUNT(adev) - 1;
206 * amdgpu_vm_bo_size - returns the size of the BOs in bytes
208 * @adev: amdgpu_device pointer
212 * The size of the BO for a page directory or page table in bytes.
214 static unsigned amdgpu_vm_bo_size(struct amdgpu_device *adev, unsigned level)
216 return AMDGPU_GPU_PAGE_ALIGN(amdgpu_vm_num_entries(adev, level) * 8);
220 * amdgpu_vm_bo_evicted - vm_bo is evicted
222 * @vm_bo: vm_bo which is evicted
224 * State for PDs/PTs and per VM BOs which are not at the location they should
227 static void amdgpu_vm_bo_evicted(struct amdgpu_vm_bo_base *vm_bo)
229 struct amdgpu_vm *vm = vm_bo->vm;
230 struct amdgpu_bo *bo = vm_bo->bo;
233 if (bo->tbo.type == ttm_bo_type_kernel)
234 list_move(&vm_bo->vm_status, &vm->evicted);
236 list_move_tail(&vm_bo->vm_status, &vm->evicted);
239 * amdgpu_vm_bo_moved - vm_bo is moved
241 * @vm_bo: vm_bo which is moved
243 * State for per VM BOs which are moved, but that change is not yet reflected
244 * in the page tables.
246 static void amdgpu_vm_bo_moved(struct amdgpu_vm_bo_base *vm_bo)
248 list_move(&vm_bo->vm_status, &vm_bo->vm->moved);
252 * amdgpu_vm_bo_idle - vm_bo is idle
254 * @vm_bo: vm_bo which is now idle
256 * State for PDs/PTs and per VM BOs which have gone through the state machine
259 static void amdgpu_vm_bo_idle(struct amdgpu_vm_bo_base *vm_bo)
261 list_move(&vm_bo->vm_status, &vm_bo->vm->idle);
262 vm_bo->moved = false;
266 * amdgpu_vm_bo_invalidated - vm_bo is invalidated
268 * @vm_bo: vm_bo which is now invalidated
270 * State for normal BOs which are invalidated and that change not yet reflected
273 static void amdgpu_vm_bo_invalidated(struct amdgpu_vm_bo_base *vm_bo)
275 spin_lock(&vm_bo->vm->invalidated_lock);
276 list_move(&vm_bo->vm_status, &vm_bo->vm->invalidated);
277 spin_unlock(&vm_bo->vm->invalidated_lock);
281 * amdgpu_vm_bo_relocated - vm_bo is reloacted
283 * @vm_bo: vm_bo which is relocated
285 * State for PDs/PTs which needs to update their parent PD.
286 * For the root PD, just move to idle state.
288 static void amdgpu_vm_bo_relocated(struct amdgpu_vm_bo_base *vm_bo)
290 if (vm_bo->bo->parent)
291 list_move(&vm_bo->vm_status, &vm_bo->vm->relocated);
293 amdgpu_vm_bo_idle(vm_bo);
297 * amdgpu_vm_bo_done - vm_bo is done
299 * @vm_bo: vm_bo which is now done
301 * State for normal BOs which are invalidated and that change has been updated
304 static void amdgpu_vm_bo_done(struct amdgpu_vm_bo_base *vm_bo)
306 spin_lock(&vm_bo->vm->invalidated_lock);
307 list_move(&vm_bo->vm_status, &vm_bo->vm->done);
308 spin_unlock(&vm_bo->vm->invalidated_lock);
312 * amdgpu_vm_bo_base_init - Adds bo to the list of bos associated with the vm
314 * @base: base structure for tracking BO usage in a VM
315 * @vm: vm to which bo is to be added
316 * @bo: amdgpu buffer object
318 * Initialize a bo_va_base structure and add it to the appropriate lists
321 static void amdgpu_vm_bo_base_init(struct amdgpu_vm_bo_base *base,
322 struct amdgpu_vm *vm,
323 struct amdgpu_bo *bo)
328 INIT_LIST_HEAD(&base->vm_status);
332 base->next = bo->vm_bo;
335 if (bo->tbo.base.resv != vm->root.bo->tbo.base.resv)
338 vm->bulk_moveable = false;
339 if (bo->tbo.type == ttm_bo_type_kernel && bo->parent)
340 amdgpu_vm_bo_relocated(base);
342 amdgpu_vm_bo_idle(base);
344 if (bo->preferred_domains &
345 amdgpu_mem_type_to_domain(bo->tbo.resource->mem_type))
349 * we checked all the prerequisites, but it looks like this per vm bo
350 * is currently evicted. add the bo to the evicted list to make sure it
351 * is validated on next vm use to avoid fault.
353 amdgpu_vm_bo_evicted(base);
357 * amdgpu_vm_pt_parent - get the parent page directory
359 * @pt: child page table
361 * Helper to get the parent entry for the child page table. NULL if we are at
362 * the root page directory.
364 static struct amdgpu_vm_bo_base *amdgpu_vm_pt_parent(struct amdgpu_vm_bo_base *pt)
366 struct amdgpu_bo *parent = pt->bo->parent;
371 return parent->vm_bo;
375 * amdgpu_vm_pt_cursor - state for for_each_amdgpu_vm_pt
377 struct amdgpu_vm_pt_cursor {
379 struct amdgpu_vm_bo_base *parent;
380 struct amdgpu_vm_bo_base *entry;
385 * amdgpu_vm_pt_start - start PD/PT walk
387 * @adev: amdgpu_device pointer
388 * @vm: amdgpu_vm structure
389 * @start: start address of the walk
390 * @cursor: state to initialize
392 * Initialize a amdgpu_vm_pt_cursor to start a walk.
394 static void amdgpu_vm_pt_start(struct amdgpu_device *adev,
395 struct amdgpu_vm *vm, uint64_t start,
396 struct amdgpu_vm_pt_cursor *cursor)
399 cursor->parent = NULL;
400 cursor->entry = &vm->root;
401 cursor->level = adev->vm_manager.root_level;
405 * amdgpu_vm_pt_descendant - go to child node
407 * @adev: amdgpu_device pointer
408 * @cursor: current state
410 * Walk to the child node of the current node.
412 * True if the walk was possible, false otherwise.
414 static bool amdgpu_vm_pt_descendant(struct amdgpu_device *adev,
415 struct amdgpu_vm_pt_cursor *cursor)
417 unsigned mask, shift, idx;
419 if ((cursor->level == AMDGPU_VM_PTB) || !cursor->entry ||
423 mask = amdgpu_vm_entries_mask(adev, cursor->level);
424 shift = amdgpu_vm_level_shift(adev, cursor->level);
427 idx = (cursor->pfn >> shift) & mask;
428 cursor->parent = cursor->entry;
429 cursor->entry = &to_amdgpu_bo_vm(cursor->entry->bo)->entries[idx];
434 * amdgpu_vm_pt_sibling - go to sibling node
436 * @adev: amdgpu_device pointer
437 * @cursor: current state
439 * Walk to the sibling node of the current node.
441 * True if the walk was possible, false otherwise.
443 static bool amdgpu_vm_pt_sibling(struct amdgpu_device *adev,
444 struct amdgpu_vm_pt_cursor *cursor)
446 unsigned shift, num_entries;
448 /* Root doesn't have a sibling */
452 /* Go to our parents and see if we got a sibling */
453 shift = amdgpu_vm_level_shift(adev, cursor->level - 1);
454 num_entries = amdgpu_vm_num_entries(adev, cursor->level - 1);
456 if (cursor->entry == &to_amdgpu_bo_vm(cursor->parent->bo)->entries[num_entries - 1])
459 cursor->pfn += 1ULL << shift;
460 cursor->pfn &= ~((1ULL << shift) - 1);
466 * amdgpu_vm_pt_ancestor - go to parent node
468 * @cursor: current state
470 * Walk to the parent node of the current node.
472 * True if the walk was possible, false otherwise.
474 static bool amdgpu_vm_pt_ancestor(struct amdgpu_vm_pt_cursor *cursor)
480 cursor->entry = cursor->parent;
481 cursor->parent = amdgpu_vm_pt_parent(cursor->parent);
486 * amdgpu_vm_pt_next - get next PD/PT in hieratchy
488 * @adev: amdgpu_device pointer
489 * @cursor: current state
491 * Walk the PD/PT tree to the next node.
493 static void amdgpu_vm_pt_next(struct amdgpu_device *adev,
494 struct amdgpu_vm_pt_cursor *cursor)
496 /* First try a newborn child */
497 if (amdgpu_vm_pt_descendant(adev, cursor))
500 /* If that didn't worked try to find a sibling */
501 while (!amdgpu_vm_pt_sibling(adev, cursor)) {
502 /* No sibling, go to our parents and grandparents */
503 if (!amdgpu_vm_pt_ancestor(cursor)) {
511 * amdgpu_vm_pt_first_dfs - start a deep first search
513 * @adev: amdgpu_device structure
514 * @vm: amdgpu_vm structure
515 * @start: optional cursor to start with
516 * @cursor: state to initialize
518 * Starts a deep first traversal of the PD/PT tree.
520 static void amdgpu_vm_pt_first_dfs(struct amdgpu_device *adev,
521 struct amdgpu_vm *vm,
522 struct amdgpu_vm_pt_cursor *start,
523 struct amdgpu_vm_pt_cursor *cursor)
528 amdgpu_vm_pt_start(adev, vm, 0, cursor);
529 while (amdgpu_vm_pt_descendant(adev, cursor));
533 * amdgpu_vm_pt_continue_dfs - check if the deep first search should continue
535 * @start: starting point for the search
536 * @entry: current entry
539 * True when the search should continue, false otherwise.
541 static bool amdgpu_vm_pt_continue_dfs(struct amdgpu_vm_pt_cursor *start,
542 struct amdgpu_vm_bo_base *entry)
544 return entry && (!start || entry != start->entry);
548 * amdgpu_vm_pt_next_dfs - get the next node for a deep first search
550 * @adev: amdgpu_device structure
551 * @cursor: current state
553 * Move the cursor to the next node in a deep first search.
555 static void amdgpu_vm_pt_next_dfs(struct amdgpu_device *adev,
556 struct amdgpu_vm_pt_cursor *cursor)
562 cursor->entry = NULL;
563 else if (amdgpu_vm_pt_sibling(adev, cursor))
564 while (amdgpu_vm_pt_descendant(adev, cursor));
566 amdgpu_vm_pt_ancestor(cursor);
570 * for_each_amdgpu_vm_pt_dfs_safe - safe deep first search of all PDs/PTs
572 #define for_each_amdgpu_vm_pt_dfs_safe(adev, vm, start, cursor, entry) \
573 for (amdgpu_vm_pt_first_dfs((adev), (vm), (start), &(cursor)), \
574 (entry) = (cursor).entry, amdgpu_vm_pt_next_dfs((adev), &(cursor));\
575 amdgpu_vm_pt_continue_dfs((start), (entry)); \
576 (entry) = (cursor).entry, amdgpu_vm_pt_next_dfs((adev), &(cursor)))
579 * amdgpu_vm_get_pd_bo - add the VM PD to a validation list
581 * @vm: vm providing the BOs
582 * @validated: head of validation list
583 * @entry: entry to add
585 * Add the page directory to the list of BOs to
586 * validate for command submission.
588 void amdgpu_vm_get_pd_bo(struct amdgpu_vm *vm,
589 struct list_head *validated,
590 struct amdgpu_bo_list_entry *entry)
593 entry->tv.bo = &vm->root.bo->tbo;
594 /* Two for VM updates, one for TTM and one for the CS job */
595 entry->tv.num_shared = 4;
596 entry->user_pages = NULL;
597 list_add(&entry->tv.head, validated);
601 * amdgpu_vm_del_from_lru_notify - update bulk_moveable flag
603 * @bo: BO which was removed from the LRU
605 * Make sure the bulk_moveable flag is updated when a BO is removed from the
608 void amdgpu_vm_del_from_lru_notify(struct ttm_buffer_object *bo)
610 struct amdgpu_bo *abo;
611 struct amdgpu_vm_bo_base *bo_base;
613 if (!amdgpu_bo_is_amdgpu_bo(bo))
619 abo = ttm_to_amdgpu_bo(bo);
622 for (bo_base = abo->vm_bo; bo_base; bo_base = bo_base->next) {
623 struct amdgpu_vm *vm = bo_base->vm;
625 if (abo->tbo.base.resv == vm->root.bo->tbo.base.resv)
626 vm->bulk_moveable = false;
631 * amdgpu_vm_move_to_lru_tail - move all BOs to the end of LRU
633 * @adev: amdgpu device pointer
634 * @vm: vm providing the BOs
636 * Move all BOs to the end of LRU and remember their positions to put them
639 void amdgpu_vm_move_to_lru_tail(struct amdgpu_device *adev,
640 struct amdgpu_vm *vm)
642 struct amdgpu_vm_bo_base *bo_base;
644 if (vm->bulk_moveable) {
645 spin_lock(&adev->mman.bdev.lru_lock);
646 ttm_bo_bulk_move_lru_tail(&vm->lru_bulk_move);
647 spin_unlock(&adev->mman.bdev.lru_lock);
651 memset(&vm->lru_bulk_move, 0, sizeof(vm->lru_bulk_move));
653 spin_lock(&adev->mman.bdev.lru_lock);
654 list_for_each_entry(bo_base, &vm->idle, vm_status) {
655 struct amdgpu_bo *bo = bo_base->bo;
656 struct amdgpu_bo *shadow = amdgpu_bo_shadowed(bo);
661 ttm_bo_move_to_lru_tail(&bo->tbo, bo->tbo.resource,
664 ttm_bo_move_to_lru_tail(&shadow->tbo,
665 shadow->tbo.resource,
668 spin_unlock(&adev->mman.bdev.lru_lock);
670 vm->bulk_moveable = true;
674 * amdgpu_vm_validate_pt_bos - validate the page table BOs
676 * @adev: amdgpu device pointer
677 * @vm: vm providing the BOs
678 * @validate: callback to do the validation
679 * @param: parameter for the validation callback
681 * Validate the page table BOs on command submission if neccessary.
686 int amdgpu_vm_validate_pt_bos(struct amdgpu_device *adev, struct amdgpu_vm *vm,
687 int (*validate)(void *p, struct amdgpu_bo *bo),
690 struct amdgpu_vm_bo_base *bo_base, *tmp;
693 vm->bulk_moveable &= list_empty(&vm->evicted);
695 list_for_each_entry_safe(bo_base, tmp, &vm->evicted, vm_status) {
696 struct amdgpu_bo *bo = bo_base->bo;
697 struct amdgpu_bo *shadow = amdgpu_bo_shadowed(bo);
699 r = validate(param, bo);
703 r = validate(param, shadow);
708 if (bo->tbo.type != ttm_bo_type_kernel) {
709 amdgpu_vm_bo_moved(bo_base);
711 vm->update_funcs->map_table(to_amdgpu_bo_vm(bo));
712 amdgpu_vm_bo_relocated(bo_base);
716 amdgpu_vm_eviction_lock(vm);
717 vm->evicting = false;
718 amdgpu_vm_eviction_unlock(vm);
724 * amdgpu_vm_ready - check VM is ready for updates
728 * Check if all VM PDs/PTs are ready for updates
731 * True if eviction list is empty.
733 bool amdgpu_vm_ready(struct amdgpu_vm *vm)
735 return list_empty(&vm->evicted);
739 * amdgpu_vm_clear_bo - initially clear the PDs/PTs
741 * @adev: amdgpu_device pointer
742 * @vm: VM to clear BO from
744 * @immediate: use an immediate update
746 * Root PD needs to be reserved when calling this.
749 * 0 on success, errno otherwise.
751 static int amdgpu_vm_clear_bo(struct amdgpu_device *adev,
752 struct amdgpu_vm *vm,
753 struct amdgpu_bo_vm *vmbo,
756 struct ttm_operation_ctx ctx = { true, false };
757 unsigned level = adev->vm_manager.root_level;
758 struct amdgpu_vm_update_params params;
759 struct amdgpu_bo *ancestor = &vmbo->bo;
760 struct amdgpu_bo *bo = &vmbo->bo;
761 unsigned entries, ats_entries;
765 /* Figure out our place in the hierarchy */
766 if (ancestor->parent) {
768 while (ancestor->parent->parent) {
770 ancestor = ancestor->parent;
774 entries = amdgpu_bo_size(bo) / 8;
775 if (!vm->pte_support_ats) {
778 } else if (!bo->parent) {
779 ats_entries = amdgpu_vm_num_ats_entries(adev);
780 ats_entries = min(ats_entries, entries);
781 entries -= ats_entries;
784 struct amdgpu_vm_bo_base *pt;
786 pt = ancestor->vm_bo;
787 ats_entries = amdgpu_vm_num_ats_entries(adev);
788 if ((pt - to_amdgpu_bo_vm(vm->root.bo)->entries) >= ats_entries) {
791 ats_entries = entries;
796 r = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx);
801 struct amdgpu_bo *shadow = vmbo->shadow;
803 r = ttm_bo_validate(&shadow->tbo, &shadow->placement, &ctx);
808 r = vm->update_funcs->map_table(vmbo);
812 memset(¶ms, 0, sizeof(params));
815 params.immediate = immediate;
817 r = vm->update_funcs->prepare(¶ms, NULL, AMDGPU_SYNC_EXPLICIT);
823 uint64_t value = 0, flags;
825 flags = AMDGPU_PTE_DEFAULT_ATC;
826 if (level != AMDGPU_VM_PTB) {
827 /* Handle leaf PDEs as PTEs */
828 flags |= AMDGPU_PDE_PTE;
829 amdgpu_gmc_get_vm_pde(adev, level, &value, &flags);
832 r = vm->update_funcs->update(¶ms, vmbo, addr, 0, ats_entries,
837 addr += ats_entries * 8;
841 uint64_t value = 0, flags = 0;
843 if (adev->asic_type >= CHIP_VEGA10) {
844 if (level != AMDGPU_VM_PTB) {
845 /* Handle leaf PDEs as PTEs */
846 flags |= AMDGPU_PDE_PTE;
847 amdgpu_gmc_get_vm_pde(adev, level,
850 /* Workaround for fault priority problem on GMC9 */
851 flags = AMDGPU_PTE_EXECUTABLE;
855 r = vm->update_funcs->update(¶ms, vmbo, addr, 0, entries,
861 return vm->update_funcs->commit(¶ms, NULL);
865 * amdgpu_vm_pt_create - create bo for PD/PT
867 * @adev: amdgpu_device pointer
869 * @level: the page table level
870 * @immediate: use a immediate update
871 * @vmbo: pointer to the buffer object pointer
873 static int amdgpu_vm_pt_create(struct amdgpu_device *adev,
874 struct amdgpu_vm *vm,
875 int level, bool immediate,
876 struct amdgpu_bo_vm **vmbo)
878 struct amdgpu_bo_param bp;
879 struct amdgpu_bo *bo;
880 struct dma_resv *resv;
881 unsigned int num_entries;
884 memset(&bp, 0, sizeof(bp));
886 bp.size = amdgpu_vm_bo_size(adev, level);
887 bp.byte_align = AMDGPU_GPU_PAGE_SIZE;
888 bp.domain = AMDGPU_GEM_DOMAIN_VRAM;
889 bp.domain = amdgpu_bo_get_preferred_pin_domain(adev, bp.domain);
890 bp.flags = AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS |
891 AMDGPU_GEM_CREATE_CPU_GTT_USWC;
893 if (level < AMDGPU_VM_PTB)
894 num_entries = amdgpu_vm_num_entries(adev, level);
898 bp.bo_ptr_size = struct_size((*vmbo), entries, num_entries);
900 if (vm->use_cpu_for_update)
901 bp.flags |= AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED;
903 bp.type = ttm_bo_type_kernel;
904 bp.no_wait_gpu = immediate;
906 bp.resv = vm->root.bo->tbo.base.resv;
908 r = amdgpu_bo_create_vm(adev, &bp, vmbo);
913 if (vm->is_compute_context || (adev->flags & AMD_IS_APU)) {
914 (*vmbo)->shadow = NULL;
919 WARN_ON(dma_resv_lock(bo->tbo.base.resv,
922 memset(&bp, 0, sizeof(bp));
923 bp.size = amdgpu_vm_bo_size(adev, level);
924 bp.domain = AMDGPU_GEM_DOMAIN_GTT;
925 bp.flags = AMDGPU_GEM_CREATE_CPU_GTT_USWC;
926 bp.type = ttm_bo_type_kernel;
927 bp.resv = bo->tbo.base.resv;
928 bp.bo_ptr_size = sizeof(struct amdgpu_bo);
930 r = amdgpu_bo_create(adev, &bp, &(*vmbo)->shadow);
933 dma_resv_unlock(bo->tbo.base.resv);
936 amdgpu_bo_unref(&bo);
940 (*vmbo)->shadow->parent = amdgpu_bo_ref(bo);
941 amdgpu_bo_add_to_shadow_list(*vmbo);
947 * amdgpu_vm_alloc_pts - Allocate a specific page table
949 * @adev: amdgpu_device pointer
950 * @vm: VM to allocate page tables for
951 * @cursor: Which page table to allocate
952 * @immediate: use an immediate update
954 * Make sure a specific page table or directory is allocated.
957 * 1 if page table needed to be allocated, 0 if page table was already
958 * allocated, negative errno if an error occurred.
960 static int amdgpu_vm_alloc_pts(struct amdgpu_device *adev,
961 struct amdgpu_vm *vm,
962 struct amdgpu_vm_pt_cursor *cursor,
965 struct amdgpu_vm_bo_base *entry = cursor->entry;
966 struct amdgpu_bo *pt_bo;
967 struct amdgpu_bo_vm *pt;
973 r = amdgpu_vm_pt_create(adev, vm, cursor->level, immediate, &pt);
977 /* Keep a reference to the root directory to avoid
978 * freeing them up in the wrong order.
981 pt_bo->parent = amdgpu_bo_ref(cursor->parent->bo);
982 amdgpu_vm_bo_base_init(entry, vm, pt_bo);
983 r = amdgpu_vm_clear_bo(adev, vm, pt, immediate);
990 amdgpu_bo_unref(&pt->shadow);
991 amdgpu_bo_unref(&pt_bo);
996 * amdgpu_vm_free_table - fre one PD/PT
998 * @entry: PDE to free
1000 static void amdgpu_vm_free_table(struct amdgpu_vm_bo_base *entry)
1002 struct amdgpu_bo *shadow;
1006 shadow = amdgpu_bo_shadowed(entry->bo);
1007 entry->bo->vm_bo = NULL;
1008 list_del(&entry->vm_status);
1009 amdgpu_bo_unref(&shadow);
1010 amdgpu_bo_unref(&entry->bo);
1014 * amdgpu_vm_free_pts - free PD/PT levels
1016 * @adev: amdgpu device structure
1017 * @vm: amdgpu vm structure
1018 * @start: optional cursor where to start freeing PDs/PTs
1020 * Free the page directory or page table level and all sub levels.
1022 static void amdgpu_vm_free_pts(struct amdgpu_device *adev,
1023 struct amdgpu_vm *vm,
1024 struct amdgpu_vm_pt_cursor *start)
1026 struct amdgpu_vm_pt_cursor cursor;
1027 struct amdgpu_vm_bo_base *entry;
1029 vm->bulk_moveable = false;
1031 for_each_amdgpu_vm_pt_dfs_safe(adev, vm, start, cursor, entry)
1032 amdgpu_vm_free_table(entry);
1035 amdgpu_vm_free_table(start->entry);
1039 * amdgpu_vm_check_compute_bug - check whether asic has compute vm bug
1041 * @adev: amdgpu_device pointer
1043 void amdgpu_vm_check_compute_bug(struct amdgpu_device *adev)
1045 const struct amdgpu_ip_block *ip_block;
1046 bool has_compute_vm_bug;
1047 struct amdgpu_ring *ring;
1050 has_compute_vm_bug = false;
1052 ip_block = amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_GFX);
1054 /* Compute has a VM bug for GFX version < 7.
1055 Compute has a VM bug for GFX 8 MEC firmware version < 673.*/
1056 if (ip_block->version->major <= 7)
1057 has_compute_vm_bug = true;
1058 else if (ip_block->version->major == 8)
1059 if (adev->gfx.mec_fw_version < 673)
1060 has_compute_vm_bug = true;
1063 for (i = 0; i < adev->num_rings; i++) {
1064 ring = adev->rings[i];
1065 if (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE)
1066 /* only compute rings */
1067 ring->has_compute_vm_bug = has_compute_vm_bug;
1069 ring->has_compute_vm_bug = false;
1074 * amdgpu_vm_need_pipeline_sync - Check if pipe sync is needed for job.
1076 * @ring: ring on which the job will be submitted
1077 * @job: job to submit
1080 * True if sync is needed.
1082 bool amdgpu_vm_need_pipeline_sync(struct amdgpu_ring *ring,
1083 struct amdgpu_job *job)
1085 struct amdgpu_device *adev = ring->adev;
1086 unsigned vmhub = ring->funcs->vmhub;
1087 struct amdgpu_vmid_mgr *id_mgr = &adev->vm_manager.id_mgr[vmhub];
1088 struct amdgpu_vmid *id;
1089 bool gds_switch_needed;
1090 bool vm_flush_needed = job->vm_needs_flush || ring->has_compute_vm_bug;
1094 id = &id_mgr->ids[job->vmid];
1095 gds_switch_needed = ring->funcs->emit_gds_switch && (
1096 id->gds_base != job->gds_base ||
1097 id->gds_size != job->gds_size ||
1098 id->gws_base != job->gws_base ||
1099 id->gws_size != job->gws_size ||
1100 id->oa_base != job->oa_base ||
1101 id->oa_size != job->oa_size);
1103 if (amdgpu_vmid_had_gpu_reset(adev, id))
1106 return vm_flush_needed || gds_switch_needed;
1110 * amdgpu_vm_flush - hardware flush the vm
1112 * @ring: ring to use for flush
1114 * @need_pipe_sync: is pipe sync needed
1116 * Emit a VM flush when it is necessary.
1119 * 0 on success, errno otherwise.
1121 int amdgpu_vm_flush(struct amdgpu_ring *ring, struct amdgpu_job *job,
1122 bool need_pipe_sync)
1124 struct amdgpu_device *adev = ring->adev;
1125 unsigned vmhub = ring->funcs->vmhub;
1126 struct amdgpu_vmid_mgr *id_mgr = &adev->vm_manager.id_mgr[vmhub];
1127 struct amdgpu_vmid *id = &id_mgr->ids[job->vmid];
1128 bool gds_switch_needed = ring->funcs->emit_gds_switch && (
1129 id->gds_base != job->gds_base ||
1130 id->gds_size != job->gds_size ||
1131 id->gws_base != job->gws_base ||
1132 id->gws_size != job->gws_size ||
1133 id->oa_base != job->oa_base ||
1134 id->oa_size != job->oa_size);
1135 bool vm_flush_needed = job->vm_needs_flush;
1136 struct dma_fence *fence = NULL;
1137 bool pasid_mapping_needed = false;
1138 unsigned patch_offset = 0;
1139 bool update_spm_vmid_needed = (job->vm && (job->vm->reserved_vmid[vmhub] != NULL));
1142 if (update_spm_vmid_needed && adev->gfx.rlc.funcs->update_spm_vmid)
1143 adev->gfx.rlc.funcs->update_spm_vmid(adev, job->vmid);
1145 if (amdgpu_vmid_had_gpu_reset(adev, id)) {
1146 gds_switch_needed = true;
1147 vm_flush_needed = true;
1148 pasid_mapping_needed = true;
1151 mutex_lock(&id_mgr->lock);
1152 if (id->pasid != job->pasid || !id->pasid_mapping ||
1153 !dma_fence_is_signaled(id->pasid_mapping))
1154 pasid_mapping_needed = true;
1155 mutex_unlock(&id_mgr->lock);
1157 gds_switch_needed &= !!ring->funcs->emit_gds_switch;
1158 vm_flush_needed &= !!ring->funcs->emit_vm_flush &&
1159 job->vm_pd_addr != AMDGPU_BO_INVALID_OFFSET;
1160 pasid_mapping_needed &= adev->gmc.gmc_funcs->emit_pasid_mapping &&
1161 ring->funcs->emit_wreg;
1163 if (!vm_flush_needed && !gds_switch_needed && !need_pipe_sync)
1166 if (ring->funcs->init_cond_exec)
1167 patch_offset = amdgpu_ring_init_cond_exec(ring);
1170 amdgpu_ring_emit_pipeline_sync(ring);
1172 if (vm_flush_needed) {
1173 trace_amdgpu_vm_flush(ring, job->vmid, job->vm_pd_addr);
1174 amdgpu_ring_emit_vm_flush(ring, job->vmid, job->vm_pd_addr);
1177 if (pasid_mapping_needed)
1178 amdgpu_gmc_emit_pasid_mapping(ring, job->vmid, job->pasid);
1180 if (vm_flush_needed || pasid_mapping_needed) {
1181 r = amdgpu_fence_emit(ring, &fence, 0);
1186 if (vm_flush_needed) {
1187 mutex_lock(&id_mgr->lock);
1188 dma_fence_put(id->last_flush);
1189 id->last_flush = dma_fence_get(fence);
1190 id->current_gpu_reset_count =
1191 atomic_read(&adev->gpu_reset_counter);
1192 mutex_unlock(&id_mgr->lock);
1195 if (pasid_mapping_needed) {
1196 mutex_lock(&id_mgr->lock);
1197 id->pasid = job->pasid;
1198 dma_fence_put(id->pasid_mapping);
1199 id->pasid_mapping = dma_fence_get(fence);
1200 mutex_unlock(&id_mgr->lock);
1202 dma_fence_put(fence);
1204 if (ring->funcs->emit_gds_switch && gds_switch_needed) {
1205 id->gds_base = job->gds_base;
1206 id->gds_size = job->gds_size;
1207 id->gws_base = job->gws_base;
1208 id->gws_size = job->gws_size;
1209 id->oa_base = job->oa_base;
1210 id->oa_size = job->oa_size;
1211 amdgpu_ring_emit_gds_switch(ring, job->vmid, job->gds_base,
1212 job->gds_size, job->gws_base,
1213 job->gws_size, job->oa_base,
1217 if (ring->funcs->patch_cond_exec)
1218 amdgpu_ring_patch_cond_exec(ring, patch_offset);
1220 /* the double SWITCH_BUFFER here *cannot* be skipped by COND_EXEC */
1221 if (ring->funcs->emit_switch_buffer) {
1222 amdgpu_ring_emit_switch_buffer(ring);
1223 amdgpu_ring_emit_switch_buffer(ring);
1229 * amdgpu_vm_bo_find - find the bo_va for a specific vm & bo
1232 * @bo: requested buffer object
1234 * Find @bo inside the requested vm.
1235 * Search inside the @bos vm list for the requested vm
1236 * Returns the found bo_va or NULL if none is found
1238 * Object has to be reserved!
1241 * Found bo_va or NULL.
1243 struct amdgpu_bo_va *amdgpu_vm_bo_find(struct amdgpu_vm *vm,
1244 struct amdgpu_bo *bo)
1246 struct amdgpu_vm_bo_base *base;
1248 for (base = bo->vm_bo; base; base = base->next) {
1252 return container_of(base, struct amdgpu_bo_va, base);
1258 * amdgpu_vm_map_gart - Resolve gart mapping of addr
1260 * @pages_addr: optional DMA address to use for lookup
1261 * @addr: the unmapped addr
1263 * Look up the physical address of the page that the pte resolves
1267 * The pointer for the page table entry.
1269 uint64_t amdgpu_vm_map_gart(const dma_addr_t *pages_addr, uint64_t addr)
1273 /* page table offset */
1274 result = pages_addr[addr >> PAGE_SHIFT];
1276 /* in case cpu page size != gpu page size*/
1277 result |= addr & (~PAGE_MASK);
1279 result &= 0xFFFFFFFFFFFFF000ULL;
1285 * amdgpu_vm_update_pde - update a single level in the hierarchy
1287 * @params: parameters for the update
1289 * @entry: entry to update
1291 * Makes sure the requested entry in parent is up to date.
1293 static int amdgpu_vm_update_pde(struct amdgpu_vm_update_params *params,
1294 struct amdgpu_vm *vm,
1295 struct amdgpu_vm_bo_base *entry)
1297 struct amdgpu_vm_bo_base *parent = amdgpu_vm_pt_parent(entry);
1298 struct amdgpu_bo *bo = parent->bo, *pbo;
1299 uint64_t pde, pt, flags;
1302 for (level = 0, pbo = bo->parent; pbo; ++level)
1305 level += params->adev->vm_manager.root_level;
1306 amdgpu_gmc_get_pde_for_bo(entry->bo, level, &pt, &flags);
1307 pde = (entry - to_amdgpu_bo_vm(parent->bo)->entries) * 8;
1308 return vm->update_funcs->update(params, to_amdgpu_bo_vm(bo), pde, pt,
1313 * amdgpu_vm_invalidate_pds - mark all PDs as invalid
1315 * @adev: amdgpu_device pointer
1318 * Mark all PD level as invalid after an error.
1320 static void amdgpu_vm_invalidate_pds(struct amdgpu_device *adev,
1321 struct amdgpu_vm *vm)
1323 struct amdgpu_vm_pt_cursor cursor;
1324 struct amdgpu_vm_bo_base *entry;
1326 for_each_amdgpu_vm_pt_dfs_safe(adev, vm, NULL, cursor, entry)
1327 if (entry->bo && !entry->moved)
1328 amdgpu_vm_bo_relocated(entry);
1332 * amdgpu_vm_update_pdes - make sure that all directories are valid
1334 * @adev: amdgpu_device pointer
1336 * @immediate: submit immediately to the paging queue
1338 * Makes sure all directories are up to date.
1341 * 0 for success, error for failure.
1343 int amdgpu_vm_update_pdes(struct amdgpu_device *adev,
1344 struct amdgpu_vm *vm, bool immediate)
1346 struct amdgpu_vm_update_params params;
1349 if (list_empty(&vm->relocated))
1352 memset(¶ms, 0, sizeof(params));
1355 params.immediate = immediate;
1357 r = vm->update_funcs->prepare(¶ms, NULL, AMDGPU_SYNC_EXPLICIT);
1361 while (!list_empty(&vm->relocated)) {
1362 struct amdgpu_vm_bo_base *entry;
1364 entry = list_first_entry(&vm->relocated,
1365 struct amdgpu_vm_bo_base,
1367 amdgpu_vm_bo_idle(entry);
1369 r = amdgpu_vm_update_pde(¶ms, vm, entry);
1374 r = vm->update_funcs->commit(¶ms, &vm->last_update);
1380 amdgpu_vm_invalidate_pds(adev, vm);
1385 * amdgpu_vm_update_flags - figure out flags for PTE updates
1387 * Make sure to set the right flags for the PTEs at the desired level.
1389 static void amdgpu_vm_update_flags(struct amdgpu_vm_update_params *params,
1390 struct amdgpu_bo_vm *pt, unsigned int level,
1391 uint64_t pe, uint64_t addr,
1392 unsigned int count, uint32_t incr,
1396 if (level != AMDGPU_VM_PTB) {
1397 flags |= AMDGPU_PDE_PTE;
1398 amdgpu_gmc_get_vm_pde(params->adev, level, &addr, &flags);
1400 } else if (params->adev->asic_type >= CHIP_VEGA10 &&
1401 !(flags & AMDGPU_PTE_VALID) &&
1402 !(flags & AMDGPU_PTE_PRT)) {
1404 /* Workaround for fault priority problem on GMC9 */
1405 flags |= AMDGPU_PTE_EXECUTABLE;
1408 params->vm->update_funcs->update(params, pt, pe, addr, count, incr,
1413 * amdgpu_vm_fragment - get fragment for PTEs
1415 * @params: see amdgpu_vm_update_params definition
1416 * @start: first PTE to handle
1417 * @end: last PTE to handle
1418 * @flags: hw mapping flags
1419 * @frag: resulting fragment size
1420 * @frag_end: end of this fragment
1422 * Returns the first possible fragment for the start and end address.
1424 static void amdgpu_vm_fragment(struct amdgpu_vm_update_params *params,
1425 uint64_t start, uint64_t end, uint64_t flags,
1426 unsigned int *frag, uint64_t *frag_end)
1429 * The MC L1 TLB supports variable sized pages, based on a fragment
1430 * field in the PTE. When this field is set to a non-zero value, page
1431 * granularity is increased from 4KB to (1 << (12 + frag)). The PTE
1432 * flags are considered valid for all PTEs within the fragment range
1433 * and corresponding mappings are assumed to be physically contiguous.
1435 * The L1 TLB can store a single PTE for the whole fragment,
1436 * significantly increasing the space available for translation
1437 * caching. This leads to large improvements in throughput when the
1438 * TLB is under pressure.
1440 * The L2 TLB distributes small and large fragments into two
1441 * asymmetric partitions. The large fragment cache is significantly
1442 * larger. Thus, we try to use large fragments wherever possible.
1443 * Userspace can support this by aligning virtual base address and
1444 * allocation size to the fragment size.
1446 * Starting with Vega10 the fragment size only controls the L1. The L2
1447 * is now directly feed with small/huge/giant pages from the walker.
1451 if (params->adev->asic_type < CHIP_VEGA10)
1452 max_frag = params->adev->vm_manager.fragment_size;
1456 /* system pages are non continuously */
1457 if (params->pages_addr) {
1463 /* This intentionally wraps around if no bit is set */
1464 *frag = min((unsigned)ffs(start) - 1, (unsigned)fls64(end - start) - 1);
1465 if (*frag >= max_frag) {
1467 *frag_end = end & ~((1ULL << max_frag) - 1);
1469 *frag_end = start + (1 << *frag);
1474 * amdgpu_vm_update_ptes - make sure that page tables are valid
1476 * @params: see amdgpu_vm_update_params definition
1477 * @start: start of GPU address range
1478 * @end: end of GPU address range
1479 * @dst: destination address to map to, the next dst inside the function
1480 * @flags: mapping flags
1482 * Update the page tables in the range @start - @end.
1485 * 0 for success, -EINVAL for failure.
1487 static int amdgpu_vm_update_ptes(struct amdgpu_vm_update_params *params,
1488 uint64_t start, uint64_t end,
1489 uint64_t dst, uint64_t flags)
1491 struct amdgpu_device *adev = params->adev;
1492 struct amdgpu_vm_pt_cursor cursor;
1493 uint64_t frag_start = start, frag_end;
1497 /* figure out the initial fragment */
1498 amdgpu_vm_fragment(params, frag_start, end, flags, &frag, &frag_end);
1500 /* walk over the address space and update the PTs */
1501 amdgpu_vm_pt_start(adev, params->vm, start, &cursor);
1502 while (cursor.pfn < end) {
1503 unsigned shift, parent_shift, mask;
1504 uint64_t incr, entry_end, pe_start;
1505 struct amdgpu_bo *pt;
1507 if (!params->unlocked) {
1508 /* make sure that the page tables covering the
1509 * address range are actually allocated
1511 r = amdgpu_vm_alloc_pts(params->adev, params->vm,
1512 &cursor, params->immediate);
1517 shift = amdgpu_vm_level_shift(adev, cursor.level);
1518 parent_shift = amdgpu_vm_level_shift(adev, cursor.level - 1);
1519 if (params->unlocked) {
1520 /* Unlocked updates are only allowed on the leaves */
1521 if (amdgpu_vm_pt_descendant(adev, &cursor))
1523 } else if (adev->asic_type < CHIP_VEGA10 &&
1524 (flags & AMDGPU_PTE_VALID)) {
1525 /* No huge page support before GMC v9 */
1526 if (cursor.level != AMDGPU_VM_PTB) {
1527 if (!amdgpu_vm_pt_descendant(adev, &cursor))
1531 } else if (frag < shift) {
1532 /* We can't use this level when the fragment size is
1533 * smaller than the address shift. Go to the next
1534 * child entry and try again.
1536 if (amdgpu_vm_pt_descendant(adev, &cursor))
1538 } else if (frag >= parent_shift) {
1539 /* If the fragment size is even larger than the parent
1540 * shift we should go up one level and check it again.
1542 if (!amdgpu_vm_pt_ancestor(&cursor))
1547 pt = cursor.entry->bo;
1549 /* We need all PDs and PTs for mapping something, */
1550 if (flags & AMDGPU_PTE_VALID)
1553 /* but unmapping something can happen at a higher
1556 if (!amdgpu_vm_pt_ancestor(&cursor))
1559 pt = cursor.entry->bo;
1560 shift = parent_shift;
1561 frag_end = max(frag_end, ALIGN(frag_start + 1,
1565 /* Looks good so far, calculate parameters for the update */
1566 incr = (uint64_t)AMDGPU_GPU_PAGE_SIZE << shift;
1567 mask = amdgpu_vm_entries_mask(adev, cursor.level);
1568 pe_start = ((cursor.pfn >> shift) & mask) * 8;
1569 entry_end = ((uint64_t)mask + 1) << shift;
1570 entry_end += cursor.pfn & ~(entry_end - 1);
1571 entry_end = min(entry_end, end);
1574 struct amdgpu_vm *vm = params->vm;
1575 uint64_t upd_end = min(entry_end, frag_end);
1576 unsigned nptes = (upd_end - frag_start) >> shift;
1577 uint64_t upd_flags = flags | AMDGPU_PTE_FRAG(frag);
1579 /* This can happen when we set higher level PDs to
1580 * silent to stop fault floods.
1582 nptes = max(nptes, 1u);
1584 trace_amdgpu_vm_update_ptes(params, frag_start, upd_end,
1585 nptes, dst, incr, upd_flags,
1587 vm->immediate.fence_context);
1588 amdgpu_vm_update_flags(params, to_amdgpu_bo_vm(pt),
1589 cursor.level, pe_start, dst,
1590 nptes, incr, upd_flags);
1592 pe_start += nptes * 8;
1593 dst += nptes * incr;
1595 frag_start = upd_end;
1596 if (frag_start >= frag_end) {
1597 /* figure out the next fragment */
1598 amdgpu_vm_fragment(params, frag_start, end,
1599 flags, &frag, &frag_end);
1603 } while (frag_start < entry_end);
1605 if (amdgpu_vm_pt_descendant(adev, &cursor)) {
1606 /* Free all child entries.
1607 * Update the tables with the flags and addresses and free up subsequent
1608 * tables in the case of huge pages or freed up areas.
1609 * This is the maximum you can free, because all other page tables are not
1610 * completely covered by the range and so potentially still in use.
1612 while (cursor.pfn < frag_start) {
1613 /* Make sure previous mapping is freed */
1614 if (cursor.entry->bo) {
1615 params->table_freed = true;
1616 amdgpu_vm_free_pts(adev, params->vm, &cursor);
1618 amdgpu_vm_pt_next(adev, &cursor);
1621 } else if (frag >= shift) {
1622 /* or just move on to the next on the same level. */
1623 amdgpu_vm_pt_next(adev, &cursor);
1631 * amdgpu_vm_bo_update_mapping - update a mapping in the vm page table
1633 * @adev: amdgpu_device pointer of the VM
1634 * @bo_adev: amdgpu_device pointer of the mapped BO
1636 * @immediate: immediate submission in a page fault
1637 * @unlocked: unlocked invalidation during MM callback
1638 * @resv: fences we need to sync to
1639 * @start: start of mapped range
1640 * @last: last mapped entry
1641 * @flags: flags for the entries
1642 * @offset: offset into nodes and pages_addr
1643 * @res: ttm_resource to map
1644 * @pages_addr: DMA addresses to use for mapping
1645 * @fence: optional resulting fence
1646 * @table_freed: return true if page table is freed
1648 * Fill in the page table entries between @start and @last.
1651 * 0 for success, -EINVAL for failure.
1653 int amdgpu_vm_bo_update_mapping(struct amdgpu_device *adev,
1654 struct amdgpu_device *bo_adev,
1655 struct amdgpu_vm *vm, bool immediate,
1656 bool unlocked, struct dma_resv *resv,
1657 uint64_t start, uint64_t last,
1658 uint64_t flags, uint64_t offset,
1659 struct ttm_resource *res,
1660 dma_addr_t *pages_addr,
1661 struct dma_fence **fence,
1664 struct amdgpu_vm_update_params params;
1665 struct amdgpu_res_cursor cursor;
1666 enum amdgpu_sync_mode sync_mode;
1669 if (!drm_dev_enter(&adev->ddev, &idx))
1672 memset(¶ms, 0, sizeof(params));
1675 params.immediate = immediate;
1676 params.pages_addr = pages_addr;
1677 params.unlocked = unlocked;
1679 /* Implicitly sync to command submissions in the same VM before
1680 * unmapping. Sync to moving fences before mapping.
1682 if (!(flags & AMDGPU_PTE_VALID))
1683 sync_mode = AMDGPU_SYNC_EQ_OWNER;
1685 sync_mode = AMDGPU_SYNC_EXPLICIT;
1687 amdgpu_vm_eviction_lock(vm);
1693 if (!unlocked && !dma_fence_is_signaled(vm->last_unlocked)) {
1694 struct dma_fence *tmp = dma_fence_get_stub();
1696 amdgpu_bo_fence(vm->root.bo, vm->last_unlocked, true);
1697 swap(vm->last_unlocked, tmp);
1701 r = vm->update_funcs->prepare(¶ms, resv, sync_mode);
1705 amdgpu_res_first(pages_addr ? NULL : res, offset,
1706 (last - start + 1) * AMDGPU_GPU_PAGE_SIZE, &cursor);
1707 while (cursor.remaining) {
1708 uint64_t tmp, num_entries, addr;
1710 num_entries = cursor.size >> AMDGPU_GPU_PAGE_SHIFT;
1712 bool contiguous = true;
1714 if (num_entries > AMDGPU_GPU_PAGES_IN_CPU_PAGE) {
1715 uint64_t pfn = cursor.start >> PAGE_SHIFT;
1718 contiguous = pages_addr[pfn + 1] ==
1719 pages_addr[pfn] + PAGE_SIZE;
1722 AMDGPU_GPU_PAGES_IN_CPU_PAGE;
1723 for (count = 2; count < tmp; ++count) {
1724 uint64_t idx = pfn + count;
1726 if (contiguous != (pages_addr[idx] ==
1727 pages_addr[idx - 1] + PAGE_SIZE))
1730 num_entries = count *
1731 AMDGPU_GPU_PAGES_IN_CPU_PAGE;
1735 addr = cursor.start;
1736 params.pages_addr = pages_addr;
1738 addr = pages_addr[cursor.start >> PAGE_SHIFT];
1739 params.pages_addr = NULL;
1742 } else if (flags & (AMDGPU_PTE_VALID | AMDGPU_PTE_PRT)) {
1743 addr = bo_adev->vm_manager.vram_base_offset +
1749 tmp = start + num_entries;
1750 r = amdgpu_vm_update_ptes(¶ms, start, tmp, addr, flags);
1754 amdgpu_res_next(&cursor, num_entries * AMDGPU_GPU_PAGE_SIZE);
1758 r = vm->update_funcs->commit(¶ms, fence);
1761 *table_freed = *table_freed || params.table_freed;
1764 amdgpu_vm_eviction_unlock(vm);
1769 void amdgpu_vm_get_memory(struct amdgpu_vm *vm, uint64_t *vram_mem,
1770 uint64_t *gtt_mem, uint64_t *cpu_mem)
1772 struct amdgpu_bo_va *bo_va, *tmp;
1774 list_for_each_entry_safe(bo_va, tmp, &vm->idle, base.vm_status) {
1775 if (!bo_va->base.bo)
1777 amdgpu_bo_get_memory(bo_va->base.bo, vram_mem,
1780 list_for_each_entry_safe(bo_va, tmp, &vm->evicted, base.vm_status) {
1781 if (!bo_va->base.bo)
1783 amdgpu_bo_get_memory(bo_va->base.bo, vram_mem,
1786 list_for_each_entry_safe(bo_va, tmp, &vm->relocated, base.vm_status) {
1787 if (!bo_va->base.bo)
1789 amdgpu_bo_get_memory(bo_va->base.bo, vram_mem,
1792 list_for_each_entry_safe(bo_va, tmp, &vm->moved, base.vm_status) {
1793 if (!bo_va->base.bo)
1795 amdgpu_bo_get_memory(bo_va->base.bo, vram_mem,
1798 spin_lock(&vm->invalidated_lock);
1799 list_for_each_entry_safe(bo_va, tmp, &vm->invalidated, base.vm_status) {
1800 if (!bo_va->base.bo)
1802 amdgpu_bo_get_memory(bo_va->base.bo, vram_mem,
1805 list_for_each_entry_safe(bo_va, tmp, &vm->done, base.vm_status) {
1806 if (!bo_va->base.bo)
1808 amdgpu_bo_get_memory(bo_va->base.bo, vram_mem,
1811 spin_unlock(&vm->invalidated_lock);
1814 * amdgpu_vm_bo_update - update all BO mappings in the vm page table
1816 * @adev: amdgpu_device pointer
1817 * @bo_va: requested BO and VM object
1818 * @clear: if true clear the entries
1819 * @table_freed: return true if page table is freed
1821 * Fill in the page table entries for @bo_va.
1824 * 0 for success, -EINVAL for failure.
1826 int amdgpu_vm_bo_update(struct amdgpu_device *adev, struct amdgpu_bo_va *bo_va,
1827 bool clear, bool *table_freed)
1829 struct amdgpu_bo *bo = bo_va->base.bo;
1830 struct amdgpu_vm *vm = bo_va->base.vm;
1831 struct amdgpu_bo_va_mapping *mapping;
1832 dma_addr_t *pages_addr = NULL;
1833 struct ttm_resource *mem;
1834 struct dma_fence **last_update;
1835 struct dma_resv *resv;
1837 struct amdgpu_device *bo_adev = adev;
1842 resv = vm->root.bo->tbo.base.resv;
1844 struct drm_gem_object *obj = &bo->tbo.base;
1846 resv = bo->tbo.base.resv;
1847 if (obj->import_attach && bo_va->is_xgmi) {
1848 struct dma_buf *dma_buf = obj->import_attach->dmabuf;
1849 struct drm_gem_object *gobj = dma_buf->priv;
1850 struct amdgpu_bo *abo = gem_to_amdgpu_bo(gobj);
1852 if (abo->tbo.resource->mem_type == TTM_PL_VRAM)
1853 bo = gem_to_amdgpu_bo(gobj);
1855 mem = bo->tbo.resource;
1856 if (mem->mem_type == TTM_PL_TT ||
1857 mem->mem_type == AMDGPU_PL_PREEMPT)
1858 pages_addr = bo->tbo.ttm->dma_address;
1862 flags = amdgpu_ttm_tt_pte_flags(adev, bo->tbo.ttm, mem);
1864 if (amdgpu_bo_encrypted(bo))
1865 flags |= AMDGPU_PTE_TMZ;
1867 bo_adev = amdgpu_ttm_adev(bo->tbo.bdev);
1872 if (clear || (bo && bo->tbo.base.resv ==
1873 vm->root.bo->tbo.base.resv))
1874 last_update = &vm->last_update;
1876 last_update = &bo_va->last_pt_update;
1878 if (!clear && bo_va->base.moved) {
1879 bo_va->base.moved = false;
1880 list_splice_init(&bo_va->valids, &bo_va->invalids);
1882 } else if (bo_va->cleared != clear) {
1883 list_splice_init(&bo_va->valids, &bo_va->invalids);
1886 list_for_each_entry(mapping, &bo_va->invalids, list) {
1887 uint64_t update_flags = flags;
1889 /* normally,bo_va->flags only contians READABLE and WIRTEABLE bit go here
1890 * but in case of something, we filter the flags in first place
1892 if (!(mapping->flags & AMDGPU_PTE_READABLE))
1893 update_flags &= ~AMDGPU_PTE_READABLE;
1894 if (!(mapping->flags & AMDGPU_PTE_WRITEABLE))
1895 update_flags &= ~AMDGPU_PTE_WRITEABLE;
1897 /* Apply ASIC specific mapping flags */
1898 amdgpu_gmc_get_vm_pte(adev, mapping, &update_flags);
1900 trace_amdgpu_vm_bo_update(mapping);
1902 r = amdgpu_vm_bo_update_mapping(adev, bo_adev, vm, false, false,
1903 resv, mapping->start,
1904 mapping->last, update_flags,
1905 mapping->offset, mem,
1906 pages_addr, last_update, table_freed);
1911 /* If the BO is not in its preferred location add it back to
1912 * the evicted list so that it gets validated again on the
1913 * next command submission.
1915 if (bo && bo->tbo.base.resv == vm->root.bo->tbo.base.resv) {
1916 uint32_t mem_type = bo->tbo.resource->mem_type;
1918 if (!(bo->preferred_domains &
1919 amdgpu_mem_type_to_domain(mem_type)))
1920 amdgpu_vm_bo_evicted(&bo_va->base);
1922 amdgpu_vm_bo_idle(&bo_va->base);
1924 amdgpu_vm_bo_done(&bo_va->base);
1927 list_splice_init(&bo_va->invalids, &bo_va->valids);
1928 bo_va->cleared = clear;
1930 if (trace_amdgpu_vm_bo_mapping_enabled()) {
1931 list_for_each_entry(mapping, &bo_va->valids, list)
1932 trace_amdgpu_vm_bo_mapping(mapping);
1939 * amdgpu_vm_update_prt_state - update the global PRT state
1941 * @adev: amdgpu_device pointer
1943 static void amdgpu_vm_update_prt_state(struct amdgpu_device *adev)
1945 unsigned long flags;
1948 spin_lock_irqsave(&adev->vm_manager.prt_lock, flags);
1949 enable = !!atomic_read(&adev->vm_manager.num_prt_users);
1950 adev->gmc.gmc_funcs->set_prt(adev, enable);
1951 spin_unlock_irqrestore(&adev->vm_manager.prt_lock, flags);
1955 * amdgpu_vm_prt_get - add a PRT user
1957 * @adev: amdgpu_device pointer
1959 static void amdgpu_vm_prt_get(struct amdgpu_device *adev)
1961 if (!adev->gmc.gmc_funcs->set_prt)
1964 if (atomic_inc_return(&adev->vm_manager.num_prt_users) == 1)
1965 amdgpu_vm_update_prt_state(adev);
1969 * amdgpu_vm_prt_put - drop a PRT user
1971 * @adev: amdgpu_device pointer
1973 static void amdgpu_vm_prt_put(struct amdgpu_device *adev)
1975 if (atomic_dec_return(&adev->vm_manager.num_prt_users) == 0)
1976 amdgpu_vm_update_prt_state(adev);
1980 * amdgpu_vm_prt_cb - callback for updating the PRT status
1982 * @fence: fence for the callback
1983 * @_cb: the callback function
1985 static void amdgpu_vm_prt_cb(struct dma_fence *fence, struct dma_fence_cb *_cb)
1987 struct amdgpu_prt_cb *cb = container_of(_cb, struct amdgpu_prt_cb, cb);
1989 amdgpu_vm_prt_put(cb->adev);
1994 * amdgpu_vm_add_prt_cb - add callback for updating the PRT status
1996 * @adev: amdgpu_device pointer
1997 * @fence: fence for the callback
1999 static void amdgpu_vm_add_prt_cb(struct amdgpu_device *adev,
2000 struct dma_fence *fence)
2002 struct amdgpu_prt_cb *cb;
2004 if (!adev->gmc.gmc_funcs->set_prt)
2007 cb = kmalloc(sizeof(struct amdgpu_prt_cb), GFP_KERNEL);
2009 /* Last resort when we are OOM */
2011 dma_fence_wait(fence, false);
2013 amdgpu_vm_prt_put(adev);
2016 if (!fence || dma_fence_add_callback(fence, &cb->cb,
2018 amdgpu_vm_prt_cb(fence, &cb->cb);
2023 * amdgpu_vm_free_mapping - free a mapping
2025 * @adev: amdgpu_device pointer
2027 * @mapping: mapping to be freed
2028 * @fence: fence of the unmap operation
2030 * Free a mapping and make sure we decrease the PRT usage count if applicable.
2032 static void amdgpu_vm_free_mapping(struct amdgpu_device *adev,
2033 struct amdgpu_vm *vm,
2034 struct amdgpu_bo_va_mapping *mapping,
2035 struct dma_fence *fence)
2037 if (mapping->flags & AMDGPU_PTE_PRT)
2038 amdgpu_vm_add_prt_cb(adev, fence);
2043 * amdgpu_vm_prt_fini - finish all prt mappings
2045 * @adev: amdgpu_device pointer
2048 * Register a cleanup callback to disable PRT support after VM dies.
2050 static void amdgpu_vm_prt_fini(struct amdgpu_device *adev, struct amdgpu_vm *vm)
2052 struct dma_resv *resv = vm->root.bo->tbo.base.resv;
2053 struct dma_fence *excl, **shared;
2054 unsigned i, shared_count;
2057 r = dma_resv_get_fences(resv, &excl, &shared_count, &shared);
2059 /* Not enough memory to grab the fence list, as last resort
2060 * block for all the fences to complete.
2062 dma_resv_wait_timeout(resv, true, false,
2063 MAX_SCHEDULE_TIMEOUT);
2067 /* Add a callback for each fence in the reservation object */
2068 amdgpu_vm_prt_get(adev);
2069 amdgpu_vm_add_prt_cb(adev, excl);
2071 for (i = 0; i < shared_count; ++i) {
2072 amdgpu_vm_prt_get(adev);
2073 amdgpu_vm_add_prt_cb(adev, shared[i]);
2080 * amdgpu_vm_clear_freed - clear freed BOs in the PT
2082 * @adev: amdgpu_device pointer
2084 * @fence: optional resulting fence (unchanged if no work needed to be done
2085 * or if an error occurred)
2087 * Make sure all freed BOs are cleared in the PT.
2088 * PTs have to be reserved and mutex must be locked!
2094 int amdgpu_vm_clear_freed(struct amdgpu_device *adev,
2095 struct amdgpu_vm *vm,
2096 struct dma_fence **fence)
2098 struct dma_resv *resv = vm->root.bo->tbo.base.resv;
2099 struct amdgpu_bo_va_mapping *mapping;
2100 uint64_t init_pte_value = 0;
2101 struct dma_fence *f = NULL;
2104 while (!list_empty(&vm->freed)) {
2105 mapping = list_first_entry(&vm->freed,
2106 struct amdgpu_bo_va_mapping, list);
2107 list_del(&mapping->list);
2109 if (vm->pte_support_ats &&
2110 mapping->start < AMDGPU_GMC_HOLE_START)
2111 init_pte_value = AMDGPU_PTE_DEFAULT_ATC;
2113 r = amdgpu_vm_bo_update_mapping(adev, adev, vm, false, false,
2114 resv, mapping->start,
2115 mapping->last, init_pte_value,
2116 0, NULL, NULL, &f, NULL);
2117 amdgpu_vm_free_mapping(adev, vm, mapping, f);
2125 dma_fence_put(*fence);
2136 * amdgpu_vm_handle_moved - handle moved BOs in the PT
2138 * @adev: amdgpu_device pointer
2141 * Make sure all BOs which are moved are updated in the PTs.
2146 * PTs have to be reserved!
2148 int amdgpu_vm_handle_moved(struct amdgpu_device *adev,
2149 struct amdgpu_vm *vm)
2151 struct amdgpu_bo_va *bo_va, *tmp;
2152 struct dma_resv *resv;
2156 list_for_each_entry_safe(bo_va, tmp, &vm->moved, base.vm_status) {
2157 /* Per VM BOs never need to bo cleared in the page tables */
2158 r = amdgpu_vm_bo_update(adev, bo_va, false, NULL);
2163 spin_lock(&vm->invalidated_lock);
2164 while (!list_empty(&vm->invalidated)) {
2165 bo_va = list_first_entry(&vm->invalidated, struct amdgpu_bo_va,
2167 resv = bo_va->base.bo->tbo.base.resv;
2168 spin_unlock(&vm->invalidated_lock);
2170 /* Try to reserve the BO to avoid clearing its ptes */
2171 if (!amdgpu_vm_debug && dma_resv_trylock(resv))
2173 /* Somebody else is using the BO right now */
2177 r = amdgpu_vm_bo_update(adev, bo_va, clear, NULL);
2182 dma_resv_unlock(resv);
2183 spin_lock(&vm->invalidated_lock);
2185 spin_unlock(&vm->invalidated_lock);
2191 * amdgpu_vm_bo_add - add a bo to a specific vm
2193 * @adev: amdgpu_device pointer
2195 * @bo: amdgpu buffer object
2197 * Add @bo into the requested vm.
2198 * Add @bo to the list of bos associated with the vm
2201 * Newly added bo_va or NULL for failure
2203 * Object has to be reserved!
2205 struct amdgpu_bo_va *amdgpu_vm_bo_add(struct amdgpu_device *adev,
2206 struct amdgpu_vm *vm,
2207 struct amdgpu_bo *bo)
2209 struct amdgpu_bo_va *bo_va;
2211 bo_va = kzalloc(sizeof(struct amdgpu_bo_va), GFP_KERNEL);
2212 if (bo_va == NULL) {
2215 amdgpu_vm_bo_base_init(&bo_va->base, vm, bo);
2217 bo_va->ref_count = 1;
2218 INIT_LIST_HEAD(&bo_va->valids);
2219 INIT_LIST_HEAD(&bo_va->invalids);
2224 if (amdgpu_dmabuf_is_xgmi_accessible(adev, bo)) {
2225 bo_va->is_xgmi = true;
2226 /* Power up XGMI if it can be potentially used */
2227 amdgpu_xgmi_set_pstate(adev, AMDGPU_XGMI_PSTATE_MAX_VEGA20);
2235 * amdgpu_vm_bo_insert_map - insert a new mapping
2237 * @adev: amdgpu_device pointer
2238 * @bo_va: bo_va to store the address
2239 * @mapping: the mapping to insert
2241 * Insert a new mapping into all structures.
2243 static void amdgpu_vm_bo_insert_map(struct amdgpu_device *adev,
2244 struct amdgpu_bo_va *bo_va,
2245 struct amdgpu_bo_va_mapping *mapping)
2247 struct amdgpu_vm *vm = bo_va->base.vm;
2248 struct amdgpu_bo *bo = bo_va->base.bo;
2250 mapping->bo_va = bo_va;
2251 list_add(&mapping->list, &bo_va->invalids);
2252 amdgpu_vm_it_insert(mapping, &vm->va);
2254 if (mapping->flags & AMDGPU_PTE_PRT)
2255 amdgpu_vm_prt_get(adev);
2257 if (bo && bo->tbo.base.resv == vm->root.bo->tbo.base.resv &&
2258 !bo_va->base.moved) {
2259 list_move(&bo_va->base.vm_status, &vm->moved);
2261 trace_amdgpu_vm_bo_map(bo_va, mapping);
2265 * amdgpu_vm_bo_map - map bo inside a vm
2267 * @adev: amdgpu_device pointer
2268 * @bo_va: bo_va to store the address
2269 * @saddr: where to map the BO
2270 * @offset: requested offset in the BO
2271 * @size: BO size in bytes
2272 * @flags: attributes of pages (read/write/valid/etc.)
2274 * Add a mapping of the BO at the specefied addr into the VM.
2277 * 0 for success, error for failure.
2279 * Object has to be reserved and unreserved outside!
2281 int amdgpu_vm_bo_map(struct amdgpu_device *adev,
2282 struct amdgpu_bo_va *bo_va,
2283 uint64_t saddr, uint64_t offset,
2284 uint64_t size, uint64_t flags)
2286 struct amdgpu_bo_va_mapping *mapping, *tmp;
2287 struct amdgpu_bo *bo = bo_va->base.bo;
2288 struct amdgpu_vm *vm = bo_va->base.vm;
2291 /* validate the parameters */
2292 if (saddr & ~PAGE_MASK || offset & ~PAGE_MASK ||
2293 size == 0 || size & ~PAGE_MASK)
2296 /* make sure object fit at this offset */
2297 eaddr = saddr + size - 1;
2298 if (saddr >= eaddr ||
2299 (bo && offset + size > amdgpu_bo_size(bo)) ||
2300 (eaddr >= adev->vm_manager.max_pfn << AMDGPU_GPU_PAGE_SHIFT))
2303 saddr /= AMDGPU_GPU_PAGE_SIZE;
2304 eaddr /= AMDGPU_GPU_PAGE_SIZE;
2306 tmp = amdgpu_vm_it_iter_first(&vm->va, saddr, eaddr);
2308 /* bo and tmp overlap, invalid addr */
2309 dev_err(adev->dev, "bo %p va 0x%010Lx-0x%010Lx conflict with "
2310 "0x%010Lx-0x%010Lx\n", bo, saddr, eaddr,
2311 tmp->start, tmp->last + 1);
2315 mapping = kmalloc(sizeof(*mapping), GFP_KERNEL);
2319 mapping->start = saddr;
2320 mapping->last = eaddr;
2321 mapping->offset = offset;
2322 mapping->flags = flags;
2324 amdgpu_vm_bo_insert_map(adev, bo_va, mapping);
2330 * amdgpu_vm_bo_replace_map - map bo inside a vm, replacing existing mappings
2332 * @adev: amdgpu_device pointer
2333 * @bo_va: bo_va to store the address
2334 * @saddr: where to map the BO
2335 * @offset: requested offset in the BO
2336 * @size: BO size in bytes
2337 * @flags: attributes of pages (read/write/valid/etc.)
2339 * Add a mapping of the BO at the specefied addr into the VM. Replace existing
2340 * mappings as we do so.
2343 * 0 for success, error for failure.
2345 * Object has to be reserved and unreserved outside!
2347 int amdgpu_vm_bo_replace_map(struct amdgpu_device *adev,
2348 struct amdgpu_bo_va *bo_va,
2349 uint64_t saddr, uint64_t offset,
2350 uint64_t size, uint64_t flags)
2352 struct amdgpu_bo_va_mapping *mapping;
2353 struct amdgpu_bo *bo = bo_va->base.bo;
2357 /* validate the parameters */
2358 if (saddr & ~PAGE_MASK || offset & ~PAGE_MASK ||
2359 size == 0 || size & ~PAGE_MASK)
2362 /* make sure object fit at this offset */
2363 eaddr = saddr + size - 1;
2364 if (saddr >= eaddr ||
2365 (bo && offset + size > amdgpu_bo_size(bo)) ||
2366 (eaddr >= adev->vm_manager.max_pfn << AMDGPU_GPU_PAGE_SHIFT))
2369 /* Allocate all the needed memory */
2370 mapping = kmalloc(sizeof(*mapping), GFP_KERNEL);
2374 r = amdgpu_vm_bo_clear_mappings(adev, bo_va->base.vm, saddr, size);
2380 saddr /= AMDGPU_GPU_PAGE_SIZE;
2381 eaddr /= AMDGPU_GPU_PAGE_SIZE;
2383 mapping->start = saddr;
2384 mapping->last = eaddr;
2385 mapping->offset = offset;
2386 mapping->flags = flags;
2388 amdgpu_vm_bo_insert_map(adev, bo_va, mapping);
2394 * amdgpu_vm_bo_unmap - remove bo mapping from vm
2396 * @adev: amdgpu_device pointer
2397 * @bo_va: bo_va to remove the address from
2398 * @saddr: where to the BO is mapped
2400 * Remove a mapping of the BO at the specefied addr from the VM.
2403 * 0 for success, error for failure.
2405 * Object has to be reserved and unreserved outside!
2407 int amdgpu_vm_bo_unmap(struct amdgpu_device *adev,
2408 struct amdgpu_bo_va *bo_va,
2411 struct amdgpu_bo_va_mapping *mapping;
2412 struct amdgpu_vm *vm = bo_va->base.vm;
2415 saddr /= AMDGPU_GPU_PAGE_SIZE;
2417 list_for_each_entry(mapping, &bo_va->valids, list) {
2418 if (mapping->start == saddr)
2422 if (&mapping->list == &bo_va->valids) {
2425 list_for_each_entry(mapping, &bo_va->invalids, list) {
2426 if (mapping->start == saddr)
2430 if (&mapping->list == &bo_va->invalids)
2434 list_del(&mapping->list);
2435 amdgpu_vm_it_remove(mapping, &vm->va);
2436 mapping->bo_va = NULL;
2437 trace_amdgpu_vm_bo_unmap(bo_va, mapping);
2440 list_add(&mapping->list, &vm->freed);
2442 amdgpu_vm_free_mapping(adev, vm, mapping,
2443 bo_va->last_pt_update);
2449 * amdgpu_vm_bo_clear_mappings - remove all mappings in a specific range
2451 * @adev: amdgpu_device pointer
2452 * @vm: VM structure to use
2453 * @saddr: start of the range
2454 * @size: size of the range
2456 * Remove all mappings in a range, split them as appropriate.
2459 * 0 for success, error for failure.
2461 int amdgpu_vm_bo_clear_mappings(struct amdgpu_device *adev,
2462 struct amdgpu_vm *vm,
2463 uint64_t saddr, uint64_t size)
2465 struct amdgpu_bo_va_mapping *before, *after, *tmp, *next;
2469 eaddr = saddr + size - 1;
2470 saddr /= AMDGPU_GPU_PAGE_SIZE;
2471 eaddr /= AMDGPU_GPU_PAGE_SIZE;
2473 /* Allocate all the needed memory */
2474 before = kzalloc(sizeof(*before), GFP_KERNEL);
2477 INIT_LIST_HEAD(&before->list);
2479 after = kzalloc(sizeof(*after), GFP_KERNEL);
2484 INIT_LIST_HEAD(&after->list);
2486 /* Now gather all removed mappings */
2487 tmp = amdgpu_vm_it_iter_first(&vm->va, saddr, eaddr);
2489 /* Remember mapping split at the start */
2490 if (tmp->start < saddr) {
2491 before->start = tmp->start;
2492 before->last = saddr - 1;
2493 before->offset = tmp->offset;
2494 before->flags = tmp->flags;
2495 before->bo_va = tmp->bo_va;
2496 list_add(&before->list, &tmp->bo_va->invalids);
2499 /* Remember mapping split at the end */
2500 if (tmp->last > eaddr) {
2501 after->start = eaddr + 1;
2502 after->last = tmp->last;
2503 after->offset = tmp->offset;
2504 after->offset += (after->start - tmp->start) << PAGE_SHIFT;
2505 after->flags = tmp->flags;
2506 after->bo_va = tmp->bo_va;
2507 list_add(&after->list, &tmp->bo_va->invalids);
2510 list_del(&tmp->list);
2511 list_add(&tmp->list, &removed);
2513 tmp = amdgpu_vm_it_iter_next(tmp, saddr, eaddr);
2516 /* And free them up */
2517 list_for_each_entry_safe(tmp, next, &removed, list) {
2518 amdgpu_vm_it_remove(tmp, &vm->va);
2519 list_del(&tmp->list);
2521 if (tmp->start < saddr)
2523 if (tmp->last > eaddr)
2527 list_add(&tmp->list, &vm->freed);
2528 trace_amdgpu_vm_bo_unmap(NULL, tmp);
2531 /* Insert partial mapping before the range */
2532 if (!list_empty(&before->list)) {
2533 amdgpu_vm_it_insert(before, &vm->va);
2534 if (before->flags & AMDGPU_PTE_PRT)
2535 amdgpu_vm_prt_get(adev);
2540 /* Insert partial mapping after the range */
2541 if (!list_empty(&after->list)) {
2542 amdgpu_vm_it_insert(after, &vm->va);
2543 if (after->flags & AMDGPU_PTE_PRT)
2544 amdgpu_vm_prt_get(adev);
2553 * amdgpu_vm_bo_lookup_mapping - find mapping by address
2555 * @vm: the requested VM
2556 * @addr: the address
2558 * Find a mapping by it's address.
2561 * The amdgpu_bo_va_mapping matching for addr or NULL
2564 struct amdgpu_bo_va_mapping *amdgpu_vm_bo_lookup_mapping(struct amdgpu_vm *vm,
2567 return amdgpu_vm_it_iter_first(&vm->va, addr, addr);
2571 * amdgpu_vm_bo_trace_cs - trace all reserved mappings
2573 * @vm: the requested vm
2574 * @ticket: CS ticket
2576 * Trace all mappings of BOs reserved during a command submission.
2578 void amdgpu_vm_bo_trace_cs(struct amdgpu_vm *vm, struct ww_acquire_ctx *ticket)
2580 struct amdgpu_bo_va_mapping *mapping;
2582 if (!trace_amdgpu_vm_bo_cs_enabled())
2585 for (mapping = amdgpu_vm_it_iter_first(&vm->va, 0, U64_MAX); mapping;
2586 mapping = amdgpu_vm_it_iter_next(mapping, 0, U64_MAX)) {
2587 if (mapping->bo_va && mapping->bo_va->base.bo) {
2588 struct amdgpu_bo *bo;
2590 bo = mapping->bo_va->base.bo;
2591 if (dma_resv_locking_ctx(bo->tbo.base.resv) !=
2596 trace_amdgpu_vm_bo_cs(mapping);
2601 * amdgpu_vm_bo_rmv - remove a bo to a specific vm
2603 * @adev: amdgpu_device pointer
2604 * @bo_va: requested bo_va
2606 * Remove @bo_va->bo from the requested vm.
2608 * Object have to be reserved!
2610 void amdgpu_vm_bo_rmv(struct amdgpu_device *adev,
2611 struct amdgpu_bo_va *bo_va)
2613 struct amdgpu_bo_va_mapping *mapping, *next;
2614 struct amdgpu_bo *bo = bo_va->base.bo;
2615 struct amdgpu_vm *vm = bo_va->base.vm;
2616 struct amdgpu_vm_bo_base **base;
2619 if (bo->tbo.base.resv == vm->root.bo->tbo.base.resv)
2620 vm->bulk_moveable = false;
2622 for (base = &bo_va->base.bo->vm_bo; *base;
2623 base = &(*base)->next) {
2624 if (*base != &bo_va->base)
2627 *base = bo_va->base.next;
2632 spin_lock(&vm->invalidated_lock);
2633 list_del(&bo_va->base.vm_status);
2634 spin_unlock(&vm->invalidated_lock);
2636 list_for_each_entry_safe(mapping, next, &bo_va->valids, list) {
2637 list_del(&mapping->list);
2638 amdgpu_vm_it_remove(mapping, &vm->va);
2639 mapping->bo_va = NULL;
2640 trace_amdgpu_vm_bo_unmap(bo_va, mapping);
2641 list_add(&mapping->list, &vm->freed);
2643 list_for_each_entry_safe(mapping, next, &bo_va->invalids, list) {
2644 list_del(&mapping->list);
2645 amdgpu_vm_it_remove(mapping, &vm->va);
2646 amdgpu_vm_free_mapping(adev, vm, mapping,
2647 bo_va->last_pt_update);
2650 dma_fence_put(bo_va->last_pt_update);
2652 if (bo && bo_va->is_xgmi)
2653 amdgpu_xgmi_set_pstate(adev, AMDGPU_XGMI_PSTATE_MIN);
2659 * amdgpu_vm_evictable - check if we can evict a VM
2661 * @bo: A page table of the VM.
2663 * Check if it is possible to evict a VM.
2665 bool amdgpu_vm_evictable(struct amdgpu_bo *bo)
2667 struct amdgpu_vm_bo_base *bo_base = bo->vm_bo;
2669 /* Page tables of a destroyed VM can go away immediately */
2670 if (!bo_base || !bo_base->vm)
2673 /* Don't evict VM page tables while they are busy */
2674 if (!dma_resv_test_signaled(bo->tbo.base.resv, true))
2677 /* Try to block ongoing updates */
2678 if (!amdgpu_vm_eviction_trylock(bo_base->vm))
2681 /* Don't evict VM page tables while they are updated */
2682 if (!dma_fence_is_signaled(bo_base->vm->last_unlocked)) {
2683 amdgpu_vm_eviction_unlock(bo_base->vm);
2687 bo_base->vm->evicting = true;
2688 amdgpu_vm_eviction_unlock(bo_base->vm);
2693 * amdgpu_vm_bo_invalidate - mark the bo as invalid
2695 * @adev: amdgpu_device pointer
2696 * @bo: amdgpu buffer object
2697 * @evicted: is the BO evicted
2699 * Mark @bo as invalid.
2701 void amdgpu_vm_bo_invalidate(struct amdgpu_device *adev,
2702 struct amdgpu_bo *bo, bool evicted)
2704 struct amdgpu_vm_bo_base *bo_base;
2706 /* shadow bo doesn't have bo base, its validation needs its parent */
2707 if (bo->parent && (amdgpu_bo_shadowed(bo->parent) == bo))
2710 for (bo_base = bo->vm_bo; bo_base; bo_base = bo_base->next) {
2711 struct amdgpu_vm *vm = bo_base->vm;
2713 if (evicted && bo->tbo.base.resv == vm->root.bo->tbo.base.resv) {
2714 amdgpu_vm_bo_evicted(bo_base);
2720 bo_base->moved = true;
2722 if (bo->tbo.type == ttm_bo_type_kernel)
2723 amdgpu_vm_bo_relocated(bo_base);
2724 else if (bo->tbo.base.resv == vm->root.bo->tbo.base.resv)
2725 amdgpu_vm_bo_moved(bo_base);
2727 amdgpu_vm_bo_invalidated(bo_base);
2732 * amdgpu_vm_get_block_size - calculate VM page table size as power of two
2737 * VM page table as power of two
2739 static uint32_t amdgpu_vm_get_block_size(uint64_t vm_size)
2741 /* Total bits covered by PD + PTs */
2742 unsigned bits = ilog2(vm_size) + 18;
2744 /* Make sure the PD is 4K in size up to 8GB address space.
2745 Above that split equal between PD and PTs */
2749 return ((bits + 3) / 2);
2753 * amdgpu_vm_adjust_size - adjust vm size, block size and fragment size
2755 * @adev: amdgpu_device pointer
2756 * @min_vm_size: the minimum vm size in GB if it's set auto
2757 * @fragment_size_default: Default PTE fragment size
2758 * @max_level: max VMPT level
2759 * @max_bits: max address space size in bits
2762 void amdgpu_vm_adjust_size(struct amdgpu_device *adev, uint32_t min_vm_size,
2763 uint32_t fragment_size_default, unsigned max_level,
2766 unsigned int max_size = 1 << (max_bits - 30);
2767 unsigned int vm_size;
2770 /* adjust vm size first */
2771 if (amdgpu_vm_size != -1) {
2772 vm_size = amdgpu_vm_size;
2773 if (vm_size > max_size) {
2774 dev_warn(adev->dev, "VM size (%d) too large, max is %u GB\n",
2775 amdgpu_vm_size, max_size);
2780 unsigned int phys_ram_gb;
2782 /* Optimal VM size depends on the amount of physical
2783 * RAM available. Underlying requirements and
2786 * - Need to map system memory and VRAM from all GPUs
2787 * - VRAM from other GPUs not known here
2788 * - Assume VRAM <= system memory
2789 * - On GFX8 and older, VM space can be segmented for
2791 * - Need to allow room for fragmentation, guard pages etc.
2793 * This adds up to a rough guess of system memory x3.
2794 * Round up to power of two to maximize the available
2795 * VM size with the given page table size.
2798 phys_ram_gb = ((uint64_t)si.totalram * si.mem_unit +
2799 (1 << 30) - 1) >> 30;
2800 vm_size = roundup_pow_of_two(
2801 min(max(phys_ram_gb * 3, min_vm_size), max_size));
2804 adev->vm_manager.max_pfn = (uint64_t)vm_size << 18;
2806 tmp = roundup_pow_of_two(adev->vm_manager.max_pfn);
2807 if (amdgpu_vm_block_size != -1)
2808 tmp >>= amdgpu_vm_block_size - 9;
2809 tmp = DIV_ROUND_UP(fls64(tmp) - 1, 9) - 1;
2810 adev->vm_manager.num_level = min(max_level, (unsigned)tmp);
2811 switch (adev->vm_manager.num_level) {
2813 adev->vm_manager.root_level = AMDGPU_VM_PDB2;
2816 adev->vm_manager.root_level = AMDGPU_VM_PDB1;
2819 adev->vm_manager.root_level = AMDGPU_VM_PDB0;
2822 dev_err(adev->dev, "VMPT only supports 2~4+1 levels\n");
2824 /* block size depends on vm size and hw setup*/
2825 if (amdgpu_vm_block_size != -1)
2826 adev->vm_manager.block_size =
2827 min((unsigned)amdgpu_vm_block_size, max_bits
2828 - AMDGPU_GPU_PAGE_SHIFT
2829 - 9 * adev->vm_manager.num_level);
2830 else if (adev->vm_manager.num_level > 1)
2831 adev->vm_manager.block_size = 9;
2833 adev->vm_manager.block_size = amdgpu_vm_get_block_size(tmp);
2835 if (amdgpu_vm_fragment_size == -1)
2836 adev->vm_manager.fragment_size = fragment_size_default;
2838 adev->vm_manager.fragment_size = amdgpu_vm_fragment_size;
2840 DRM_INFO("vm size is %u GB, %u levels, block size is %u-bit, fragment size is %u-bit\n",
2841 vm_size, adev->vm_manager.num_level + 1,
2842 adev->vm_manager.block_size,
2843 adev->vm_manager.fragment_size);
2847 * amdgpu_vm_wait_idle - wait for the VM to become idle
2849 * @vm: VM object to wait for
2850 * @timeout: timeout to wait for VM to become idle
2852 long amdgpu_vm_wait_idle(struct amdgpu_vm *vm, long timeout)
2854 timeout = dma_resv_wait_timeout(vm->root.bo->tbo.base.resv, true,
2859 return dma_fence_wait_timeout(vm->last_unlocked, true, timeout);
2863 * amdgpu_vm_init - initialize a vm instance
2865 * @adev: amdgpu_device pointer
2867 * @pasid: Process address space identifier
2872 * 0 for success, error for failure.
2874 int amdgpu_vm_init(struct amdgpu_device *adev, struct amdgpu_vm *vm, u32 pasid)
2876 struct amdgpu_bo *root_bo;
2877 struct amdgpu_bo_vm *root;
2880 vm->va = RB_ROOT_CACHED;
2881 for (i = 0; i < AMDGPU_MAX_VMHUBS; i++)
2882 vm->reserved_vmid[i] = NULL;
2883 INIT_LIST_HEAD(&vm->evicted);
2884 INIT_LIST_HEAD(&vm->relocated);
2885 INIT_LIST_HEAD(&vm->moved);
2886 INIT_LIST_HEAD(&vm->idle);
2887 INIT_LIST_HEAD(&vm->invalidated);
2888 spin_lock_init(&vm->invalidated_lock);
2889 INIT_LIST_HEAD(&vm->freed);
2890 INIT_LIST_HEAD(&vm->done);
2892 /* create scheduler entities for page table updates */
2893 r = drm_sched_entity_init(&vm->immediate, DRM_SCHED_PRIORITY_NORMAL,
2894 adev->vm_manager.vm_pte_scheds,
2895 adev->vm_manager.vm_pte_num_scheds, NULL);
2899 r = drm_sched_entity_init(&vm->delayed, DRM_SCHED_PRIORITY_NORMAL,
2900 adev->vm_manager.vm_pte_scheds,
2901 adev->vm_manager.vm_pte_num_scheds, NULL);
2903 goto error_free_immediate;
2905 vm->pte_support_ats = false;
2906 vm->is_compute_context = false;
2908 vm->use_cpu_for_update = !!(adev->vm_manager.vm_update_mode &
2909 AMDGPU_VM_USE_CPU_FOR_GFX);
2911 DRM_DEBUG_DRIVER("VM update mode is %s\n",
2912 vm->use_cpu_for_update ? "CPU" : "SDMA");
2913 WARN_ONCE((vm->use_cpu_for_update &&
2914 !amdgpu_gmc_vram_full_visible(&adev->gmc)),
2915 "CPU update of VM recommended only for large BAR system\n");
2917 if (vm->use_cpu_for_update)
2918 vm->update_funcs = &amdgpu_vm_cpu_funcs;
2920 vm->update_funcs = &amdgpu_vm_sdma_funcs;
2921 vm->last_update = NULL;
2922 vm->last_unlocked = dma_fence_get_stub();
2924 mutex_init(&vm->eviction_lock);
2925 vm->evicting = false;
2927 r = amdgpu_vm_pt_create(adev, vm, adev->vm_manager.root_level,
2930 goto error_free_delayed;
2931 root_bo = &root->bo;
2932 r = amdgpu_bo_reserve(root_bo, true);
2934 goto error_free_root;
2936 r = dma_resv_reserve_shared(root_bo->tbo.base.resv, 1);
2938 goto error_unreserve;
2940 amdgpu_vm_bo_base_init(&vm->root, vm, root_bo);
2942 r = amdgpu_vm_clear_bo(adev, vm, root, false);
2944 goto error_unreserve;
2946 amdgpu_bo_unreserve(vm->root.bo);
2949 unsigned long flags;
2951 spin_lock_irqsave(&adev->vm_manager.pasid_lock, flags);
2952 r = idr_alloc(&adev->vm_manager.pasid_idr, vm, pasid, pasid + 1,
2954 spin_unlock_irqrestore(&adev->vm_manager.pasid_lock, flags);
2956 goto error_free_root;
2961 INIT_KFIFO(vm->faults);
2966 amdgpu_bo_unreserve(vm->root.bo);
2969 amdgpu_bo_unref(&root->shadow);
2970 amdgpu_bo_unref(&root_bo);
2974 dma_fence_put(vm->last_unlocked);
2975 drm_sched_entity_destroy(&vm->delayed);
2977 error_free_immediate:
2978 drm_sched_entity_destroy(&vm->immediate);
2984 * amdgpu_vm_check_clean_reserved - check if a VM is clean
2986 * @adev: amdgpu_device pointer
2987 * @vm: the VM to check
2989 * check all entries of the root PD, if any subsequent PDs are allocated,
2990 * it means there are page table creating and filling, and is no a clean
2994 * 0 if this VM is clean
2996 static int amdgpu_vm_check_clean_reserved(struct amdgpu_device *adev,
2997 struct amdgpu_vm *vm)
2999 enum amdgpu_vm_level root = adev->vm_manager.root_level;
3000 unsigned int entries = amdgpu_vm_num_entries(adev, root);
3003 for (i = 0; i < entries; i++) {
3004 if (to_amdgpu_bo_vm(vm->root.bo)->entries[i].bo)
3012 * amdgpu_vm_make_compute - Turn a GFX VM into a compute VM
3014 * @adev: amdgpu_device pointer
3016 * @pasid: pasid to use
3018 * This only works on GFX VMs that don't have any BOs added and no
3019 * page tables allocated yet.
3021 * Changes the following VM parameters:
3022 * - use_cpu_for_update
3023 * - pte_supports_ats
3024 * - pasid (old PASID is released, because compute manages its own PASIDs)
3026 * Reinitializes the page directory to reflect the changed ATS
3030 * 0 for success, -errno for errors.
3032 int amdgpu_vm_make_compute(struct amdgpu_device *adev, struct amdgpu_vm *vm,
3035 bool pte_support_ats = (adev->asic_type == CHIP_RAVEN);
3038 r = amdgpu_bo_reserve(vm->root.bo, true);
3043 r = amdgpu_vm_check_clean_reserved(adev, vm);
3048 unsigned long flags;
3050 spin_lock_irqsave(&adev->vm_manager.pasid_lock, flags);
3051 r = idr_alloc(&adev->vm_manager.pasid_idr, vm, pasid, pasid + 1,
3053 spin_unlock_irqrestore(&adev->vm_manager.pasid_lock, flags);
3060 /* Check if PD needs to be reinitialized and do it before
3061 * changing any other state, in case it fails.
3063 if (pte_support_ats != vm->pte_support_ats) {
3064 vm->pte_support_ats = pte_support_ats;
3065 r = amdgpu_vm_clear_bo(adev, vm,
3066 to_amdgpu_bo_vm(vm->root.bo),
3072 /* Update VM state */
3073 vm->use_cpu_for_update = !!(adev->vm_manager.vm_update_mode &
3074 AMDGPU_VM_USE_CPU_FOR_COMPUTE);
3075 DRM_DEBUG_DRIVER("VM update mode is %s\n",
3076 vm->use_cpu_for_update ? "CPU" : "SDMA");
3077 WARN_ONCE((vm->use_cpu_for_update &&
3078 !amdgpu_gmc_vram_full_visible(&adev->gmc)),
3079 "CPU update of VM recommended only for large BAR system\n");
3081 if (vm->use_cpu_for_update) {
3082 /* Sync with last SDMA update/clear before switching to CPU */
3083 r = amdgpu_bo_sync_wait(vm->root.bo,
3084 AMDGPU_FENCE_OWNER_UNDEFINED, true);
3088 vm->update_funcs = &amdgpu_vm_cpu_funcs;
3090 vm->update_funcs = &amdgpu_vm_sdma_funcs;
3092 dma_fence_put(vm->last_update);
3093 vm->last_update = NULL;
3094 vm->is_compute_context = true;
3097 unsigned long flags;
3099 spin_lock_irqsave(&adev->vm_manager.pasid_lock, flags);
3100 idr_remove(&adev->vm_manager.pasid_idr, vm->pasid);
3101 spin_unlock_irqrestore(&adev->vm_manager.pasid_lock, flags);
3103 /* Free the original amdgpu allocated pasid
3104 * Will be replaced with kfd allocated pasid
3106 amdgpu_pasid_free(vm->pasid);
3110 /* Free the shadow bo for compute VM */
3111 amdgpu_bo_unref(&to_amdgpu_bo_vm(vm->root.bo)->shadow);
3120 unsigned long flags;
3122 spin_lock_irqsave(&adev->vm_manager.pasid_lock, flags);
3123 idr_remove(&adev->vm_manager.pasid_idr, pasid);
3124 spin_unlock_irqrestore(&adev->vm_manager.pasid_lock, flags);
3127 amdgpu_bo_unreserve(vm->root.bo);
3132 * amdgpu_vm_release_compute - release a compute vm
3133 * @adev: amdgpu_device pointer
3134 * @vm: a vm turned into compute vm by calling amdgpu_vm_make_compute
3136 * This is a correspondant of amdgpu_vm_make_compute. It decouples compute
3137 * pasid from vm. Compute should stop use of vm after this call.
3139 void amdgpu_vm_release_compute(struct amdgpu_device *adev, struct amdgpu_vm *vm)
3142 unsigned long flags;
3144 spin_lock_irqsave(&adev->vm_manager.pasid_lock, flags);
3145 idr_remove(&adev->vm_manager.pasid_idr, vm->pasid);
3146 spin_unlock_irqrestore(&adev->vm_manager.pasid_lock, flags);
3149 vm->is_compute_context = false;
3153 * amdgpu_vm_fini - tear down a vm instance
3155 * @adev: amdgpu_device pointer
3159 * Unbind the VM and remove all bos from the vm bo list
3161 void amdgpu_vm_fini(struct amdgpu_device *adev, struct amdgpu_vm *vm)
3163 struct amdgpu_bo_va_mapping *mapping, *tmp;
3164 bool prt_fini_needed = !!adev->gmc.gmc_funcs->set_prt;
3165 struct amdgpu_bo *root;
3168 amdgpu_amdkfd_gpuvm_destroy_cb(adev, vm);
3170 root = amdgpu_bo_ref(vm->root.bo);
3171 amdgpu_bo_reserve(root, true);
3173 unsigned long flags;
3175 spin_lock_irqsave(&adev->vm_manager.pasid_lock, flags);
3176 idr_remove(&adev->vm_manager.pasid_idr, vm->pasid);
3177 spin_unlock_irqrestore(&adev->vm_manager.pasid_lock, flags);
3181 dma_fence_wait(vm->last_unlocked, false);
3182 dma_fence_put(vm->last_unlocked);
3184 list_for_each_entry_safe(mapping, tmp, &vm->freed, list) {
3185 if (mapping->flags & AMDGPU_PTE_PRT && prt_fini_needed) {
3186 amdgpu_vm_prt_fini(adev, vm);
3187 prt_fini_needed = false;
3190 list_del(&mapping->list);
3191 amdgpu_vm_free_mapping(adev, vm, mapping, NULL);
3194 amdgpu_vm_free_pts(adev, vm, NULL);
3195 amdgpu_bo_unreserve(root);
3196 amdgpu_bo_unref(&root);
3197 WARN_ON(vm->root.bo);
3199 drm_sched_entity_destroy(&vm->immediate);
3200 drm_sched_entity_destroy(&vm->delayed);
3202 if (!RB_EMPTY_ROOT(&vm->va.rb_root)) {
3203 dev_err(adev->dev, "still active bo inside vm\n");
3205 rbtree_postorder_for_each_entry_safe(mapping, tmp,
3206 &vm->va.rb_root, rb) {
3207 /* Don't remove the mapping here, we don't want to trigger a
3208 * rebalance and the tree is about to be destroyed anyway.
3210 list_del(&mapping->list);
3214 dma_fence_put(vm->last_update);
3215 for (i = 0; i < AMDGPU_MAX_VMHUBS; i++)
3216 amdgpu_vmid_free_reserved(adev, vm, i);
3220 * amdgpu_vm_manager_init - init the VM manager
3222 * @adev: amdgpu_device pointer
3224 * Initialize the VM manager structures
3226 void amdgpu_vm_manager_init(struct amdgpu_device *adev)
3230 /* Concurrent flushes are only possible starting with Vega10 and
3231 * are broken on Navi10 and Navi14.
3233 adev->vm_manager.concurrent_flush = !(adev->asic_type < CHIP_VEGA10 ||
3234 adev->asic_type == CHIP_NAVI10 ||
3235 adev->asic_type == CHIP_NAVI14);
3236 amdgpu_vmid_mgr_init(adev);
3238 adev->vm_manager.fence_context =
3239 dma_fence_context_alloc(AMDGPU_MAX_RINGS);
3240 for (i = 0; i < AMDGPU_MAX_RINGS; ++i)
3241 adev->vm_manager.seqno[i] = 0;
3243 spin_lock_init(&adev->vm_manager.prt_lock);
3244 atomic_set(&adev->vm_manager.num_prt_users, 0);
3246 /* If not overridden by the user, by default, only in large BAR systems
3247 * Compute VM tables will be updated by CPU
3249 #ifdef CONFIG_X86_64
3250 if (amdgpu_vm_update_mode == -1) {
3251 if (amdgpu_gmc_vram_full_visible(&adev->gmc))
3252 adev->vm_manager.vm_update_mode =
3253 AMDGPU_VM_USE_CPU_FOR_COMPUTE;
3255 adev->vm_manager.vm_update_mode = 0;
3257 adev->vm_manager.vm_update_mode = amdgpu_vm_update_mode;
3259 adev->vm_manager.vm_update_mode = 0;
3262 idr_init(&adev->vm_manager.pasid_idr);
3263 spin_lock_init(&adev->vm_manager.pasid_lock);
3267 * amdgpu_vm_manager_fini - cleanup VM manager
3269 * @adev: amdgpu_device pointer
3271 * Cleanup the VM manager and free resources.
3273 void amdgpu_vm_manager_fini(struct amdgpu_device *adev)
3275 WARN_ON(!idr_is_empty(&adev->vm_manager.pasid_idr));
3276 idr_destroy(&adev->vm_manager.pasid_idr);
3278 amdgpu_vmid_mgr_fini(adev);
3282 * amdgpu_vm_ioctl - Manages VMID reservation for vm hubs.
3284 * @dev: drm device pointer
3285 * @data: drm_amdgpu_vm
3286 * @filp: drm file pointer
3289 * 0 for success, -errno for errors.
3291 int amdgpu_vm_ioctl(struct drm_device *dev, void *data, struct drm_file *filp)
3293 union drm_amdgpu_vm *args = data;
3294 struct amdgpu_device *adev = drm_to_adev(dev);
3295 struct amdgpu_fpriv *fpriv = filp->driver_priv;
3296 long timeout = msecs_to_jiffies(2000);
3299 switch (args->in.op) {
3300 case AMDGPU_VM_OP_RESERVE_VMID:
3301 /* We only have requirement to reserve vmid from gfxhub */
3302 r = amdgpu_vmid_alloc_reserved(adev, &fpriv->vm,
3307 case AMDGPU_VM_OP_UNRESERVE_VMID:
3308 if (amdgpu_sriov_runtime(adev))
3309 timeout = 8 * timeout;
3311 /* Wait vm idle to make sure the vmid set in SPM_VMID is
3312 * not referenced anymore.
3314 r = amdgpu_bo_reserve(fpriv->vm.root.bo, true);
3318 r = amdgpu_vm_wait_idle(&fpriv->vm, timeout);
3322 amdgpu_bo_unreserve(fpriv->vm.root.bo);
3323 amdgpu_vmid_free_reserved(adev, &fpriv->vm, AMDGPU_GFXHUB_0);
3333 * amdgpu_vm_get_task_info - Extracts task info for a PASID.
3335 * @adev: drm device pointer
3336 * @pasid: PASID identifier for VM
3337 * @task_info: task_info to fill.
3339 void amdgpu_vm_get_task_info(struct amdgpu_device *adev, u32 pasid,
3340 struct amdgpu_task_info *task_info)
3342 struct amdgpu_vm *vm;
3343 unsigned long flags;
3345 spin_lock_irqsave(&adev->vm_manager.pasid_lock, flags);
3347 vm = idr_find(&adev->vm_manager.pasid_idr, pasid);
3349 *task_info = vm->task_info;
3351 spin_unlock_irqrestore(&adev->vm_manager.pasid_lock, flags);
3355 * amdgpu_vm_set_task_info - Sets VMs task info.
3357 * @vm: vm for which to set the info
3359 void amdgpu_vm_set_task_info(struct amdgpu_vm *vm)
3361 if (vm->task_info.pid)
3364 vm->task_info.pid = current->pid;
3365 get_task_comm(vm->task_info.task_name, current);
3367 if (current->group_leader->mm != current->mm)
3370 vm->task_info.tgid = current->group_leader->pid;
3371 get_task_comm(vm->task_info.process_name, current->group_leader);
3375 * amdgpu_vm_handle_fault - graceful handling of VM faults.
3376 * @adev: amdgpu device pointer
3377 * @pasid: PASID of the VM
3378 * @addr: Address of the fault
3380 * Try to gracefully handle a VM fault. Return true if the fault was handled and
3381 * shouldn't be reported any more.
3383 bool amdgpu_vm_handle_fault(struct amdgpu_device *adev, u32 pasid,
3386 bool is_compute_context = false;
3387 struct amdgpu_bo *root;
3388 unsigned long irqflags;
3389 uint64_t value, flags;
3390 struct amdgpu_vm *vm;
3393 spin_lock_irqsave(&adev->vm_manager.pasid_lock, irqflags);
3394 vm = idr_find(&adev->vm_manager.pasid_idr, pasid);
3396 root = amdgpu_bo_ref(vm->root.bo);
3397 is_compute_context = vm->is_compute_context;
3401 spin_unlock_irqrestore(&adev->vm_manager.pasid_lock, irqflags);
3406 addr /= AMDGPU_GPU_PAGE_SIZE;
3408 if (is_compute_context &&
3409 !svm_range_restore_pages(adev, pasid, addr)) {
3410 amdgpu_bo_unref(&root);
3414 r = amdgpu_bo_reserve(root, true);
3418 /* Double check that the VM still exists */
3419 spin_lock_irqsave(&adev->vm_manager.pasid_lock, irqflags);
3420 vm = idr_find(&adev->vm_manager.pasid_idr, pasid);
3421 if (vm && vm->root.bo != root)
3423 spin_unlock_irqrestore(&adev->vm_manager.pasid_lock, irqflags);
3427 flags = AMDGPU_PTE_VALID | AMDGPU_PTE_SNOOPED |
3430 if (is_compute_context) {
3431 /* Intentionally setting invalid PTE flag
3432 * combination to force a no-retry-fault
3434 flags = AMDGPU_PTE_EXECUTABLE | AMDGPU_PDE_PTE |
3437 } else if (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_NEVER) {
3438 /* Redirect the access to the dummy page */
3439 value = adev->dummy_page_addr;
3440 flags |= AMDGPU_PTE_EXECUTABLE | AMDGPU_PTE_READABLE |
3441 AMDGPU_PTE_WRITEABLE;
3444 /* Let the hw retry silently on the PTE */
3448 r = dma_resv_reserve_shared(root->tbo.base.resv, 1);
3450 pr_debug("failed %d to reserve fence slot\n", r);
3454 r = amdgpu_vm_bo_update_mapping(adev, adev, vm, true, false, NULL, addr,
3455 addr, flags, value, NULL, NULL, NULL,
3460 r = amdgpu_vm_update_pdes(adev, vm, true);
3463 amdgpu_bo_unreserve(root);
3465 DRM_ERROR("Can't handle page fault (%d)\n", r);
3468 amdgpu_bo_unref(&root);
3473 #if defined(CONFIG_DEBUG_FS)
3475 * amdgpu_debugfs_vm_bo_info - print BO info for the VM
3477 * @vm: Requested VM for printing BO info
3480 * Print BO information in debugfs file for the VM
3482 void amdgpu_debugfs_vm_bo_info(struct amdgpu_vm *vm, struct seq_file *m)
3484 struct amdgpu_bo_va *bo_va, *tmp;
3486 u64 total_evicted = 0;
3487 u64 total_relocated = 0;
3488 u64 total_moved = 0;
3489 u64 total_invalidated = 0;
3491 unsigned int total_idle_objs = 0;
3492 unsigned int total_evicted_objs = 0;
3493 unsigned int total_relocated_objs = 0;
3494 unsigned int total_moved_objs = 0;
3495 unsigned int total_invalidated_objs = 0;
3496 unsigned int total_done_objs = 0;
3497 unsigned int id = 0;
3499 seq_puts(m, "\tIdle BOs:\n");
3500 list_for_each_entry_safe(bo_va, tmp, &vm->idle, base.vm_status) {
3501 if (!bo_va->base.bo)
3503 total_idle += amdgpu_bo_print_info(id++, bo_va->base.bo, m);
3505 total_idle_objs = id;
3508 seq_puts(m, "\tEvicted BOs:\n");
3509 list_for_each_entry_safe(bo_va, tmp, &vm->evicted, base.vm_status) {
3510 if (!bo_va->base.bo)
3512 total_evicted += amdgpu_bo_print_info(id++, bo_va->base.bo, m);
3514 total_evicted_objs = id;
3517 seq_puts(m, "\tRelocated BOs:\n");
3518 list_for_each_entry_safe(bo_va, tmp, &vm->relocated, base.vm_status) {
3519 if (!bo_va->base.bo)
3521 total_relocated += amdgpu_bo_print_info(id++, bo_va->base.bo, m);
3523 total_relocated_objs = id;
3526 seq_puts(m, "\tMoved BOs:\n");
3527 list_for_each_entry_safe(bo_va, tmp, &vm->moved, base.vm_status) {
3528 if (!bo_va->base.bo)
3530 total_moved += amdgpu_bo_print_info(id++, bo_va->base.bo, m);
3532 total_moved_objs = id;
3535 seq_puts(m, "\tInvalidated BOs:\n");
3536 spin_lock(&vm->invalidated_lock);
3537 list_for_each_entry_safe(bo_va, tmp, &vm->invalidated, base.vm_status) {
3538 if (!bo_va->base.bo)
3540 total_invalidated += amdgpu_bo_print_info(id++, bo_va->base.bo, m);
3542 total_invalidated_objs = id;
3545 seq_puts(m, "\tDone BOs:\n");
3546 list_for_each_entry_safe(bo_va, tmp, &vm->done, base.vm_status) {
3547 if (!bo_va->base.bo)
3549 total_done += amdgpu_bo_print_info(id++, bo_va->base.bo, m);
3551 spin_unlock(&vm->invalidated_lock);
3552 total_done_objs = id;
3554 seq_printf(m, "\tTotal idle size: %12lld\tobjs:\t%d\n", total_idle,
3556 seq_printf(m, "\tTotal evicted size: %12lld\tobjs:\t%d\n", total_evicted,
3557 total_evicted_objs);
3558 seq_printf(m, "\tTotal relocated size: %12lld\tobjs:\t%d\n", total_relocated,
3559 total_relocated_objs);
3560 seq_printf(m, "\tTotal moved size: %12lld\tobjs:\t%d\n", total_moved,
3562 seq_printf(m, "\tTotal invalidated size: %12lld\tobjs:\t%d\n", total_invalidated,
3563 total_invalidated_objs);
3564 seq_printf(m, "\tTotal done size: %12lld\tobjs:\t%d\n", total_done,