2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
24 * Authors: Dave Airlie
29 #include <drm/amdgpu_drm.h>
31 #include "amdgpu_trace.h"
35 * GPUVM is similar to the legacy gart on older asics, however
36 * rather than there being a single global gart table
37 * for the entire GPU, there are multiple VM page tables active
38 * at any given time. The VM page tables can contain a mix
39 * vram pages and system memory pages and system memory pages
40 * can be mapped as snooped (cached system pages) or unsnooped
41 * (uncached system pages).
42 * Each VM has an ID associated with it and there is a page table
43 * associated with each VMID. When execting a command buffer,
44 * the kernel tells the the ring what VMID to use for that command
45 * buffer. VMIDs are allocated dynamically as commands are submitted.
46 * The userspace drivers maintain their own address space and the kernel
47 * sets up their pages tables accordingly when they submit their
48 * command buffers and a VMID is assigned.
49 * Cayman/Trinity support up to 8 active VMs at any given time;
53 /* Special value that no flush is necessary */
54 #define AMDGPU_VM_NO_FLUSH (~0ll)
57 * amdgpu_vm_num_pde - return the number of page directory entries
59 * @adev: amdgpu_device pointer
61 * Calculate the number of page directory entries.
63 static unsigned amdgpu_vm_num_pdes(struct amdgpu_device *adev)
65 return adev->vm_manager.max_pfn >> amdgpu_vm_block_size;
69 * amdgpu_vm_directory_size - returns the size of the page directory in bytes
71 * @adev: amdgpu_device pointer
73 * Calculate the size of the page directory in bytes.
75 static unsigned amdgpu_vm_directory_size(struct amdgpu_device *adev)
77 return AMDGPU_GPU_PAGE_ALIGN(amdgpu_vm_num_pdes(adev) * 8);
81 * amdgpu_vm_get_pd_bo - add the VM PD to a validation list
83 * @vm: vm providing the BOs
84 * @validated: head of validation list
85 * @entry: entry to add
87 * Add the page directory to the list of BOs to
88 * validate for command submission.
90 void amdgpu_vm_get_pd_bo(struct amdgpu_vm *vm,
91 struct list_head *validated,
92 struct amdgpu_bo_list_entry *entry)
94 entry->robj = vm->page_directory;
96 entry->tv.bo = &vm->page_directory->tbo;
97 entry->tv.shared = true;
98 entry->user_pages = NULL;
99 list_add(&entry->tv.head, validated);
103 * amdgpu_vm_get_bos - add the vm BOs to a duplicates list
105 * @vm: vm providing the BOs
106 * @duplicates: head of duplicates list
108 * Add the page directory to the BO duplicates list
109 * for command submission.
111 void amdgpu_vm_get_pt_bos(struct amdgpu_vm *vm, struct list_head *duplicates)
115 /* add the vm page table to the list */
116 for (i = 0; i <= vm->max_pde_used; ++i) {
117 struct amdgpu_bo_list_entry *entry = &vm->page_tables[i].entry;
122 list_add(&entry->tv.head, duplicates);
128 * amdgpu_vm_move_pt_bos_in_lru - move the PT BOs to the LRU tail
130 * @adev: amdgpu device instance
131 * @vm: vm providing the BOs
133 * Move the PT BOs to the tail of the LRU.
135 void amdgpu_vm_move_pt_bos_in_lru(struct amdgpu_device *adev,
136 struct amdgpu_vm *vm)
138 struct ttm_bo_global *glob = adev->mman.bdev.glob;
141 spin_lock(&glob->lru_lock);
142 for (i = 0; i <= vm->max_pde_used; ++i) {
143 struct amdgpu_bo_list_entry *entry = &vm->page_tables[i].entry;
148 ttm_bo_move_to_lru_tail(&entry->robj->tbo);
150 spin_unlock(&glob->lru_lock);
154 * amdgpu_vm_grab_id - allocate the next free VMID
156 * @vm: vm to allocate id for
157 * @ring: ring we want to submit job to
158 * @sync: sync object where we add dependencies
159 * @fence: fence protecting ID from reuse
161 * Allocate an id for the vm, adding fences to the sync obj as necessary.
163 int amdgpu_vm_grab_id(struct amdgpu_vm *vm, struct amdgpu_ring *ring,
164 struct amdgpu_sync *sync, struct fence *fence,
165 unsigned *vm_id, uint64_t *vm_pd_addr)
167 uint64_t pd_addr = amdgpu_bo_gpu_offset(vm->page_directory);
168 struct amdgpu_device *adev = ring->adev;
169 struct fence *updates = sync->last_vm_update;
170 struct amdgpu_vm_id *id;
171 unsigned i = ring->idx;
174 mutex_lock(&adev->vm_manager.lock);
176 /* Check if we can use a VMID already assigned to this VM */
178 struct fence *flushed;
181 if (i == AMDGPU_MAX_RINGS)
184 /* Check all the prerequisites to using this VMID */
188 if (atomic64_read(&id->owner) != vm->client_id)
191 if (pd_addr != id->pd_gpu_addr)
194 if (id->last_user != ring &&
195 (!id->last_flush || !fence_is_signaled(id->last_flush)))
198 flushed = id->flushed_updates;
199 if (updates && (!flushed || fence_is_later(updates, flushed)))
202 /* Good we can use this VMID */
203 if (id->last_user == ring) {
204 r = amdgpu_sync_fence(ring->adev, sync,
210 /* And remember this submission as user of the VMID */
211 r = amdgpu_sync_fence(ring->adev, &id->active, fence);
215 list_move_tail(&id->list, &adev->vm_manager.ids_lru);
216 vm->ids[ring->idx] = id;
218 *vm_id = id - adev->vm_manager.ids;
219 *vm_pd_addr = AMDGPU_VM_NO_FLUSH;
220 trace_amdgpu_vm_grab_id(vm, ring->idx, *vm_id, *vm_pd_addr);
222 mutex_unlock(&adev->vm_manager.lock);
225 } while (i != ring->idx);
227 id = list_first_entry(&adev->vm_manager.ids_lru,
231 if (!amdgpu_sync_is_idle(&id->active)) {
232 struct list_head *head = &adev->vm_manager.ids_lru;
233 struct amdgpu_vm_id *tmp;
235 list_for_each_entry_safe(id, tmp, &adev->vm_manager.ids_lru,
237 if (amdgpu_sync_is_idle(&id->active)) {
238 list_move(&id->list, head);
242 id = list_first_entry(&adev->vm_manager.ids_lru,
247 r = amdgpu_sync_cycle_fences(sync, &id->active, fence);
251 fence_put(id->first);
252 id->first = fence_get(fence);
254 fence_put(id->last_flush);
255 id->last_flush = NULL;
257 fence_put(id->flushed_updates);
258 id->flushed_updates = fence_get(updates);
260 id->pd_gpu_addr = pd_addr;
262 list_move_tail(&id->list, &adev->vm_manager.ids_lru);
263 id->last_user = ring;
264 atomic64_set(&id->owner, vm->client_id);
265 vm->ids[ring->idx] = id;
267 *vm_id = id - adev->vm_manager.ids;
268 *vm_pd_addr = pd_addr;
269 trace_amdgpu_vm_grab_id(vm, ring->idx, *vm_id, *vm_pd_addr);
272 mutex_unlock(&adev->vm_manager.lock);
277 * amdgpu_vm_flush - hardware flush the vm
279 * @ring: ring to use for flush
280 * @vm_id: vmid number to use
281 * @pd_addr: address of the page directory
283 * Emit a VM flush when it is necessary.
285 int amdgpu_vm_flush(struct amdgpu_ring *ring,
286 unsigned vm_id, uint64_t pd_addr,
287 uint32_t gds_base, uint32_t gds_size,
288 uint32_t gws_base, uint32_t gws_size,
289 uint32_t oa_base, uint32_t oa_size)
291 struct amdgpu_device *adev = ring->adev;
292 struct amdgpu_vm_id *id = &adev->vm_manager.ids[vm_id];
293 bool gds_switch_needed = ring->funcs->emit_gds_switch && (
294 id->gds_base != gds_base ||
295 id->gds_size != gds_size ||
296 id->gws_base != gws_base ||
297 id->gws_size != gws_size ||
298 id->oa_base != oa_base ||
299 id->oa_size != oa_size);
302 if (ring->funcs->emit_pipeline_sync && (
303 pd_addr != AMDGPU_VM_NO_FLUSH || gds_switch_needed ||
304 ring->type == AMDGPU_RING_TYPE_COMPUTE))
305 amdgpu_ring_emit_pipeline_sync(ring);
307 if (ring->funcs->emit_vm_flush &&
308 pd_addr != AMDGPU_VM_NO_FLUSH) {
311 trace_amdgpu_vm_flush(pd_addr, ring->idx, vm_id);
312 amdgpu_ring_emit_vm_flush(ring, vm_id, pd_addr);
314 mutex_lock(&adev->vm_manager.lock);
315 if ((id->pd_gpu_addr == pd_addr) && (id->last_user == ring)) {
316 r = amdgpu_fence_emit(ring, &fence);
318 mutex_unlock(&adev->vm_manager.lock);
321 fence_put(id->last_flush);
322 id->last_flush = fence;
324 mutex_unlock(&adev->vm_manager.lock);
327 if (gds_switch_needed) {
328 id->gds_base = gds_base;
329 id->gds_size = gds_size;
330 id->gws_base = gws_base;
331 id->gws_size = gws_size;
332 id->oa_base = oa_base;
333 id->oa_size = oa_size;
334 amdgpu_ring_emit_gds_switch(ring, vm_id,
344 * amdgpu_vm_reset_id - reset VMID to zero
346 * @adev: amdgpu device structure
347 * @vm_id: vmid number to use
349 * Reset saved GDW, GWS and OA to force switch on next flush.
351 void amdgpu_vm_reset_id(struct amdgpu_device *adev, unsigned vm_id)
353 struct amdgpu_vm_id *id = &adev->vm_manager.ids[vm_id];
364 * amdgpu_vm_bo_find - find the bo_va for a specific vm & bo
367 * @bo: requested buffer object
369 * Find @bo inside the requested vm.
370 * Search inside the @bos vm list for the requested vm
371 * Returns the found bo_va or NULL if none is found
373 * Object has to be reserved!
375 struct amdgpu_bo_va *amdgpu_vm_bo_find(struct amdgpu_vm *vm,
376 struct amdgpu_bo *bo)
378 struct amdgpu_bo_va *bo_va;
380 list_for_each_entry(bo_va, &bo->va, bo_list) {
381 if (bo_va->vm == vm) {
389 * amdgpu_vm_update_pages - helper to call the right asic function
391 * @adev: amdgpu_device pointer
392 * @src: address where to copy page table entries from
393 * @pages_addr: DMA addresses to use for mapping
394 * @ib: indirect buffer to fill with commands
395 * @pe: addr of the page entry
396 * @addr: dst addr to write into pe
397 * @count: number of page entries to update
398 * @incr: increase next addr by incr bytes
399 * @flags: hw access flags
401 * Traces the parameters and calls the right asic functions
402 * to setup the page table using the DMA.
404 static void amdgpu_vm_update_pages(struct amdgpu_device *adev,
406 dma_addr_t *pages_addr,
407 struct amdgpu_ib *ib,
408 uint64_t pe, uint64_t addr,
409 unsigned count, uint32_t incr,
412 trace_amdgpu_vm_set_page(pe, addr, count, incr, flags);
415 src += (addr >> 12) * 8;
416 amdgpu_vm_copy_pte(adev, ib, pe, src, count);
418 } else if (pages_addr) {
419 amdgpu_vm_write_pte(adev, ib, pages_addr, pe, addr,
422 } else if (count < 3) {
423 amdgpu_vm_write_pte(adev, ib, NULL, pe, addr,
427 amdgpu_vm_set_pte_pde(adev, ib, pe, addr,
433 * amdgpu_vm_clear_bo - initially clear the page dir/table
435 * @adev: amdgpu_device pointer
438 * need to reserve bo first before calling it.
440 static int amdgpu_vm_clear_bo(struct amdgpu_device *adev,
441 struct amdgpu_vm *vm,
442 struct amdgpu_bo *bo)
444 struct amdgpu_ring *ring;
445 struct fence *fence = NULL;
446 struct amdgpu_job *job;
451 ring = container_of(vm->entity.sched, struct amdgpu_ring, sched);
453 r = reservation_object_reserve_shared(bo->tbo.resv);
457 r = ttm_bo_validate(&bo->tbo, &bo->placement, true, false);
461 addr = amdgpu_bo_gpu_offset(bo);
462 entries = amdgpu_bo_size(bo) / 8;
464 r = amdgpu_job_alloc_with_ib(adev, 64, &job);
468 amdgpu_vm_update_pages(adev, 0, NULL, &job->ibs[0], addr, 0, entries,
470 amdgpu_ring_pad_ib(ring, &job->ibs[0]);
472 WARN_ON(job->ibs[0].length_dw > 64);
473 r = amdgpu_job_submit(job, ring, &vm->entity,
474 AMDGPU_FENCE_OWNER_VM, &fence);
478 amdgpu_bo_fence(bo, fence, true);
483 amdgpu_job_free(job);
490 * amdgpu_vm_map_gart - Resolve gart mapping of addr
492 * @pages_addr: optional DMA address to use for lookup
493 * @addr: the unmapped addr
495 * Look up the physical address of the page that the pte resolves
496 * to and return the pointer for the page table entry.
498 uint64_t amdgpu_vm_map_gart(const dma_addr_t *pages_addr, uint64_t addr)
503 /* page table offset */
504 result = pages_addr[addr >> PAGE_SHIFT];
506 /* in case cpu page size != gpu page size*/
507 result |= addr & (~PAGE_MASK);
510 /* No mapping required */
514 result &= 0xFFFFFFFFFFFFF000ULL;
520 * amdgpu_vm_update_pdes - make sure that page directory is valid
522 * @adev: amdgpu_device pointer
524 * @start: start of GPU address range
525 * @end: end of GPU address range
527 * Allocates new page tables if necessary
528 * and updates the page directory.
529 * Returns 0 for success, error for failure.
531 int amdgpu_vm_update_page_directory(struct amdgpu_device *adev,
532 struct amdgpu_vm *vm)
534 struct amdgpu_ring *ring;
535 struct amdgpu_bo *pd = vm->page_directory;
536 uint64_t pd_addr = amdgpu_bo_gpu_offset(pd);
537 uint32_t incr = AMDGPU_VM_PTE_COUNT * 8;
538 uint64_t last_pde = ~0, last_pt = ~0;
539 unsigned count = 0, pt_idx, ndw;
540 struct amdgpu_job *job;
541 struct amdgpu_ib *ib;
542 struct fence *fence = NULL;
546 ring = container_of(vm->entity.sched, struct amdgpu_ring, sched);
551 /* assume the worst case */
552 ndw += vm->max_pde_used * 6;
554 r = amdgpu_job_alloc_with_ib(adev, ndw * 4, &job);
560 /* walk over the address space and update the page directory */
561 for (pt_idx = 0; pt_idx <= vm->max_pde_used; ++pt_idx) {
562 struct amdgpu_bo *bo = vm->page_tables[pt_idx].entry.robj;
568 pt = amdgpu_bo_gpu_offset(bo);
569 if (vm->page_tables[pt_idx].addr == pt)
571 vm->page_tables[pt_idx].addr = pt;
573 pde = pd_addr + pt_idx * 8;
574 if (((last_pde + 8 * count) != pde) ||
575 ((last_pt + incr * count) != pt)) {
578 amdgpu_vm_update_pages(adev, 0, NULL, ib,
593 amdgpu_vm_update_pages(adev, 0, NULL, ib, last_pde, last_pt,
594 count, incr, AMDGPU_PTE_VALID);
596 if (ib->length_dw != 0) {
597 amdgpu_ring_pad_ib(ring, ib);
598 amdgpu_sync_resv(adev, &job->sync, pd->tbo.resv,
599 AMDGPU_FENCE_OWNER_VM);
600 WARN_ON(ib->length_dw > ndw);
601 r = amdgpu_job_submit(job, ring, &vm->entity,
602 AMDGPU_FENCE_OWNER_VM, &fence);
606 amdgpu_bo_fence(pd, fence, true);
607 fence_put(vm->page_directory_fence);
608 vm->page_directory_fence = fence_get(fence);
612 amdgpu_job_free(job);
618 amdgpu_job_free(job);
623 * amdgpu_vm_frag_ptes - add fragment information to PTEs
625 * @adev: amdgpu_device pointer
626 * @src: address where to copy page table entries from
627 * @pages_addr: DMA addresses to use for mapping
628 * @ib: IB for the update
629 * @pe_start: first PTE to handle
630 * @pe_end: last PTE to handle
631 * @addr: addr those PTEs should point to
632 * @flags: hw mapping flags
634 static void amdgpu_vm_frag_ptes(struct amdgpu_device *adev,
636 dma_addr_t *pages_addr,
637 struct amdgpu_ib *ib,
638 uint64_t pe_start, uint64_t pe_end,
639 uint64_t addr, uint32_t flags)
642 * The MC L1 TLB supports variable sized pages, based on a fragment
643 * field in the PTE. When this field is set to a non-zero value, page
644 * granularity is increased from 4KB to (1 << (12 + frag)). The PTE
645 * flags are considered valid for all PTEs within the fragment range
646 * and corresponding mappings are assumed to be physically contiguous.
648 * The L1 TLB can store a single PTE for the whole fragment,
649 * significantly increasing the space available for translation
650 * caching. This leads to large improvements in throughput when the
651 * TLB is under pressure.
653 * The L2 TLB distributes small and large fragments into two
654 * asymmetric partitions. The large fragment cache is significantly
655 * larger. Thus, we try to use large fragments wherever possible.
656 * Userspace can support this by aligning virtual base address and
657 * allocation size to the fragment size.
660 /* SI and newer are optimized for 64KB */
661 uint64_t frag_flags = AMDGPU_PTE_FRAG_64KB;
662 uint64_t frag_align = 0x80;
664 uint64_t frag_start = ALIGN(pe_start, frag_align);
665 uint64_t frag_end = pe_end & ~(frag_align - 1);
669 /* Abort early if there isn't anything to do */
670 if (pe_start == pe_end)
673 /* system pages are non continuously */
674 if (src || pages_addr || !(flags & AMDGPU_PTE_VALID) ||
675 (frag_start >= frag_end)) {
677 count = (pe_end - pe_start) / 8;
678 amdgpu_vm_update_pages(adev, src, pages_addr, ib, pe_start,
679 addr, count, AMDGPU_GPU_PAGE_SIZE,
684 /* handle the 4K area at the beginning */
685 if (pe_start != frag_start) {
686 count = (frag_start - pe_start) / 8;
687 amdgpu_vm_update_pages(adev, 0, NULL, ib, pe_start, addr,
688 count, AMDGPU_GPU_PAGE_SIZE, flags);
689 addr += AMDGPU_GPU_PAGE_SIZE * count;
692 /* handle the area in the middle */
693 count = (frag_end - frag_start) / 8;
694 amdgpu_vm_update_pages(adev, 0, NULL, ib, frag_start, addr, count,
695 AMDGPU_GPU_PAGE_SIZE, flags | frag_flags);
697 /* handle the 4K area at the end */
698 if (frag_end != pe_end) {
699 addr += AMDGPU_GPU_PAGE_SIZE * count;
700 count = (pe_end - frag_end) / 8;
701 amdgpu_vm_update_pages(adev, 0, NULL, ib, frag_end, addr,
702 count, AMDGPU_GPU_PAGE_SIZE, flags);
707 * amdgpu_vm_update_ptes - make sure that page tables are valid
709 * @adev: amdgpu_device pointer
710 * @src: address where to copy page table entries from
711 * @pages_addr: DMA addresses to use for mapping
713 * @start: start of GPU address range
714 * @end: end of GPU address range
715 * @dst: destination address to map to
716 * @flags: mapping flags
718 * Update the page tables in the range @start - @end.
720 static void amdgpu_vm_update_ptes(struct amdgpu_device *adev,
722 dma_addr_t *pages_addr,
723 struct amdgpu_vm *vm,
724 struct amdgpu_ib *ib,
725 uint64_t start, uint64_t end,
726 uint64_t dst, uint32_t flags)
728 const uint64_t mask = AMDGPU_VM_PTE_COUNT - 1;
730 uint64_t last_pe_start = ~0, last_pe_end = ~0, last_dst = ~0;
733 /* walk over the address space and update the page tables */
734 for (addr = start; addr < end; ) {
735 uint64_t pt_idx = addr >> amdgpu_vm_block_size;
736 struct amdgpu_bo *pt = vm->page_tables[pt_idx].entry.robj;
740 if ((addr & ~mask) == (end & ~mask))
743 nptes = AMDGPU_VM_PTE_COUNT - (addr & mask);
745 pe_start = amdgpu_bo_gpu_offset(pt);
746 pe_start += (addr & mask) * 8;
748 if (last_pe_end != pe_start) {
750 amdgpu_vm_frag_ptes(adev, src, pages_addr, ib,
751 last_pe_start, last_pe_end,
754 last_pe_start = pe_start;
755 last_pe_end = pe_start + 8 * nptes;
758 last_pe_end += 8 * nptes;
762 dst += nptes * AMDGPU_GPU_PAGE_SIZE;
765 amdgpu_vm_frag_ptes(adev, src, pages_addr, ib, last_pe_start,
766 last_pe_end, last_dst, flags);
770 * amdgpu_vm_bo_update_mapping - update a mapping in the vm page table
772 * @adev: amdgpu_device pointer
773 * @src: address where to copy page table entries from
774 * @pages_addr: DMA addresses to use for mapping
776 * @start: start of mapped range
777 * @last: last mapped entry
778 * @flags: flags for the entries
779 * @addr: addr to set the area to
780 * @fence: optional resulting fence
782 * Fill in the page table entries between @start and @last.
783 * Returns 0 for success, -EINVAL for failure.
785 static int amdgpu_vm_bo_update_mapping(struct amdgpu_device *adev,
787 dma_addr_t *pages_addr,
788 struct amdgpu_vm *vm,
789 uint64_t start, uint64_t last,
790 uint32_t flags, uint64_t addr,
791 struct fence **fence)
793 struct amdgpu_ring *ring;
794 void *owner = AMDGPU_FENCE_OWNER_VM;
795 unsigned nptes, ncmds, ndw;
796 struct amdgpu_job *job;
797 struct amdgpu_ib *ib;
798 struct fence *f = NULL;
801 ring = container_of(vm->entity.sched, struct amdgpu_ring, sched);
803 /* sync to everything on unmapping */
804 if (!(flags & AMDGPU_PTE_VALID))
805 owner = AMDGPU_FENCE_OWNER_UNDEFINED;
807 nptes = last - start + 1;
810 * reserve space for one command every (1 << BLOCK_SIZE)
811 * entries or 2k dwords (whatever is smaller)
813 ncmds = (nptes >> min(amdgpu_vm_block_size, 11)) + 1;
819 /* only copy commands needed */
822 } else if (pages_addr) {
823 /* header for write data commands */
826 /* body of write data command */
830 /* set page commands needed */
833 /* two extra commands for begin/end of fragment */
837 r = amdgpu_job_alloc_with_ib(adev, ndw * 4, &job);
843 r = amdgpu_sync_resv(adev, &job->sync, vm->page_directory->tbo.resv,
848 r = reservation_object_reserve_shared(vm->page_directory->tbo.resv);
852 amdgpu_vm_update_ptes(adev, src, pages_addr, vm, ib, start,
853 last + 1, addr, flags);
855 amdgpu_ring_pad_ib(ring, ib);
856 WARN_ON(ib->length_dw > ndw);
857 r = amdgpu_job_submit(job, ring, &vm->entity,
858 AMDGPU_FENCE_OWNER_VM, &f);
862 amdgpu_bo_fence(vm->page_directory, f, true);
865 *fence = fence_get(f);
871 amdgpu_job_free(job);
876 * amdgpu_vm_bo_split_mapping - split a mapping into smaller chunks
878 * @adev: amdgpu_device pointer
879 * @gtt_flags: flags as they are used for GTT
880 * @pages_addr: DMA addresses to use for mapping
882 * @mapping: mapped range and flags to use for the update
883 * @addr: addr to set the area to
884 * @flags: HW flags for the mapping
885 * @fence: optional resulting fence
887 * Split the mapping into smaller chunks so that each update fits
889 * Returns 0 for success, -EINVAL for failure.
891 static int amdgpu_vm_bo_split_mapping(struct amdgpu_device *adev,
893 dma_addr_t *pages_addr,
894 struct amdgpu_vm *vm,
895 struct amdgpu_bo_va_mapping *mapping,
896 uint32_t flags, uint64_t addr,
897 struct fence **fence)
899 const uint64_t max_size = 64ULL * 1024ULL * 1024ULL / AMDGPU_GPU_PAGE_SIZE;
901 uint64_t src = 0, start = mapping->it.start;
904 /* normally,bo_va->flags only contians READABLE and WIRTEABLE bit go here
905 * but in case of something, we filter the flags in first place
907 if (!(mapping->flags & AMDGPU_PTE_READABLE))
908 flags &= ~AMDGPU_PTE_READABLE;
909 if (!(mapping->flags & AMDGPU_PTE_WRITEABLE))
910 flags &= ~AMDGPU_PTE_WRITEABLE;
912 trace_amdgpu_vm_bo_update(mapping);
915 if (flags == gtt_flags)
916 src = adev->gart.table_addr + (addr >> 12) * 8;
919 addr += mapping->offset;
921 if (!pages_addr || src)
922 return amdgpu_vm_bo_update_mapping(adev, src, pages_addr, vm,
923 start, mapping->it.last,
926 while (start != mapping->it.last + 1) {
929 last = min((uint64_t)mapping->it.last, start + max_size - 1);
930 r = amdgpu_vm_bo_update_mapping(adev, src, pages_addr, vm,
931 start, last, flags, addr,
937 addr += max_size * AMDGPU_GPU_PAGE_SIZE;
944 * amdgpu_vm_bo_update - update all BO mappings in the vm page table
946 * @adev: amdgpu_device pointer
947 * @bo_va: requested BO and VM object
950 * Fill in the page table entries for @bo_va.
951 * Returns 0 for success, -EINVAL for failure.
953 * Object have to be reserved and mutex must be locked!
955 int amdgpu_vm_bo_update(struct amdgpu_device *adev,
956 struct amdgpu_bo_va *bo_va,
957 struct ttm_mem_reg *mem)
959 struct amdgpu_vm *vm = bo_va->vm;
960 struct amdgpu_bo_va_mapping *mapping;
961 dma_addr_t *pages_addr = NULL;
962 uint32_t gtt_flags, flags;
967 struct ttm_dma_tt *ttm;
969 addr = (u64)mem->start << PAGE_SHIFT;
970 switch (mem->mem_type) {
972 ttm = container_of(bo_va->bo->tbo.ttm, struct
974 pages_addr = ttm->dma_address;
978 addr += adev->vm_manager.vram_base_offset;
988 flags = amdgpu_ttm_tt_pte_flags(adev, bo_va->bo->tbo.ttm, mem);
989 gtt_flags = (adev == bo_va->bo->adev) ? flags : 0;
991 spin_lock(&vm->status_lock);
992 if (!list_empty(&bo_va->vm_status))
993 list_splice_init(&bo_va->valids, &bo_va->invalids);
994 spin_unlock(&vm->status_lock);
996 list_for_each_entry(mapping, &bo_va->invalids, list) {
997 r = amdgpu_vm_bo_split_mapping(adev, gtt_flags, pages_addr, vm,
998 mapping, flags, addr,
999 &bo_va->last_pt_update);
1004 if (trace_amdgpu_vm_bo_mapping_enabled()) {
1005 list_for_each_entry(mapping, &bo_va->valids, list)
1006 trace_amdgpu_vm_bo_mapping(mapping);
1008 list_for_each_entry(mapping, &bo_va->invalids, list)
1009 trace_amdgpu_vm_bo_mapping(mapping);
1012 spin_lock(&vm->status_lock);
1013 list_splice_init(&bo_va->invalids, &bo_va->valids);
1014 list_del_init(&bo_va->vm_status);
1016 list_add(&bo_va->vm_status, &vm->cleared);
1017 spin_unlock(&vm->status_lock);
1023 * amdgpu_vm_clear_freed - clear freed BOs in the PT
1025 * @adev: amdgpu_device pointer
1028 * Make sure all freed BOs are cleared in the PT.
1029 * Returns 0 for success.
1031 * PTs have to be reserved and mutex must be locked!
1033 int amdgpu_vm_clear_freed(struct amdgpu_device *adev,
1034 struct amdgpu_vm *vm)
1036 struct amdgpu_bo_va_mapping *mapping;
1039 while (!list_empty(&vm->freed)) {
1040 mapping = list_first_entry(&vm->freed,
1041 struct amdgpu_bo_va_mapping, list);
1042 list_del(&mapping->list);
1044 r = amdgpu_vm_bo_split_mapping(adev, 0, NULL, vm, mapping,
1056 * amdgpu_vm_clear_invalids - clear invalidated BOs in the PT
1058 * @adev: amdgpu_device pointer
1061 * Make sure all invalidated BOs are cleared in the PT.
1062 * Returns 0 for success.
1064 * PTs have to be reserved and mutex must be locked!
1066 int amdgpu_vm_clear_invalids(struct amdgpu_device *adev,
1067 struct amdgpu_vm *vm, struct amdgpu_sync *sync)
1069 struct amdgpu_bo_va *bo_va = NULL;
1072 spin_lock(&vm->status_lock);
1073 while (!list_empty(&vm->invalidated)) {
1074 bo_va = list_first_entry(&vm->invalidated,
1075 struct amdgpu_bo_va, vm_status);
1076 spin_unlock(&vm->status_lock);
1078 r = amdgpu_vm_bo_update(adev, bo_va, NULL);
1082 spin_lock(&vm->status_lock);
1084 spin_unlock(&vm->status_lock);
1087 r = amdgpu_sync_fence(adev, sync, bo_va->last_pt_update);
1093 * amdgpu_vm_bo_add - add a bo to a specific vm
1095 * @adev: amdgpu_device pointer
1097 * @bo: amdgpu buffer object
1099 * Add @bo into the requested vm.
1100 * Add @bo to the list of bos associated with the vm
1101 * Returns newly added bo_va or NULL for failure
1103 * Object has to be reserved!
1105 struct amdgpu_bo_va *amdgpu_vm_bo_add(struct amdgpu_device *adev,
1106 struct amdgpu_vm *vm,
1107 struct amdgpu_bo *bo)
1109 struct amdgpu_bo_va *bo_va;
1111 bo_va = kzalloc(sizeof(struct amdgpu_bo_va), GFP_KERNEL);
1112 if (bo_va == NULL) {
1117 bo_va->ref_count = 1;
1118 INIT_LIST_HEAD(&bo_va->bo_list);
1119 INIT_LIST_HEAD(&bo_va->valids);
1120 INIT_LIST_HEAD(&bo_va->invalids);
1121 INIT_LIST_HEAD(&bo_va->vm_status);
1123 list_add_tail(&bo_va->bo_list, &bo->va);
1129 * amdgpu_vm_bo_map - map bo inside a vm
1131 * @adev: amdgpu_device pointer
1132 * @bo_va: bo_va to store the address
1133 * @saddr: where to map the BO
1134 * @offset: requested offset in the BO
1135 * @flags: attributes of pages (read/write/valid/etc.)
1137 * Add a mapping of the BO at the specefied addr into the VM.
1138 * Returns 0 for success, error for failure.
1140 * Object has to be reserved and unreserved outside!
1142 int amdgpu_vm_bo_map(struct amdgpu_device *adev,
1143 struct amdgpu_bo_va *bo_va,
1144 uint64_t saddr, uint64_t offset,
1145 uint64_t size, uint32_t flags)
1147 struct amdgpu_bo_va_mapping *mapping;
1148 struct amdgpu_vm *vm = bo_va->vm;
1149 struct interval_tree_node *it;
1150 unsigned last_pfn, pt_idx;
1154 /* validate the parameters */
1155 if (saddr & AMDGPU_GPU_PAGE_MASK || offset & AMDGPU_GPU_PAGE_MASK ||
1156 size == 0 || size & AMDGPU_GPU_PAGE_MASK)
1159 /* make sure object fit at this offset */
1160 eaddr = saddr + size - 1;
1161 if ((saddr >= eaddr) || (offset + size > amdgpu_bo_size(bo_va->bo)))
1164 last_pfn = eaddr / AMDGPU_GPU_PAGE_SIZE;
1165 if (last_pfn >= adev->vm_manager.max_pfn) {
1166 dev_err(adev->dev, "va above limit (0x%08X >= 0x%08X)\n",
1167 last_pfn, adev->vm_manager.max_pfn);
1171 saddr /= AMDGPU_GPU_PAGE_SIZE;
1172 eaddr /= AMDGPU_GPU_PAGE_SIZE;
1174 it = interval_tree_iter_first(&vm->va, saddr, eaddr);
1176 struct amdgpu_bo_va_mapping *tmp;
1177 tmp = container_of(it, struct amdgpu_bo_va_mapping, it);
1178 /* bo and tmp overlap, invalid addr */
1179 dev_err(adev->dev, "bo %p va 0x%010Lx-0x%010Lx conflict with "
1180 "0x%010lx-0x%010lx\n", bo_va->bo, saddr, eaddr,
1181 tmp->it.start, tmp->it.last + 1);
1186 mapping = kmalloc(sizeof(*mapping), GFP_KERNEL);
1192 INIT_LIST_HEAD(&mapping->list);
1193 mapping->it.start = saddr;
1194 mapping->it.last = eaddr;
1195 mapping->offset = offset;
1196 mapping->flags = flags;
1198 list_add(&mapping->list, &bo_va->invalids);
1199 interval_tree_insert(&mapping->it, &vm->va);
1201 /* Make sure the page tables are allocated */
1202 saddr >>= amdgpu_vm_block_size;
1203 eaddr >>= amdgpu_vm_block_size;
1205 BUG_ON(eaddr >= amdgpu_vm_num_pdes(adev));
1207 if (eaddr > vm->max_pde_used)
1208 vm->max_pde_used = eaddr;
1210 /* walk over the address space and allocate the page tables */
1211 for (pt_idx = saddr; pt_idx <= eaddr; ++pt_idx) {
1212 struct reservation_object *resv = vm->page_directory->tbo.resv;
1213 struct amdgpu_bo_list_entry *entry;
1214 struct amdgpu_bo *pt;
1216 entry = &vm->page_tables[pt_idx].entry;
1220 r = amdgpu_bo_create(adev, AMDGPU_VM_PTE_COUNT * 8,
1221 AMDGPU_GPU_PAGE_SIZE, true,
1222 AMDGPU_GEM_DOMAIN_VRAM,
1223 AMDGPU_GEM_CREATE_NO_CPU_ACCESS,
1228 /* Keep a reference to the page table to avoid freeing
1229 * them up in the wrong order.
1231 pt->parent = amdgpu_bo_ref(vm->page_directory);
1233 r = amdgpu_vm_clear_bo(adev, vm, pt);
1235 amdgpu_bo_unref(&pt);
1240 entry->priority = 0;
1241 entry->tv.bo = &entry->robj->tbo;
1242 entry->tv.shared = true;
1243 entry->user_pages = NULL;
1244 vm->page_tables[pt_idx].addr = 0;
1250 list_del(&mapping->list);
1251 interval_tree_remove(&mapping->it, &vm->va);
1252 trace_amdgpu_vm_bo_unmap(bo_va, mapping);
1260 * amdgpu_vm_bo_unmap - remove bo mapping from vm
1262 * @adev: amdgpu_device pointer
1263 * @bo_va: bo_va to remove the address from
1264 * @saddr: where to the BO is mapped
1266 * Remove a mapping of the BO at the specefied addr from the VM.
1267 * Returns 0 for success, error for failure.
1269 * Object has to be reserved and unreserved outside!
1271 int amdgpu_vm_bo_unmap(struct amdgpu_device *adev,
1272 struct amdgpu_bo_va *bo_va,
1275 struct amdgpu_bo_va_mapping *mapping;
1276 struct amdgpu_vm *vm = bo_va->vm;
1279 saddr /= AMDGPU_GPU_PAGE_SIZE;
1281 list_for_each_entry(mapping, &bo_va->valids, list) {
1282 if (mapping->it.start == saddr)
1286 if (&mapping->list == &bo_va->valids) {
1289 list_for_each_entry(mapping, &bo_va->invalids, list) {
1290 if (mapping->it.start == saddr)
1294 if (&mapping->list == &bo_va->invalids)
1298 list_del(&mapping->list);
1299 interval_tree_remove(&mapping->it, &vm->va);
1300 trace_amdgpu_vm_bo_unmap(bo_va, mapping);
1303 list_add(&mapping->list, &vm->freed);
1311 * amdgpu_vm_bo_rmv - remove a bo to a specific vm
1313 * @adev: amdgpu_device pointer
1314 * @bo_va: requested bo_va
1316 * Remove @bo_va->bo from the requested vm.
1318 * Object have to be reserved!
1320 void amdgpu_vm_bo_rmv(struct amdgpu_device *adev,
1321 struct amdgpu_bo_va *bo_va)
1323 struct amdgpu_bo_va_mapping *mapping, *next;
1324 struct amdgpu_vm *vm = bo_va->vm;
1326 list_del(&bo_va->bo_list);
1328 spin_lock(&vm->status_lock);
1329 list_del(&bo_va->vm_status);
1330 spin_unlock(&vm->status_lock);
1332 list_for_each_entry_safe(mapping, next, &bo_va->valids, list) {
1333 list_del(&mapping->list);
1334 interval_tree_remove(&mapping->it, &vm->va);
1335 trace_amdgpu_vm_bo_unmap(bo_va, mapping);
1336 list_add(&mapping->list, &vm->freed);
1338 list_for_each_entry_safe(mapping, next, &bo_va->invalids, list) {
1339 list_del(&mapping->list);
1340 interval_tree_remove(&mapping->it, &vm->va);
1344 fence_put(bo_va->last_pt_update);
1349 * amdgpu_vm_bo_invalidate - mark the bo as invalid
1351 * @adev: amdgpu_device pointer
1353 * @bo: amdgpu buffer object
1355 * Mark @bo as invalid.
1357 void amdgpu_vm_bo_invalidate(struct amdgpu_device *adev,
1358 struct amdgpu_bo *bo)
1360 struct amdgpu_bo_va *bo_va;
1362 list_for_each_entry(bo_va, &bo->va, bo_list) {
1363 spin_lock(&bo_va->vm->status_lock);
1364 if (list_empty(&bo_va->vm_status))
1365 list_add(&bo_va->vm_status, &bo_va->vm->invalidated);
1366 spin_unlock(&bo_va->vm->status_lock);
1371 * amdgpu_vm_init - initialize a vm instance
1373 * @adev: amdgpu_device pointer
1378 int amdgpu_vm_init(struct amdgpu_device *adev, struct amdgpu_vm *vm)
1380 const unsigned align = min(AMDGPU_VM_PTB_ALIGN_SIZE,
1381 AMDGPU_VM_PTE_COUNT * 8);
1382 unsigned pd_size, pd_entries;
1383 unsigned ring_instance;
1384 struct amdgpu_ring *ring;
1385 struct amd_sched_rq *rq;
1388 for (i = 0; i < AMDGPU_MAX_RINGS; ++i)
1391 vm->client_id = atomic64_inc_return(&adev->vm_manager.client_counter);
1392 spin_lock_init(&vm->status_lock);
1393 INIT_LIST_HEAD(&vm->invalidated);
1394 INIT_LIST_HEAD(&vm->cleared);
1395 INIT_LIST_HEAD(&vm->freed);
1397 pd_size = amdgpu_vm_directory_size(adev);
1398 pd_entries = amdgpu_vm_num_pdes(adev);
1400 /* allocate page table array */
1401 vm->page_tables = drm_calloc_large(pd_entries, sizeof(struct amdgpu_vm_pt));
1402 if (vm->page_tables == NULL) {
1403 DRM_ERROR("Cannot allocate memory for page table array\n");
1407 /* create scheduler entity for page table updates */
1409 ring_instance = atomic_inc_return(&adev->vm_manager.vm_pte_next_ring);
1410 ring_instance %= adev->vm_manager.vm_pte_num_rings;
1411 ring = adev->vm_manager.vm_pte_rings[ring_instance];
1412 rq = &ring->sched.sched_rq[AMD_SCHED_PRIORITY_KERNEL];
1413 r = amd_sched_entity_init(&ring->sched, &vm->entity,
1414 rq, amdgpu_sched_jobs);
1418 vm->page_directory_fence = NULL;
1420 r = amdgpu_bo_create(adev, pd_size, align, true,
1421 AMDGPU_GEM_DOMAIN_VRAM,
1422 AMDGPU_GEM_CREATE_NO_CPU_ACCESS,
1423 NULL, NULL, &vm->page_directory);
1425 goto error_free_sched_entity;
1427 r = amdgpu_bo_reserve(vm->page_directory, false);
1429 goto error_free_page_directory;
1431 r = amdgpu_vm_clear_bo(adev, vm, vm->page_directory);
1432 amdgpu_bo_unreserve(vm->page_directory);
1434 goto error_free_page_directory;
1438 error_free_page_directory:
1439 amdgpu_bo_unref(&vm->page_directory);
1440 vm->page_directory = NULL;
1442 error_free_sched_entity:
1443 amd_sched_entity_fini(&ring->sched, &vm->entity);
1449 * amdgpu_vm_fini - tear down a vm instance
1451 * @adev: amdgpu_device pointer
1455 * Unbind the VM and remove all bos from the vm bo list
1457 void amdgpu_vm_fini(struct amdgpu_device *adev, struct amdgpu_vm *vm)
1459 struct amdgpu_bo_va_mapping *mapping, *tmp;
1462 amd_sched_entity_fini(vm->entity.sched, &vm->entity);
1464 if (!RB_EMPTY_ROOT(&vm->va)) {
1465 dev_err(adev->dev, "still active bo inside vm\n");
1467 rbtree_postorder_for_each_entry_safe(mapping, tmp, &vm->va, it.rb) {
1468 list_del(&mapping->list);
1469 interval_tree_remove(&mapping->it, &vm->va);
1472 list_for_each_entry_safe(mapping, tmp, &vm->freed, list) {
1473 list_del(&mapping->list);
1477 for (i = 0; i < amdgpu_vm_num_pdes(adev); i++)
1478 amdgpu_bo_unref(&vm->page_tables[i].entry.robj);
1479 drm_free_large(vm->page_tables);
1481 amdgpu_bo_unref(&vm->page_directory);
1482 fence_put(vm->page_directory_fence);
1486 * amdgpu_vm_manager_init - init the VM manager
1488 * @adev: amdgpu_device pointer
1490 * Initialize the VM manager structures
1492 void amdgpu_vm_manager_init(struct amdgpu_device *adev)
1496 INIT_LIST_HEAD(&adev->vm_manager.ids_lru);
1498 /* skip over VMID 0, since it is the system VM */
1499 for (i = 1; i < adev->vm_manager.num_ids; ++i) {
1500 amdgpu_vm_reset_id(adev, i);
1501 amdgpu_sync_create(&adev->vm_manager.ids[i].active);
1502 list_add_tail(&adev->vm_manager.ids[i].list,
1503 &adev->vm_manager.ids_lru);
1506 atomic_set(&adev->vm_manager.vm_pte_next_ring, 0);
1507 atomic64_set(&adev->vm_manager.client_counter, 0);
1511 * amdgpu_vm_manager_fini - cleanup VM manager
1513 * @adev: amdgpu_device pointer
1515 * Cleanup the VM manager and free resources.
1517 void amdgpu_vm_manager_fini(struct amdgpu_device *adev)
1521 for (i = 0; i < AMDGPU_NUM_VM; ++i) {
1522 struct amdgpu_vm_id *id = &adev->vm_manager.ids[i];
1524 fence_put(adev->vm_manager.ids[i].first);
1525 amdgpu_sync_free(&adev->vm_manager.ids[i].active);
1526 fence_put(id->flushed_updates);