2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
24 * Authors: Dave Airlie
29 #include <linux/dma-fence-array.h>
30 #include <linux/interval_tree_generic.h>
31 #include <linux/idr.h>
32 #include <linux/dma-buf.h>
34 #include <drm/amdgpu_drm.h>
35 #include <drm/drm_drv.h>
37 #include "amdgpu_trace.h"
38 #include "amdgpu_amdkfd.h"
39 #include "amdgpu_gmc.h"
40 #include "amdgpu_xgmi.h"
41 #include "amdgpu_dma_buf.h"
42 #include "amdgpu_res_cursor.h"
48 * GPUVM is similar to the legacy gart on older asics, however
49 * rather than there being a single global gart table
50 * for the entire GPU, there are multiple VM page tables active
51 * at any given time. The VM page tables can contain a mix
52 * vram pages and system memory pages and system memory pages
53 * can be mapped as snooped (cached system pages) or unsnooped
54 * (uncached system pages).
55 * Each VM has an ID associated with it and there is a page table
56 * associated with each VMID. When executing a command buffer,
57 * the kernel tells the the ring what VMID to use for that command
58 * buffer. VMIDs are allocated dynamically as commands are submitted.
59 * The userspace drivers maintain their own address space and the kernel
60 * sets up their pages tables accordingly when they submit their
61 * command buffers and a VMID is assigned.
62 * Cayman/Trinity support up to 8 active VMs at any given time;
66 #define START(node) ((node)->start)
67 #define LAST(node) ((node)->last)
69 INTERVAL_TREE_DEFINE(struct amdgpu_bo_va_mapping, rb, uint64_t, __subtree_last,
70 START, LAST, static, amdgpu_vm_it)
76 * struct amdgpu_prt_cb - Helper to disable partial resident texture feature from a fence callback
78 struct amdgpu_prt_cb {
81 * @adev: amdgpu device
83 struct amdgpu_device *adev;
88 struct dma_fence_cb cb;
92 * amdgpu_vm_set_pasid - manage pasid and vm ptr mapping
94 * @adev: amdgpu_device pointer
95 * @vm: amdgpu_vm pointer
96 * @pasid: the pasid the VM is using on this GPU
98 * Set the pasid this VM is using on this GPU, can also be used to remove the
99 * pasid by passing in zero.
102 int amdgpu_vm_set_pasid(struct amdgpu_device *adev, struct amdgpu_vm *vm,
107 if (vm->pasid == pasid)
111 r = xa_err(xa_erase_irq(&adev->vm_manager.pasids, vm->pasid));
119 r = xa_err(xa_store_irq(&adev->vm_manager.pasids, pasid, vm,
132 * vm eviction_lock can be taken in MMU notifiers. Make sure no reclaim-FS
133 * happens while holding this lock anywhere to prevent deadlocks when
134 * an MMU notifier runs in reclaim-FS context.
136 static inline void amdgpu_vm_eviction_lock(struct amdgpu_vm *vm)
138 mutex_lock(&vm->eviction_lock);
139 vm->saved_flags = memalloc_noreclaim_save();
142 static inline int amdgpu_vm_eviction_trylock(struct amdgpu_vm *vm)
144 if (mutex_trylock(&vm->eviction_lock)) {
145 vm->saved_flags = memalloc_noreclaim_save();
151 static inline void amdgpu_vm_eviction_unlock(struct amdgpu_vm *vm)
153 memalloc_noreclaim_restore(vm->saved_flags);
154 mutex_unlock(&vm->eviction_lock);
158 * amdgpu_vm_level_shift - return the addr shift for each level
160 * @adev: amdgpu_device pointer
164 * The number of bits the pfn needs to be right shifted for a level.
166 static unsigned amdgpu_vm_level_shift(struct amdgpu_device *adev,
173 return 9 * (AMDGPU_VM_PDB0 - level) +
174 adev->vm_manager.block_size;
183 * amdgpu_vm_num_entries - return the number of entries in a PD/PT
185 * @adev: amdgpu_device pointer
189 * The number of entries in a page directory or page table.
191 static unsigned amdgpu_vm_num_entries(struct amdgpu_device *adev,
194 unsigned shift = amdgpu_vm_level_shift(adev,
195 adev->vm_manager.root_level);
197 if (level == adev->vm_manager.root_level)
198 /* For the root directory */
199 return round_up(adev->vm_manager.max_pfn, 1ULL << shift)
201 else if (level != AMDGPU_VM_PTB)
202 /* Everything in between */
205 /* For the page tables on the leaves */
206 return AMDGPU_VM_PTE_COUNT(adev);
210 * amdgpu_vm_num_ats_entries - return the number of ATS entries in the root PD
212 * @adev: amdgpu_device pointer
215 * The number of entries in the root page directory which needs the ATS setting.
217 static unsigned amdgpu_vm_num_ats_entries(struct amdgpu_device *adev)
221 shift = amdgpu_vm_level_shift(adev, adev->vm_manager.root_level);
222 return AMDGPU_GMC_HOLE_START >> (shift + AMDGPU_GPU_PAGE_SHIFT);
226 * amdgpu_vm_entries_mask - the mask to get the entry number of a PD/PT
228 * @adev: amdgpu_device pointer
232 * The mask to extract the entry number of a PD/PT from an address.
234 static uint32_t amdgpu_vm_entries_mask(struct amdgpu_device *adev,
237 if (level <= adev->vm_manager.root_level)
239 else if (level != AMDGPU_VM_PTB)
242 return AMDGPU_VM_PTE_COUNT(adev) - 1;
246 * amdgpu_vm_bo_size - returns the size of the BOs in bytes
248 * @adev: amdgpu_device pointer
252 * The size of the BO for a page directory or page table in bytes.
254 static unsigned amdgpu_vm_bo_size(struct amdgpu_device *adev, unsigned level)
256 return AMDGPU_GPU_PAGE_ALIGN(amdgpu_vm_num_entries(adev, level) * 8);
260 * amdgpu_vm_bo_evicted - vm_bo is evicted
262 * @vm_bo: vm_bo which is evicted
264 * State for PDs/PTs and per VM BOs which are not at the location they should
267 static void amdgpu_vm_bo_evicted(struct amdgpu_vm_bo_base *vm_bo)
269 struct amdgpu_vm *vm = vm_bo->vm;
270 struct amdgpu_bo *bo = vm_bo->bo;
273 if (bo->tbo.type == ttm_bo_type_kernel)
274 list_move(&vm_bo->vm_status, &vm->evicted);
276 list_move_tail(&vm_bo->vm_status, &vm->evicted);
279 * amdgpu_vm_bo_moved - vm_bo is moved
281 * @vm_bo: vm_bo which is moved
283 * State for per VM BOs which are moved, but that change is not yet reflected
284 * in the page tables.
286 static void amdgpu_vm_bo_moved(struct amdgpu_vm_bo_base *vm_bo)
288 list_move(&vm_bo->vm_status, &vm_bo->vm->moved);
292 * amdgpu_vm_bo_idle - vm_bo is idle
294 * @vm_bo: vm_bo which is now idle
296 * State for PDs/PTs and per VM BOs which have gone through the state machine
299 static void amdgpu_vm_bo_idle(struct amdgpu_vm_bo_base *vm_bo)
301 list_move(&vm_bo->vm_status, &vm_bo->vm->idle);
302 vm_bo->moved = false;
306 * amdgpu_vm_bo_invalidated - vm_bo is invalidated
308 * @vm_bo: vm_bo which is now invalidated
310 * State for normal BOs which are invalidated and that change not yet reflected
313 static void amdgpu_vm_bo_invalidated(struct amdgpu_vm_bo_base *vm_bo)
315 spin_lock(&vm_bo->vm->invalidated_lock);
316 list_move(&vm_bo->vm_status, &vm_bo->vm->invalidated);
317 spin_unlock(&vm_bo->vm->invalidated_lock);
321 * amdgpu_vm_bo_relocated - vm_bo is reloacted
323 * @vm_bo: vm_bo which is relocated
325 * State for PDs/PTs which needs to update their parent PD.
326 * For the root PD, just move to idle state.
328 static void amdgpu_vm_bo_relocated(struct amdgpu_vm_bo_base *vm_bo)
330 if (vm_bo->bo->parent)
331 list_move(&vm_bo->vm_status, &vm_bo->vm->relocated);
333 amdgpu_vm_bo_idle(vm_bo);
337 * amdgpu_vm_bo_done - vm_bo is done
339 * @vm_bo: vm_bo which is now done
341 * State for normal BOs which are invalidated and that change has been updated
344 static void amdgpu_vm_bo_done(struct amdgpu_vm_bo_base *vm_bo)
346 spin_lock(&vm_bo->vm->invalidated_lock);
347 list_move(&vm_bo->vm_status, &vm_bo->vm->done);
348 spin_unlock(&vm_bo->vm->invalidated_lock);
352 * amdgpu_vm_bo_base_init - Adds bo to the list of bos associated with the vm
354 * @base: base structure for tracking BO usage in a VM
355 * @vm: vm to which bo is to be added
356 * @bo: amdgpu buffer object
358 * Initialize a bo_va_base structure and add it to the appropriate lists
361 static void amdgpu_vm_bo_base_init(struct amdgpu_vm_bo_base *base,
362 struct amdgpu_vm *vm,
363 struct amdgpu_bo *bo)
368 INIT_LIST_HEAD(&base->vm_status);
372 base->next = bo->vm_bo;
375 if (bo->tbo.base.resv != vm->root.bo->tbo.base.resv)
378 vm->bulk_moveable = false;
379 if (bo->tbo.type == ttm_bo_type_kernel && bo->parent)
380 amdgpu_vm_bo_relocated(base);
382 amdgpu_vm_bo_idle(base);
384 if (bo->preferred_domains &
385 amdgpu_mem_type_to_domain(bo->tbo.resource->mem_type))
389 * we checked all the prerequisites, but it looks like this per vm bo
390 * is currently evicted. add the bo to the evicted list to make sure it
391 * is validated on next vm use to avoid fault.
393 amdgpu_vm_bo_evicted(base);
397 * amdgpu_vm_pt_parent - get the parent page directory
399 * @pt: child page table
401 * Helper to get the parent entry for the child page table. NULL if we are at
402 * the root page directory.
404 static struct amdgpu_vm_bo_base *amdgpu_vm_pt_parent(struct amdgpu_vm_bo_base *pt)
406 struct amdgpu_bo *parent = pt->bo->parent;
411 return parent->vm_bo;
415 * amdgpu_vm_pt_cursor - state for for_each_amdgpu_vm_pt
417 struct amdgpu_vm_pt_cursor {
419 struct amdgpu_vm_bo_base *parent;
420 struct amdgpu_vm_bo_base *entry;
425 * amdgpu_vm_pt_start - start PD/PT walk
427 * @adev: amdgpu_device pointer
428 * @vm: amdgpu_vm structure
429 * @start: start address of the walk
430 * @cursor: state to initialize
432 * Initialize a amdgpu_vm_pt_cursor to start a walk.
434 static void amdgpu_vm_pt_start(struct amdgpu_device *adev,
435 struct amdgpu_vm *vm, uint64_t start,
436 struct amdgpu_vm_pt_cursor *cursor)
439 cursor->parent = NULL;
440 cursor->entry = &vm->root;
441 cursor->level = adev->vm_manager.root_level;
445 * amdgpu_vm_pt_descendant - go to child node
447 * @adev: amdgpu_device pointer
448 * @cursor: current state
450 * Walk to the child node of the current node.
452 * True if the walk was possible, false otherwise.
454 static bool amdgpu_vm_pt_descendant(struct amdgpu_device *adev,
455 struct amdgpu_vm_pt_cursor *cursor)
457 unsigned mask, shift, idx;
459 if ((cursor->level == AMDGPU_VM_PTB) || !cursor->entry ||
463 mask = amdgpu_vm_entries_mask(adev, cursor->level);
464 shift = amdgpu_vm_level_shift(adev, cursor->level);
467 idx = (cursor->pfn >> shift) & mask;
468 cursor->parent = cursor->entry;
469 cursor->entry = &to_amdgpu_bo_vm(cursor->entry->bo)->entries[idx];
474 * amdgpu_vm_pt_sibling - go to sibling node
476 * @adev: amdgpu_device pointer
477 * @cursor: current state
479 * Walk to the sibling node of the current node.
481 * True if the walk was possible, false otherwise.
483 static bool amdgpu_vm_pt_sibling(struct amdgpu_device *adev,
484 struct amdgpu_vm_pt_cursor *cursor)
486 unsigned shift, num_entries;
488 /* Root doesn't have a sibling */
492 /* Go to our parents and see if we got a sibling */
493 shift = amdgpu_vm_level_shift(adev, cursor->level - 1);
494 num_entries = amdgpu_vm_num_entries(adev, cursor->level - 1);
496 if (cursor->entry == &to_amdgpu_bo_vm(cursor->parent->bo)->entries[num_entries - 1])
499 cursor->pfn += 1ULL << shift;
500 cursor->pfn &= ~((1ULL << shift) - 1);
506 * amdgpu_vm_pt_ancestor - go to parent node
508 * @cursor: current state
510 * Walk to the parent node of the current node.
512 * True if the walk was possible, false otherwise.
514 static bool amdgpu_vm_pt_ancestor(struct amdgpu_vm_pt_cursor *cursor)
520 cursor->entry = cursor->parent;
521 cursor->parent = amdgpu_vm_pt_parent(cursor->parent);
526 * amdgpu_vm_pt_next - get next PD/PT in hieratchy
528 * @adev: amdgpu_device pointer
529 * @cursor: current state
531 * Walk the PD/PT tree to the next node.
533 static void amdgpu_vm_pt_next(struct amdgpu_device *adev,
534 struct amdgpu_vm_pt_cursor *cursor)
536 /* First try a newborn child */
537 if (amdgpu_vm_pt_descendant(adev, cursor))
540 /* If that didn't worked try to find a sibling */
541 while (!amdgpu_vm_pt_sibling(adev, cursor)) {
542 /* No sibling, go to our parents and grandparents */
543 if (!amdgpu_vm_pt_ancestor(cursor)) {
551 * amdgpu_vm_pt_first_dfs - start a deep first search
553 * @adev: amdgpu_device structure
554 * @vm: amdgpu_vm structure
555 * @start: optional cursor to start with
556 * @cursor: state to initialize
558 * Starts a deep first traversal of the PD/PT tree.
560 static void amdgpu_vm_pt_first_dfs(struct amdgpu_device *adev,
561 struct amdgpu_vm *vm,
562 struct amdgpu_vm_pt_cursor *start,
563 struct amdgpu_vm_pt_cursor *cursor)
568 amdgpu_vm_pt_start(adev, vm, 0, cursor);
569 while (amdgpu_vm_pt_descendant(adev, cursor));
573 * amdgpu_vm_pt_continue_dfs - check if the deep first search should continue
575 * @start: starting point for the search
576 * @entry: current entry
579 * True when the search should continue, false otherwise.
581 static bool amdgpu_vm_pt_continue_dfs(struct amdgpu_vm_pt_cursor *start,
582 struct amdgpu_vm_bo_base *entry)
584 return entry && (!start || entry != start->entry);
588 * amdgpu_vm_pt_next_dfs - get the next node for a deep first search
590 * @adev: amdgpu_device structure
591 * @cursor: current state
593 * Move the cursor to the next node in a deep first search.
595 static void amdgpu_vm_pt_next_dfs(struct amdgpu_device *adev,
596 struct amdgpu_vm_pt_cursor *cursor)
602 cursor->entry = NULL;
603 else if (amdgpu_vm_pt_sibling(adev, cursor))
604 while (amdgpu_vm_pt_descendant(adev, cursor));
606 amdgpu_vm_pt_ancestor(cursor);
610 * for_each_amdgpu_vm_pt_dfs_safe - safe deep first search of all PDs/PTs
612 #define for_each_amdgpu_vm_pt_dfs_safe(adev, vm, start, cursor, entry) \
613 for (amdgpu_vm_pt_first_dfs((adev), (vm), (start), &(cursor)), \
614 (entry) = (cursor).entry, amdgpu_vm_pt_next_dfs((adev), &(cursor));\
615 amdgpu_vm_pt_continue_dfs((start), (entry)); \
616 (entry) = (cursor).entry, amdgpu_vm_pt_next_dfs((adev), &(cursor)))
619 * amdgpu_vm_get_pd_bo - add the VM PD to a validation list
621 * @vm: vm providing the BOs
622 * @validated: head of validation list
623 * @entry: entry to add
625 * Add the page directory to the list of BOs to
626 * validate for command submission.
628 void amdgpu_vm_get_pd_bo(struct amdgpu_vm *vm,
629 struct list_head *validated,
630 struct amdgpu_bo_list_entry *entry)
633 entry->tv.bo = &vm->root.bo->tbo;
634 /* Two for VM updates, one for TTM and one for the CS job */
635 entry->tv.num_shared = 4;
636 entry->user_pages = NULL;
637 list_add(&entry->tv.head, validated);
641 * amdgpu_vm_del_from_lru_notify - update bulk_moveable flag
643 * @bo: BO which was removed from the LRU
645 * Make sure the bulk_moveable flag is updated when a BO is removed from the
648 void amdgpu_vm_del_from_lru_notify(struct ttm_buffer_object *bo)
650 struct amdgpu_bo *abo;
651 struct amdgpu_vm_bo_base *bo_base;
653 if (!amdgpu_bo_is_amdgpu_bo(bo))
659 abo = ttm_to_amdgpu_bo(bo);
662 for (bo_base = abo->vm_bo; bo_base; bo_base = bo_base->next) {
663 struct amdgpu_vm *vm = bo_base->vm;
665 if (abo->tbo.base.resv == vm->root.bo->tbo.base.resv)
666 vm->bulk_moveable = false;
671 * amdgpu_vm_move_to_lru_tail - move all BOs to the end of LRU
673 * @adev: amdgpu device pointer
674 * @vm: vm providing the BOs
676 * Move all BOs to the end of LRU and remember their positions to put them
679 void amdgpu_vm_move_to_lru_tail(struct amdgpu_device *adev,
680 struct amdgpu_vm *vm)
682 struct amdgpu_vm_bo_base *bo_base;
684 if (vm->bulk_moveable) {
685 spin_lock(&adev->mman.bdev.lru_lock);
686 ttm_bo_bulk_move_lru_tail(&vm->lru_bulk_move);
687 spin_unlock(&adev->mman.bdev.lru_lock);
691 memset(&vm->lru_bulk_move, 0, sizeof(vm->lru_bulk_move));
693 spin_lock(&adev->mman.bdev.lru_lock);
694 list_for_each_entry(bo_base, &vm->idle, vm_status) {
695 struct amdgpu_bo *bo = bo_base->bo;
696 struct amdgpu_bo *shadow = amdgpu_bo_shadowed(bo);
701 ttm_bo_move_to_lru_tail(&bo->tbo, bo->tbo.resource,
704 ttm_bo_move_to_lru_tail(&shadow->tbo,
705 shadow->tbo.resource,
708 spin_unlock(&adev->mman.bdev.lru_lock);
710 vm->bulk_moveable = true;
714 * amdgpu_vm_validate_pt_bos - validate the page table BOs
716 * @adev: amdgpu device pointer
717 * @vm: vm providing the BOs
718 * @validate: callback to do the validation
719 * @param: parameter for the validation callback
721 * Validate the page table BOs on command submission if neccessary.
726 int amdgpu_vm_validate_pt_bos(struct amdgpu_device *adev, struct amdgpu_vm *vm,
727 int (*validate)(void *p, struct amdgpu_bo *bo),
730 struct amdgpu_vm_bo_base *bo_base, *tmp;
733 vm->bulk_moveable &= list_empty(&vm->evicted);
735 list_for_each_entry_safe(bo_base, tmp, &vm->evicted, vm_status) {
736 struct amdgpu_bo *bo = bo_base->bo;
737 struct amdgpu_bo *shadow = amdgpu_bo_shadowed(bo);
739 r = validate(param, bo);
743 r = validate(param, shadow);
748 if (bo->tbo.type != ttm_bo_type_kernel) {
749 amdgpu_vm_bo_moved(bo_base);
751 vm->update_funcs->map_table(to_amdgpu_bo_vm(bo));
752 amdgpu_vm_bo_relocated(bo_base);
756 amdgpu_vm_eviction_lock(vm);
757 vm->evicting = false;
758 amdgpu_vm_eviction_unlock(vm);
764 * amdgpu_vm_ready - check VM is ready for updates
768 * Check if all VM PDs/PTs are ready for updates
771 * True if VM is not evicting.
773 bool amdgpu_vm_ready(struct amdgpu_vm *vm)
777 amdgpu_vm_eviction_lock(vm);
779 amdgpu_vm_eviction_unlock(vm);
784 * amdgpu_vm_clear_bo - initially clear the PDs/PTs
786 * @adev: amdgpu_device pointer
787 * @vm: VM to clear BO from
789 * @immediate: use an immediate update
791 * Root PD needs to be reserved when calling this.
794 * 0 on success, errno otherwise.
796 static int amdgpu_vm_clear_bo(struct amdgpu_device *adev,
797 struct amdgpu_vm *vm,
798 struct amdgpu_bo_vm *vmbo,
801 struct ttm_operation_ctx ctx = { true, false };
802 unsigned level = adev->vm_manager.root_level;
803 struct amdgpu_vm_update_params params;
804 struct amdgpu_bo *ancestor = &vmbo->bo;
805 struct amdgpu_bo *bo = &vmbo->bo;
806 unsigned entries, ats_entries;
810 /* Figure out our place in the hierarchy */
811 if (ancestor->parent) {
813 while (ancestor->parent->parent) {
815 ancestor = ancestor->parent;
819 entries = amdgpu_bo_size(bo) / 8;
820 if (!vm->pte_support_ats) {
823 } else if (!bo->parent) {
824 ats_entries = amdgpu_vm_num_ats_entries(adev);
825 ats_entries = min(ats_entries, entries);
826 entries -= ats_entries;
829 struct amdgpu_vm_bo_base *pt;
831 pt = ancestor->vm_bo;
832 ats_entries = amdgpu_vm_num_ats_entries(adev);
833 if ((pt - to_amdgpu_bo_vm(vm->root.bo)->entries) >= ats_entries) {
836 ats_entries = entries;
841 r = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx);
846 struct amdgpu_bo *shadow = vmbo->shadow;
848 r = ttm_bo_validate(&shadow->tbo, &shadow->placement, &ctx);
853 if (!drm_dev_enter(adev_to_drm(adev), &idx))
856 r = vm->update_funcs->map_table(vmbo);
860 memset(¶ms, 0, sizeof(params));
863 params.immediate = immediate;
865 r = vm->update_funcs->prepare(¶ms, NULL, AMDGPU_SYNC_EXPLICIT);
871 uint64_t value = 0, flags;
873 flags = AMDGPU_PTE_DEFAULT_ATC;
874 if (level != AMDGPU_VM_PTB) {
875 /* Handle leaf PDEs as PTEs */
876 flags |= AMDGPU_PDE_PTE;
877 amdgpu_gmc_get_vm_pde(adev, level, &value, &flags);
880 r = vm->update_funcs->update(¶ms, vmbo, addr, 0, ats_entries,
885 addr += ats_entries * 8;
889 uint64_t value = 0, flags = 0;
891 if (adev->asic_type >= CHIP_VEGA10) {
892 if (level != AMDGPU_VM_PTB) {
893 /* Handle leaf PDEs as PTEs */
894 flags |= AMDGPU_PDE_PTE;
895 amdgpu_gmc_get_vm_pde(adev, level,
898 /* Workaround for fault priority problem on GMC9 */
899 flags = AMDGPU_PTE_EXECUTABLE;
903 r = vm->update_funcs->update(¶ms, vmbo, addr, 0, entries,
909 r = vm->update_funcs->commit(¶ms, NULL);
916 * amdgpu_vm_pt_create - create bo for PD/PT
918 * @adev: amdgpu_device pointer
920 * @level: the page table level
921 * @immediate: use a immediate update
922 * @vmbo: pointer to the buffer object pointer
924 static int amdgpu_vm_pt_create(struct amdgpu_device *adev,
925 struct amdgpu_vm *vm,
926 int level, bool immediate,
927 struct amdgpu_bo_vm **vmbo)
929 struct amdgpu_bo_param bp;
930 struct amdgpu_bo *bo;
931 struct dma_resv *resv;
932 unsigned int num_entries;
935 memset(&bp, 0, sizeof(bp));
937 bp.size = amdgpu_vm_bo_size(adev, level);
938 bp.byte_align = AMDGPU_GPU_PAGE_SIZE;
939 bp.domain = AMDGPU_GEM_DOMAIN_VRAM;
940 bp.domain = amdgpu_bo_get_preferred_domain(adev, bp.domain);
941 bp.flags = AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS |
942 AMDGPU_GEM_CREATE_CPU_GTT_USWC;
944 if (level < AMDGPU_VM_PTB)
945 num_entries = amdgpu_vm_num_entries(adev, level);
949 bp.bo_ptr_size = struct_size((*vmbo), entries, num_entries);
951 if (vm->use_cpu_for_update)
952 bp.flags |= AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED;
954 bp.type = ttm_bo_type_kernel;
955 bp.no_wait_gpu = immediate;
957 bp.resv = vm->root.bo->tbo.base.resv;
959 r = amdgpu_bo_create_vm(adev, &bp, vmbo);
964 if (vm->is_compute_context || (adev->flags & AMD_IS_APU)) {
965 (*vmbo)->shadow = NULL;
970 WARN_ON(dma_resv_lock(bo->tbo.base.resv,
973 memset(&bp, 0, sizeof(bp));
974 bp.size = amdgpu_vm_bo_size(adev, level);
975 bp.domain = AMDGPU_GEM_DOMAIN_GTT;
976 bp.flags = AMDGPU_GEM_CREATE_CPU_GTT_USWC;
977 bp.type = ttm_bo_type_kernel;
978 bp.resv = bo->tbo.base.resv;
979 bp.bo_ptr_size = sizeof(struct amdgpu_bo);
981 r = amdgpu_bo_create(adev, &bp, &(*vmbo)->shadow);
984 dma_resv_unlock(bo->tbo.base.resv);
987 amdgpu_bo_unref(&bo);
991 (*vmbo)->shadow->parent = amdgpu_bo_ref(bo);
992 amdgpu_bo_add_to_shadow_list(*vmbo);
998 * amdgpu_vm_alloc_pts - Allocate a specific page table
1000 * @adev: amdgpu_device pointer
1001 * @vm: VM to allocate page tables for
1002 * @cursor: Which page table to allocate
1003 * @immediate: use an immediate update
1005 * Make sure a specific page table or directory is allocated.
1008 * 1 if page table needed to be allocated, 0 if page table was already
1009 * allocated, negative errno if an error occurred.
1011 static int amdgpu_vm_alloc_pts(struct amdgpu_device *adev,
1012 struct amdgpu_vm *vm,
1013 struct amdgpu_vm_pt_cursor *cursor,
1016 struct amdgpu_vm_bo_base *entry = cursor->entry;
1017 struct amdgpu_bo *pt_bo;
1018 struct amdgpu_bo_vm *pt;
1024 r = amdgpu_vm_pt_create(adev, vm, cursor->level, immediate, &pt);
1028 /* Keep a reference to the root directory to avoid
1029 * freeing them up in the wrong order.
1032 pt_bo->parent = amdgpu_bo_ref(cursor->parent->bo);
1033 amdgpu_vm_bo_base_init(entry, vm, pt_bo);
1034 r = amdgpu_vm_clear_bo(adev, vm, pt, immediate);
1041 amdgpu_bo_unref(&pt->shadow);
1042 amdgpu_bo_unref(&pt_bo);
1047 * amdgpu_vm_free_table - fre one PD/PT
1049 * @entry: PDE to free
1051 static void amdgpu_vm_free_table(struct amdgpu_vm_bo_base *entry)
1053 struct amdgpu_bo *shadow;
1057 shadow = amdgpu_bo_shadowed(entry->bo);
1058 entry->bo->vm_bo = NULL;
1059 list_del(&entry->vm_status);
1060 amdgpu_bo_unref(&shadow);
1061 amdgpu_bo_unref(&entry->bo);
1065 * amdgpu_vm_free_pts - free PD/PT levels
1067 * @adev: amdgpu device structure
1068 * @vm: amdgpu vm structure
1069 * @start: optional cursor where to start freeing PDs/PTs
1071 * Free the page directory or page table level and all sub levels.
1073 static void amdgpu_vm_free_pts(struct amdgpu_device *adev,
1074 struct amdgpu_vm *vm,
1075 struct amdgpu_vm_pt_cursor *start)
1077 struct amdgpu_vm_pt_cursor cursor;
1078 struct amdgpu_vm_bo_base *entry;
1080 vm->bulk_moveable = false;
1082 for_each_amdgpu_vm_pt_dfs_safe(adev, vm, start, cursor, entry)
1083 amdgpu_vm_free_table(entry);
1086 amdgpu_vm_free_table(start->entry);
1090 * amdgpu_vm_check_compute_bug - check whether asic has compute vm bug
1092 * @adev: amdgpu_device pointer
1094 void amdgpu_vm_check_compute_bug(struct amdgpu_device *adev)
1096 const struct amdgpu_ip_block *ip_block;
1097 bool has_compute_vm_bug;
1098 struct amdgpu_ring *ring;
1101 has_compute_vm_bug = false;
1103 ip_block = amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_GFX);
1105 /* Compute has a VM bug for GFX version < 7.
1106 Compute has a VM bug for GFX 8 MEC firmware version < 673.*/
1107 if (ip_block->version->major <= 7)
1108 has_compute_vm_bug = true;
1109 else if (ip_block->version->major == 8)
1110 if (adev->gfx.mec_fw_version < 673)
1111 has_compute_vm_bug = true;
1114 for (i = 0; i < adev->num_rings; i++) {
1115 ring = adev->rings[i];
1116 if (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE)
1117 /* only compute rings */
1118 ring->has_compute_vm_bug = has_compute_vm_bug;
1120 ring->has_compute_vm_bug = false;
1125 * amdgpu_vm_need_pipeline_sync - Check if pipe sync is needed for job.
1127 * @ring: ring on which the job will be submitted
1128 * @job: job to submit
1131 * True if sync is needed.
1133 bool amdgpu_vm_need_pipeline_sync(struct amdgpu_ring *ring,
1134 struct amdgpu_job *job)
1136 struct amdgpu_device *adev = ring->adev;
1137 unsigned vmhub = ring->funcs->vmhub;
1138 struct amdgpu_vmid_mgr *id_mgr = &adev->vm_manager.id_mgr[vmhub];
1139 struct amdgpu_vmid *id;
1140 bool gds_switch_needed;
1141 bool vm_flush_needed = job->vm_needs_flush || ring->has_compute_vm_bug;
1145 id = &id_mgr->ids[job->vmid];
1146 gds_switch_needed = ring->funcs->emit_gds_switch && (
1147 id->gds_base != job->gds_base ||
1148 id->gds_size != job->gds_size ||
1149 id->gws_base != job->gws_base ||
1150 id->gws_size != job->gws_size ||
1151 id->oa_base != job->oa_base ||
1152 id->oa_size != job->oa_size);
1154 if (amdgpu_vmid_had_gpu_reset(adev, id))
1157 return vm_flush_needed || gds_switch_needed;
1161 * amdgpu_vm_flush - hardware flush the vm
1163 * @ring: ring to use for flush
1165 * @need_pipe_sync: is pipe sync needed
1167 * Emit a VM flush when it is necessary.
1170 * 0 on success, errno otherwise.
1172 int amdgpu_vm_flush(struct amdgpu_ring *ring, struct amdgpu_job *job,
1173 bool need_pipe_sync)
1175 struct amdgpu_device *adev = ring->adev;
1176 unsigned vmhub = ring->funcs->vmhub;
1177 struct amdgpu_vmid_mgr *id_mgr = &adev->vm_manager.id_mgr[vmhub];
1178 struct amdgpu_vmid *id = &id_mgr->ids[job->vmid];
1179 bool gds_switch_needed = ring->funcs->emit_gds_switch && (
1180 id->gds_base != job->gds_base ||
1181 id->gds_size != job->gds_size ||
1182 id->gws_base != job->gws_base ||
1183 id->gws_size != job->gws_size ||
1184 id->oa_base != job->oa_base ||
1185 id->oa_size != job->oa_size);
1186 bool vm_flush_needed = job->vm_needs_flush;
1187 struct dma_fence *fence = NULL;
1188 bool pasid_mapping_needed = false;
1189 unsigned patch_offset = 0;
1190 bool update_spm_vmid_needed = (job->vm && (job->vm->reserved_vmid[vmhub] != NULL));
1193 if (update_spm_vmid_needed && adev->gfx.rlc.funcs->update_spm_vmid)
1194 adev->gfx.rlc.funcs->update_spm_vmid(adev, job->vmid);
1196 if (amdgpu_vmid_had_gpu_reset(adev, id)) {
1197 gds_switch_needed = true;
1198 vm_flush_needed = true;
1199 pasid_mapping_needed = true;
1202 mutex_lock(&id_mgr->lock);
1203 if (id->pasid != job->pasid || !id->pasid_mapping ||
1204 !dma_fence_is_signaled(id->pasid_mapping))
1205 pasid_mapping_needed = true;
1206 mutex_unlock(&id_mgr->lock);
1208 gds_switch_needed &= !!ring->funcs->emit_gds_switch;
1209 vm_flush_needed &= !!ring->funcs->emit_vm_flush &&
1210 job->vm_pd_addr != AMDGPU_BO_INVALID_OFFSET;
1211 pasid_mapping_needed &= adev->gmc.gmc_funcs->emit_pasid_mapping &&
1212 ring->funcs->emit_wreg;
1214 if (!vm_flush_needed && !gds_switch_needed && !need_pipe_sync)
1217 if (ring->funcs->init_cond_exec)
1218 patch_offset = amdgpu_ring_init_cond_exec(ring);
1221 amdgpu_ring_emit_pipeline_sync(ring);
1223 if (vm_flush_needed) {
1224 trace_amdgpu_vm_flush(ring, job->vmid, job->vm_pd_addr);
1225 amdgpu_ring_emit_vm_flush(ring, job->vmid, job->vm_pd_addr);
1228 if (pasid_mapping_needed)
1229 amdgpu_gmc_emit_pasid_mapping(ring, job->vmid, job->pasid);
1231 if (vm_flush_needed || pasid_mapping_needed) {
1232 r = amdgpu_fence_emit(ring, &fence, NULL, 0);
1237 if (vm_flush_needed) {
1238 mutex_lock(&id_mgr->lock);
1239 dma_fence_put(id->last_flush);
1240 id->last_flush = dma_fence_get(fence);
1241 id->current_gpu_reset_count =
1242 atomic_read(&adev->gpu_reset_counter);
1243 mutex_unlock(&id_mgr->lock);
1246 if (pasid_mapping_needed) {
1247 mutex_lock(&id_mgr->lock);
1248 id->pasid = job->pasid;
1249 dma_fence_put(id->pasid_mapping);
1250 id->pasid_mapping = dma_fence_get(fence);
1251 mutex_unlock(&id_mgr->lock);
1253 dma_fence_put(fence);
1255 if (ring->funcs->emit_gds_switch && gds_switch_needed) {
1256 id->gds_base = job->gds_base;
1257 id->gds_size = job->gds_size;
1258 id->gws_base = job->gws_base;
1259 id->gws_size = job->gws_size;
1260 id->oa_base = job->oa_base;
1261 id->oa_size = job->oa_size;
1262 amdgpu_ring_emit_gds_switch(ring, job->vmid, job->gds_base,
1263 job->gds_size, job->gws_base,
1264 job->gws_size, job->oa_base,
1268 if (ring->funcs->patch_cond_exec)
1269 amdgpu_ring_patch_cond_exec(ring, patch_offset);
1271 /* the double SWITCH_BUFFER here *cannot* be skipped by COND_EXEC */
1272 if (ring->funcs->emit_switch_buffer) {
1273 amdgpu_ring_emit_switch_buffer(ring);
1274 amdgpu_ring_emit_switch_buffer(ring);
1280 * amdgpu_vm_bo_find - find the bo_va for a specific vm & bo
1283 * @bo: requested buffer object
1285 * Find @bo inside the requested vm.
1286 * Search inside the @bos vm list for the requested vm
1287 * Returns the found bo_va or NULL if none is found
1289 * Object has to be reserved!
1292 * Found bo_va or NULL.
1294 struct amdgpu_bo_va *amdgpu_vm_bo_find(struct amdgpu_vm *vm,
1295 struct amdgpu_bo *bo)
1297 struct amdgpu_vm_bo_base *base;
1299 for (base = bo->vm_bo; base; base = base->next) {
1303 return container_of(base, struct amdgpu_bo_va, base);
1309 * amdgpu_vm_map_gart - Resolve gart mapping of addr
1311 * @pages_addr: optional DMA address to use for lookup
1312 * @addr: the unmapped addr
1314 * Look up the physical address of the page that the pte resolves
1318 * The pointer for the page table entry.
1320 uint64_t amdgpu_vm_map_gart(const dma_addr_t *pages_addr, uint64_t addr)
1324 /* page table offset */
1325 result = pages_addr[addr >> PAGE_SHIFT];
1327 /* in case cpu page size != gpu page size*/
1328 result |= addr & (~PAGE_MASK);
1330 result &= 0xFFFFFFFFFFFFF000ULL;
1336 * amdgpu_vm_update_pde - update a single level in the hierarchy
1338 * @params: parameters for the update
1340 * @entry: entry to update
1342 * Makes sure the requested entry in parent is up to date.
1344 static int amdgpu_vm_update_pde(struct amdgpu_vm_update_params *params,
1345 struct amdgpu_vm *vm,
1346 struct amdgpu_vm_bo_base *entry)
1348 struct amdgpu_vm_bo_base *parent = amdgpu_vm_pt_parent(entry);
1349 struct amdgpu_bo *bo = parent->bo, *pbo;
1350 uint64_t pde, pt, flags;
1353 for (level = 0, pbo = bo->parent; pbo; ++level)
1356 level += params->adev->vm_manager.root_level;
1357 amdgpu_gmc_get_pde_for_bo(entry->bo, level, &pt, &flags);
1358 pde = (entry - to_amdgpu_bo_vm(parent->bo)->entries) * 8;
1359 return vm->update_funcs->update(params, to_amdgpu_bo_vm(bo), pde, pt,
1364 * amdgpu_vm_invalidate_pds - mark all PDs as invalid
1366 * @adev: amdgpu_device pointer
1369 * Mark all PD level as invalid after an error.
1371 static void amdgpu_vm_invalidate_pds(struct amdgpu_device *adev,
1372 struct amdgpu_vm *vm)
1374 struct amdgpu_vm_pt_cursor cursor;
1375 struct amdgpu_vm_bo_base *entry;
1377 for_each_amdgpu_vm_pt_dfs_safe(adev, vm, NULL, cursor, entry)
1378 if (entry->bo && !entry->moved)
1379 amdgpu_vm_bo_relocated(entry);
1383 * amdgpu_vm_update_pdes - make sure that all directories are valid
1385 * @adev: amdgpu_device pointer
1387 * @immediate: submit immediately to the paging queue
1389 * Makes sure all directories are up to date.
1392 * 0 for success, error for failure.
1394 int amdgpu_vm_update_pdes(struct amdgpu_device *adev,
1395 struct amdgpu_vm *vm, bool immediate)
1397 struct amdgpu_vm_update_params params;
1400 if (list_empty(&vm->relocated))
1403 if (!drm_dev_enter(adev_to_drm(adev), &idx))
1406 memset(¶ms, 0, sizeof(params));
1409 params.immediate = immediate;
1411 r = vm->update_funcs->prepare(¶ms, NULL, AMDGPU_SYNC_EXPLICIT);
1415 while (!list_empty(&vm->relocated)) {
1416 struct amdgpu_vm_bo_base *entry;
1418 entry = list_first_entry(&vm->relocated,
1419 struct amdgpu_vm_bo_base,
1421 amdgpu_vm_bo_idle(entry);
1423 r = amdgpu_vm_update_pde(¶ms, vm, entry);
1428 r = vm->update_funcs->commit(¶ms, &vm->last_update);
1435 amdgpu_vm_invalidate_pds(adev, vm);
1442 * amdgpu_vm_update_flags - figure out flags for PTE updates
1444 * Make sure to set the right flags for the PTEs at the desired level.
1446 static void amdgpu_vm_update_flags(struct amdgpu_vm_update_params *params,
1447 struct amdgpu_bo_vm *pt, unsigned int level,
1448 uint64_t pe, uint64_t addr,
1449 unsigned int count, uint32_t incr,
1453 if (level != AMDGPU_VM_PTB) {
1454 flags |= AMDGPU_PDE_PTE;
1455 amdgpu_gmc_get_vm_pde(params->adev, level, &addr, &flags);
1457 } else if (params->adev->asic_type >= CHIP_VEGA10 &&
1458 !(flags & AMDGPU_PTE_VALID) &&
1459 !(flags & AMDGPU_PTE_PRT)) {
1461 /* Workaround for fault priority problem on GMC9 */
1462 flags |= AMDGPU_PTE_EXECUTABLE;
1465 params->vm->update_funcs->update(params, pt, pe, addr, count, incr,
1470 * amdgpu_vm_fragment - get fragment for PTEs
1472 * @params: see amdgpu_vm_update_params definition
1473 * @start: first PTE to handle
1474 * @end: last PTE to handle
1475 * @flags: hw mapping flags
1476 * @frag: resulting fragment size
1477 * @frag_end: end of this fragment
1479 * Returns the first possible fragment for the start and end address.
1481 static void amdgpu_vm_fragment(struct amdgpu_vm_update_params *params,
1482 uint64_t start, uint64_t end, uint64_t flags,
1483 unsigned int *frag, uint64_t *frag_end)
1486 * The MC L1 TLB supports variable sized pages, based on a fragment
1487 * field in the PTE. When this field is set to a non-zero value, page
1488 * granularity is increased from 4KB to (1 << (12 + frag)). The PTE
1489 * flags are considered valid for all PTEs within the fragment range
1490 * and corresponding mappings are assumed to be physically contiguous.
1492 * The L1 TLB can store a single PTE for the whole fragment,
1493 * significantly increasing the space available for translation
1494 * caching. This leads to large improvements in throughput when the
1495 * TLB is under pressure.
1497 * The L2 TLB distributes small and large fragments into two
1498 * asymmetric partitions. The large fragment cache is significantly
1499 * larger. Thus, we try to use large fragments wherever possible.
1500 * Userspace can support this by aligning virtual base address and
1501 * allocation size to the fragment size.
1503 * Starting with Vega10 the fragment size only controls the L1. The L2
1504 * is now directly feed with small/huge/giant pages from the walker.
1508 if (params->adev->asic_type < CHIP_VEGA10)
1509 max_frag = params->adev->vm_manager.fragment_size;
1513 /* system pages are non continuously */
1514 if (params->pages_addr) {
1520 /* This intentionally wraps around if no bit is set */
1521 *frag = min((unsigned)ffs(start) - 1, (unsigned)fls64(end - start) - 1);
1522 if (*frag >= max_frag) {
1524 *frag_end = end & ~((1ULL << max_frag) - 1);
1526 *frag_end = start + (1 << *frag);
1531 * amdgpu_vm_update_ptes - make sure that page tables are valid
1533 * @params: see amdgpu_vm_update_params definition
1534 * @start: start of GPU address range
1535 * @end: end of GPU address range
1536 * @dst: destination address to map to, the next dst inside the function
1537 * @flags: mapping flags
1539 * Update the page tables in the range @start - @end.
1542 * 0 for success, -EINVAL for failure.
1544 static int amdgpu_vm_update_ptes(struct amdgpu_vm_update_params *params,
1545 uint64_t start, uint64_t end,
1546 uint64_t dst, uint64_t flags)
1548 struct amdgpu_device *adev = params->adev;
1549 struct amdgpu_vm_pt_cursor cursor;
1550 uint64_t frag_start = start, frag_end;
1554 /* figure out the initial fragment */
1555 amdgpu_vm_fragment(params, frag_start, end, flags, &frag, &frag_end);
1557 /* walk over the address space and update the PTs */
1558 amdgpu_vm_pt_start(adev, params->vm, start, &cursor);
1559 while (cursor.pfn < end) {
1560 unsigned shift, parent_shift, mask;
1561 uint64_t incr, entry_end, pe_start;
1562 struct amdgpu_bo *pt;
1564 if (!params->unlocked) {
1565 /* make sure that the page tables covering the
1566 * address range are actually allocated
1568 r = amdgpu_vm_alloc_pts(params->adev, params->vm,
1569 &cursor, params->immediate);
1574 shift = amdgpu_vm_level_shift(adev, cursor.level);
1575 parent_shift = amdgpu_vm_level_shift(adev, cursor.level - 1);
1576 if (params->unlocked) {
1577 /* Unlocked updates are only allowed on the leaves */
1578 if (amdgpu_vm_pt_descendant(adev, &cursor))
1580 } else if (adev->asic_type < CHIP_VEGA10 &&
1581 (flags & AMDGPU_PTE_VALID)) {
1582 /* No huge page support before GMC v9 */
1583 if (cursor.level != AMDGPU_VM_PTB) {
1584 if (!amdgpu_vm_pt_descendant(adev, &cursor))
1588 } else if (frag < shift) {
1589 /* We can't use this level when the fragment size is
1590 * smaller than the address shift. Go to the next
1591 * child entry and try again.
1593 if (amdgpu_vm_pt_descendant(adev, &cursor))
1595 } else if (frag >= parent_shift) {
1596 /* If the fragment size is even larger than the parent
1597 * shift we should go up one level and check it again.
1599 if (!amdgpu_vm_pt_ancestor(&cursor))
1604 pt = cursor.entry->bo;
1606 /* We need all PDs and PTs for mapping something, */
1607 if (flags & AMDGPU_PTE_VALID)
1610 /* but unmapping something can happen at a higher
1613 if (!amdgpu_vm_pt_ancestor(&cursor))
1616 pt = cursor.entry->bo;
1617 shift = parent_shift;
1618 frag_end = max(frag_end, ALIGN(frag_start + 1,
1622 /* Looks good so far, calculate parameters for the update */
1623 incr = (uint64_t)AMDGPU_GPU_PAGE_SIZE << shift;
1624 mask = amdgpu_vm_entries_mask(adev, cursor.level);
1625 pe_start = ((cursor.pfn >> shift) & mask) * 8;
1626 entry_end = ((uint64_t)mask + 1) << shift;
1627 entry_end += cursor.pfn & ~(entry_end - 1);
1628 entry_end = min(entry_end, end);
1631 struct amdgpu_vm *vm = params->vm;
1632 uint64_t upd_end = min(entry_end, frag_end);
1633 unsigned nptes = (upd_end - frag_start) >> shift;
1634 uint64_t upd_flags = flags | AMDGPU_PTE_FRAG(frag);
1636 /* This can happen when we set higher level PDs to
1637 * silent to stop fault floods.
1639 nptes = max(nptes, 1u);
1641 trace_amdgpu_vm_update_ptes(params, frag_start, upd_end,
1642 nptes, dst, incr, upd_flags,
1644 vm->immediate.fence_context);
1645 amdgpu_vm_update_flags(params, to_amdgpu_bo_vm(pt),
1646 cursor.level, pe_start, dst,
1647 nptes, incr, upd_flags);
1649 pe_start += nptes * 8;
1650 dst += nptes * incr;
1652 frag_start = upd_end;
1653 if (frag_start >= frag_end) {
1654 /* figure out the next fragment */
1655 amdgpu_vm_fragment(params, frag_start, end,
1656 flags, &frag, &frag_end);
1660 } while (frag_start < entry_end);
1662 if (amdgpu_vm_pt_descendant(adev, &cursor)) {
1663 /* Free all child entries.
1664 * Update the tables with the flags and addresses and free up subsequent
1665 * tables in the case of huge pages or freed up areas.
1666 * This is the maximum you can free, because all other page tables are not
1667 * completely covered by the range and so potentially still in use.
1669 while (cursor.pfn < frag_start) {
1670 /* Make sure previous mapping is freed */
1671 if (cursor.entry->bo) {
1672 params->table_freed = true;
1673 amdgpu_vm_free_pts(adev, params->vm, &cursor);
1675 amdgpu_vm_pt_next(adev, &cursor);
1678 } else if (frag >= shift) {
1679 /* or just move on to the next on the same level. */
1680 amdgpu_vm_pt_next(adev, &cursor);
1688 * amdgpu_vm_bo_update_mapping - update a mapping in the vm page table
1690 * @adev: amdgpu_device pointer of the VM
1691 * @bo_adev: amdgpu_device pointer of the mapped BO
1693 * @immediate: immediate submission in a page fault
1694 * @unlocked: unlocked invalidation during MM callback
1695 * @resv: fences we need to sync to
1696 * @start: start of mapped range
1697 * @last: last mapped entry
1698 * @flags: flags for the entries
1699 * @offset: offset into nodes and pages_addr
1700 * @res: ttm_resource to map
1701 * @pages_addr: DMA addresses to use for mapping
1702 * @fence: optional resulting fence
1703 * @table_freed: return true if page table is freed
1705 * Fill in the page table entries between @start and @last.
1708 * 0 for success, -EINVAL for failure.
1710 int amdgpu_vm_bo_update_mapping(struct amdgpu_device *adev,
1711 struct amdgpu_device *bo_adev,
1712 struct amdgpu_vm *vm, bool immediate,
1713 bool unlocked, struct dma_resv *resv,
1714 uint64_t start, uint64_t last,
1715 uint64_t flags, uint64_t offset,
1716 struct ttm_resource *res,
1717 dma_addr_t *pages_addr,
1718 struct dma_fence **fence,
1721 struct amdgpu_vm_update_params params;
1722 struct amdgpu_res_cursor cursor;
1723 enum amdgpu_sync_mode sync_mode;
1726 if (!drm_dev_enter(adev_to_drm(adev), &idx))
1729 memset(¶ms, 0, sizeof(params));
1732 params.immediate = immediate;
1733 params.pages_addr = pages_addr;
1734 params.unlocked = unlocked;
1736 /* Implicitly sync to command submissions in the same VM before
1737 * unmapping. Sync to moving fences before mapping.
1739 if (!(flags & AMDGPU_PTE_VALID))
1740 sync_mode = AMDGPU_SYNC_EQ_OWNER;
1742 sync_mode = AMDGPU_SYNC_EXPLICIT;
1744 amdgpu_vm_eviction_lock(vm);
1750 if (!unlocked && !dma_fence_is_signaled(vm->last_unlocked)) {
1751 struct dma_fence *tmp = dma_fence_get_stub();
1753 amdgpu_bo_fence(vm->root.bo, vm->last_unlocked, true);
1754 swap(vm->last_unlocked, tmp);
1758 r = vm->update_funcs->prepare(¶ms, resv, sync_mode);
1762 amdgpu_res_first(pages_addr ? NULL : res, offset,
1763 (last - start + 1) * AMDGPU_GPU_PAGE_SIZE, &cursor);
1764 while (cursor.remaining) {
1765 uint64_t tmp, num_entries, addr;
1767 num_entries = cursor.size >> AMDGPU_GPU_PAGE_SHIFT;
1769 bool contiguous = true;
1771 if (num_entries > AMDGPU_GPU_PAGES_IN_CPU_PAGE) {
1772 uint64_t pfn = cursor.start >> PAGE_SHIFT;
1775 contiguous = pages_addr[pfn + 1] ==
1776 pages_addr[pfn] + PAGE_SIZE;
1779 AMDGPU_GPU_PAGES_IN_CPU_PAGE;
1780 for (count = 2; count < tmp; ++count) {
1781 uint64_t idx = pfn + count;
1783 if (contiguous != (pages_addr[idx] ==
1784 pages_addr[idx - 1] + PAGE_SIZE))
1787 num_entries = count *
1788 AMDGPU_GPU_PAGES_IN_CPU_PAGE;
1792 addr = cursor.start;
1793 params.pages_addr = pages_addr;
1795 addr = pages_addr[cursor.start >> PAGE_SHIFT];
1796 params.pages_addr = NULL;
1799 } else if (flags & (AMDGPU_PTE_VALID | AMDGPU_PTE_PRT)) {
1800 addr = bo_adev->vm_manager.vram_base_offset +
1806 tmp = start + num_entries;
1807 r = amdgpu_vm_update_ptes(¶ms, start, tmp, addr, flags);
1811 amdgpu_res_next(&cursor, num_entries * AMDGPU_GPU_PAGE_SIZE);
1815 r = vm->update_funcs->commit(¶ms, fence);
1818 *table_freed = *table_freed || params.table_freed;
1821 amdgpu_vm_eviction_unlock(vm);
1826 void amdgpu_vm_get_memory(struct amdgpu_vm *vm, uint64_t *vram_mem,
1827 uint64_t *gtt_mem, uint64_t *cpu_mem)
1829 struct amdgpu_bo_va *bo_va, *tmp;
1831 list_for_each_entry_safe(bo_va, tmp, &vm->idle, base.vm_status) {
1832 if (!bo_va->base.bo)
1834 amdgpu_bo_get_memory(bo_va->base.bo, vram_mem,
1837 list_for_each_entry_safe(bo_va, tmp, &vm->evicted, base.vm_status) {
1838 if (!bo_va->base.bo)
1840 amdgpu_bo_get_memory(bo_va->base.bo, vram_mem,
1843 list_for_each_entry_safe(bo_va, tmp, &vm->relocated, base.vm_status) {
1844 if (!bo_va->base.bo)
1846 amdgpu_bo_get_memory(bo_va->base.bo, vram_mem,
1849 list_for_each_entry_safe(bo_va, tmp, &vm->moved, base.vm_status) {
1850 if (!bo_va->base.bo)
1852 amdgpu_bo_get_memory(bo_va->base.bo, vram_mem,
1855 spin_lock(&vm->invalidated_lock);
1856 list_for_each_entry_safe(bo_va, tmp, &vm->invalidated, base.vm_status) {
1857 if (!bo_va->base.bo)
1859 amdgpu_bo_get_memory(bo_va->base.bo, vram_mem,
1862 list_for_each_entry_safe(bo_va, tmp, &vm->done, base.vm_status) {
1863 if (!bo_va->base.bo)
1865 amdgpu_bo_get_memory(bo_va->base.bo, vram_mem,
1868 spin_unlock(&vm->invalidated_lock);
1871 * amdgpu_vm_bo_update - update all BO mappings in the vm page table
1873 * @adev: amdgpu_device pointer
1874 * @bo_va: requested BO and VM object
1875 * @clear: if true clear the entries
1876 * @table_freed: return true if page table is freed
1878 * Fill in the page table entries for @bo_va.
1881 * 0 for success, -EINVAL for failure.
1883 int amdgpu_vm_bo_update(struct amdgpu_device *adev, struct amdgpu_bo_va *bo_va,
1884 bool clear, bool *table_freed)
1886 struct amdgpu_bo *bo = bo_va->base.bo;
1887 struct amdgpu_vm *vm = bo_va->base.vm;
1888 struct amdgpu_bo_va_mapping *mapping;
1889 dma_addr_t *pages_addr = NULL;
1890 struct ttm_resource *mem;
1891 struct dma_fence **last_update;
1892 struct dma_resv *resv;
1894 struct amdgpu_device *bo_adev = adev;
1899 resv = vm->root.bo->tbo.base.resv;
1901 struct drm_gem_object *obj = &bo->tbo.base;
1903 resv = bo->tbo.base.resv;
1904 if (obj->import_attach && bo_va->is_xgmi) {
1905 struct dma_buf *dma_buf = obj->import_attach->dmabuf;
1906 struct drm_gem_object *gobj = dma_buf->priv;
1907 struct amdgpu_bo *abo = gem_to_amdgpu_bo(gobj);
1909 if (abo->tbo.resource->mem_type == TTM_PL_VRAM)
1910 bo = gem_to_amdgpu_bo(gobj);
1912 mem = bo->tbo.resource;
1913 if (mem->mem_type == TTM_PL_TT ||
1914 mem->mem_type == AMDGPU_PL_PREEMPT)
1915 pages_addr = bo->tbo.ttm->dma_address;
1919 flags = amdgpu_ttm_tt_pte_flags(adev, bo->tbo.ttm, mem);
1921 if (amdgpu_bo_encrypted(bo))
1922 flags |= AMDGPU_PTE_TMZ;
1924 bo_adev = amdgpu_ttm_adev(bo->tbo.bdev);
1929 if (clear || (bo && bo->tbo.base.resv ==
1930 vm->root.bo->tbo.base.resv))
1931 last_update = &vm->last_update;
1933 last_update = &bo_va->last_pt_update;
1935 if (!clear && bo_va->base.moved) {
1936 bo_va->base.moved = false;
1937 list_splice_init(&bo_va->valids, &bo_va->invalids);
1939 } else if (bo_va->cleared != clear) {
1940 list_splice_init(&bo_va->valids, &bo_va->invalids);
1943 list_for_each_entry(mapping, &bo_va->invalids, list) {
1944 uint64_t update_flags = flags;
1946 /* normally,bo_va->flags only contians READABLE and WIRTEABLE bit go here
1947 * but in case of something, we filter the flags in first place
1949 if (!(mapping->flags & AMDGPU_PTE_READABLE))
1950 update_flags &= ~AMDGPU_PTE_READABLE;
1951 if (!(mapping->flags & AMDGPU_PTE_WRITEABLE))
1952 update_flags &= ~AMDGPU_PTE_WRITEABLE;
1954 /* Apply ASIC specific mapping flags */
1955 amdgpu_gmc_get_vm_pte(adev, mapping, &update_flags);
1957 trace_amdgpu_vm_bo_update(mapping);
1959 r = amdgpu_vm_bo_update_mapping(adev, bo_adev, vm, false, false,
1960 resv, mapping->start,
1961 mapping->last, update_flags,
1962 mapping->offset, mem,
1963 pages_addr, last_update, table_freed);
1968 /* If the BO is not in its preferred location add it back to
1969 * the evicted list so that it gets validated again on the
1970 * next command submission.
1972 if (bo && bo->tbo.base.resv == vm->root.bo->tbo.base.resv) {
1973 uint32_t mem_type = bo->tbo.resource->mem_type;
1975 if (!(bo->preferred_domains &
1976 amdgpu_mem_type_to_domain(mem_type)))
1977 amdgpu_vm_bo_evicted(&bo_va->base);
1979 amdgpu_vm_bo_idle(&bo_va->base);
1981 amdgpu_vm_bo_done(&bo_va->base);
1984 list_splice_init(&bo_va->invalids, &bo_va->valids);
1985 bo_va->cleared = clear;
1987 if (trace_amdgpu_vm_bo_mapping_enabled()) {
1988 list_for_each_entry(mapping, &bo_va->valids, list)
1989 trace_amdgpu_vm_bo_mapping(mapping);
1996 * amdgpu_vm_update_prt_state - update the global PRT state
1998 * @adev: amdgpu_device pointer
2000 static void amdgpu_vm_update_prt_state(struct amdgpu_device *adev)
2002 unsigned long flags;
2005 spin_lock_irqsave(&adev->vm_manager.prt_lock, flags);
2006 enable = !!atomic_read(&adev->vm_manager.num_prt_users);
2007 adev->gmc.gmc_funcs->set_prt(adev, enable);
2008 spin_unlock_irqrestore(&adev->vm_manager.prt_lock, flags);
2012 * amdgpu_vm_prt_get - add a PRT user
2014 * @adev: amdgpu_device pointer
2016 static void amdgpu_vm_prt_get(struct amdgpu_device *adev)
2018 if (!adev->gmc.gmc_funcs->set_prt)
2021 if (atomic_inc_return(&adev->vm_manager.num_prt_users) == 1)
2022 amdgpu_vm_update_prt_state(adev);
2026 * amdgpu_vm_prt_put - drop a PRT user
2028 * @adev: amdgpu_device pointer
2030 static void amdgpu_vm_prt_put(struct amdgpu_device *adev)
2032 if (atomic_dec_return(&adev->vm_manager.num_prt_users) == 0)
2033 amdgpu_vm_update_prt_state(adev);
2037 * amdgpu_vm_prt_cb - callback for updating the PRT status
2039 * @fence: fence for the callback
2040 * @_cb: the callback function
2042 static void amdgpu_vm_prt_cb(struct dma_fence *fence, struct dma_fence_cb *_cb)
2044 struct amdgpu_prt_cb *cb = container_of(_cb, struct amdgpu_prt_cb, cb);
2046 amdgpu_vm_prt_put(cb->adev);
2051 * amdgpu_vm_add_prt_cb - add callback for updating the PRT status
2053 * @adev: amdgpu_device pointer
2054 * @fence: fence for the callback
2056 static void amdgpu_vm_add_prt_cb(struct amdgpu_device *adev,
2057 struct dma_fence *fence)
2059 struct amdgpu_prt_cb *cb;
2061 if (!adev->gmc.gmc_funcs->set_prt)
2064 cb = kmalloc(sizeof(struct amdgpu_prt_cb), GFP_KERNEL);
2066 /* Last resort when we are OOM */
2068 dma_fence_wait(fence, false);
2070 amdgpu_vm_prt_put(adev);
2073 if (!fence || dma_fence_add_callback(fence, &cb->cb,
2075 amdgpu_vm_prt_cb(fence, &cb->cb);
2080 * amdgpu_vm_free_mapping - free a mapping
2082 * @adev: amdgpu_device pointer
2084 * @mapping: mapping to be freed
2085 * @fence: fence of the unmap operation
2087 * Free a mapping and make sure we decrease the PRT usage count if applicable.
2089 static void amdgpu_vm_free_mapping(struct amdgpu_device *adev,
2090 struct amdgpu_vm *vm,
2091 struct amdgpu_bo_va_mapping *mapping,
2092 struct dma_fence *fence)
2094 if (mapping->flags & AMDGPU_PTE_PRT)
2095 amdgpu_vm_add_prt_cb(adev, fence);
2100 * amdgpu_vm_prt_fini - finish all prt mappings
2102 * @adev: amdgpu_device pointer
2105 * Register a cleanup callback to disable PRT support after VM dies.
2107 static void amdgpu_vm_prt_fini(struct amdgpu_device *adev, struct amdgpu_vm *vm)
2109 struct dma_resv *resv = vm->root.bo->tbo.base.resv;
2110 struct dma_resv_iter cursor;
2111 struct dma_fence *fence;
2113 dma_resv_for_each_fence(&cursor, resv, true, fence) {
2114 /* Add a callback for each fence in the reservation object */
2115 amdgpu_vm_prt_get(adev);
2116 amdgpu_vm_add_prt_cb(adev, fence);
2121 * amdgpu_vm_clear_freed - clear freed BOs in the PT
2123 * @adev: amdgpu_device pointer
2125 * @fence: optional resulting fence (unchanged if no work needed to be done
2126 * or if an error occurred)
2128 * Make sure all freed BOs are cleared in the PT.
2129 * PTs have to be reserved and mutex must be locked!
2135 int amdgpu_vm_clear_freed(struct amdgpu_device *adev,
2136 struct amdgpu_vm *vm,
2137 struct dma_fence **fence)
2139 struct dma_resv *resv = vm->root.bo->tbo.base.resv;
2140 struct amdgpu_bo_va_mapping *mapping;
2141 uint64_t init_pte_value = 0;
2142 struct dma_fence *f = NULL;
2145 while (!list_empty(&vm->freed)) {
2146 mapping = list_first_entry(&vm->freed,
2147 struct amdgpu_bo_va_mapping, list);
2148 list_del(&mapping->list);
2150 if (vm->pte_support_ats &&
2151 mapping->start < AMDGPU_GMC_HOLE_START)
2152 init_pte_value = AMDGPU_PTE_DEFAULT_ATC;
2154 r = amdgpu_vm_bo_update_mapping(adev, adev, vm, false, false,
2155 resv, mapping->start,
2156 mapping->last, init_pte_value,
2157 0, NULL, NULL, &f, NULL);
2158 amdgpu_vm_free_mapping(adev, vm, mapping, f);
2166 dma_fence_put(*fence);
2177 * amdgpu_vm_handle_moved - handle moved BOs in the PT
2179 * @adev: amdgpu_device pointer
2182 * Make sure all BOs which are moved are updated in the PTs.
2187 * PTs have to be reserved!
2189 int amdgpu_vm_handle_moved(struct amdgpu_device *adev,
2190 struct amdgpu_vm *vm)
2192 struct amdgpu_bo_va *bo_va, *tmp;
2193 struct dma_resv *resv;
2197 list_for_each_entry_safe(bo_va, tmp, &vm->moved, base.vm_status) {
2198 /* Per VM BOs never need to bo cleared in the page tables */
2199 r = amdgpu_vm_bo_update(adev, bo_va, false, NULL);
2204 spin_lock(&vm->invalidated_lock);
2205 while (!list_empty(&vm->invalidated)) {
2206 bo_va = list_first_entry(&vm->invalidated, struct amdgpu_bo_va,
2208 resv = bo_va->base.bo->tbo.base.resv;
2209 spin_unlock(&vm->invalidated_lock);
2211 /* Try to reserve the BO to avoid clearing its ptes */
2212 if (!amdgpu_vm_debug && dma_resv_trylock(resv))
2214 /* Somebody else is using the BO right now */
2218 r = amdgpu_vm_bo_update(adev, bo_va, clear, NULL);
2223 dma_resv_unlock(resv);
2224 spin_lock(&vm->invalidated_lock);
2226 spin_unlock(&vm->invalidated_lock);
2232 * amdgpu_vm_bo_add - add a bo to a specific vm
2234 * @adev: amdgpu_device pointer
2236 * @bo: amdgpu buffer object
2238 * Add @bo into the requested vm.
2239 * Add @bo to the list of bos associated with the vm
2242 * Newly added bo_va or NULL for failure
2244 * Object has to be reserved!
2246 struct amdgpu_bo_va *amdgpu_vm_bo_add(struct amdgpu_device *adev,
2247 struct amdgpu_vm *vm,
2248 struct amdgpu_bo *bo)
2250 struct amdgpu_bo_va *bo_va;
2252 bo_va = kzalloc(sizeof(struct amdgpu_bo_va), GFP_KERNEL);
2253 if (bo_va == NULL) {
2256 amdgpu_vm_bo_base_init(&bo_va->base, vm, bo);
2258 bo_va->ref_count = 1;
2259 INIT_LIST_HEAD(&bo_va->valids);
2260 INIT_LIST_HEAD(&bo_va->invalids);
2265 if (amdgpu_dmabuf_is_xgmi_accessible(adev, bo)) {
2266 bo_va->is_xgmi = true;
2267 /* Power up XGMI if it can be potentially used */
2268 amdgpu_xgmi_set_pstate(adev, AMDGPU_XGMI_PSTATE_MAX_VEGA20);
2276 * amdgpu_vm_bo_insert_map - insert a new mapping
2278 * @adev: amdgpu_device pointer
2279 * @bo_va: bo_va to store the address
2280 * @mapping: the mapping to insert
2282 * Insert a new mapping into all structures.
2284 static void amdgpu_vm_bo_insert_map(struct amdgpu_device *adev,
2285 struct amdgpu_bo_va *bo_va,
2286 struct amdgpu_bo_va_mapping *mapping)
2288 struct amdgpu_vm *vm = bo_va->base.vm;
2289 struct amdgpu_bo *bo = bo_va->base.bo;
2291 mapping->bo_va = bo_va;
2292 list_add(&mapping->list, &bo_va->invalids);
2293 amdgpu_vm_it_insert(mapping, &vm->va);
2295 if (mapping->flags & AMDGPU_PTE_PRT)
2296 amdgpu_vm_prt_get(adev);
2298 if (bo && bo->tbo.base.resv == vm->root.bo->tbo.base.resv &&
2299 !bo_va->base.moved) {
2300 list_move(&bo_va->base.vm_status, &vm->moved);
2302 trace_amdgpu_vm_bo_map(bo_va, mapping);
2306 * amdgpu_vm_bo_map - map bo inside a vm
2308 * @adev: amdgpu_device pointer
2309 * @bo_va: bo_va to store the address
2310 * @saddr: where to map the BO
2311 * @offset: requested offset in the BO
2312 * @size: BO size in bytes
2313 * @flags: attributes of pages (read/write/valid/etc.)
2315 * Add a mapping of the BO at the specefied addr into the VM.
2318 * 0 for success, error for failure.
2320 * Object has to be reserved and unreserved outside!
2322 int amdgpu_vm_bo_map(struct amdgpu_device *adev,
2323 struct amdgpu_bo_va *bo_va,
2324 uint64_t saddr, uint64_t offset,
2325 uint64_t size, uint64_t flags)
2327 struct amdgpu_bo_va_mapping *mapping, *tmp;
2328 struct amdgpu_bo *bo = bo_va->base.bo;
2329 struct amdgpu_vm *vm = bo_va->base.vm;
2332 /* validate the parameters */
2333 if (saddr & ~PAGE_MASK || offset & ~PAGE_MASK ||
2334 size == 0 || size & ~PAGE_MASK)
2337 /* make sure object fit at this offset */
2338 eaddr = saddr + size - 1;
2339 if (saddr >= eaddr ||
2340 (bo && offset + size > amdgpu_bo_size(bo)) ||
2341 (eaddr >= adev->vm_manager.max_pfn << AMDGPU_GPU_PAGE_SHIFT))
2344 saddr /= AMDGPU_GPU_PAGE_SIZE;
2345 eaddr /= AMDGPU_GPU_PAGE_SIZE;
2347 tmp = amdgpu_vm_it_iter_first(&vm->va, saddr, eaddr);
2349 /* bo and tmp overlap, invalid addr */
2350 dev_err(adev->dev, "bo %p va 0x%010Lx-0x%010Lx conflict with "
2351 "0x%010Lx-0x%010Lx\n", bo, saddr, eaddr,
2352 tmp->start, tmp->last + 1);
2356 mapping = kmalloc(sizeof(*mapping), GFP_KERNEL);
2360 mapping->start = saddr;
2361 mapping->last = eaddr;
2362 mapping->offset = offset;
2363 mapping->flags = flags;
2365 amdgpu_vm_bo_insert_map(adev, bo_va, mapping);
2371 * amdgpu_vm_bo_replace_map - map bo inside a vm, replacing existing mappings
2373 * @adev: amdgpu_device pointer
2374 * @bo_va: bo_va to store the address
2375 * @saddr: where to map the BO
2376 * @offset: requested offset in the BO
2377 * @size: BO size in bytes
2378 * @flags: attributes of pages (read/write/valid/etc.)
2380 * Add a mapping of the BO at the specefied addr into the VM. Replace existing
2381 * mappings as we do so.
2384 * 0 for success, error for failure.
2386 * Object has to be reserved and unreserved outside!
2388 int amdgpu_vm_bo_replace_map(struct amdgpu_device *adev,
2389 struct amdgpu_bo_va *bo_va,
2390 uint64_t saddr, uint64_t offset,
2391 uint64_t size, uint64_t flags)
2393 struct amdgpu_bo_va_mapping *mapping;
2394 struct amdgpu_bo *bo = bo_va->base.bo;
2398 /* validate the parameters */
2399 if (saddr & ~PAGE_MASK || offset & ~PAGE_MASK ||
2400 size == 0 || size & ~PAGE_MASK)
2403 /* make sure object fit at this offset */
2404 eaddr = saddr + size - 1;
2405 if (saddr >= eaddr ||
2406 (bo && offset + size > amdgpu_bo_size(bo)) ||
2407 (eaddr >= adev->vm_manager.max_pfn << AMDGPU_GPU_PAGE_SHIFT))
2410 /* Allocate all the needed memory */
2411 mapping = kmalloc(sizeof(*mapping), GFP_KERNEL);
2415 r = amdgpu_vm_bo_clear_mappings(adev, bo_va->base.vm, saddr, size);
2421 saddr /= AMDGPU_GPU_PAGE_SIZE;
2422 eaddr /= AMDGPU_GPU_PAGE_SIZE;
2424 mapping->start = saddr;
2425 mapping->last = eaddr;
2426 mapping->offset = offset;
2427 mapping->flags = flags;
2429 amdgpu_vm_bo_insert_map(adev, bo_va, mapping);
2435 * amdgpu_vm_bo_unmap - remove bo mapping from vm
2437 * @adev: amdgpu_device pointer
2438 * @bo_va: bo_va to remove the address from
2439 * @saddr: where to the BO is mapped
2441 * Remove a mapping of the BO at the specefied addr from the VM.
2444 * 0 for success, error for failure.
2446 * Object has to be reserved and unreserved outside!
2448 int amdgpu_vm_bo_unmap(struct amdgpu_device *adev,
2449 struct amdgpu_bo_va *bo_va,
2452 struct amdgpu_bo_va_mapping *mapping;
2453 struct amdgpu_vm *vm = bo_va->base.vm;
2456 saddr /= AMDGPU_GPU_PAGE_SIZE;
2458 list_for_each_entry(mapping, &bo_va->valids, list) {
2459 if (mapping->start == saddr)
2463 if (&mapping->list == &bo_va->valids) {
2466 list_for_each_entry(mapping, &bo_va->invalids, list) {
2467 if (mapping->start == saddr)
2471 if (&mapping->list == &bo_va->invalids)
2475 list_del(&mapping->list);
2476 amdgpu_vm_it_remove(mapping, &vm->va);
2477 mapping->bo_va = NULL;
2478 trace_amdgpu_vm_bo_unmap(bo_va, mapping);
2481 list_add(&mapping->list, &vm->freed);
2483 amdgpu_vm_free_mapping(adev, vm, mapping,
2484 bo_va->last_pt_update);
2490 * amdgpu_vm_bo_clear_mappings - remove all mappings in a specific range
2492 * @adev: amdgpu_device pointer
2493 * @vm: VM structure to use
2494 * @saddr: start of the range
2495 * @size: size of the range
2497 * Remove all mappings in a range, split them as appropriate.
2500 * 0 for success, error for failure.
2502 int amdgpu_vm_bo_clear_mappings(struct amdgpu_device *adev,
2503 struct amdgpu_vm *vm,
2504 uint64_t saddr, uint64_t size)
2506 struct amdgpu_bo_va_mapping *before, *after, *tmp, *next;
2510 eaddr = saddr + size - 1;
2511 saddr /= AMDGPU_GPU_PAGE_SIZE;
2512 eaddr /= AMDGPU_GPU_PAGE_SIZE;
2514 /* Allocate all the needed memory */
2515 before = kzalloc(sizeof(*before), GFP_KERNEL);
2518 INIT_LIST_HEAD(&before->list);
2520 after = kzalloc(sizeof(*after), GFP_KERNEL);
2525 INIT_LIST_HEAD(&after->list);
2527 /* Now gather all removed mappings */
2528 tmp = amdgpu_vm_it_iter_first(&vm->va, saddr, eaddr);
2530 /* Remember mapping split at the start */
2531 if (tmp->start < saddr) {
2532 before->start = tmp->start;
2533 before->last = saddr - 1;
2534 before->offset = tmp->offset;
2535 before->flags = tmp->flags;
2536 before->bo_va = tmp->bo_va;
2537 list_add(&before->list, &tmp->bo_va->invalids);
2540 /* Remember mapping split at the end */
2541 if (tmp->last > eaddr) {
2542 after->start = eaddr + 1;
2543 after->last = tmp->last;
2544 after->offset = tmp->offset;
2545 after->offset += (after->start - tmp->start) << PAGE_SHIFT;
2546 after->flags = tmp->flags;
2547 after->bo_va = tmp->bo_va;
2548 list_add(&after->list, &tmp->bo_va->invalids);
2551 list_del(&tmp->list);
2552 list_add(&tmp->list, &removed);
2554 tmp = amdgpu_vm_it_iter_next(tmp, saddr, eaddr);
2557 /* And free them up */
2558 list_for_each_entry_safe(tmp, next, &removed, list) {
2559 amdgpu_vm_it_remove(tmp, &vm->va);
2560 list_del(&tmp->list);
2562 if (tmp->start < saddr)
2564 if (tmp->last > eaddr)
2568 list_add(&tmp->list, &vm->freed);
2569 trace_amdgpu_vm_bo_unmap(NULL, tmp);
2572 /* Insert partial mapping before the range */
2573 if (!list_empty(&before->list)) {
2574 amdgpu_vm_it_insert(before, &vm->va);
2575 if (before->flags & AMDGPU_PTE_PRT)
2576 amdgpu_vm_prt_get(adev);
2581 /* Insert partial mapping after the range */
2582 if (!list_empty(&after->list)) {
2583 amdgpu_vm_it_insert(after, &vm->va);
2584 if (after->flags & AMDGPU_PTE_PRT)
2585 amdgpu_vm_prt_get(adev);
2594 * amdgpu_vm_bo_lookup_mapping - find mapping by address
2596 * @vm: the requested VM
2597 * @addr: the address
2599 * Find a mapping by it's address.
2602 * The amdgpu_bo_va_mapping matching for addr or NULL
2605 struct amdgpu_bo_va_mapping *amdgpu_vm_bo_lookup_mapping(struct amdgpu_vm *vm,
2608 return amdgpu_vm_it_iter_first(&vm->va, addr, addr);
2612 * amdgpu_vm_bo_trace_cs - trace all reserved mappings
2614 * @vm: the requested vm
2615 * @ticket: CS ticket
2617 * Trace all mappings of BOs reserved during a command submission.
2619 void amdgpu_vm_bo_trace_cs(struct amdgpu_vm *vm, struct ww_acquire_ctx *ticket)
2621 struct amdgpu_bo_va_mapping *mapping;
2623 if (!trace_amdgpu_vm_bo_cs_enabled())
2626 for (mapping = amdgpu_vm_it_iter_first(&vm->va, 0, U64_MAX); mapping;
2627 mapping = amdgpu_vm_it_iter_next(mapping, 0, U64_MAX)) {
2628 if (mapping->bo_va && mapping->bo_va->base.bo) {
2629 struct amdgpu_bo *bo;
2631 bo = mapping->bo_va->base.bo;
2632 if (dma_resv_locking_ctx(bo->tbo.base.resv) !=
2637 trace_amdgpu_vm_bo_cs(mapping);
2642 * amdgpu_vm_bo_rmv - remove a bo to a specific vm
2644 * @adev: amdgpu_device pointer
2645 * @bo_va: requested bo_va
2647 * Remove @bo_va->bo from the requested vm.
2649 * Object have to be reserved!
2651 void amdgpu_vm_bo_rmv(struct amdgpu_device *adev,
2652 struct amdgpu_bo_va *bo_va)
2654 struct amdgpu_bo_va_mapping *mapping, *next;
2655 struct amdgpu_bo *bo = bo_va->base.bo;
2656 struct amdgpu_vm *vm = bo_va->base.vm;
2657 struct amdgpu_vm_bo_base **base;
2660 if (bo->tbo.base.resv == vm->root.bo->tbo.base.resv)
2661 vm->bulk_moveable = false;
2663 for (base = &bo_va->base.bo->vm_bo; *base;
2664 base = &(*base)->next) {
2665 if (*base != &bo_va->base)
2668 *base = bo_va->base.next;
2673 spin_lock(&vm->invalidated_lock);
2674 list_del(&bo_va->base.vm_status);
2675 spin_unlock(&vm->invalidated_lock);
2677 list_for_each_entry_safe(mapping, next, &bo_va->valids, list) {
2678 list_del(&mapping->list);
2679 amdgpu_vm_it_remove(mapping, &vm->va);
2680 mapping->bo_va = NULL;
2681 trace_amdgpu_vm_bo_unmap(bo_va, mapping);
2682 list_add(&mapping->list, &vm->freed);
2684 list_for_each_entry_safe(mapping, next, &bo_va->invalids, list) {
2685 list_del(&mapping->list);
2686 amdgpu_vm_it_remove(mapping, &vm->va);
2687 amdgpu_vm_free_mapping(adev, vm, mapping,
2688 bo_va->last_pt_update);
2691 dma_fence_put(bo_va->last_pt_update);
2693 if (bo && bo_va->is_xgmi)
2694 amdgpu_xgmi_set_pstate(adev, AMDGPU_XGMI_PSTATE_MIN);
2700 * amdgpu_vm_evictable - check if we can evict a VM
2702 * @bo: A page table of the VM.
2704 * Check if it is possible to evict a VM.
2706 bool amdgpu_vm_evictable(struct amdgpu_bo *bo)
2708 struct amdgpu_vm_bo_base *bo_base = bo->vm_bo;
2710 /* Page tables of a destroyed VM can go away immediately */
2711 if (!bo_base || !bo_base->vm)
2714 /* Don't evict VM page tables while they are busy */
2715 if (!dma_resv_test_signaled(bo->tbo.base.resv, true))
2718 /* Try to block ongoing updates */
2719 if (!amdgpu_vm_eviction_trylock(bo_base->vm))
2722 /* Don't evict VM page tables while they are updated */
2723 if (!dma_fence_is_signaled(bo_base->vm->last_unlocked)) {
2724 amdgpu_vm_eviction_unlock(bo_base->vm);
2728 bo_base->vm->evicting = true;
2729 amdgpu_vm_eviction_unlock(bo_base->vm);
2734 * amdgpu_vm_bo_invalidate - mark the bo as invalid
2736 * @adev: amdgpu_device pointer
2737 * @bo: amdgpu buffer object
2738 * @evicted: is the BO evicted
2740 * Mark @bo as invalid.
2742 void amdgpu_vm_bo_invalidate(struct amdgpu_device *adev,
2743 struct amdgpu_bo *bo, bool evicted)
2745 struct amdgpu_vm_bo_base *bo_base;
2747 /* shadow bo doesn't have bo base, its validation needs its parent */
2748 if (bo->parent && (amdgpu_bo_shadowed(bo->parent) == bo))
2751 for (bo_base = bo->vm_bo; bo_base; bo_base = bo_base->next) {
2752 struct amdgpu_vm *vm = bo_base->vm;
2754 if (evicted && bo->tbo.base.resv == vm->root.bo->tbo.base.resv) {
2755 amdgpu_vm_bo_evicted(bo_base);
2761 bo_base->moved = true;
2763 if (bo->tbo.type == ttm_bo_type_kernel)
2764 amdgpu_vm_bo_relocated(bo_base);
2765 else if (bo->tbo.base.resv == vm->root.bo->tbo.base.resv)
2766 amdgpu_vm_bo_moved(bo_base);
2768 amdgpu_vm_bo_invalidated(bo_base);
2773 * amdgpu_vm_get_block_size - calculate VM page table size as power of two
2778 * VM page table as power of two
2780 static uint32_t amdgpu_vm_get_block_size(uint64_t vm_size)
2782 /* Total bits covered by PD + PTs */
2783 unsigned bits = ilog2(vm_size) + 18;
2785 /* Make sure the PD is 4K in size up to 8GB address space.
2786 Above that split equal between PD and PTs */
2790 return ((bits + 3) / 2);
2794 * amdgpu_vm_adjust_size - adjust vm size, block size and fragment size
2796 * @adev: amdgpu_device pointer
2797 * @min_vm_size: the minimum vm size in GB if it's set auto
2798 * @fragment_size_default: Default PTE fragment size
2799 * @max_level: max VMPT level
2800 * @max_bits: max address space size in bits
2803 void amdgpu_vm_adjust_size(struct amdgpu_device *adev, uint32_t min_vm_size,
2804 uint32_t fragment_size_default, unsigned max_level,
2807 unsigned int max_size = 1 << (max_bits - 30);
2808 unsigned int vm_size;
2811 /* adjust vm size first */
2812 if (amdgpu_vm_size != -1) {
2813 vm_size = amdgpu_vm_size;
2814 if (vm_size > max_size) {
2815 dev_warn(adev->dev, "VM size (%d) too large, max is %u GB\n",
2816 amdgpu_vm_size, max_size);
2821 unsigned int phys_ram_gb;
2823 /* Optimal VM size depends on the amount of physical
2824 * RAM available. Underlying requirements and
2827 * - Need to map system memory and VRAM from all GPUs
2828 * - VRAM from other GPUs not known here
2829 * - Assume VRAM <= system memory
2830 * - On GFX8 and older, VM space can be segmented for
2832 * - Need to allow room for fragmentation, guard pages etc.
2834 * This adds up to a rough guess of system memory x3.
2835 * Round up to power of two to maximize the available
2836 * VM size with the given page table size.
2839 phys_ram_gb = ((uint64_t)si.totalram * si.mem_unit +
2840 (1 << 30) - 1) >> 30;
2841 vm_size = roundup_pow_of_two(
2842 min(max(phys_ram_gb * 3, min_vm_size), max_size));
2845 adev->vm_manager.max_pfn = (uint64_t)vm_size << 18;
2847 tmp = roundup_pow_of_two(adev->vm_manager.max_pfn);
2848 if (amdgpu_vm_block_size != -1)
2849 tmp >>= amdgpu_vm_block_size - 9;
2850 tmp = DIV_ROUND_UP(fls64(tmp) - 1, 9) - 1;
2851 adev->vm_manager.num_level = min(max_level, (unsigned)tmp);
2852 switch (adev->vm_manager.num_level) {
2854 adev->vm_manager.root_level = AMDGPU_VM_PDB2;
2857 adev->vm_manager.root_level = AMDGPU_VM_PDB1;
2860 adev->vm_manager.root_level = AMDGPU_VM_PDB0;
2863 dev_err(adev->dev, "VMPT only supports 2~4+1 levels\n");
2865 /* block size depends on vm size and hw setup*/
2866 if (amdgpu_vm_block_size != -1)
2867 adev->vm_manager.block_size =
2868 min((unsigned)amdgpu_vm_block_size, max_bits
2869 - AMDGPU_GPU_PAGE_SHIFT
2870 - 9 * adev->vm_manager.num_level);
2871 else if (adev->vm_manager.num_level > 1)
2872 adev->vm_manager.block_size = 9;
2874 adev->vm_manager.block_size = amdgpu_vm_get_block_size(tmp);
2876 if (amdgpu_vm_fragment_size == -1)
2877 adev->vm_manager.fragment_size = fragment_size_default;
2879 adev->vm_manager.fragment_size = amdgpu_vm_fragment_size;
2881 DRM_INFO("vm size is %u GB, %u levels, block size is %u-bit, fragment size is %u-bit\n",
2882 vm_size, adev->vm_manager.num_level + 1,
2883 adev->vm_manager.block_size,
2884 adev->vm_manager.fragment_size);
2888 * amdgpu_vm_wait_idle - wait for the VM to become idle
2890 * @vm: VM object to wait for
2891 * @timeout: timeout to wait for VM to become idle
2893 long amdgpu_vm_wait_idle(struct amdgpu_vm *vm, long timeout)
2895 timeout = dma_resv_wait_timeout(vm->root.bo->tbo.base.resv, true,
2900 return dma_fence_wait_timeout(vm->last_unlocked, true, timeout);
2904 * amdgpu_vm_init - initialize a vm instance
2906 * @adev: amdgpu_device pointer
2912 * 0 for success, error for failure.
2914 int amdgpu_vm_init(struct amdgpu_device *adev, struct amdgpu_vm *vm)
2916 struct amdgpu_bo *root_bo;
2917 struct amdgpu_bo_vm *root;
2920 vm->va = RB_ROOT_CACHED;
2921 for (i = 0; i < AMDGPU_MAX_VMHUBS; i++)
2922 vm->reserved_vmid[i] = NULL;
2923 INIT_LIST_HEAD(&vm->evicted);
2924 INIT_LIST_HEAD(&vm->relocated);
2925 INIT_LIST_HEAD(&vm->moved);
2926 INIT_LIST_HEAD(&vm->idle);
2927 INIT_LIST_HEAD(&vm->invalidated);
2928 spin_lock_init(&vm->invalidated_lock);
2929 INIT_LIST_HEAD(&vm->freed);
2930 INIT_LIST_HEAD(&vm->done);
2932 /* create scheduler entities for page table updates */
2933 r = drm_sched_entity_init(&vm->immediate, DRM_SCHED_PRIORITY_NORMAL,
2934 adev->vm_manager.vm_pte_scheds,
2935 adev->vm_manager.vm_pte_num_scheds, NULL);
2939 r = drm_sched_entity_init(&vm->delayed, DRM_SCHED_PRIORITY_NORMAL,
2940 adev->vm_manager.vm_pte_scheds,
2941 adev->vm_manager.vm_pte_num_scheds, NULL);
2943 goto error_free_immediate;
2945 vm->pte_support_ats = false;
2946 vm->is_compute_context = false;
2948 vm->use_cpu_for_update = !!(adev->vm_manager.vm_update_mode &
2949 AMDGPU_VM_USE_CPU_FOR_GFX);
2951 DRM_DEBUG_DRIVER("VM update mode is %s\n",
2952 vm->use_cpu_for_update ? "CPU" : "SDMA");
2953 WARN_ONCE((vm->use_cpu_for_update &&
2954 !amdgpu_gmc_vram_full_visible(&adev->gmc)),
2955 "CPU update of VM recommended only for large BAR system\n");
2957 if (vm->use_cpu_for_update)
2958 vm->update_funcs = &amdgpu_vm_cpu_funcs;
2960 vm->update_funcs = &amdgpu_vm_sdma_funcs;
2961 vm->last_update = NULL;
2962 vm->last_unlocked = dma_fence_get_stub();
2964 mutex_init(&vm->eviction_lock);
2965 vm->evicting = false;
2967 r = amdgpu_vm_pt_create(adev, vm, adev->vm_manager.root_level,
2970 goto error_free_delayed;
2971 root_bo = &root->bo;
2972 r = amdgpu_bo_reserve(root_bo, true);
2974 goto error_free_root;
2976 r = dma_resv_reserve_shared(root_bo->tbo.base.resv, 1);
2978 goto error_unreserve;
2980 amdgpu_vm_bo_base_init(&vm->root, vm, root_bo);
2982 r = amdgpu_vm_clear_bo(adev, vm, root, false);
2984 goto error_unreserve;
2986 amdgpu_bo_unreserve(vm->root.bo);
2988 INIT_KFIFO(vm->faults);
2993 amdgpu_bo_unreserve(vm->root.bo);
2996 amdgpu_bo_unref(&root->shadow);
2997 amdgpu_bo_unref(&root_bo);
3001 dma_fence_put(vm->last_unlocked);
3002 drm_sched_entity_destroy(&vm->delayed);
3004 error_free_immediate:
3005 drm_sched_entity_destroy(&vm->immediate);
3011 * amdgpu_vm_check_clean_reserved - check if a VM is clean
3013 * @adev: amdgpu_device pointer
3014 * @vm: the VM to check
3016 * check all entries of the root PD, if any subsequent PDs are allocated,
3017 * it means there are page table creating and filling, and is no a clean
3021 * 0 if this VM is clean
3023 static int amdgpu_vm_check_clean_reserved(struct amdgpu_device *adev,
3024 struct amdgpu_vm *vm)
3026 enum amdgpu_vm_level root = adev->vm_manager.root_level;
3027 unsigned int entries = amdgpu_vm_num_entries(adev, root);
3030 for (i = 0; i < entries; i++) {
3031 if (to_amdgpu_bo_vm(vm->root.bo)->entries[i].bo)
3039 * amdgpu_vm_make_compute - Turn a GFX VM into a compute VM
3041 * @adev: amdgpu_device pointer
3044 * This only works on GFX VMs that don't have any BOs added and no
3045 * page tables allocated yet.
3047 * Changes the following VM parameters:
3048 * - use_cpu_for_update
3049 * - pte_supports_ats
3051 * Reinitializes the page directory to reflect the changed ATS
3055 * 0 for success, -errno for errors.
3057 int amdgpu_vm_make_compute(struct amdgpu_device *adev, struct amdgpu_vm *vm)
3059 bool pte_support_ats = (adev->asic_type == CHIP_RAVEN);
3062 r = amdgpu_bo_reserve(vm->root.bo, true);
3067 r = amdgpu_vm_check_clean_reserved(adev, vm);
3071 /* Check if PD needs to be reinitialized and do it before
3072 * changing any other state, in case it fails.
3074 if (pte_support_ats != vm->pte_support_ats) {
3075 vm->pte_support_ats = pte_support_ats;
3076 r = amdgpu_vm_clear_bo(adev, vm,
3077 to_amdgpu_bo_vm(vm->root.bo),
3083 /* Update VM state */
3084 vm->use_cpu_for_update = !!(adev->vm_manager.vm_update_mode &
3085 AMDGPU_VM_USE_CPU_FOR_COMPUTE);
3086 DRM_DEBUG_DRIVER("VM update mode is %s\n",
3087 vm->use_cpu_for_update ? "CPU" : "SDMA");
3088 WARN_ONCE((vm->use_cpu_for_update &&
3089 !amdgpu_gmc_vram_full_visible(&adev->gmc)),
3090 "CPU update of VM recommended only for large BAR system\n");
3092 if (vm->use_cpu_for_update) {
3093 /* Sync with last SDMA update/clear before switching to CPU */
3094 r = amdgpu_bo_sync_wait(vm->root.bo,
3095 AMDGPU_FENCE_OWNER_UNDEFINED, true);
3099 vm->update_funcs = &amdgpu_vm_cpu_funcs;
3101 vm->update_funcs = &amdgpu_vm_sdma_funcs;
3103 dma_fence_put(vm->last_update);
3104 vm->last_update = NULL;
3105 vm->is_compute_context = true;
3107 /* Free the shadow bo for compute VM */
3108 amdgpu_bo_unref(&to_amdgpu_bo_vm(vm->root.bo)->shadow);
3113 amdgpu_bo_unreserve(vm->root.bo);
3118 * amdgpu_vm_release_compute - release a compute vm
3119 * @adev: amdgpu_device pointer
3120 * @vm: a vm turned into compute vm by calling amdgpu_vm_make_compute
3122 * This is a correspondant of amdgpu_vm_make_compute. It decouples compute
3123 * pasid from vm. Compute should stop use of vm after this call.
3125 void amdgpu_vm_release_compute(struct amdgpu_device *adev, struct amdgpu_vm *vm)
3127 amdgpu_vm_set_pasid(adev, vm, 0);
3128 vm->is_compute_context = false;
3132 * amdgpu_vm_fini - tear down a vm instance
3134 * @adev: amdgpu_device pointer
3138 * Unbind the VM and remove all bos from the vm bo list
3140 void amdgpu_vm_fini(struct amdgpu_device *adev, struct amdgpu_vm *vm)
3142 struct amdgpu_bo_va_mapping *mapping, *tmp;
3143 bool prt_fini_needed = !!adev->gmc.gmc_funcs->set_prt;
3144 struct amdgpu_bo *root;
3147 amdgpu_amdkfd_gpuvm_destroy_cb(adev, vm);
3149 root = amdgpu_bo_ref(vm->root.bo);
3150 amdgpu_bo_reserve(root, true);
3151 amdgpu_vm_set_pasid(adev, vm, 0);
3152 dma_fence_wait(vm->last_unlocked, false);
3153 dma_fence_put(vm->last_unlocked);
3155 list_for_each_entry_safe(mapping, tmp, &vm->freed, list) {
3156 if (mapping->flags & AMDGPU_PTE_PRT && prt_fini_needed) {
3157 amdgpu_vm_prt_fini(adev, vm);
3158 prt_fini_needed = false;
3161 list_del(&mapping->list);
3162 amdgpu_vm_free_mapping(adev, vm, mapping, NULL);
3165 amdgpu_vm_free_pts(adev, vm, NULL);
3166 amdgpu_bo_unreserve(root);
3167 amdgpu_bo_unref(&root);
3168 WARN_ON(vm->root.bo);
3170 drm_sched_entity_destroy(&vm->immediate);
3171 drm_sched_entity_destroy(&vm->delayed);
3173 if (!RB_EMPTY_ROOT(&vm->va.rb_root)) {
3174 dev_err(adev->dev, "still active bo inside vm\n");
3176 rbtree_postorder_for_each_entry_safe(mapping, tmp,
3177 &vm->va.rb_root, rb) {
3178 /* Don't remove the mapping here, we don't want to trigger a
3179 * rebalance and the tree is about to be destroyed anyway.
3181 list_del(&mapping->list);
3185 dma_fence_put(vm->last_update);
3186 for (i = 0; i < AMDGPU_MAX_VMHUBS; i++)
3187 amdgpu_vmid_free_reserved(adev, vm, i);
3191 * amdgpu_vm_manager_init - init the VM manager
3193 * @adev: amdgpu_device pointer
3195 * Initialize the VM manager structures
3197 void amdgpu_vm_manager_init(struct amdgpu_device *adev)
3201 /* Concurrent flushes are only possible starting with Vega10 and
3202 * are broken on Navi10 and Navi14.
3204 adev->vm_manager.concurrent_flush = !(adev->asic_type < CHIP_VEGA10 ||
3205 adev->asic_type == CHIP_NAVI10 ||
3206 adev->asic_type == CHIP_NAVI14);
3207 amdgpu_vmid_mgr_init(adev);
3209 adev->vm_manager.fence_context =
3210 dma_fence_context_alloc(AMDGPU_MAX_RINGS);
3211 for (i = 0; i < AMDGPU_MAX_RINGS; ++i)
3212 adev->vm_manager.seqno[i] = 0;
3214 spin_lock_init(&adev->vm_manager.prt_lock);
3215 atomic_set(&adev->vm_manager.num_prt_users, 0);
3217 /* If not overridden by the user, by default, only in large BAR systems
3218 * Compute VM tables will be updated by CPU
3220 #ifdef CONFIG_X86_64
3221 if (amdgpu_vm_update_mode == -1) {
3222 if (amdgpu_gmc_vram_full_visible(&adev->gmc))
3223 adev->vm_manager.vm_update_mode =
3224 AMDGPU_VM_USE_CPU_FOR_COMPUTE;
3226 adev->vm_manager.vm_update_mode = 0;
3228 adev->vm_manager.vm_update_mode = amdgpu_vm_update_mode;
3230 adev->vm_manager.vm_update_mode = 0;
3233 xa_init_flags(&adev->vm_manager.pasids, XA_FLAGS_LOCK_IRQ);
3237 * amdgpu_vm_manager_fini - cleanup VM manager
3239 * @adev: amdgpu_device pointer
3241 * Cleanup the VM manager and free resources.
3243 void amdgpu_vm_manager_fini(struct amdgpu_device *adev)
3245 WARN_ON(!xa_empty(&adev->vm_manager.pasids));
3246 xa_destroy(&adev->vm_manager.pasids);
3248 amdgpu_vmid_mgr_fini(adev);
3252 * amdgpu_vm_ioctl - Manages VMID reservation for vm hubs.
3254 * @dev: drm device pointer
3255 * @data: drm_amdgpu_vm
3256 * @filp: drm file pointer
3259 * 0 for success, -errno for errors.
3261 int amdgpu_vm_ioctl(struct drm_device *dev, void *data, struct drm_file *filp)
3263 union drm_amdgpu_vm *args = data;
3264 struct amdgpu_device *adev = drm_to_adev(dev);
3265 struct amdgpu_fpriv *fpriv = filp->driver_priv;
3266 long timeout = msecs_to_jiffies(2000);
3269 switch (args->in.op) {
3270 case AMDGPU_VM_OP_RESERVE_VMID:
3271 /* We only have requirement to reserve vmid from gfxhub */
3272 r = amdgpu_vmid_alloc_reserved(adev, &fpriv->vm,
3277 case AMDGPU_VM_OP_UNRESERVE_VMID:
3278 if (amdgpu_sriov_runtime(adev))
3279 timeout = 8 * timeout;
3281 /* Wait vm idle to make sure the vmid set in SPM_VMID is
3282 * not referenced anymore.
3284 r = amdgpu_bo_reserve(fpriv->vm.root.bo, true);
3288 r = amdgpu_vm_wait_idle(&fpriv->vm, timeout);
3292 amdgpu_bo_unreserve(fpriv->vm.root.bo);
3293 amdgpu_vmid_free_reserved(adev, &fpriv->vm, AMDGPU_GFXHUB_0);
3303 * amdgpu_vm_get_task_info - Extracts task info for a PASID.
3305 * @adev: drm device pointer
3306 * @pasid: PASID identifier for VM
3307 * @task_info: task_info to fill.
3309 void amdgpu_vm_get_task_info(struct amdgpu_device *adev, u32 pasid,
3310 struct amdgpu_task_info *task_info)
3312 struct amdgpu_vm *vm;
3313 unsigned long flags;
3315 xa_lock_irqsave(&adev->vm_manager.pasids, flags);
3317 vm = xa_load(&adev->vm_manager.pasids, pasid);
3319 *task_info = vm->task_info;
3321 xa_unlock_irqrestore(&adev->vm_manager.pasids, flags);
3325 * amdgpu_vm_set_task_info - Sets VMs task info.
3327 * @vm: vm for which to set the info
3329 void amdgpu_vm_set_task_info(struct amdgpu_vm *vm)
3331 if (vm->task_info.pid)
3334 vm->task_info.pid = current->pid;
3335 get_task_comm(vm->task_info.task_name, current);
3337 if (current->group_leader->mm != current->mm)
3340 vm->task_info.tgid = current->group_leader->pid;
3341 get_task_comm(vm->task_info.process_name, current->group_leader);
3345 * amdgpu_vm_handle_fault - graceful handling of VM faults.
3346 * @adev: amdgpu device pointer
3347 * @pasid: PASID of the VM
3348 * @addr: Address of the fault
3349 * @write_fault: true is write fault, false is read fault
3351 * Try to gracefully handle a VM fault. Return true if the fault was handled and
3352 * shouldn't be reported any more.
3354 bool amdgpu_vm_handle_fault(struct amdgpu_device *adev, u32 pasid,
3355 uint64_t addr, bool write_fault)
3357 bool is_compute_context = false;
3358 struct amdgpu_bo *root;
3359 unsigned long irqflags;
3360 uint64_t value, flags;
3361 struct amdgpu_vm *vm;
3364 xa_lock_irqsave(&adev->vm_manager.pasids, irqflags);
3365 vm = xa_load(&adev->vm_manager.pasids, pasid);
3367 root = amdgpu_bo_ref(vm->root.bo);
3368 is_compute_context = vm->is_compute_context;
3372 xa_unlock_irqrestore(&adev->vm_manager.pasids, irqflags);
3377 addr /= AMDGPU_GPU_PAGE_SIZE;
3379 if (is_compute_context &&
3380 !svm_range_restore_pages(adev, pasid, addr, write_fault)) {
3381 amdgpu_bo_unref(&root);
3385 r = amdgpu_bo_reserve(root, true);
3389 /* Double check that the VM still exists */
3390 xa_lock_irqsave(&adev->vm_manager.pasids, irqflags);
3391 vm = xa_load(&adev->vm_manager.pasids, pasid);
3392 if (vm && vm->root.bo != root)
3394 xa_unlock_irqrestore(&adev->vm_manager.pasids, irqflags);
3398 flags = AMDGPU_PTE_VALID | AMDGPU_PTE_SNOOPED |
3401 if (is_compute_context) {
3402 /* Intentionally setting invalid PTE flag
3403 * combination to force a no-retry-fault
3405 flags = AMDGPU_PTE_EXECUTABLE | AMDGPU_PDE_PTE |
3408 } else if (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_NEVER) {
3409 /* Redirect the access to the dummy page */
3410 value = adev->dummy_page_addr;
3411 flags |= AMDGPU_PTE_EXECUTABLE | AMDGPU_PTE_READABLE |
3412 AMDGPU_PTE_WRITEABLE;
3415 /* Let the hw retry silently on the PTE */
3419 r = dma_resv_reserve_shared(root->tbo.base.resv, 1);
3421 pr_debug("failed %d to reserve fence slot\n", r);
3425 r = amdgpu_vm_bo_update_mapping(adev, adev, vm, true, false, NULL, addr,
3426 addr, flags, value, NULL, NULL, NULL,
3431 r = amdgpu_vm_update_pdes(adev, vm, true);
3434 amdgpu_bo_unreserve(root);
3436 DRM_ERROR("Can't handle page fault (%d)\n", r);
3439 amdgpu_bo_unref(&root);
3444 #if defined(CONFIG_DEBUG_FS)
3446 * amdgpu_debugfs_vm_bo_info - print BO info for the VM
3448 * @vm: Requested VM for printing BO info
3451 * Print BO information in debugfs file for the VM
3453 void amdgpu_debugfs_vm_bo_info(struct amdgpu_vm *vm, struct seq_file *m)
3455 struct amdgpu_bo_va *bo_va, *tmp;
3457 u64 total_evicted = 0;
3458 u64 total_relocated = 0;
3459 u64 total_moved = 0;
3460 u64 total_invalidated = 0;
3462 unsigned int total_idle_objs = 0;
3463 unsigned int total_evicted_objs = 0;
3464 unsigned int total_relocated_objs = 0;
3465 unsigned int total_moved_objs = 0;
3466 unsigned int total_invalidated_objs = 0;
3467 unsigned int total_done_objs = 0;
3468 unsigned int id = 0;
3470 seq_puts(m, "\tIdle BOs:\n");
3471 list_for_each_entry_safe(bo_va, tmp, &vm->idle, base.vm_status) {
3472 if (!bo_va->base.bo)
3474 total_idle += amdgpu_bo_print_info(id++, bo_va->base.bo, m);
3476 total_idle_objs = id;
3479 seq_puts(m, "\tEvicted BOs:\n");
3480 list_for_each_entry_safe(bo_va, tmp, &vm->evicted, base.vm_status) {
3481 if (!bo_va->base.bo)
3483 total_evicted += amdgpu_bo_print_info(id++, bo_va->base.bo, m);
3485 total_evicted_objs = id;
3488 seq_puts(m, "\tRelocated BOs:\n");
3489 list_for_each_entry_safe(bo_va, tmp, &vm->relocated, base.vm_status) {
3490 if (!bo_va->base.bo)
3492 total_relocated += amdgpu_bo_print_info(id++, bo_va->base.bo, m);
3494 total_relocated_objs = id;
3497 seq_puts(m, "\tMoved BOs:\n");
3498 list_for_each_entry_safe(bo_va, tmp, &vm->moved, base.vm_status) {
3499 if (!bo_va->base.bo)
3501 total_moved += amdgpu_bo_print_info(id++, bo_va->base.bo, m);
3503 total_moved_objs = id;
3506 seq_puts(m, "\tInvalidated BOs:\n");
3507 spin_lock(&vm->invalidated_lock);
3508 list_for_each_entry_safe(bo_va, tmp, &vm->invalidated, base.vm_status) {
3509 if (!bo_va->base.bo)
3511 total_invalidated += amdgpu_bo_print_info(id++, bo_va->base.bo, m);
3513 total_invalidated_objs = id;
3516 seq_puts(m, "\tDone BOs:\n");
3517 list_for_each_entry_safe(bo_va, tmp, &vm->done, base.vm_status) {
3518 if (!bo_va->base.bo)
3520 total_done += amdgpu_bo_print_info(id++, bo_va->base.bo, m);
3522 spin_unlock(&vm->invalidated_lock);
3523 total_done_objs = id;
3525 seq_printf(m, "\tTotal idle size: %12lld\tobjs:\t%d\n", total_idle,
3527 seq_printf(m, "\tTotal evicted size: %12lld\tobjs:\t%d\n", total_evicted,
3528 total_evicted_objs);
3529 seq_printf(m, "\tTotal relocated size: %12lld\tobjs:\t%d\n", total_relocated,
3530 total_relocated_objs);
3531 seq_printf(m, "\tTotal moved size: %12lld\tobjs:\t%d\n", total_moved,
3533 seq_printf(m, "\tTotal invalidated size: %12lld\tobjs:\t%d\n", total_invalidated,
3534 total_invalidated_objs);
3535 seq_printf(m, "\tTotal done size: %12lld\tobjs:\t%d\n", total_done,