drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c

   1 /*
   2  * Copyright 2016 Advanced Micro Devices, Inc.
   3  * All Rights Reserved.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the
   7  * "Software"), to deal in the Software without restriction, including
   8  * without limitation the rights to use, copy, modify, merge, publish,
   9  * distribute, sub license, and/or sell copies of the Software, and to
  10  * permit persons to whom the Software is furnished to do so, subject to
  11  * the following conditions:
  12  *
  13  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  14  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  15  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  16  * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
  17  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  18  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  19  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  20  *
  21  * The above copyright notice and this permission notice (including the
  22  * next paragraph) shall be included in all copies or substantial portions
  23  * of the Software.
  24  *
  25  */
  26
  27 #include <linux/firmware.h>
  28 #include <linux/module.h>
  29 #include <drm/drmP.h>
  30 #include <drm/drm.h>
  31
  32 #include "amdgpu.h"
  33 #include "amdgpu_pm.h"
  34 #include "amdgpu_vcn.h"
  35 #include "soc15d.h"
  36 #include "soc15_common.h"
  37
  38 #include "vcn/vcn_1_0_offset.h"
  39 #include "vcn/vcn_1_0_sh_mask.h"
  40
  41 /* 1 second timeout */
  42 #define VCN_IDLE_TIMEOUT        msecs_to_jiffies(1000)
  43
  44 /* Firmware Names */
  45 #define FIRMWARE_RAVEN          "amdgpu/raven_vcn.bin"
  46 #define FIRMWARE_PICASSO        "amdgpu/picasso_vcn.bin"
  47 #define FIRMWARE_RAVEN2         "amdgpu/raven2_vcn.bin"
  48 #define FIRMWARE_NAVI10         "amdgpu/navi10_vcn.bin"
  49
  50 MODULE_FIRMWARE(FIRMWARE_RAVEN);
  51 MODULE_FIRMWARE(FIRMWARE_PICASSO);
  52 MODULE_FIRMWARE(FIRMWARE_RAVEN2);
  53 MODULE_FIRMWARE(FIRMWARE_NAVI10);
  54
  55 static void amdgpu_vcn_idle_work_handler(struct work_struct *work);
  56
  57 int amdgpu_vcn_sw_init(struct amdgpu_device *adev)
  58 {
  59         unsigned long bo_size;
  60         const char *fw_name;
  61         const struct common_firmware_header *hdr;
  62         unsigned char fw_check;
  63         int r;
  64
  65         INIT_DELAYED_WORK(&adev->vcn.idle_work, amdgpu_vcn_idle_work_handler);
  66
  67         switch (adev->asic_type) {
  68         case CHIP_RAVEN:
  69                 if (adev->rev_id >= 8)
  70                         fw_name = FIRMWARE_RAVEN2;
  71                 else if (adev->pdev->device == 0x15d8)
  72                         fw_name = FIRMWARE_PICASSO;
  73                 else
  74                         fw_name = FIRMWARE_RAVEN;
  75                 break;
  76         case CHIP_NAVI10:
  77                 fw_name = FIRMWARE_NAVI10;
  78                 break;
  79         default:
  80                 return -EINVAL;
  81         }
  82
  83         r = request_firmware(&adev->vcn.fw, fw_name, adev->dev);
  84         if (r) {
  85                 dev_err(adev->dev, "amdgpu_vcn: Can't load firmware \"%s\"\n",
  86                         fw_name);
  87                 return r;
  88         }
  89
  90         r = amdgpu_ucode_validate(adev->vcn.fw);
  91         if (r) {
  92                 dev_err(adev->dev, "amdgpu_vcn: Can't validate firmware \"%s\"\n",
  93                         fw_name);
  94                 release_firmware(adev->vcn.fw);
  95                 adev->vcn.fw = NULL;
  96                 return r;
  97         }
  98
  99         hdr = (const struct common_firmware_header *)adev->vcn.fw->data;
 100         adev->vcn.fw_version = le32_to_cpu(hdr->ucode_version);
 101
 102         /* Bit 20-23, it is encode major and non-zero for new naming convention.
 103          * This field is part of version minor and DRM_DISABLED_FLAG in old naming
 104          * convention. Since the l:wq!atest version minor is 0x5B and DRM_DISABLED_FLAG
 105          * is zero in old naming convention, this field is always zero so far.
 106          * These four bits are used to tell which naming convention is present.
 107          */
 108         fw_check = (le32_to_cpu(hdr->ucode_version) >> 20) & 0xf;
 109         if (fw_check) {
 110                 unsigned int dec_ver, enc_major, enc_minor, vep, fw_rev;
 111
 112                 fw_rev = le32_to_cpu(hdr->ucode_version) & 0xfff;
 113                 enc_minor = (le32_to_cpu(hdr->ucode_version) >> 12) & 0xff;
 114                 enc_major = fw_check;
 115                 dec_ver = (le32_to_cpu(hdr->ucode_version) >> 24) & 0xf;
 116                 vep = (le32_to_cpu(hdr->ucode_version) >> 28) & 0xf;
 117                 DRM_INFO("Found VCN firmware Version ENC: %hu.%hu DEC: %hu VEP: %hu Revision: %hu\n",
 118                         enc_major, enc_minor, dec_ver, vep, fw_rev);
 119         } else {
 120                 unsigned int version_major, version_minor, family_id;
 121
 122                 family_id = le32_to_cpu(hdr->ucode_version) & 0xff;
 123                 version_major = (le32_to_cpu(hdr->ucode_version) >> 24) & 0xff;
 124                 version_minor = (le32_to_cpu(hdr->ucode_version) >> 8) & 0xff;
 125                 DRM_INFO("Found VCN firmware Version: %hu.%hu Family ID: %hu\n",
 126                         version_major, version_minor, family_id);
 127         }
 128
 129         bo_size = AMDGPU_VCN_STACK_SIZE + AMDGPU_VCN_CONTEXT_SIZE;
 130         if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP)
 131                 bo_size += AMDGPU_GPU_PAGE_ALIGN(le32_to_cpu(hdr->ucode_size_bytes) + 8);
 132         r = amdgpu_bo_create_kernel(adev, bo_size, PAGE_SIZE,
 133                                     AMDGPU_GEM_DOMAIN_VRAM, &adev->vcn.vcpu_bo,
 134                                     &adev->vcn.gpu_addr, &adev->vcn.cpu_addr);
 135         if (r) {
 136                 dev_err(adev->dev, "(%d) failed to allocate vcn bo\n", r);
 137                 return r;
 138         }
 139
 140         if (adev->vcn.indirect_sram) {
 141                 r = amdgpu_bo_create_kernel(adev, 64 * 2 * 4, PAGE_SIZE,
 142                             AMDGPU_GEM_DOMAIN_VRAM, &adev->vcn.dpg_sram_bo,
 143                             &adev->vcn.dpg_sram_gpu_addr, &adev->vcn.dpg_sram_cpu_addr);
 144                 if (r) {
 145                         dev_err(adev->dev, "(%d) failed to allocate DPG bo\n", r);
 146                         return r;
 147                 }
 148         }
 149
 150         return 0;
 151 }
 152
 153 int amdgpu_vcn_sw_fini(struct amdgpu_device *adev)
 154 {
 155         int i;
 156
 157         kvfree(adev->vcn.saved_bo);
 158
 159         if (adev->vcn.indirect_sram) {
 160                 amdgpu_bo_free_kernel(&adev->vcn.dpg_sram_bo,
 161                               &adev->vcn.dpg_sram_gpu_addr,
 162                               (void **)&adev->vcn.dpg_sram_cpu_addr);
 163         }
 164
 165         amdgpu_bo_free_kernel(&adev->vcn.vcpu_bo,
 166                               &adev->vcn.gpu_addr,
 167                               (void **)&adev->vcn.cpu_addr);
 168
 169         amdgpu_ring_fini(&adev->vcn.ring_dec);
 170
 171         for (i = 0; i < adev->vcn.num_enc_rings; ++i)
 172                 amdgpu_ring_fini(&adev->vcn.ring_enc[i]);
 173
 174         amdgpu_ring_fini(&adev->vcn.ring_jpeg);
 175
 176         release_firmware(adev->vcn.fw);
 177
 178         return 0;
 179 }
 180
 181 int amdgpu_vcn_suspend(struct amdgpu_device *adev)
 182 {
 183         unsigned size;
 184         void *ptr;
 185
 186         cancel_delayed_work_sync(&adev->vcn.idle_work);
 187
 188         if (adev->vcn.vcpu_bo == NULL)
 189                 return 0;
 190
 191         size = amdgpu_bo_size(adev->vcn.vcpu_bo);
 192         ptr = adev->vcn.cpu_addr;
 193
 194         adev->vcn.saved_bo = kvmalloc(size, GFP_KERNEL);
 195         if (!adev->vcn.saved_bo)
 196                 return -ENOMEM;
 197
 198         memcpy_fromio(adev->vcn.saved_bo, ptr, size);
 199
 200         return 0;
 201 }
 202
 203 int amdgpu_vcn_resume(struct amdgpu_device *adev)
 204 {
 205         unsigned size;
 206         void *ptr;
 207
 208         if (adev->vcn.vcpu_bo == NULL)
 209                 return -EINVAL;
 210
 211         size = amdgpu_bo_size(adev->vcn.vcpu_bo);
 212         ptr = adev->vcn.cpu_addr;
 213
 214         if (adev->vcn.saved_bo != NULL) {
 215                 memcpy_toio(ptr, adev->vcn.saved_bo, size);
 216                 kvfree(adev->vcn.saved_bo);
 217                 adev->vcn.saved_bo = NULL;
 218         } else {
 219                 const struct common_firmware_header *hdr;
 220                 unsigned offset;
 221
 222                 hdr = (const struct common_firmware_header *)adev->vcn.fw->data;
 223                 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) {
 224                         offset = le32_to_cpu(hdr->ucode_array_offset_bytes);
 225                         memcpy_toio(adev->vcn.cpu_addr, adev->vcn.fw->data + offset,
 226                                     le32_to_cpu(hdr->ucode_size_bytes));
 227                         size -= le32_to_cpu(hdr->ucode_size_bytes);
 228                         ptr += le32_to_cpu(hdr->ucode_size_bytes);
 229                 }
 230                 memset_io(ptr, 0, size);
 231         }
 232
 233         return 0;
 234 }
 235
 236 static void amdgpu_vcn_idle_work_handler(struct work_struct *work)
 237 {
 238         struct amdgpu_device *adev =
 239                 container_of(work, struct amdgpu_device, vcn.idle_work.work);
 240         unsigned int fences = 0;
 241         unsigned int i;
 242
 243         for (i = 0; i < adev->vcn.num_enc_rings; ++i) {
 244                 fences += amdgpu_fence_count_emitted(&adev->vcn.ring_enc[i]);
 245         }
 246
 247         if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG)    {
 248                 struct dpg_pause_state new_state;
 249
 250                 if (fences)
 251                         new_state.fw_based = VCN_DPG_STATE__PAUSE;
 252                 else
 253                         new_state.fw_based = VCN_DPG_STATE__UNPAUSE;
 254
 255                 if (amdgpu_fence_count_emitted(&adev->vcn.ring_jpeg))
 256                         new_state.jpeg = VCN_DPG_STATE__PAUSE;
 257                 else
 258                         new_state.jpeg = VCN_DPG_STATE__UNPAUSE;
 259
 260                 adev->vcn.pause_dpg_mode(adev, &new_state);
 261         }
 262
 263         fences += amdgpu_fence_count_emitted(&adev->vcn.ring_jpeg);
 264         fences += amdgpu_fence_count_emitted(&adev->vcn.ring_dec);
 265
 266         if (fences == 0) {
 267                 amdgpu_gfx_off_ctrl(adev, true);
 268                 if (adev->asic_type < CHIP_NAVI10 && adev->pm.dpm_enabled)
 269                         amdgpu_dpm_enable_uvd(adev, false);
 270                 else
 271                         amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_VCN,
 272                                                                AMD_PG_STATE_GATE);
 273         } else {
 274                 schedule_delayed_work(&adev->vcn.idle_work, VCN_IDLE_TIMEOUT);
 275         }
 276 }
 277
 278 void amdgpu_vcn_ring_begin_use(struct amdgpu_ring *ring)
 279 {
 280         struct amdgpu_device *adev = ring->adev;
 281         bool set_clocks = !cancel_delayed_work_sync(&adev->vcn.idle_work);
 282
 283         if (set_clocks) {
 284                 amdgpu_gfx_off_ctrl(adev, false);
 285                 if (adev->asic_type < CHIP_NAVI10 && adev->pm.dpm_enabled)
 286                         amdgpu_dpm_enable_uvd(adev, true);
 287                 else
 288                         amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_VCN,
 289                                                                AMD_PG_STATE_UNGATE);
 290         }
 291
 292         if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG)    {
 293                 struct dpg_pause_state new_state;
 294                 unsigned int fences = 0;
 295                 unsigned int i;
 296
 297                 for (i = 0; i < adev->vcn.num_enc_rings; ++i) {
 298                         fences += amdgpu_fence_count_emitted(&adev->vcn.ring_enc[i]);
 299                 }
 300                 if (fences)
 301                         new_state.fw_based = VCN_DPG_STATE__PAUSE;
 302                 else
 303                         new_state.fw_based = VCN_DPG_STATE__UNPAUSE;
 304
 305                 if (amdgpu_fence_count_emitted(&adev->vcn.ring_jpeg))
 306                         new_state.jpeg = VCN_DPG_STATE__PAUSE;
 307                 else
 308                         new_state.jpeg = VCN_DPG_STATE__UNPAUSE;
 309
 310                 if (ring->funcs->type == AMDGPU_RING_TYPE_VCN_ENC)
 311                         new_state.fw_based = VCN_DPG_STATE__PAUSE;
 312                 else if (ring->funcs->type == AMDGPU_RING_TYPE_VCN_JPEG)
 313                         new_state.jpeg = VCN_DPG_STATE__PAUSE;
 314
 315                 adev->vcn.pause_dpg_mode(adev, &new_state);
 316         }
 317 }
 318
 319 void amdgpu_vcn_ring_end_use(struct amdgpu_ring *ring)
 320 {
 321         schedule_delayed_work(&ring->adev->vcn.idle_work, VCN_IDLE_TIMEOUT);
 322 }
 323
 324 int amdgpu_vcn_dec_ring_test_ring(struct amdgpu_ring *ring)
 325 {
 326         struct amdgpu_device *adev = ring->adev;
 327         uint32_t tmp = 0;
 328         unsigned i;
 329         int r;
 330
 331         WREG32(adev->vcn.external.scratch9, 0xCAFEDEAD);
 332         r = amdgpu_ring_alloc(ring, 3);
 333         if (r)
 334                 return r;
 335         amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.scratch9, 0));
 336         amdgpu_ring_write(ring, 0xDEADBEEF);
 337         amdgpu_ring_commit(ring);
 338         for (i = 0; i < adev->usec_timeout; i++) {
 339                 tmp = RREG32(adev->vcn.external.scratch9);
 340                 if (tmp == 0xDEADBEEF)
 341                         break;
 342                 DRM_UDELAY(1);
 343         }
 344
 345         if (i >= adev->usec_timeout)
 346                 r = -ETIMEDOUT;
 347
 348         return r;
 349 }
 350
 351 static int amdgpu_vcn_dec_send_msg(struct amdgpu_ring *ring,
 352                                    struct amdgpu_bo *bo,
 353                                    struct dma_fence **fence)
 354 {
 355         struct amdgpu_device *adev = ring->adev;
 356         struct dma_fence *f = NULL;
 357         struct amdgpu_job *job;
 358         struct amdgpu_ib *ib;
 359         uint64_t addr;
 360         int i, r;
 361
 362         r = amdgpu_job_alloc_with_ib(adev, 64, &job);
 363         if (r)
 364                 goto err;
 365
 366         ib = &job->ibs[0];
 367         addr = amdgpu_bo_gpu_offset(bo);
 368         ib->ptr[0] = PACKET0(adev->vcn.internal.data0, 0);
 369         ib->ptr[1] = addr;
 370         ib->ptr[2] = PACKET0(adev->vcn.internal.data1, 0);
 371         ib->ptr[3] = addr >> 32;
 372         ib->ptr[4] = PACKET0(adev->vcn.internal.cmd, 0);
 373         ib->ptr[5] = 0;
 374         for (i = 6; i < 16; i += 2) {
 375                 ib->ptr[i] = PACKET0(adev->vcn.internal.nop, 0);
 376                 ib->ptr[i+1] = 0;
 377         }
 378         ib->length_dw = 16;
 379
 380         r = amdgpu_job_submit_direct(job, ring, &f);
 381         if (r)
 382                 goto err_free;
 383
 384         amdgpu_bo_fence(bo, f, false);
 385         amdgpu_bo_unreserve(bo);
 386         amdgpu_bo_unref(&bo);
 387
 388         if (fence)
 389                 *fence = dma_fence_get(f);
 390         dma_fence_put(f);
 391
 392         return 0;
 393
 394 err_free:
 395         amdgpu_job_free(job);
 396
 397 err:
 398         amdgpu_bo_unreserve(bo);
 399         amdgpu_bo_unref(&bo);
 400         return r;
 401 }
 402
 403 static int amdgpu_vcn_dec_get_create_msg(struct amdgpu_ring *ring, uint32_t handle,
 404                               struct dma_fence **fence)
 405 {
 406         struct amdgpu_device *adev = ring->adev;
 407         struct amdgpu_bo *bo = NULL;
 408         uint32_t *msg;
 409         int r, i;
 410
 411         r = amdgpu_bo_create_reserved(adev, 1024, PAGE_SIZE,
 412                                       AMDGPU_GEM_DOMAIN_VRAM,
 413                                       &bo, NULL, (void **)&msg);
 414         if (r)
 415                 return r;
 416
 417         msg[0] = cpu_to_le32(0x00000028);
 418         msg[1] = cpu_to_le32(0x00000038);
 419         msg[2] = cpu_to_le32(0x00000001);
 420         msg[3] = cpu_to_le32(0x00000000);
 421         msg[4] = cpu_to_le32(handle);
 422         msg[5] = cpu_to_le32(0x00000000);
 423         msg[6] = cpu_to_le32(0x00000001);
 424         msg[7] = cpu_to_le32(0x00000028);
 425         msg[8] = cpu_to_le32(0x00000010);
 426         msg[9] = cpu_to_le32(0x00000000);
 427         msg[10] = cpu_to_le32(0x00000007);
 428         msg[11] = cpu_to_le32(0x00000000);
 429         msg[12] = cpu_to_le32(0x00000780);
 430         msg[13] = cpu_to_le32(0x00000440);
 431         for (i = 14; i < 1024; ++i)
 432                 msg[i] = cpu_to_le32(0x0);
 433
 434         return amdgpu_vcn_dec_send_msg(ring, bo, fence);
 435 }
 436
 437 static int amdgpu_vcn_dec_get_destroy_msg(struct amdgpu_ring *ring, uint32_t handle,
 438                                struct dma_fence **fence)
 439 {
 440         struct amdgpu_device *adev = ring->adev;
 441         struct amdgpu_bo *bo = NULL;
 442         uint32_t *msg;
 443         int r, i;
 444
 445         r = amdgpu_bo_create_reserved(adev, 1024, PAGE_SIZE,
 446                                       AMDGPU_GEM_DOMAIN_VRAM,
 447                                       &bo, NULL, (void **)&msg);
 448         if (r)
 449                 return r;
 450
 451         msg[0] = cpu_to_le32(0x00000028);
 452         msg[1] = cpu_to_le32(0x00000018);
 453         msg[2] = cpu_to_le32(0x00000000);
 454         msg[3] = cpu_to_le32(0x00000002);
 455         msg[4] = cpu_to_le32(handle);
 456         msg[5] = cpu_to_le32(0x00000000);
 457         for (i = 6; i < 1024; ++i)
 458                 msg[i] = cpu_to_le32(0x0);
 459
 460         return amdgpu_vcn_dec_send_msg(ring, bo, fence);
 461 }
 462
 463 int amdgpu_vcn_dec_ring_test_ib(struct amdgpu_ring *ring, long timeout)
 464 {
 465         struct dma_fence *fence;
 466         long r;
 467
 468         r = amdgpu_vcn_dec_get_create_msg(ring, 1, NULL);
 469         if (r)
 470                 goto error;
 471
 472         r = amdgpu_vcn_dec_get_destroy_msg(ring, 1, &fence);
 473         if (r)
 474                 goto error;
 475
 476         r = dma_fence_wait_timeout(fence, false, timeout);
 477         if (r == 0)
 478                 r = -ETIMEDOUT;
 479         else if (r > 0)
 480                 r = 0;
 481
 482         dma_fence_put(fence);
 483 error:
 484         return r;
 485 }
 486
 487 int amdgpu_vcn_enc_ring_test_ring(struct amdgpu_ring *ring)
 488 {
 489         struct amdgpu_device *adev = ring->adev;
 490         uint32_t rptr;
 491         unsigned i;
 492         int r;
 493
 494         r = amdgpu_ring_alloc(ring, 16);
 495         if (r)
 496                 return r;
 497
 498         rptr = amdgpu_ring_get_rptr(ring);
 499
 500         amdgpu_ring_write(ring, VCN_ENC_CMD_END);
 501         amdgpu_ring_commit(ring);
 502
 503         for (i = 0; i < adev->usec_timeout; i++) {
 504                 if (amdgpu_ring_get_rptr(ring) != rptr)
 505                         break;
 506                 DRM_UDELAY(1);
 507         }
 508
 509         if (i >= adev->usec_timeout)
 510                 r = -ETIMEDOUT;
 511
 512         return r;
 513 }
 514
 515 static int amdgpu_vcn_enc_get_create_msg(struct amdgpu_ring *ring, uint32_t handle,
 516                               struct dma_fence **fence)
 517 {
 518         const unsigned ib_size_dw = 16;
 519         struct amdgpu_job *job;
 520         struct amdgpu_ib *ib;
 521         struct dma_fence *f = NULL;
 522         uint64_t dummy;
 523         int i, r;
 524
 525         r = amdgpu_job_alloc_with_ib(ring->adev, ib_size_dw * 4, &job);
 526         if (r)
 527                 return r;
 528
 529         ib = &job->ibs[0];
 530         dummy = ib->gpu_addr + 1024;
 531
 532         ib->length_dw = 0;
 533         ib->ptr[ib->length_dw++] = 0x00000018;
 534         ib->ptr[ib->length_dw++] = 0x00000001; /* session info */
 535         ib->ptr[ib->length_dw++] = handle;
 536         ib->ptr[ib->length_dw++] = upper_32_bits(dummy);
 537         ib->ptr[ib->length_dw++] = dummy;
 538         ib->ptr[ib->length_dw++] = 0x0000000b;
 539
 540         ib->ptr[ib->length_dw++] = 0x00000014;
 541         ib->ptr[ib->length_dw++] = 0x00000002; /* task info */
 542         ib->ptr[ib->length_dw++] = 0x0000001c;
 543         ib->ptr[ib->length_dw++] = 0x00000000;
 544         ib->ptr[ib->length_dw++] = 0x00000000;
 545
 546         ib->ptr[ib->length_dw++] = 0x00000008;
 547         ib->ptr[ib->length_dw++] = 0x08000001; /* op initialize */
 548
 549         for (i = ib->length_dw; i < ib_size_dw; ++i)
 550                 ib->ptr[i] = 0x0;
 551
 552         r = amdgpu_job_submit_direct(job, ring, &f);
 553         if (r)
 554                 goto err;
 555
 556         if (fence)
 557                 *fence = dma_fence_get(f);
 558         dma_fence_put(f);
 559
 560         return 0;
 561
 562 err:
 563         amdgpu_job_free(job);
 564         return r;
 565 }
 566
 567 static int amdgpu_vcn_enc_get_destroy_msg(struct amdgpu_ring *ring, uint32_t handle,
 568                                 struct dma_fence **fence)
 569 {
 570         const unsigned ib_size_dw = 16;
 571         struct amdgpu_job *job;
 572         struct amdgpu_ib *ib;
 573         struct dma_fence *f = NULL;
 574         uint64_t dummy;
 575         int i, r;
 576
 577         r = amdgpu_job_alloc_with_ib(ring->adev, ib_size_dw * 4, &job);
 578         if (r)
 579                 return r;
 580
 581         ib = &job->ibs[0];
 582         dummy = ib->gpu_addr + 1024;
 583
 584         ib->length_dw = 0;
 585         ib->ptr[ib->length_dw++] = 0x00000018;
 586         ib->ptr[ib->length_dw++] = 0x00000001;
 587         ib->ptr[ib->length_dw++] = handle;
 588         ib->ptr[ib->length_dw++] = upper_32_bits(dummy);
 589         ib->ptr[ib->length_dw++] = dummy;
 590         ib->ptr[ib->length_dw++] = 0x0000000b;
 591
 592         ib->ptr[ib->length_dw++] = 0x00000014;
 593         ib->ptr[ib->length_dw++] = 0x00000002;
 594         ib->ptr[ib->length_dw++] = 0x0000001c;
 595         ib->ptr[ib->length_dw++] = 0x00000000;
 596         ib->ptr[ib->length_dw++] = 0x00000000;
 597
 598         ib->ptr[ib->length_dw++] = 0x00000008;
 599         ib->ptr[ib->length_dw++] = 0x08000002; /* op close session */
 600
 601         for (i = ib->length_dw; i < ib_size_dw; ++i)
 602                 ib->ptr[i] = 0x0;
 603
 604         r = amdgpu_job_submit_direct(job, ring, &f);
 605         if (r)
 606                 goto err;
 607
 608         if (fence)
 609                 *fence = dma_fence_get(f);
 610         dma_fence_put(f);
 611
 612         return 0;
 613
 614 err:
 615         amdgpu_job_free(job);
 616         return r;
 617 }
 618
 619 int amdgpu_vcn_enc_ring_test_ib(struct amdgpu_ring *ring, long timeout)
 620 {
 621         struct dma_fence *fence = NULL;
 622         long r;
 623
 624         r = amdgpu_vcn_enc_get_create_msg(ring, 1, NULL);
 625         if (r)
 626                 goto error;
 627
 628         r = amdgpu_vcn_enc_get_destroy_msg(ring, 1, &fence);
 629         if (r)
 630                 goto error;
 631
 632         r = dma_fence_wait_timeout(fence, false, timeout);
 633         if (r == 0)
 634                 r = -ETIMEDOUT;
 635         else if (r > 0)
 636                 r = 0;
 637
 638 error:
 639         dma_fence_put(fence);
 640         return r;
 641 }
 642
 643 int amdgpu_vcn_jpeg_ring_test_ring(struct amdgpu_ring *ring)
 644 {
 645         struct amdgpu_device *adev = ring->adev;
 646         uint32_t tmp = 0;
 647         unsigned i;
 648         int r;
 649
 650         WREG32(adev->vcn.external.jpeg_pitch, 0xCAFEDEAD);
 651         r = amdgpu_ring_alloc(ring, 3);
 652         if (r)
 653                 return r;
 654
 655         amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.jpeg_pitch, 0));
 656         amdgpu_ring_write(ring, 0xDEADBEEF);
 657         amdgpu_ring_commit(ring);
 658
 659         for (i = 0; i < adev->usec_timeout; i++) {
 660                 tmp = RREG32(adev->vcn.external.jpeg_pitch);
 661                 if (tmp == 0xDEADBEEF)
 662                         break;
 663                 DRM_UDELAY(1);
 664         }
 665
 666         if (i >= adev->usec_timeout)
 667                 r = -ETIMEDOUT;
 668
 669         return r;
 670 }
 671
 672 static int amdgpu_vcn_jpeg_set_reg(struct amdgpu_ring *ring, uint32_t handle,
 673                 struct dma_fence **fence)
 674 {
 675         struct amdgpu_device *adev = ring->adev;
 676         struct amdgpu_job *job;
 677         struct amdgpu_ib *ib;
 678         struct dma_fence *f = NULL;
 679         const unsigned ib_size_dw = 16;
 680         int i, r;
 681
 682         r = amdgpu_job_alloc_with_ib(ring->adev, ib_size_dw * 4, &job);
 683         if (r)
 684                 return r;
 685
 686         ib = &job->ibs[0];
 687
 688         ib->ptr[0] = PACKETJ(adev->vcn.internal.jpeg_pitch, 0, 0, PACKETJ_TYPE0);
 689         ib->ptr[1] = 0xDEADBEEF;
 690         for (i = 2; i < 16; i += 2) {
 691                 ib->ptr[i] = PACKETJ(0, 0, 0, PACKETJ_TYPE6);
 692                 ib->ptr[i+1] = 0;
 693         }
 694         ib->length_dw = 16;
 695
 696         r = amdgpu_job_submit_direct(job, ring, &f);
 697         if (r)
 698                 goto err;
 699
 700         if (fence)
 701                 *fence = dma_fence_get(f);
 702         dma_fence_put(f);
 703
 704         return 0;
 705
 706 err:
 707         amdgpu_job_free(job);
 708         return r;
 709 }
 710
 711 int amdgpu_vcn_jpeg_ring_test_ib(struct amdgpu_ring *ring, long timeout)
 712 {
 713         struct amdgpu_device *adev = ring->adev;
 714         uint32_t tmp = 0;
 715         unsigned i;
 716         struct dma_fence *fence = NULL;
 717         long r = 0;
 718
 719         r = amdgpu_vcn_jpeg_set_reg(ring, 1, &fence);
 720         if (r)
 721                 goto error;
 722
 723         r = dma_fence_wait_timeout(fence, false, timeout);
 724         if (r == 0) {
 725                 r = -ETIMEDOUT;
 726                 goto error;
 727         } else if (r < 0) {
 728                 goto error;
 729         } else {
 730                 r = 0;
 731         }
 732
 733         for (i = 0; i < adev->usec_timeout; i++) {
 734                 tmp = RREG32(adev->vcn.external.jpeg_pitch);
 735                 if (tmp == 0xDEADBEEF)
 736                         break;
 737                 DRM_UDELAY(1);
 738         }
 739
 740         if (i >= adev->usec_timeout)
 741                 r = -ETIMEDOUT;
 742
 743         dma_fence_put(fence);
 744 error:
 745         return r;
 746 }