2 * Copyright 2016 Advanced Micro Devices, Inc.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the
7 * "Software"), to deal in the Software without restriction, including
8 * without limitation the rights to use, copy, modify, merge, publish,
9 * distribute, sub license, and/or sell copies of the Software, and to
10 * permit persons to whom the Software is furnished to do so, subject to
11 * the following conditions:
13 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
14 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
15 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
16 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
17 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
18 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
19 * USE OR OTHER DEALINGS IN THE SOFTWARE.
21 * The above copyright notice and this permission notice (including the
22 * next paragraph) shall be included in all copies or substantial portions
27 #include <linux/firmware.h>
28 #include <linux/module.h>
29 #include <linux/pci.h>
32 #include "amdgpu_pm.h"
33 #include "amdgpu_vcn.h"
37 #define FIRMWARE_RAVEN "amdgpu/raven_vcn.bin"
38 #define FIRMWARE_PICASSO "amdgpu/picasso_vcn.bin"
39 #define FIRMWARE_RAVEN2 "amdgpu/raven2_vcn.bin"
40 #define FIRMWARE_ARCTURUS "amdgpu/arcturus_vcn.bin"
41 #define FIRMWARE_RENOIR "amdgpu/renoir_vcn.bin"
42 #define FIRMWARE_GREEN_SARDINE "amdgpu/green_sardine_vcn.bin"
43 #define FIRMWARE_NAVI10 "amdgpu/navi10_vcn.bin"
44 #define FIRMWARE_NAVI14 "amdgpu/navi14_vcn.bin"
45 #define FIRMWARE_NAVI12 "amdgpu/navi12_vcn.bin"
46 #define FIRMWARE_SIENNA_CICHLID "amdgpu/sienna_cichlid_vcn.bin"
47 #define FIRMWARE_NAVY_FLOUNDER "amdgpu/navy_flounder_vcn.bin"
48 #define FIRMWARE_VANGOGH "amdgpu/vangogh_vcn.bin"
49 #define FIRMWARE_DIMGREY_CAVEFISH "amdgpu/dimgrey_cavefish_vcn.bin"
50 #define FIRMWARE_ALDEBARAN "amdgpu/aldebaran_vcn.bin"
52 MODULE_FIRMWARE(FIRMWARE_RAVEN);
53 MODULE_FIRMWARE(FIRMWARE_PICASSO);
54 MODULE_FIRMWARE(FIRMWARE_RAVEN2);
55 MODULE_FIRMWARE(FIRMWARE_ARCTURUS);
56 MODULE_FIRMWARE(FIRMWARE_RENOIR);
57 MODULE_FIRMWARE(FIRMWARE_GREEN_SARDINE);
58 MODULE_FIRMWARE(FIRMWARE_ALDEBARAN);
59 MODULE_FIRMWARE(FIRMWARE_NAVI10);
60 MODULE_FIRMWARE(FIRMWARE_NAVI14);
61 MODULE_FIRMWARE(FIRMWARE_NAVI12);
62 MODULE_FIRMWARE(FIRMWARE_SIENNA_CICHLID);
63 MODULE_FIRMWARE(FIRMWARE_NAVY_FLOUNDER);
64 MODULE_FIRMWARE(FIRMWARE_VANGOGH);
65 MODULE_FIRMWARE(FIRMWARE_DIMGREY_CAVEFISH);
67 static void amdgpu_vcn_idle_work_handler(struct work_struct *work);
69 int amdgpu_vcn_sw_init(struct amdgpu_device *adev)
71 unsigned long bo_size;
73 const struct common_firmware_header *hdr;
74 unsigned char fw_check;
77 INIT_DELAYED_WORK(&adev->vcn.idle_work, amdgpu_vcn_idle_work_handler);
78 mutex_init(&adev->vcn.vcn_pg_lock);
79 mutex_init(&adev->vcn.vcn1_jpeg1_workaround);
80 atomic_set(&adev->vcn.total_submission_cnt, 0);
81 for (i = 0; i < adev->vcn.num_vcn_inst; i++)
82 atomic_set(&adev->vcn.inst[i].dpg_enc_submission_cnt, 0);
84 switch (adev->asic_type) {
86 if (adev->apu_flags & AMD_APU_IS_RAVEN2)
87 fw_name = FIRMWARE_RAVEN2;
88 else if (adev->apu_flags & AMD_APU_IS_PICASSO)
89 fw_name = FIRMWARE_PICASSO;
91 fw_name = FIRMWARE_RAVEN;
94 fw_name = FIRMWARE_ARCTURUS;
95 if ((adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) &&
96 (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG))
97 adev->vcn.indirect_sram = true;
100 if (adev->apu_flags & AMD_APU_IS_RENOIR)
101 fw_name = FIRMWARE_RENOIR;
103 fw_name = FIRMWARE_GREEN_SARDINE;
105 if ((adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) &&
106 (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG))
107 adev->vcn.indirect_sram = true;
110 fw_name = FIRMWARE_ALDEBARAN;
111 if ((adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) &&
112 (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG))
113 adev->vcn.indirect_sram = true;
116 fw_name = FIRMWARE_NAVI10;
117 if ((adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) &&
118 (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG))
119 adev->vcn.indirect_sram = true;
122 fw_name = FIRMWARE_NAVI14;
123 if ((adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) &&
124 (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG))
125 adev->vcn.indirect_sram = true;
128 fw_name = FIRMWARE_NAVI12;
129 if ((adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) &&
130 (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG))
131 adev->vcn.indirect_sram = true;
133 case CHIP_SIENNA_CICHLID:
134 fw_name = FIRMWARE_SIENNA_CICHLID;
135 if ((adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) &&
136 (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG))
137 adev->vcn.indirect_sram = true;
139 case CHIP_NAVY_FLOUNDER:
140 fw_name = FIRMWARE_NAVY_FLOUNDER;
141 if ((adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) &&
142 (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG))
143 adev->vcn.indirect_sram = true;
146 fw_name = FIRMWARE_VANGOGH;
148 case CHIP_DIMGREY_CAVEFISH:
149 fw_name = FIRMWARE_DIMGREY_CAVEFISH;
150 if ((adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) &&
151 (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG))
152 adev->vcn.indirect_sram = true;
158 r = request_firmware(&adev->vcn.fw, fw_name, adev->dev);
160 dev_err(adev->dev, "amdgpu_vcn: Can't load firmware \"%s\"\n",
165 r = amdgpu_ucode_validate(adev->vcn.fw);
167 dev_err(adev->dev, "amdgpu_vcn: Can't validate firmware \"%s\"\n",
169 release_firmware(adev->vcn.fw);
174 hdr = (const struct common_firmware_header *)adev->vcn.fw->data;
175 adev->vcn.fw_version = le32_to_cpu(hdr->ucode_version);
177 /* Bit 20-23, it is encode major and non-zero for new naming convention.
178 * This field is part of version minor and DRM_DISABLED_FLAG in old naming
179 * convention. Since the l:wq!atest version minor is 0x5B and DRM_DISABLED_FLAG
180 * is zero in old naming convention, this field is always zero so far.
181 * These four bits are used to tell which naming convention is present.
183 fw_check = (le32_to_cpu(hdr->ucode_version) >> 20) & 0xf;
185 unsigned int dec_ver, enc_major, enc_minor, vep, fw_rev;
187 fw_rev = le32_to_cpu(hdr->ucode_version) & 0xfff;
188 enc_minor = (le32_to_cpu(hdr->ucode_version) >> 12) & 0xff;
189 enc_major = fw_check;
190 dec_ver = (le32_to_cpu(hdr->ucode_version) >> 24) & 0xf;
191 vep = (le32_to_cpu(hdr->ucode_version) >> 28) & 0xf;
192 DRM_INFO("Found VCN firmware Version ENC: %u.%u DEC: %u VEP: %u Revision: %u\n",
193 enc_major, enc_minor, dec_ver, vep, fw_rev);
195 unsigned int version_major, version_minor, family_id;
197 family_id = le32_to_cpu(hdr->ucode_version) & 0xff;
198 version_major = (le32_to_cpu(hdr->ucode_version) >> 24) & 0xff;
199 version_minor = (le32_to_cpu(hdr->ucode_version) >> 8) & 0xff;
200 DRM_INFO("Found VCN firmware Version: %u.%u Family ID: %u\n",
201 version_major, version_minor, family_id);
204 bo_size = AMDGPU_VCN_STACK_SIZE + AMDGPU_VCN_CONTEXT_SIZE;
205 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP)
206 bo_size += AMDGPU_GPU_PAGE_ALIGN(le32_to_cpu(hdr->ucode_size_bytes) + 8);
207 bo_size += AMDGPU_GPU_PAGE_ALIGN(sizeof(struct amdgpu_fw_shared));
209 for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
210 if (adev->vcn.harvest_config & (1 << i))
213 r = amdgpu_bo_create_kernel(adev, bo_size, PAGE_SIZE,
214 AMDGPU_GEM_DOMAIN_VRAM, &adev->vcn.inst[i].vcpu_bo,
215 &adev->vcn.inst[i].gpu_addr, &adev->vcn.inst[i].cpu_addr);
217 dev_err(adev->dev, "(%d) failed to allocate vcn bo\n", r);
221 adev->vcn.inst[i].fw_shared_cpu_addr = adev->vcn.inst[i].cpu_addr +
222 bo_size - AMDGPU_GPU_PAGE_ALIGN(sizeof(struct amdgpu_fw_shared));
223 adev->vcn.inst[i].fw_shared_gpu_addr = adev->vcn.inst[i].gpu_addr +
224 bo_size - AMDGPU_GPU_PAGE_ALIGN(sizeof(struct amdgpu_fw_shared));
226 if (adev->vcn.indirect_sram) {
227 r = amdgpu_bo_create_kernel(adev, 64 * 2 * 4, PAGE_SIZE,
228 AMDGPU_GEM_DOMAIN_VRAM, &adev->vcn.inst[i].dpg_sram_bo,
229 &adev->vcn.inst[i].dpg_sram_gpu_addr, &adev->vcn.inst[i].dpg_sram_cpu_addr);
231 dev_err(adev->dev, "VCN %d (%d) failed to allocate DPG bo\n", i, r);
240 int amdgpu_vcn_sw_fini(struct amdgpu_device *adev)
244 cancel_delayed_work_sync(&adev->vcn.idle_work);
246 for (j = 0; j < adev->vcn.num_vcn_inst; ++j) {
247 if (adev->vcn.harvest_config & (1 << j))
250 if (adev->vcn.indirect_sram) {
251 amdgpu_bo_free_kernel(&adev->vcn.inst[j].dpg_sram_bo,
252 &adev->vcn.inst[j].dpg_sram_gpu_addr,
253 (void **)&adev->vcn.inst[j].dpg_sram_cpu_addr);
255 kvfree(adev->vcn.inst[j].saved_bo);
257 amdgpu_bo_free_kernel(&adev->vcn.inst[j].vcpu_bo,
258 &adev->vcn.inst[j].gpu_addr,
259 (void **)&adev->vcn.inst[j].cpu_addr);
261 amdgpu_ring_fini(&adev->vcn.inst[j].ring_dec);
263 for (i = 0; i < adev->vcn.num_enc_rings; ++i)
264 amdgpu_ring_fini(&adev->vcn.inst[j].ring_enc[i]);
267 release_firmware(adev->vcn.fw);
268 mutex_destroy(&adev->vcn.vcn1_jpeg1_workaround);
269 mutex_destroy(&adev->vcn.vcn_pg_lock);
274 int amdgpu_vcn_suspend(struct amdgpu_device *adev)
280 cancel_delayed_work_sync(&adev->vcn.idle_work);
282 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
283 if (adev->vcn.harvest_config & (1 << i))
285 if (adev->vcn.inst[i].vcpu_bo == NULL)
288 size = amdgpu_bo_size(adev->vcn.inst[i].vcpu_bo);
289 ptr = adev->vcn.inst[i].cpu_addr;
291 adev->vcn.inst[i].saved_bo = kvmalloc(size, GFP_KERNEL);
292 if (!adev->vcn.inst[i].saved_bo)
295 memcpy_fromio(adev->vcn.inst[i].saved_bo, ptr, size);
300 int amdgpu_vcn_resume(struct amdgpu_device *adev)
306 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
307 if (adev->vcn.harvest_config & (1 << i))
309 if (adev->vcn.inst[i].vcpu_bo == NULL)
312 size = amdgpu_bo_size(adev->vcn.inst[i].vcpu_bo);
313 ptr = adev->vcn.inst[i].cpu_addr;
315 if (adev->vcn.inst[i].saved_bo != NULL) {
316 memcpy_toio(ptr, adev->vcn.inst[i].saved_bo, size);
317 kvfree(adev->vcn.inst[i].saved_bo);
318 adev->vcn.inst[i].saved_bo = NULL;
320 const struct common_firmware_header *hdr;
323 hdr = (const struct common_firmware_header *)adev->vcn.fw->data;
324 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) {
325 offset = le32_to_cpu(hdr->ucode_array_offset_bytes);
326 memcpy_toio(adev->vcn.inst[i].cpu_addr, adev->vcn.fw->data + offset,
327 le32_to_cpu(hdr->ucode_size_bytes));
328 size -= le32_to_cpu(hdr->ucode_size_bytes);
329 ptr += le32_to_cpu(hdr->ucode_size_bytes);
331 memset_io(ptr, 0, size);
337 static void amdgpu_vcn_idle_work_handler(struct work_struct *work)
339 struct amdgpu_device *adev =
340 container_of(work, struct amdgpu_device, vcn.idle_work.work);
341 unsigned int fences = 0, fence[AMDGPU_MAX_VCN_INSTANCES] = {0};
345 for (j = 0; j < adev->vcn.num_vcn_inst; ++j) {
346 if (adev->vcn.harvest_config & (1 << j))
349 for (i = 0; i < adev->vcn.num_enc_rings; ++i) {
350 fence[j] += amdgpu_fence_count_emitted(&adev->vcn.inst[j].ring_enc[i]);
353 if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) {
354 struct dpg_pause_state new_state;
357 unlikely(atomic_read(&adev->vcn.inst[j].dpg_enc_submission_cnt)))
358 new_state.fw_based = VCN_DPG_STATE__PAUSE;
360 new_state.fw_based = VCN_DPG_STATE__UNPAUSE;
362 adev->vcn.pause_dpg_mode(adev, j, &new_state);
365 fence[j] += amdgpu_fence_count_emitted(&adev->vcn.inst[j].ring_dec);
369 if (!fences && !atomic_read(&adev->vcn.total_submission_cnt)) {
370 amdgpu_gfx_off_ctrl(adev, true);
371 amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_VCN,
373 r = amdgpu_dpm_switch_power_profile(adev, PP_SMC_POWER_PROFILE_VIDEO,
376 dev_warn(adev->dev, "(%d) failed to disable video power profile mode\n", r);
378 schedule_delayed_work(&adev->vcn.idle_work, VCN_IDLE_TIMEOUT);
382 void amdgpu_vcn_ring_begin_use(struct amdgpu_ring *ring)
384 struct amdgpu_device *adev = ring->adev;
387 atomic_inc(&adev->vcn.total_submission_cnt);
389 if (!cancel_delayed_work_sync(&adev->vcn.idle_work)) {
390 amdgpu_gfx_off_ctrl(adev, false);
391 r = amdgpu_dpm_switch_power_profile(adev, PP_SMC_POWER_PROFILE_VIDEO,
394 dev_warn(adev->dev, "(%d) failed to switch to video power profile mode\n", r);
397 mutex_lock(&adev->vcn.vcn_pg_lock);
398 amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_VCN,
399 AMD_PG_STATE_UNGATE);
401 if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) {
402 struct dpg_pause_state new_state;
404 if (ring->funcs->type == AMDGPU_RING_TYPE_VCN_ENC) {
405 atomic_inc(&adev->vcn.inst[ring->me].dpg_enc_submission_cnt);
406 new_state.fw_based = VCN_DPG_STATE__PAUSE;
408 unsigned int fences = 0;
411 for (i = 0; i < adev->vcn.num_enc_rings; ++i)
412 fences += amdgpu_fence_count_emitted(&adev->vcn.inst[ring->me].ring_enc[i]);
414 if (fences || atomic_read(&adev->vcn.inst[ring->me].dpg_enc_submission_cnt))
415 new_state.fw_based = VCN_DPG_STATE__PAUSE;
417 new_state.fw_based = VCN_DPG_STATE__UNPAUSE;
420 adev->vcn.pause_dpg_mode(adev, ring->me, &new_state);
422 mutex_unlock(&adev->vcn.vcn_pg_lock);
425 void amdgpu_vcn_ring_end_use(struct amdgpu_ring *ring)
427 if (ring->adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG &&
428 ring->funcs->type == AMDGPU_RING_TYPE_VCN_ENC)
429 atomic_dec(&ring->adev->vcn.inst[ring->me].dpg_enc_submission_cnt);
431 atomic_dec(&ring->adev->vcn.total_submission_cnt);
433 schedule_delayed_work(&ring->adev->vcn.idle_work, VCN_IDLE_TIMEOUT);
436 int amdgpu_vcn_dec_ring_test_ring(struct amdgpu_ring *ring)
438 struct amdgpu_device *adev = ring->adev;
443 /* VCN in SRIOV does not support direct register read/write */
444 if (amdgpu_sriov_vf(adev))
447 WREG32(adev->vcn.inst[ring->me].external.scratch9, 0xCAFEDEAD);
448 r = amdgpu_ring_alloc(ring, 3);
451 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.scratch9, 0));
452 amdgpu_ring_write(ring, 0xDEADBEEF);
453 amdgpu_ring_commit(ring);
454 for (i = 0; i < adev->usec_timeout; i++) {
455 tmp = RREG32(adev->vcn.inst[ring->me].external.scratch9);
456 if (tmp == 0xDEADBEEF)
461 if (i >= adev->usec_timeout)
467 int amdgpu_vcn_dec_sw_ring_test_ring(struct amdgpu_ring *ring)
469 struct amdgpu_device *adev = ring->adev;
474 if (amdgpu_sriov_vf(adev))
477 r = amdgpu_ring_alloc(ring, 16);
481 rptr = amdgpu_ring_get_rptr(ring);
483 amdgpu_ring_write(ring, VCN_DEC_SW_CMD_END);
484 amdgpu_ring_commit(ring);
486 for (i = 0; i < adev->usec_timeout; i++) {
487 if (amdgpu_ring_get_rptr(ring) != rptr)
492 if (i >= adev->usec_timeout)
498 static int amdgpu_vcn_dec_send_msg(struct amdgpu_ring *ring,
499 struct amdgpu_bo *bo,
500 struct dma_fence **fence)
502 struct amdgpu_device *adev = ring->adev;
503 struct dma_fence *f = NULL;
504 struct amdgpu_job *job;
505 struct amdgpu_ib *ib;
510 r = amdgpu_job_alloc_with_ib(adev, 64,
511 AMDGPU_IB_POOL_DIRECT, &job);
516 addr = amdgpu_bo_gpu_offset(bo);
517 msg = amdgpu_bo_kptr(bo);
518 ib->ptr[0] = PACKET0(adev->vcn.internal.data0, 0);
520 ib->ptr[2] = PACKET0(adev->vcn.internal.data1, 0);
521 ib->ptr[3] = addr >> 32;
522 ib->ptr[4] = PACKET0(adev->vcn.internal.cmd, 0);
524 for (i = 6; i < 16; i += 2) {
525 ib->ptr[i] = PACKET0(adev->vcn.internal.nop, 0);
530 r = amdgpu_job_submit_direct(job, ring, &f);
534 amdgpu_bo_fence(bo, f, false);
535 amdgpu_bo_unreserve(bo);
536 amdgpu_bo_free_kernel(&bo, NULL, (void **)&msg);
539 *fence = dma_fence_get(f);
545 amdgpu_job_free(job);
548 amdgpu_bo_unreserve(bo);
549 amdgpu_bo_free_kernel(&bo, NULL, (void **)&msg);
553 static int amdgpu_vcn_dec_get_create_msg(struct amdgpu_ring *ring, uint32_t handle,
554 struct amdgpu_bo **bo)
556 struct amdgpu_device *adev = ring->adev;
561 r = amdgpu_bo_create_reserved(adev, 1024, PAGE_SIZE,
562 AMDGPU_GEM_DOMAIN_VRAM,
563 bo, NULL, (void **)&msg);
567 msg[0] = cpu_to_le32(0x00000028);
568 msg[1] = cpu_to_le32(0x00000038);
569 msg[2] = cpu_to_le32(0x00000001);
570 msg[3] = cpu_to_le32(0x00000000);
571 msg[4] = cpu_to_le32(handle);
572 msg[5] = cpu_to_le32(0x00000000);
573 msg[6] = cpu_to_le32(0x00000001);
574 msg[7] = cpu_to_le32(0x00000028);
575 msg[8] = cpu_to_le32(0x00000010);
576 msg[9] = cpu_to_le32(0x00000000);
577 msg[10] = cpu_to_le32(0x00000007);
578 msg[11] = cpu_to_le32(0x00000000);
579 msg[12] = cpu_to_le32(0x00000780);
580 msg[13] = cpu_to_le32(0x00000440);
581 for (i = 14; i < 1024; ++i)
582 msg[i] = cpu_to_le32(0x0);
587 static int amdgpu_vcn_dec_get_destroy_msg(struct amdgpu_ring *ring, uint32_t handle,
588 struct amdgpu_bo **bo)
590 struct amdgpu_device *adev = ring->adev;
595 r = amdgpu_bo_create_reserved(adev, 1024, PAGE_SIZE,
596 AMDGPU_GEM_DOMAIN_VRAM,
597 bo, NULL, (void **)&msg);
601 msg[0] = cpu_to_le32(0x00000028);
602 msg[1] = cpu_to_le32(0x00000018);
603 msg[2] = cpu_to_le32(0x00000000);
604 msg[3] = cpu_to_le32(0x00000002);
605 msg[4] = cpu_to_le32(handle);
606 msg[5] = cpu_to_le32(0x00000000);
607 for (i = 6; i < 1024; ++i)
608 msg[i] = cpu_to_le32(0x0);
613 int amdgpu_vcn_dec_ring_test_ib(struct amdgpu_ring *ring, long timeout)
615 struct dma_fence *fence = NULL;
616 struct amdgpu_bo *bo;
619 r = amdgpu_vcn_dec_get_create_msg(ring, 1, &bo);
623 r = amdgpu_vcn_dec_send_msg(ring, bo, NULL);
626 r = amdgpu_vcn_dec_get_destroy_msg(ring, 1, &bo);
630 r = amdgpu_vcn_dec_send_msg(ring, bo, &fence);
634 r = dma_fence_wait_timeout(fence, false, timeout);
640 dma_fence_put(fence);
645 static int amdgpu_vcn_dec_sw_send_msg(struct amdgpu_ring *ring,
646 struct amdgpu_bo *bo,
647 struct dma_fence **fence)
649 struct amdgpu_vcn_decode_buffer *decode_buffer = NULL;
650 const unsigned int ib_size_dw = 64;
651 struct amdgpu_device *adev = ring->adev;
652 struct dma_fence *f = NULL;
653 struct amdgpu_job *job;
654 struct amdgpu_ib *ib;
658 r = amdgpu_job_alloc_with_ib(adev, ib_size_dw * 4,
659 AMDGPU_IB_POOL_DIRECT, &job);
664 addr = amdgpu_bo_gpu_offset(bo);
667 ib->ptr[ib->length_dw++] = sizeof(struct amdgpu_vcn_decode_buffer) + 8;
668 ib->ptr[ib->length_dw++] = cpu_to_le32(AMDGPU_VCN_IB_FLAG_DECODE_BUFFER);
669 decode_buffer = (struct amdgpu_vcn_decode_buffer *)&(ib->ptr[ib->length_dw]);
670 ib->length_dw += sizeof(struct amdgpu_vcn_decode_buffer) / 4;
671 memset(decode_buffer, 0, sizeof(struct amdgpu_vcn_decode_buffer));
673 decode_buffer->valid_buf_flag |= cpu_to_le32(AMDGPU_VCN_CMD_FLAG_MSG_BUFFER);
674 decode_buffer->msg_buffer_address_hi = cpu_to_le32(addr >> 32);
675 decode_buffer->msg_buffer_address_lo = cpu_to_le32(addr);
677 for (i = ib->length_dw; i < ib_size_dw; ++i)
680 r = amdgpu_job_submit_direct(job, ring, &f);
684 amdgpu_bo_fence(bo, f, false);
685 amdgpu_bo_unreserve(bo);
686 amdgpu_bo_unref(&bo);
689 *fence = dma_fence_get(f);
695 amdgpu_job_free(job);
698 amdgpu_bo_unreserve(bo);
699 amdgpu_bo_unref(&bo);
703 int amdgpu_vcn_dec_sw_ring_test_ib(struct amdgpu_ring *ring, long timeout)
705 struct dma_fence *fence = NULL;
706 struct amdgpu_bo *bo;
709 r = amdgpu_vcn_dec_get_create_msg(ring, 1, &bo);
713 r = amdgpu_vcn_dec_sw_send_msg(ring, bo, NULL);
716 r = amdgpu_vcn_dec_get_destroy_msg(ring, 1, &bo);
720 r = amdgpu_vcn_dec_sw_send_msg(ring, bo, &fence);
724 r = dma_fence_wait_timeout(fence, false, timeout);
730 dma_fence_put(fence);
735 int amdgpu_vcn_enc_ring_test_ring(struct amdgpu_ring *ring)
737 struct amdgpu_device *adev = ring->adev;
742 if (amdgpu_sriov_vf(adev))
745 r = amdgpu_ring_alloc(ring, 16);
749 rptr = amdgpu_ring_get_rptr(ring);
751 amdgpu_ring_write(ring, VCN_ENC_CMD_END);
752 amdgpu_ring_commit(ring);
754 for (i = 0; i < adev->usec_timeout; i++) {
755 if (amdgpu_ring_get_rptr(ring) != rptr)
760 if (i >= adev->usec_timeout)
766 static int amdgpu_vcn_enc_get_create_msg(struct amdgpu_ring *ring, uint32_t handle,
767 struct amdgpu_bo *bo,
768 struct dma_fence **fence)
770 const unsigned ib_size_dw = 16;
771 struct amdgpu_job *job;
772 struct amdgpu_ib *ib;
773 struct dma_fence *f = NULL;
777 r = amdgpu_job_alloc_with_ib(ring->adev, ib_size_dw * 4,
778 AMDGPU_IB_POOL_DIRECT, &job);
783 addr = amdgpu_bo_gpu_offset(bo);
786 ib->ptr[ib->length_dw++] = 0x00000018;
787 ib->ptr[ib->length_dw++] = 0x00000001; /* session info */
788 ib->ptr[ib->length_dw++] = handle;
789 ib->ptr[ib->length_dw++] = upper_32_bits(addr);
790 ib->ptr[ib->length_dw++] = addr;
791 ib->ptr[ib->length_dw++] = 0x0000000b;
793 ib->ptr[ib->length_dw++] = 0x00000014;
794 ib->ptr[ib->length_dw++] = 0x00000002; /* task info */
795 ib->ptr[ib->length_dw++] = 0x0000001c;
796 ib->ptr[ib->length_dw++] = 0x00000000;
797 ib->ptr[ib->length_dw++] = 0x00000000;
799 ib->ptr[ib->length_dw++] = 0x00000008;
800 ib->ptr[ib->length_dw++] = 0x08000001; /* op initialize */
802 for (i = ib->length_dw; i < ib_size_dw; ++i)
805 r = amdgpu_job_submit_direct(job, ring, &f);
810 *fence = dma_fence_get(f);
816 amdgpu_job_free(job);
820 static int amdgpu_vcn_enc_get_destroy_msg(struct amdgpu_ring *ring, uint32_t handle,
821 struct amdgpu_bo *bo,
822 struct dma_fence **fence)
824 const unsigned ib_size_dw = 16;
825 struct amdgpu_job *job;
826 struct amdgpu_ib *ib;
827 struct dma_fence *f = NULL;
831 r = amdgpu_job_alloc_with_ib(ring->adev, ib_size_dw * 4,
832 AMDGPU_IB_POOL_DIRECT, &job);
837 addr = amdgpu_bo_gpu_offset(bo);
840 ib->ptr[ib->length_dw++] = 0x00000018;
841 ib->ptr[ib->length_dw++] = 0x00000001;
842 ib->ptr[ib->length_dw++] = handle;
843 ib->ptr[ib->length_dw++] = upper_32_bits(addr);
844 ib->ptr[ib->length_dw++] = addr;
845 ib->ptr[ib->length_dw++] = 0x0000000b;
847 ib->ptr[ib->length_dw++] = 0x00000014;
848 ib->ptr[ib->length_dw++] = 0x00000002;
849 ib->ptr[ib->length_dw++] = 0x0000001c;
850 ib->ptr[ib->length_dw++] = 0x00000000;
851 ib->ptr[ib->length_dw++] = 0x00000000;
853 ib->ptr[ib->length_dw++] = 0x00000008;
854 ib->ptr[ib->length_dw++] = 0x08000002; /* op close session */
856 for (i = ib->length_dw; i < ib_size_dw; ++i)
859 r = amdgpu_job_submit_direct(job, ring, &f);
864 *fence = dma_fence_get(f);
870 amdgpu_job_free(job);
874 int amdgpu_vcn_enc_ring_test_ib(struct amdgpu_ring *ring, long timeout)
876 struct dma_fence *fence = NULL;
877 struct amdgpu_bo *bo = NULL;
880 r = amdgpu_bo_create_reserved(ring->adev, 128 * 1024, PAGE_SIZE,
881 AMDGPU_GEM_DOMAIN_VRAM,
886 r = amdgpu_vcn_enc_get_create_msg(ring, 1, bo, NULL);
890 r = amdgpu_vcn_enc_get_destroy_msg(ring, 1, bo, &fence);
894 r = dma_fence_wait_timeout(fence, false, timeout);
901 dma_fence_put(fence);
902 amdgpu_bo_unreserve(bo);
903 amdgpu_bo_free_kernel(&bo, NULL, NULL);