drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c

   1 /*
   2  * Copyright 2013 Advanced Micro Devices, Inc.
   3  * All Rights Reserved.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the
   7  * "Software"), to deal in the Software without restriction, including
   8  * without limitation the rights to use, copy, modify, merge, publish,
   9  * distribute, sub license, and/or sell copies of the Software, and to
  10  * permit persons to whom the Software is furnished to do so, subject to
  11  * the following conditions:
  12  *
  13  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  14  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  15  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  16  * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
  17  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  18  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  19  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  20  *
  21  * The above copyright notice and this permission notice (including the
  22  * next paragraph) shall be included in all copies or substantial portions
  23  * of the Software.
  24  *
  25  * Authors: Christian König <christian.koenig@amd.com>
  26  */
  27
  28 #include <linux/firmware.h>
  29 #include <linux/module.h>
  30
  31 #include <drm/drm.h>
  32
  33 #include "amdgpu.h"
  34 #include "amdgpu_pm.h"
  35 #include "amdgpu_vce.h"
  36 #include "cikd.h"
  37
  38 /* 1 second timeout */
  39 #define VCE_IDLE_TIMEOUT        msecs_to_jiffies(1000)
  40
  41 /* Firmware Names */
  42 #ifdef CONFIG_DRM_AMDGPU_CIK
  43 #define FIRMWARE_BONAIRE        "amdgpu/bonaire_vce.bin"
  44 #define FIRMWARE_KABINI "amdgpu/kabini_vce.bin"
  45 #define FIRMWARE_KAVERI "amdgpu/kaveri_vce.bin"
  46 #define FIRMWARE_HAWAII "amdgpu/hawaii_vce.bin"
  47 #define FIRMWARE_MULLINS        "amdgpu/mullins_vce.bin"
  48 #endif
  49 #define FIRMWARE_TONGA          "amdgpu/tonga_vce.bin"
  50 #define FIRMWARE_CARRIZO        "amdgpu/carrizo_vce.bin"
  51 #define FIRMWARE_FIJI           "amdgpu/fiji_vce.bin"
  52 #define FIRMWARE_STONEY         "amdgpu/stoney_vce.bin"
  53 #define FIRMWARE_POLARIS10      "amdgpu/polaris10_vce.bin"
  54 #define FIRMWARE_POLARIS11      "amdgpu/polaris11_vce.bin"
  55 #define FIRMWARE_POLARIS12      "amdgpu/polaris12_vce.bin"
  56 #define FIRMWARE_VEGAM          "amdgpu/vegam_vce.bin"
  57
  58 #define FIRMWARE_VEGA10         "amdgpu/vega10_vce.bin"
  59 #define FIRMWARE_VEGA12         "amdgpu/vega12_vce.bin"
  60 #define FIRMWARE_VEGA20         "amdgpu/vega20_vce.bin"
  61
  62 #ifdef CONFIG_DRM_AMDGPU_CIK
  63 MODULE_FIRMWARE(FIRMWARE_BONAIRE);
  64 MODULE_FIRMWARE(FIRMWARE_KABINI);
  65 MODULE_FIRMWARE(FIRMWARE_KAVERI);
  66 MODULE_FIRMWARE(FIRMWARE_HAWAII);
  67 MODULE_FIRMWARE(FIRMWARE_MULLINS);
  68 #endif
  69 MODULE_FIRMWARE(FIRMWARE_TONGA);
  70 MODULE_FIRMWARE(FIRMWARE_CARRIZO);
  71 MODULE_FIRMWARE(FIRMWARE_FIJI);
  72 MODULE_FIRMWARE(FIRMWARE_STONEY);
  73 MODULE_FIRMWARE(FIRMWARE_POLARIS10);
  74 MODULE_FIRMWARE(FIRMWARE_POLARIS11);
  75 MODULE_FIRMWARE(FIRMWARE_POLARIS12);
  76 MODULE_FIRMWARE(FIRMWARE_VEGAM);
  77
  78 MODULE_FIRMWARE(FIRMWARE_VEGA10);
  79 MODULE_FIRMWARE(FIRMWARE_VEGA12);
  80 MODULE_FIRMWARE(FIRMWARE_VEGA20);
  81
  82 static void amdgpu_vce_idle_work_handler(struct work_struct *work);
  83 static int amdgpu_vce_get_create_msg(struct amdgpu_ring *ring, uint32_t handle,
  84                                      struct amdgpu_bo *bo,
  85                                      struct dma_fence **fence);
  86 static int amdgpu_vce_get_destroy_msg(struct amdgpu_ring *ring, uint32_t handle,
  87                                       bool direct, struct dma_fence **fence);
  88
  89 /**
  90  * amdgpu_vce_init - allocate memory, load vce firmware
  91  *
  92  * @adev: amdgpu_device pointer
  93  *
  94  * First step to get VCE online, allocate memory and load the firmware
  95  */
  96 int amdgpu_vce_sw_init(struct amdgpu_device *adev, unsigned long size)
  97 {
  98         const char *fw_name;
  99         const struct common_firmware_header *hdr;
 100         unsigned ucode_version, version_major, version_minor, binary_id;
 101         int i, r;
 102
 103         switch (adev->asic_type) {
 104 #ifdef CONFIG_DRM_AMDGPU_CIK
 105         case CHIP_BONAIRE:
 106                 fw_name = FIRMWARE_BONAIRE;
 107                 break;
 108         case CHIP_KAVERI:
 109                 fw_name = FIRMWARE_KAVERI;
 110                 break;
 111         case CHIP_KABINI:
 112                 fw_name = FIRMWARE_KABINI;
 113                 break;
 114         case CHIP_HAWAII:
 115                 fw_name = FIRMWARE_HAWAII;
 116                 break;
 117         case CHIP_MULLINS:
 118                 fw_name = FIRMWARE_MULLINS;
 119                 break;
 120 #endif
 121         case CHIP_TONGA:
 122                 fw_name = FIRMWARE_TONGA;
 123                 break;
 124         case CHIP_CARRIZO:
 125                 fw_name = FIRMWARE_CARRIZO;
 126                 break;
 127         case CHIP_FIJI:
 128                 fw_name = FIRMWARE_FIJI;
 129                 break;
 130         case CHIP_STONEY:
 131                 fw_name = FIRMWARE_STONEY;
 132                 break;
 133         case CHIP_POLARIS10:
 134                 fw_name = FIRMWARE_POLARIS10;
 135                 break;
 136         case CHIP_POLARIS11:
 137                 fw_name = FIRMWARE_POLARIS11;
 138                 break;
 139         case CHIP_POLARIS12:
 140                 fw_name = FIRMWARE_POLARIS12;
 141                 break;
 142         case CHIP_VEGAM:
 143                 fw_name = FIRMWARE_VEGAM;
 144                 break;
 145         case CHIP_VEGA10:
 146                 fw_name = FIRMWARE_VEGA10;
 147                 break;
 148         case CHIP_VEGA12:
 149                 fw_name = FIRMWARE_VEGA12;
 150                 break;
 151         case CHIP_VEGA20:
 152                 fw_name = FIRMWARE_VEGA20;
 153                 break;
 154
 155         default:
 156                 return -EINVAL;
 157         }
 158
 159         r = request_firmware(&adev->vce.fw, fw_name, adev->dev);
 160         if (r) {
 161                 dev_err(adev->dev, "amdgpu_vce: Can't load firmware \"%s\"\n",
 162                         fw_name);
 163                 return r;
 164         }
 165
 166         r = amdgpu_ucode_validate(adev->vce.fw);
 167         if (r) {
 168                 dev_err(adev->dev, "amdgpu_vce: Can't validate firmware \"%s\"\n",
 169                         fw_name);
 170                 release_firmware(adev->vce.fw);
 171                 adev->vce.fw = NULL;
 172                 return r;
 173         }
 174
 175         hdr = (const struct common_firmware_header *)adev->vce.fw->data;
 176
 177         ucode_version = le32_to_cpu(hdr->ucode_version);
 178         version_major = (ucode_version >> 20) & 0xfff;
 179         version_minor = (ucode_version >> 8) & 0xfff;
 180         binary_id = ucode_version & 0xff;
 181         DRM_INFO("Found VCE firmware Version: %hhd.%hhd Binary ID: %hhd\n",
 182                 version_major, version_minor, binary_id);
 183         adev->vce.fw_version = ((version_major << 24) | (version_minor << 16) |
 184                                 (binary_id << 8));
 185
 186         r = amdgpu_bo_create_kernel(adev, size, PAGE_SIZE,
 187                                     AMDGPU_GEM_DOMAIN_VRAM, &adev->vce.vcpu_bo,
 188                                     &adev->vce.gpu_addr, &adev->vce.cpu_addr);
 189         if (r) {
 190                 dev_err(adev->dev, "(%d) failed to allocate VCE bo\n", r);
 191                 return r;
 192         }
 193
 194         for (i = 0; i < AMDGPU_MAX_VCE_HANDLES; ++i) {
 195                 atomic_set(&adev->vce.handles[i], 0);
 196                 adev->vce.filp[i] = NULL;
 197         }
 198
 199         INIT_DELAYED_WORK(&adev->vce.idle_work, amdgpu_vce_idle_work_handler);
 200         mutex_init(&adev->vce.idle_mutex);
 201
 202         return 0;
 203 }
 204
 205 /**
 206  * amdgpu_vce_fini - free memory
 207  *
 208  * @adev: amdgpu_device pointer
 209  *
 210  * Last step on VCE teardown, free firmware memory
 211  */
 212 int amdgpu_vce_sw_fini(struct amdgpu_device *adev)
 213 {
 214         unsigned i;
 215
 216         if (adev->vce.vcpu_bo == NULL)
 217                 return 0;
 218
 219         cancel_delayed_work_sync(&adev->vce.idle_work);
 220         drm_sched_entity_destroy(&adev->vce.entity);
 221
 222         amdgpu_bo_free_kernel(&adev->vce.vcpu_bo, &adev->vce.gpu_addr,
 223                 (void **)&adev->vce.cpu_addr);
 224
 225         for (i = 0; i < adev->vce.num_rings; i++)
 226                 amdgpu_ring_fini(&adev->vce.ring[i]);
 227
 228         release_firmware(adev->vce.fw);
 229         mutex_destroy(&adev->vce.idle_mutex);
 230
 231         return 0;
 232 }
 233
 234 /**
 235  * amdgpu_vce_entity_init - init entity
 236  *
 237  * @adev: amdgpu_device pointer
 238  *
 239  */
 240 int amdgpu_vce_entity_init(struct amdgpu_device *adev)
 241 {
 242         struct amdgpu_ring *ring;
 243         struct drm_gpu_scheduler *sched;
 244         int r;
 245
 246         ring = &adev->vce.ring[0];
 247         sched = &ring->sched;
 248         r = drm_sched_entity_init(&adev->vce.entity, DRM_SCHED_PRIORITY_NORMAL,
 249                                   &sched, 1, NULL);
 250         if (r != 0) {
 251                 DRM_ERROR("Failed setting up VCE run queue.\n");
 252                 return r;
 253         }
 254
 255         return 0;
 256 }
 257
 258 /**
 259  * amdgpu_vce_suspend - unpin VCE fw memory
 260  *
 261  * @adev: amdgpu_device pointer
 262  *
 263  */
 264 int amdgpu_vce_suspend(struct amdgpu_device *adev)
 265 {
 266         int i;
 267
 268         cancel_delayed_work_sync(&adev->vce.idle_work);
 269
 270         if (adev->vce.vcpu_bo == NULL)
 271                 return 0;
 272
 273         for (i = 0; i < AMDGPU_MAX_VCE_HANDLES; ++i)
 274                 if (atomic_read(&adev->vce.handles[i]))
 275                         break;
 276
 277         if (i == AMDGPU_MAX_VCE_HANDLES)
 278                 return 0;
 279
 280         /* TODO: suspending running encoding sessions isn't supported */
 281         return -EINVAL;
 282 }
 283
 284 /**
 285  * amdgpu_vce_resume - pin VCE fw memory
 286  *
 287  * @adev: amdgpu_device pointer
 288  *
 289  */
 290 int amdgpu_vce_resume(struct amdgpu_device *adev)
 291 {
 292         void *cpu_addr;
 293         const struct common_firmware_header *hdr;
 294         unsigned offset;
 295         int r;
 296
 297         if (adev->vce.vcpu_bo == NULL)
 298                 return -EINVAL;
 299
 300         r = amdgpu_bo_reserve(adev->vce.vcpu_bo, false);
 301         if (r) {
 302                 dev_err(adev->dev, "(%d) failed to reserve VCE bo\n", r);
 303                 return r;
 304         }
 305
 306         r = amdgpu_bo_kmap(adev->vce.vcpu_bo, &cpu_addr);
 307         if (r) {
 308                 amdgpu_bo_unreserve(adev->vce.vcpu_bo);
 309                 dev_err(adev->dev, "(%d) VCE map failed\n", r);
 310                 return r;
 311         }
 312
 313         hdr = (const struct common_firmware_header *)adev->vce.fw->data;
 314         offset = le32_to_cpu(hdr->ucode_array_offset_bytes);
 315         memcpy_toio(cpu_addr, adev->vce.fw->data + offset,
 316                     adev->vce.fw->size - offset);
 317
 318         amdgpu_bo_kunmap(adev->vce.vcpu_bo);
 319
 320         amdgpu_bo_unreserve(adev->vce.vcpu_bo);
 321
 322         return 0;
 323 }
 324
 325 /**
 326  * amdgpu_vce_idle_work_handler - power off VCE
 327  *
 328  * @work: pointer to work structure
 329  *
 330  * power of VCE when it's not used any more
 331  */
 332 static void amdgpu_vce_idle_work_handler(struct work_struct *work)
 333 {
 334         struct amdgpu_device *adev =
 335                 container_of(work, struct amdgpu_device, vce.idle_work.work);
 336         unsigned i, count = 0;
 337
 338         for (i = 0; i < adev->vce.num_rings; i++)
 339                 count += amdgpu_fence_count_emitted(&adev->vce.ring[i]);
 340
 341         if (count == 0) {
 342                 if (adev->pm.dpm_enabled) {
 343                         amdgpu_dpm_enable_vce(adev, false);
 344                 } else {
 345                         amdgpu_asic_set_vce_clocks(adev, 0, 0);
 346                         amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_VCE,
 347                                                                AMD_PG_STATE_GATE);
 348                         amdgpu_device_ip_set_clockgating_state(adev, AMD_IP_BLOCK_TYPE_VCE,
 349                                                                AMD_CG_STATE_GATE);
 350                 }
 351         } else {
 352                 schedule_delayed_work(&adev->vce.idle_work, VCE_IDLE_TIMEOUT);
 353         }
 354 }
 355
 356 /**
 357  * amdgpu_vce_ring_begin_use - power up VCE
 358  *
 359  * @ring: amdgpu ring
 360  *
 361  * Make sure VCE is powerd up when we want to use it
 362  */
 363 void amdgpu_vce_ring_begin_use(struct amdgpu_ring *ring)
 364 {
 365         struct amdgpu_device *adev = ring->adev;
 366         bool set_clocks;
 367
 368         if (amdgpu_sriov_vf(adev))
 369                 return;
 370
 371         mutex_lock(&adev->vce.idle_mutex);
 372         set_clocks = !cancel_delayed_work_sync(&adev->vce.idle_work);
 373         if (set_clocks) {
 374                 if (adev->pm.dpm_enabled) {
 375                         amdgpu_dpm_enable_vce(adev, true);
 376                 } else {
 377                         amdgpu_asic_set_vce_clocks(adev, 53300, 40000);
 378                         amdgpu_device_ip_set_clockgating_state(adev, AMD_IP_BLOCK_TYPE_VCE,
 379                                                                AMD_CG_STATE_UNGATE);
 380                         amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_VCE,
 381                                                                AMD_PG_STATE_UNGATE);
 382
 383                 }
 384         }
 385         mutex_unlock(&adev->vce.idle_mutex);
 386 }
 387
 388 /**
 389  * amdgpu_vce_ring_end_use - power VCE down
 390  *
 391  * @ring: amdgpu ring
 392  *
 393  * Schedule work to power VCE down again
 394  */
 395 void amdgpu_vce_ring_end_use(struct amdgpu_ring *ring)
 396 {
 397         if (!amdgpu_sriov_vf(ring->adev))
 398                 schedule_delayed_work(&ring->adev->vce.idle_work, VCE_IDLE_TIMEOUT);
 399 }
 400
 401 /**
 402  * amdgpu_vce_free_handles - free still open VCE handles
 403  *
 404  * @adev: amdgpu_device pointer
 405  * @filp: drm file pointer
 406  *
 407  * Close all VCE handles still open by this file pointer
 408  */
 409 void amdgpu_vce_free_handles(struct amdgpu_device *adev, struct drm_file *filp)
 410 {
 411         struct amdgpu_ring *ring = &adev->vce.ring[0];
 412         int i, r;
 413         for (i = 0; i < AMDGPU_MAX_VCE_HANDLES; ++i) {
 414                 uint32_t handle = atomic_read(&adev->vce.handles[i]);
 415
 416                 if (!handle || adev->vce.filp[i] != filp)
 417                         continue;
 418
 419                 r = amdgpu_vce_get_destroy_msg(ring, handle, false, NULL);
 420                 if (r)
 421                         DRM_ERROR("Error destroying VCE handle (%d)!\n", r);
 422
 423                 adev->vce.filp[i] = NULL;
 424                 atomic_set(&adev->vce.handles[i], 0);
 425         }
 426 }
 427
 428 /**
 429  * amdgpu_vce_get_create_msg - generate a VCE create msg
 430  *
 431  * @adev: amdgpu_device pointer
 432  * @ring: ring we should submit the msg to
 433  * @handle: VCE session handle to use
 434  * @fence: optional fence to return
 435  *
 436  * Open up a stream for HW test
 437  */
 438 static int amdgpu_vce_get_create_msg(struct amdgpu_ring *ring, uint32_t handle,
 439                                      struct amdgpu_bo *bo,
 440                                      struct dma_fence **fence)
 441 {
 442         const unsigned ib_size_dw = 1024;
 443         struct amdgpu_job *job;
 444         struct amdgpu_ib *ib;
 445         struct dma_fence *f = NULL;
 446         uint64_t addr;
 447         int i, r;
 448
 449         r = amdgpu_job_alloc_with_ib(ring->adev, ib_size_dw * 4,
 450                                         AMDGPU_IB_POOL_DIRECT, &job);
 451         if (r)
 452                 return r;
 453
 454         ib = &job->ibs[0];
 455
 456         addr = amdgpu_bo_gpu_offset(bo);
 457
 458         /* stitch together an VCE create msg */
 459         ib->length_dw = 0;
 460         ib->ptr[ib->length_dw++] = 0x0000000c; /* len */
 461         ib->ptr[ib->length_dw++] = 0x00000001; /* session cmd */
 462         ib->ptr[ib->length_dw++] = handle;
 463
 464         if ((ring->adev->vce.fw_version >> 24) >= 52)
 465                 ib->ptr[ib->length_dw++] = 0x00000040; /* len */
 466         else
 467                 ib->ptr[ib->length_dw++] = 0x00000030; /* len */
 468         ib->ptr[ib->length_dw++] = 0x01000001; /* create cmd */
 469         ib->ptr[ib->length_dw++] = 0x00000000;
 470         ib->ptr[ib->length_dw++] = 0x00000042;
 471         ib->ptr[ib->length_dw++] = 0x0000000a;
 472         ib->ptr[ib->length_dw++] = 0x00000001;
 473         ib->ptr[ib->length_dw++] = 0x00000080;
 474         ib->ptr[ib->length_dw++] = 0x00000060;
 475         ib->ptr[ib->length_dw++] = 0x00000100;
 476         ib->ptr[ib->length_dw++] = 0x00000100;
 477         ib->ptr[ib->length_dw++] = 0x0000000c;
 478         ib->ptr[ib->length_dw++] = 0x00000000;
 479         if ((ring->adev->vce.fw_version >> 24) >= 52) {
 480                 ib->ptr[ib->length_dw++] = 0x00000000;
 481                 ib->ptr[ib->length_dw++] = 0x00000000;
 482                 ib->ptr[ib->length_dw++] = 0x00000000;
 483                 ib->ptr[ib->length_dw++] = 0x00000000;
 484         }
 485
 486         ib->ptr[ib->length_dw++] = 0x00000014; /* len */
 487         ib->ptr[ib->length_dw++] = 0x05000005; /* feedback buffer */
 488         ib->ptr[ib->length_dw++] = upper_32_bits(addr);
 489         ib->ptr[ib->length_dw++] = addr;
 490         ib->ptr[ib->length_dw++] = 0x00000001;
 491
 492         for (i = ib->length_dw; i < ib_size_dw; ++i)
 493                 ib->ptr[i] = 0x0;
 494
 495         r = amdgpu_job_submit_direct(job, ring, &f);
 496         if (r)
 497                 goto err;
 498
 499         if (fence)
 500                 *fence = dma_fence_get(f);
 501         dma_fence_put(f);
 502         return 0;
 503
 504 err:
 505         amdgpu_job_free(job);
 506         return r;
 507 }
 508
 509 /**
 510  * amdgpu_vce_get_destroy_msg - generate a VCE destroy msg
 511  *
 512  * @adev: amdgpu_device pointer
 513  * @ring: ring we should submit the msg to
 514  * @handle: VCE session handle to use
 515  * @fence: optional fence to return
 516  *
 517  * Close up a stream for HW test or if userspace failed to do so
 518  */
 519 static int amdgpu_vce_get_destroy_msg(struct amdgpu_ring *ring, uint32_t handle,
 520                                       bool direct, struct dma_fence **fence)
 521 {
 522         const unsigned ib_size_dw = 1024;
 523         struct amdgpu_job *job;
 524         struct amdgpu_ib *ib;
 525         struct dma_fence *f = NULL;
 526         int i, r;
 527
 528         r = amdgpu_job_alloc_with_ib(ring->adev, ib_size_dw * 4,
 529                         direct ? AMDGPU_IB_POOL_DIRECT : AMDGPU_IB_POOL_NORMAL, &job);
 530         if (r)
 531                 return r;
 532
 533         ib = &job->ibs[0];
 534
 535         /* stitch together an VCE destroy msg */
 536         ib->length_dw = 0;
 537         ib->ptr[ib->length_dw++] = 0x0000000c; /* len */
 538         ib->ptr[ib->length_dw++] = 0x00000001; /* session cmd */
 539         ib->ptr[ib->length_dw++] = handle;
 540
 541         ib->ptr[ib->length_dw++] = 0x00000020; /* len */
 542         ib->ptr[ib->length_dw++] = 0x00000002; /* task info */
 543         ib->ptr[ib->length_dw++] = 0xffffffff; /* next task info, set to 0xffffffff if no */
 544         ib->ptr[ib->length_dw++] = 0x00000001; /* destroy session */
 545         ib->ptr[ib->length_dw++] = 0x00000000;
 546         ib->ptr[ib->length_dw++] = 0x00000000;
 547         ib->ptr[ib->length_dw++] = 0xffffffff; /* feedback is not needed, set to 0xffffffff and firmware will not output feedback */
 548         ib->ptr[ib->length_dw++] = 0x00000000;
 549
 550         ib->ptr[ib->length_dw++] = 0x00000008; /* len */
 551         ib->ptr[ib->length_dw++] = 0x02000001; /* destroy cmd */
 552
 553         for (i = ib->length_dw; i < ib_size_dw; ++i)
 554                 ib->ptr[i] = 0x0;
 555
 556         if (direct)
 557                 r = amdgpu_job_submit_direct(job, ring, &f);
 558         else
 559                 r = amdgpu_job_submit(job, &ring->adev->vce.entity,
 560                                       AMDGPU_FENCE_OWNER_UNDEFINED, &f);
 561         if (r)
 562                 goto err;
 563
 564         if (fence)
 565                 *fence = dma_fence_get(f);
 566         dma_fence_put(f);
 567         return 0;
 568
 569 err:
 570         amdgpu_job_free(job);
 571         return r;
 572 }
 573
 574 /**
 575  * amdgpu_vce_cs_validate_bo - make sure not to cross 4GB boundary
 576  *
 577  * @p: parser context
 578  * @lo: address of lower dword
 579  * @hi: address of higher dword
 580  * @size: minimum size
 581  * @index: bs/fb index
 582  *
 583  * Make sure that no BO cross a 4GB boundary.
 584  */
 585 static int amdgpu_vce_validate_bo(struct amdgpu_cs_parser *p, uint32_t ib_idx,
 586                                   int lo, int hi, unsigned size, int32_t index)
 587 {
 588         int64_t offset = ((uint64_t)size) * ((int64_t)index);
 589         struct ttm_operation_ctx ctx = { false, false };
 590         struct amdgpu_bo_va_mapping *mapping;
 591         unsigned i, fpfn, lpfn;
 592         struct amdgpu_bo *bo;
 593         uint64_t addr;
 594         int r;
 595
 596         addr = ((uint64_t)amdgpu_get_ib_value(p, ib_idx, lo)) |
 597                ((uint64_t)amdgpu_get_ib_value(p, ib_idx, hi)) << 32;
 598         if (index >= 0) {
 599                 addr += offset;
 600                 fpfn = PAGE_ALIGN(offset) >> PAGE_SHIFT;
 601                 lpfn = 0x100000000ULL >> PAGE_SHIFT;
 602         } else {
 603                 fpfn = 0;
 604                 lpfn = (0x100000000ULL - PAGE_ALIGN(offset)) >> PAGE_SHIFT;
 605         }
 606
 607         r = amdgpu_cs_find_mapping(p, addr, &bo, &mapping);
 608         if (r) {
 609                 DRM_ERROR("Can't find BO for addr 0x%010Lx %d %d %d %d\n",
 610                           addr, lo, hi, size, index);
 611                 return r;
 612         }
 613
 614         for (i = 0; i < bo->placement.num_placement; ++i) {
 615                 bo->placements[i].fpfn = max(bo->placements[i].fpfn, fpfn);
 616                 bo->placements[i].lpfn = bo->placements[i].lpfn ?
 617                         min(bo->placements[i].lpfn, lpfn) : lpfn;
 618         }
 619         return ttm_bo_validate(&bo->tbo, &bo->placement, &ctx);
 620 }
 621
 622
 623 /**
 624  * amdgpu_vce_cs_reloc - command submission relocation
 625  *
 626  * @p: parser context
 627  * @lo: address of lower dword
 628  * @hi: address of higher dword
 629  * @size: minimum size
 630  *
 631  * Patch relocation inside command stream with real buffer address
 632  */
 633 static int amdgpu_vce_cs_reloc(struct amdgpu_cs_parser *p, uint32_t ib_idx,
 634                                int lo, int hi, unsigned size, uint32_t index)
 635 {
 636         struct amdgpu_bo_va_mapping *mapping;
 637         struct amdgpu_bo *bo;
 638         uint64_t addr;
 639         int r;
 640
 641         if (index == 0xffffffff)
 642                 index = 0;
 643
 644         addr = ((uint64_t)amdgpu_get_ib_value(p, ib_idx, lo)) |
 645                ((uint64_t)amdgpu_get_ib_value(p, ib_idx, hi)) << 32;
 646         addr += ((uint64_t)size) * ((uint64_t)index);
 647
 648         r = amdgpu_cs_find_mapping(p, addr, &bo, &mapping);
 649         if (r) {
 650                 DRM_ERROR("Can't find BO for addr 0x%010Lx %d %d %d %d\n",
 651                           addr, lo, hi, size, index);
 652                 return r;
 653         }
 654
 655         if ((addr + (uint64_t)size) >
 656             (mapping->last + 1) * AMDGPU_GPU_PAGE_SIZE) {
 657                 DRM_ERROR("BO too small for addr 0x%010Lx %d %d\n",
 658                           addr, lo, hi);
 659                 return -EINVAL;
 660         }
 661
 662         addr -= mapping->start * AMDGPU_GPU_PAGE_SIZE;
 663         addr += amdgpu_bo_gpu_offset(bo);
 664         addr -= ((uint64_t)size) * ((uint64_t)index);
 665
 666         amdgpu_set_ib_value(p, ib_idx, lo, lower_32_bits(addr));
 667         amdgpu_set_ib_value(p, ib_idx, hi, upper_32_bits(addr));
 668
 669         return 0;
 670 }
 671
 672 /**
 673  * amdgpu_vce_validate_handle - validate stream handle
 674  *
 675  * @p: parser context
 676  * @handle: handle to validate
 677  * @allocated: allocated a new handle?
 678  *
 679  * Validates the handle and return the found session index or -EINVAL
 680  * we we don't have another free session index.
 681  */
 682 static int amdgpu_vce_validate_handle(struct amdgpu_cs_parser *p,
 683                                       uint32_t handle, uint32_t *allocated)
 684 {
 685         unsigned i;
 686
 687         /* validate the handle */
 688         for (i = 0; i < AMDGPU_MAX_VCE_HANDLES; ++i) {
 689                 if (atomic_read(&p->adev->vce.handles[i]) == handle) {
 690                         if (p->adev->vce.filp[i] != p->filp) {
 691                                 DRM_ERROR("VCE handle collision detected!\n");
 692                                 return -EINVAL;
 693                         }
 694                         return i;
 695                 }
 696         }
 697
 698         /* handle not found try to alloc a new one */
 699         for (i = 0; i < AMDGPU_MAX_VCE_HANDLES; ++i) {
 700                 if (!atomic_cmpxchg(&p->adev->vce.handles[i], 0, handle)) {
 701                         p->adev->vce.filp[i] = p->filp;
 702                         p->adev->vce.img_size[i] = 0;
 703                         *allocated |= 1 << i;
 704                         return i;
 705                 }
 706         }
 707
 708         DRM_ERROR("No more free VCE handles!\n");
 709         return -EINVAL;
 710 }
 711
 712 /**
 713  * amdgpu_vce_cs_parse - parse and validate the command stream
 714  *
 715  * @p: parser context
 716  *
 717  */
 718 int amdgpu_vce_ring_parse_cs(struct amdgpu_cs_parser *p, uint32_t ib_idx)
 719 {
 720         struct amdgpu_ib *ib = &p->job->ibs[ib_idx];
 721         unsigned fb_idx = 0, bs_idx = 0;
 722         int session_idx = -1;
 723         uint32_t destroyed = 0;
 724         uint32_t created = 0;
 725         uint32_t allocated = 0;
 726         uint32_t tmp, handle = 0;
 727         uint32_t *size = &tmp;
 728         unsigned idx;
 729         int i, r = 0;
 730
 731         p->job->vm = NULL;
 732         ib->gpu_addr = amdgpu_sa_bo_gpu_addr(ib->sa_bo);
 733
 734         for (idx = 0; idx < ib->length_dw;) {
 735                 uint32_t len = amdgpu_get_ib_value(p, ib_idx, idx);
 736                 uint32_t cmd = amdgpu_get_ib_value(p, ib_idx, idx + 1);
 737
 738                 if ((len < 8) || (len & 3)) {
 739                         DRM_ERROR("invalid VCE command length (%d)!\n", len);
 740                         r = -EINVAL;
 741                         goto out;
 742                 }
 743
 744                 switch (cmd) {
 745                 case 0x00000002: /* task info */
 746                         fb_idx = amdgpu_get_ib_value(p, ib_idx, idx + 6);
 747                         bs_idx = amdgpu_get_ib_value(p, ib_idx, idx + 7);
 748                         break;
 749
 750                 case 0x03000001: /* encode */
 751                         r = amdgpu_vce_validate_bo(p, ib_idx, idx + 10,
 752                                                    idx + 9, 0, 0);
 753                         if (r)
 754                                 goto out;
 755
 756                         r = amdgpu_vce_validate_bo(p, ib_idx, idx + 12,
 757                                                    idx + 11, 0, 0);
 758                         if (r)
 759                                 goto out;
 760                         break;
 761
 762                 case 0x05000001: /* context buffer */
 763                         r = amdgpu_vce_validate_bo(p, ib_idx, idx + 3,
 764                                                    idx + 2, 0, 0);
 765                         if (r)
 766                                 goto out;
 767                         break;
 768
 769                 case 0x05000004: /* video bitstream buffer */
 770                         tmp = amdgpu_get_ib_value(p, ib_idx, idx + 4);
 771                         r = amdgpu_vce_validate_bo(p, ib_idx, idx + 3, idx + 2,
 772                                                    tmp, bs_idx);
 773                         if (r)
 774                                 goto out;
 775                         break;
 776
 777                 case 0x05000005: /* feedback buffer */
 778                         r = amdgpu_vce_validate_bo(p, ib_idx, idx + 3, idx + 2,
 779                                                    4096, fb_idx);
 780                         if (r)
 781                                 goto out;
 782                         break;
 783
 784                 case 0x0500000d: /* MV buffer */
 785                         r = amdgpu_vce_validate_bo(p, ib_idx, idx + 3,
 786                                                         idx + 2, 0, 0);
 787                         if (r)
 788                                 goto out;
 789
 790                         r = amdgpu_vce_validate_bo(p, ib_idx, idx + 8,
 791                                                         idx + 7, 0, 0);
 792                         if (r)
 793                                 goto out;
 794                         break;
 795                 }
 796
 797                 idx += len / 4;
 798         }
 799
 800         for (idx = 0; idx < ib->length_dw;) {
 801                 uint32_t len = amdgpu_get_ib_value(p, ib_idx, idx);
 802                 uint32_t cmd = amdgpu_get_ib_value(p, ib_idx, idx + 1);
 803
 804                 switch (cmd) {
 805                 case 0x00000001: /* session */
 806                         handle = amdgpu_get_ib_value(p, ib_idx, idx + 2);
 807                         session_idx = amdgpu_vce_validate_handle(p, handle,
 808                                                                  &allocated);
 809                         if (session_idx < 0) {
 810                                 r = session_idx;
 811                                 goto out;
 812                         }
 813                         size = &p->adev->vce.img_size[session_idx];
 814                         break;
 815
 816                 case 0x00000002: /* task info */
 817                         fb_idx = amdgpu_get_ib_value(p, ib_idx, idx + 6);
 818                         bs_idx = amdgpu_get_ib_value(p, ib_idx, idx + 7);
 819                         break;
 820
 821                 case 0x01000001: /* create */
 822                         created |= 1 << session_idx;
 823                         if (destroyed & (1 << session_idx)) {
 824                                 destroyed &= ~(1 << session_idx);
 825                                 allocated |= 1 << session_idx;
 826
 827                         } else if (!(allocated & (1 << session_idx))) {
 828                                 DRM_ERROR("Handle already in use!\n");
 829                                 r = -EINVAL;
 830                                 goto out;
 831                         }
 832
 833                         *size = amdgpu_get_ib_value(p, ib_idx, idx + 8) *
 834                                 amdgpu_get_ib_value(p, ib_idx, idx + 10) *
 835                                 8 * 3 / 2;
 836                         break;
 837
 838                 case 0x04000001: /* config extension */
 839                 case 0x04000002: /* pic control */
 840                 case 0x04000005: /* rate control */
 841                 case 0x04000007: /* motion estimation */
 842                 case 0x04000008: /* rdo */
 843                 case 0x04000009: /* vui */
 844                 case 0x05000002: /* auxiliary buffer */
 845                 case 0x05000009: /* clock table */
 846                         break;
 847
 848                 case 0x0500000c: /* hw config */
 849                         switch (p->adev->asic_type) {
 850 #ifdef CONFIG_DRM_AMDGPU_CIK
 851                         case CHIP_KAVERI:
 852                         case CHIP_MULLINS:
 853 #endif
 854                         case CHIP_CARRIZO:
 855                                 break;
 856                         default:
 857                                 r = -EINVAL;
 858                                 goto out;
 859                         }
 860                         break;
 861
 862                 case 0x03000001: /* encode */
 863                         r = amdgpu_vce_cs_reloc(p, ib_idx, idx + 10, idx + 9,
 864                                                 *size, 0);
 865                         if (r)
 866                                 goto out;
 867
 868                         r = amdgpu_vce_cs_reloc(p, ib_idx, idx + 12, idx + 11,
 869                                                 *size / 3, 0);
 870                         if (r)
 871                                 goto out;
 872                         break;
 873
 874                 case 0x02000001: /* destroy */
 875                         destroyed |= 1 << session_idx;
 876                         break;
 877
 878                 case 0x05000001: /* context buffer */
 879                         r = amdgpu_vce_cs_reloc(p, ib_idx, idx + 3, idx + 2,
 880                                                 *size * 2, 0);
 881                         if (r)
 882                                 goto out;
 883                         break;
 884
 885                 case 0x05000004: /* video bitstream buffer */
 886                         tmp = amdgpu_get_ib_value(p, ib_idx, idx + 4);
 887                         r = amdgpu_vce_cs_reloc(p, ib_idx, idx + 3, idx + 2,
 888                                                 tmp, bs_idx);
 889                         if (r)
 890                                 goto out;
 891                         break;
 892
 893                 case 0x05000005: /* feedback buffer */
 894                         r = amdgpu_vce_cs_reloc(p, ib_idx, idx + 3, idx + 2,
 895                                                 4096, fb_idx);
 896                         if (r)
 897                                 goto out;
 898                         break;
 899
 900                 case 0x0500000d: /* MV buffer */
 901                         r = amdgpu_vce_cs_reloc(p, ib_idx, idx + 3,
 902                                                         idx + 2, *size, 0);
 903                         if (r)
 904                                 goto out;
 905
 906                         r = amdgpu_vce_cs_reloc(p, ib_idx, idx + 8,
 907                                                         idx + 7, *size / 12, 0);
 908                         if (r)
 909                                 goto out;
 910                         break;
 911
 912                 default:
 913                         DRM_ERROR("invalid VCE command (0x%x)!\n", cmd);
 914                         r = -EINVAL;
 915                         goto out;
 916                 }
 917
 918                 if (session_idx == -1) {
 919                         DRM_ERROR("no session command at start of IB\n");
 920                         r = -EINVAL;
 921                         goto out;
 922                 }
 923
 924                 idx += len / 4;
 925         }
 926
 927         if (allocated & ~created) {
 928                 DRM_ERROR("New session without create command!\n");
 929                 r = -ENOENT;
 930         }
 931
 932 out:
 933         if (!r) {
 934                 /* No error, free all destroyed handle slots */
 935                 tmp = destroyed;
 936         } else {
 937                 /* Error during parsing, free all allocated handle slots */
 938                 tmp = allocated;
 939         }
 940
 941         for (i = 0; i < AMDGPU_MAX_VCE_HANDLES; ++i)
 942                 if (tmp & (1 << i))
 943                         atomic_set(&p->adev->vce.handles[i], 0);
 944
 945         return r;
 946 }
 947
 948 /**
 949  * amdgpu_vce_cs_parse_vm - parse the command stream in VM mode
 950  *
 951  * @p: parser context
 952  *
 953  */
 954 int amdgpu_vce_ring_parse_cs_vm(struct amdgpu_cs_parser *p, uint32_t ib_idx)
 955 {
 956         struct amdgpu_ib *ib = &p->job->ibs[ib_idx];
 957         int session_idx = -1;
 958         uint32_t destroyed = 0;
 959         uint32_t created = 0;
 960         uint32_t allocated = 0;
 961         uint32_t tmp, handle = 0;
 962         int i, r = 0, idx = 0;
 963
 964         while (idx < ib->length_dw) {
 965                 uint32_t len = amdgpu_get_ib_value(p, ib_idx, idx);
 966                 uint32_t cmd = amdgpu_get_ib_value(p, ib_idx, idx + 1);
 967
 968                 if ((len < 8) || (len & 3)) {
 969                         DRM_ERROR("invalid VCE command length (%d)!\n", len);
 970                         r = -EINVAL;
 971                         goto out;
 972                 }
 973
 974                 switch (cmd) {
 975                 case 0x00000001: /* session */
 976                         handle = amdgpu_get_ib_value(p, ib_idx, idx + 2);
 977                         session_idx = amdgpu_vce_validate_handle(p, handle,
 978                                                                  &allocated);
 979                         if (session_idx < 0) {
 980                                 r = session_idx;
 981                                 goto out;
 982                         }
 983                         break;
 984
 985                 case 0x01000001: /* create */
 986                         created |= 1 << session_idx;
 987                         if (destroyed & (1 << session_idx)) {
 988                                 destroyed &= ~(1 << session_idx);
 989                                 allocated |= 1 << session_idx;
 990
 991                         } else if (!(allocated & (1 << session_idx))) {
 992                                 DRM_ERROR("Handle already in use!\n");
 993                                 r = -EINVAL;
 994                                 goto out;
 995                         }
 996
 997                         break;
 998
 999                 case 0x02000001: /* destroy */
1000                         destroyed |= 1 << session_idx;
1001                         break;
1002
1003                 default:
1004                         break;
1005                 }
1006
1007                 if (session_idx == -1) {
1008                         DRM_ERROR("no session command at start of IB\n");
1009                         r = -EINVAL;
1010                         goto out;
1011                 }
1012
1013                 idx += len / 4;
1014         }
1015
1016         if (allocated & ~created) {
1017                 DRM_ERROR("New session without create command!\n");
1018                 r = -ENOENT;
1019         }
1020
1021 out:
1022         if (!r) {
1023                 /* No error, free all destroyed handle slots */
1024                 tmp = destroyed;
1025                 amdgpu_ib_free(p->adev, ib, NULL);
1026         } else {
1027                 /* Error during parsing, free all allocated handle slots */
1028                 tmp = allocated;
1029         }
1030
1031         for (i = 0; i < AMDGPU_MAX_VCE_HANDLES; ++i)
1032                 if (tmp & (1 << i))
1033                         atomic_set(&p->adev->vce.handles[i], 0);
1034
1035         return r;
1036 }
1037
1038 /**
1039  * amdgpu_vce_ring_emit_ib - execute indirect buffer
1040  *
1041  * @ring: engine to use
1042  * @ib: the IB to execute
1043  *
1044  */
1045 void amdgpu_vce_ring_emit_ib(struct amdgpu_ring *ring,
1046                                 struct amdgpu_job *job,
1047                                 struct amdgpu_ib *ib,
1048                                 uint32_t flags)
1049 {
1050         amdgpu_ring_write(ring, VCE_CMD_IB);
1051         amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr));
1052         amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
1053         amdgpu_ring_write(ring, ib->length_dw);
1054 }
1055
1056 /**
1057  * amdgpu_vce_ring_emit_fence - add a fence command to the ring
1058  *
1059  * @ring: engine to use
1060  * @fence: the fence
1061  *
1062  */
1063 void amdgpu_vce_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq,
1064                                 unsigned flags)
1065 {
1066         WARN_ON(flags & AMDGPU_FENCE_FLAG_64BIT);
1067
1068         amdgpu_ring_write(ring, VCE_CMD_FENCE);
1069         amdgpu_ring_write(ring, addr);
1070         amdgpu_ring_write(ring, upper_32_bits(addr));
1071         amdgpu_ring_write(ring, seq);
1072         amdgpu_ring_write(ring, VCE_CMD_TRAP);
1073         amdgpu_ring_write(ring, VCE_CMD_END);
1074 }
1075
1076 /**
1077  * amdgpu_vce_ring_test_ring - test if VCE ring is working
1078  *
1079  * @ring: the engine to test on
1080  *
1081  */
1082 int amdgpu_vce_ring_test_ring(struct amdgpu_ring *ring)
1083 {
1084         struct amdgpu_device *adev = ring->adev;
1085         uint32_t rptr;
1086         unsigned i;
1087         int r, timeout = adev->usec_timeout;
1088
1089         /* skip ring test for sriov*/
1090         if (amdgpu_sriov_vf(adev))
1091                 return 0;
1092
1093         r = amdgpu_ring_alloc(ring, 16);
1094         if (r)
1095                 return r;
1096
1097         rptr = amdgpu_ring_get_rptr(ring);
1098
1099         amdgpu_ring_write(ring, VCE_CMD_END);
1100         amdgpu_ring_commit(ring);
1101
1102         for (i = 0; i < timeout; i++) {
1103                 if (amdgpu_ring_get_rptr(ring) != rptr)
1104                         break;
1105                 udelay(1);
1106         }
1107
1108         if (i >= timeout)
1109                 r = -ETIMEDOUT;
1110
1111         return r;
1112 }
1113
1114 /**
1115  * amdgpu_vce_ring_test_ib - test if VCE IBs are working
1116  *
1117  * @ring: the engine to test on
1118  *
1119  */
1120 int amdgpu_vce_ring_test_ib(struct amdgpu_ring *ring, long timeout)
1121 {
1122         struct dma_fence *fence = NULL;
1123         struct amdgpu_bo *bo = NULL;
1124         long r;
1125
1126         /* skip vce ring1/2 ib test for now, since it's not reliable */
1127         if (ring != &ring->adev->vce.ring[0])
1128                 return 0;
1129
1130         r = amdgpu_bo_create_reserved(ring->adev, 512, PAGE_SIZE,
1131                                       AMDGPU_GEM_DOMAIN_VRAM,
1132                                       &bo, NULL, NULL);
1133         if (r)
1134                 return r;
1135
1136         r = amdgpu_vce_get_create_msg(ring, 1, bo, NULL);
1137         if (r)
1138                 goto error;
1139
1140         r = amdgpu_vce_get_destroy_msg(ring, 1, true, &fence);
1141         if (r)
1142                 goto error;
1143
1144         r = dma_fence_wait_timeout(fence, false, timeout);
1145         if (r == 0)
1146                 r = -ETIMEDOUT;
1147         else if (r > 0)
1148                 r = 0;
1149
1150 error:
1151         dma_fence_put(fence);
1152         amdgpu_bo_unreserve(bo);
1153         amdgpu_bo_unref(&bo);
1154         return r;
1155 }