drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c

   1 /*
   2  * Copyright 2009 Jerome Glisse.
   3  * All Rights Reserved.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the
   7  * "Software"), to deal in the Software without restriction, including
   8  * without limitation the rights to use, copy, modify, merge, publish,
   9  * distribute, sub license, and/or sell copies of the Software, and to
  10  * permit persons to whom the Software is furnished to do so, subject to
  11  * the following conditions:
  12  *
  13  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  14  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  15  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  16  * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
  17  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  18  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  19  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  20  *
  21  * The above copyright notice and this permission notice (including the
  22  * next paragraph) shall be included in all copies or substantial portions
  23  * of the Software.
  24  *
  25  */
  26 /*
  27  * Authors:
  28  *    Jerome Glisse <glisse@freedesktop.org>
  29  *    Thomas Hellstrom <thomas-at-tungstengraphics-dot-com>
  30  *    Dave Airlie
  31  */
  32
  33 #include <linux/dma-mapping.h>
  34 #include <linux/iommu.h>
  35 #include <linux/hmm.h>
  36 #include <linux/pagemap.h>
  37 #include <linux/sched/task.h>
  38 #include <linux/sched/mm.h>
  39 #include <linux/seq_file.h>
  40 #include <linux/slab.h>
  41 #include <linux/swap.h>
  42 #include <linux/swiotlb.h>
  43 #include <linux/dma-buf.h>
  44 #include <linux/sizes.h>
  45
  46 #include <drm/ttm/ttm_bo_api.h>
  47 #include <drm/ttm/ttm_bo_driver.h>
  48 #include <drm/ttm/ttm_placement.h>
  49
  50 #include <drm/amdgpu_drm.h>
  51
  52 #include "amdgpu.h"
  53 #include "amdgpu_object.h"
  54 #include "amdgpu_trace.h"
  55 #include "amdgpu_amdkfd.h"
  56 #include "amdgpu_sdma.h"
  57 #include "amdgpu_ras.h"
  58 #include "amdgpu_atomfirmware.h"
  59 #include "amdgpu_res_cursor.h"
  60 #include "bif/bif_4_1_d.h"
  61
  62 #define AMDGPU_TTM_VRAM_MAX_DW_READ     (size_t)128
  63
  64 static int amdgpu_ttm_backend_bind(struct ttm_device *bdev,
  65                                    struct ttm_tt *ttm,
  66                                    struct ttm_resource *bo_mem);
  67 static void amdgpu_ttm_backend_unbind(struct ttm_device *bdev,
  68                                       struct ttm_tt *ttm);
  69
  70 static int amdgpu_ttm_init_on_chip(struct amdgpu_device *adev,
  71                                     unsigned int type,
  72                                     uint64_t size_in_page)
  73 {
  74         return ttm_range_man_init(&adev->mman.bdev, type,
  75                                   false, size_in_page);
  76 }
  77
  78 /**
  79  * amdgpu_evict_flags - Compute placement flags
  80  *
  81  * @bo: The buffer object to evict
  82  * @placement: Possible destination(s) for evicted BO
  83  *
  84  * Fill in placement data when ttm_bo_evict() is called
  85  */
  86 static void amdgpu_evict_flags(struct ttm_buffer_object *bo,
  87                                 struct ttm_placement *placement)
  88 {
  89         struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev);
  90         struct amdgpu_bo *abo;
  91         static const struct ttm_place placements = {
  92                 .fpfn = 0,
  93                 .lpfn = 0,
  94                 .mem_type = TTM_PL_SYSTEM,
  95                 .flags = 0
  96         };
  97
  98         /* Don't handle scatter gather BOs */
  99         if (bo->type == ttm_bo_type_sg) {
 100                 placement->num_placement = 0;
 101                 placement->num_busy_placement = 0;
 102                 return;
 103         }
 104
 105         /* Object isn't an AMDGPU object so ignore */
 106         if (!amdgpu_bo_is_amdgpu_bo(bo)) {
 107                 placement->placement = &placements;
 108                 placement->busy_placement = &placements;
 109                 placement->num_placement = 1;
 110                 placement->num_busy_placement = 1;
 111                 return;
 112         }
 113
 114         abo = ttm_to_amdgpu_bo(bo);
 115         switch (bo->mem.mem_type) {
 116         case AMDGPU_PL_GDS:
 117         case AMDGPU_PL_GWS:
 118         case AMDGPU_PL_OA:
 119                 placement->num_placement = 0;
 120                 placement->num_busy_placement = 0;
 121                 return;
 122
 123         case TTM_PL_VRAM:
 124                 if (!adev->mman.buffer_funcs_enabled) {
 125                         /* Move to system memory */
 126                         amdgpu_bo_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_CPU);
 127                 } else if (!amdgpu_gmc_vram_full_visible(&adev->gmc) &&
 128                            !(abo->flags & AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED) &&
 129                            amdgpu_bo_in_cpu_visible_vram(abo)) {
 130
 131                         /* Try evicting to the CPU inaccessible part of VRAM
 132                          * first, but only set GTT as busy placement, so this
 133                          * BO will be evicted to GTT rather than causing other
 134                          * BOs to be evicted from VRAM
 135                          */
 136                         amdgpu_bo_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_VRAM |
 137                                                          AMDGPU_GEM_DOMAIN_GTT);
 138                         abo->placements[0].fpfn = adev->gmc.visible_vram_size >> PAGE_SHIFT;
 139                         abo->placements[0].lpfn = 0;
 140                         abo->placement.busy_placement = &abo->placements[1];
 141                         abo->placement.num_busy_placement = 1;
 142                 } else {
 143                         /* Move to GTT memory */
 144                         amdgpu_bo_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_GTT);
 145                 }
 146                 break;
 147         case TTM_PL_TT:
 148         default:
 149                 amdgpu_bo_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_CPU);
 150                 break;
 151         }
 152         *placement = abo->placement;
 153 }
 154
 155 /**
 156  * amdgpu_verify_access - Verify access for a mmap call
 157  *
 158  * @bo: The buffer object to map
 159  * @filp: The file pointer from the process performing the mmap
 160  *
 161  * This is called by ttm_bo_mmap() to verify whether a process
 162  * has the right to mmap a BO to their process space.
 163  */
 164 static int amdgpu_verify_access(struct ttm_buffer_object *bo, struct file *filp)
 165 {
 166         struct amdgpu_bo *abo = ttm_to_amdgpu_bo(bo);
 167
 168         /*
 169          * Don't verify access for KFD BOs. They don't have a GEM
 170          * object associated with them.
 171          */
 172         if (abo->kfd_bo)
 173                 return 0;
 174
 175         if (amdgpu_ttm_tt_get_usermm(bo->ttm))
 176                 return -EPERM;
 177         return drm_vma_node_verify_access(&abo->tbo.base.vma_node,
 178                                           filp->private_data);
 179 }
 180
 181 /**
 182  * amdgpu_ttm_map_buffer - Map memory into the GART windows
 183  * @bo: buffer object to map
 184  * @mem: memory object to map
 185  * @mm_cur: range to map
 186  * @num_pages: number of pages to map
 187  * @window: which GART window to use
 188  * @ring: DMA ring to use for the copy
 189  * @tmz: if we should setup a TMZ enabled mapping
 190  * @addr: resulting address inside the MC address space
 191  *
 192  * Setup one of the GART windows to access a specific piece of memory or return
 193  * the physical address for local memory.
 194  */
 195 static int amdgpu_ttm_map_buffer(struct ttm_buffer_object *bo,
 196                                  struct ttm_resource *mem,
 197                                  struct amdgpu_res_cursor *mm_cur,
 198                                  unsigned num_pages, unsigned window,
 199                                  struct amdgpu_ring *ring, bool tmz,
 200                                  uint64_t *addr)
 201 {
 202         struct amdgpu_device *adev = ring->adev;
 203         struct amdgpu_job *job;
 204         unsigned num_dw, num_bytes;
 205         struct dma_fence *fence;
 206         uint64_t src_addr, dst_addr;
 207         void *cpu_addr;
 208         uint64_t flags;
 209         unsigned int i;
 210         int r;
 211
 212         BUG_ON(adev->mman.buffer_funcs->copy_max_bytes <
 213                AMDGPU_GTT_MAX_TRANSFER_SIZE * 8);
 214
 215         /* Map only what can't be accessed directly */
 216         if (!tmz && mem->start != AMDGPU_BO_INVALID_OFFSET) {
 217                 *addr = amdgpu_ttm_domain_start(adev, mem->mem_type) +
 218                         mm_cur->start;
 219                 return 0;
 220         }
 221
 222         *addr = adev->gmc.gart_start;
 223         *addr += (u64)window * AMDGPU_GTT_MAX_TRANSFER_SIZE *
 224                 AMDGPU_GPU_PAGE_SIZE;
 225         *addr += mm_cur->start & ~PAGE_MASK;
 226
 227         num_dw = ALIGN(adev->mman.buffer_funcs->copy_num_dw, 8);
 228         num_bytes = num_pages * 8;
 229
 230         r = amdgpu_job_alloc_with_ib(adev, num_dw * 4 + num_bytes,
 231                                      AMDGPU_IB_POOL_DELAYED, &job);
 232         if (r)
 233                 return r;
 234
 235         src_addr = num_dw * 4;
 236         src_addr += job->ibs[0].gpu_addr;
 237
 238         dst_addr = amdgpu_bo_gpu_offset(adev->gart.bo);
 239         dst_addr += window * AMDGPU_GTT_MAX_TRANSFER_SIZE * 8;
 240         amdgpu_emit_copy_buffer(adev, &job->ibs[0], src_addr,
 241                                 dst_addr, num_bytes, false);
 242
 243         amdgpu_ring_pad_ib(ring, &job->ibs[0]);
 244         WARN_ON(job->ibs[0].length_dw > num_dw);
 245
 246         flags = amdgpu_ttm_tt_pte_flags(adev, bo->ttm, mem);
 247         if (tmz)
 248                 flags |= AMDGPU_PTE_TMZ;
 249
 250         cpu_addr = &job->ibs[0].ptr[num_dw];
 251
 252         if (mem->mem_type == TTM_PL_TT) {
 253                 dma_addr_t *dma_addr;
 254
 255                 dma_addr = &bo->ttm->dma_address[mm_cur->start >> PAGE_SHIFT];
 256                 r = amdgpu_gart_map(adev, 0, num_pages, dma_addr, flags,
 257                                     cpu_addr);
 258                 if (r)
 259                         goto error_free;
 260         } else {
 261                 dma_addr_t dma_address;
 262
 263                 dma_address = mm_cur->start;
 264                 dma_address += adev->vm_manager.vram_base_offset;
 265
 266                 for (i = 0; i < num_pages; ++i) {
 267                         r = amdgpu_gart_map(adev, i << PAGE_SHIFT, 1,
 268                                             &dma_address, flags, cpu_addr);
 269                         if (r)
 270                                 goto error_free;
 271
 272                         dma_address += PAGE_SIZE;
 273                 }
 274         }
 275
 276         r = amdgpu_job_submit(job, &adev->mman.entity,
 277                               AMDGPU_FENCE_OWNER_UNDEFINED, &fence);
 278         if (r)
 279                 goto error_free;
 280
 281         dma_fence_put(fence);
 282
 283         return r;
 284
 285 error_free:
 286         amdgpu_job_free(job);
 287         return r;
 288 }
 289
 290 /**
 291  * amdgpu_copy_ttm_mem_to_mem - Helper function for copy
 292  * @adev: amdgpu device
 293  * @src: buffer/address where to read from
 294  * @dst: buffer/address where to write to
 295  * @size: number of bytes to copy
 296  * @tmz: if a secure copy should be used
 297  * @resv: resv object to sync to
 298  * @f: Returns the last fence if multiple jobs are submitted.
 299  *
 300  * The function copies @size bytes from {src->mem + src->offset} to
 301  * {dst->mem + dst->offset}. src->bo and dst->bo could be same BO for a
 302  * move and different for a BO to BO copy.
 303  *
 304  */
 305 int amdgpu_ttm_copy_mem_to_mem(struct amdgpu_device *adev,
 306                                const struct amdgpu_copy_mem *src,
 307                                const struct amdgpu_copy_mem *dst,
 308                                uint64_t size, bool tmz,
 309                                struct dma_resv *resv,
 310                                struct dma_fence **f)
 311 {
 312         const uint32_t GTT_MAX_BYTES = (AMDGPU_GTT_MAX_TRANSFER_SIZE *
 313                                         AMDGPU_GPU_PAGE_SIZE);
 314
 315         struct amdgpu_ring *ring = adev->mman.buffer_funcs_ring;
 316         struct amdgpu_res_cursor src_mm, dst_mm;
 317         struct dma_fence *fence = NULL;
 318         int r = 0;
 319
 320         if (!adev->mman.buffer_funcs_enabled) {
 321                 DRM_ERROR("Trying to move memory with ring turned off.\n");
 322                 return -EINVAL;
 323         }
 324
 325         amdgpu_res_first(src->mem, src->offset, size, &src_mm);
 326         amdgpu_res_first(dst->mem, dst->offset, size, &dst_mm);
 327
 328         mutex_lock(&adev->mman.gtt_window_lock);
 329         while (src_mm.remaining) {
 330                 uint32_t src_page_offset = src_mm.start & ~PAGE_MASK;
 331                 uint32_t dst_page_offset = dst_mm.start & ~PAGE_MASK;
 332                 struct dma_fence *next;
 333                 uint32_t cur_size;
 334                 uint64_t from, to;
 335
 336                 /* Copy size cannot exceed GTT_MAX_BYTES. So if src or dst
 337                  * begins at an offset, then adjust the size accordingly
 338                  */
 339                 cur_size = max(src_page_offset, dst_page_offset);
 340                 cur_size = min(min3(src_mm.size, dst_mm.size, size),
 341                                (uint64_t)(GTT_MAX_BYTES - cur_size));
 342
 343                 /* Map src to window 0 and dst to window 1. */
 344                 r = amdgpu_ttm_map_buffer(src->bo, src->mem, &src_mm,
 345                                           PFN_UP(cur_size + src_page_offset),
 346                                           0, ring, tmz, &from);
 347                 if (r)
 348                         goto error;
 349
 350                 r = amdgpu_ttm_map_buffer(dst->bo, dst->mem, &dst_mm,
 351                                           PFN_UP(cur_size + dst_page_offset),
 352                                           1, ring, tmz, &to);
 353                 if (r)
 354                         goto error;
 355
 356                 r = amdgpu_copy_buffer(ring, from, to, cur_size,
 357                                        resv, &next, false, true, tmz);
 358                 if (r)
 359                         goto error;
 360
 361                 dma_fence_put(fence);
 362                 fence = next;
 363
 364                 amdgpu_res_next(&src_mm, cur_size);
 365                 amdgpu_res_next(&dst_mm, cur_size);
 366         }
 367 error:
 368         mutex_unlock(&adev->mman.gtt_window_lock);
 369         if (f)
 370                 *f = dma_fence_get(fence);
 371         dma_fence_put(fence);
 372         return r;
 373 }
 374
 375 /*
 376  * amdgpu_move_blit - Copy an entire buffer to another buffer
 377  *
 378  * This is a helper called by amdgpu_bo_move() and amdgpu_move_vram_ram() to
 379  * help move buffers to and from VRAM.
 380  */
 381 static int amdgpu_move_blit(struct ttm_buffer_object *bo,
 382                             bool evict,
 383                             struct ttm_resource *new_mem,
 384                             struct ttm_resource *old_mem)
 385 {
 386         struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev);
 387         struct amdgpu_bo *abo = ttm_to_amdgpu_bo(bo);
 388         struct amdgpu_copy_mem src, dst;
 389         struct dma_fence *fence = NULL;
 390         int r;
 391
 392         src.bo = bo;
 393         dst.bo = bo;
 394         src.mem = old_mem;
 395         dst.mem = new_mem;
 396         src.offset = 0;
 397         dst.offset = 0;
 398
 399         r = amdgpu_ttm_copy_mem_to_mem(adev, &src, &dst,
 400                                        new_mem->num_pages << PAGE_SHIFT,
 401                                        amdgpu_bo_encrypted(abo),
 402                                        bo->base.resv, &fence);
 403         if (r)
 404                 goto error;
 405
 406         /* clear the space being freed */
 407         if (old_mem->mem_type == TTM_PL_VRAM &&
 408             (abo->flags & AMDGPU_GEM_CREATE_VRAM_WIPE_ON_RELEASE)) {
 409                 struct dma_fence *wipe_fence = NULL;
 410
 411                 r = amdgpu_fill_buffer(ttm_to_amdgpu_bo(bo), AMDGPU_POISON,
 412                                        NULL, &wipe_fence);
 413                 if (r) {
 414                         goto error;
 415                 } else if (wipe_fence) {
 416                         dma_fence_put(fence);
 417                         fence = wipe_fence;
 418                 }
 419         }
 420
 421         /* Always block for VM page tables before committing the new location */
 422         if (bo->type == ttm_bo_type_kernel)
 423                 r = ttm_bo_move_accel_cleanup(bo, fence, true, false, new_mem);
 424         else
 425                 r = ttm_bo_move_accel_cleanup(bo, fence, evict, true, new_mem);
 426         dma_fence_put(fence);
 427         return r;
 428
 429 error:
 430         if (fence)
 431                 dma_fence_wait(fence, false);
 432         dma_fence_put(fence);
 433         return r;
 434 }
 435
 436 /*
 437  * amdgpu_mem_visible - Check that memory can be accessed by ttm_bo_move_memcpy
 438  *
 439  * Called by amdgpu_bo_move()
 440  */
 441 static bool amdgpu_mem_visible(struct amdgpu_device *adev,
 442                                struct ttm_resource *mem)
 443 {
 444         uint64_t mem_size = (u64)mem->num_pages << PAGE_SHIFT;
 445         struct amdgpu_res_cursor cursor;
 446
 447         if (mem->mem_type == TTM_PL_SYSTEM ||
 448             mem->mem_type == TTM_PL_TT)
 449                 return true;
 450         if (mem->mem_type != TTM_PL_VRAM)
 451                 return false;
 452
 453         amdgpu_res_first(mem, 0, mem_size, &cursor);
 454
 455         /* ttm_resource_ioremap only supports contiguous memory */
 456         if (cursor.size != mem_size)
 457                 return false;
 458
 459         return cursor.start + cursor.size <= adev->gmc.visible_vram_size;
 460 }
 461
 462 /*
 463  * amdgpu_bo_move - Move a buffer object to a new memory location
 464  *
 465  * Called by ttm_bo_handle_move_mem()
 466  */
 467 static int amdgpu_bo_move(struct ttm_buffer_object *bo, bool evict,
 468                           struct ttm_operation_ctx *ctx,
 469                           struct ttm_resource *new_mem,
 470                           struct ttm_place *hop)
 471 {
 472         struct amdgpu_device *adev;
 473         struct amdgpu_bo *abo;
 474         struct ttm_resource *old_mem = &bo->mem;
 475         int r;
 476
 477         if (new_mem->mem_type == TTM_PL_TT) {
 478                 r = amdgpu_ttm_backend_bind(bo->bdev, bo->ttm, new_mem);
 479                 if (r)
 480                         return r;
 481         }
 482
 483         /* Can't move a pinned BO */
 484         abo = ttm_to_amdgpu_bo(bo);
 485         if (WARN_ON_ONCE(abo->tbo.pin_count > 0))
 486                 return -EINVAL;
 487
 488         adev = amdgpu_ttm_adev(bo->bdev);
 489
 490         if (old_mem->mem_type == TTM_PL_SYSTEM && bo->ttm == NULL) {
 491                 ttm_bo_move_null(bo, new_mem);
 492                 goto out;
 493         }
 494         if (old_mem->mem_type == TTM_PL_SYSTEM &&
 495             new_mem->mem_type == TTM_PL_TT) {
 496                 ttm_bo_move_null(bo, new_mem);
 497                 goto out;
 498         }
 499         if (old_mem->mem_type == TTM_PL_TT &&
 500             new_mem->mem_type == TTM_PL_SYSTEM) {
 501                 r = ttm_bo_wait_ctx(bo, ctx);
 502                 if (r)
 503                         return r;
 504
 505                 amdgpu_ttm_backend_unbind(bo->bdev, bo->ttm);
 506                 ttm_resource_free(bo, &bo->mem);
 507                 ttm_bo_assign_mem(bo, new_mem);
 508                 goto out;
 509         }
 510
 511         if (old_mem->mem_type == AMDGPU_PL_GDS ||
 512             old_mem->mem_type == AMDGPU_PL_GWS ||
 513             old_mem->mem_type == AMDGPU_PL_OA ||
 514             new_mem->mem_type == AMDGPU_PL_GDS ||
 515             new_mem->mem_type == AMDGPU_PL_GWS ||
 516             new_mem->mem_type == AMDGPU_PL_OA) {
 517                 /* Nothing to save here */
 518                 ttm_bo_move_null(bo, new_mem);
 519                 goto out;
 520         }
 521
 522         if (adev->mman.buffer_funcs_enabled) {
 523                 if (((old_mem->mem_type == TTM_PL_SYSTEM &&
 524                       new_mem->mem_type == TTM_PL_VRAM) ||
 525                      (old_mem->mem_type == TTM_PL_VRAM &&
 526                       new_mem->mem_type == TTM_PL_SYSTEM))) {
 527                         hop->fpfn = 0;
 528                         hop->lpfn = 0;
 529                         hop->mem_type = TTM_PL_TT;
 530                         hop->flags = 0;
 531                         return -EMULTIHOP;
 532                 }
 533
 534                 r = amdgpu_move_blit(bo, evict, new_mem, old_mem);
 535         } else {
 536                 r = -ENODEV;
 537         }
 538
 539         if (r) {
 540                 /* Check that all memory is CPU accessible */
 541                 if (!amdgpu_mem_visible(adev, old_mem) ||
 542                     !amdgpu_mem_visible(adev, new_mem)) {
 543                         pr_err("Move buffer fallback to memcpy unavailable\n");
 544                         return r;
 545                 }
 546
 547                 r = ttm_bo_move_memcpy(bo, ctx, new_mem);
 548                 if (r)
 549                         return r;
 550         }
 551
 552         if (bo->type == ttm_bo_type_device &&
 553             new_mem->mem_type == TTM_PL_VRAM &&
 554             old_mem->mem_type != TTM_PL_VRAM) {
 555                 /* amdgpu_bo_fault_reserve_notify will re-set this if the CPU
 556                  * accesses the BO after it's moved.
 557                  */
 558                 abo->flags &= ~AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED;
 559         }
 560
 561 out:
 562         /* update statistics */
 563         atomic64_add(bo->base.size, &adev->num_bytes_moved);
 564         amdgpu_bo_move_notify(bo, evict, new_mem);
 565         return 0;
 566 }
 567
 568 /*
 569  * amdgpu_ttm_io_mem_reserve - Reserve a block of memory during a fault
 570  *
 571  * Called by ttm_mem_io_reserve() ultimately via ttm_bo_vm_fault()
 572  */
 573 static int amdgpu_ttm_io_mem_reserve(struct ttm_device *bdev, struct ttm_resource *mem)
 574 {
 575         struct amdgpu_device *adev = amdgpu_ttm_adev(bdev);
 576         struct drm_mm_node *mm_node = mem->mm_node;
 577         size_t bus_size = (size_t)mem->num_pages << PAGE_SHIFT;
 578
 579         switch (mem->mem_type) {
 580         case TTM_PL_SYSTEM:
 581                 /* system memory */
 582                 return 0;
 583         case TTM_PL_TT:
 584                 break;
 585         case TTM_PL_VRAM:
 586                 mem->bus.offset = mem->start << PAGE_SHIFT;
 587                 /* check if it's visible */
 588                 if ((mem->bus.offset + bus_size) > adev->gmc.visible_vram_size)
 589                         return -EINVAL;
 590                 /* Only physically contiguous buffers apply. In a contiguous
 591                  * buffer, size of the first mm_node would match the number of
 592                  * pages in ttm_resource.
 593                  */
 594                 if (adev->mman.aper_base_kaddr &&
 595                     (mm_node->size == mem->num_pages))
 596                         mem->bus.addr = (u8 *)adev->mman.aper_base_kaddr +
 597                                         mem->bus.offset;
 598
 599                 mem->bus.offset += adev->gmc.aper_base;
 600                 mem->bus.is_iomem = true;
 601                 if (adev->gmc.xgmi.connected_to_cpu)
 602                         mem->bus.caching = ttm_cached;
 603                 else
 604                         mem->bus.caching = ttm_write_combined;
 605                 break;
 606         default:
 607                 return -EINVAL;
 608         }
 609         return 0;
 610 }
 611
 612 static unsigned long amdgpu_ttm_io_mem_pfn(struct ttm_buffer_object *bo,
 613                                            unsigned long page_offset)
 614 {
 615         struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev);
 616         struct amdgpu_res_cursor cursor;
 617
 618         amdgpu_res_first(&bo->mem, (u64)page_offset << PAGE_SHIFT, 0, &cursor);
 619         return (adev->gmc.aper_base + cursor.start) >> PAGE_SHIFT;
 620 }
 621
 622 /**
 623  * amdgpu_ttm_domain_start - Returns GPU start address
 624  * @adev: amdgpu device object
 625  * @type: type of the memory
 626  *
 627  * Returns:
 628  * GPU start address of a memory domain
 629  */
 630
 631 uint64_t amdgpu_ttm_domain_start(struct amdgpu_device *adev, uint32_t type)
 632 {
 633         switch (type) {
 634         case TTM_PL_TT:
 635                 return adev->gmc.gart_start;
 636         case TTM_PL_VRAM:
 637                 return adev->gmc.vram_start;
 638         }
 639
 640         return 0;
 641 }
 642
 643 /*
 644  * TTM backend functions.
 645  */
 646 struct amdgpu_ttm_tt {
 647         struct ttm_tt   ttm;
 648         struct drm_gem_object   *gobj;
 649         u64                     offset;
 650         uint64_t                userptr;
 651         struct task_struct      *usertask;
 652         uint32_t                userflags;
 653         bool                    bound;
 654 #if IS_ENABLED(CONFIG_DRM_AMDGPU_USERPTR)
 655         struct hmm_range        *range;
 656 #endif
 657 };
 658
 659 #ifdef CONFIG_DRM_AMDGPU_USERPTR
 660 /*
 661  * amdgpu_ttm_tt_get_user_pages - get device accessible pages that back user
 662  * memory and start HMM tracking CPU page table update
 663  *
 664  * Calling function must call amdgpu_ttm_tt_userptr_range_done() once and only
 665  * once afterwards to stop HMM tracking
 666  */
 667 int amdgpu_ttm_tt_get_user_pages(struct amdgpu_bo *bo, struct page **pages)
 668 {
 669         struct ttm_tt *ttm = bo->tbo.ttm;
 670         struct amdgpu_ttm_tt *gtt = (void *)ttm;
 671         unsigned long start = gtt->userptr;
 672         struct vm_area_struct *vma;
 673         struct hmm_range *range;
 674         unsigned long timeout;
 675         struct mm_struct *mm;
 676         unsigned long i;
 677         int r = 0;
 678
 679         mm = bo->notifier.mm;
 680         if (unlikely(!mm)) {
 681                 DRM_DEBUG_DRIVER("BO is not registered?\n");
 682                 return -EFAULT;
 683         }
 684
 685         /* Another get_user_pages is running at the same time?? */
 686         if (WARN_ON(gtt->range))
 687                 return -EFAULT;
 688
 689         if (!mmget_not_zero(mm)) /* Happens during process shutdown */
 690                 return -ESRCH;
 691
 692         range = kzalloc(sizeof(*range), GFP_KERNEL);
 693         if (unlikely(!range)) {
 694                 r = -ENOMEM;
 695                 goto out;
 696         }
 697         range->notifier = &bo->notifier;
 698         range->start = bo->notifier.interval_tree.start;
 699         range->end = bo->notifier.interval_tree.last + 1;
 700         range->default_flags = HMM_PFN_REQ_FAULT;
 701         if (!amdgpu_ttm_tt_is_readonly(ttm))
 702                 range->default_flags |= HMM_PFN_REQ_WRITE;
 703
 704         range->hmm_pfns = kvmalloc_array(ttm->num_pages,
 705                                          sizeof(*range->hmm_pfns), GFP_KERNEL);
 706         if (unlikely(!range->hmm_pfns)) {
 707                 r = -ENOMEM;
 708                 goto out_free_ranges;
 709         }
 710
 711         mmap_read_lock(mm);
 712         vma = find_vma(mm, start);
 713         if (unlikely(!vma || start < vma->vm_start)) {
 714                 r = -EFAULT;
 715                 goto out_unlock;
 716         }
 717         if (unlikely((gtt->userflags & AMDGPU_GEM_USERPTR_ANONONLY) &&
 718                 vma->vm_file)) {
 719                 r = -EPERM;
 720                 goto out_unlock;
 721         }
 722         mmap_read_unlock(mm);
 723         timeout = jiffies + msecs_to_jiffies(HMM_RANGE_DEFAULT_TIMEOUT);
 724
 725 retry:
 726         range->notifier_seq = mmu_interval_read_begin(&bo->notifier);
 727
 728         mmap_read_lock(mm);
 729         r = hmm_range_fault(range);
 730         mmap_read_unlock(mm);
 731         if (unlikely(r)) {
 732                 /*
 733                  * FIXME: This timeout should encompass the retry from
 734                  * mmu_interval_read_retry() as well.
 735                  */
 736                 if (r == -EBUSY && !time_after(jiffies, timeout))
 737                         goto retry;
 738                 goto out_free_pfns;
 739         }
 740
 741         /*
 742          * Due to default_flags, all pages are HMM_PFN_VALID or
 743          * hmm_range_fault() fails. FIXME: The pages cannot be touched outside
 744          * the notifier_lock, and mmu_interval_read_retry() must be done first.
 745          */
 746         for (i = 0; i < ttm->num_pages; i++)
 747                 pages[i] = hmm_pfn_to_page(range->hmm_pfns[i]);
 748
 749         gtt->range = range;
 750         mmput(mm);
 751
 752         return 0;
 753
 754 out_unlock:
 755         mmap_read_unlock(mm);
 756 out_free_pfns:
 757         kvfree(range->hmm_pfns);
 758 out_free_ranges:
 759         kfree(range);
 760 out:
 761         mmput(mm);
 762         return r;
 763 }
 764
 765 /*
 766  * amdgpu_ttm_tt_userptr_range_done - stop HMM track the CPU page table change
 767  * Check if the pages backing this ttm range have been invalidated
 768  *
 769  * Returns: true if pages are still valid
 770  */
 771 bool amdgpu_ttm_tt_get_user_pages_done(struct ttm_tt *ttm)
 772 {
 773         struct amdgpu_ttm_tt *gtt = (void *)ttm;
 774         bool r = false;
 775
 776         if (!gtt || !gtt->userptr)
 777                 return false;
 778
 779         DRM_DEBUG_DRIVER("user_pages_done 0x%llx pages 0x%x\n",
 780                 gtt->userptr, ttm->num_pages);
 781
 782         WARN_ONCE(!gtt->range || !gtt->range->hmm_pfns,
 783                 "No user pages to check\n");
 784
 785         if (gtt->range) {
 786                 /*
 787                  * FIXME: Must always hold notifier_lock for this, and must
 788                  * not ignore the return code.
 789                  */
 790                 r = mmu_interval_read_retry(gtt->range->notifier,
 791                                          gtt->range->notifier_seq);
 792                 kvfree(gtt->range->hmm_pfns);
 793                 kfree(gtt->range);
 794                 gtt->range = NULL;
 795         }
 796
 797         return !r;
 798 }
 799 #endif
 800
 801 /*
 802  * amdgpu_ttm_tt_set_user_pages - Copy pages in, putting old pages as necessary.
 803  *
 804  * Called by amdgpu_cs_list_validate(). This creates the page list
 805  * that backs user memory and will ultimately be mapped into the device
 806  * address space.
 807  */
 808 void amdgpu_ttm_tt_set_user_pages(struct ttm_tt *ttm, struct page **pages)
 809 {
 810         unsigned long i;
 811
 812         for (i = 0; i < ttm->num_pages; ++i)
 813                 ttm->pages[i] = pages ? pages[i] : NULL;
 814 }
 815
 816 /*
 817  * amdgpu_ttm_tt_pin_userptr - prepare the sg table with the user pages
 818  *
 819  * Called by amdgpu_ttm_backend_bind()
 820  **/
 821 static int amdgpu_ttm_tt_pin_userptr(struct ttm_device *bdev,
 822                                      struct ttm_tt *ttm)
 823 {
 824         struct amdgpu_device *adev = amdgpu_ttm_adev(bdev);
 825         struct amdgpu_ttm_tt *gtt = (void *)ttm;
 826         int write = !(gtt->userflags & AMDGPU_GEM_USERPTR_READONLY);
 827         enum dma_data_direction direction = write ?
 828                 DMA_BIDIRECTIONAL : DMA_TO_DEVICE;
 829         int r;
 830
 831         /* Allocate an SG array and squash pages into it */
 832         r = sg_alloc_table_from_pages(ttm->sg, ttm->pages, ttm->num_pages, 0,
 833                                       (u64)ttm->num_pages << PAGE_SHIFT,
 834                                       GFP_KERNEL);
 835         if (r)
 836                 goto release_sg;
 837
 838         /* Map SG to device */
 839         r = dma_map_sgtable(adev->dev, ttm->sg, direction, 0);
 840         if (r)
 841                 goto release_sg;
 842
 843         /* convert SG to linear array of pages and dma addresses */
 844         drm_prime_sg_to_dma_addr_array(ttm->sg, gtt->ttm.dma_address,
 845                                        ttm->num_pages);
 846
 847         return 0;
 848
 849 release_sg:
 850         kfree(ttm->sg);
 851         ttm->sg = NULL;
 852         return r;
 853 }
 854
 855 /*
 856  * amdgpu_ttm_tt_unpin_userptr - Unpin and unmap userptr pages
 857  */
 858 static void amdgpu_ttm_tt_unpin_userptr(struct ttm_device *bdev,
 859                                         struct ttm_tt *ttm)
 860 {
 861         struct amdgpu_device *adev = amdgpu_ttm_adev(bdev);
 862         struct amdgpu_ttm_tt *gtt = (void *)ttm;
 863         int write = !(gtt->userflags & AMDGPU_GEM_USERPTR_READONLY);
 864         enum dma_data_direction direction = write ?
 865                 DMA_BIDIRECTIONAL : DMA_TO_DEVICE;
 866
 867         /* double check that we don't free the table twice */
 868         if (!ttm->sg || !ttm->sg->sgl)
 869                 return;
 870
 871         /* unmap the pages mapped to the device */
 872         dma_unmap_sgtable(adev->dev, ttm->sg, direction, 0);
 873         sg_free_table(ttm->sg);
 874
 875 #if IS_ENABLED(CONFIG_DRM_AMDGPU_USERPTR)
 876         if (gtt->range) {
 877                 unsigned long i;
 878
 879                 for (i = 0; i < ttm->num_pages; i++) {
 880                         if (ttm->pages[i] !=
 881                             hmm_pfn_to_page(gtt->range->hmm_pfns[i]))
 882                                 break;
 883                 }
 884
 885                 WARN((i == ttm->num_pages), "Missing get_user_page_done\n");
 886         }
 887 #endif
 888 }
 889
 890 static int amdgpu_ttm_gart_bind(struct amdgpu_device *adev,
 891                                 struct ttm_buffer_object *tbo,
 892                                 uint64_t flags)
 893 {
 894         struct amdgpu_bo *abo = ttm_to_amdgpu_bo(tbo);
 895         struct ttm_tt *ttm = tbo->ttm;
 896         struct amdgpu_ttm_tt *gtt = (void *)ttm;
 897         int r;
 898
 899         if (amdgpu_bo_encrypted(abo))
 900                 flags |= AMDGPU_PTE_TMZ;
 901
 902         if (abo->flags & AMDGPU_GEM_CREATE_CP_MQD_GFX9) {
 903                 uint64_t page_idx = 1;
 904
 905                 r = amdgpu_gart_bind(adev, gtt->offset, page_idx,
 906                                 ttm->pages, gtt->ttm.dma_address, flags);
 907                 if (r)
 908                         goto gart_bind_fail;
 909
 910                 /* The memory type of the first page defaults to UC. Now
 911                  * modify the memory type to NC from the second page of
 912                  * the BO onward.
 913                  */
 914                 flags &= ~AMDGPU_PTE_MTYPE_VG10_MASK;
 915                 flags |= AMDGPU_PTE_MTYPE_VG10(AMDGPU_MTYPE_NC);
 916
 917                 r = amdgpu_gart_bind(adev,
 918                                 gtt->offset + (page_idx << PAGE_SHIFT),
 919                                 ttm->num_pages - page_idx,
 920                                 &ttm->pages[page_idx],
 921                                 &(gtt->ttm.dma_address[page_idx]), flags);
 922         } else {
 923                 r = amdgpu_gart_bind(adev, gtt->offset, ttm->num_pages,
 924                                      ttm->pages, gtt->ttm.dma_address, flags);
 925         }
 926
 927 gart_bind_fail:
 928         if (r)
 929                 DRM_ERROR("failed to bind %u pages at 0x%08llX\n",
 930                           ttm->num_pages, gtt->offset);
 931
 932         return r;
 933 }
 934
 935 /*
 936  * amdgpu_ttm_backend_bind - Bind GTT memory
 937  *
 938  * Called by ttm_tt_bind() on behalf of ttm_bo_handle_move_mem().
 939  * This handles binding GTT memory to the device address space.
 940  */
 941 static int amdgpu_ttm_backend_bind(struct ttm_device *bdev,
 942                                    struct ttm_tt *ttm,
 943                                    struct ttm_resource *bo_mem)
 944 {
 945         struct amdgpu_device *adev = amdgpu_ttm_adev(bdev);
 946         struct amdgpu_ttm_tt *gtt = (void*)ttm;
 947         uint64_t flags;
 948         int r = 0;
 949
 950         if (!bo_mem)
 951                 return -EINVAL;
 952
 953         if (gtt->bound)
 954                 return 0;
 955
 956         if (gtt->userptr) {
 957                 r = amdgpu_ttm_tt_pin_userptr(bdev, ttm);
 958                 if (r) {
 959                         DRM_ERROR("failed to pin userptr\n");
 960                         return r;
 961                 }
 962         }
 963         if (!ttm->num_pages) {
 964                 WARN(1, "nothing to bind %u pages for mreg %p back %p!\n",
 965                      ttm->num_pages, bo_mem, ttm);
 966         }
 967
 968         if (bo_mem->mem_type == AMDGPU_PL_GDS ||
 969             bo_mem->mem_type == AMDGPU_PL_GWS ||
 970             bo_mem->mem_type == AMDGPU_PL_OA)
 971                 return -EINVAL;
 972
 973         if (!amdgpu_gtt_mgr_has_gart_addr(bo_mem)) {
 974                 gtt->offset = AMDGPU_BO_INVALID_OFFSET;
 975                 return 0;
 976         }
 977
 978         /* compute PTE flags relevant to this BO memory */
 979         flags = amdgpu_ttm_tt_pte_flags(adev, ttm, bo_mem);
 980
 981         /* bind pages into GART page tables */
 982         gtt->offset = (u64)bo_mem->start << PAGE_SHIFT;
 983         r = amdgpu_gart_bind(adev, gtt->offset, ttm->num_pages,
 984                 ttm->pages, gtt->ttm.dma_address, flags);
 985
 986         if (r)
 987                 DRM_ERROR("failed to bind %u pages at 0x%08llX\n",
 988                           ttm->num_pages, gtt->offset);
 989         gtt->bound = true;
 990         return r;
 991 }
 992
 993 /*
 994  * amdgpu_ttm_alloc_gart - Make sure buffer object is accessible either
 995  * through AGP or GART aperture.
 996  *
 997  * If bo is accessible through AGP aperture, then use AGP aperture
 998  * to access bo; otherwise allocate logical space in GART aperture
 999  * and map bo to GART aperture.
1000  */
1001 int amdgpu_ttm_alloc_gart(struct ttm_buffer_object *bo)
1002 {
1003         struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev);
1004         struct ttm_operation_ctx ctx = { false, false };
1005         struct amdgpu_ttm_tt *gtt = (void *)bo->ttm;
1006         struct ttm_resource tmp;
1007         struct ttm_placement placement;
1008         struct ttm_place placements;
1009         uint64_t addr, flags;
1010         int r;
1011
1012         if (bo->mem.start != AMDGPU_BO_INVALID_OFFSET)
1013                 return 0;
1014
1015         addr = amdgpu_gmc_agp_addr(bo);
1016         if (addr != AMDGPU_BO_INVALID_OFFSET) {
1017                 bo->mem.start = addr >> PAGE_SHIFT;
1018         } else {
1019
1020                 /* allocate GART space */
1021                 placement.num_placement = 1;
1022                 placement.placement = &placements;
1023                 placement.num_busy_placement = 1;
1024                 placement.busy_placement = &placements;
1025                 placements.fpfn = 0;
1026                 placements.lpfn = adev->gmc.gart_size >> PAGE_SHIFT;
1027                 placements.mem_type = TTM_PL_TT;
1028                 placements.flags = bo->mem.placement;
1029
1030                 r = ttm_bo_mem_space(bo, &placement, &tmp, &ctx);
1031                 if (unlikely(r))
1032                         return r;
1033
1034                 /* compute PTE flags for this buffer object */
1035                 flags = amdgpu_ttm_tt_pte_flags(adev, bo->ttm, &tmp);
1036
1037                 /* Bind pages */
1038                 gtt->offset = (u64)tmp.start << PAGE_SHIFT;
1039                 r = amdgpu_ttm_gart_bind(adev, bo, flags);
1040                 if (unlikely(r)) {
1041                         ttm_resource_free(bo, &tmp);
1042                         return r;
1043                 }
1044
1045                 ttm_resource_free(bo, &bo->mem);
1046                 bo->mem = tmp;
1047         }
1048
1049         return 0;
1050 }
1051
1052 /*
1053  * amdgpu_ttm_recover_gart - Rebind GTT pages
1054  *
1055  * Called by amdgpu_gtt_mgr_recover() from amdgpu_device_reset() to
1056  * rebind GTT pages during a GPU reset.
1057  */
1058 int amdgpu_ttm_recover_gart(struct ttm_buffer_object *tbo)
1059 {
1060         struct amdgpu_device *adev = amdgpu_ttm_adev(tbo->bdev);
1061         uint64_t flags;
1062         int r;
1063
1064         if (!tbo->ttm)
1065                 return 0;
1066
1067         flags = amdgpu_ttm_tt_pte_flags(adev, tbo->ttm, &tbo->mem);
1068         r = amdgpu_ttm_gart_bind(adev, tbo, flags);
1069
1070         return r;
1071 }
1072
1073 /*
1074  * amdgpu_ttm_backend_unbind - Unbind GTT mapped pages
1075  *
1076  * Called by ttm_tt_unbind() on behalf of ttm_bo_move_ttm() and
1077  * ttm_tt_destroy().
1078  */
1079 static void amdgpu_ttm_backend_unbind(struct ttm_device *bdev,
1080                                       struct ttm_tt *ttm)
1081 {
1082         struct amdgpu_device *adev = amdgpu_ttm_adev(bdev);
1083         struct amdgpu_ttm_tt *gtt = (void *)ttm;
1084         int r;
1085
1086         /* if the pages have userptr pinning then clear that first */
1087         if (gtt->userptr)
1088                 amdgpu_ttm_tt_unpin_userptr(bdev, ttm);
1089
1090         if (!gtt->bound)
1091                 return;
1092
1093         if (gtt->offset == AMDGPU_BO_INVALID_OFFSET)
1094                 return;
1095
1096         /* unbind shouldn't be done for GDS/GWS/OA in ttm_bo_clean_mm */
1097         r = amdgpu_gart_unbind(adev, gtt->offset, ttm->num_pages);
1098         if (r)
1099                 DRM_ERROR("failed to unbind %u pages at 0x%08llX\n",
1100                           gtt->ttm.num_pages, gtt->offset);
1101         gtt->bound = false;
1102 }
1103
1104 static void amdgpu_ttm_backend_destroy(struct ttm_device *bdev,
1105                                        struct ttm_tt *ttm)
1106 {
1107         struct amdgpu_ttm_tt *gtt = (void *)ttm;
1108
1109         amdgpu_ttm_backend_unbind(bdev, ttm);
1110         ttm_tt_destroy_common(bdev, ttm);
1111         if (gtt->usertask)
1112                 put_task_struct(gtt->usertask);
1113
1114         ttm_tt_fini(&gtt->ttm);
1115         kfree(gtt);
1116 }
1117
1118 /**
1119  * amdgpu_ttm_tt_create - Create a ttm_tt object for a given BO
1120  *
1121  * @bo: The buffer object to create a GTT ttm_tt object around
1122  * @page_flags: Page flags to be added to the ttm_tt object
1123  *
1124  * Called by ttm_tt_create().
1125  */
1126 static struct ttm_tt *amdgpu_ttm_tt_create(struct ttm_buffer_object *bo,
1127                                            uint32_t page_flags)
1128 {
1129         struct amdgpu_bo *abo = ttm_to_amdgpu_bo(bo);
1130         struct amdgpu_ttm_tt *gtt;
1131         enum ttm_caching caching;
1132
1133         gtt = kzalloc(sizeof(struct amdgpu_ttm_tt), GFP_KERNEL);
1134         if (gtt == NULL) {
1135                 return NULL;
1136         }
1137         gtt->gobj = &bo->base;
1138
1139         if (abo->flags & AMDGPU_GEM_CREATE_CPU_GTT_USWC)
1140                 caching = ttm_write_combined;
1141         else
1142                 caching = ttm_cached;
1143
1144         /* allocate space for the uninitialized page entries */
1145         if (ttm_sg_tt_init(&gtt->ttm, bo, page_flags, caching)) {
1146                 kfree(gtt);
1147                 return NULL;
1148         }
1149         return &gtt->ttm;
1150 }
1151
1152 /*
1153  * amdgpu_ttm_tt_populate - Map GTT pages visible to the device
1154  *
1155  * Map the pages of a ttm_tt object to an address space visible
1156  * to the underlying device.
1157  */
1158 static int amdgpu_ttm_tt_populate(struct ttm_device *bdev,
1159                                   struct ttm_tt *ttm,
1160                                   struct ttm_operation_ctx *ctx)
1161 {
1162         struct amdgpu_device *adev = amdgpu_ttm_adev(bdev);
1163         struct amdgpu_ttm_tt *gtt = (void *)ttm;
1164
1165         /* user pages are bound by amdgpu_ttm_tt_pin_userptr() */
1166         if (gtt && gtt->userptr) {
1167                 ttm->sg = kzalloc(sizeof(struct sg_table), GFP_KERNEL);
1168                 if (!ttm->sg)
1169                         return -ENOMEM;
1170
1171                 ttm->page_flags |= TTM_PAGE_FLAG_SG;
1172                 return 0;
1173         }
1174
1175         if (ttm->page_flags & TTM_PAGE_FLAG_SG) {
1176                 if (!ttm->sg) {
1177                         struct dma_buf_attachment *attach;
1178                         struct sg_table *sgt;
1179
1180                         attach = gtt->gobj->import_attach;
1181                         sgt = dma_buf_map_attachment(attach, DMA_BIDIRECTIONAL);
1182                         if (IS_ERR(sgt))
1183                                 return PTR_ERR(sgt);
1184
1185                         ttm->sg = sgt;
1186                 }
1187
1188                 drm_prime_sg_to_dma_addr_array(ttm->sg, gtt->ttm.dma_address,
1189                                                ttm->num_pages);
1190                 return 0;
1191         }
1192
1193         return ttm_pool_alloc(&adev->mman.bdev.pool, ttm, ctx);
1194 }
1195
1196 /*
1197  * amdgpu_ttm_tt_unpopulate - unmap GTT pages and unpopulate page arrays
1198  *
1199  * Unmaps pages of a ttm_tt object from the device address space and
1200  * unpopulates the page array backing it.
1201  */
1202 static void amdgpu_ttm_tt_unpopulate(struct ttm_device *bdev,
1203                                      struct ttm_tt *ttm)
1204 {
1205         struct amdgpu_ttm_tt *gtt = (void *)ttm;
1206         struct amdgpu_device *adev;
1207
1208         if (gtt && gtt->userptr) {
1209                 amdgpu_ttm_tt_set_user_pages(ttm, NULL);
1210                 kfree(ttm->sg);
1211                 ttm->page_flags &= ~TTM_PAGE_FLAG_SG;
1212                 return;
1213         }
1214
1215         if (ttm->sg && gtt->gobj->import_attach) {
1216                 struct dma_buf_attachment *attach;
1217
1218                 attach = gtt->gobj->import_attach;
1219                 dma_buf_unmap_attachment(attach, ttm->sg, DMA_BIDIRECTIONAL);
1220                 ttm->sg = NULL;
1221                 return;
1222         }
1223
1224         if (ttm->page_flags & TTM_PAGE_FLAG_SG)
1225                 return;
1226
1227         adev = amdgpu_ttm_adev(bdev);
1228         return ttm_pool_free(&adev->mman.bdev.pool, ttm);
1229 }
1230
1231 /**
1232  * amdgpu_ttm_tt_set_userptr - Initialize userptr GTT ttm_tt for the current
1233  * task
1234  *
1235  * @bo: The ttm_buffer_object to bind this userptr to
1236  * @addr:  The address in the current tasks VM space to use
1237  * @flags: Requirements of userptr object.
1238  *
1239  * Called by amdgpu_gem_userptr_ioctl() to bind userptr pages
1240  * to current task
1241  */
1242 int amdgpu_ttm_tt_set_userptr(struct ttm_buffer_object *bo,
1243                               uint64_t addr, uint32_t flags)
1244 {
1245         struct amdgpu_ttm_tt *gtt;
1246
1247         if (!bo->ttm) {
1248                 /* TODO: We want a separate TTM object type for userptrs */
1249                 bo->ttm = amdgpu_ttm_tt_create(bo, 0);
1250                 if (bo->ttm == NULL)
1251                         return -ENOMEM;
1252         }
1253
1254         gtt = (void *)bo->ttm;
1255         gtt->userptr = addr;
1256         gtt->userflags = flags;
1257
1258         if (gtt->usertask)
1259                 put_task_struct(gtt->usertask);
1260         gtt->usertask = current->group_leader;
1261         get_task_struct(gtt->usertask);
1262
1263         return 0;
1264 }
1265
1266 /*
1267  * amdgpu_ttm_tt_get_usermm - Return memory manager for ttm_tt object
1268  */
1269 struct mm_struct *amdgpu_ttm_tt_get_usermm(struct ttm_tt *ttm)
1270 {
1271         struct amdgpu_ttm_tt *gtt = (void *)ttm;
1272
1273         if (gtt == NULL)
1274                 return NULL;
1275
1276         if (gtt->usertask == NULL)
1277                 return NULL;
1278
1279         return gtt->usertask->mm;
1280 }
1281
1282 /*
1283  * amdgpu_ttm_tt_affect_userptr - Determine if a ttm_tt object lays inside an
1284  * address range for the current task.
1285  *
1286  */
1287 bool amdgpu_ttm_tt_affect_userptr(struct ttm_tt *ttm, unsigned long start,
1288                                   unsigned long end)
1289 {
1290         struct amdgpu_ttm_tt *gtt = (void *)ttm;
1291         unsigned long size;
1292
1293         if (gtt == NULL || !gtt->userptr)
1294                 return false;
1295
1296         /* Return false if no part of the ttm_tt object lies within
1297          * the range
1298          */
1299         size = (unsigned long)gtt->ttm.num_pages * PAGE_SIZE;
1300         if (gtt->userptr > end || gtt->userptr + size <= start)
1301                 return false;
1302
1303         return true;
1304 }
1305
1306 /*
1307  * amdgpu_ttm_tt_is_userptr - Have the pages backing by userptr?
1308  */
1309 bool amdgpu_ttm_tt_is_userptr(struct ttm_tt *ttm)
1310 {
1311         struct amdgpu_ttm_tt *gtt = (void *)ttm;
1312
1313         if (gtt == NULL || !gtt->userptr)
1314                 return false;
1315
1316         return true;
1317 }
1318
1319 /*
1320  * amdgpu_ttm_tt_is_readonly - Is the ttm_tt object read only?
1321  */
1322 bool amdgpu_ttm_tt_is_readonly(struct ttm_tt *ttm)
1323 {
1324         struct amdgpu_ttm_tt *gtt = (void *)ttm;
1325
1326         if (gtt == NULL)
1327                 return false;
1328
1329         return !!(gtt->userflags & AMDGPU_GEM_USERPTR_READONLY);
1330 }
1331
1332 /**
1333  * amdgpu_ttm_tt_pde_flags - Compute PDE flags for ttm_tt object
1334  *
1335  * @ttm: The ttm_tt object to compute the flags for
1336  * @mem: The memory registry backing this ttm_tt object
1337  *
1338  * Figure out the flags to use for a VM PDE (Page Directory Entry).
1339  */
1340 uint64_t amdgpu_ttm_tt_pde_flags(struct ttm_tt *ttm, struct ttm_resource *mem)
1341 {
1342         uint64_t flags = 0;
1343
1344         if (mem && mem->mem_type != TTM_PL_SYSTEM)
1345                 flags |= AMDGPU_PTE_VALID;
1346
1347         if (mem && mem->mem_type == TTM_PL_TT) {
1348                 flags |= AMDGPU_PTE_SYSTEM;
1349
1350                 if (ttm->caching == ttm_cached)
1351                         flags |= AMDGPU_PTE_SNOOPED;
1352         }
1353
1354         if (mem && mem->mem_type == TTM_PL_VRAM &&
1355                         mem->bus.caching == ttm_cached)
1356                 flags |= AMDGPU_PTE_SNOOPED;
1357
1358         return flags;
1359 }
1360
1361 /**
1362  * amdgpu_ttm_tt_pte_flags - Compute PTE flags for ttm_tt object
1363  *
1364  * @adev: amdgpu_device pointer
1365  * @ttm: The ttm_tt object to compute the flags for
1366  * @mem: The memory registry backing this ttm_tt object
1367  *
1368  * Figure out the flags to use for a VM PTE (Page Table Entry).
1369  */
1370 uint64_t amdgpu_ttm_tt_pte_flags(struct amdgpu_device *adev, struct ttm_tt *ttm,
1371                                  struct ttm_resource *mem)
1372 {
1373         uint64_t flags = amdgpu_ttm_tt_pde_flags(ttm, mem);
1374
1375         flags |= adev->gart.gart_pte_flags;
1376         flags |= AMDGPU_PTE_READABLE;
1377
1378         if (!amdgpu_ttm_tt_is_readonly(ttm))
1379                 flags |= AMDGPU_PTE_WRITEABLE;
1380
1381         return flags;
1382 }
1383
1384 /*
1385  * amdgpu_ttm_bo_eviction_valuable - Check to see if we can evict a buffer
1386  * object.
1387  *
1388  * Return true if eviction is sensible. Called by ttm_mem_evict_first() on
1389  * behalf of ttm_bo_mem_force_space() which tries to evict buffer objects until
1390  * it can find space for a new object and by ttm_bo_force_list_clean() which is
1391  * used to clean out a memory space.
1392  */
1393 static bool amdgpu_ttm_bo_eviction_valuable(struct ttm_buffer_object *bo,
1394                                             const struct ttm_place *place)
1395 {
1396         unsigned long num_pages = bo->mem.num_pages;
1397         struct amdgpu_res_cursor cursor;
1398         struct dma_resv_list *flist;
1399         struct dma_fence *f;
1400         int i;
1401
1402         if (bo->type == ttm_bo_type_kernel &&
1403             !amdgpu_vm_evictable(ttm_to_amdgpu_bo(bo)))
1404                 return false;
1405
1406         /* If bo is a KFD BO, check if the bo belongs to the current process.
1407          * If true, then return false as any KFD process needs all its BOs to
1408          * be resident to run successfully
1409          */
1410         flist = dma_resv_get_list(bo->base.resv);
1411         if (flist) {
1412                 for (i = 0; i < flist->shared_count; ++i) {
1413                         f = rcu_dereference_protected(flist->shared[i],
1414                                 dma_resv_held(bo->base.resv));
1415                         if (amdkfd_fence_check_mm(f, current->mm))
1416                                 return false;
1417                 }
1418         }
1419
1420         switch (bo->mem.mem_type) {
1421         case TTM_PL_TT:
1422                 if (amdgpu_bo_is_amdgpu_bo(bo) &&
1423                     amdgpu_bo_encrypted(ttm_to_amdgpu_bo(bo)))
1424                         return false;
1425                 return true;
1426
1427         case TTM_PL_VRAM:
1428                 /* Check each drm MM node individually */
1429                 amdgpu_res_first(&bo->mem, 0, (u64)num_pages << PAGE_SHIFT,
1430                                  &cursor);
1431                 while (cursor.remaining) {
1432                         if (place->fpfn < PFN_DOWN(cursor.start + cursor.size)
1433                             && !(place->lpfn &&
1434                                  place->lpfn <= PFN_DOWN(cursor.start)))
1435                                 return true;
1436
1437                         amdgpu_res_next(&cursor, cursor.size);
1438                 }
1439                 return false;
1440
1441         default:
1442                 break;
1443         }
1444
1445         return ttm_bo_eviction_valuable(bo, place);
1446 }
1447
1448 /**
1449  * amdgpu_ttm_access_memory - Read or Write memory that backs a buffer object.
1450  *
1451  * @bo:  The buffer object to read/write
1452  * @offset:  Offset into buffer object
1453  * @buf:  Secondary buffer to write/read from
1454  * @len: Length in bytes of access
1455  * @write:  true if writing
1456  *
1457  * This is used to access VRAM that backs a buffer object via MMIO
1458  * access for debugging purposes.
1459  */
1460 static int amdgpu_ttm_access_memory(struct ttm_buffer_object *bo,
1461                                     unsigned long offset, void *buf, int len,
1462                                     int write)
1463 {
1464         struct amdgpu_bo *abo = ttm_to_amdgpu_bo(bo);
1465         struct amdgpu_device *adev = amdgpu_ttm_adev(abo->tbo.bdev);
1466         struct amdgpu_res_cursor cursor;
1467         unsigned long flags;
1468         uint32_t value = 0;
1469         int ret = 0;
1470
1471         if (bo->mem.mem_type != TTM_PL_VRAM)
1472                 return -EIO;
1473
1474         amdgpu_res_first(&bo->mem, offset, len, &cursor);
1475         while (cursor.remaining) {
1476                 uint64_t aligned_pos = cursor.start & ~(uint64_t)3;
1477                 uint64_t bytes = 4 - (cursor.start & 3);
1478                 uint32_t shift = (cursor.start & 3) * 8;
1479                 uint32_t mask = 0xffffffff << shift;
1480
1481                 if (cursor.size < bytes) {
1482                         mask &= 0xffffffff >> (bytes - cursor.size) * 8;
1483                         bytes = cursor.size;
1484                 }
1485
1486                 if (mask != 0xffffffff) {
1487                         spin_lock_irqsave(&adev->mmio_idx_lock, flags);
1488                         WREG32_NO_KIQ(mmMM_INDEX, ((uint32_t)aligned_pos) | 0x80000000);
1489                         WREG32_NO_KIQ(mmMM_INDEX_HI, aligned_pos >> 31);
1490                         value = RREG32_NO_KIQ(mmMM_DATA);
1491                         if (write) {
1492                                 value &= ~mask;
1493                                 value |= (*(uint32_t *)buf << shift) & mask;
1494                                 WREG32_NO_KIQ(mmMM_DATA, value);
1495                         }
1496                         spin_unlock_irqrestore(&adev->mmio_idx_lock, flags);
1497                         if (!write) {
1498                                 value = (value & mask) >> shift;
1499                                 memcpy(buf, &value, bytes);
1500                         }
1501                 } else {
1502                         bytes = cursor.size & ~0x3ULL;
1503                         amdgpu_device_vram_access(adev, cursor.start,
1504                                                   (uint32_t *)buf, bytes,
1505                                                   write);
1506                 }
1507
1508                 ret += bytes;
1509                 buf = (uint8_t *)buf + bytes;
1510                 amdgpu_res_next(&cursor, bytes);
1511         }
1512
1513         return ret;
1514 }
1515
1516 static void
1517 amdgpu_bo_delete_mem_notify(struct ttm_buffer_object *bo)
1518 {
1519         amdgpu_bo_move_notify(bo, false, NULL);
1520 }
1521
1522 static struct ttm_device_funcs amdgpu_bo_driver = {
1523         .ttm_tt_create = &amdgpu_ttm_tt_create,
1524         .ttm_tt_populate = &amdgpu_ttm_tt_populate,
1525         .ttm_tt_unpopulate = &amdgpu_ttm_tt_unpopulate,
1526         .ttm_tt_destroy = &amdgpu_ttm_backend_destroy,
1527         .eviction_valuable = amdgpu_ttm_bo_eviction_valuable,
1528         .evict_flags = &amdgpu_evict_flags,
1529         .move = &amdgpu_bo_move,
1530         .verify_access = &amdgpu_verify_access,
1531         .delete_mem_notify = &amdgpu_bo_delete_mem_notify,
1532         .release_notify = &amdgpu_bo_release_notify,
1533         .io_mem_reserve = &amdgpu_ttm_io_mem_reserve,
1534         .io_mem_pfn = amdgpu_ttm_io_mem_pfn,
1535         .access_memory = &amdgpu_ttm_access_memory,
1536         .del_from_lru_notify = &amdgpu_vm_del_from_lru_notify
1537 };
1538
1539 /*
1540  * Firmware Reservation functions
1541  */
1542 /**
1543  * amdgpu_ttm_fw_reserve_vram_fini - free fw reserved vram
1544  *
1545  * @adev: amdgpu_device pointer
1546  *
1547  * free fw reserved vram if it has been reserved.
1548  */
1549 static void amdgpu_ttm_fw_reserve_vram_fini(struct amdgpu_device *adev)
1550 {
1551         amdgpu_bo_free_kernel(&adev->mman.fw_vram_usage_reserved_bo,
1552                 NULL, &adev->mman.fw_vram_usage_va);
1553 }
1554
1555 /**
1556  * amdgpu_ttm_fw_reserve_vram_init - create bo vram reservation from fw
1557  *
1558  * @adev: amdgpu_device pointer
1559  *
1560  * create bo vram reservation from fw.
1561  */
1562 static int amdgpu_ttm_fw_reserve_vram_init(struct amdgpu_device *adev)
1563 {
1564         uint64_t vram_size = adev->gmc.visible_vram_size;
1565
1566         adev->mman.fw_vram_usage_va = NULL;
1567         adev->mman.fw_vram_usage_reserved_bo = NULL;
1568
1569         if (adev->mman.fw_vram_usage_size == 0 ||
1570             adev->mman.fw_vram_usage_size > vram_size)
1571                 return 0;
1572
1573         return amdgpu_bo_create_kernel_at(adev,
1574                                           adev->mman.fw_vram_usage_start_offset,
1575                                           adev->mman.fw_vram_usage_size,
1576                                           AMDGPU_GEM_DOMAIN_VRAM,
1577                                           &adev->mman.fw_vram_usage_reserved_bo,
1578                                           &adev->mman.fw_vram_usage_va);
1579 }
1580
1581 /*
1582  * Memoy training reservation functions
1583  */
1584
1585 /**
1586  * amdgpu_ttm_training_reserve_vram_fini - free memory training reserved vram
1587  *
1588  * @adev: amdgpu_device pointer
1589  *
1590  * free memory training reserved vram if it has been reserved.
1591  */
1592 static int amdgpu_ttm_training_reserve_vram_fini(struct amdgpu_device *adev)
1593 {
1594         struct psp_memory_training_context *ctx = &adev->psp.mem_train_ctx;
1595
1596         ctx->init = PSP_MEM_TRAIN_NOT_SUPPORT;
1597         amdgpu_bo_free_kernel(&ctx->c2p_bo, NULL, NULL);
1598         ctx->c2p_bo = NULL;
1599
1600         return 0;
1601 }
1602
1603 static void amdgpu_ttm_training_data_block_init(struct amdgpu_device *adev)
1604 {
1605         struct psp_memory_training_context *ctx = &adev->psp.mem_train_ctx;
1606
1607         memset(ctx, 0, sizeof(*ctx));
1608
1609         ctx->c2p_train_data_offset =
1610                 ALIGN((adev->gmc.mc_vram_size - adev->mman.discovery_tmr_size - SZ_1M), SZ_1M);
1611         ctx->p2c_train_data_offset =
1612                 (adev->gmc.mc_vram_size - GDDR6_MEM_TRAINING_OFFSET);
1613         ctx->train_data_size =
1614                 GDDR6_MEM_TRAINING_DATA_SIZE_IN_BYTES;
1615
1616         DRM_DEBUG("train_data_size:%llx,p2c_train_data_offset:%llx,c2p_train_data_offset:%llx.\n",
1617                         ctx->train_data_size,
1618                         ctx->p2c_train_data_offset,
1619                         ctx->c2p_train_data_offset);
1620 }
1621
1622 /*
1623  * reserve TMR memory at the top of VRAM which holds
1624  * IP Discovery data and is protected by PSP.
1625  */
1626 static int amdgpu_ttm_reserve_tmr(struct amdgpu_device *adev)
1627 {
1628         int ret;
1629         struct psp_memory_training_context *ctx = &adev->psp.mem_train_ctx;
1630         bool mem_train_support = false;
1631
1632         if (!amdgpu_sriov_vf(adev)) {
1633                 ret = amdgpu_mem_train_support(adev);
1634                 if (ret == 1)
1635                         mem_train_support = true;
1636                 else if (ret == -1)
1637                         return -EINVAL;
1638                 else
1639                         DRM_DEBUG("memory training does not support!\n");
1640         }
1641
1642         /*
1643          * Query reserved tmr size through atom firmwareinfo for Sienna_Cichlid and onwards for all
1644          * the use cases (IP discovery/G6 memory training/profiling/diagnostic data.etc)
1645          *
1646          * Otherwise, fallback to legacy approach to check and reserve tmr block for ip
1647          * discovery data and G6 memory training data respectively
1648          */
1649         adev->mman.discovery_tmr_size =
1650                 amdgpu_atomfirmware_get_fw_reserved_fb_size(adev);
1651         if (!adev->mman.discovery_tmr_size)
1652                 adev->mman.discovery_tmr_size = DISCOVERY_TMR_OFFSET;
1653
1654         if (mem_train_support) {
1655                 /* reserve vram for mem train according to TMR location */
1656                 amdgpu_ttm_training_data_block_init(adev);
1657                 ret = amdgpu_bo_create_kernel_at(adev,
1658                                          ctx->c2p_train_data_offset,
1659                                          ctx->train_data_size,
1660                                          AMDGPU_GEM_DOMAIN_VRAM,
1661                                          &ctx->c2p_bo,
1662                                          NULL);
1663                 if (ret) {
1664                         DRM_ERROR("alloc c2p_bo failed(%d)!\n", ret);
1665                         amdgpu_ttm_training_reserve_vram_fini(adev);
1666                         return ret;
1667                 }
1668                 ctx->init = PSP_MEM_TRAIN_RESERVE_SUCCESS;
1669         }
1670
1671         ret = amdgpu_bo_create_kernel_at(adev,
1672                                 adev->gmc.real_vram_size - adev->mman.discovery_tmr_size,
1673                                 adev->mman.discovery_tmr_size,
1674                                 AMDGPU_GEM_DOMAIN_VRAM,
1675                                 &adev->mman.discovery_memory,
1676                                 NULL);
1677         if (ret) {
1678                 DRM_ERROR("alloc tmr failed(%d)!\n", ret);
1679                 amdgpu_bo_free_kernel(&adev->mman.discovery_memory, NULL, NULL);
1680                 return ret;
1681         }
1682
1683         return 0;
1684 }
1685
1686 /*
1687  * amdgpu_ttm_init - Init the memory management (ttm) as well as various
1688  * gtt/vram related fields.
1689  *
1690  * This initializes all of the memory space pools that the TTM layer
1691  * will need such as the GTT space (system memory mapped to the device),
1692  * VRAM (on-board memory), and on-chip memories (GDS, GWS, OA) which
1693  * can be mapped per VMID.
1694  */
1695 int amdgpu_ttm_init(struct amdgpu_device *adev)
1696 {
1697         uint64_t gtt_size;
1698         int r;
1699         u64 vis_vram_limit;
1700
1701         mutex_init(&adev->mman.gtt_window_lock);
1702
1703         /* No others user of address space so set it to 0 */
1704         r = ttm_device_init(&adev->mman.bdev, &amdgpu_bo_driver, adev->dev,
1705                                adev_to_drm(adev)->anon_inode->i_mapping,
1706                                adev_to_drm(adev)->vma_offset_manager,
1707                                adev->need_swiotlb,
1708                                dma_addressing_limited(adev->dev));
1709         if (r) {
1710                 DRM_ERROR("failed initializing buffer object driver(%d).\n", r);
1711                 return r;
1712         }
1713         adev->mman.initialized = true;
1714
1715         /* Initialize VRAM pool with all of VRAM divided into pages */
1716         r = amdgpu_vram_mgr_init(adev);
1717         if (r) {
1718                 DRM_ERROR("Failed initializing VRAM heap.\n");
1719                 return r;
1720         }
1721
1722         /* Reduce size of CPU-visible VRAM if requested */
1723         vis_vram_limit = (u64)amdgpu_vis_vram_limit * 1024 * 1024;
1724         if (amdgpu_vis_vram_limit > 0 &&
1725             vis_vram_limit <= adev->gmc.visible_vram_size)
1726                 adev->gmc.visible_vram_size = vis_vram_limit;
1727
1728         /* Change the size here instead of the init above so only lpfn is affected */
1729         amdgpu_ttm_set_buffer_funcs_status(adev, false);
1730 #ifdef CONFIG_64BIT
1731 #ifdef CONFIG_X86
1732         if (adev->gmc.xgmi.connected_to_cpu)
1733                 adev->mman.aper_base_kaddr = ioremap_cache(adev->gmc.aper_base,
1734                                 adev->gmc.visible_vram_size);
1735
1736         else
1737 #endif
1738                 adev->mman.aper_base_kaddr = ioremap_wc(adev->gmc.aper_base,
1739                                 adev->gmc.visible_vram_size);
1740 #endif
1741
1742         /*
1743          *The reserved vram for firmware must be pinned to the specified
1744          *place on the VRAM, so reserve it early.
1745          */
1746         r = amdgpu_ttm_fw_reserve_vram_init(adev);
1747         if (r) {
1748                 return r;
1749         }
1750
1751         /*
1752          * only NAVI10 and onwards ASIC support for IP discovery.
1753          * If IP discovery enabled, a block of memory should be
1754          * reserved for IP discovey.
1755          */
1756         if (adev->mman.discovery_bin) {
1757                 r = amdgpu_ttm_reserve_tmr(adev);
1758                 if (r)
1759                         return r;
1760         }
1761
1762         /* allocate memory as required for VGA
1763          * This is used for VGA emulation and pre-OS scanout buffers to
1764          * avoid display artifacts while transitioning between pre-OS
1765          * and driver.  */
1766         r = amdgpu_bo_create_kernel_at(adev, 0, adev->mman.stolen_vga_size,
1767                                        AMDGPU_GEM_DOMAIN_VRAM,
1768                                        &adev->mman.stolen_vga_memory,
1769                                        NULL);
1770         if (r)
1771                 return r;
1772         r = amdgpu_bo_create_kernel_at(adev, adev->mman.stolen_vga_size,
1773                                        adev->mman.stolen_extended_size,
1774                                        AMDGPU_GEM_DOMAIN_VRAM,
1775                                        &adev->mman.stolen_extended_memory,
1776                                        NULL);
1777         if (r)
1778                 return r;
1779
1780         DRM_INFO("amdgpu: %uM of VRAM memory ready\n",
1781                  (unsigned) (adev->gmc.real_vram_size / (1024 * 1024)));
1782
1783         /* Compute GTT size, either bsaed on 3/4th the size of RAM size
1784          * or whatever the user passed on module init */
1785         if (amdgpu_gtt_size == -1) {
1786                 struct sysinfo si;
1787
1788                 si_meminfo(&si);
1789                 gtt_size = min(max((AMDGPU_DEFAULT_GTT_SIZE_MB << 20),
1790                                adev->gmc.mc_vram_size),
1791                                ((uint64_t)si.totalram * si.mem_unit * 3/4));
1792         }
1793         else
1794                 gtt_size = (uint64_t)amdgpu_gtt_size << 20;
1795
1796         /* Initialize GTT memory pool */
1797         r = amdgpu_gtt_mgr_init(adev, gtt_size);
1798         if (r) {
1799                 DRM_ERROR("Failed initializing GTT heap.\n");
1800                 return r;
1801         }
1802         DRM_INFO("amdgpu: %uM of GTT memory ready.\n",
1803                  (unsigned)(gtt_size / (1024 * 1024)));
1804
1805         /* Initialize various on-chip memory pools */
1806         r = amdgpu_ttm_init_on_chip(adev, AMDGPU_PL_GDS, adev->gds.gds_size);
1807         if (r) {
1808                 DRM_ERROR("Failed initializing GDS heap.\n");
1809                 return r;
1810         }
1811
1812         r = amdgpu_ttm_init_on_chip(adev, AMDGPU_PL_GWS, adev->gds.gws_size);
1813         if (r) {
1814                 DRM_ERROR("Failed initializing gws heap.\n");
1815                 return r;
1816         }
1817
1818         r = amdgpu_ttm_init_on_chip(adev, AMDGPU_PL_OA, adev->gds.oa_size);
1819         if (r) {
1820                 DRM_ERROR("Failed initializing oa heap.\n");
1821                 return r;
1822         }
1823
1824         return 0;
1825 }
1826
1827 /*
1828  * amdgpu_ttm_fini - De-initialize the TTM memory pools
1829  */
1830 void amdgpu_ttm_fini(struct amdgpu_device *adev)
1831 {
1832         if (!adev->mman.initialized)
1833                 return;
1834
1835         amdgpu_ttm_training_reserve_vram_fini(adev);
1836         /* return the stolen vga memory back to VRAM */
1837         amdgpu_bo_free_kernel(&adev->mman.stolen_vga_memory, NULL, NULL);
1838         amdgpu_bo_free_kernel(&adev->mman.stolen_extended_memory, NULL, NULL);
1839         /* return the IP Discovery TMR memory back to VRAM */
1840         amdgpu_bo_free_kernel(&adev->mman.discovery_memory, NULL, NULL);
1841         amdgpu_ttm_fw_reserve_vram_fini(adev);
1842
1843         if (adev->mman.aper_base_kaddr)
1844                 iounmap(adev->mman.aper_base_kaddr);
1845         adev->mman.aper_base_kaddr = NULL;
1846
1847         amdgpu_vram_mgr_fini(adev);
1848         amdgpu_gtt_mgr_fini(adev);
1849         ttm_range_man_fini(&adev->mman.bdev, AMDGPU_PL_GDS);
1850         ttm_range_man_fini(&adev->mman.bdev, AMDGPU_PL_GWS);
1851         ttm_range_man_fini(&adev->mman.bdev, AMDGPU_PL_OA);
1852         ttm_device_fini(&adev->mman.bdev);
1853         adev->mman.initialized = false;
1854         DRM_INFO("amdgpu: ttm finalized\n");
1855 }
1856
1857 /**
1858  * amdgpu_ttm_set_buffer_funcs_status - enable/disable use of buffer functions
1859  *
1860  * @adev: amdgpu_device pointer
1861  * @enable: true when we can use buffer functions.
1862  *
1863  * Enable/disable use of buffer functions during suspend/resume. This should
1864  * only be called at bootup or when userspace isn't running.
1865  */
1866 void amdgpu_ttm_set_buffer_funcs_status(struct amdgpu_device *adev, bool enable)
1867 {
1868         struct ttm_resource_manager *man = ttm_manager_type(&adev->mman.bdev, TTM_PL_VRAM);
1869         uint64_t size;
1870         int r;
1871
1872         if (!adev->mman.initialized || amdgpu_in_reset(adev) ||
1873             adev->mman.buffer_funcs_enabled == enable)
1874                 return;
1875
1876         if (enable) {
1877                 struct amdgpu_ring *ring;
1878                 struct drm_gpu_scheduler *sched;
1879
1880                 ring = adev->mman.buffer_funcs_ring;
1881                 sched = &ring->sched;
1882                 r = drm_sched_entity_init(&adev->mman.entity,
1883                                           DRM_SCHED_PRIORITY_KERNEL, &sched,
1884                                           1, NULL);
1885                 if (r) {
1886                         DRM_ERROR("Failed setting up TTM BO move entity (%d)\n",
1887                                   r);
1888                         return;
1889                 }
1890         } else {
1891                 drm_sched_entity_destroy(&adev->mman.entity);
1892                 dma_fence_put(man->move);
1893                 man->move = NULL;
1894         }
1895
1896         /* this just adjusts TTM size idea, which sets lpfn to the correct value */
1897         if (enable)
1898                 size = adev->gmc.real_vram_size;
1899         else
1900                 size = adev->gmc.visible_vram_size;
1901         man->size = size >> PAGE_SHIFT;
1902         adev->mman.buffer_funcs_enabled = enable;
1903 }
1904
1905 static vm_fault_t amdgpu_ttm_fault(struct vm_fault *vmf)
1906 {
1907         struct ttm_buffer_object *bo = vmf->vma->vm_private_data;
1908         vm_fault_t ret;
1909
1910         ret = ttm_bo_vm_reserve(bo, vmf);
1911         if (ret)
1912                 return ret;
1913
1914         ret = amdgpu_bo_fault_reserve_notify(bo);
1915         if (ret)
1916                 goto unlock;
1917
1918         ret = ttm_bo_vm_fault_reserved(vmf, vmf->vma->vm_page_prot,
1919                                        TTM_BO_VM_NUM_PREFAULT, 1);
1920         if (ret == VM_FAULT_RETRY && !(vmf->flags & FAULT_FLAG_RETRY_NOWAIT))
1921                 return ret;
1922
1923 unlock:
1924         dma_resv_unlock(bo->base.resv);
1925         return ret;
1926 }
1927
1928 static const struct vm_operations_struct amdgpu_ttm_vm_ops = {
1929         .fault = amdgpu_ttm_fault,
1930         .open = ttm_bo_vm_open,
1931         .close = ttm_bo_vm_close,
1932         .access = ttm_bo_vm_access
1933 };
1934
1935 int amdgpu_mmap(struct file *filp, struct vm_area_struct *vma)
1936 {
1937         struct drm_file *file_priv = filp->private_data;
1938         struct amdgpu_device *adev = drm_to_adev(file_priv->minor->dev);
1939         int r;
1940
1941         r = ttm_bo_mmap(filp, vma, &adev->mman.bdev);
1942         if (unlikely(r != 0))
1943                 return r;
1944
1945         vma->vm_ops = &amdgpu_ttm_vm_ops;
1946         return 0;
1947 }
1948
1949 int amdgpu_copy_buffer(struct amdgpu_ring *ring, uint64_t src_offset,
1950                        uint64_t dst_offset, uint32_t byte_count,
1951                        struct dma_resv *resv,
1952                        struct dma_fence **fence, bool direct_submit,
1953                        bool vm_needs_flush, bool tmz)
1954 {
1955         enum amdgpu_ib_pool_type pool = direct_submit ? AMDGPU_IB_POOL_DIRECT :
1956                 AMDGPU_IB_POOL_DELAYED;
1957         struct amdgpu_device *adev = ring->adev;
1958         struct amdgpu_job *job;
1959
1960         uint32_t max_bytes;
1961         unsigned num_loops, num_dw;
1962         unsigned i;
1963         int r;
1964
1965         if (direct_submit && !ring->sched.ready) {
1966                 DRM_ERROR("Trying to move memory with ring turned off.\n");
1967                 return -EINVAL;
1968         }
1969
1970         max_bytes = adev->mman.buffer_funcs->copy_max_bytes;
1971         num_loops = DIV_ROUND_UP(byte_count, max_bytes);
1972         num_dw = ALIGN(num_loops * adev->mman.buffer_funcs->copy_num_dw, 8);
1973
1974         r = amdgpu_job_alloc_with_ib(adev, num_dw * 4, pool, &job);
1975         if (r)
1976                 return r;
1977
1978         if (vm_needs_flush) {
1979                 job->vm_pd_addr = amdgpu_gmc_pd_addr(adev->gmc.pdb0_bo ?
1980                                         adev->gmc.pdb0_bo : adev->gart.bo);
1981                 job->vm_needs_flush = true;
1982         }
1983         if (resv) {
1984                 r = amdgpu_sync_resv(adev, &job->sync, resv,
1985                                      AMDGPU_SYNC_ALWAYS,
1986                                      AMDGPU_FENCE_OWNER_UNDEFINED);
1987                 if (r) {
1988                         DRM_ERROR("sync failed (%d).\n", r);
1989                         goto error_free;
1990                 }
1991         }
1992
1993         for (i = 0; i < num_loops; i++) {
1994                 uint32_t cur_size_in_bytes = min(byte_count, max_bytes);
1995
1996                 amdgpu_emit_copy_buffer(adev, &job->ibs[0], src_offset,
1997                                         dst_offset, cur_size_in_bytes, tmz);
1998
1999                 src_offset += cur_size_in_bytes;
2000                 dst_offset += cur_size_in_bytes;
2001                 byte_count -= cur_size_in_bytes;
2002         }
2003
2004         amdgpu_ring_pad_ib(ring, &job->ibs[0]);
2005         WARN_ON(job->ibs[0].length_dw > num_dw);
2006         if (direct_submit)
2007                 r = amdgpu_job_submit_direct(job, ring, fence);
2008         else
2009                 r = amdgpu_job_submit(job, &adev->mman.entity,
2010                                       AMDGPU_FENCE_OWNER_UNDEFINED, fence);
2011         if (r)
2012                 goto error_free;
2013
2014         return r;
2015
2016 error_free:
2017         amdgpu_job_free(job);
2018         DRM_ERROR("Error scheduling IBs (%d)\n", r);
2019         return r;
2020 }
2021
2022 int amdgpu_fill_buffer(struct amdgpu_bo *bo,
2023                        uint32_t src_data,
2024                        struct dma_resv *resv,
2025                        struct dma_fence **fence)
2026 {
2027         struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
2028         uint32_t max_bytes = adev->mman.buffer_funcs->fill_max_bytes;
2029         struct amdgpu_ring *ring = adev->mman.buffer_funcs_ring;
2030
2031         struct amdgpu_res_cursor cursor;
2032         unsigned int num_loops, num_dw;
2033         uint64_t num_bytes;
2034
2035         struct amdgpu_job *job;
2036         int r;
2037
2038         if (!adev->mman.buffer_funcs_enabled) {
2039                 DRM_ERROR("Trying to clear memory with ring turned off.\n");
2040                 return -EINVAL;
2041         }
2042
2043         if (bo->tbo.mem.mem_type == TTM_PL_TT) {
2044                 r = amdgpu_ttm_alloc_gart(&bo->tbo);
2045                 if (r)
2046                         return r;
2047         }
2048
2049         num_bytes = bo->tbo.mem.num_pages << PAGE_SHIFT;
2050         num_loops = 0;
2051
2052         amdgpu_res_first(&bo->tbo.mem, 0, num_bytes, &cursor);
2053         while (cursor.remaining) {
2054                 num_loops += DIV_ROUND_UP_ULL(cursor.size, max_bytes);
2055                 amdgpu_res_next(&cursor, cursor.size);
2056         }
2057         num_dw = num_loops * adev->mman.buffer_funcs->fill_num_dw;
2058
2059         /* for IB padding */
2060         num_dw += 64;
2061
2062         r = amdgpu_job_alloc_with_ib(adev, num_dw * 4, AMDGPU_IB_POOL_DELAYED,
2063                                      &job);
2064         if (r)
2065                 return r;
2066
2067         if (resv) {
2068                 r = amdgpu_sync_resv(adev, &job->sync, resv,
2069                                      AMDGPU_SYNC_ALWAYS,
2070                                      AMDGPU_FENCE_OWNER_UNDEFINED);
2071                 if (r) {
2072                         DRM_ERROR("sync failed (%d).\n", r);
2073                         goto error_free;
2074                 }
2075         }
2076
2077         amdgpu_res_first(&bo->tbo.mem, 0, num_bytes, &cursor);
2078         while (cursor.remaining) {
2079                 uint32_t cur_size = min_t(uint64_t, cursor.size, max_bytes);
2080                 uint64_t dst_addr = cursor.start;
2081
2082                 dst_addr += amdgpu_ttm_domain_start(adev, bo->tbo.mem.mem_type);
2083                 amdgpu_emit_fill_buffer(adev, &job->ibs[0], src_data, dst_addr,
2084                                         cur_size);
2085
2086                 amdgpu_res_next(&cursor, cur_size);
2087         }
2088
2089         amdgpu_ring_pad_ib(ring, &job->ibs[0]);
2090         WARN_ON(job->ibs[0].length_dw > num_dw);
2091         r = amdgpu_job_submit(job, &adev->mman.entity,
2092                               AMDGPU_FENCE_OWNER_UNDEFINED, fence);
2093         if (r)
2094                 goto error_free;
2095
2096         return 0;
2097
2098 error_free:
2099         amdgpu_job_free(job);
2100         return r;
2101 }
2102
2103 #if defined(CONFIG_DEBUG_FS)
2104
2105 static int amdgpu_mm_vram_table_show(struct seq_file *m, void *unused)
2106 {
2107         struct amdgpu_device *adev = (struct amdgpu_device *)m->private;
2108         struct ttm_resource_manager *man = ttm_manager_type(&adev->mman.bdev,
2109                                                             TTM_PL_VRAM);
2110         struct drm_printer p = drm_seq_file_printer(m);
2111
2112         man->func->debug(man, &p);
2113         return 0;
2114 }
2115
2116 static int amdgpu_ttm_page_pool_show(struct seq_file *m, void *unused)
2117 {
2118         struct amdgpu_device *adev = (struct amdgpu_device *)m->private;
2119
2120         return ttm_pool_debugfs(&adev->mman.bdev.pool, m);
2121 }
2122
2123 static int amdgpu_mm_tt_table_show(struct seq_file *m, void *unused)
2124 {
2125         struct amdgpu_device *adev = (struct amdgpu_device *)m->private;
2126         struct ttm_resource_manager *man = ttm_manager_type(&adev->mman.bdev,
2127                                                             TTM_PL_TT);
2128         struct drm_printer p = drm_seq_file_printer(m);
2129
2130         man->func->debug(man, &p);
2131         return 0;
2132 }
2133
2134 static int amdgpu_mm_gds_table_show(struct seq_file *m, void *unused)
2135 {
2136         struct amdgpu_device *adev = (struct amdgpu_device *)m->private;
2137         struct ttm_resource_manager *man = ttm_manager_type(&adev->mman.bdev,
2138                                                             AMDGPU_PL_GDS);
2139         struct drm_printer p = drm_seq_file_printer(m);
2140
2141         man->func->debug(man, &p);
2142         return 0;
2143 }
2144
2145 static int amdgpu_mm_gws_table_show(struct seq_file *m, void *unused)
2146 {
2147         struct amdgpu_device *adev = (struct amdgpu_device *)m->private;
2148         struct ttm_resource_manager *man = ttm_manager_type(&adev->mman.bdev,
2149                                                             AMDGPU_PL_GWS);
2150         struct drm_printer p = drm_seq_file_printer(m);
2151
2152         man->func->debug(man, &p);
2153         return 0;
2154 }
2155
2156 static int amdgpu_mm_oa_table_show(struct seq_file *m, void *unused)
2157 {
2158         struct amdgpu_device *adev = (struct amdgpu_device *)m->private;
2159         struct ttm_resource_manager *man = ttm_manager_type(&adev->mman.bdev,
2160                                                             AMDGPU_PL_OA);
2161         struct drm_printer p = drm_seq_file_printer(m);
2162
2163         man->func->debug(man, &p);
2164         return 0;
2165 }
2166
2167 DEFINE_SHOW_ATTRIBUTE(amdgpu_mm_vram_table);
2168 DEFINE_SHOW_ATTRIBUTE(amdgpu_mm_tt_table);
2169 DEFINE_SHOW_ATTRIBUTE(amdgpu_mm_gds_table);
2170 DEFINE_SHOW_ATTRIBUTE(amdgpu_mm_gws_table);
2171 DEFINE_SHOW_ATTRIBUTE(amdgpu_mm_oa_table);
2172 DEFINE_SHOW_ATTRIBUTE(amdgpu_ttm_page_pool);
2173
2174 /*
2175  * amdgpu_ttm_vram_read - Linear read access to VRAM
2176  *
2177  * Accesses VRAM via MMIO for debugging purposes.
2178  */
2179 static ssize_t amdgpu_ttm_vram_read(struct file *f, char __user *buf,
2180                                     size_t size, loff_t *pos)
2181 {
2182         struct amdgpu_device *adev = file_inode(f)->i_private;
2183         ssize_t result = 0;
2184
2185         if (size & 0x3 || *pos & 0x3)
2186                 return -EINVAL;
2187
2188         if (*pos >= adev->gmc.mc_vram_size)
2189                 return -ENXIO;
2190
2191         size = min(size, (size_t)(adev->gmc.mc_vram_size - *pos));
2192         while (size) {
2193                 size_t bytes = min(size, AMDGPU_TTM_VRAM_MAX_DW_READ * 4);
2194                 uint32_t value[AMDGPU_TTM_VRAM_MAX_DW_READ];
2195
2196                 amdgpu_device_vram_access(adev, *pos, value, bytes, false);
2197                 if (copy_to_user(buf, value, bytes))
2198                         return -EFAULT;
2199
2200                 result += bytes;
2201                 buf += bytes;
2202                 *pos += bytes;
2203                 size -= bytes;
2204         }
2205
2206         return result;
2207 }
2208
2209 /*
2210  * amdgpu_ttm_vram_write - Linear write access to VRAM
2211  *
2212  * Accesses VRAM via MMIO for debugging purposes.
2213  */
2214 static ssize_t amdgpu_ttm_vram_write(struct file *f, const char __user *buf,
2215                                     size_t size, loff_t *pos)
2216 {
2217         struct amdgpu_device *adev = file_inode(f)->i_private;
2218         ssize_t result = 0;
2219         int r;
2220
2221         if (size & 0x3 || *pos & 0x3)
2222                 return -EINVAL;
2223
2224         if (*pos >= adev->gmc.mc_vram_size)
2225                 return -ENXIO;
2226
2227         while (size) {
2228                 unsigned long flags;
2229                 uint32_t value;
2230
2231                 if (*pos >= adev->gmc.mc_vram_size)
2232                         return result;
2233
2234                 r = get_user(value, (uint32_t *)buf);
2235                 if (r)
2236                         return r;
2237
2238                 spin_lock_irqsave(&adev->mmio_idx_lock, flags);
2239                 WREG32_NO_KIQ(mmMM_INDEX, ((uint32_t)*pos) | 0x80000000);
2240                 WREG32_NO_KIQ(mmMM_INDEX_HI, *pos >> 31);
2241                 WREG32_NO_KIQ(mmMM_DATA, value);
2242                 spin_unlock_irqrestore(&adev->mmio_idx_lock, flags);
2243
2244                 result += 4;
2245                 buf += 4;
2246                 *pos += 4;
2247                 size -= 4;
2248         }
2249
2250         return result;
2251 }
2252
2253 static const struct file_operations amdgpu_ttm_vram_fops = {
2254         .owner = THIS_MODULE,
2255         .read = amdgpu_ttm_vram_read,
2256         .write = amdgpu_ttm_vram_write,
2257         .llseek = default_llseek,
2258 };
2259
2260 /*
2261  * amdgpu_iomem_read - Virtual read access to GPU mapped memory
2262  *
2263  * This function is used to read memory that has been mapped to the
2264  * GPU and the known addresses are not physical addresses but instead
2265  * bus addresses (e.g., what you'd put in an IB or ring buffer).
2266  */
2267 static ssize_t amdgpu_iomem_read(struct file *f, char __user *buf,
2268                                  size_t size, loff_t *pos)
2269 {
2270         struct amdgpu_device *adev = file_inode(f)->i_private;
2271         struct iommu_domain *dom;
2272         ssize_t result = 0;
2273         int r;
2274
2275         /* retrieve the IOMMU domain if any for this device */
2276         dom = iommu_get_domain_for_dev(adev->dev);
2277
2278         while (size) {
2279                 phys_addr_t addr = *pos & PAGE_MASK;
2280                 loff_t off = *pos & ~PAGE_MASK;
2281                 size_t bytes = PAGE_SIZE - off;
2282                 unsigned long pfn;
2283                 struct page *p;
2284                 void *ptr;
2285
2286                 bytes = bytes < size ? bytes : size;
2287
2288                 /* Translate the bus address to a physical address.  If
2289                  * the domain is NULL it means there is no IOMMU active
2290                  * and the address translation is the identity
2291                  */
2292                 addr = dom ? iommu_iova_to_phys(dom, addr) : addr;
2293
2294                 pfn = addr >> PAGE_SHIFT;
2295                 if (!pfn_valid(pfn))
2296                         return -EPERM;
2297
2298                 p = pfn_to_page(pfn);
2299                 if (p->mapping != adev->mman.bdev.dev_mapping)
2300                         return -EPERM;
2301
2302                 ptr = kmap(p);
2303                 r = copy_to_user(buf, ptr + off, bytes);
2304                 kunmap(p);
2305                 if (r)
2306                         return -EFAULT;
2307
2308                 size -= bytes;
2309                 *pos += bytes;
2310                 result += bytes;
2311         }
2312
2313         return result;
2314 }
2315
2316 /*
2317  * amdgpu_iomem_write - Virtual write access to GPU mapped memory
2318  *
2319  * This function is used to write memory that has been mapped to the
2320  * GPU and the known addresses are not physical addresses but instead
2321  * bus addresses (e.g., what you'd put in an IB or ring buffer).
2322  */
2323 static ssize_t amdgpu_iomem_write(struct file *f, const char __user *buf,
2324                                  size_t size, loff_t *pos)
2325 {
2326         struct amdgpu_device *adev = file_inode(f)->i_private;
2327         struct iommu_domain *dom;
2328         ssize_t result = 0;
2329         int r;
2330
2331         dom = iommu_get_domain_for_dev(adev->dev);
2332
2333         while (size) {
2334                 phys_addr_t addr = *pos & PAGE_MASK;
2335                 loff_t off = *pos & ~PAGE_MASK;
2336                 size_t bytes = PAGE_SIZE - off;
2337                 unsigned long pfn;
2338                 struct page *p;
2339                 void *ptr;
2340
2341                 bytes = bytes < size ? bytes : size;
2342
2343                 addr = dom ? iommu_iova_to_phys(dom, addr) : addr;
2344
2345                 pfn = addr >> PAGE_SHIFT;
2346                 if (!pfn_valid(pfn))
2347                         return -EPERM;
2348
2349                 p = pfn_to_page(pfn);
2350                 if (p->mapping != adev->mman.bdev.dev_mapping)
2351                         return -EPERM;
2352
2353                 ptr = kmap(p);
2354                 r = copy_from_user(ptr + off, buf, bytes);
2355                 kunmap(p);
2356                 if (r)
2357                         return -EFAULT;
2358
2359                 size -= bytes;
2360                 *pos += bytes;
2361                 result += bytes;
2362         }
2363
2364         return result;
2365 }
2366
2367 static const struct file_operations amdgpu_ttm_iomem_fops = {
2368         .owner = THIS_MODULE,
2369         .read = amdgpu_iomem_read,
2370         .write = amdgpu_iomem_write,
2371         .llseek = default_llseek
2372 };
2373
2374 #endif
2375
2376 void amdgpu_ttm_debugfs_init(struct amdgpu_device *adev)
2377 {
2378 #if defined(CONFIG_DEBUG_FS)
2379         struct drm_minor *minor = adev_to_drm(adev)->primary;
2380         struct dentry *root = minor->debugfs_root;
2381
2382         debugfs_create_file_size("amdgpu_vram", 0444, root, adev,
2383                                  &amdgpu_ttm_vram_fops, adev->gmc.mc_vram_size);
2384         debugfs_create_file("amdgpu_iomem", 0444, root, adev,
2385                             &amdgpu_ttm_iomem_fops);
2386         debugfs_create_file("amdgpu_vram_mm", 0444, root, adev,
2387                             &amdgpu_mm_vram_table_fops);
2388         debugfs_create_file("amdgpu_gtt_mm", 0444, root, adev,
2389                             &amdgpu_mm_tt_table_fops);
2390         debugfs_create_file("amdgpu_gds_mm", 0444, root, adev,
2391                             &amdgpu_mm_gds_table_fops);
2392         debugfs_create_file("amdgpu_gws_mm", 0444, root, adev,
2393                             &amdgpu_mm_gws_table_fops);
2394         debugfs_create_file("amdgpu_oa_mm", 0444, root, adev,
2395                             &amdgpu_mm_oa_table_fops);
2396         debugfs_create_file("ttm_page_pool", 0444, root, adev,
2397                             &amdgpu_ttm_page_pool_fops);
2398 #endif
2399 }