drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c

   1 /*
   2  * Copyright 2009 Jerome Glisse.
   3  * All Rights Reserved.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the
   7  * "Software"), to deal in the Software without restriction, including
   8  * without limitation the rights to use, copy, modify, merge, publish,
   9  * distribute, sub license, and/or sell copies of the Software, and to
  10  * permit persons to whom the Software is furnished to do so, subject to
  11  * the following conditions:
  12  *
  13  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  14  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  15  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  16  * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
  17  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  18  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  19  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  20  *
  21  * The above copyright notice and this permission notice (including the
  22  * next paragraph) shall be included in all copies or substantial portions
  23  * of the Software.
  24  *
  25  */
  26 /*
  27  * Authors:
  28  *    Jerome Glisse <glisse@freedesktop.org>
  29  *    Thomas Hellstrom <thomas-at-tungstengraphics-dot-com>
  30  *    Dave Airlie
  31  */
  32
  33 #include <linux/dma-mapping.h>
  34 #include <linux/iommu.h>
  35 #include <linux/hmm.h>
  36 #include <linux/pagemap.h>
  37 #include <linux/sched/task.h>
  38 #include <linux/sched/mm.h>
  39 #include <linux/seq_file.h>
  40 #include <linux/slab.h>
  41 #include <linux/swap.h>
  42 #include <linux/swiotlb.h>
  43 #include <linux/dma-buf.h>
  44 #include <linux/sizes.h>
  45
  46 #include <drm/ttm/ttm_bo_api.h>
  47 #include <drm/ttm/ttm_bo_driver.h>
  48 #include <drm/ttm/ttm_placement.h>
  49 #include <drm/ttm/ttm_module.h>
  50 #include <drm/ttm/ttm_page_alloc.h>
  51
  52 #include <drm/drm_debugfs.h>
  53 #include <drm/amdgpu_drm.h>
  54
  55 #include "amdgpu.h"
  56 #include "amdgpu_object.h"
  57 #include "amdgpu_trace.h"
  58 #include "amdgpu_amdkfd.h"
  59 #include "amdgpu_sdma.h"
  60 #include "amdgpu_ras.h"
  61 #include "bif/bif_4_1_d.h"
  62
  63 #define AMDGPU_TTM_VRAM_MAX_DW_READ     (size_t)128
  64
  65
  66 /**
  67  * amdgpu_init_mem_type - Initialize a memory manager for a specific type of
  68  * memory request.
  69  *
  70  * @bdev: The TTM BO device object (contains a reference to amdgpu_device)
  71  * @type: The type of memory requested
  72  * @man: The memory type manager for each domain
  73  *
  74  * This is called by ttm_bo_init_mm() when a buffer object is being
  75  * initialized.
  76  */
  77 static int amdgpu_init_mem_type(struct ttm_bo_device *bdev, uint32_t type,
  78                                 struct ttm_mem_type_manager *man)
  79 {
  80         struct amdgpu_device *adev;
  81
  82         adev = amdgpu_ttm_adev(bdev);
  83
  84         switch (type) {
  85         case TTM_PL_SYSTEM:
  86                 /* System memory */
  87                 man->flags = TTM_MEMTYPE_FLAG_MAPPABLE;
  88                 man->available_caching = TTM_PL_MASK_CACHING;
  89                 man->default_caching = TTM_PL_FLAG_CACHED;
  90                 break;
  91         case TTM_PL_TT:
  92                 /* GTT memory  */
  93                 man->func = &amdgpu_gtt_mgr_func;
  94                 man->available_caching = TTM_PL_MASK_CACHING;
  95                 man->default_caching = TTM_PL_FLAG_CACHED;
  96                 man->flags = TTM_MEMTYPE_FLAG_MAPPABLE;
  97                 break;
  98         case TTM_PL_VRAM:
  99                 /* "On-card" video ram */
 100                 man->func = &amdgpu_vram_mgr_func;
 101                 man->flags = TTM_MEMTYPE_FLAG_FIXED |
 102                              TTM_MEMTYPE_FLAG_MAPPABLE;
 103                 man->available_caching = TTM_PL_FLAG_UNCACHED | TTM_PL_FLAG_WC;
 104                 man->default_caching = TTM_PL_FLAG_WC;
 105                 break;
 106         case AMDGPU_PL_GDS:
 107         case AMDGPU_PL_GWS:
 108         case AMDGPU_PL_OA:
 109                 /* On-chip GDS memory*/
 110                 man->func = &ttm_bo_manager_func;
 111                 man->flags = TTM_MEMTYPE_FLAG_FIXED;
 112                 man->available_caching = TTM_PL_FLAG_UNCACHED;
 113                 man->default_caching = TTM_PL_FLAG_UNCACHED;
 114                 break;
 115         default:
 116                 DRM_ERROR("Unsupported memory type %u\n", (unsigned)type);
 117                 return -EINVAL;
 118         }
 119         return 0;
 120 }
 121
 122 /**
 123  * amdgpu_evict_flags - Compute placement flags
 124  *
 125  * @bo: The buffer object to evict
 126  * @placement: Possible destination(s) for evicted BO
 127  *
 128  * Fill in placement data when ttm_bo_evict() is called
 129  */
 130 static void amdgpu_evict_flags(struct ttm_buffer_object *bo,
 131                                 struct ttm_placement *placement)
 132 {
 133         struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev);
 134         struct amdgpu_bo *abo;
 135         static const struct ttm_place placements = {
 136                 .fpfn = 0,
 137                 .lpfn = 0,
 138                 .flags = TTM_PL_MASK_CACHING | TTM_PL_FLAG_SYSTEM
 139         };
 140
 141         /* Don't handle scatter gather BOs */
 142         if (bo->type == ttm_bo_type_sg) {
 143                 placement->num_placement = 0;
 144                 placement->num_busy_placement = 0;
 145                 return;
 146         }
 147
 148         /* Object isn't an AMDGPU object so ignore */
 149         if (!amdgpu_bo_is_amdgpu_bo(bo)) {
 150                 placement->placement = &placements;
 151                 placement->busy_placement = &placements;
 152                 placement->num_placement = 1;
 153                 placement->num_busy_placement = 1;
 154                 return;
 155         }
 156
 157         abo = ttm_to_amdgpu_bo(bo);
 158         switch (bo->mem.mem_type) {
 159         case AMDGPU_PL_GDS:
 160         case AMDGPU_PL_GWS:
 161         case AMDGPU_PL_OA:
 162                 placement->num_placement = 0;
 163                 placement->num_busy_placement = 0;
 164                 return;
 165
 166         case TTM_PL_VRAM:
 167                 if (!adev->mman.buffer_funcs_enabled) {
 168                         /* Move to system memory */
 169                         amdgpu_bo_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_CPU);
 170                 } else if (!amdgpu_gmc_vram_full_visible(&adev->gmc) &&
 171                            !(abo->flags & AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED) &&
 172                            amdgpu_bo_in_cpu_visible_vram(abo)) {
 173
 174                         /* Try evicting to the CPU inaccessible part of VRAM
 175                          * first, but only set GTT as busy placement, so this
 176                          * BO will be evicted to GTT rather than causing other
 177                          * BOs to be evicted from VRAM
 178                          */
 179                         amdgpu_bo_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_VRAM |
 180                                                          AMDGPU_GEM_DOMAIN_GTT);
 181                         abo->placements[0].fpfn = adev->gmc.visible_vram_size >> PAGE_SHIFT;
 182                         abo->placements[0].lpfn = 0;
 183                         abo->placement.busy_placement = &abo->placements[1];
 184                         abo->placement.num_busy_placement = 1;
 185                 } else {
 186                         /* Move to GTT memory */
 187                         amdgpu_bo_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_GTT);
 188                 }
 189                 break;
 190         case TTM_PL_TT:
 191         default:
 192                 amdgpu_bo_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_CPU);
 193                 break;
 194         }
 195         *placement = abo->placement;
 196 }
 197
 198 /**
 199  * amdgpu_verify_access - Verify access for a mmap call
 200  *
 201  * @bo: The buffer object to map
 202  * @filp: The file pointer from the process performing the mmap
 203  *
 204  * This is called by ttm_bo_mmap() to verify whether a process
 205  * has the right to mmap a BO to their process space.
 206  */
 207 static int amdgpu_verify_access(struct ttm_buffer_object *bo, struct file *filp)
 208 {
 209         struct amdgpu_bo *abo = ttm_to_amdgpu_bo(bo);
 210
 211         /*
 212          * Don't verify access for KFD BOs. They don't have a GEM
 213          * object associated with them.
 214          */
 215         if (abo->kfd_bo)
 216                 return 0;
 217
 218         if (amdgpu_ttm_tt_get_usermm(bo->ttm))
 219                 return -EPERM;
 220         return drm_vma_node_verify_access(&abo->tbo.base.vma_node,
 221                                           filp->private_data);
 222 }
 223
 224 /**
 225  * amdgpu_move_null - Register memory for a buffer object
 226  *
 227  * @bo: The bo to assign the memory to
 228  * @new_mem: The memory to be assigned.
 229  *
 230  * Assign the memory from new_mem to the memory of the buffer object bo.
 231  */
 232 static void amdgpu_move_null(struct ttm_buffer_object *bo,
 233                              struct ttm_mem_reg *new_mem)
 234 {
 235         struct ttm_mem_reg *old_mem = &bo->mem;
 236
 237         BUG_ON(old_mem->mm_node != NULL);
 238         *old_mem = *new_mem;
 239         new_mem->mm_node = NULL;
 240 }
 241
 242 /**
 243  * amdgpu_mm_node_addr - Compute the GPU relative offset of a GTT buffer.
 244  *
 245  * @bo: The bo to assign the memory to.
 246  * @mm_node: Memory manager node for drm allocator.
 247  * @mem: The region where the bo resides.
 248  *
 249  */
 250 static uint64_t amdgpu_mm_node_addr(struct ttm_buffer_object *bo,
 251                                     struct drm_mm_node *mm_node,
 252                                     struct ttm_mem_reg *mem)
 253 {
 254         uint64_t addr = 0;
 255
 256         if (mm_node->start != AMDGPU_BO_INVALID_OFFSET) {
 257                 addr = mm_node->start << PAGE_SHIFT;
 258                 addr += amdgpu_ttm_domain_start(amdgpu_ttm_adev(bo->bdev),
 259                                                 mem->mem_type);
 260         }
 261         return addr;
 262 }
 263
 264 /**
 265  * amdgpu_find_mm_node - Helper function finds the drm_mm_node corresponding to
 266  * @offset. It also modifies the offset to be within the drm_mm_node returned
 267  *
 268  * @mem: The region where the bo resides.
 269  * @offset: The offset that drm_mm_node is used for finding.
 270  *
 271  */
 272 static struct drm_mm_node *amdgpu_find_mm_node(struct ttm_mem_reg *mem,
 273                                                uint64_t *offset)
 274 {
 275         struct drm_mm_node *mm_node = mem->mm_node;
 276
 277         while (*offset >= (mm_node->size << PAGE_SHIFT)) {
 278                 *offset -= (mm_node->size << PAGE_SHIFT);
 279                 ++mm_node;
 280         }
 281         return mm_node;
 282 }
 283
 284 /**
 285  * amdgpu_ttm_map_buffer - Map memory into the GART windows
 286  * @bo: buffer object to map
 287  * @mem: memory object to map
 288  * @mm_node: drm_mm node object to map
 289  * @num_pages: number of pages to map
 290  * @offset: offset into @mm_node where to start
 291  * @window: which GART window to use
 292  * @ring: DMA ring to use for the copy
 293  * @tmz: if we should setup a TMZ enabled mapping
 294  * @addr: resulting address inside the MC address space
 295  *
 296  * Setup one of the GART windows to access a specific piece of memory or return
 297  * the physical address for local memory.
 298  */
 299 static int amdgpu_ttm_map_buffer(struct ttm_buffer_object *bo,
 300                                  struct ttm_mem_reg *mem,
 301                                  struct drm_mm_node *mm_node,
 302                                  unsigned num_pages, uint64_t offset,
 303                                  unsigned window, struct amdgpu_ring *ring,
 304                                  bool tmz, uint64_t *addr)
 305 {
 306         struct amdgpu_device *adev = ring->adev;
 307         struct amdgpu_job *job;
 308         unsigned num_dw, num_bytes;
 309         struct dma_fence *fence;
 310         uint64_t src_addr, dst_addr;
 311         void *cpu_addr;
 312         uint64_t flags;
 313         unsigned int i;
 314         int r;
 315
 316         BUG_ON(adev->mman.buffer_funcs->copy_max_bytes <
 317                AMDGPU_GTT_MAX_TRANSFER_SIZE * 8);
 318
 319         /* Map only what can't be accessed directly */
 320         if (!tmz && mem->start != AMDGPU_BO_INVALID_OFFSET) {
 321                 *addr = amdgpu_mm_node_addr(bo, mm_node, mem) + offset;
 322                 return 0;
 323         }
 324
 325         *addr = adev->gmc.gart_start;
 326         *addr += (u64)window * AMDGPU_GTT_MAX_TRANSFER_SIZE *
 327                 AMDGPU_GPU_PAGE_SIZE;
 328         *addr += offset & ~PAGE_MASK;
 329
 330         num_dw = ALIGN(adev->mman.buffer_funcs->copy_num_dw, 8);
 331         num_bytes = num_pages * 8;
 332
 333         r = amdgpu_job_alloc_with_ib(adev, num_dw * 4 + num_bytes,
 334                                      AMDGPU_IB_POOL_DELAYED, &job);
 335         if (r)
 336                 return r;
 337
 338         src_addr = num_dw * 4;
 339         src_addr += job->ibs[0].gpu_addr;
 340
 341         dst_addr = amdgpu_bo_gpu_offset(adev->gart.bo);
 342         dst_addr += window * AMDGPU_GTT_MAX_TRANSFER_SIZE * 8;
 343         amdgpu_emit_copy_buffer(adev, &job->ibs[0], src_addr,
 344                                 dst_addr, num_bytes, false);
 345
 346         amdgpu_ring_pad_ib(ring, &job->ibs[0]);
 347         WARN_ON(job->ibs[0].length_dw > num_dw);
 348
 349         flags = amdgpu_ttm_tt_pte_flags(adev, bo->ttm, mem);
 350         if (tmz)
 351                 flags |= AMDGPU_PTE_TMZ;
 352
 353         cpu_addr = &job->ibs[0].ptr[num_dw];
 354
 355         if (mem->mem_type == TTM_PL_TT) {
 356                 struct ttm_dma_tt *dma;
 357                 dma_addr_t *dma_address;
 358
 359                 dma = container_of(bo->ttm, struct ttm_dma_tt, ttm);
 360                 dma_address = &dma->dma_address[offset >> PAGE_SHIFT];
 361                 r = amdgpu_gart_map(adev, 0, num_pages, dma_address, flags,
 362                                     cpu_addr);
 363                 if (r)
 364                         goto error_free;
 365         } else {
 366                 dma_addr_t dma_address;
 367
 368                 dma_address = (mm_node->start << PAGE_SHIFT) + offset;
 369                 dma_address += adev->vm_manager.vram_base_offset;
 370
 371                 for (i = 0; i < num_pages; ++i) {
 372                         r = amdgpu_gart_map(adev, i << PAGE_SHIFT, 1,
 373                                             &dma_address, flags, cpu_addr);
 374                         if (r)
 375                                 goto error_free;
 376
 377                         dma_address += PAGE_SIZE;
 378                 }
 379         }
 380
 381         r = amdgpu_job_submit(job, &adev->mman.entity,
 382                               AMDGPU_FENCE_OWNER_UNDEFINED, &fence);
 383         if (r)
 384                 goto error_free;
 385
 386         dma_fence_put(fence);
 387
 388         return r;
 389
 390 error_free:
 391         amdgpu_job_free(job);
 392         return r;
 393 }
 394
 395 /**
 396  * amdgpu_copy_ttm_mem_to_mem - Helper function for copy
 397  * @adev: amdgpu device
 398  * @src: buffer/address where to read from
 399  * @dst: buffer/address where to write to
 400  * @size: number of bytes to copy
 401  * @tmz: if a secure copy should be used
 402  * @resv: resv object to sync to
 403  * @f: Returns the last fence if multiple jobs are submitted.
 404  *
 405  * The function copies @size bytes from {src->mem + src->offset} to
 406  * {dst->mem + dst->offset}. src->bo and dst->bo could be same BO for a
 407  * move and different for a BO to BO copy.
 408  *
 409  */
 410 int amdgpu_ttm_copy_mem_to_mem(struct amdgpu_device *adev,
 411                                const struct amdgpu_copy_mem *src,
 412                                const struct amdgpu_copy_mem *dst,
 413                                uint64_t size, bool tmz,
 414                                struct dma_resv *resv,
 415                                struct dma_fence **f)
 416 {
 417         const uint32_t GTT_MAX_BYTES = (AMDGPU_GTT_MAX_TRANSFER_SIZE *
 418                                         AMDGPU_GPU_PAGE_SIZE);
 419
 420         uint64_t src_node_size, dst_node_size, src_offset, dst_offset;
 421         struct amdgpu_ring *ring = adev->mman.buffer_funcs_ring;
 422         struct drm_mm_node *src_mm, *dst_mm;
 423         struct dma_fence *fence = NULL;
 424         int r = 0;
 425
 426         if (!adev->mman.buffer_funcs_enabled) {
 427                 DRM_ERROR("Trying to move memory with ring turned off.\n");
 428                 return -EINVAL;
 429         }
 430
 431         src_offset = src->offset;
 432         if (src->mem->mm_node) {
 433                 src_mm = amdgpu_find_mm_node(src->mem, &src_offset);
 434                 src_node_size = (src_mm->size << PAGE_SHIFT) - src_offset;
 435         } else {
 436                 src_mm = NULL;
 437                 src_node_size = ULLONG_MAX;
 438         }
 439
 440         dst_offset = dst->offset;
 441         if (dst->mem->mm_node) {
 442                 dst_mm = amdgpu_find_mm_node(dst->mem, &dst_offset);
 443                 dst_node_size = (dst_mm->size << PAGE_SHIFT) - dst_offset;
 444         } else {
 445                 dst_mm = NULL;
 446                 dst_node_size = ULLONG_MAX;
 447         }
 448
 449         mutex_lock(&adev->mman.gtt_window_lock);
 450
 451         while (size) {
 452                 uint32_t src_page_offset = src_offset & ~PAGE_MASK;
 453                 uint32_t dst_page_offset = dst_offset & ~PAGE_MASK;
 454                 struct dma_fence *next;
 455                 uint32_t cur_size;
 456                 uint64_t from, to;
 457
 458                 /* Copy size cannot exceed GTT_MAX_BYTES. So if src or dst
 459                  * begins at an offset, then adjust the size accordingly
 460                  */
 461                 cur_size = max(src_page_offset, dst_page_offset);
 462                 cur_size = min(min3(src_node_size, dst_node_size, size),
 463                                (uint64_t)(GTT_MAX_BYTES - cur_size));
 464
 465                 /* Map src to window 0 and dst to window 1. */
 466                 r = amdgpu_ttm_map_buffer(src->bo, src->mem, src_mm,
 467                                           PFN_UP(cur_size + src_page_offset),
 468                                           src_offset, 0, ring, tmz, &from);
 469                 if (r)
 470                         goto error;
 471
 472                 r = amdgpu_ttm_map_buffer(dst->bo, dst->mem, dst_mm,
 473                                           PFN_UP(cur_size + dst_page_offset),
 474                                           dst_offset, 1, ring, tmz, &to);
 475                 if (r)
 476                         goto error;
 477
 478                 r = amdgpu_copy_buffer(ring, from, to, cur_size,
 479                                        resv, &next, false, true, tmz);
 480                 if (r)
 481                         goto error;
 482
 483                 dma_fence_put(fence);
 484                 fence = next;
 485
 486                 size -= cur_size;
 487                 if (!size)
 488                         break;
 489
 490                 src_node_size -= cur_size;
 491                 if (!src_node_size) {
 492                         ++src_mm;
 493                         src_node_size = src_mm->size << PAGE_SHIFT;
 494                         src_offset = 0;
 495                 } else {
 496                         src_offset += cur_size;
 497                 }
 498
 499                 dst_node_size -= cur_size;
 500                 if (!dst_node_size) {
 501                         ++dst_mm;
 502                         dst_node_size = dst_mm->size << PAGE_SHIFT;
 503                         dst_offset = 0;
 504                 } else {
 505                         dst_offset += cur_size;
 506                 }
 507         }
 508 error:
 509         mutex_unlock(&adev->mman.gtt_window_lock);
 510         if (f)
 511                 *f = dma_fence_get(fence);
 512         dma_fence_put(fence);
 513         return r;
 514 }
 515
 516 /**
 517  * amdgpu_move_blit - Copy an entire buffer to another buffer
 518  *
 519  * This is a helper called by amdgpu_bo_move() and amdgpu_move_vram_ram() to
 520  * help move buffers to and from VRAM.
 521  */
 522 static int amdgpu_move_blit(struct ttm_buffer_object *bo,
 523                             bool evict, bool no_wait_gpu,
 524                             struct ttm_mem_reg *new_mem,
 525                             struct ttm_mem_reg *old_mem)
 526 {
 527         struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev);
 528         struct amdgpu_bo *abo = ttm_to_amdgpu_bo(bo);
 529         struct amdgpu_copy_mem src, dst;
 530         struct dma_fence *fence = NULL;
 531         int r;
 532
 533         src.bo = bo;
 534         dst.bo = bo;
 535         src.mem = old_mem;
 536         dst.mem = new_mem;
 537         src.offset = 0;
 538         dst.offset = 0;
 539
 540         r = amdgpu_ttm_copy_mem_to_mem(adev, &src, &dst,
 541                                        new_mem->num_pages << PAGE_SHIFT,
 542                                        amdgpu_bo_encrypted(abo),
 543                                        bo->base.resv, &fence);
 544         if (r)
 545                 goto error;
 546
 547         /* clear the space being freed */
 548         if (old_mem->mem_type == TTM_PL_VRAM &&
 549             (abo->flags & AMDGPU_GEM_CREATE_VRAM_WIPE_ON_RELEASE)) {
 550                 struct dma_fence *wipe_fence = NULL;
 551
 552                 r = amdgpu_fill_buffer(ttm_to_amdgpu_bo(bo), AMDGPU_POISON,
 553                                        NULL, &wipe_fence);
 554                 if (r) {
 555                         goto error;
 556                 } else if (wipe_fence) {
 557                         dma_fence_put(fence);
 558                         fence = wipe_fence;
 559                 }
 560         }
 561
 562         /* Always block for VM page tables before committing the new location */
 563         if (bo->type == ttm_bo_type_kernel)
 564                 r = ttm_bo_move_accel_cleanup(bo, fence, true, new_mem);
 565         else
 566                 r = ttm_bo_pipeline_move(bo, fence, evict, new_mem);
 567         dma_fence_put(fence);
 568         return r;
 569
 570 error:
 571         if (fence)
 572                 dma_fence_wait(fence, false);
 573         dma_fence_put(fence);
 574         return r;
 575 }
 576
 577 /**
 578  * amdgpu_move_vram_ram - Copy VRAM buffer to RAM buffer
 579  *
 580  * Called by amdgpu_bo_move().
 581  */
 582 static int amdgpu_move_vram_ram(struct ttm_buffer_object *bo, bool evict,
 583                                 struct ttm_operation_ctx *ctx,
 584                                 struct ttm_mem_reg *new_mem)
 585 {
 586         struct ttm_mem_reg *old_mem = &bo->mem;
 587         struct ttm_mem_reg tmp_mem;
 588         struct ttm_place placements;
 589         struct ttm_placement placement;
 590         int r;
 591
 592         /* create space/pages for new_mem in GTT space */
 593         tmp_mem = *new_mem;
 594         tmp_mem.mm_node = NULL;
 595         placement.num_placement = 1;
 596         placement.placement = &placements;
 597         placement.num_busy_placement = 1;
 598         placement.busy_placement = &placements;
 599         placements.fpfn = 0;
 600         placements.lpfn = 0;
 601         placements.flags = TTM_PL_MASK_CACHING | TTM_PL_FLAG_TT;
 602         r = ttm_bo_mem_space(bo, &placement, &tmp_mem, ctx);
 603         if (unlikely(r)) {
 604                 pr_err("Failed to find GTT space for blit from VRAM\n");
 605                 return r;
 606         }
 607
 608         /* set caching flags */
 609         r = ttm_tt_set_placement_caching(bo->ttm, tmp_mem.placement);
 610         if (unlikely(r)) {
 611                 goto out_cleanup;
 612         }
 613
 614         /* Bind the memory to the GTT space */
 615         r = ttm_tt_bind(bo->ttm, &tmp_mem, ctx);
 616         if (unlikely(r)) {
 617                 goto out_cleanup;
 618         }
 619
 620         /* blit VRAM to GTT */
 621         r = amdgpu_move_blit(bo, evict, ctx->no_wait_gpu, &tmp_mem, old_mem);
 622         if (unlikely(r)) {
 623                 goto out_cleanup;
 624         }
 625
 626         /* move BO (in tmp_mem) to new_mem */
 627         r = ttm_bo_move_ttm(bo, ctx, new_mem);
 628 out_cleanup:
 629         ttm_bo_mem_put(bo, &tmp_mem);
 630         return r;
 631 }
 632
 633 /**
 634  * amdgpu_move_ram_vram - Copy buffer from RAM to VRAM
 635  *
 636  * Called by amdgpu_bo_move().
 637  */
 638 static int amdgpu_move_ram_vram(struct ttm_buffer_object *bo, bool evict,
 639                                 struct ttm_operation_ctx *ctx,
 640                                 struct ttm_mem_reg *new_mem)
 641 {
 642         struct ttm_mem_reg *old_mem = &bo->mem;
 643         struct ttm_mem_reg tmp_mem;
 644         struct ttm_placement placement;
 645         struct ttm_place placements;
 646         int r;
 647
 648         /* make space in GTT for old_mem buffer */
 649         tmp_mem = *new_mem;
 650         tmp_mem.mm_node = NULL;
 651         placement.num_placement = 1;
 652         placement.placement = &placements;
 653         placement.num_busy_placement = 1;
 654         placement.busy_placement = &placements;
 655         placements.fpfn = 0;
 656         placements.lpfn = 0;
 657         placements.flags = TTM_PL_MASK_CACHING | TTM_PL_FLAG_TT;
 658         r = ttm_bo_mem_space(bo, &placement, &tmp_mem, ctx);
 659         if (unlikely(r)) {
 660                 pr_err("Failed to find GTT space for blit to VRAM\n");
 661                 return r;
 662         }
 663
 664         /* move/bind old memory to GTT space */
 665         r = ttm_bo_move_ttm(bo, ctx, &tmp_mem);
 666         if (unlikely(r)) {
 667                 goto out_cleanup;
 668         }
 669
 670         /* copy to VRAM */
 671         r = amdgpu_move_blit(bo, evict, ctx->no_wait_gpu, new_mem, old_mem);
 672         if (unlikely(r)) {
 673                 goto out_cleanup;
 674         }
 675 out_cleanup:
 676         ttm_bo_mem_put(bo, &tmp_mem);
 677         return r;
 678 }
 679
 680 /**
 681  * amdgpu_mem_visible - Check that memory can be accessed by ttm_bo_move_memcpy
 682  *
 683  * Called by amdgpu_bo_move()
 684  */
 685 static bool amdgpu_mem_visible(struct amdgpu_device *adev,
 686                                struct ttm_mem_reg *mem)
 687 {
 688         struct drm_mm_node *nodes = mem->mm_node;
 689
 690         if (mem->mem_type == TTM_PL_SYSTEM ||
 691             mem->mem_type == TTM_PL_TT)
 692                 return true;
 693         if (mem->mem_type != TTM_PL_VRAM)
 694                 return false;
 695
 696         /* ttm_mem_reg_ioremap only supports contiguous memory */
 697         if (nodes->size != mem->num_pages)
 698                 return false;
 699
 700         return ((nodes->start + nodes->size) << PAGE_SHIFT)
 701                 <= adev->gmc.visible_vram_size;
 702 }
 703
 704 /**
 705  * amdgpu_bo_move - Move a buffer object to a new memory location
 706  *
 707  * Called by ttm_bo_handle_move_mem()
 708  */
 709 static int amdgpu_bo_move(struct ttm_buffer_object *bo, bool evict,
 710                           struct ttm_operation_ctx *ctx,
 711                           struct ttm_mem_reg *new_mem)
 712 {
 713         struct amdgpu_device *adev;
 714         struct amdgpu_bo *abo;
 715         struct ttm_mem_reg *old_mem = &bo->mem;
 716         int r;
 717
 718         /* Can't move a pinned BO */
 719         abo = ttm_to_amdgpu_bo(bo);
 720         if (WARN_ON_ONCE(abo->pin_count > 0))
 721                 return -EINVAL;
 722
 723         adev = amdgpu_ttm_adev(bo->bdev);
 724
 725         if (old_mem->mem_type == TTM_PL_SYSTEM && bo->ttm == NULL) {
 726                 amdgpu_move_null(bo, new_mem);
 727                 return 0;
 728         }
 729         if ((old_mem->mem_type == TTM_PL_TT &&
 730              new_mem->mem_type == TTM_PL_SYSTEM) ||
 731             (old_mem->mem_type == TTM_PL_SYSTEM &&
 732              new_mem->mem_type == TTM_PL_TT)) {
 733                 /* bind is enough */
 734                 amdgpu_move_null(bo, new_mem);
 735                 return 0;
 736         }
 737         if (old_mem->mem_type == AMDGPU_PL_GDS ||
 738             old_mem->mem_type == AMDGPU_PL_GWS ||
 739             old_mem->mem_type == AMDGPU_PL_OA ||
 740             new_mem->mem_type == AMDGPU_PL_GDS ||
 741             new_mem->mem_type == AMDGPU_PL_GWS ||
 742             new_mem->mem_type == AMDGPU_PL_OA) {
 743                 /* Nothing to save here */
 744                 amdgpu_move_null(bo, new_mem);
 745                 return 0;
 746         }
 747
 748         if (!adev->mman.buffer_funcs_enabled) {
 749                 r = -ENODEV;
 750                 goto memcpy;
 751         }
 752
 753         if (old_mem->mem_type == TTM_PL_VRAM &&
 754             new_mem->mem_type == TTM_PL_SYSTEM) {
 755                 r = amdgpu_move_vram_ram(bo, evict, ctx, new_mem);
 756         } else if (old_mem->mem_type == TTM_PL_SYSTEM &&
 757                    new_mem->mem_type == TTM_PL_VRAM) {
 758                 r = amdgpu_move_ram_vram(bo, evict, ctx, new_mem);
 759         } else {
 760                 r = amdgpu_move_blit(bo, evict, ctx->no_wait_gpu,
 761                                      new_mem, old_mem);
 762         }
 763
 764         if (r) {
 765 memcpy:
 766                 /* Check that all memory is CPU accessible */
 767                 if (!amdgpu_mem_visible(adev, old_mem) ||
 768                     !amdgpu_mem_visible(adev, new_mem)) {
 769                         pr_err("Move buffer fallback to memcpy unavailable\n");
 770                         return r;
 771                 }
 772
 773                 r = ttm_bo_move_memcpy(bo, ctx, new_mem);
 774                 if (r)
 775                         return r;
 776         }
 777
 778         if (bo->type == ttm_bo_type_device &&
 779             new_mem->mem_type == TTM_PL_VRAM &&
 780             old_mem->mem_type != TTM_PL_VRAM) {
 781                 /* amdgpu_bo_fault_reserve_notify will re-set this if the CPU
 782                  * accesses the BO after it's moved.
 783                  */
 784                 abo->flags &= ~AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED;
 785         }
 786
 787         /* update statistics */
 788         atomic64_add((u64)bo->num_pages << PAGE_SHIFT, &adev->num_bytes_moved);
 789         return 0;
 790 }
 791
 792 /**
 793  * amdgpu_ttm_io_mem_reserve - Reserve a block of memory during a fault
 794  *
 795  * Called by ttm_mem_io_reserve() ultimately via ttm_bo_vm_fault()
 796  */
 797 static int amdgpu_ttm_io_mem_reserve(struct ttm_bo_device *bdev, struct ttm_mem_reg *mem)
 798 {
 799         struct ttm_mem_type_manager *man = &bdev->man[mem->mem_type];
 800         struct amdgpu_device *adev = amdgpu_ttm_adev(bdev);
 801         struct drm_mm_node *mm_node = mem->mm_node;
 802
 803         mem->bus.addr = NULL;
 804         mem->bus.offset = 0;
 805         mem->bus.size = mem->num_pages << PAGE_SHIFT;
 806         mem->bus.base = 0;
 807         mem->bus.is_iomem = false;
 808         if (!(man->flags & TTM_MEMTYPE_FLAG_MAPPABLE))
 809                 return -EINVAL;
 810         switch (mem->mem_type) {
 811         case TTM_PL_SYSTEM:
 812                 /* system memory */
 813                 return 0;
 814         case TTM_PL_TT:
 815                 break;
 816         case TTM_PL_VRAM:
 817                 mem->bus.offset = mem->start << PAGE_SHIFT;
 818                 /* check if it's visible */
 819                 if ((mem->bus.offset + mem->bus.size) > adev->gmc.visible_vram_size)
 820                         return -EINVAL;
 821                 /* Only physically contiguous buffers apply. In a contiguous
 822                  * buffer, size of the first mm_node would match the number of
 823                  * pages in ttm_mem_reg.
 824                  */
 825                 if (adev->mman.aper_base_kaddr &&
 826                     (mm_node->size == mem->num_pages))
 827                         mem->bus.addr = (u8 *)adev->mman.aper_base_kaddr +
 828                                         mem->bus.offset;
 829
 830                 mem->bus.base = adev->gmc.aper_base;
 831                 mem->bus.is_iomem = true;
 832                 break;
 833         default:
 834                 return -EINVAL;
 835         }
 836         return 0;
 837 }
 838
 839 static unsigned long amdgpu_ttm_io_mem_pfn(struct ttm_buffer_object *bo,
 840                                            unsigned long page_offset)
 841 {
 842         uint64_t offset = (page_offset << PAGE_SHIFT);
 843         struct drm_mm_node *mm;
 844
 845         mm = amdgpu_find_mm_node(&bo->mem, &offset);
 846         return (bo->mem.bus.base >> PAGE_SHIFT) + mm->start +
 847                 (offset >> PAGE_SHIFT);
 848 }
 849
 850 /**
 851  * amdgpu_ttm_domain_start - Returns GPU start address
 852  * @adev: amdgpu device object
 853  * @type: type of the memory
 854  *
 855  * Returns:
 856  * GPU start address of a memory domain
 857  */
 858
 859 uint64_t amdgpu_ttm_domain_start(struct amdgpu_device *adev, uint32_t type)
 860 {
 861         switch (type) {
 862         case TTM_PL_TT:
 863                 return adev->gmc.gart_start;
 864         case TTM_PL_VRAM:
 865                 return adev->gmc.vram_start;
 866         }
 867
 868         return 0;
 869 }
 870
 871 /*
 872  * TTM backend functions.
 873  */
 874 struct amdgpu_ttm_tt {
 875         struct ttm_dma_tt       ttm;
 876         struct drm_gem_object   *gobj;
 877         u64                     offset;
 878         uint64_t                userptr;
 879         struct task_struct      *usertask;
 880         uint32_t                userflags;
 881 #if IS_ENABLED(CONFIG_DRM_AMDGPU_USERPTR)
 882         struct hmm_range        *range;
 883 #endif
 884 };
 885
 886 #ifdef CONFIG_DRM_AMDGPU_USERPTR
 887 /**
 888  * amdgpu_ttm_tt_get_user_pages - get device accessible pages that back user
 889  * memory and start HMM tracking CPU page table update
 890  *
 891  * Calling function must call amdgpu_ttm_tt_userptr_range_done() once and only
 892  * once afterwards to stop HMM tracking
 893  */
 894 int amdgpu_ttm_tt_get_user_pages(struct amdgpu_bo *bo, struct page **pages)
 895 {
 896         struct ttm_tt *ttm = bo->tbo.ttm;
 897         struct amdgpu_ttm_tt *gtt = (void *)ttm;
 898         unsigned long start = gtt->userptr;
 899         struct vm_area_struct *vma;
 900         struct hmm_range *range;
 901         unsigned long timeout;
 902         struct mm_struct *mm;
 903         unsigned long i;
 904         int r = 0;
 905
 906         mm = bo->notifier.mm;
 907         if (unlikely(!mm)) {
 908                 DRM_DEBUG_DRIVER("BO is not registered?\n");
 909                 return -EFAULT;
 910         }
 911
 912         /* Another get_user_pages is running at the same time?? */
 913         if (WARN_ON(gtt->range))
 914                 return -EFAULT;
 915
 916         if (!mmget_not_zero(mm)) /* Happens during process shutdown */
 917                 return -ESRCH;
 918
 919         range = kzalloc(sizeof(*range), GFP_KERNEL);
 920         if (unlikely(!range)) {
 921                 r = -ENOMEM;
 922                 goto out;
 923         }
 924         range->notifier = &bo->notifier;
 925         range->start = bo->notifier.interval_tree.start;
 926         range->end = bo->notifier.interval_tree.last + 1;
 927         range->default_flags = HMM_PFN_REQ_FAULT;
 928         if (!amdgpu_ttm_tt_is_readonly(ttm))
 929                 range->default_flags |= HMM_PFN_REQ_WRITE;
 930
 931         range->hmm_pfns = kvmalloc_array(ttm->num_pages,
 932                                          sizeof(*range->hmm_pfns), GFP_KERNEL);
 933         if (unlikely(!range->hmm_pfns)) {
 934                 r = -ENOMEM;
 935                 goto out_free_ranges;
 936         }
 937
 938         mmap_read_lock(mm);
 939         vma = find_vma(mm, start);
 940         if (unlikely(!vma || start < vma->vm_start)) {
 941                 r = -EFAULT;
 942                 goto out_unlock;
 943         }
 944         if (unlikely((gtt->userflags & AMDGPU_GEM_USERPTR_ANONONLY) &&
 945                 vma->vm_file)) {
 946                 r = -EPERM;
 947                 goto out_unlock;
 948         }
 949         mmap_read_unlock(mm);
 950         timeout = jiffies + msecs_to_jiffies(HMM_RANGE_DEFAULT_TIMEOUT);
 951
 952 retry:
 953         range->notifier_seq = mmu_interval_read_begin(&bo->notifier);
 954
 955         mmap_read_lock(mm);
 956         r = hmm_range_fault(range);
 957         mmap_read_unlock(mm);
 958         if (unlikely(r)) {
 959                 /*
 960                  * FIXME: This timeout should encompass the retry from
 961                  * mmu_interval_read_retry() as well.
 962                  */
 963                 if (r == -EBUSY && !time_after(jiffies, timeout))
 964                         goto retry;
 965                 goto out_free_pfns;
 966         }
 967
 968         /*
 969          * Due to default_flags, all pages are HMM_PFN_VALID or
 970          * hmm_range_fault() fails. FIXME: The pages cannot be touched outside
 971          * the notifier_lock, and mmu_interval_read_retry() must be done first.
 972          */
 973         for (i = 0; i < ttm->num_pages; i++)
 974                 pages[i] = hmm_pfn_to_page(range->hmm_pfns[i]);
 975
 976         gtt->range = range;
 977         mmput(mm);
 978
 979         return 0;
 980
 981 out_unlock:
 982         mmap_read_unlock(mm);
 983 out_free_pfns:
 984         kvfree(range->hmm_pfns);
 985 out_free_ranges:
 986         kfree(range);
 987 out:
 988         mmput(mm);
 989         return r;
 990 }
 991
 992 /**
 993  * amdgpu_ttm_tt_userptr_range_done - stop HMM track the CPU page table change
 994  * Check if the pages backing this ttm range have been invalidated
 995  *
 996  * Returns: true if pages are still valid
 997  */
 998 bool amdgpu_ttm_tt_get_user_pages_done(struct ttm_tt *ttm)
 999 {
1000         struct amdgpu_ttm_tt *gtt = (void *)ttm;
1001         bool r = false;
1002
1003         if (!gtt || !gtt->userptr)
1004                 return false;
1005
1006         DRM_DEBUG_DRIVER("user_pages_done 0x%llx pages 0x%lx\n",
1007                 gtt->userptr, ttm->num_pages);
1008
1009         WARN_ONCE(!gtt->range || !gtt->range->hmm_pfns,
1010                 "No user pages to check\n");
1011
1012         if (gtt->range) {
1013                 /*
1014                  * FIXME: Must always hold notifier_lock for this, and must
1015                  * not ignore the return code.
1016                  */
1017                 r = mmu_interval_read_retry(gtt->range->notifier,
1018                                          gtt->range->notifier_seq);
1019                 kvfree(gtt->range->hmm_pfns);
1020                 kfree(gtt->range);
1021                 gtt->range = NULL;
1022         }
1023
1024         return !r;
1025 }
1026 #endif
1027
1028 /**
1029  * amdgpu_ttm_tt_set_user_pages - Copy pages in, putting old pages as necessary.
1030  *
1031  * Called by amdgpu_cs_list_validate(). This creates the page list
1032  * that backs user memory and will ultimately be mapped into the device
1033  * address space.
1034  */
1035 void amdgpu_ttm_tt_set_user_pages(struct ttm_tt *ttm, struct page **pages)
1036 {
1037         unsigned long i;
1038
1039         for (i = 0; i < ttm->num_pages; ++i)
1040                 ttm->pages[i] = pages ? pages[i] : NULL;
1041 }
1042
1043 /**
1044  * amdgpu_ttm_tt_pin_userptr -  prepare the sg table with the user pages
1045  *
1046  * Called by amdgpu_ttm_backend_bind()
1047  **/
1048 static int amdgpu_ttm_tt_pin_userptr(struct ttm_tt *ttm)
1049 {
1050         struct amdgpu_device *adev = amdgpu_ttm_adev(ttm->bdev);
1051         struct amdgpu_ttm_tt *gtt = (void *)ttm;
1052         int r;
1053
1054         int write = !(gtt->userflags & AMDGPU_GEM_USERPTR_READONLY);
1055         enum dma_data_direction direction = write ?
1056                 DMA_BIDIRECTIONAL : DMA_TO_DEVICE;
1057
1058         /* Allocate an SG array and squash pages into it */
1059         r = sg_alloc_table_from_pages(ttm->sg, ttm->pages, ttm->num_pages, 0,
1060                                       ttm->num_pages << PAGE_SHIFT,
1061                                       GFP_KERNEL);
1062         if (r)
1063                 goto release_sg;
1064
1065         /* Map SG to device */
1066         r = dma_map_sgtable(adev->dev, ttm->sg, direction, 0);
1067         if (r)
1068                 goto release_sg;
1069
1070         /* convert SG to linear array of pages and dma addresses */
1071         drm_prime_sg_to_page_addr_arrays(ttm->sg, ttm->pages,
1072                                          gtt->ttm.dma_address, ttm->num_pages);
1073
1074         return 0;
1075
1076 release_sg:
1077         kfree(ttm->sg);
1078         return r;
1079 }
1080
1081 /**
1082  * amdgpu_ttm_tt_unpin_userptr - Unpin and unmap userptr pages
1083  */
1084 static void amdgpu_ttm_tt_unpin_userptr(struct ttm_tt *ttm)
1085 {
1086         struct amdgpu_device *adev = amdgpu_ttm_adev(ttm->bdev);
1087         struct amdgpu_ttm_tt *gtt = (void *)ttm;
1088
1089         int write = !(gtt->userflags & AMDGPU_GEM_USERPTR_READONLY);
1090         enum dma_data_direction direction = write ?
1091                 DMA_BIDIRECTIONAL : DMA_TO_DEVICE;
1092
1093         /* double check that we don't free the table twice */
1094         if (!ttm->sg->sgl)
1095                 return;
1096
1097         /* unmap the pages mapped to the device */
1098         dma_unmap_sgtable(adev->dev, ttm->sg, direction, 0);
1099         sg_free_table(ttm->sg);
1100
1101 #if IS_ENABLED(CONFIG_DRM_AMDGPU_USERPTR)
1102         if (gtt->range) {
1103                 unsigned long i;
1104
1105                 for (i = 0; i < ttm->num_pages; i++) {
1106                         if (ttm->pages[i] !=
1107                             hmm_pfn_to_page(gtt->range->hmm_pfns[i]))
1108                                 break;
1109                 }
1110
1111                 WARN((i == ttm->num_pages), "Missing get_user_page_done\n");
1112         }
1113 #endif
1114 }
1115
1116 int amdgpu_ttm_gart_bind(struct amdgpu_device *adev,
1117                                 struct ttm_buffer_object *tbo,
1118                                 uint64_t flags)
1119 {
1120         struct amdgpu_bo *abo = ttm_to_amdgpu_bo(tbo);
1121         struct ttm_tt *ttm = tbo->ttm;
1122         struct amdgpu_ttm_tt *gtt = (void *)ttm;
1123         int r;
1124
1125         if (amdgpu_bo_encrypted(abo))
1126                 flags |= AMDGPU_PTE_TMZ;
1127
1128         if (abo->flags & AMDGPU_GEM_CREATE_CP_MQD_GFX9) {
1129                 uint64_t page_idx = 1;
1130
1131                 r = amdgpu_gart_bind(adev, gtt->offset, page_idx,
1132                                 ttm->pages, gtt->ttm.dma_address, flags);
1133                 if (r)
1134                         goto gart_bind_fail;
1135
1136                 /* The memory type of the first page defaults to UC. Now
1137                  * modify the memory type to NC from the second page of
1138                  * the BO onward.
1139                  */
1140                 flags &= ~AMDGPU_PTE_MTYPE_VG10_MASK;
1141                 flags |= AMDGPU_PTE_MTYPE_VG10(AMDGPU_MTYPE_NC);
1142
1143                 r = amdgpu_gart_bind(adev,
1144                                 gtt->offset + (page_idx << PAGE_SHIFT),
1145                                 ttm->num_pages - page_idx,
1146                                 &ttm->pages[page_idx],
1147                                 &(gtt->ttm.dma_address[page_idx]), flags);
1148         } else {
1149                 r = amdgpu_gart_bind(adev, gtt->offset, ttm->num_pages,
1150                                      ttm->pages, gtt->ttm.dma_address, flags);
1151         }
1152
1153 gart_bind_fail:
1154         if (r)
1155                 DRM_ERROR("failed to bind %lu pages at 0x%08llX\n",
1156                           ttm->num_pages, gtt->offset);
1157
1158         return r;
1159 }
1160
1161 /**
1162  * amdgpu_ttm_backend_bind - Bind GTT memory
1163  *
1164  * Called by ttm_tt_bind() on behalf of ttm_bo_handle_move_mem().
1165  * This handles binding GTT memory to the device address space.
1166  */
1167 static int amdgpu_ttm_backend_bind(struct ttm_tt *ttm,
1168                                    struct ttm_mem_reg *bo_mem)
1169 {
1170         struct amdgpu_device *adev = amdgpu_ttm_adev(ttm->bdev);
1171         struct amdgpu_ttm_tt *gtt = (void*)ttm;
1172         uint64_t flags;
1173         int r = 0;
1174
1175         if (gtt->userptr) {
1176                 r = amdgpu_ttm_tt_pin_userptr(ttm);
1177                 if (r) {
1178                         DRM_ERROR("failed to pin userptr\n");
1179                         return r;
1180                 }
1181         }
1182         if (!ttm->num_pages) {
1183                 WARN(1, "nothing to bind %lu pages for mreg %p back %p!\n",
1184                      ttm->num_pages, bo_mem, ttm);
1185         }
1186
1187         if (bo_mem->mem_type == AMDGPU_PL_GDS ||
1188             bo_mem->mem_type == AMDGPU_PL_GWS ||
1189             bo_mem->mem_type == AMDGPU_PL_OA)
1190                 return -EINVAL;
1191
1192         if (!amdgpu_gtt_mgr_has_gart_addr(bo_mem)) {
1193                 gtt->offset = AMDGPU_BO_INVALID_OFFSET;
1194                 return 0;
1195         }
1196
1197         /* compute PTE flags relevant to this BO memory */
1198         flags = amdgpu_ttm_tt_pte_flags(adev, ttm, bo_mem);
1199
1200         /* bind pages into GART page tables */
1201         gtt->offset = (u64)bo_mem->start << PAGE_SHIFT;
1202         r = amdgpu_gart_bind(adev, gtt->offset, ttm->num_pages,
1203                 ttm->pages, gtt->ttm.dma_address, flags);
1204
1205         if (r)
1206                 DRM_ERROR("failed to bind %lu pages at 0x%08llX\n",
1207                           ttm->num_pages, gtt->offset);
1208         return r;
1209 }
1210
1211 /**
1212  * amdgpu_ttm_alloc_gart - Allocate GART memory for buffer object
1213  */
1214 int amdgpu_ttm_alloc_gart(struct ttm_buffer_object *bo)
1215 {
1216         struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev);
1217         struct ttm_operation_ctx ctx = { false, false };
1218         struct amdgpu_ttm_tt *gtt = (void*)bo->ttm;
1219         struct ttm_mem_reg tmp;
1220         struct ttm_placement placement;
1221         struct ttm_place placements;
1222         uint64_t addr, flags;
1223         int r;
1224
1225         if (bo->mem.start != AMDGPU_BO_INVALID_OFFSET)
1226                 return 0;
1227
1228         addr = amdgpu_gmc_agp_addr(bo);
1229         if (addr != AMDGPU_BO_INVALID_OFFSET) {
1230                 bo->mem.start = addr >> PAGE_SHIFT;
1231         } else {
1232
1233                 /* allocate GART space */
1234                 tmp = bo->mem;
1235                 tmp.mm_node = NULL;
1236                 placement.num_placement = 1;
1237                 placement.placement = &placements;
1238                 placement.num_busy_placement = 1;
1239                 placement.busy_placement = &placements;
1240                 placements.fpfn = 0;
1241                 placements.lpfn = adev->gmc.gart_size >> PAGE_SHIFT;
1242                 placements.flags = (bo->mem.placement & ~TTM_PL_MASK_MEM) |
1243                         TTM_PL_FLAG_TT;
1244
1245                 r = ttm_bo_mem_space(bo, &placement, &tmp, &ctx);
1246                 if (unlikely(r))
1247                         return r;
1248
1249                 /* compute PTE flags for this buffer object */
1250                 flags = amdgpu_ttm_tt_pte_flags(adev, bo->ttm, &tmp);
1251
1252                 /* Bind pages */
1253                 gtt->offset = (u64)tmp.start << PAGE_SHIFT;
1254                 r = amdgpu_ttm_gart_bind(adev, bo, flags);
1255                 if (unlikely(r)) {
1256                         ttm_bo_mem_put(bo, &tmp);
1257                         return r;
1258                 }
1259
1260                 ttm_bo_mem_put(bo, &bo->mem);
1261                 bo->mem = tmp;
1262         }
1263
1264         return 0;
1265 }
1266
1267 /**
1268  * amdgpu_ttm_recover_gart - Rebind GTT pages
1269  *
1270  * Called by amdgpu_gtt_mgr_recover() from amdgpu_device_reset() to
1271  * rebind GTT pages during a GPU reset.
1272  */
1273 int amdgpu_ttm_recover_gart(struct ttm_buffer_object *tbo)
1274 {
1275         struct amdgpu_device *adev = amdgpu_ttm_adev(tbo->bdev);
1276         uint64_t flags;
1277         int r;
1278
1279         if (!tbo->ttm)
1280                 return 0;
1281
1282         flags = amdgpu_ttm_tt_pte_flags(adev, tbo->ttm, &tbo->mem);
1283         r = amdgpu_ttm_gart_bind(adev, tbo, flags);
1284
1285         return r;
1286 }
1287
1288 /**
1289  * amdgpu_ttm_backend_unbind - Unbind GTT mapped pages
1290  *
1291  * Called by ttm_tt_unbind() on behalf of ttm_bo_move_ttm() and
1292  * ttm_tt_destroy().
1293  */
1294 static int amdgpu_ttm_backend_unbind(struct ttm_tt *ttm)
1295 {
1296         struct amdgpu_device *adev = amdgpu_ttm_adev(ttm->bdev);
1297         struct amdgpu_ttm_tt *gtt = (void *)ttm;
1298         int r;
1299
1300         /* if the pages have userptr pinning then clear that first */
1301         if (gtt->userptr)
1302                 amdgpu_ttm_tt_unpin_userptr(ttm);
1303
1304         if (gtt->offset == AMDGPU_BO_INVALID_OFFSET)
1305                 return 0;
1306
1307         /* unbind shouldn't be done for GDS/GWS/OA in ttm_bo_clean_mm */
1308         r = amdgpu_gart_unbind(adev, gtt->offset, ttm->num_pages);
1309         if (r)
1310                 DRM_ERROR("failed to unbind %lu pages at 0x%08llX\n",
1311                           gtt->ttm.ttm.num_pages, gtt->offset);
1312         return r;
1313 }
1314
1315 static void amdgpu_ttm_backend_destroy(struct ttm_tt *ttm)
1316 {
1317         struct amdgpu_ttm_tt *gtt = (void *)ttm;
1318
1319         if (gtt->usertask)
1320                 put_task_struct(gtt->usertask);
1321
1322         ttm_dma_tt_fini(&gtt->ttm);
1323         kfree(gtt);
1324 }
1325
1326 static struct ttm_backend_func amdgpu_backend_func = {
1327         .bind = &amdgpu_ttm_backend_bind,
1328         .unbind = &amdgpu_ttm_backend_unbind,
1329         .destroy = &amdgpu_ttm_backend_destroy,
1330 };
1331
1332 /**
1333  * amdgpu_ttm_tt_create - Create a ttm_tt object for a given BO
1334  *
1335  * @bo: The buffer object to create a GTT ttm_tt object around
1336  *
1337  * Called by ttm_tt_create().
1338  */
1339 static struct ttm_tt *amdgpu_ttm_tt_create(struct ttm_buffer_object *bo,
1340                                            uint32_t page_flags)
1341 {
1342         struct amdgpu_ttm_tt *gtt;
1343
1344         gtt = kzalloc(sizeof(struct amdgpu_ttm_tt), GFP_KERNEL);
1345         if (gtt == NULL) {
1346                 return NULL;
1347         }
1348         gtt->ttm.ttm.func = &amdgpu_backend_func;
1349         gtt->gobj = &bo->base;
1350
1351         /* allocate space for the uninitialized page entries */
1352         if (ttm_sg_tt_init(&gtt->ttm, bo, page_flags)) {
1353                 kfree(gtt);
1354                 return NULL;
1355         }
1356         return &gtt->ttm.ttm;
1357 }
1358
1359 /**
1360  * amdgpu_ttm_tt_populate - Map GTT pages visible to the device
1361  *
1362  * Map the pages of a ttm_tt object to an address space visible
1363  * to the underlying device.
1364  */
1365 static int amdgpu_ttm_tt_populate(struct ttm_tt *ttm,
1366                         struct ttm_operation_ctx *ctx)
1367 {
1368         struct amdgpu_device *adev = amdgpu_ttm_adev(ttm->bdev);
1369         struct amdgpu_ttm_tt *gtt = (void *)ttm;
1370
1371         /* user pages are bound by amdgpu_ttm_tt_pin_userptr() */
1372         if (gtt && gtt->userptr) {
1373                 ttm->sg = kzalloc(sizeof(struct sg_table), GFP_KERNEL);
1374                 if (!ttm->sg)
1375                         return -ENOMEM;
1376
1377                 ttm->page_flags |= TTM_PAGE_FLAG_SG;
1378                 ttm->state = tt_unbound;
1379                 return 0;
1380         }
1381
1382         if (ttm->page_flags & TTM_PAGE_FLAG_SG) {
1383                 if (!ttm->sg) {
1384                         struct dma_buf_attachment *attach;
1385                         struct sg_table *sgt;
1386
1387                         attach = gtt->gobj->import_attach;
1388                         sgt = dma_buf_map_attachment(attach, DMA_BIDIRECTIONAL);
1389                         if (IS_ERR(sgt))
1390                                 return PTR_ERR(sgt);
1391
1392                         ttm->sg = sgt;
1393                 }
1394
1395                 drm_prime_sg_to_page_addr_arrays(ttm->sg, ttm->pages,
1396                                                  gtt->ttm.dma_address,
1397                                                  ttm->num_pages);
1398                 ttm->state = tt_unbound;
1399                 return 0;
1400         }
1401
1402 #ifdef CONFIG_SWIOTLB
1403         if (adev->need_swiotlb && swiotlb_nr_tbl()) {
1404                 return ttm_dma_populate(&gtt->ttm, adev->dev, ctx);
1405         }
1406 #endif
1407
1408         /* fall back to generic helper to populate the page array
1409          * and map them to the device */
1410         return ttm_populate_and_map_pages(adev->dev, &gtt->ttm, ctx);
1411 }
1412
1413 /**
1414  * amdgpu_ttm_tt_unpopulate - unmap GTT pages and unpopulate page arrays
1415  *
1416  * Unmaps pages of a ttm_tt object from the device address space and
1417  * unpopulates the page array backing it.
1418  */
1419 static void amdgpu_ttm_tt_unpopulate(struct ttm_tt *ttm)
1420 {
1421         struct amdgpu_ttm_tt *gtt = (void *)ttm;
1422         struct amdgpu_device *adev;
1423
1424         if (gtt && gtt->userptr) {
1425                 amdgpu_ttm_tt_set_user_pages(ttm, NULL);
1426                 kfree(ttm->sg);
1427                 ttm->page_flags &= ~TTM_PAGE_FLAG_SG;
1428                 return;
1429         }
1430
1431         if (ttm->sg && gtt->gobj->import_attach) {
1432                 struct dma_buf_attachment *attach;
1433
1434                 attach = gtt->gobj->import_attach;
1435                 dma_buf_unmap_attachment(attach, ttm->sg, DMA_BIDIRECTIONAL);
1436                 ttm->sg = NULL;
1437                 return;
1438         }
1439
1440         if (ttm->page_flags & TTM_PAGE_FLAG_SG)
1441                 return;
1442
1443         adev = amdgpu_ttm_adev(ttm->bdev);
1444
1445 #ifdef CONFIG_SWIOTLB
1446         if (adev->need_swiotlb && swiotlb_nr_tbl()) {
1447                 ttm_dma_unpopulate(&gtt->ttm, adev->dev);
1448                 return;
1449         }
1450 #endif
1451
1452         /* fall back to generic helper to unmap and unpopulate array */
1453         ttm_unmap_and_unpopulate_pages(adev->dev, &gtt->ttm);
1454 }
1455
1456 /**
1457  * amdgpu_ttm_tt_set_userptr - Initialize userptr GTT ttm_tt for the current
1458  * task
1459  *
1460  * @ttm: The ttm_tt object to bind this userptr object to
1461  * @addr:  The address in the current tasks VM space to use
1462  * @flags: Requirements of userptr object.
1463  *
1464  * Called by amdgpu_gem_userptr_ioctl() to bind userptr pages
1465  * to current task
1466  */
1467 int amdgpu_ttm_tt_set_userptr(struct ttm_tt *ttm, uint64_t addr,
1468                               uint32_t flags)
1469 {
1470         struct amdgpu_ttm_tt *gtt = (void *)ttm;
1471
1472         if (gtt == NULL)
1473                 return -EINVAL;
1474
1475         gtt->userptr = addr;
1476         gtt->userflags = flags;
1477
1478         if (gtt->usertask)
1479                 put_task_struct(gtt->usertask);
1480         gtt->usertask = current->group_leader;
1481         get_task_struct(gtt->usertask);
1482
1483         return 0;
1484 }
1485
1486 /**
1487  * amdgpu_ttm_tt_get_usermm - Return memory manager for ttm_tt object
1488  */
1489 struct mm_struct *amdgpu_ttm_tt_get_usermm(struct ttm_tt *ttm)
1490 {
1491         struct amdgpu_ttm_tt *gtt = (void *)ttm;
1492
1493         if (gtt == NULL)
1494                 return NULL;
1495
1496         if (gtt->usertask == NULL)
1497                 return NULL;
1498
1499         return gtt->usertask->mm;
1500 }
1501
1502 /**
1503  * amdgpu_ttm_tt_affect_userptr - Determine if a ttm_tt object lays inside an
1504  * address range for the current task.
1505  *
1506  */
1507 bool amdgpu_ttm_tt_affect_userptr(struct ttm_tt *ttm, unsigned long start,
1508                                   unsigned long end)
1509 {
1510         struct amdgpu_ttm_tt *gtt = (void *)ttm;
1511         unsigned long size;
1512
1513         if (gtt == NULL || !gtt->userptr)
1514                 return false;
1515
1516         /* Return false if no part of the ttm_tt object lies within
1517          * the range
1518          */
1519         size = (unsigned long)gtt->ttm.ttm.num_pages * PAGE_SIZE;
1520         if (gtt->userptr > end || gtt->userptr + size <= start)
1521                 return false;
1522
1523         return true;
1524 }
1525
1526 /**
1527  * amdgpu_ttm_tt_is_userptr - Have the pages backing by userptr?
1528  */
1529 bool amdgpu_ttm_tt_is_userptr(struct ttm_tt *ttm)
1530 {
1531         struct amdgpu_ttm_tt *gtt = (void *)ttm;
1532
1533         if (gtt == NULL || !gtt->userptr)
1534                 return false;
1535
1536         return true;
1537 }
1538
1539 /**
1540  * amdgpu_ttm_tt_is_readonly - Is the ttm_tt object read only?
1541  */
1542 bool amdgpu_ttm_tt_is_readonly(struct ttm_tt *ttm)
1543 {
1544         struct amdgpu_ttm_tt *gtt = (void *)ttm;
1545
1546         if (gtt == NULL)
1547                 return false;
1548
1549         return !!(gtt->userflags & AMDGPU_GEM_USERPTR_READONLY);
1550 }
1551
1552 /**
1553  * amdgpu_ttm_tt_pde_flags - Compute PDE flags for ttm_tt object
1554  *
1555  * @ttm: The ttm_tt object to compute the flags for
1556  * @mem: The memory registry backing this ttm_tt object
1557  *
1558  * Figure out the flags to use for a VM PDE (Page Directory Entry).
1559  */
1560 uint64_t amdgpu_ttm_tt_pde_flags(struct ttm_tt *ttm, struct ttm_mem_reg *mem)
1561 {
1562         uint64_t flags = 0;
1563
1564         if (mem && mem->mem_type != TTM_PL_SYSTEM)
1565                 flags |= AMDGPU_PTE_VALID;
1566
1567         if (mem && mem->mem_type == TTM_PL_TT) {
1568                 flags |= AMDGPU_PTE_SYSTEM;
1569
1570                 if (ttm->caching_state == tt_cached)
1571                         flags |= AMDGPU_PTE_SNOOPED;
1572         }
1573
1574         return flags;
1575 }
1576
1577 /**
1578  * amdgpu_ttm_tt_pte_flags - Compute PTE flags for ttm_tt object
1579  *
1580  * @ttm: The ttm_tt object to compute the flags for
1581  * @mem: The memory registry backing this ttm_tt object
1582
1583  * Figure out the flags to use for a VM PTE (Page Table Entry).
1584  */
1585 uint64_t amdgpu_ttm_tt_pte_flags(struct amdgpu_device *adev, struct ttm_tt *ttm,
1586                                  struct ttm_mem_reg *mem)
1587 {
1588         uint64_t flags = amdgpu_ttm_tt_pde_flags(ttm, mem);
1589
1590         flags |= adev->gart.gart_pte_flags;
1591         flags |= AMDGPU_PTE_READABLE;
1592
1593         if (!amdgpu_ttm_tt_is_readonly(ttm))
1594                 flags |= AMDGPU_PTE_WRITEABLE;
1595
1596         return flags;
1597 }
1598
1599 /**
1600  * amdgpu_ttm_bo_eviction_valuable - Check to see if we can evict a buffer
1601  * object.
1602  *
1603  * Return true if eviction is sensible. Called by ttm_mem_evict_first() on
1604  * behalf of ttm_bo_mem_force_space() which tries to evict buffer objects until
1605  * it can find space for a new object and by ttm_bo_force_list_clean() which is
1606  * used to clean out a memory space.
1607  */
1608 static bool amdgpu_ttm_bo_eviction_valuable(struct ttm_buffer_object *bo,
1609                                             const struct ttm_place *place)
1610 {
1611         unsigned long num_pages = bo->mem.num_pages;
1612         struct drm_mm_node *node = bo->mem.mm_node;
1613         struct dma_resv_list *flist;
1614         struct dma_fence *f;
1615         int i;
1616
1617         if (bo->type == ttm_bo_type_kernel &&
1618             !amdgpu_vm_evictable(ttm_to_amdgpu_bo(bo)))
1619                 return false;
1620
1621         /* If bo is a KFD BO, check if the bo belongs to the current process.
1622          * If true, then return false as any KFD process needs all its BOs to
1623          * be resident to run successfully
1624          */
1625         flist = dma_resv_get_list(bo->base.resv);
1626         if (flist) {
1627                 for (i = 0; i < flist->shared_count; ++i) {
1628                         f = rcu_dereference_protected(flist->shared[i],
1629                                 dma_resv_held(bo->base.resv));
1630                         if (amdkfd_fence_check_mm(f, current->mm))
1631                                 return false;
1632                 }
1633         }
1634
1635         switch (bo->mem.mem_type) {
1636         case TTM_PL_TT:
1637                 if (amdgpu_bo_is_amdgpu_bo(bo) &&
1638                     amdgpu_bo_encrypted(ttm_to_amdgpu_bo(bo)))
1639                         return false;
1640                 return true;
1641
1642         case TTM_PL_VRAM:
1643                 /* Check each drm MM node individually */
1644                 while (num_pages) {
1645                         if (place->fpfn < (node->start + node->size) &&
1646                             !(place->lpfn && place->lpfn <= node->start))
1647                                 return true;
1648
1649                         num_pages -= node->size;
1650                         ++node;
1651                 }
1652                 return false;
1653
1654         default:
1655                 break;
1656         }
1657
1658         return ttm_bo_eviction_valuable(bo, place);
1659 }
1660
1661 /**
1662  * amdgpu_ttm_access_memory - Read or Write memory that backs a buffer object.
1663  *
1664  * @bo:  The buffer object to read/write
1665  * @offset:  Offset into buffer object
1666  * @buf:  Secondary buffer to write/read from
1667  * @len: Length in bytes of access
1668  * @write:  true if writing
1669  *
1670  * This is used to access VRAM that backs a buffer object via MMIO
1671  * access for debugging purposes.
1672  */
1673 static int amdgpu_ttm_access_memory(struct ttm_buffer_object *bo,
1674                                     unsigned long offset,
1675                                     void *buf, int len, int write)
1676 {
1677         struct amdgpu_bo *abo = ttm_to_amdgpu_bo(bo);
1678         struct amdgpu_device *adev = amdgpu_ttm_adev(abo->tbo.bdev);
1679         struct drm_mm_node *nodes;
1680         uint32_t value = 0;
1681         int ret = 0;
1682         uint64_t pos;
1683         unsigned long flags;
1684
1685         if (bo->mem.mem_type != TTM_PL_VRAM)
1686                 return -EIO;
1687
1688         pos = offset;
1689         nodes = amdgpu_find_mm_node(&abo->tbo.mem, &pos);
1690         pos += (nodes->start << PAGE_SHIFT);
1691
1692         while (len && pos < adev->gmc.mc_vram_size) {
1693                 uint64_t aligned_pos = pos & ~(uint64_t)3;
1694                 uint64_t bytes = 4 - (pos & 3);
1695                 uint32_t shift = (pos & 3) * 8;
1696                 uint32_t mask = 0xffffffff << shift;
1697
1698                 if (len < bytes) {
1699                         mask &= 0xffffffff >> (bytes - len) * 8;
1700                         bytes = len;
1701                 }
1702
1703                 if (mask != 0xffffffff) {
1704                         spin_lock_irqsave(&adev->mmio_idx_lock, flags);
1705                         WREG32_NO_KIQ(mmMM_INDEX, ((uint32_t)aligned_pos) | 0x80000000);
1706                         WREG32_NO_KIQ(mmMM_INDEX_HI, aligned_pos >> 31);
1707                         if (!write || mask != 0xffffffff)
1708                                 value = RREG32_NO_KIQ(mmMM_DATA);
1709                         if (write) {
1710                                 value &= ~mask;
1711                                 value |= (*(uint32_t *)buf << shift) & mask;
1712                                 WREG32_NO_KIQ(mmMM_DATA, value);
1713                         }
1714                         spin_unlock_irqrestore(&adev->mmio_idx_lock, flags);
1715                         if (!write) {
1716                                 value = (value & mask) >> shift;
1717                                 memcpy(buf, &value, bytes);
1718                         }
1719                 } else {
1720                         bytes = (nodes->start + nodes->size) << PAGE_SHIFT;
1721                         bytes = min(bytes - pos, (uint64_t)len & ~0x3ull);
1722
1723                         amdgpu_device_vram_access(adev, pos, (uint32_t *)buf,
1724                                                   bytes, write);
1725                 }
1726
1727                 ret += bytes;
1728                 buf = (uint8_t *)buf + bytes;
1729                 pos += bytes;
1730                 len -= bytes;
1731                 if (pos >= (nodes->start + nodes->size) << PAGE_SHIFT) {
1732                         ++nodes;
1733                         pos = (nodes->start << PAGE_SHIFT);
1734                 }
1735         }
1736
1737         return ret;
1738 }
1739
1740 static struct ttm_bo_driver amdgpu_bo_driver = {
1741         .ttm_tt_create = &amdgpu_ttm_tt_create,
1742         .ttm_tt_populate = &amdgpu_ttm_tt_populate,
1743         .ttm_tt_unpopulate = &amdgpu_ttm_tt_unpopulate,
1744         .init_mem_type = &amdgpu_init_mem_type,
1745         .eviction_valuable = amdgpu_ttm_bo_eviction_valuable,
1746         .evict_flags = &amdgpu_evict_flags,
1747         .move = &amdgpu_bo_move,
1748         .verify_access = &amdgpu_verify_access,
1749         .move_notify = &amdgpu_bo_move_notify,
1750         .release_notify = &amdgpu_bo_release_notify,
1751         .fault_reserve_notify = &amdgpu_bo_fault_reserve_notify,
1752         .io_mem_reserve = &amdgpu_ttm_io_mem_reserve,
1753         .io_mem_pfn = amdgpu_ttm_io_mem_pfn,
1754         .access_memory = &amdgpu_ttm_access_memory,
1755         .del_from_lru_notify = &amdgpu_vm_del_from_lru_notify
1756 };
1757
1758 /*
1759  * Firmware Reservation functions
1760  */
1761 /**
1762  * amdgpu_ttm_fw_reserve_vram_fini - free fw reserved vram
1763  *
1764  * @adev: amdgpu_device pointer
1765  *
1766  * free fw reserved vram if it has been reserved.
1767  */
1768 static void amdgpu_ttm_fw_reserve_vram_fini(struct amdgpu_device *adev)
1769 {
1770         amdgpu_bo_free_kernel(&adev->fw_vram_usage.reserved_bo,
1771                 NULL, &adev->fw_vram_usage.va);
1772 }
1773
1774 /**
1775  * amdgpu_ttm_fw_reserve_vram_init - create bo vram reservation from fw
1776  *
1777  * @adev: amdgpu_device pointer
1778  *
1779  * create bo vram reservation from fw.
1780  */
1781 static int amdgpu_ttm_fw_reserve_vram_init(struct amdgpu_device *adev)
1782 {
1783         uint64_t vram_size = adev->gmc.visible_vram_size;
1784
1785         adev->fw_vram_usage.va = NULL;
1786         adev->fw_vram_usage.reserved_bo = NULL;
1787
1788         if (adev->fw_vram_usage.size == 0 ||
1789             adev->fw_vram_usage.size > vram_size)
1790                 return 0;
1791
1792         return amdgpu_bo_create_kernel_at(adev,
1793                                           adev->fw_vram_usage.start_offset,
1794                                           adev->fw_vram_usage.size,
1795                                           AMDGPU_GEM_DOMAIN_VRAM,
1796                                           &adev->fw_vram_usage.reserved_bo,
1797                                           &adev->fw_vram_usage.va);
1798 }
1799
1800 /*
1801  * Memoy training reservation functions
1802  */
1803
1804 /**
1805  * amdgpu_ttm_training_reserve_vram_fini - free memory training reserved vram
1806  *
1807  * @adev: amdgpu_device pointer
1808  *
1809  * free memory training reserved vram if it has been reserved.
1810  */
1811 static int amdgpu_ttm_training_reserve_vram_fini(struct amdgpu_device *adev)
1812 {
1813         struct psp_memory_training_context *ctx = &adev->psp.mem_train_ctx;
1814
1815         ctx->init = PSP_MEM_TRAIN_NOT_SUPPORT;
1816         amdgpu_bo_free_kernel(&ctx->c2p_bo, NULL, NULL);
1817         ctx->c2p_bo = NULL;
1818
1819         return 0;
1820 }
1821
1822 static u64 amdgpu_ttm_training_get_c2p_offset(u64 vram_size)
1823 {
1824        if ((vram_size & (SZ_1M - 1)) < (SZ_4K + 1) )
1825                vram_size -= SZ_1M;
1826
1827        return ALIGN(vram_size, SZ_1M);
1828 }
1829
1830 /**
1831  * amdgpu_ttm_training_reserve_vram_init - create bo vram reservation from memory training
1832  *
1833  * @adev: amdgpu_device pointer
1834  *
1835  * create bo vram reservation from memory training.
1836  */
1837 static int amdgpu_ttm_training_reserve_vram_init(struct amdgpu_device *adev)
1838 {
1839         int ret;
1840         struct psp_memory_training_context *ctx = &adev->psp.mem_train_ctx;
1841
1842         memset(ctx, 0, sizeof(*ctx));
1843         if (!adev->fw_vram_usage.mem_train_support) {
1844                 DRM_DEBUG("memory training does not support!\n");
1845                 return 0;
1846         }
1847
1848         ctx->c2p_train_data_offset = amdgpu_ttm_training_get_c2p_offset(adev->gmc.mc_vram_size);
1849         ctx->p2c_train_data_offset = (adev->gmc.mc_vram_size - GDDR6_MEM_TRAINING_OFFSET);
1850         ctx->train_data_size = GDDR6_MEM_TRAINING_DATA_SIZE_IN_BYTES;
1851
1852         DRM_DEBUG("train_data_size:%llx,p2c_train_data_offset:%llx,c2p_train_data_offset:%llx.\n",
1853                   ctx->train_data_size,
1854                   ctx->p2c_train_data_offset,
1855                   ctx->c2p_train_data_offset);
1856
1857         ret = amdgpu_bo_create_kernel_at(adev,
1858                                          ctx->c2p_train_data_offset,
1859                                          ctx->train_data_size,
1860                                          AMDGPU_GEM_DOMAIN_VRAM,
1861                                          &ctx->c2p_bo,
1862                                          NULL);
1863         if (ret) {
1864                 DRM_ERROR("alloc c2p_bo failed(%d)!\n", ret);
1865                 amdgpu_ttm_training_reserve_vram_fini(adev);
1866                 return ret;
1867         }
1868
1869         ctx->init = PSP_MEM_TRAIN_RESERVE_SUCCESS;
1870         return 0;
1871 }
1872
1873 /**
1874  * amdgpu_ttm_init - Init the memory management (ttm) as well as various
1875  * gtt/vram related fields.
1876  *
1877  * This initializes all of the memory space pools that the TTM layer
1878  * will need such as the GTT space (system memory mapped to the device),
1879  * VRAM (on-board memory), and on-chip memories (GDS, GWS, OA) which
1880  * can be mapped per VMID.
1881  */
1882 int amdgpu_ttm_init(struct amdgpu_device *adev)
1883 {
1884         uint64_t gtt_size;
1885         int r;
1886         u64 vis_vram_limit;
1887         void *stolen_vga_buf;
1888
1889         mutex_init(&adev->mman.gtt_window_lock);
1890
1891         /* No others user of address space so set it to 0 */
1892         r = ttm_bo_device_init(&adev->mman.bdev,
1893                                &amdgpu_bo_driver,
1894                                adev->ddev->anon_inode->i_mapping,
1895                                adev->ddev->vma_offset_manager,
1896                                dma_addressing_limited(adev->dev));
1897         if (r) {
1898                 DRM_ERROR("failed initializing buffer object driver(%d).\n", r);
1899                 return r;
1900         }
1901         adev->mman.initialized = true;
1902
1903         /* We opt to avoid OOM on system pages allocations */
1904         adev->mman.bdev.no_retry = true;
1905
1906         /* Initialize VRAM pool with all of VRAM divided into pages */
1907         r = ttm_bo_init_mm(&adev->mman.bdev, TTM_PL_VRAM,
1908                                 adev->gmc.real_vram_size >> PAGE_SHIFT);
1909         if (r) {
1910                 DRM_ERROR("Failed initializing VRAM heap.\n");
1911                 return r;
1912         }
1913
1914         /* Reduce size of CPU-visible VRAM if requested */
1915         vis_vram_limit = (u64)amdgpu_vis_vram_limit * 1024 * 1024;
1916         if (amdgpu_vis_vram_limit > 0 &&
1917             vis_vram_limit <= adev->gmc.visible_vram_size)
1918                 adev->gmc.visible_vram_size = vis_vram_limit;
1919
1920         /* Change the size here instead of the init above so only lpfn is affected */
1921         amdgpu_ttm_set_buffer_funcs_status(adev, false);
1922 #ifdef CONFIG_64BIT
1923         adev->mman.aper_base_kaddr = ioremap_wc(adev->gmc.aper_base,
1924                                                 adev->gmc.visible_vram_size);
1925 #endif
1926
1927         /*
1928          *The reserved vram for firmware must be pinned to the specified
1929          *place on the VRAM, so reserve it early.
1930          */
1931         r = amdgpu_ttm_fw_reserve_vram_init(adev);
1932         if (r) {
1933                 return r;
1934         }
1935
1936         /*
1937          *The reserved vram for memory training must be pinned to the specified
1938          *place on the VRAM, so reserve it early.
1939          */
1940         if (!amdgpu_sriov_vf(adev)) {
1941                 r = amdgpu_ttm_training_reserve_vram_init(adev);
1942                 if (r)
1943                         return r;
1944         }
1945
1946         /* allocate memory as required for VGA
1947          * This is used for VGA emulation and pre-OS scanout buffers to
1948          * avoid display artifacts while transitioning between pre-OS
1949          * and driver.  */
1950         r = amdgpu_bo_create_kernel(adev, adev->gmc.stolen_size, PAGE_SIZE,
1951                                     AMDGPU_GEM_DOMAIN_VRAM,
1952                                     &adev->stolen_vga_memory,
1953                                     NULL, &stolen_vga_buf);
1954         if (r)
1955                 return r;
1956
1957         /*
1958          * reserve TMR memory at the top of VRAM which holds
1959          * IP Discovery data and is protected by PSP.
1960          */
1961         if (adev->discovery_tmr_size > 0) {
1962                 r = amdgpu_bo_create_kernel_at(adev,
1963                         adev->gmc.real_vram_size - adev->discovery_tmr_size,
1964                         adev->discovery_tmr_size,
1965                         AMDGPU_GEM_DOMAIN_VRAM,
1966                         &adev->discovery_memory,
1967                         NULL);
1968                 if (r)
1969                         return r;
1970         }
1971
1972         DRM_INFO("amdgpu: %uM of VRAM memory ready\n",
1973                  (unsigned) (adev->gmc.real_vram_size / (1024 * 1024)));
1974
1975         /* Compute GTT size, either bsaed on 3/4th the size of RAM size
1976          * or whatever the user passed on module init */
1977         if (amdgpu_gtt_size == -1) {
1978                 struct sysinfo si;
1979
1980                 si_meminfo(&si);
1981                 gtt_size = min(max((AMDGPU_DEFAULT_GTT_SIZE_MB << 20),
1982                                adev->gmc.mc_vram_size),
1983                                ((uint64_t)si.totalram * si.mem_unit * 3/4));
1984         }
1985         else
1986                 gtt_size = (uint64_t)amdgpu_gtt_size << 20;
1987
1988         /* Initialize GTT memory pool */
1989         r = ttm_bo_init_mm(&adev->mman.bdev, TTM_PL_TT, gtt_size >> PAGE_SHIFT);
1990         if (r) {
1991                 DRM_ERROR("Failed initializing GTT heap.\n");
1992                 return r;
1993         }
1994         DRM_INFO("amdgpu: %uM of GTT memory ready.\n",
1995                  (unsigned)(gtt_size / (1024 * 1024)));
1996
1997         /* Initialize various on-chip memory pools */
1998         r = ttm_bo_init_mm(&adev->mman.bdev, AMDGPU_PL_GDS,
1999                            adev->gds.gds_size);
2000         if (r) {
2001                 DRM_ERROR("Failed initializing GDS heap.\n");
2002                 return r;
2003         }
2004
2005         r = ttm_bo_init_mm(&adev->mman.bdev, AMDGPU_PL_GWS,
2006                            adev->gds.gws_size);
2007         if (r) {
2008                 DRM_ERROR("Failed initializing gws heap.\n");
2009                 return r;
2010         }
2011
2012         r = ttm_bo_init_mm(&adev->mman.bdev, AMDGPU_PL_OA,
2013                            adev->gds.oa_size);
2014         if (r) {
2015                 DRM_ERROR("Failed initializing oa heap.\n");
2016                 return r;
2017         }
2018
2019         return 0;
2020 }
2021
2022 /**
2023  * amdgpu_ttm_late_init - Handle any late initialization for amdgpu_ttm
2024  */
2025 void amdgpu_ttm_late_init(struct amdgpu_device *adev)
2026 {
2027         void *stolen_vga_buf;
2028         /* return the VGA stolen memory (if any) back to VRAM */
2029         amdgpu_bo_free_kernel(&adev->stolen_vga_memory, NULL, &stolen_vga_buf);
2030 }
2031
2032 /**
2033  * amdgpu_ttm_fini - De-initialize the TTM memory pools
2034  */
2035 void amdgpu_ttm_fini(struct amdgpu_device *adev)
2036 {
2037         if (!adev->mman.initialized)
2038                 return;
2039
2040         amdgpu_ttm_training_reserve_vram_fini(adev);
2041         /* return the IP Discovery TMR memory back to VRAM */
2042         amdgpu_bo_free_kernel(&adev->discovery_memory, NULL, NULL);
2043         amdgpu_ttm_fw_reserve_vram_fini(adev);
2044
2045         if (adev->mman.aper_base_kaddr)
2046                 iounmap(adev->mman.aper_base_kaddr);
2047         adev->mman.aper_base_kaddr = NULL;
2048
2049         ttm_bo_clean_mm(&adev->mman.bdev, TTM_PL_VRAM);
2050         ttm_bo_clean_mm(&adev->mman.bdev, TTM_PL_TT);
2051         ttm_bo_clean_mm(&adev->mman.bdev, AMDGPU_PL_GDS);
2052         ttm_bo_clean_mm(&adev->mman.bdev, AMDGPU_PL_GWS);
2053         ttm_bo_clean_mm(&adev->mman.bdev, AMDGPU_PL_OA);
2054         ttm_bo_device_release(&adev->mman.bdev);
2055         adev->mman.initialized = false;
2056         DRM_INFO("amdgpu: ttm finalized\n");
2057 }
2058
2059 /**
2060  * amdgpu_ttm_set_buffer_funcs_status - enable/disable use of buffer functions
2061  *
2062  * @adev: amdgpu_device pointer
2063  * @enable: true when we can use buffer functions.
2064  *
2065  * Enable/disable use of buffer functions during suspend/resume. This should
2066  * only be called at bootup or when userspace isn't running.
2067  */
2068 void amdgpu_ttm_set_buffer_funcs_status(struct amdgpu_device *adev, bool enable)
2069 {
2070         struct ttm_mem_type_manager *man = &adev->mman.bdev.man[TTM_PL_VRAM];
2071         uint64_t size;
2072         int r;
2073
2074         if (!adev->mman.initialized || adev->in_gpu_reset ||
2075             adev->mman.buffer_funcs_enabled == enable)
2076                 return;
2077
2078         if (enable) {
2079                 struct amdgpu_ring *ring;
2080                 struct drm_gpu_scheduler *sched;
2081
2082                 ring = adev->mman.buffer_funcs_ring;
2083                 sched = &ring->sched;
2084                 r = drm_sched_entity_init(&adev->mman.entity,
2085                                           DRM_SCHED_PRIORITY_KERNEL, &sched,
2086                                           1, NULL);
2087                 if (r) {
2088                         DRM_ERROR("Failed setting up TTM BO move entity (%d)\n",
2089                                   r);
2090                         return;
2091                 }
2092         } else {
2093                 drm_sched_entity_destroy(&adev->mman.entity);
2094                 dma_fence_put(man->move);
2095                 man->move = NULL;
2096         }
2097
2098         /* this just adjusts TTM size idea, which sets lpfn to the correct value */
2099         if (enable)
2100                 size = adev->gmc.real_vram_size;
2101         else
2102                 size = adev->gmc.visible_vram_size;
2103         man->size = size >> PAGE_SHIFT;
2104         adev->mman.buffer_funcs_enabled = enable;
2105 }
2106
2107 int amdgpu_mmap(struct file *filp, struct vm_area_struct *vma)
2108 {
2109         struct drm_file *file_priv = filp->private_data;
2110         struct amdgpu_device *adev = file_priv->minor->dev->dev_private;
2111
2112         if (adev == NULL)
2113                 return -EINVAL;
2114
2115         return ttm_bo_mmap(filp, vma, &adev->mman.bdev);
2116 }
2117
2118 int amdgpu_copy_buffer(struct amdgpu_ring *ring, uint64_t src_offset,
2119                        uint64_t dst_offset, uint32_t byte_count,
2120                        struct dma_resv *resv,
2121                        struct dma_fence **fence, bool direct_submit,
2122                        bool vm_needs_flush, bool tmz)
2123 {
2124         enum amdgpu_ib_pool_type pool = direct_submit ? AMDGPU_IB_POOL_DIRECT :
2125                 AMDGPU_IB_POOL_DELAYED;
2126         struct amdgpu_device *adev = ring->adev;
2127         struct amdgpu_job *job;
2128
2129         uint32_t max_bytes;
2130         unsigned num_loops, num_dw;
2131         unsigned i;
2132         int r;
2133
2134         if (direct_submit && !ring->sched.ready) {
2135                 DRM_ERROR("Trying to move memory with ring turned off.\n");
2136                 return -EINVAL;
2137         }
2138
2139         max_bytes = adev->mman.buffer_funcs->copy_max_bytes;
2140         num_loops = DIV_ROUND_UP(byte_count, max_bytes);
2141         num_dw = ALIGN(num_loops * adev->mman.buffer_funcs->copy_num_dw, 8);
2142
2143         r = amdgpu_job_alloc_with_ib(adev, num_dw * 4, pool, &job);
2144         if (r)
2145                 return r;
2146
2147         if (vm_needs_flush) {
2148                 job->vm_pd_addr = amdgpu_gmc_pd_addr(adev->gart.bo);
2149                 job->vm_needs_flush = true;
2150         }
2151         if (resv) {
2152                 r = amdgpu_sync_resv(adev, &job->sync, resv,
2153                                      AMDGPU_SYNC_ALWAYS,
2154                                      AMDGPU_FENCE_OWNER_UNDEFINED);
2155                 if (r) {
2156                         DRM_ERROR("sync failed (%d).\n", r);
2157                         goto error_free;
2158                 }
2159         }
2160
2161         for (i = 0; i < num_loops; i++) {
2162                 uint32_t cur_size_in_bytes = min(byte_count, max_bytes);
2163
2164                 amdgpu_emit_copy_buffer(adev, &job->ibs[0], src_offset,
2165                                         dst_offset, cur_size_in_bytes, tmz);
2166
2167                 src_offset += cur_size_in_bytes;
2168                 dst_offset += cur_size_in_bytes;
2169                 byte_count -= cur_size_in_bytes;
2170         }
2171
2172         amdgpu_ring_pad_ib(ring, &job->ibs[0]);
2173         WARN_ON(job->ibs[0].length_dw > num_dw);
2174         if (direct_submit)
2175                 r = amdgpu_job_submit_direct(job, ring, fence);
2176         else
2177                 r = amdgpu_job_submit(job, &adev->mman.entity,
2178                                       AMDGPU_FENCE_OWNER_UNDEFINED, fence);
2179         if (r)
2180                 goto error_free;
2181
2182         return r;
2183
2184 error_free:
2185         amdgpu_job_free(job);
2186         DRM_ERROR("Error scheduling IBs (%d)\n", r);
2187         return r;
2188 }
2189
2190 int amdgpu_fill_buffer(struct amdgpu_bo *bo,
2191                        uint32_t src_data,
2192                        struct dma_resv *resv,
2193                        struct dma_fence **fence)
2194 {
2195         struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
2196         uint32_t max_bytes = adev->mman.buffer_funcs->fill_max_bytes;
2197         struct amdgpu_ring *ring = adev->mman.buffer_funcs_ring;
2198
2199         struct drm_mm_node *mm_node;
2200         unsigned long num_pages;
2201         unsigned int num_loops, num_dw;
2202
2203         struct amdgpu_job *job;
2204         int r;
2205
2206         if (!adev->mman.buffer_funcs_enabled) {
2207                 DRM_ERROR("Trying to clear memory with ring turned off.\n");
2208                 return -EINVAL;
2209         }
2210
2211         if (bo->tbo.mem.mem_type == TTM_PL_TT) {
2212                 r = amdgpu_ttm_alloc_gart(&bo->tbo);
2213                 if (r)
2214                         return r;
2215         }
2216
2217         num_pages = bo->tbo.num_pages;
2218         mm_node = bo->tbo.mem.mm_node;
2219         num_loops = 0;
2220         while (num_pages) {
2221                 uint64_t byte_count = mm_node->size << PAGE_SHIFT;
2222
2223                 num_loops += DIV_ROUND_UP_ULL(byte_count, max_bytes);
2224                 num_pages -= mm_node->size;
2225                 ++mm_node;
2226         }
2227         num_dw = num_loops * adev->mman.buffer_funcs->fill_num_dw;
2228
2229         /* for IB padding */
2230         num_dw += 64;
2231
2232         r = amdgpu_job_alloc_with_ib(adev, num_dw * 4, AMDGPU_IB_POOL_DELAYED,
2233                                      &job);
2234         if (r)
2235                 return r;
2236
2237         if (resv) {
2238                 r = amdgpu_sync_resv(adev, &job->sync, resv,
2239                                      AMDGPU_SYNC_ALWAYS,
2240                                      AMDGPU_FENCE_OWNER_UNDEFINED);
2241                 if (r) {
2242                         DRM_ERROR("sync failed (%d).\n", r);
2243                         goto error_free;
2244                 }
2245         }
2246
2247         num_pages = bo->tbo.num_pages;
2248         mm_node = bo->tbo.mem.mm_node;
2249
2250         while (num_pages) {
2251                 uint64_t byte_count = mm_node->size << PAGE_SHIFT;
2252                 uint64_t dst_addr;
2253
2254                 dst_addr = amdgpu_mm_node_addr(&bo->tbo, mm_node, &bo->tbo.mem);
2255                 while (byte_count) {
2256                         uint32_t cur_size_in_bytes = min_t(uint64_t, byte_count,
2257                                                            max_bytes);
2258
2259                         amdgpu_emit_fill_buffer(adev, &job->ibs[0], src_data,
2260                                                 dst_addr, cur_size_in_bytes);
2261
2262                         dst_addr += cur_size_in_bytes;
2263                         byte_count -= cur_size_in_bytes;
2264                 }
2265
2266                 num_pages -= mm_node->size;
2267                 ++mm_node;
2268         }
2269
2270         amdgpu_ring_pad_ib(ring, &job->ibs[0]);
2271         WARN_ON(job->ibs[0].length_dw > num_dw);
2272         r = amdgpu_job_submit(job, &adev->mman.entity,
2273                               AMDGPU_FENCE_OWNER_UNDEFINED, fence);
2274         if (r)
2275                 goto error_free;
2276
2277         return 0;
2278
2279 error_free:
2280         amdgpu_job_free(job);
2281         return r;
2282 }
2283
2284 #if defined(CONFIG_DEBUG_FS)
2285
2286 static int amdgpu_mm_dump_table(struct seq_file *m, void *data)
2287 {
2288         struct drm_info_node *node = (struct drm_info_node *)m->private;
2289         unsigned ttm_pl = (uintptr_t)node->info_ent->data;
2290         struct drm_device *dev = node->minor->dev;
2291         struct amdgpu_device *adev = dev->dev_private;
2292         struct ttm_mem_type_manager *man = &adev->mman.bdev.man[ttm_pl];
2293         struct drm_printer p = drm_seq_file_printer(m);
2294
2295         man->func->debug(man, &p);
2296         return 0;
2297 }
2298
2299 static const struct drm_info_list amdgpu_ttm_debugfs_list[] = {
2300         {"amdgpu_vram_mm", amdgpu_mm_dump_table, 0, (void *)TTM_PL_VRAM},
2301         {"amdgpu_gtt_mm", amdgpu_mm_dump_table, 0, (void *)TTM_PL_TT},
2302         {"amdgpu_gds_mm", amdgpu_mm_dump_table, 0, (void *)AMDGPU_PL_GDS},
2303         {"amdgpu_gws_mm", amdgpu_mm_dump_table, 0, (void *)AMDGPU_PL_GWS},
2304         {"amdgpu_oa_mm", amdgpu_mm_dump_table, 0, (void *)AMDGPU_PL_OA},
2305         {"ttm_page_pool", ttm_page_alloc_debugfs, 0, NULL},
2306 #ifdef CONFIG_SWIOTLB
2307         {"ttm_dma_page_pool", ttm_dma_page_alloc_debugfs, 0, NULL}
2308 #endif
2309 };
2310
2311 /**
2312  * amdgpu_ttm_vram_read - Linear read access to VRAM
2313  *
2314  * Accesses VRAM via MMIO for debugging purposes.
2315  */
2316 static ssize_t amdgpu_ttm_vram_read(struct file *f, char __user *buf,
2317                                     size_t size, loff_t *pos)
2318 {
2319         struct amdgpu_device *adev = file_inode(f)->i_private;
2320         ssize_t result = 0;
2321
2322         if (size & 0x3 || *pos & 0x3)
2323                 return -EINVAL;
2324
2325         if (*pos >= adev->gmc.mc_vram_size)
2326                 return -ENXIO;
2327
2328         size = min(size, (size_t)(adev->gmc.mc_vram_size - *pos));
2329         while (size) {
2330                 size_t bytes = min(size, AMDGPU_TTM_VRAM_MAX_DW_READ * 4);
2331                 uint32_t value[AMDGPU_TTM_VRAM_MAX_DW_READ];
2332
2333                 amdgpu_device_vram_access(adev, *pos, value, bytes, false);
2334                 if (copy_to_user(buf, value, bytes))
2335                         return -EFAULT;
2336
2337                 result += bytes;
2338                 buf += bytes;
2339                 *pos += bytes;
2340                 size -= bytes;
2341         }
2342
2343         return result;
2344 }
2345
2346 /**
2347  * amdgpu_ttm_vram_write - Linear write access to VRAM
2348  *
2349  * Accesses VRAM via MMIO for debugging purposes.
2350  */
2351 static ssize_t amdgpu_ttm_vram_write(struct file *f, const char __user *buf,
2352                                     size_t size, loff_t *pos)
2353 {
2354         struct amdgpu_device *adev = file_inode(f)->i_private;
2355         ssize_t result = 0;
2356         int r;
2357
2358         if (size & 0x3 || *pos & 0x3)
2359                 return -EINVAL;
2360
2361         if (*pos >= adev->gmc.mc_vram_size)
2362                 return -ENXIO;
2363
2364         while (size) {
2365                 unsigned long flags;
2366                 uint32_t value;
2367
2368                 if (*pos >= adev->gmc.mc_vram_size)
2369                         return result;
2370
2371                 r = get_user(value, (uint32_t *)buf);
2372                 if (r)
2373                         return r;
2374
2375                 spin_lock_irqsave(&adev->mmio_idx_lock, flags);
2376                 WREG32_NO_KIQ(mmMM_INDEX, ((uint32_t)*pos) | 0x80000000);
2377                 WREG32_NO_KIQ(mmMM_INDEX_HI, *pos >> 31);
2378                 WREG32_NO_KIQ(mmMM_DATA, value);
2379                 spin_unlock_irqrestore(&adev->mmio_idx_lock, flags);
2380
2381                 result += 4;
2382                 buf += 4;
2383                 *pos += 4;
2384                 size -= 4;
2385         }
2386
2387         return result;
2388 }
2389
2390 static const struct file_operations amdgpu_ttm_vram_fops = {
2391         .owner = THIS_MODULE,
2392         .read = amdgpu_ttm_vram_read,
2393         .write = amdgpu_ttm_vram_write,
2394         .llseek = default_llseek,
2395 };
2396
2397 #ifdef CONFIG_DRM_AMDGPU_GART_DEBUGFS
2398
2399 /**
2400  * amdgpu_ttm_gtt_read - Linear read access to GTT memory
2401  */
2402 static ssize_t amdgpu_ttm_gtt_read(struct file *f, char __user *buf,
2403                                    size_t size, loff_t *pos)
2404 {
2405         struct amdgpu_device *adev = file_inode(f)->i_private;
2406         ssize_t result = 0;
2407         int r;
2408
2409         while (size) {
2410                 loff_t p = *pos / PAGE_SIZE;
2411                 unsigned off = *pos & ~PAGE_MASK;
2412                 size_t cur_size = min_t(size_t, size, PAGE_SIZE - off);
2413                 struct page *page;
2414                 void *ptr;
2415
2416                 if (p >= adev->gart.num_cpu_pages)
2417                         return result;
2418
2419                 page = adev->gart.pages[p];
2420                 if (page) {
2421                         ptr = kmap(page);
2422                         ptr += off;
2423
2424                         r = copy_to_user(buf, ptr, cur_size);
2425                         kunmap(adev->gart.pages[p]);
2426                 } else
2427                         r = clear_user(buf, cur_size);
2428
2429                 if (r)
2430                         return -EFAULT;
2431
2432                 result += cur_size;
2433                 buf += cur_size;
2434                 *pos += cur_size;
2435                 size -= cur_size;
2436         }
2437
2438         return result;
2439 }
2440
2441 static const struct file_operations amdgpu_ttm_gtt_fops = {
2442         .owner = THIS_MODULE,
2443         .read = amdgpu_ttm_gtt_read,
2444         .llseek = default_llseek
2445 };
2446
2447 #endif
2448
2449 /**
2450  * amdgpu_iomem_read - Virtual read access to GPU mapped memory
2451  *
2452  * This function is used to read memory that has been mapped to the
2453  * GPU and the known addresses are not physical addresses but instead
2454  * bus addresses (e.g., what you'd put in an IB or ring buffer).
2455  */
2456 static ssize_t amdgpu_iomem_read(struct file *f, char __user *buf,
2457                                  size_t size, loff_t *pos)
2458 {
2459         struct amdgpu_device *adev = file_inode(f)->i_private;
2460         struct iommu_domain *dom;
2461         ssize_t result = 0;
2462         int r;
2463
2464         /* retrieve the IOMMU domain if any for this device */
2465         dom = iommu_get_domain_for_dev(adev->dev);
2466
2467         while (size) {
2468                 phys_addr_t addr = *pos & PAGE_MASK;
2469                 loff_t off = *pos & ~PAGE_MASK;
2470                 size_t bytes = PAGE_SIZE - off;
2471                 unsigned long pfn;
2472                 struct page *p;
2473                 void *ptr;
2474
2475                 bytes = bytes < size ? bytes : size;
2476
2477                 /* Translate the bus address to a physical address.  If
2478                  * the domain is NULL it means there is no IOMMU active
2479                  * and the address translation is the identity
2480                  */
2481                 addr = dom ? iommu_iova_to_phys(dom, addr) : addr;
2482
2483                 pfn = addr >> PAGE_SHIFT;
2484                 if (!pfn_valid(pfn))
2485                         return -EPERM;
2486
2487                 p = pfn_to_page(pfn);
2488                 if (p->mapping != adev->mman.bdev.dev_mapping)
2489                         return -EPERM;
2490
2491                 ptr = kmap(p);
2492                 r = copy_to_user(buf, ptr + off, bytes);
2493                 kunmap(p);
2494                 if (r)
2495                         return -EFAULT;
2496
2497                 size -= bytes;
2498                 *pos += bytes;
2499                 result += bytes;
2500         }
2501
2502         return result;
2503 }
2504
2505 /**
2506  * amdgpu_iomem_write - Virtual write access to GPU mapped memory
2507  *
2508  * This function is used to write memory that has been mapped to the
2509  * GPU and the known addresses are not physical addresses but instead
2510  * bus addresses (e.g., what you'd put in an IB or ring buffer).
2511  */
2512 static ssize_t amdgpu_iomem_write(struct file *f, const char __user *buf,
2513                                  size_t size, loff_t *pos)
2514 {
2515         struct amdgpu_device *adev = file_inode(f)->i_private;
2516         struct iommu_domain *dom;
2517         ssize_t result = 0;
2518         int r;
2519
2520         dom = iommu_get_domain_for_dev(adev->dev);
2521
2522         while (size) {
2523                 phys_addr_t addr = *pos & PAGE_MASK;
2524                 loff_t off = *pos & ~PAGE_MASK;
2525                 size_t bytes = PAGE_SIZE - off;
2526                 unsigned long pfn;
2527                 struct page *p;
2528                 void *ptr;
2529
2530                 bytes = bytes < size ? bytes : size;
2531
2532                 addr = dom ? iommu_iova_to_phys(dom, addr) : addr;
2533
2534                 pfn = addr >> PAGE_SHIFT;
2535                 if (!pfn_valid(pfn))
2536                         return -EPERM;
2537
2538                 p = pfn_to_page(pfn);
2539                 if (p->mapping != adev->mman.bdev.dev_mapping)
2540                         return -EPERM;
2541
2542                 ptr = kmap(p);
2543                 r = copy_from_user(ptr + off, buf, bytes);
2544                 kunmap(p);
2545                 if (r)
2546                         return -EFAULT;
2547
2548                 size -= bytes;
2549                 *pos += bytes;
2550                 result += bytes;
2551         }
2552
2553         return result;
2554 }
2555
2556 static const struct file_operations amdgpu_ttm_iomem_fops = {
2557         .owner = THIS_MODULE,
2558         .read = amdgpu_iomem_read,
2559         .write = amdgpu_iomem_write,
2560         .llseek = default_llseek
2561 };
2562
2563 static const struct {
2564         char *name;
2565         const struct file_operations *fops;
2566         int domain;
2567 } ttm_debugfs_entries[] = {
2568         { "amdgpu_vram", &amdgpu_ttm_vram_fops, TTM_PL_VRAM },
2569 #ifdef CONFIG_DRM_AMDGPU_GART_DEBUGFS
2570         { "amdgpu_gtt", &amdgpu_ttm_gtt_fops, TTM_PL_TT },
2571 #endif
2572         { "amdgpu_iomem", &amdgpu_ttm_iomem_fops, TTM_PL_SYSTEM },
2573 };
2574
2575 #endif
2576
2577 int amdgpu_ttm_debugfs_init(struct amdgpu_device *adev)
2578 {
2579 #if defined(CONFIG_DEBUG_FS)
2580         unsigned count;
2581
2582         struct drm_minor *minor = adev->ddev->primary;
2583         struct dentry *ent, *root = minor->debugfs_root;
2584
2585         for (count = 0; count < ARRAY_SIZE(ttm_debugfs_entries); count++) {
2586                 ent = debugfs_create_file(
2587                                 ttm_debugfs_entries[count].name,
2588                                 S_IFREG | S_IRUGO, root,
2589                                 adev,
2590                                 ttm_debugfs_entries[count].fops);
2591                 if (IS_ERR(ent))
2592                         return PTR_ERR(ent);
2593                 if (ttm_debugfs_entries[count].domain == TTM_PL_VRAM)
2594                         i_size_write(ent->d_inode, adev->gmc.mc_vram_size);
2595                 else if (ttm_debugfs_entries[count].domain == TTM_PL_TT)
2596                         i_size_write(ent->d_inode, adev->gmc.gart_size);
2597                 adev->mman.debugfs_entries[count] = ent;
2598         }
2599
2600         count = ARRAY_SIZE(amdgpu_ttm_debugfs_list);
2601
2602 #ifdef CONFIG_SWIOTLB
2603         if (!(adev->need_swiotlb && swiotlb_nr_tbl()))
2604                 --count;
2605 #endif
2606
2607         return amdgpu_debugfs_add_files(adev, amdgpu_ttm_debugfs_list, count);
2608 #else
2609         return 0;
2610 #endif
2611 }