drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c

   1 /*
   2  * Copyright 2009 Jerome Glisse.
   3  * All Rights Reserved.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the
   7  * "Software"), to deal in the Software without restriction, including
   8  * without limitation the rights to use, copy, modify, merge, publish,
   9  * distribute, sub license, and/or sell copies of the Software, and to
  10  * permit persons to whom the Software is furnished to do so, subject to
  11  * the following conditions:
  12  *
  13  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  14  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  15  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  16  * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
  17  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  18  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  19  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  20  *
  21  * The above copyright notice and this permission notice (including the
  22  * next paragraph) shall be included in all copies or substantial portions
  23  * of the Software.
  24  *
  25  */
  26 /*
  27  * Authors:
  28  *    Jerome Glisse <glisse@freedesktop.org>
  29  *    Thomas Hellstrom <thomas-at-tungstengraphics-dot-com>
  30  *    Dave Airlie
  31  */
  32
  33 #include <linux/dma-mapping.h>
  34 #include <linux/iommu.h>
  35 #include <linux/hmm.h>
  36 #include <linux/pagemap.h>
  37 #include <linux/sched/task.h>
  38 #include <linux/sched/mm.h>
  39 #include <linux/seq_file.h>
  40 #include <linux/slab.h>
  41 #include <linux/swap.h>
  42 #include <linux/swiotlb.h>
  43 #include <linux/dma-buf.h>
  44 #include <linux/sizes.h>
  45
  46 #include <drm/ttm/ttm_bo_api.h>
  47 #include <drm/ttm/ttm_bo_driver.h>
  48 #include <drm/ttm/ttm_placement.h>
  49 #include <drm/ttm/ttm_module.h>
  50 #include <drm/ttm/ttm_page_alloc.h>
  51
  52 #include <drm/drm_debugfs.h>
  53 #include <drm/amdgpu_drm.h>
  54
  55 #include "amdgpu.h"
  56 #include "amdgpu_object.h"
  57 #include "amdgpu_trace.h"
  58 #include "amdgpu_amdkfd.h"
  59 #include "amdgpu_sdma.h"
  60 #include "amdgpu_ras.h"
  61 #include "bif/bif_4_1_d.h"
  62
  63 #define AMDGPU_TTM_VRAM_MAX_DW_READ     (size_t)128
  64
  65 static int amdgpu_map_buffer(struct ttm_buffer_object *bo,
  66                              struct ttm_mem_reg *mem, unsigned num_pages,
  67                              uint64_t offset, unsigned window,
  68                              struct amdgpu_ring *ring, bool tmz,
  69                              uint64_t *addr);
  70
  71 /**
  72  * amdgpu_init_mem_type - Initialize a memory manager for a specific type of
  73  * memory request.
  74  *
  75  * @bdev: The TTM BO device object (contains a reference to amdgpu_device)
  76  * @type: The type of memory requested
  77  * @man: The memory type manager for each domain
  78  *
  79  * This is called by ttm_bo_init_mm() when a buffer object is being
  80  * initialized.
  81  */
  82 static int amdgpu_init_mem_type(struct ttm_bo_device *bdev, uint32_t type,
  83                                 struct ttm_mem_type_manager *man)
  84 {
  85         struct amdgpu_device *adev;
  86
  87         adev = amdgpu_ttm_adev(bdev);
  88
  89         switch (type) {
  90         case TTM_PL_SYSTEM:
  91                 /* System memory */
  92                 man->flags = TTM_MEMTYPE_FLAG_MAPPABLE;
  93                 man->available_caching = TTM_PL_MASK_CACHING;
  94                 man->default_caching = TTM_PL_FLAG_CACHED;
  95                 break;
  96         case TTM_PL_TT:
  97                 /* GTT memory  */
  98                 man->func = &amdgpu_gtt_mgr_func;
  99                 man->gpu_offset = adev->gmc.gart_start;
 100                 man->available_caching = TTM_PL_MASK_CACHING;
 101                 man->default_caching = TTM_PL_FLAG_CACHED;
 102                 man->flags = TTM_MEMTYPE_FLAG_MAPPABLE | TTM_MEMTYPE_FLAG_CMA;
 103                 break;
 104         case TTM_PL_VRAM:
 105                 /* "On-card" video ram */
 106                 man->func = &amdgpu_vram_mgr_func;
 107                 man->gpu_offset = adev->gmc.vram_start;
 108                 man->flags = TTM_MEMTYPE_FLAG_FIXED |
 109                              TTM_MEMTYPE_FLAG_MAPPABLE;
 110                 man->available_caching = TTM_PL_FLAG_UNCACHED | TTM_PL_FLAG_WC;
 111                 man->default_caching = TTM_PL_FLAG_WC;
 112                 break;
 113         case AMDGPU_PL_GDS:
 114         case AMDGPU_PL_GWS:
 115         case AMDGPU_PL_OA:
 116                 /* On-chip GDS memory*/
 117                 man->func = &ttm_bo_manager_func;
 118                 man->gpu_offset = 0;
 119                 man->flags = TTM_MEMTYPE_FLAG_FIXED | TTM_MEMTYPE_FLAG_CMA;
 120                 man->available_caching = TTM_PL_FLAG_UNCACHED;
 121                 man->default_caching = TTM_PL_FLAG_UNCACHED;
 122                 break;
 123         default:
 124                 DRM_ERROR("Unsupported memory type %u\n", (unsigned)type);
 125                 return -EINVAL;
 126         }
 127         return 0;
 128 }
 129
 130 /**
 131  * amdgpu_evict_flags - Compute placement flags
 132  *
 133  * @bo: The buffer object to evict
 134  * @placement: Possible destination(s) for evicted BO
 135  *
 136  * Fill in placement data when ttm_bo_evict() is called
 137  */
 138 static void amdgpu_evict_flags(struct ttm_buffer_object *bo,
 139                                 struct ttm_placement *placement)
 140 {
 141         struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev);
 142         struct amdgpu_bo *abo;
 143         static const struct ttm_place placements = {
 144                 .fpfn = 0,
 145                 .lpfn = 0,
 146                 .flags = TTM_PL_MASK_CACHING | TTM_PL_FLAG_SYSTEM
 147         };
 148
 149         /* Don't handle scatter gather BOs */
 150         if (bo->type == ttm_bo_type_sg) {
 151                 placement->num_placement = 0;
 152                 placement->num_busy_placement = 0;
 153                 return;
 154         }
 155
 156         /* Object isn't an AMDGPU object so ignore */
 157         if (!amdgpu_bo_is_amdgpu_bo(bo)) {
 158                 placement->placement = &placements;
 159                 placement->busy_placement = &placements;
 160                 placement->num_placement = 1;
 161                 placement->num_busy_placement = 1;
 162                 return;
 163         }
 164
 165         abo = ttm_to_amdgpu_bo(bo);
 166         switch (bo->mem.mem_type) {
 167         case AMDGPU_PL_GDS:
 168         case AMDGPU_PL_GWS:
 169         case AMDGPU_PL_OA:
 170                 placement->num_placement = 0;
 171                 placement->num_busy_placement = 0;
 172                 return;
 173
 174         case TTM_PL_VRAM:
 175                 if (!adev->mman.buffer_funcs_enabled) {
 176                         /* Move to system memory */
 177                         amdgpu_bo_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_CPU);
 178                 } else if (!amdgpu_gmc_vram_full_visible(&adev->gmc) &&
 179                            !(abo->flags & AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED) &&
 180                            amdgpu_bo_in_cpu_visible_vram(abo)) {
 181
 182                         /* Try evicting to the CPU inaccessible part of VRAM
 183                          * first, but only set GTT as busy placement, so this
 184                          * BO will be evicted to GTT rather than causing other
 185                          * BOs to be evicted from VRAM
 186                          */
 187                         amdgpu_bo_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_VRAM |
 188                                                          AMDGPU_GEM_DOMAIN_GTT);
 189                         abo->placements[0].fpfn = adev->gmc.visible_vram_size >> PAGE_SHIFT;
 190                         abo->placements[0].lpfn = 0;
 191                         abo->placement.busy_placement = &abo->placements[1];
 192                         abo->placement.num_busy_placement = 1;
 193                 } else {
 194                         /* Move to GTT memory */
 195                         amdgpu_bo_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_GTT);
 196                 }
 197                 break;
 198         case TTM_PL_TT:
 199         default:
 200                 amdgpu_bo_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_CPU);
 201                 break;
 202         }
 203         *placement = abo->placement;
 204 }
 205
 206 /**
 207  * amdgpu_verify_access - Verify access for a mmap call
 208  *
 209  * @bo: The buffer object to map
 210  * @filp: The file pointer from the process performing the mmap
 211  *
 212  * This is called by ttm_bo_mmap() to verify whether a process
 213  * has the right to mmap a BO to their process space.
 214  */
 215 static int amdgpu_verify_access(struct ttm_buffer_object *bo, struct file *filp)
 216 {
 217         struct amdgpu_bo *abo = ttm_to_amdgpu_bo(bo);
 218
 219         /*
 220          * Don't verify access for KFD BOs. They don't have a GEM
 221          * object associated with them.
 222          */
 223         if (abo->kfd_bo)
 224                 return 0;
 225
 226         if (amdgpu_ttm_tt_get_usermm(bo->ttm))
 227                 return -EPERM;
 228         return drm_vma_node_verify_access(&abo->tbo.base.vma_node,
 229                                           filp->private_data);
 230 }
 231
 232 /**
 233  * amdgpu_move_null - Register memory for a buffer object
 234  *
 235  * @bo: The bo to assign the memory to
 236  * @new_mem: The memory to be assigned.
 237  *
 238  * Assign the memory from new_mem to the memory of the buffer object bo.
 239  */
 240 static void amdgpu_move_null(struct ttm_buffer_object *bo,
 241                              struct ttm_mem_reg *new_mem)
 242 {
 243         struct ttm_mem_reg *old_mem = &bo->mem;
 244
 245         BUG_ON(old_mem->mm_node != NULL);
 246         *old_mem = *new_mem;
 247         new_mem->mm_node = NULL;
 248 }
 249
 250 /**
 251  * amdgpu_mm_node_addr - Compute the GPU relative offset of a GTT buffer.
 252  *
 253  * @bo: The bo to assign the memory to.
 254  * @mm_node: Memory manager node for drm allocator.
 255  * @mem: The region where the bo resides.
 256  *
 257  */
 258 static uint64_t amdgpu_mm_node_addr(struct ttm_buffer_object *bo,
 259                                     struct drm_mm_node *mm_node,
 260                                     struct ttm_mem_reg *mem)
 261 {
 262         uint64_t addr = 0;
 263
 264         if (mm_node->start != AMDGPU_BO_INVALID_OFFSET) {
 265                 addr = mm_node->start << PAGE_SHIFT;
 266                 addr += bo->bdev->man[mem->mem_type].gpu_offset;
 267         }
 268         return addr;
 269 }
 270
 271 /**
 272  * amdgpu_find_mm_node - Helper function finds the drm_mm_node corresponding to
 273  * @offset. It also modifies the offset to be within the drm_mm_node returned
 274  *
 275  * @mem: The region where the bo resides.
 276  * @offset: The offset that drm_mm_node is used for finding.
 277  *
 278  */
 279 static struct drm_mm_node *amdgpu_find_mm_node(struct ttm_mem_reg *mem,
 280                                                unsigned long *offset)
 281 {
 282         struct drm_mm_node *mm_node = mem->mm_node;
 283
 284         while (*offset >= (mm_node->size << PAGE_SHIFT)) {
 285                 *offset -= (mm_node->size << PAGE_SHIFT);
 286                 ++mm_node;
 287         }
 288         return mm_node;
 289 }
 290
 291 /**
 292  * amdgpu_copy_ttm_mem_to_mem - Helper function for copy
 293  * @adev: amdgpu device
 294  * @src: buffer/address where to read from
 295  * @dst: buffer/address where to write to
 296  * @size: number of bytes to copy
 297  * @tmz: if a secure copy should be used
 298  * @resv: resv object to sync to
 299  * @f: Returns the last fence if multiple jobs are submitted.
 300  *
 301  * The function copies @size bytes from {src->mem + src->offset} to
 302  * {dst->mem + dst->offset}. src->bo and dst->bo could be same BO for a
 303  * move and different for a BO to BO copy.
 304  *
 305  */
 306 int amdgpu_ttm_copy_mem_to_mem(struct amdgpu_device *adev,
 307                                struct amdgpu_copy_mem *src,
 308                                struct amdgpu_copy_mem *dst,
 309                                uint64_t size, bool tmz,
 310                                struct dma_resv *resv,
 311                                struct dma_fence **f)
 312 {
 313         struct amdgpu_ring *ring = adev->mman.buffer_funcs_ring;
 314         struct drm_mm_node *src_mm, *dst_mm;
 315         uint64_t src_node_start, dst_node_start, src_node_size,
 316                  dst_node_size, src_page_offset, dst_page_offset;
 317         struct dma_fence *fence = NULL;
 318         int r = 0;
 319         const uint64_t GTT_MAX_BYTES = (AMDGPU_GTT_MAX_TRANSFER_SIZE *
 320                                         AMDGPU_GPU_PAGE_SIZE);
 321
 322         if (!adev->mman.buffer_funcs_enabled) {
 323                 DRM_ERROR("Trying to move memory with ring turned off.\n");
 324                 return -EINVAL;
 325         }
 326
 327         src_mm = amdgpu_find_mm_node(src->mem, &src->offset);
 328         src_node_start = amdgpu_mm_node_addr(src->bo, src_mm, src->mem) +
 329                                              src->offset;
 330         src_node_size = (src_mm->size << PAGE_SHIFT) - src->offset;
 331         src_page_offset = src_node_start & (PAGE_SIZE - 1);
 332
 333         dst_mm = amdgpu_find_mm_node(dst->mem, &dst->offset);
 334         dst_node_start = amdgpu_mm_node_addr(dst->bo, dst_mm, dst->mem) +
 335                                              dst->offset;
 336         dst_node_size = (dst_mm->size << PAGE_SHIFT) - dst->offset;
 337         dst_page_offset = dst_node_start & (PAGE_SIZE - 1);
 338
 339         mutex_lock(&adev->mman.gtt_window_lock);
 340
 341         while (size) {
 342                 unsigned long cur_size;
 343                 uint64_t from = src_node_start, to = dst_node_start;
 344                 struct dma_fence *next;
 345
 346                 /* Copy size cannot exceed GTT_MAX_BYTES. So if src or dst
 347                  * begins at an offset, then adjust the size accordingly
 348                  */
 349                 cur_size = min3(min(src_node_size, dst_node_size), size,
 350                                 GTT_MAX_BYTES);
 351                 if (cur_size + src_page_offset > GTT_MAX_BYTES ||
 352                     cur_size + dst_page_offset > GTT_MAX_BYTES)
 353                         cur_size -= max(src_page_offset, dst_page_offset);
 354
 355                 /* Map only what needs to be accessed. Map src to window 0 and
 356                  * dst to window 1
 357                  */
 358                 if (src->mem->start == AMDGPU_BO_INVALID_OFFSET) {
 359                         r = amdgpu_map_buffer(src->bo, src->mem,
 360                                         PFN_UP(cur_size + src_page_offset),
 361                                         src_node_start, 0, ring, tmz,
 362                                         &from);
 363                         if (r)
 364                                 goto error;
 365                         /* Adjust the offset because amdgpu_map_buffer returns
 366                          * start of mapped page
 367                          */
 368                         from += src_page_offset;
 369                 }
 370
 371                 if (dst->mem->start == AMDGPU_BO_INVALID_OFFSET) {
 372                         r = amdgpu_map_buffer(dst->bo, dst->mem,
 373                                         PFN_UP(cur_size + dst_page_offset),
 374                                         dst_node_start, 1, ring, tmz,
 375                                         &to);
 376                         if (r)
 377                                 goto error;
 378                         to += dst_page_offset;
 379                 }
 380
 381                 r = amdgpu_copy_buffer(ring, from, to, cur_size,
 382                                        resv, &next, false, true, tmz);
 383                 if (r)
 384                         goto error;
 385
 386                 dma_fence_put(fence);
 387                 fence = next;
 388
 389                 size -= cur_size;
 390                 if (!size)
 391                         break;
 392
 393                 src_node_size -= cur_size;
 394                 if (!src_node_size) {
 395                         src_node_start = amdgpu_mm_node_addr(src->bo, ++src_mm,
 396                                                              src->mem);
 397                         src_node_size = (src_mm->size << PAGE_SHIFT);
 398                         src_page_offset = 0;
 399                 } else {
 400                         src_node_start += cur_size;
 401                         src_page_offset = src_node_start & (PAGE_SIZE - 1);
 402                 }
 403                 dst_node_size -= cur_size;
 404                 if (!dst_node_size) {
 405                         dst_node_start = amdgpu_mm_node_addr(dst->bo, ++dst_mm,
 406                                                              dst->mem);
 407                         dst_node_size = (dst_mm->size << PAGE_SHIFT);
 408                         dst_page_offset = 0;
 409                 } else {
 410                         dst_node_start += cur_size;
 411                         dst_page_offset = dst_node_start & (PAGE_SIZE - 1);
 412                 }
 413         }
 414 error:
 415         mutex_unlock(&adev->mman.gtt_window_lock);
 416         if (f)
 417                 *f = dma_fence_get(fence);
 418         dma_fence_put(fence);
 419         return r;
 420 }
 421
 422 /**
 423  * amdgpu_move_blit - Copy an entire buffer to another buffer
 424  *
 425  * This is a helper called by amdgpu_bo_move() and amdgpu_move_vram_ram() to
 426  * help move buffers to and from VRAM.
 427  */
 428 static int amdgpu_move_blit(struct ttm_buffer_object *bo,
 429                             bool evict, bool no_wait_gpu,
 430                             struct ttm_mem_reg *new_mem,
 431                             struct ttm_mem_reg *old_mem)
 432 {
 433         struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev);
 434         struct amdgpu_bo *abo = ttm_to_amdgpu_bo(bo);
 435         struct amdgpu_copy_mem src, dst;
 436         struct dma_fence *fence = NULL;
 437         int r;
 438
 439         src.bo = bo;
 440         dst.bo = bo;
 441         src.mem = old_mem;
 442         dst.mem = new_mem;
 443         src.offset = 0;
 444         dst.offset = 0;
 445
 446         r = amdgpu_ttm_copy_mem_to_mem(adev, &src, &dst,
 447                                        new_mem->num_pages << PAGE_SHIFT,
 448                                        amdgpu_bo_encrypted(abo),
 449                                        bo->base.resv, &fence);
 450         if (r)
 451                 goto error;
 452
 453         /* clear the space being freed */
 454         if (old_mem->mem_type == TTM_PL_VRAM &&
 455             (abo->flags & AMDGPU_GEM_CREATE_VRAM_WIPE_ON_RELEASE)) {
 456                 struct dma_fence *wipe_fence = NULL;
 457
 458                 r = amdgpu_fill_buffer(ttm_to_amdgpu_bo(bo), AMDGPU_POISON,
 459                                        NULL, &wipe_fence);
 460                 if (r) {
 461                         goto error;
 462                 } else if (wipe_fence) {
 463                         dma_fence_put(fence);
 464                         fence = wipe_fence;
 465                 }
 466         }
 467
 468         /* Always block for VM page tables before committing the new location */
 469         if (bo->type == ttm_bo_type_kernel)
 470                 r = ttm_bo_move_accel_cleanup(bo, fence, true, new_mem);
 471         else
 472                 r = ttm_bo_pipeline_move(bo, fence, evict, new_mem);
 473         dma_fence_put(fence);
 474         return r;
 475
 476 error:
 477         if (fence)
 478                 dma_fence_wait(fence, false);
 479         dma_fence_put(fence);
 480         return r;
 481 }
 482
 483 /**
 484  * amdgpu_move_vram_ram - Copy VRAM buffer to RAM buffer
 485  *
 486  * Called by amdgpu_bo_move().
 487  */
 488 static int amdgpu_move_vram_ram(struct ttm_buffer_object *bo, bool evict,
 489                                 struct ttm_operation_ctx *ctx,
 490                                 struct ttm_mem_reg *new_mem)
 491 {
 492         struct ttm_mem_reg *old_mem = &bo->mem;
 493         struct ttm_mem_reg tmp_mem;
 494         struct ttm_place placements;
 495         struct ttm_placement placement;
 496         int r;
 497
 498         /* create space/pages for new_mem in GTT space */
 499         tmp_mem = *new_mem;
 500         tmp_mem.mm_node = NULL;
 501         placement.num_placement = 1;
 502         placement.placement = &placements;
 503         placement.num_busy_placement = 1;
 504         placement.busy_placement = &placements;
 505         placements.fpfn = 0;
 506         placements.lpfn = 0;
 507         placements.flags = TTM_PL_MASK_CACHING | TTM_PL_FLAG_TT;
 508         r = ttm_bo_mem_space(bo, &placement, &tmp_mem, ctx);
 509         if (unlikely(r)) {
 510                 pr_err("Failed to find GTT space for blit from VRAM\n");
 511                 return r;
 512         }
 513
 514         /* set caching flags */
 515         r = ttm_tt_set_placement_caching(bo->ttm, tmp_mem.placement);
 516         if (unlikely(r)) {
 517                 goto out_cleanup;
 518         }
 519
 520         /* Bind the memory to the GTT space */
 521         r = ttm_tt_bind(bo->ttm, &tmp_mem, ctx);
 522         if (unlikely(r)) {
 523                 goto out_cleanup;
 524         }
 525
 526         /* blit VRAM to GTT */
 527         r = amdgpu_move_blit(bo, evict, ctx->no_wait_gpu, &tmp_mem, old_mem);
 528         if (unlikely(r)) {
 529                 goto out_cleanup;
 530         }
 531
 532         /* move BO (in tmp_mem) to new_mem */
 533         r = ttm_bo_move_ttm(bo, ctx, new_mem);
 534 out_cleanup:
 535         ttm_bo_mem_put(bo, &tmp_mem);
 536         return r;
 537 }
 538
 539 /**
 540  * amdgpu_move_ram_vram - Copy buffer from RAM to VRAM
 541  *
 542  * Called by amdgpu_bo_move().
 543  */
 544 static int amdgpu_move_ram_vram(struct ttm_buffer_object *bo, bool evict,
 545                                 struct ttm_operation_ctx *ctx,
 546                                 struct ttm_mem_reg *new_mem)
 547 {
 548         struct ttm_mem_reg *old_mem = &bo->mem;
 549         struct ttm_mem_reg tmp_mem;
 550         struct ttm_placement placement;
 551         struct ttm_place placements;
 552         int r;
 553
 554         /* make space in GTT for old_mem buffer */
 555         tmp_mem = *new_mem;
 556         tmp_mem.mm_node = NULL;
 557         placement.num_placement = 1;
 558         placement.placement = &placements;
 559         placement.num_busy_placement = 1;
 560         placement.busy_placement = &placements;
 561         placements.fpfn = 0;
 562         placements.lpfn = 0;
 563         placements.flags = TTM_PL_MASK_CACHING | TTM_PL_FLAG_TT;
 564         r = ttm_bo_mem_space(bo, &placement, &tmp_mem, ctx);
 565         if (unlikely(r)) {
 566                 pr_err("Failed to find GTT space for blit to VRAM\n");
 567                 return r;
 568         }
 569
 570         /* move/bind old memory to GTT space */
 571         r = ttm_bo_move_ttm(bo, ctx, &tmp_mem);
 572         if (unlikely(r)) {
 573                 goto out_cleanup;
 574         }
 575
 576         /* copy to VRAM */
 577         r = amdgpu_move_blit(bo, evict, ctx->no_wait_gpu, new_mem, old_mem);
 578         if (unlikely(r)) {
 579                 goto out_cleanup;
 580         }
 581 out_cleanup:
 582         ttm_bo_mem_put(bo, &tmp_mem);
 583         return r;
 584 }
 585
 586 /**
 587  * amdgpu_mem_visible - Check that memory can be accessed by ttm_bo_move_memcpy
 588  *
 589  * Called by amdgpu_bo_move()
 590  */
 591 static bool amdgpu_mem_visible(struct amdgpu_device *adev,
 592                                struct ttm_mem_reg *mem)
 593 {
 594         struct drm_mm_node *nodes = mem->mm_node;
 595
 596         if (mem->mem_type == TTM_PL_SYSTEM ||
 597             mem->mem_type == TTM_PL_TT)
 598                 return true;
 599         if (mem->mem_type != TTM_PL_VRAM)
 600                 return false;
 601
 602         /* ttm_mem_reg_ioremap only supports contiguous memory */
 603         if (nodes->size != mem->num_pages)
 604                 return false;
 605
 606         return ((nodes->start + nodes->size) << PAGE_SHIFT)
 607                 <= adev->gmc.visible_vram_size;
 608 }
 609
 610 /**
 611  * amdgpu_bo_move - Move a buffer object to a new memory location
 612  *
 613  * Called by ttm_bo_handle_move_mem()
 614  */
 615 static int amdgpu_bo_move(struct ttm_buffer_object *bo, bool evict,
 616                           struct ttm_operation_ctx *ctx,
 617                           struct ttm_mem_reg *new_mem)
 618 {
 619         struct amdgpu_device *adev;
 620         struct amdgpu_bo *abo;
 621         struct ttm_mem_reg *old_mem = &bo->mem;
 622         int r;
 623
 624         /* Can't move a pinned BO */
 625         abo = ttm_to_amdgpu_bo(bo);
 626         if (WARN_ON_ONCE(abo->pin_count > 0))
 627                 return -EINVAL;
 628
 629         adev = amdgpu_ttm_adev(bo->bdev);
 630
 631         if (old_mem->mem_type == TTM_PL_SYSTEM && bo->ttm == NULL) {
 632                 amdgpu_move_null(bo, new_mem);
 633                 return 0;
 634         }
 635         if ((old_mem->mem_type == TTM_PL_TT &&
 636              new_mem->mem_type == TTM_PL_SYSTEM) ||
 637             (old_mem->mem_type == TTM_PL_SYSTEM &&
 638              new_mem->mem_type == TTM_PL_TT)) {
 639                 /* bind is enough */
 640                 amdgpu_move_null(bo, new_mem);
 641                 return 0;
 642         }
 643         if (old_mem->mem_type == AMDGPU_PL_GDS ||
 644             old_mem->mem_type == AMDGPU_PL_GWS ||
 645             old_mem->mem_type == AMDGPU_PL_OA ||
 646             new_mem->mem_type == AMDGPU_PL_GDS ||
 647             new_mem->mem_type == AMDGPU_PL_GWS ||
 648             new_mem->mem_type == AMDGPU_PL_OA) {
 649                 /* Nothing to save here */
 650                 amdgpu_move_null(bo, new_mem);
 651                 return 0;
 652         }
 653
 654         if (!adev->mman.buffer_funcs_enabled) {
 655                 r = -ENODEV;
 656                 goto memcpy;
 657         }
 658
 659         if (old_mem->mem_type == TTM_PL_VRAM &&
 660             new_mem->mem_type == TTM_PL_SYSTEM) {
 661                 r = amdgpu_move_vram_ram(bo, evict, ctx, new_mem);
 662         } else if (old_mem->mem_type == TTM_PL_SYSTEM &&
 663                    new_mem->mem_type == TTM_PL_VRAM) {
 664                 r = amdgpu_move_ram_vram(bo, evict, ctx, new_mem);
 665         } else {
 666                 r = amdgpu_move_blit(bo, evict, ctx->no_wait_gpu,
 667                                      new_mem, old_mem);
 668         }
 669
 670         if (r) {
 671 memcpy:
 672                 /* Check that all memory is CPU accessible */
 673                 if (!amdgpu_mem_visible(adev, old_mem) ||
 674                     !amdgpu_mem_visible(adev, new_mem)) {
 675                         pr_err("Move buffer fallback to memcpy unavailable\n");
 676                         return r;
 677                 }
 678
 679                 r = ttm_bo_move_memcpy(bo, ctx, new_mem);
 680                 if (r)
 681                         return r;
 682         }
 683
 684         if (bo->type == ttm_bo_type_device &&
 685             new_mem->mem_type == TTM_PL_VRAM &&
 686             old_mem->mem_type != TTM_PL_VRAM) {
 687                 /* amdgpu_bo_fault_reserve_notify will re-set this if the CPU
 688                  * accesses the BO after it's moved.
 689                  */
 690                 abo->flags &= ~AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED;
 691         }
 692
 693         /* update statistics */
 694         atomic64_add((u64)bo->num_pages << PAGE_SHIFT, &adev->num_bytes_moved);
 695         return 0;
 696 }
 697
 698 /**
 699  * amdgpu_ttm_io_mem_reserve - Reserve a block of memory during a fault
 700  *
 701  * Called by ttm_mem_io_reserve() ultimately via ttm_bo_vm_fault()
 702  */
 703 static int amdgpu_ttm_io_mem_reserve(struct ttm_bo_device *bdev, struct ttm_mem_reg *mem)
 704 {
 705         struct ttm_mem_type_manager *man = &bdev->man[mem->mem_type];
 706         struct amdgpu_device *adev = amdgpu_ttm_adev(bdev);
 707         struct drm_mm_node *mm_node = mem->mm_node;
 708
 709         mem->bus.addr = NULL;
 710         mem->bus.offset = 0;
 711         mem->bus.size = mem->num_pages << PAGE_SHIFT;
 712         mem->bus.base = 0;
 713         mem->bus.is_iomem = false;
 714         if (!(man->flags & TTM_MEMTYPE_FLAG_MAPPABLE))
 715                 return -EINVAL;
 716         switch (mem->mem_type) {
 717         case TTM_PL_SYSTEM:
 718                 /* system memory */
 719                 return 0;
 720         case TTM_PL_TT:
 721                 break;
 722         case TTM_PL_VRAM:
 723                 mem->bus.offset = mem->start << PAGE_SHIFT;
 724                 /* check if it's visible */
 725                 if ((mem->bus.offset + mem->bus.size) > adev->gmc.visible_vram_size)
 726                         return -EINVAL;
 727                 /* Only physically contiguous buffers apply. In a contiguous
 728                  * buffer, size of the first mm_node would match the number of
 729                  * pages in ttm_mem_reg.
 730                  */
 731                 if (adev->mman.aper_base_kaddr &&
 732                     (mm_node->size == mem->num_pages))
 733                         mem->bus.addr = (u8 *)adev->mman.aper_base_kaddr +
 734                                         mem->bus.offset;
 735
 736                 mem->bus.base = adev->gmc.aper_base;
 737                 mem->bus.is_iomem = true;
 738                 break;
 739         default:
 740                 return -EINVAL;
 741         }
 742         return 0;
 743 }
 744
 745 static void amdgpu_ttm_io_mem_free(struct ttm_bo_device *bdev, struct ttm_mem_reg *mem)
 746 {
 747 }
 748
 749 static unsigned long amdgpu_ttm_io_mem_pfn(struct ttm_buffer_object *bo,
 750                                            unsigned long page_offset)
 751 {
 752         struct drm_mm_node *mm;
 753         unsigned long offset = (page_offset << PAGE_SHIFT);
 754
 755         mm = amdgpu_find_mm_node(&bo->mem, &offset);
 756         return (bo->mem.bus.base >> PAGE_SHIFT) + mm->start +
 757                 (offset >> PAGE_SHIFT);
 758 }
 759
 760 /*
 761  * TTM backend functions.
 762  */
 763 struct amdgpu_ttm_tt {
 764         struct ttm_dma_tt       ttm;
 765         struct drm_gem_object   *gobj;
 766         u64                     offset;
 767         uint64_t                userptr;
 768         struct task_struct      *usertask;
 769         uint32_t                userflags;
 770 #if IS_ENABLED(CONFIG_DRM_AMDGPU_USERPTR)
 771         struct hmm_range        *range;
 772 #endif
 773 };
 774
 775 #ifdef CONFIG_DRM_AMDGPU_USERPTR
 776 /* flags used by HMM internal, not related to CPU/GPU PTE flags */
 777 static const uint64_t hmm_range_flags[HMM_PFN_FLAG_MAX] = {
 778         (1 << 0), /* HMM_PFN_VALID */
 779         (1 << 1), /* HMM_PFN_WRITE */
 780         0 /* HMM_PFN_DEVICE_PRIVATE */
 781 };
 782
 783 static const uint64_t hmm_range_values[HMM_PFN_VALUE_MAX] = {
 784         0xfffffffffffffffeUL, /* HMM_PFN_ERROR */
 785         0, /* HMM_PFN_NONE */
 786         0xfffffffffffffffcUL /* HMM_PFN_SPECIAL */
 787 };
 788
 789 /**
 790  * amdgpu_ttm_tt_get_user_pages - get device accessible pages that back user
 791  * memory and start HMM tracking CPU page table update
 792  *
 793  * Calling function must call amdgpu_ttm_tt_userptr_range_done() once and only
 794  * once afterwards to stop HMM tracking
 795  */
 796 int amdgpu_ttm_tt_get_user_pages(struct amdgpu_bo *bo, struct page **pages)
 797 {
 798         struct ttm_tt *ttm = bo->tbo.ttm;
 799         struct amdgpu_ttm_tt *gtt = (void *)ttm;
 800         unsigned long start = gtt->userptr;
 801         struct vm_area_struct *vma;
 802         struct hmm_range *range;
 803         unsigned long timeout;
 804         struct mm_struct *mm;
 805         unsigned long i;
 806         int r = 0;
 807
 808         mm = bo->notifier.mm;
 809         if (unlikely(!mm)) {
 810                 DRM_DEBUG_DRIVER("BO is not registered?\n");
 811                 return -EFAULT;
 812         }
 813
 814         /* Another get_user_pages is running at the same time?? */
 815         if (WARN_ON(gtt->range))
 816                 return -EFAULT;
 817
 818         if (!mmget_not_zero(mm)) /* Happens during process shutdown */
 819                 return -ESRCH;
 820
 821         range = kzalloc(sizeof(*range), GFP_KERNEL);
 822         if (unlikely(!range)) {
 823                 r = -ENOMEM;
 824                 goto out;
 825         }
 826         range->notifier = &bo->notifier;
 827         range->flags = hmm_range_flags;
 828         range->values = hmm_range_values;
 829         range->pfn_shift = PAGE_SHIFT;
 830         range->start = bo->notifier.interval_tree.start;
 831         range->end = bo->notifier.interval_tree.last + 1;
 832         range->default_flags = hmm_range_flags[HMM_PFN_VALID];
 833         if (!amdgpu_ttm_tt_is_readonly(ttm))
 834                 range->default_flags |= range->flags[HMM_PFN_WRITE];
 835
 836         range->pfns = kvmalloc_array(ttm->num_pages, sizeof(*range->pfns),
 837                                      GFP_KERNEL);
 838         if (unlikely(!range->pfns)) {
 839                 r = -ENOMEM;
 840                 goto out_free_ranges;
 841         }
 842
 843         down_read(&mm->mmap_sem);
 844         vma = find_vma(mm, start);
 845         if (unlikely(!vma || start < vma->vm_start)) {
 846                 r = -EFAULT;
 847                 goto out_unlock;
 848         }
 849         if (unlikely((gtt->userflags & AMDGPU_GEM_USERPTR_ANONONLY) &&
 850                 vma->vm_file)) {
 851                 r = -EPERM;
 852                 goto out_unlock;
 853         }
 854         up_read(&mm->mmap_sem);
 855         timeout = jiffies + msecs_to_jiffies(HMM_RANGE_DEFAULT_TIMEOUT);
 856
 857 retry:
 858         range->notifier_seq = mmu_interval_read_begin(&bo->notifier);
 859
 860         down_read(&mm->mmap_sem);
 861         r = hmm_range_fault(range, 0);
 862         up_read(&mm->mmap_sem);
 863         if (unlikely(r <= 0)) {
 864                 /*
 865                  * FIXME: This timeout should encompass the retry from
 866                  * mmu_interval_read_retry() as well.
 867                  */
 868                 if ((r == 0 || r == -EBUSY) && !time_after(jiffies, timeout))
 869                         goto retry;
 870                 goto out_free_pfns;
 871         }
 872
 873         for (i = 0; i < ttm->num_pages; i++) {
 874                 /* FIXME: The pages cannot be touched outside the notifier_lock */
 875                 pages[i] = hmm_device_entry_to_page(range, range->pfns[i]);
 876                 if (unlikely(!pages[i])) {
 877                         pr_err("Page fault failed for pfn[%lu] = 0x%llx\n",
 878                                i, range->pfns[i]);
 879                         r = -ENOMEM;
 880
 881                         goto out_free_pfns;
 882                 }
 883         }
 884
 885         gtt->range = range;
 886         mmput(mm);
 887
 888         return 0;
 889
 890 out_unlock:
 891         up_read(&mm->mmap_sem);
 892 out_free_pfns:
 893         kvfree(range->pfns);
 894 out_free_ranges:
 895         kfree(range);
 896 out:
 897         mmput(mm);
 898         return r;
 899 }
 900
 901 /**
 902  * amdgpu_ttm_tt_userptr_range_done - stop HMM track the CPU page table change
 903  * Check if the pages backing this ttm range have been invalidated
 904  *
 905  * Returns: true if pages are still valid
 906  */
 907 bool amdgpu_ttm_tt_get_user_pages_done(struct ttm_tt *ttm)
 908 {
 909         struct amdgpu_ttm_tt *gtt = (void *)ttm;
 910         bool r = false;
 911
 912         if (!gtt || !gtt->userptr)
 913                 return false;
 914
 915         DRM_DEBUG_DRIVER("user_pages_done 0x%llx pages 0x%lx\n",
 916                 gtt->userptr, ttm->num_pages);
 917
 918         WARN_ONCE(!gtt->range || !gtt->range->pfns,
 919                 "No user pages to check\n");
 920
 921         if (gtt->range) {
 922                 /*
 923                  * FIXME: Must always hold notifier_lock for this, and must
 924                  * not ignore the return code.
 925                  */
 926                 r = mmu_interval_read_retry(gtt->range->notifier,
 927                                          gtt->range->notifier_seq);
 928                 kvfree(gtt->range->pfns);
 929                 kfree(gtt->range);
 930                 gtt->range = NULL;
 931         }
 932
 933         return !r;
 934 }
 935 #endif
 936
 937 /**
 938  * amdgpu_ttm_tt_set_user_pages - Copy pages in, putting old pages as necessary.
 939  *
 940  * Called by amdgpu_cs_list_validate(). This creates the page list
 941  * that backs user memory and will ultimately be mapped into the device
 942  * address space.
 943  */
 944 void amdgpu_ttm_tt_set_user_pages(struct ttm_tt *ttm, struct page **pages)
 945 {
 946         unsigned long i;
 947
 948         for (i = 0; i < ttm->num_pages; ++i)
 949                 ttm->pages[i] = pages ? pages[i] : NULL;
 950 }
 951
 952 /**
 953  * amdgpu_ttm_tt_pin_userptr -  prepare the sg table with the user pages
 954  *
 955  * Called by amdgpu_ttm_backend_bind()
 956  **/
 957 static int amdgpu_ttm_tt_pin_userptr(struct ttm_tt *ttm)
 958 {
 959         struct amdgpu_device *adev = amdgpu_ttm_adev(ttm->bdev);
 960         struct amdgpu_ttm_tt *gtt = (void *)ttm;
 961         unsigned nents;
 962         int r;
 963
 964         int write = !(gtt->userflags & AMDGPU_GEM_USERPTR_READONLY);
 965         enum dma_data_direction direction = write ?
 966                 DMA_BIDIRECTIONAL : DMA_TO_DEVICE;
 967
 968         /* Allocate an SG array and squash pages into it */
 969         r = sg_alloc_table_from_pages(ttm->sg, ttm->pages, ttm->num_pages, 0,
 970                                       ttm->num_pages << PAGE_SHIFT,
 971                                       GFP_KERNEL);
 972         if (r)
 973                 goto release_sg;
 974
 975         /* Map SG to device */
 976         r = -ENOMEM;
 977         nents = dma_map_sg(adev->dev, ttm->sg->sgl, ttm->sg->nents, direction);
 978         if (nents == 0)
 979                 goto release_sg;
 980
 981         /* convert SG to linear array of pages and dma addresses */
 982         drm_prime_sg_to_page_addr_arrays(ttm->sg, ttm->pages,
 983                                          gtt->ttm.dma_address, ttm->num_pages);
 984
 985         return 0;
 986
 987 release_sg:
 988         kfree(ttm->sg);
 989         return r;
 990 }
 991
 992 /**
 993  * amdgpu_ttm_tt_unpin_userptr - Unpin and unmap userptr pages
 994  */
 995 static void amdgpu_ttm_tt_unpin_userptr(struct ttm_tt *ttm)
 996 {
 997         struct amdgpu_device *adev = amdgpu_ttm_adev(ttm->bdev);
 998         struct amdgpu_ttm_tt *gtt = (void *)ttm;
 999
1000         int write = !(gtt->userflags & AMDGPU_GEM_USERPTR_READONLY);
1001         enum dma_data_direction direction = write ?
1002                 DMA_BIDIRECTIONAL : DMA_TO_DEVICE;
1003
1004         /* double check that we don't free the table twice */
1005         if (!ttm->sg->sgl)
1006                 return;
1007
1008         /* unmap the pages mapped to the device */
1009         dma_unmap_sg(adev->dev, ttm->sg->sgl, ttm->sg->nents, direction);
1010
1011         sg_free_table(ttm->sg);
1012
1013 #if IS_ENABLED(CONFIG_DRM_AMDGPU_USERPTR)
1014         if (gtt->range) {
1015                 unsigned long i;
1016
1017                 for (i = 0; i < ttm->num_pages; i++) {
1018                         if (ttm->pages[i] !=
1019                                 hmm_device_entry_to_page(gtt->range,
1020                                               gtt->range->pfns[i]))
1021                                 break;
1022                 }
1023
1024                 WARN((i == ttm->num_pages), "Missing get_user_page_done\n");
1025         }
1026 #endif
1027 }
1028
1029 int amdgpu_ttm_gart_bind(struct amdgpu_device *adev,
1030                                 struct ttm_buffer_object *tbo,
1031                                 uint64_t flags)
1032 {
1033         struct amdgpu_bo *abo = ttm_to_amdgpu_bo(tbo);
1034         struct ttm_tt *ttm = tbo->ttm;
1035         struct amdgpu_ttm_tt *gtt = (void *)ttm;
1036         int r;
1037
1038         if (amdgpu_bo_encrypted(abo))
1039                 flags |= AMDGPU_PTE_TMZ;
1040
1041         if (abo->flags & AMDGPU_GEM_CREATE_CP_MQD_GFX9) {
1042                 uint64_t page_idx = 1;
1043
1044                 r = amdgpu_gart_bind(adev, gtt->offset, page_idx,
1045                                 ttm->pages, gtt->ttm.dma_address, flags);
1046                 if (r)
1047                         goto gart_bind_fail;
1048
1049                 /* The memory type of the first page defaults to UC. Now
1050                  * modify the memory type to NC from the second page of
1051                  * the BO onward.
1052                  */
1053                 flags &= ~AMDGPU_PTE_MTYPE_VG10_MASK;
1054                 flags |= AMDGPU_PTE_MTYPE_VG10(AMDGPU_MTYPE_NC);
1055
1056                 r = amdgpu_gart_bind(adev,
1057                                 gtt->offset + (page_idx << PAGE_SHIFT),
1058                                 ttm->num_pages - page_idx,
1059                                 &ttm->pages[page_idx],
1060                                 &(gtt->ttm.dma_address[page_idx]), flags);
1061         } else {
1062                 r = amdgpu_gart_bind(adev, gtt->offset, ttm->num_pages,
1063                                      ttm->pages, gtt->ttm.dma_address, flags);
1064         }
1065
1066 gart_bind_fail:
1067         if (r)
1068                 DRM_ERROR("failed to bind %lu pages at 0x%08llX\n",
1069                           ttm->num_pages, gtt->offset);
1070
1071         return r;
1072 }
1073
1074 /**
1075  * amdgpu_ttm_backend_bind - Bind GTT memory
1076  *
1077  * Called by ttm_tt_bind() on behalf of ttm_bo_handle_move_mem().
1078  * This handles binding GTT memory to the device address space.
1079  */
1080 static int amdgpu_ttm_backend_bind(struct ttm_tt *ttm,
1081                                    struct ttm_mem_reg *bo_mem)
1082 {
1083         struct amdgpu_device *adev = amdgpu_ttm_adev(ttm->bdev);
1084         struct amdgpu_ttm_tt *gtt = (void*)ttm;
1085         uint64_t flags;
1086         int r = 0;
1087
1088         if (gtt->userptr) {
1089                 r = amdgpu_ttm_tt_pin_userptr(ttm);
1090                 if (r) {
1091                         DRM_ERROR("failed to pin userptr\n");
1092                         return r;
1093                 }
1094         }
1095         if (!ttm->num_pages) {
1096                 WARN(1, "nothing to bind %lu pages for mreg %p back %p!\n",
1097                      ttm->num_pages, bo_mem, ttm);
1098         }
1099
1100         if (bo_mem->mem_type == AMDGPU_PL_GDS ||
1101             bo_mem->mem_type == AMDGPU_PL_GWS ||
1102             bo_mem->mem_type == AMDGPU_PL_OA)
1103                 return -EINVAL;
1104
1105         if (!amdgpu_gtt_mgr_has_gart_addr(bo_mem)) {
1106                 gtt->offset = AMDGPU_BO_INVALID_OFFSET;
1107                 return 0;
1108         }
1109
1110         /* compute PTE flags relevant to this BO memory */
1111         flags = amdgpu_ttm_tt_pte_flags(adev, ttm, bo_mem);
1112
1113         /* bind pages into GART page tables */
1114         gtt->offset = (u64)bo_mem->start << PAGE_SHIFT;
1115         r = amdgpu_gart_bind(adev, gtt->offset, ttm->num_pages,
1116                 ttm->pages, gtt->ttm.dma_address, flags);
1117
1118         if (r)
1119                 DRM_ERROR("failed to bind %lu pages at 0x%08llX\n",
1120                           ttm->num_pages, gtt->offset);
1121         return r;
1122 }
1123
1124 /**
1125  * amdgpu_ttm_alloc_gart - Allocate GART memory for buffer object
1126  */
1127 int amdgpu_ttm_alloc_gart(struct ttm_buffer_object *bo)
1128 {
1129         struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev);
1130         struct ttm_operation_ctx ctx = { false, false };
1131         struct amdgpu_ttm_tt *gtt = (void*)bo->ttm;
1132         struct ttm_mem_reg tmp;
1133         struct ttm_placement placement;
1134         struct ttm_place placements;
1135         uint64_t addr, flags;
1136         int r;
1137
1138         if (bo->mem.start != AMDGPU_BO_INVALID_OFFSET)
1139                 return 0;
1140
1141         addr = amdgpu_gmc_agp_addr(bo);
1142         if (addr != AMDGPU_BO_INVALID_OFFSET) {
1143                 bo->mem.start = addr >> PAGE_SHIFT;
1144         } else {
1145
1146                 /* allocate GART space */
1147                 tmp = bo->mem;
1148                 tmp.mm_node = NULL;
1149                 placement.num_placement = 1;
1150                 placement.placement = &placements;
1151                 placement.num_busy_placement = 1;
1152                 placement.busy_placement = &placements;
1153                 placements.fpfn = 0;
1154                 placements.lpfn = adev->gmc.gart_size >> PAGE_SHIFT;
1155                 placements.flags = (bo->mem.placement & ~TTM_PL_MASK_MEM) |
1156                         TTM_PL_FLAG_TT;
1157
1158                 r = ttm_bo_mem_space(bo, &placement, &tmp, &ctx);
1159                 if (unlikely(r))
1160                         return r;
1161
1162                 /* compute PTE flags for this buffer object */
1163                 flags = amdgpu_ttm_tt_pte_flags(adev, bo->ttm, &tmp);
1164
1165                 /* Bind pages */
1166                 gtt->offset = (u64)tmp.start << PAGE_SHIFT;
1167                 r = amdgpu_ttm_gart_bind(adev, bo, flags);
1168                 if (unlikely(r)) {
1169                         ttm_bo_mem_put(bo, &tmp);
1170                         return r;
1171                 }
1172
1173                 ttm_bo_mem_put(bo, &bo->mem);
1174                 bo->mem = tmp;
1175         }
1176
1177         bo->offset = (bo->mem.start << PAGE_SHIFT) +
1178                 bo->bdev->man[bo->mem.mem_type].gpu_offset;
1179
1180         return 0;
1181 }
1182
1183 /**
1184  * amdgpu_ttm_recover_gart - Rebind GTT pages
1185  *
1186  * Called by amdgpu_gtt_mgr_recover() from amdgpu_device_reset() to
1187  * rebind GTT pages during a GPU reset.
1188  */
1189 int amdgpu_ttm_recover_gart(struct ttm_buffer_object *tbo)
1190 {
1191         struct amdgpu_device *adev = amdgpu_ttm_adev(tbo->bdev);
1192         uint64_t flags;
1193         int r;
1194
1195         if (!tbo->ttm)
1196                 return 0;
1197
1198         flags = amdgpu_ttm_tt_pte_flags(adev, tbo->ttm, &tbo->mem);
1199         r = amdgpu_ttm_gart_bind(adev, tbo, flags);
1200
1201         return r;
1202 }
1203
1204 /**
1205  * amdgpu_ttm_backend_unbind - Unbind GTT mapped pages
1206  *
1207  * Called by ttm_tt_unbind() on behalf of ttm_bo_move_ttm() and
1208  * ttm_tt_destroy().
1209  */
1210 static int amdgpu_ttm_backend_unbind(struct ttm_tt *ttm)
1211 {
1212         struct amdgpu_device *adev = amdgpu_ttm_adev(ttm->bdev);
1213         struct amdgpu_ttm_tt *gtt = (void *)ttm;
1214         int r;
1215
1216         /* if the pages have userptr pinning then clear that first */
1217         if (gtt->userptr)
1218                 amdgpu_ttm_tt_unpin_userptr(ttm);
1219
1220         if (gtt->offset == AMDGPU_BO_INVALID_OFFSET)
1221                 return 0;
1222
1223         /* unbind shouldn't be done for GDS/GWS/OA in ttm_bo_clean_mm */
1224         r = amdgpu_gart_unbind(adev, gtt->offset, ttm->num_pages);
1225         if (r)
1226                 DRM_ERROR("failed to unbind %lu pages at 0x%08llX\n",
1227                           gtt->ttm.ttm.num_pages, gtt->offset);
1228         return r;
1229 }
1230
1231 static void amdgpu_ttm_backend_destroy(struct ttm_tt *ttm)
1232 {
1233         struct amdgpu_ttm_tt *gtt = (void *)ttm;
1234
1235         if (gtt->usertask)
1236                 put_task_struct(gtt->usertask);
1237
1238         ttm_dma_tt_fini(&gtt->ttm);
1239         kfree(gtt);
1240 }
1241
1242 static struct ttm_backend_func amdgpu_backend_func = {
1243         .bind = &amdgpu_ttm_backend_bind,
1244         .unbind = &amdgpu_ttm_backend_unbind,
1245         .destroy = &amdgpu_ttm_backend_destroy,
1246 };
1247
1248 /**
1249  * amdgpu_ttm_tt_create - Create a ttm_tt object for a given BO
1250  *
1251  * @bo: The buffer object to create a GTT ttm_tt object around
1252  *
1253  * Called by ttm_tt_create().
1254  */
1255 static struct ttm_tt *amdgpu_ttm_tt_create(struct ttm_buffer_object *bo,
1256                                            uint32_t page_flags)
1257 {
1258         struct amdgpu_ttm_tt *gtt;
1259
1260         gtt = kzalloc(sizeof(struct amdgpu_ttm_tt), GFP_KERNEL);
1261         if (gtt == NULL) {
1262                 return NULL;
1263         }
1264         gtt->ttm.ttm.func = &amdgpu_backend_func;
1265         gtt->gobj = &bo->base;
1266
1267         /* allocate space for the uninitialized page entries */
1268         if (ttm_sg_tt_init(&gtt->ttm, bo, page_flags)) {
1269                 kfree(gtt);
1270                 return NULL;
1271         }
1272         return &gtt->ttm.ttm;
1273 }
1274
1275 /**
1276  * amdgpu_ttm_tt_populate - Map GTT pages visible to the device
1277  *
1278  * Map the pages of a ttm_tt object to an address space visible
1279  * to the underlying device.
1280  */
1281 static int amdgpu_ttm_tt_populate(struct ttm_tt *ttm,
1282                         struct ttm_operation_ctx *ctx)
1283 {
1284         struct amdgpu_device *adev = amdgpu_ttm_adev(ttm->bdev);
1285         struct amdgpu_ttm_tt *gtt = (void *)ttm;
1286
1287         /* user pages are bound by amdgpu_ttm_tt_pin_userptr() */
1288         if (gtt && gtt->userptr) {
1289                 ttm->sg = kzalloc(sizeof(struct sg_table), GFP_KERNEL);
1290                 if (!ttm->sg)
1291                         return -ENOMEM;
1292
1293                 ttm->page_flags |= TTM_PAGE_FLAG_SG;
1294                 ttm->state = tt_unbound;
1295                 return 0;
1296         }
1297
1298         if (ttm->page_flags & TTM_PAGE_FLAG_SG) {
1299                 if (!ttm->sg) {
1300                         struct dma_buf_attachment *attach;
1301                         struct sg_table *sgt;
1302
1303                         attach = gtt->gobj->import_attach;
1304                         sgt = dma_buf_map_attachment(attach, DMA_BIDIRECTIONAL);
1305                         if (IS_ERR(sgt))
1306                                 return PTR_ERR(sgt);
1307
1308                         ttm->sg = sgt;
1309                 }
1310
1311                 drm_prime_sg_to_page_addr_arrays(ttm->sg, ttm->pages,
1312                                                  gtt->ttm.dma_address,
1313                                                  ttm->num_pages);
1314                 ttm->state = tt_unbound;
1315                 return 0;
1316         }
1317
1318 #ifdef CONFIG_SWIOTLB
1319         if (adev->need_swiotlb && swiotlb_nr_tbl()) {
1320                 return ttm_dma_populate(&gtt->ttm, adev->dev, ctx);
1321         }
1322 #endif
1323
1324         /* fall back to generic helper to populate the page array
1325          * and map them to the device */
1326         return ttm_populate_and_map_pages(adev->dev, &gtt->ttm, ctx);
1327 }
1328
1329 /**
1330  * amdgpu_ttm_tt_unpopulate - unmap GTT pages and unpopulate page arrays
1331  *
1332  * Unmaps pages of a ttm_tt object from the device address space and
1333  * unpopulates the page array backing it.
1334  */
1335 static void amdgpu_ttm_tt_unpopulate(struct ttm_tt *ttm)
1336 {
1337         struct amdgpu_ttm_tt *gtt = (void *)ttm;
1338         struct amdgpu_device *adev;
1339
1340         if (gtt && gtt->userptr) {
1341                 amdgpu_ttm_tt_set_user_pages(ttm, NULL);
1342                 kfree(ttm->sg);
1343                 ttm->page_flags &= ~TTM_PAGE_FLAG_SG;
1344                 return;
1345         }
1346
1347         if (ttm->sg && gtt->gobj->import_attach) {
1348                 struct dma_buf_attachment *attach;
1349
1350                 attach = gtt->gobj->import_attach;
1351                 dma_buf_unmap_attachment(attach, ttm->sg, DMA_BIDIRECTIONAL);
1352                 ttm->sg = NULL;
1353                 return;
1354         }
1355
1356         if (ttm->page_flags & TTM_PAGE_FLAG_SG)
1357                 return;
1358
1359         adev = amdgpu_ttm_adev(ttm->bdev);
1360
1361 #ifdef CONFIG_SWIOTLB
1362         if (adev->need_swiotlb && swiotlb_nr_tbl()) {
1363                 ttm_dma_unpopulate(&gtt->ttm, adev->dev);
1364                 return;
1365         }
1366 #endif
1367
1368         /* fall back to generic helper to unmap and unpopulate array */
1369         ttm_unmap_and_unpopulate_pages(adev->dev, &gtt->ttm);
1370 }
1371
1372 /**
1373  * amdgpu_ttm_tt_set_userptr - Initialize userptr GTT ttm_tt for the current
1374  * task
1375  *
1376  * @ttm: The ttm_tt object to bind this userptr object to
1377  * @addr:  The address in the current tasks VM space to use
1378  * @flags: Requirements of userptr object.
1379  *
1380  * Called by amdgpu_gem_userptr_ioctl() to bind userptr pages
1381  * to current task
1382  */
1383 int amdgpu_ttm_tt_set_userptr(struct ttm_tt *ttm, uint64_t addr,
1384                               uint32_t flags)
1385 {
1386         struct amdgpu_ttm_tt *gtt = (void *)ttm;
1387
1388         if (gtt == NULL)
1389                 return -EINVAL;
1390
1391         gtt->userptr = addr;
1392         gtt->userflags = flags;
1393
1394         if (gtt->usertask)
1395                 put_task_struct(gtt->usertask);
1396         gtt->usertask = current->group_leader;
1397         get_task_struct(gtt->usertask);
1398
1399         return 0;
1400 }
1401
1402 /**
1403  * amdgpu_ttm_tt_get_usermm - Return memory manager for ttm_tt object
1404  */
1405 struct mm_struct *amdgpu_ttm_tt_get_usermm(struct ttm_tt *ttm)
1406 {
1407         struct amdgpu_ttm_tt *gtt = (void *)ttm;
1408
1409         if (gtt == NULL)
1410                 return NULL;
1411
1412         if (gtt->usertask == NULL)
1413                 return NULL;
1414
1415         return gtt->usertask->mm;
1416 }
1417
1418 /**
1419  * amdgpu_ttm_tt_affect_userptr - Determine if a ttm_tt object lays inside an
1420  * address range for the current task.
1421  *
1422  */
1423 bool amdgpu_ttm_tt_affect_userptr(struct ttm_tt *ttm, unsigned long start,
1424                                   unsigned long end)
1425 {
1426         struct amdgpu_ttm_tt *gtt = (void *)ttm;
1427         unsigned long size;
1428
1429         if (gtt == NULL || !gtt->userptr)
1430                 return false;
1431
1432         /* Return false if no part of the ttm_tt object lies within
1433          * the range
1434          */
1435         size = (unsigned long)gtt->ttm.ttm.num_pages * PAGE_SIZE;
1436         if (gtt->userptr > end || gtt->userptr + size <= start)
1437                 return false;
1438
1439         return true;
1440 }
1441
1442 /**
1443  * amdgpu_ttm_tt_is_userptr - Have the pages backing by userptr?
1444  */
1445 bool amdgpu_ttm_tt_is_userptr(struct ttm_tt *ttm)
1446 {
1447         struct amdgpu_ttm_tt *gtt = (void *)ttm;
1448
1449         if (gtt == NULL || !gtt->userptr)
1450                 return false;
1451
1452         return true;
1453 }
1454
1455 /**
1456  * amdgpu_ttm_tt_is_readonly - Is the ttm_tt object read only?
1457  */
1458 bool amdgpu_ttm_tt_is_readonly(struct ttm_tt *ttm)
1459 {
1460         struct amdgpu_ttm_tt *gtt = (void *)ttm;
1461
1462         if (gtt == NULL)
1463                 return false;
1464
1465         return !!(gtt->userflags & AMDGPU_GEM_USERPTR_READONLY);
1466 }
1467
1468 /**
1469  * amdgpu_ttm_tt_pde_flags - Compute PDE flags for ttm_tt object
1470  *
1471  * @ttm: The ttm_tt object to compute the flags for
1472  * @mem: The memory registry backing this ttm_tt object
1473  *
1474  * Figure out the flags to use for a VM PDE (Page Directory Entry).
1475  */
1476 uint64_t amdgpu_ttm_tt_pde_flags(struct ttm_tt *ttm, struct ttm_mem_reg *mem)
1477 {
1478         uint64_t flags = 0;
1479
1480         if (mem && mem->mem_type != TTM_PL_SYSTEM)
1481                 flags |= AMDGPU_PTE_VALID;
1482
1483         if (mem && mem->mem_type == TTM_PL_TT) {
1484                 flags |= AMDGPU_PTE_SYSTEM;
1485
1486                 if (ttm->caching_state == tt_cached)
1487                         flags |= AMDGPU_PTE_SNOOPED;
1488         }
1489
1490         return flags;
1491 }
1492
1493 /**
1494  * amdgpu_ttm_tt_pte_flags - Compute PTE flags for ttm_tt object
1495  *
1496  * @ttm: The ttm_tt object to compute the flags for
1497  * @mem: The memory registry backing this ttm_tt object
1498
1499  * Figure out the flags to use for a VM PTE (Page Table Entry).
1500  */
1501 uint64_t amdgpu_ttm_tt_pte_flags(struct amdgpu_device *adev, struct ttm_tt *ttm,
1502                                  struct ttm_mem_reg *mem)
1503 {
1504         uint64_t flags = amdgpu_ttm_tt_pde_flags(ttm, mem);
1505
1506         flags |= adev->gart.gart_pte_flags;
1507         flags |= AMDGPU_PTE_READABLE;
1508
1509         if (!amdgpu_ttm_tt_is_readonly(ttm))
1510                 flags |= AMDGPU_PTE_WRITEABLE;
1511
1512         return flags;
1513 }
1514
1515 /**
1516  * amdgpu_ttm_bo_eviction_valuable - Check to see if we can evict a buffer
1517  * object.
1518  *
1519  * Return true if eviction is sensible. Called by ttm_mem_evict_first() on
1520  * behalf of ttm_bo_mem_force_space() which tries to evict buffer objects until
1521  * it can find space for a new object and by ttm_bo_force_list_clean() which is
1522  * used to clean out a memory space.
1523  */
1524 static bool amdgpu_ttm_bo_eviction_valuable(struct ttm_buffer_object *bo,
1525                                             const struct ttm_place *place)
1526 {
1527         unsigned long num_pages = bo->mem.num_pages;
1528         struct drm_mm_node *node = bo->mem.mm_node;
1529         struct dma_resv_list *flist;
1530         struct dma_fence *f;
1531         int i;
1532
1533         if (bo->type == ttm_bo_type_kernel &&
1534             !amdgpu_vm_evictable(ttm_to_amdgpu_bo(bo)))
1535                 return false;
1536
1537         /* If bo is a KFD BO, check if the bo belongs to the current process.
1538          * If true, then return false as any KFD process needs all its BOs to
1539          * be resident to run successfully
1540          */
1541         flist = dma_resv_get_list(bo->base.resv);
1542         if (flist) {
1543                 for (i = 0; i < flist->shared_count; ++i) {
1544                         f = rcu_dereference_protected(flist->shared[i],
1545                                 dma_resv_held(bo->base.resv));
1546                         if (amdkfd_fence_check_mm(f, current->mm))
1547                                 return false;
1548                 }
1549         }
1550
1551         switch (bo->mem.mem_type) {
1552         case TTM_PL_TT:
1553                 return true;
1554
1555         case TTM_PL_VRAM:
1556                 /* Check each drm MM node individually */
1557                 while (num_pages) {
1558                         if (place->fpfn < (node->start + node->size) &&
1559                             !(place->lpfn && place->lpfn <= node->start))
1560                                 return true;
1561
1562                         num_pages -= node->size;
1563                         ++node;
1564                 }
1565                 return false;
1566
1567         default:
1568                 break;
1569         }
1570
1571         return ttm_bo_eviction_valuable(bo, place);
1572 }
1573
1574 /**
1575  * amdgpu_ttm_access_memory - Read or Write memory that backs a buffer object.
1576  *
1577  * @bo:  The buffer object to read/write
1578  * @offset:  Offset into buffer object
1579  * @buf:  Secondary buffer to write/read from
1580  * @len: Length in bytes of access
1581  * @write:  true if writing
1582  *
1583  * This is used to access VRAM that backs a buffer object via MMIO
1584  * access for debugging purposes.
1585  */
1586 static int amdgpu_ttm_access_memory(struct ttm_buffer_object *bo,
1587                                     unsigned long offset,
1588                                     void *buf, int len, int write)
1589 {
1590         struct amdgpu_bo *abo = ttm_to_amdgpu_bo(bo);
1591         struct amdgpu_device *adev = amdgpu_ttm_adev(abo->tbo.bdev);
1592         struct drm_mm_node *nodes;
1593         uint32_t value = 0;
1594         int ret = 0;
1595         uint64_t pos;
1596         unsigned long flags;
1597
1598         if (bo->mem.mem_type != TTM_PL_VRAM)
1599                 return -EIO;
1600
1601         nodes = amdgpu_find_mm_node(&abo->tbo.mem, &offset);
1602         pos = (nodes->start << PAGE_SHIFT) + offset;
1603
1604         while (len && pos < adev->gmc.mc_vram_size) {
1605                 uint64_t aligned_pos = pos & ~(uint64_t)3;
1606                 uint64_t bytes = 4 - (pos & 3);
1607                 uint32_t shift = (pos & 3) * 8;
1608                 uint32_t mask = 0xffffffff << shift;
1609
1610                 if (len < bytes) {
1611                         mask &= 0xffffffff >> (bytes - len) * 8;
1612                         bytes = len;
1613                 }
1614
1615                 if (mask != 0xffffffff) {
1616                         spin_lock_irqsave(&adev->mmio_idx_lock, flags);
1617                         WREG32_NO_KIQ(mmMM_INDEX, ((uint32_t)aligned_pos) | 0x80000000);
1618                         WREG32_NO_KIQ(mmMM_INDEX_HI, aligned_pos >> 31);
1619                         if (!write || mask != 0xffffffff)
1620                                 value = RREG32_NO_KIQ(mmMM_DATA);
1621                         if (write) {
1622                                 value &= ~mask;
1623                                 value |= (*(uint32_t *)buf << shift) & mask;
1624                                 WREG32_NO_KIQ(mmMM_DATA, value);
1625                         }
1626                         spin_unlock_irqrestore(&adev->mmio_idx_lock, flags);
1627                         if (!write) {
1628                                 value = (value & mask) >> shift;
1629                                 memcpy(buf, &value, bytes);
1630                         }
1631                 } else {
1632                         bytes = (nodes->start + nodes->size) << PAGE_SHIFT;
1633                         bytes = min(bytes - pos, (uint64_t)len & ~0x3ull);
1634
1635                         amdgpu_device_vram_access(adev, pos, (uint32_t *)buf,
1636                                                   bytes, write);
1637                 }
1638
1639                 ret += bytes;
1640                 buf = (uint8_t *)buf + bytes;
1641                 pos += bytes;
1642                 len -= bytes;
1643                 if (pos >= (nodes->start + nodes->size) << PAGE_SHIFT) {
1644                         ++nodes;
1645                         pos = (nodes->start << PAGE_SHIFT);
1646                 }
1647         }
1648
1649         return ret;
1650 }
1651
1652 static struct ttm_bo_driver amdgpu_bo_driver = {
1653         .ttm_tt_create = &amdgpu_ttm_tt_create,
1654         .ttm_tt_populate = &amdgpu_ttm_tt_populate,
1655         .ttm_tt_unpopulate = &amdgpu_ttm_tt_unpopulate,
1656         .init_mem_type = &amdgpu_init_mem_type,
1657         .eviction_valuable = amdgpu_ttm_bo_eviction_valuable,
1658         .evict_flags = &amdgpu_evict_flags,
1659         .move = &amdgpu_bo_move,
1660         .verify_access = &amdgpu_verify_access,
1661         .move_notify = &amdgpu_bo_move_notify,
1662         .release_notify = &amdgpu_bo_release_notify,
1663         .fault_reserve_notify = &amdgpu_bo_fault_reserve_notify,
1664         .io_mem_reserve = &amdgpu_ttm_io_mem_reserve,
1665         .io_mem_free = &amdgpu_ttm_io_mem_free,
1666         .io_mem_pfn = amdgpu_ttm_io_mem_pfn,
1667         .access_memory = &amdgpu_ttm_access_memory,
1668         .del_from_lru_notify = &amdgpu_vm_del_from_lru_notify
1669 };
1670
1671 /*
1672  * Firmware Reservation functions
1673  */
1674 /**
1675  * amdgpu_ttm_fw_reserve_vram_fini - free fw reserved vram
1676  *
1677  * @adev: amdgpu_device pointer
1678  *
1679  * free fw reserved vram if it has been reserved.
1680  */
1681 static void amdgpu_ttm_fw_reserve_vram_fini(struct amdgpu_device *adev)
1682 {
1683         amdgpu_bo_free_kernel(&adev->fw_vram_usage.reserved_bo,
1684                 NULL, &adev->fw_vram_usage.va);
1685 }
1686
1687 /**
1688  * amdgpu_ttm_fw_reserve_vram_init - create bo vram reservation from fw
1689  *
1690  * @adev: amdgpu_device pointer
1691  *
1692  * create bo vram reservation from fw.
1693  */
1694 static int amdgpu_ttm_fw_reserve_vram_init(struct amdgpu_device *adev)
1695 {
1696         uint64_t vram_size = adev->gmc.visible_vram_size;
1697
1698         adev->fw_vram_usage.va = NULL;
1699         adev->fw_vram_usage.reserved_bo = NULL;
1700
1701         if (adev->fw_vram_usage.size == 0 ||
1702             adev->fw_vram_usage.size > vram_size)
1703                 return 0;
1704
1705         return amdgpu_bo_create_kernel_at(adev,
1706                                           adev->fw_vram_usage.start_offset,
1707                                           adev->fw_vram_usage.size,
1708                                           AMDGPU_GEM_DOMAIN_VRAM,
1709                                           &adev->fw_vram_usage.reserved_bo,
1710                                           &adev->fw_vram_usage.va);
1711 }
1712
1713 /*
1714  * Memoy training reservation functions
1715  */
1716
1717 /**
1718  * amdgpu_ttm_training_reserve_vram_fini - free memory training reserved vram
1719  *
1720  * @adev: amdgpu_device pointer
1721  *
1722  * free memory training reserved vram if it has been reserved.
1723  */
1724 static int amdgpu_ttm_training_reserve_vram_fini(struct amdgpu_device *adev)
1725 {
1726         struct psp_memory_training_context *ctx = &adev->psp.mem_train_ctx;
1727
1728         ctx->init = PSP_MEM_TRAIN_NOT_SUPPORT;
1729         amdgpu_bo_free_kernel(&ctx->c2p_bo, NULL, NULL);
1730         ctx->c2p_bo = NULL;
1731
1732         return 0;
1733 }
1734
1735 static u64 amdgpu_ttm_training_get_c2p_offset(u64 vram_size)
1736 {
1737        if ((vram_size & (SZ_1M - 1)) < (SZ_4K + 1) )
1738                vram_size -= SZ_1M;
1739
1740        return ALIGN(vram_size, SZ_1M);
1741 }
1742
1743 /**
1744  * amdgpu_ttm_training_reserve_vram_init - create bo vram reservation from memory training
1745  *
1746  * @adev: amdgpu_device pointer
1747  *
1748  * create bo vram reservation from memory training.
1749  */
1750 static int amdgpu_ttm_training_reserve_vram_init(struct amdgpu_device *adev)
1751 {
1752         int ret;
1753         struct psp_memory_training_context *ctx = &adev->psp.mem_train_ctx;
1754
1755         memset(ctx, 0, sizeof(*ctx));
1756         if (!adev->fw_vram_usage.mem_train_support) {
1757                 DRM_DEBUG("memory training does not support!\n");
1758                 return 0;
1759         }
1760
1761         ctx->c2p_train_data_offset = amdgpu_ttm_training_get_c2p_offset(adev->gmc.mc_vram_size);
1762         ctx->p2c_train_data_offset = (adev->gmc.mc_vram_size - GDDR6_MEM_TRAINING_OFFSET);
1763         ctx->train_data_size = GDDR6_MEM_TRAINING_DATA_SIZE_IN_BYTES;
1764
1765         DRM_DEBUG("train_data_size:%llx,p2c_train_data_offset:%llx,c2p_train_data_offset:%llx.\n",
1766                   ctx->train_data_size,
1767                   ctx->p2c_train_data_offset,
1768                   ctx->c2p_train_data_offset);
1769
1770         ret = amdgpu_bo_create_kernel_at(adev,
1771                                          ctx->c2p_train_data_offset,
1772                                          ctx->train_data_size,
1773                                          AMDGPU_GEM_DOMAIN_VRAM,
1774                                          &ctx->c2p_bo,
1775                                          NULL);
1776         if (ret) {
1777                 DRM_ERROR("alloc c2p_bo failed(%d)!\n", ret);
1778                 amdgpu_ttm_training_reserve_vram_fini(adev);
1779                 return ret;
1780         }
1781
1782         ctx->init = PSP_MEM_TRAIN_RESERVE_SUCCESS;
1783         return 0;
1784 }
1785
1786 /**
1787  * amdgpu_ttm_init - Init the memory management (ttm) as well as various
1788  * gtt/vram related fields.
1789  *
1790  * This initializes all of the memory space pools that the TTM layer
1791  * will need such as the GTT space (system memory mapped to the device),
1792  * VRAM (on-board memory), and on-chip memories (GDS, GWS, OA) which
1793  * can be mapped per VMID.
1794  */
1795 int amdgpu_ttm_init(struct amdgpu_device *adev)
1796 {
1797         uint64_t gtt_size;
1798         int r;
1799         u64 vis_vram_limit;
1800         void *stolen_vga_buf;
1801
1802         mutex_init(&adev->mman.gtt_window_lock);
1803
1804         /* No others user of address space so set it to 0 */
1805         r = ttm_bo_device_init(&adev->mman.bdev,
1806                                &amdgpu_bo_driver,
1807                                adev->ddev->anon_inode->i_mapping,
1808                                adev->ddev->vma_offset_manager,
1809                                dma_addressing_limited(adev->dev));
1810         if (r) {
1811                 DRM_ERROR("failed initializing buffer object driver(%d).\n", r);
1812                 return r;
1813         }
1814         adev->mman.initialized = true;
1815
1816         /* We opt to avoid OOM on system pages allocations */
1817         adev->mman.bdev.no_retry = true;
1818
1819         /* Initialize VRAM pool with all of VRAM divided into pages */
1820         r = ttm_bo_init_mm(&adev->mman.bdev, TTM_PL_VRAM,
1821                                 adev->gmc.real_vram_size >> PAGE_SHIFT);
1822         if (r) {
1823                 DRM_ERROR("Failed initializing VRAM heap.\n");
1824                 return r;
1825         }
1826
1827         /* Reduce size of CPU-visible VRAM if requested */
1828         vis_vram_limit = (u64)amdgpu_vis_vram_limit * 1024 * 1024;
1829         if (amdgpu_vis_vram_limit > 0 &&
1830             vis_vram_limit <= adev->gmc.visible_vram_size)
1831                 adev->gmc.visible_vram_size = vis_vram_limit;
1832
1833         /* Change the size here instead of the init above so only lpfn is affected */
1834         amdgpu_ttm_set_buffer_funcs_status(adev, false);
1835 #ifdef CONFIG_64BIT
1836         adev->mman.aper_base_kaddr = ioremap_wc(adev->gmc.aper_base,
1837                                                 adev->gmc.visible_vram_size);
1838 #endif
1839
1840         /*
1841          *The reserved vram for firmware must be pinned to the specified
1842          *place on the VRAM, so reserve it early.
1843          */
1844         r = amdgpu_ttm_fw_reserve_vram_init(adev);
1845         if (r) {
1846                 return r;
1847         }
1848
1849         /*
1850          *The reserved vram for memory training must be pinned to the specified
1851          *place on the VRAM, so reserve it early.
1852          */
1853         if (!amdgpu_sriov_vf(adev)) {
1854                 r = amdgpu_ttm_training_reserve_vram_init(adev);
1855                 if (r)
1856                         return r;
1857         }
1858
1859         /* allocate memory as required for VGA
1860          * This is used for VGA emulation and pre-OS scanout buffers to
1861          * avoid display artifacts while transitioning between pre-OS
1862          * and driver.  */
1863         r = amdgpu_bo_create_kernel(adev, adev->gmc.stolen_size, PAGE_SIZE,
1864                                     AMDGPU_GEM_DOMAIN_VRAM,
1865                                     &adev->stolen_vga_memory,
1866                                     NULL, &stolen_vga_buf);
1867         if (r)
1868                 return r;
1869
1870         /*
1871          * reserve one TMR (64K) memory at the top of VRAM which holds
1872          * IP Discovery data and is protected by PSP.
1873          */
1874         r = amdgpu_bo_create_kernel_at(adev,
1875                                        adev->gmc.real_vram_size - DISCOVERY_TMR_SIZE,
1876                                        DISCOVERY_TMR_SIZE,
1877                                        AMDGPU_GEM_DOMAIN_VRAM,
1878                                        &adev->discovery_memory,
1879                                        NULL);
1880         if (r)
1881                 return r;
1882
1883         DRM_INFO("amdgpu: %uM of VRAM memory ready\n",
1884                  (unsigned) (adev->gmc.real_vram_size / (1024 * 1024)));
1885
1886         /* Compute GTT size, either bsaed on 3/4th the size of RAM size
1887          * or whatever the user passed on module init */
1888         if (amdgpu_gtt_size == -1) {
1889                 struct sysinfo si;
1890
1891                 si_meminfo(&si);
1892                 gtt_size = min(max((AMDGPU_DEFAULT_GTT_SIZE_MB << 20),
1893                                adev->gmc.mc_vram_size),
1894                                ((uint64_t)si.totalram * si.mem_unit * 3/4));
1895         }
1896         else
1897                 gtt_size = (uint64_t)amdgpu_gtt_size << 20;
1898
1899         /* Initialize GTT memory pool */
1900         r = ttm_bo_init_mm(&adev->mman.bdev, TTM_PL_TT, gtt_size >> PAGE_SHIFT);
1901         if (r) {
1902                 DRM_ERROR("Failed initializing GTT heap.\n");
1903                 return r;
1904         }
1905         DRM_INFO("amdgpu: %uM of GTT memory ready.\n",
1906                  (unsigned)(gtt_size / (1024 * 1024)));
1907
1908         /* Initialize various on-chip memory pools */
1909         r = ttm_bo_init_mm(&adev->mman.bdev, AMDGPU_PL_GDS,
1910                            adev->gds.gds_size);
1911         if (r) {
1912                 DRM_ERROR("Failed initializing GDS heap.\n");
1913                 return r;
1914         }
1915
1916         r = ttm_bo_init_mm(&adev->mman.bdev, AMDGPU_PL_GWS,
1917                            adev->gds.gws_size);
1918         if (r) {
1919                 DRM_ERROR("Failed initializing gws heap.\n");
1920                 return r;
1921         }
1922
1923         r = ttm_bo_init_mm(&adev->mman.bdev, AMDGPU_PL_OA,
1924                            adev->gds.oa_size);
1925         if (r) {
1926                 DRM_ERROR("Failed initializing oa heap.\n");
1927                 return r;
1928         }
1929
1930         return 0;
1931 }
1932
1933 /**
1934  * amdgpu_ttm_late_init - Handle any late initialization for amdgpu_ttm
1935  */
1936 void amdgpu_ttm_late_init(struct amdgpu_device *adev)
1937 {
1938         void *stolen_vga_buf;
1939         /* return the VGA stolen memory (if any) back to VRAM */
1940         amdgpu_bo_free_kernel(&adev->stolen_vga_memory, NULL, &stolen_vga_buf);
1941 }
1942
1943 /**
1944  * amdgpu_ttm_fini - De-initialize the TTM memory pools
1945  */
1946 void amdgpu_ttm_fini(struct amdgpu_device *adev)
1947 {
1948         if (!adev->mman.initialized)
1949                 return;
1950
1951         amdgpu_ttm_training_reserve_vram_fini(adev);
1952         /* return the IP Discovery TMR memory back to VRAM */
1953         amdgpu_bo_free_kernel(&adev->discovery_memory, NULL, NULL);
1954         amdgpu_ttm_fw_reserve_vram_fini(adev);
1955
1956         if (adev->mman.aper_base_kaddr)
1957                 iounmap(adev->mman.aper_base_kaddr);
1958         adev->mman.aper_base_kaddr = NULL;
1959
1960         ttm_bo_clean_mm(&adev->mman.bdev, TTM_PL_VRAM);
1961         ttm_bo_clean_mm(&adev->mman.bdev, TTM_PL_TT);
1962         ttm_bo_clean_mm(&adev->mman.bdev, AMDGPU_PL_GDS);
1963         ttm_bo_clean_mm(&adev->mman.bdev, AMDGPU_PL_GWS);
1964         ttm_bo_clean_mm(&adev->mman.bdev, AMDGPU_PL_OA);
1965         ttm_bo_device_release(&adev->mman.bdev);
1966         adev->mman.initialized = false;
1967         DRM_INFO("amdgpu: ttm finalized\n");
1968 }
1969
1970 /**
1971  * amdgpu_ttm_set_buffer_funcs_status - enable/disable use of buffer functions
1972  *
1973  * @adev: amdgpu_device pointer
1974  * @enable: true when we can use buffer functions.
1975  *
1976  * Enable/disable use of buffer functions during suspend/resume. This should
1977  * only be called at bootup or when userspace isn't running.
1978  */
1979 void amdgpu_ttm_set_buffer_funcs_status(struct amdgpu_device *adev, bool enable)
1980 {
1981         struct ttm_mem_type_manager *man = &adev->mman.bdev.man[TTM_PL_VRAM];
1982         uint64_t size;
1983         int r;
1984
1985         if (!adev->mman.initialized || adev->in_gpu_reset ||
1986             adev->mman.buffer_funcs_enabled == enable)
1987                 return;
1988
1989         if (enable) {
1990                 struct amdgpu_ring *ring;
1991                 struct drm_gpu_scheduler *sched;
1992
1993                 ring = adev->mman.buffer_funcs_ring;
1994                 sched = &ring->sched;
1995                 r = drm_sched_entity_init(&adev->mman.entity,
1996                                           DRM_SCHED_PRIORITY_KERNEL, &sched,
1997                                           1, NULL);
1998                 if (r) {
1999                         DRM_ERROR("Failed setting up TTM BO move entity (%d)\n",
2000                                   r);
2001                         return;
2002                 }
2003         } else {
2004                 drm_sched_entity_destroy(&adev->mman.entity);
2005                 dma_fence_put(man->move);
2006                 man->move = NULL;
2007         }
2008
2009         /* this just adjusts TTM size idea, which sets lpfn to the correct value */
2010         if (enable)
2011                 size = adev->gmc.real_vram_size;
2012         else
2013                 size = adev->gmc.visible_vram_size;
2014         man->size = size >> PAGE_SHIFT;
2015         adev->mman.buffer_funcs_enabled = enable;
2016 }
2017
2018 int amdgpu_mmap(struct file *filp, struct vm_area_struct *vma)
2019 {
2020         struct drm_file *file_priv = filp->private_data;
2021         struct amdgpu_device *adev = file_priv->minor->dev->dev_private;
2022
2023         if (adev == NULL)
2024                 return -EINVAL;
2025
2026         return ttm_bo_mmap(filp, vma, &adev->mman.bdev);
2027 }
2028
2029 static int amdgpu_map_buffer(struct ttm_buffer_object *bo,
2030                              struct ttm_mem_reg *mem, unsigned num_pages,
2031                              uint64_t offset, unsigned window,
2032                              struct amdgpu_ring *ring, bool tmz,
2033                              uint64_t *addr)
2034 {
2035         struct amdgpu_ttm_tt *gtt = (void *)bo->ttm;
2036         struct amdgpu_device *adev = ring->adev;
2037         struct ttm_tt *ttm = bo->ttm;
2038         struct amdgpu_job *job;
2039         unsigned num_dw, num_bytes;
2040         dma_addr_t *dma_address;
2041         struct dma_fence *fence;
2042         uint64_t src_addr, dst_addr;
2043         uint64_t flags;
2044         int r;
2045
2046         BUG_ON(adev->mman.buffer_funcs->copy_max_bytes <
2047                AMDGPU_GTT_MAX_TRANSFER_SIZE * 8);
2048
2049         *addr = adev->gmc.gart_start;
2050         *addr += (u64)window * AMDGPU_GTT_MAX_TRANSFER_SIZE *
2051                 AMDGPU_GPU_PAGE_SIZE;
2052
2053         num_dw = ALIGN(adev->mman.buffer_funcs->copy_num_dw, 8);
2054         num_bytes = num_pages * 8;
2055
2056         r = amdgpu_job_alloc_with_ib(adev, num_dw * 4 + num_bytes,
2057                                                                         AMDGPU_IB_POOL_NORMAL, &job);
2058         if (r)
2059                 return r;
2060
2061         src_addr = num_dw * 4;
2062         src_addr += job->ibs[0].gpu_addr;
2063
2064         dst_addr = amdgpu_bo_gpu_offset(adev->gart.bo);
2065         dst_addr += window * AMDGPU_GTT_MAX_TRANSFER_SIZE * 8;
2066         amdgpu_emit_copy_buffer(adev, &job->ibs[0], src_addr,
2067                                 dst_addr, num_bytes, false);
2068
2069         amdgpu_ring_pad_ib(ring, &job->ibs[0]);
2070         WARN_ON(job->ibs[0].length_dw > num_dw);
2071
2072         dma_address = &gtt->ttm.dma_address[offset >> PAGE_SHIFT];
2073         flags = amdgpu_ttm_tt_pte_flags(adev, ttm, mem);
2074         if (tmz)
2075                 flags |= AMDGPU_PTE_TMZ;
2076
2077         r = amdgpu_gart_map(adev, 0, num_pages, dma_address, flags,
2078                             &job->ibs[0].ptr[num_dw]);
2079         if (r)
2080                 goto error_free;
2081
2082         r = amdgpu_job_submit(job, &adev->mman.entity,
2083                               AMDGPU_FENCE_OWNER_UNDEFINED, &fence);
2084         if (r)
2085                 goto error_free;
2086
2087         dma_fence_put(fence);
2088
2089         return r;
2090
2091 error_free:
2092         amdgpu_job_free(job);
2093         return r;
2094 }
2095
2096 int amdgpu_copy_buffer(struct amdgpu_ring *ring, uint64_t src_offset,
2097                        uint64_t dst_offset, uint32_t byte_count,
2098                        struct dma_resv *resv,
2099                        struct dma_fence **fence, bool direct_submit,
2100                        bool vm_needs_flush, bool tmz)
2101 {
2102         struct amdgpu_device *adev = ring->adev;
2103         struct amdgpu_job *job;
2104
2105         uint32_t max_bytes;
2106         unsigned num_loops, num_dw;
2107         unsigned i;
2108         int r;
2109
2110         if (direct_submit && !ring->sched.ready) {
2111                 DRM_ERROR("Trying to move memory with ring turned off.\n");
2112                 return -EINVAL;
2113         }
2114
2115         max_bytes = adev->mman.buffer_funcs->copy_max_bytes;
2116         num_loops = DIV_ROUND_UP(byte_count, max_bytes);
2117         num_dw = ALIGN(num_loops * adev->mman.buffer_funcs->copy_num_dw, 8);
2118
2119         r = amdgpu_job_alloc_with_ib(adev, num_dw * 4,
2120                         direct_submit ? AMDGPU_IB_POOL_DIRECT : AMDGPU_IB_POOL_NORMAL, &job);
2121         if (r)
2122                 return r;
2123
2124         if (vm_needs_flush) {
2125                 job->vm_pd_addr = amdgpu_gmc_pd_addr(adev->gart.bo);
2126                 job->vm_needs_flush = true;
2127         }
2128         if (resv) {
2129                 r = amdgpu_sync_resv(adev, &job->sync, resv,
2130                                      AMDGPU_SYNC_ALWAYS,
2131                                      AMDGPU_FENCE_OWNER_UNDEFINED);
2132                 if (r) {
2133                         DRM_ERROR("sync failed (%d).\n", r);
2134                         goto error_free;
2135                 }
2136         }
2137
2138         for (i = 0; i < num_loops; i++) {
2139                 uint32_t cur_size_in_bytes = min(byte_count, max_bytes);
2140
2141                 amdgpu_emit_copy_buffer(adev, &job->ibs[0], src_offset,
2142                                         dst_offset, cur_size_in_bytes, tmz);
2143
2144                 src_offset += cur_size_in_bytes;
2145                 dst_offset += cur_size_in_bytes;
2146                 byte_count -= cur_size_in_bytes;
2147         }
2148
2149         amdgpu_ring_pad_ib(ring, &job->ibs[0]);
2150         WARN_ON(job->ibs[0].length_dw > num_dw);
2151         if (direct_submit)
2152                 r = amdgpu_job_submit_direct(job, ring, fence);
2153         else
2154                 r = amdgpu_job_submit(job, &adev->mman.entity,
2155                                       AMDGPU_FENCE_OWNER_UNDEFINED, fence);
2156         if (r)
2157                 goto error_free;
2158
2159         return r;
2160
2161 error_free:
2162         amdgpu_job_free(job);
2163         DRM_ERROR("Error scheduling IBs (%d)\n", r);
2164         return r;
2165 }
2166
2167 int amdgpu_fill_buffer(struct amdgpu_bo *bo,
2168                        uint32_t src_data,
2169                        struct dma_resv *resv,
2170                        struct dma_fence **fence)
2171 {
2172         struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
2173         uint32_t max_bytes = adev->mman.buffer_funcs->fill_max_bytes;
2174         struct amdgpu_ring *ring = adev->mman.buffer_funcs_ring;
2175
2176         struct drm_mm_node *mm_node;
2177         unsigned long num_pages;
2178         unsigned int num_loops, num_dw;
2179
2180         struct amdgpu_job *job;
2181         int r;
2182
2183         if (!adev->mman.buffer_funcs_enabled) {
2184                 DRM_ERROR("Trying to clear memory with ring turned off.\n");
2185                 return -EINVAL;
2186         }
2187
2188         if (bo->tbo.mem.mem_type == TTM_PL_TT) {
2189                 r = amdgpu_ttm_alloc_gart(&bo->tbo);
2190                 if (r)
2191                         return r;
2192         }
2193
2194         num_pages = bo->tbo.num_pages;
2195         mm_node = bo->tbo.mem.mm_node;
2196         num_loops = 0;
2197         while (num_pages) {
2198                 uint64_t byte_count = mm_node->size << PAGE_SHIFT;
2199
2200                 num_loops += DIV_ROUND_UP_ULL(byte_count, max_bytes);
2201                 num_pages -= mm_node->size;
2202                 ++mm_node;
2203         }
2204         num_dw = num_loops * adev->mman.buffer_funcs->fill_num_dw;
2205
2206         /* for IB padding */
2207         num_dw += 64;
2208
2209         r = amdgpu_job_alloc_with_ib(adev, num_dw * 4, AMDGPU_IB_POOL_NORMAL, &job);
2210         if (r)
2211                 return r;
2212
2213         if (resv) {
2214                 r = amdgpu_sync_resv(adev, &job->sync, resv,
2215                                      AMDGPU_SYNC_ALWAYS,
2216                                      AMDGPU_FENCE_OWNER_UNDEFINED);
2217                 if (r) {
2218                         DRM_ERROR("sync failed (%d).\n", r);
2219                         goto error_free;
2220                 }
2221         }
2222
2223         num_pages = bo->tbo.num_pages;
2224         mm_node = bo->tbo.mem.mm_node;
2225
2226         while (num_pages) {
2227                 uint64_t byte_count = mm_node->size << PAGE_SHIFT;
2228                 uint64_t dst_addr;
2229
2230                 dst_addr = amdgpu_mm_node_addr(&bo->tbo, mm_node, &bo->tbo.mem);
2231                 while (byte_count) {
2232                         uint32_t cur_size_in_bytes = min_t(uint64_t, byte_count,
2233                                                            max_bytes);
2234
2235                         amdgpu_emit_fill_buffer(adev, &job->ibs[0], src_data,
2236                                                 dst_addr, cur_size_in_bytes);
2237
2238                         dst_addr += cur_size_in_bytes;
2239                         byte_count -= cur_size_in_bytes;
2240                 }
2241
2242                 num_pages -= mm_node->size;
2243                 ++mm_node;
2244         }
2245
2246         amdgpu_ring_pad_ib(ring, &job->ibs[0]);
2247         WARN_ON(job->ibs[0].length_dw > num_dw);
2248         r = amdgpu_job_submit(job, &adev->mman.entity,
2249                               AMDGPU_FENCE_OWNER_UNDEFINED, fence);
2250         if (r)
2251                 goto error_free;
2252
2253         return 0;
2254
2255 error_free:
2256         amdgpu_job_free(job);
2257         return r;
2258 }
2259
2260 #if defined(CONFIG_DEBUG_FS)
2261
2262 static int amdgpu_mm_dump_table(struct seq_file *m, void *data)
2263 {
2264         struct drm_info_node *node = (struct drm_info_node *)m->private;
2265         unsigned ttm_pl = (uintptr_t)node->info_ent->data;
2266         struct drm_device *dev = node->minor->dev;
2267         struct amdgpu_device *adev = dev->dev_private;
2268         struct ttm_mem_type_manager *man = &adev->mman.bdev.man[ttm_pl];
2269         struct drm_printer p = drm_seq_file_printer(m);
2270
2271         man->func->debug(man, &p);
2272         return 0;
2273 }
2274
2275 static const struct drm_info_list amdgpu_ttm_debugfs_list[] = {
2276         {"amdgpu_vram_mm", amdgpu_mm_dump_table, 0, (void *)TTM_PL_VRAM},
2277         {"amdgpu_gtt_mm", amdgpu_mm_dump_table, 0, (void *)TTM_PL_TT},
2278         {"amdgpu_gds_mm", amdgpu_mm_dump_table, 0, (void *)AMDGPU_PL_GDS},
2279         {"amdgpu_gws_mm", amdgpu_mm_dump_table, 0, (void *)AMDGPU_PL_GWS},
2280         {"amdgpu_oa_mm", amdgpu_mm_dump_table, 0, (void *)AMDGPU_PL_OA},
2281         {"ttm_page_pool", ttm_page_alloc_debugfs, 0, NULL},
2282 #ifdef CONFIG_SWIOTLB
2283         {"ttm_dma_page_pool", ttm_dma_page_alloc_debugfs, 0, NULL}
2284 #endif
2285 };
2286
2287 /**
2288  * amdgpu_ttm_vram_read - Linear read access to VRAM
2289  *
2290  * Accesses VRAM via MMIO for debugging purposes.
2291  */
2292 static ssize_t amdgpu_ttm_vram_read(struct file *f, char __user *buf,
2293                                     size_t size, loff_t *pos)
2294 {
2295         struct amdgpu_device *adev = file_inode(f)->i_private;
2296         ssize_t result = 0;
2297
2298         if (size & 0x3 || *pos & 0x3)
2299                 return -EINVAL;
2300
2301         if (*pos >= adev->gmc.mc_vram_size)
2302                 return -ENXIO;
2303
2304         size = min(size, (size_t)(adev->gmc.mc_vram_size - *pos));
2305         while (size) {
2306                 size_t bytes = min(size, AMDGPU_TTM_VRAM_MAX_DW_READ * 4);
2307                 uint32_t value[AMDGPU_TTM_VRAM_MAX_DW_READ];
2308
2309                 amdgpu_device_vram_access(adev, *pos, value, bytes, false);
2310                 if (copy_to_user(buf, value, bytes))
2311                         return -EFAULT;
2312
2313                 result += bytes;
2314                 buf += bytes;
2315                 *pos += bytes;
2316                 size -= bytes;
2317         }
2318
2319         return result;
2320 }
2321
2322 /**
2323  * amdgpu_ttm_vram_write - Linear write access to VRAM
2324  *
2325  * Accesses VRAM via MMIO for debugging purposes.
2326  */
2327 static ssize_t amdgpu_ttm_vram_write(struct file *f, const char __user *buf,
2328                                     size_t size, loff_t *pos)
2329 {
2330         struct amdgpu_device *adev = file_inode(f)->i_private;
2331         ssize_t result = 0;
2332         int r;
2333
2334         if (size & 0x3 || *pos & 0x3)
2335                 return -EINVAL;
2336
2337         if (*pos >= adev->gmc.mc_vram_size)
2338                 return -ENXIO;
2339
2340         while (size) {
2341                 unsigned long flags;
2342                 uint32_t value;
2343
2344                 if (*pos >= adev->gmc.mc_vram_size)
2345                         return result;
2346
2347                 r = get_user(value, (uint32_t *)buf);
2348                 if (r)
2349                         return r;
2350
2351                 spin_lock_irqsave(&adev->mmio_idx_lock, flags);
2352                 WREG32_NO_KIQ(mmMM_INDEX, ((uint32_t)*pos) | 0x80000000);
2353                 WREG32_NO_KIQ(mmMM_INDEX_HI, *pos >> 31);
2354                 WREG32_NO_KIQ(mmMM_DATA, value);
2355                 spin_unlock_irqrestore(&adev->mmio_idx_lock, flags);
2356
2357                 result += 4;
2358                 buf += 4;
2359                 *pos += 4;
2360                 size -= 4;
2361         }
2362
2363         return result;
2364 }
2365
2366 static const struct file_operations amdgpu_ttm_vram_fops = {
2367         .owner = THIS_MODULE,
2368         .read = amdgpu_ttm_vram_read,
2369         .write = amdgpu_ttm_vram_write,
2370         .llseek = default_llseek,
2371 };
2372
2373 #ifdef CONFIG_DRM_AMDGPU_GART_DEBUGFS
2374
2375 /**
2376  * amdgpu_ttm_gtt_read - Linear read access to GTT memory
2377  */
2378 static ssize_t amdgpu_ttm_gtt_read(struct file *f, char __user *buf,
2379                                    size_t size, loff_t *pos)
2380 {
2381         struct amdgpu_device *adev = file_inode(f)->i_private;
2382         ssize_t result = 0;
2383         int r;
2384
2385         while (size) {
2386                 loff_t p = *pos / PAGE_SIZE;
2387                 unsigned off = *pos & ~PAGE_MASK;
2388                 size_t cur_size = min_t(size_t, size, PAGE_SIZE - off);
2389                 struct page *page;
2390                 void *ptr;
2391
2392                 if (p >= adev->gart.num_cpu_pages)
2393                         return result;
2394
2395                 page = adev->gart.pages[p];
2396                 if (page) {
2397                         ptr = kmap(page);
2398                         ptr += off;
2399
2400                         r = copy_to_user(buf, ptr, cur_size);
2401                         kunmap(adev->gart.pages[p]);
2402                 } else
2403                         r = clear_user(buf, cur_size);
2404
2405                 if (r)
2406                         return -EFAULT;
2407
2408                 result += cur_size;
2409                 buf += cur_size;
2410                 *pos += cur_size;
2411                 size -= cur_size;
2412         }
2413
2414         return result;
2415 }
2416
2417 static const struct file_operations amdgpu_ttm_gtt_fops = {
2418         .owner = THIS_MODULE,
2419         .read = amdgpu_ttm_gtt_read,
2420         .llseek = default_llseek
2421 };
2422
2423 #endif
2424
2425 /**
2426  * amdgpu_iomem_read - Virtual read access to GPU mapped memory
2427  *
2428  * This function is used to read memory that has been mapped to the
2429  * GPU and the known addresses are not physical addresses but instead
2430  * bus addresses (e.g., what you'd put in an IB or ring buffer).
2431  */
2432 static ssize_t amdgpu_iomem_read(struct file *f, char __user *buf,
2433                                  size_t size, loff_t *pos)
2434 {
2435         struct amdgpu_device *adev = file_inode(f)->i_private;
2436         struct iommu_domain *dom;
2437         ssize_t result = 0;
2438         int r;
2439
2440         /* retrieve the IOMMU domain if any for this device */
2441         dom = iommu_get_domain_for_dev(adev->dev);
2442
2443         while (size) {
2444                 phys_addr_t addr = *pos & PAGE_MASK;
2445                 loff_t off = *pos & ~PAGE_MASK;
2446                 size_t bytes = PAGE_SIZE - off;
2447                 unsigned long pfn;
2448                 struct page *p;
2449                 void *ptr;
2450
2451                 bytes = bytes < size ? bytes : size;
2452
2453                 /* Translate the bus address to a physical address.  If
2454                  * the domain is NULL it means there is no IOMMU active
2455                  * and the address translation is the identity
2456                  */
2457                 addr = dom ? iommu_iova_to_phys(dom, addr) : addr;
2458
2459                 pfn = addr >> PAGE_SHIFT;
2460                 if (!pfn_valid(pfn))
2461                         return -EPERM;
2462
2463                 p = pfn_to_page(pfn);
2464                 if (p->mapping != adev->mman.bdev.dev_mapping)
2465                         return -EPERM;
2466
2467                 ptr = kmap(p);
2468                 r = copy_to_user(buf, ptr + off, bytes);
2469                 kunmap(p);
2470                 if (r)
2471                         return -EFAULT;
2472
2473                 size -= bytes;
2474                 *pos += bytes;
2475                 result += bytes;
2476         }
2477
2478         return result;
2479 }
2480
2481 /**
2482  * amdgpu_iomem_write - Virtual write access to GPU mapped memory
2483  *
2484  * This function is used to write memory that has been mapped to the
2485  * GPU and the known addresses are not physical addresses but instead
2486  * bus addresses (e.g., what you'd put in an IB or ring buffer).
2487  */
2488 static ssize_t amdgpu_iomem_write(struct file *f, const char __user *buf,
2489                                  size_t size, loff_t *pos)
2490 {
2491         struct amdgpu_device *adev = file_inode(f)->i_private;
2492         struct iommu_domain *dom;
2493         ssize_t result = 0;
2494         int r;
2495
2496         dom = iommu_get_domain_for_dev(adev->dev);
2497
2498         while (size) {
2499                 phys_addr_t addr = *pos & PAGE_MASK;
2500                 loff_t off = *pos & ~PAGE_MASK;
2501                 size_t bytes = PAGE_SIZE - off;
2502                 unsigned long pfn;
2503                 struct page *p;
2504                 void *ptr;
2505
2506                 bytes = bytes < size ? bytes : size;
2507
2508                 addr = dom ? iommu_iova_to_phys(dom, addr) : addr;
2509
2510                 pfn = addr >> PAGE_SHIFT;
2511                 if (!pfn_valid(pfn))
2512                         return -EPERM;
2513
2514                 p = pfn_to_page(pfn);
2515                 if (p->mapping != adev->mman.bdev.dev_mapping)
2516                         return -EPERM;
2517
2518                 ptr = kmap(p);
2519                 r = copy_from_user(ptr + off, buf, bytes);
2520                 kunmap(p);
2521                 if (r)
2522                         return -EFAULT;
2523
2524                 size -= bytes;
2525                 *pos += bytes;
2526                 result += bytes;
2527         }
2528
2529         return result;
2530 }
2531
2532 static const struct file_operations amdgpu_ttm_iomem_fops = {
2533         .owner = THIS_MODULE,
2534         .read = amdgpu_iomem_read,
2535         .write = amdgpu_iomem_write,
2536         .llseek = default_llseek
2537 };
2538
2539 static const struct {
2540         char *name;
2541         const struct file_operations *fops;
2542         int domain;
2543 } ttm_debugfs_entries[] = {
2544         { "amdgpu_vram", &amdgpu_ttm_vram_fops, TTM_PL_VRAM },
2545 #ifdef CONFIG_DRM_AMDGPU_GART_DEBUGFS
2546         { "amdgpu_gtt", &amdgpu_ttm_gtt_fops, TTM_PL_TT },
2547 #endif
2548         { "amdgpu_iomem", &amdgpu_ttm_iomem_fops, TTM_PL_SYSTEM },
2549 };
2550
2551 #endif
2552
2553 int amdgpu_ttm_debugfs_init(struct amdgpu_device *adev)
2554 {
2555 #if defined(CONFIG_DEBUG_FS)
2556         unsigned count;
2557
2558         struct drm_minor *minor = adev->ddev->primary;
2559         struct dentry *ent, *root = minor->debugfs_root;
2560
2561         for (count = 0; count < ARRAY_SIZE(ttm_debugfs_entries); count++) {
2562                 ent = debugfs_create_file(
2563                                 ttm_debugfs_entries[count].name,
2564                                 S_IFREG | S_IRUGO, root,
2565                                 adev,
2566                                 ttm_debugfs_entries[count].fops);
2567                 if (IS_ERR(ent))
2568                         return PTR_ERR(ent);
2569                 if (ttm_debugfs_entries[count].domain == TTM_PL_VRAM)
2570                         i_size_write(ent->d_inode, adev->gmc.mc_vram_size);
2571                 else if (ttm_debugfs_entries[count].domain == TTM_PL_TT)
2572                         i_size_write(ent->d_inode, adev->gmc.gart_size);
2573                 adev->mman.debugfs_entries[count] = ent;
2574         }
2575
2576         count = ARRAY_SIZE(amdgpu_ttm_debugfs_list);
2577
2578 #ifdef CONFIG_SWIOTLB
2579         if (!(adev->need_swiotlb && swiotlb_nr_tbl()))
2580                 --count;
2581 #endif
2582
2583         return amdgpu_debugfs_add_files(adev, amdgpu_ttm_debugfs_list, count);
2584 #else
2585         return 0;
2586 #endif
2587 }