2 * Copyright 2009 Jerome Glisse.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the
7 * "Software"), to deal in the Software without restriction, including
8 * without limitation the rights to use, copy, modify, merge, publish,
9 * distribute, sub license, and/or sell copies of the Software, and to
10 * permit persons to whom the Software is furnished to do so, subject to
11 * the following conditions:
13 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
14 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
15 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
16 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
17 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
18 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
19 * USE OR OTHER DEALINGS IN THE SOFTWARE.
21 * The above copyright notice and this permission notice (including the
22 * next paragraph) shall be included in all copies or substantial portions
28 * Jerome Glisse <glisse@freedesktop.org>
29 * Thomas Hellstrom <thomas-at-tungstengraphics-dot-com>
33 #include <linux/dma-mapping.h>
34 #include <linux/iommu.h>
35 #include <linux/hmm.h>
36 #include <linux/pagemap.h>
37 #include <linux/sched/task.h>
38 #include <linux/sched/mm.h>
39 #include <linux/seq_file.h>
40 #include <linux/slab.h>
41 #include <linux/swap.h>
42 #include <linux/swiotlb.h>
43 #include <linux/dma-buf.h>
44 #include <linux/sizes.h>
46 #include <drm/ttm/ttm_bo_api.h>
47 #include <drm/ttm/ttm_bo_driver.h>
48 #include <drm/ttm/ttm_placement.h>
49 #include <drm/ttm/ttm_module.h>
50 #include <drm/ttm/ttm_page_alloc.h>
52 #include <drm/drm_debugfs.h>
53 #include <drm/amdgpu_drm.h>
56 #include "amdgpu_object.h"
57 #include "amdgpu_trace.h"
58 #include "amdgpu_amdkfd.h"
59 #include "amdgpu_sdma.h"
60 #include "amdgpu_ras.h"
61 #include "amdgpu_atomfirmware.h"
62 #include "bif/bif_4_1_d.h"
64 #define AMDGPU_TTM_VRAM_MAX_DW_READ (size_t)128
66 static int amdgpu_ttm_backend_bind(struct ttm_bo_device *bdev,
68 struct ttm_resource *bo_mem);
69 static void amdgpu_ttm_backend_unbind(struct ttm_bo_device *bdev,
72 static int amdgpu_ttm_init_on_chip(struct amdgpu_device *adev,
76 return ttm_range_man_init(&adev->mman.bdev, type,
77 false, size >> PAGE_SHIFT);
81 * amdgpu_evict_flags - Compute placement flags
83 * @bo: The buffer object to evict
84 * @placement: Possible destination(s) for evicted BO
86 * Fill in placement data when ttm_bo_evict() is called
88 static void amdgpu_evict_flags(struct ttm_buffer_object *bo,
89 struct ttm_placement *placement)
91 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev);
92 struct amdgpu_bo *abo;
93 static const struct ttm_place placements = {
96 .mem_type = TTM_PL_SYSTEM,
100 /* Don't handle scatter gather BOs */
101 if (bo->type == ttm_bo_type_sg) {
102 placement->num_placement = 0;
103 placement->num_busy_placement = 0;
107 /* Object isn't an AMDGPU object so ignore */
108 if (!amdgpu_bo_is_amdgpu_bo(bo)) {
109 placement->placement = &placements;
110 placement->busy_placement = &placements;
111 placement->num_placement = 1;
112 placement->num_busy_placement = 1;
116 abo = ttm_to_amdgpu_bo(bo);
117 switch (bo->mem.mem_type) {
121 placement->num_placement = 0;
122 placement->num_busy_placement = 0;
126 if (!adev->mman.buffer_funcs_enabled) {
127 /* Move to system memory */
128 amdgpu_bo_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_CPU);
129 } else if (!amdgpu_gmc_vram_full_visible(&adev->gmc) &&
130 !(abo->flags & AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED) &&
131 amdgpu_bo_in_cpu_visible_vram(abo)) {
133 /* Try evicting to the CPU inaccessible part of VRAM
134 * first, but only set GTT as busy placement, so this
135 * BO will be evicted to GTT rather than causing other
136 * BOs to be evicted from VRAM
138 amdgpu_bo_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_VRAM |
139 AMDGPU_GEM_DOMAIN_GTT);
140 abo->placements[0].fpfn = adev->gmc.visible_vram_size >> PAGE_SHIFT;
141 abo->placements[0].lpfn = 0;
142 abo->placement.busy_placement = &abo->placements[1];
143 abo->placement.num_busy_placement = 1;
145 /* Move to GTT memory */
146 amdgpu_bo_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_GTT);
151 amdgpu_bo_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_CPU);
154 *placement = abo->placement;
158 * amdgpu_verify_access - Verify access for a mmap call
160 * @bo: The buffer object to map
161 * @filp: The file pointer from the process performing the mmap
163 * This is called by ttm_bo_mmap() to verify whether a process
164 * has the right to mmap a BO to their process space.
166 static int amdgpu_verify_access(struct ttm_buffer_object *bo, struct file *filp)
168 struct amdgpu_bo *abo = ttm_to_amdgpu_bo(bo);
171 * Don't verify access for KFD BOs. They don't have a GEM
172 * object associated with them.
177 if (amdgpu_ttm_tt_get_usermm(bo->ttm))
179 return drm_vma_node_verify_access(&abo->tbo.base.vma_node,
184 * amdgpu_mm_node_addr - Compute the GPU relative offset of a GTT buffer.
186 * @bo: The bo to assign the memory to.
187 * @mm_node: Memory manager node for drm allocator.
188 * @mem: The region where the bo resides.
191 static uint64_t amdgpu_mm_node_addr(struct ttm_buffer_object *bo,
192 struct drm_mm_node *mm_node,
193 struct ttm_resource *mem)
197 if (mm_node->start != AMDGPU_BO_INVALID_OFFSET) {
198 addr = mm_node->start << PAGE_SHIFT;
199 addr += amdgpu_ttm_domain_start(amdgpu_ttm_adev(bo->bdev),
206 * amdgpu_find_mm_node - Helper function finds the drm_mm_node corresponding to
207 * @offset. It also modifies the offset to be within the drm_mm_node returned
209 * @mem: The region where the bo resides.
210 * @offset: The offset that drm_mm_node is used for finding.
213 static struct drm_mm_node *amdgpu_find_mm_node(struct ttm_resource *mem,
216 struct drm_mm_node *mm_node = mem->mm_node;
218 while (*offset >= (mm_node->size << PAGE_SHIFT)) {
219 *offset -= (mm_node->size << PAGE_SHIFT);
226 * amdgpu_ttm_map_buffer - Map memory into the GART windows
227 * @bo: buffer object to map
228 * @mem: memory object to map
229 * @mm_node: drm_mm node object to map
230 * @num_pages: number of pages to map
231 * @offset: offset into @mm_node where to start
232 * @window: which GART window to use
233 * @ring: DMA ring to use for the copy
234 * @tmz: if we should setup a TMZ enabled mapping
235 * @addr: resulting address inside the MC address space
237 * Setup one of the GART windows to access a specific piece of memory or return
238 * the physical address for local memory.
240 static int amdgpu_ttm_map_buffer(struct ttm_buffer_object *bo,
241 struct ttm_resource *mem,
242 struct drm_mm_node *mm_node,
243 unsigned num_pages, uint64_t offset,
244 unsigned window, struct amdgpu_ring *ring,
245 bool tmz, uint64_t *addr)
247 struct amdgpu_device *adev = ring->adev;
248 struct amdgpu_job *job;
249 unsigned num_dw, num_bytes;
250 struct dma_fence *fence;
251 uint64_t src_addr, dst_addr;
257 BUG_ON(adev->mman.buffer_funcs->copy_max_bytes <
258 AMDGPU_GTT_MAX_TRANSFER_SIZE * 8);
260 /* Map only what can't be accessed directly */
261 if (!tmz && mem->start != AMDGPU_BO_INVALID_OFFSET) {
262 *addr = amdgpu_mm_node_addr(bo, mm_node, mem) + offset;
266 *addr = adev->gmc.gart_start;
267 *addr += (u64)window * AMDGPU_GTT_MAX_TRANSFER_SIZE *
268 AMDGPU_GPU_PAGE_SIZE;
269 *addr += offset & ~PAGE_MASK;
271 num_dw = ALIGN(adev->mman.buffer_funcs->copy_num_dw, 8);
272 num_bytes = num_pages * 8;
274 r = amdgpu_job_alloc_with_ib(adev, num_dw * 4 + num_bytes,
275 AMDGPU_IB_POOL_DELAYED, &job);
279 src_addr = num_dw * 4;
280 src_addr += job->ibs[0].gpu_addr;
282 dst_addr = amdgpu_bo_gpu_offset(adev->gart.bo);
283 dst_addr += window * AMDGPU_GTT_MAX_TRANSFER_SIZE * 8;
284 amdgpu_emit_copy_buffer(adev, &job->ibs[0], src_addr,
285 dst_addr, num_bytes, false);
287 amdgpu_ring_pad_ib(ring, &job->ibs[0]);
288 WARN_ON(job->ibs[0].length_dw > num_dw);
290 flags = amdgpu_ttm_tt_pte_flags(adev, bo->ttm, mem);
292 flags |= AMDGPU_PTE_TMZ;
294 cpu_addr = &job->ibs[0].ptr[num_dw];
296 if (mem->mem_type == TTM_PL_TT) {
297 struct ttm_dma_tt *dma;
298 dma_addr_t *dma_address;
300 dma = container_of(bo->ttm, struct ttm_dma_tt, ttm);
301 dma_address = &dma->dma_address[offset >> PAGE_SHIFT];
302 r = amdgpu_gart_map(adev, 0, num_pages, dma_address, flags,
307 dma_addr_t dma_address;
309 dma_address = (mm_node->start << PAGE_SHIFT) + offset;
310 dma_address += adev->vm_manager.vram_base_offset;
312 for (i = 0; i < num_pages; ++i) {
313 r = amdgpu_gart_map(adev, i << PAGE_SHIFT, 1,
314 &dma_address, flags, cpu_addr);
318 dma_address += PAGE_SIZE;
322 r = amdgpu_job_submit(job, &adev->mman.entity,
323 AMDGPU_FENCE_OWNER_UNDEFINED, &fence);
327 dma_fence_put(fence);
332 amdgpu_job_free(job);
337 * amdgpu_copy_ttm_mem_to_mem - Helper function for copy
338 * @adev: amdgpu device
339 * @src: buffer/address where to read from
340 * @dst: buffer/address where to write to
341 * @size: number of bytes to copy
342 * @tmz: if a secure copy should be used
343 * @resv: resv object to sync to
344 * @f: Returns the last fence if multiple jobs are submitted.
346 * The function copies @size bytes from {src->mem + src->offset} to
347 * {dst->mem + dst->offset}. src->bo and dst->bo could be same BO for a
348 * move and different for a BO to BO copy.
351 int amdgpu_ttm_copy_mem_to_mem(struct amdgpu_device *adev,
352 const struct amdgpu_copy_mem *src,
353 const struct amdgpu_copy_mem *dst,
354 uint64_t size, bool tmz,
355 struct dma_resv *resv,
356 struct dma_fence **f)
358 const uint32_t GTT_MAX_BYTES = (AMDGPU_GTT_MAX_TRANSFER_SIZE *
359 AMDGPU_GPU_PAGE_SIZE);
361 uint64_t src_node_size, dst_node_size, src_offset, dst_offset;
362 struct amdgpu_ring *ring = adev->mman.buffer_funcs_ring;
363 struct drm_mm_node *src_mm, *dst_mm;
364 struct dma_fence *fence = NULL;
367 if (!adev->mman.buffer_funcs_enabled) {
368 DRM_ERROR("Trying to move memory with ring turned off.\n");
372 src_offset = src->offset;
373 if (src->mem->mm_node) {
374 src_mm = amdgpu_find_mm_node(src->mem, &src_offset);
375 src_node_size = (src_mm->size << PAGE_SHIFT) - src_offset;
378 src_node_size = ULLONG_MAX;
381 dst_offset = dst->offset;
382 if (dst->mem->mm_node) {
383 dst_mm = amdgpu_find_mm_node(dst->mem, &dst_offset);
384 dst_node_size = (dst_mm->size << PAGE_SHIFT) - dst_offset;
387 dst_node_size = ULLONG_MAX;
390 mutex_lock(&adev->mman.gtt_window_lock);
393 uint32_t src_page_offset = src_offset & ~PAGE_MASK;
394 uint32_t dst_page_offset = dst_offset & ~PAGE_MASK;
395 struct dma_fence *next;
399 /* Copy size cannot exceed GTT_MAX_BYTES. So if src or dst
400 * begins at an offset, then adjust the size accordingly
402 cur_size = max(src_page_offset, dst_page_offset);
403 cur_size = min(min3(src_node_size, dst_node_size, size),
404 (uint64_t)(GTT_MAX_BYTES - cur_size));
406 /* Map src to window 0 and dst to window 1. */
407 r = amdgpu_ttm_map_buffer(src->bo, src->mem, src_mm,
408 PFN_UP(cur_size + src_page_offset),
409 src_offset, 0, ring, tmz, &from);
413 r = amdgpu_ttm_map_buffer(dst->bo, dst->mem, dst_mm,
414 PFN_UP(cur_size + dst_page_offset),
415 dst_offset, 1, ring, tmz, &to);
419 r = amdgpu_copy_buffer(ring, from, to, cur_size,
420 resv, &next, false, true, tmz);
424 dma_fence_put(fence);
431 src_node_size -= cur_size;
432 if (!src_node_size) {
434 src_node_size = src_mm->size << PAGE_SHIFT;
437 src_offset += cur_size;
440 dst_node_size -= cur_size;
441 if (!dst_node_size) {
443 dst_node_size = dst_mm->size << PAGE_SHIFT;
446 dst_offset += cur_size;
450 mutex_unlock(&adev->mman.gtt_window_lock);
452 *f = dma_fence_get(fence);
453 dma_fence_put(fence);
458 * amdgpu_move_blit - Copy an entire buffer to another buffer
460 * This is a helper called by amdgpu_bo_move() and amdgpu_move_vram_ram() to
461 * help move buffers to and from VRAM.
463 static int amdgpu_move_blit(struct ttm_buffer_object *bo,
465 struct ttm_resource *new_mem,
466 struct ttm_resource *old_mem)
468 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev);
469 struct amdgpu_bo *abo = ttm_to_amdgpu_bo(bo);
470 struct amdgpu_copy_mem src, dst;
471 struct dma_fence *fence = NULL;
481 r = amdgpu_ttm_copy_mem_to_mem(adev, &src, &dst,
482 new_mem->num_pages << PAGE_SHIFT,
483 amdgpu_bo_encrypted(abo),
484 bo->base.resv, &fence);
488 /* clear the space being freed */
489 if (old_mem->mem_type == TTM_PL_VRAM &&
490 (abo->flags & AMDGPU_GEM_CREATE_VRAM_WIPE_ON_RELEASE)) {
491 struct dma_fence *wipe_fence = NULL;
493 r = amdgpu_fill_buffer(ttm_to_amdgpu_bo(bo), AMDGPU_POISON,
497 } else if (wipe_fence) {
498 dma_fence_put(fence);
503 /* Always block for VM page tables before committing the new location */
504 if (bo->type == ttm_bo_type_kernel)
505 r = ttm_bo_move_accel_cleanup(bo, fence, true, false, new_mem);
507 r = ttm_bo_move_accel_cleanup(bo, fence, evict, true, new_mem);
508 dma_fence_put(fence);
513 dma_fence_wait(fence, false);
514 dma_fence_put(fence);
519 * amdgpu_move_vram_ram - Copy VRAM buffer to RAM buffer
521 * Called by amdgpu_bo_move().
523 static int amdgpu_move_vram_ram(struct ttm_buffer_object *bo, bool evict,
524 struct ttm_operation_ctx *ctx,
525 struct ttm_resource *new_mem)
527 struct ttm_resource *old_mem = &bo->mem;
528 struct ttm_resource tmp_mem;
529 struct ttm_place placements;
530 struct ttm_placement placement;
533 /* create space/pages for new_mem in GTT space */
535 tmp_mem.mm_node = NULL;
536 placement.num_placement = 1;
537 placement.placement = &placements;
538 placement.num_busy_placement = 1;
539 placement.busy_placement = &placements;
542 placements.mem_type = TTM_PL_TT;
543 placements.flags = 0;
544 r = ttm_bo_mem_space(bo, &placement, &tmp_mem, ctx);
546 pr_err("Failed to find GTT space for blit from VRAM\n");
550 r = ttm_tt_populate(bo->bdev, bo->ttm, ctx);
554 /* Bind the memory to the GTT space */
555 r = amdgpu_ttm_backend_bind(bo->bdev, bo->ttm, &tmp_mem);
560 /* blit VRAM to GTT */
561 r = amdgpu_move_blit(bo, evict, &tmp_mem, old_mem);
566 r = ttm_bo_wait_ctx(bo, ctx);
570 amdgpu_ttm_backend_unbind(bo->bdev, bo->ttm);
571 ttm_resource_free(bo, &bo->mem);
572 ttm_bo_assign_mem(bo, new_mem);
574 ttm_resource_free(bo, &tmp_mem);
579 * amdgpu_move_ram_vram - Copy buffer from RAM to VRAM
581 * Called by amdgpu_bo_move().
583 static int amdgpu_move_ram_vram(struct ttm_buffer_object *bo, bool evict,
584 struct ttm_operation_ctx *ctx,
585 struct ttm_resource *new_mem)
587 struct ttm_resource *old_mem = &bo->mem;
588 struct ttm_resource tmp_mem;
589 struct ttm_placement placement;
590 struct ttm_place placements;
593 /* make space in GTT for old_mem buffer */
595 tmp_mem.mm_node = NULL;
596 placement.num_placement = 1;
597 placement.placement = &placements;
598 placement.num_busy_placement = 1;
599 placement.busy_placement = &placements;
602 placements.mem_type = TTM_PL_TT;
603 placements.flags = 0;
604 r = ttm_bo_mem_space(bo, &placement, &tmp_mem, ctx);
606 pr_err("Failed to find GTT space for blit to VRAM\n");
610 /* move/bind old memory to GTT space */
611 r = ttm_tt_populate(bo->bdev, bo->ttm, ctx);
615 r = amdgpu_ttm_backend_bind(bo->bdev, bo->ttm, &tmp_mem);
620 ttm_bo_assign_mem(bo, &tmp_mem);
622 r = amdgpu_move_blit(bo, evict, new_mem, old_mem);
627 ttm_resource_free(bo, &tmp_mem);
632 * amdgpu_mem_visible - Check that memory can be accessed by ttm_bo_move_memcpy
634 * Called by amdgpu_bo_move()
636 static bool amdgpu_mem_visible(struct amdgpu_device *adev,
637 struct ttm_resource *mem)
639 struct drm_mm_node *nodes = mem->mm_node;
641 if (mem->mem_type == TTM_PL_SYSTEM ||
642 mem->mem_type == TTM_PL_TT)
644 if (mem->mem_type != TTM_PL_VRAM)
647 /* ttm_resource_ioremap only supports contiguous memory */
648 if (nodes->size != mem->num_pages)
651 return ((nodes->start + nodes->size) << PAGE_SHIFT)
652 <= adev->gmc.visible_vram_size;
656 * amdgpu_bo_move - Move a buffer object to a new memory location
658 * Called by ttm_bo_handle_move_mem()
660 static int amdgpu_bo_move(struct ttm_buffer_object *bo, bool evict,
661 struct ttm_operation_ctx *ctx,
662 struct ttm_resource *new_mem)
664 struct amdgpu_device *adev;
665 struct amdgpu_bo *abo;
666 struct ttm_resource *old_mem = &bo->mem;
669 if (new_mem->mem_type == TTM_PL_TT) {
670 r = amdgpu_ttm_backend_bind(bo->bdev, bo->ttm, new_mem);
675 amdgpu_bo_move_notify(bo, evict, new_mem);
677 /* Can't move a pinned BO */
678 abo = ttm_to_amdgpu_bo(bo);
679 if (WARN_ON_ONCE(abo->tbo.pin_count > 0))
682 adev = amdgpu_ttm_adev(bo->bdev);
684 if (old_mem->mem_type == TTM_PL_SYSTEM && bo->ttm == NULL) {
685 ttm_bo_move_null(bo, new_mem);
688 if (old_mem->mem_type == TTM_PL_SYSTEM &&
689 new_mem->mem_type == TTM_PL_TT) {
690 ttm_bo_move_null(bo, new_mem);
694 if (old_mem->mem_type == TTM_PL_TT &&
695 new_mem->mem_type == TTM_PL_SYSTEM) {
696 r = ttm_bo_wait_ctx(bo, ctx);
700 amdgpu_ttm_backend_unbind(bo->bdev, bo->ttm);
701 ttm_resource_free(bo, &bo->mem);
702 ttm_bo_assign_mem(bo, new_mem);
706 if (old_mem->mem_type == AMDGPU_PL_GDS ||
707 old_mem->mem_type == AMDGPU_PL_GWS ||
708 old_mem->mem_type == AMDGPU_PL_OA ||
709 new_mem->mem_type == AMDGPU_PL_GDS ||
710 new_mem->mem_type == AMDGPU_PL_GWS ||
711 new_mem->mem_type == AMDGPU_PL_OA) {
712 /* Nothing to save here */
713 ttm_bo_move_null(bo, new_mem);
717 if (!adev->mman.buffer_funcs_enabled) {
722 if (old_mem->mem_type == TTM_PL_VRAM &&
723 new_mem->mem_type == TTM_PL_SYSTEM) {
724 r = amdgpu_move_vram_ram(bo, evict, ctx, new_mem);
725 } else if (old_mem->mem_type == TTM_PL_SYSTEM &&
726 new_mem->mem_type == TTM_PL_VRAM) {
727 r = amdgpu_move_ram_vram(bo, evict, ctx, new_mem);
729 r = amdgpu_move_blit(bo, evict,
735 /* Check that all memory is CPU accessible */
736 if (!amdgpu_mem_visible(adev, old_mem) ||
737 !amdgpu_mem_visible(adev, new_mem)) {
738 pr_err("Move buffer fallback to memcpy unavailable\n");
742 r = ttm_bo_move_memcpy(bo, ctx, new_mem);
747 if (bo->type == ttm_bo_type_device &&
748 new_mem->mem_type == TTM_PL_VRAM &&
749 old_mem->mem_type != TTM_PL_VRAM) {
750 /* amdgpu_bo_fault_reserve_notify will re-set this if the CPU
751 * accesses the BO after it's moved.
753 abo->flags &= ~AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED;
756 /* update statistics */
757 atomic64_add((u64)bo->num_pages << PAGE_SHIFT, &adev->num_bytes_moved);
760 swap(*new_mem, bo->mem);
761 amdgpu_bo_move_notify(bo, false, new_mem);
762 swap(*new_mem, bo->mem);
767 * amdgpu_ttm_io_mem_reserve - Reserve a block of memory during a fault
769 * Called by ttm_mem_io_reserve() ultimately via ttm_bo_vm_fault()
771 static int amdgpu_ttm_io_mem_reserve(struct ttm_bo_device *bdev, struct ttm_resource *mem)
773 struct amdgpu_device *adev = amdgpu_ttm_adev(bdev);
774 struct drm_mm_node *mm_node = mem->mm_node;
775 size_t bus_size = (size_t)mem->num_pages << PAGE_SHIFT;
777 switch (mem->mem_type) {
784 mem->bus.offset = mem->start << PAGE_SHIFT;
785 /* check if it's visible */
786 if ((mem->bus.offset + bus_size) > adev->gmc.visible_vram_size)
788 /* Only physically contiguous buffers apply. In a contiguous
789 * buffer, size of the first mm_node would match the number of
790 * pages in ttm_resource.
792 if (adev->mman.aper_base_kaddr &&
793 (mm_node->size == mem->num_pages))
794 mem->bus.addr = (u8 *)adev->mman.aper_base_kaddr +
797 mem->bus.offset += adev->gmc.aper_base;
798 mem->bus.is_iomem = true;
799 mem->bus.caching = ttm_write_combined;
807 static unsigned long amdgpu_ttm_io_mem_pfn(struct ttm_buffer_object *bo,
808 unsigned long page_offset)
810 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev);
811 uint64_t offset = (page_offset << PAGE_SHIFT);
812 struct drm_mm_node *mm;
814 mm = amdgpu_find_mm_node(&bo->mem, &offset);
815 offset += adev->gmc.aper_base;
816 return mm->start + (offset >> PAGE_SHIFT);
820 * amdgpu_ttm_domain_start - Returns GPU start address
821 * @adev: amdgpu device object
822 * @type: type of the memory
825 * GPU start address of a memory domain
828 uint64_t amdgpu_ttm_domain_start(struct amdgpu_device *adev, uint32_t type)
832 return adev->gmc.gart_start;
834 return adev->gmc.vram_start;
841 * TTM backend functions.
843 struct amdgpu_ttm_tt {
844 struct ttm_dma_tt ttm;
845 struct drm_gem_object *gobj;
848 struct task_struct *usertask;
851 #if IS_ENABLED(CONFIG_DRM_AMDGPU_USERPTR)
852 struct hmm_range *range;
856 #ifdef CONFIG_DRM_AMDGPU_USERPTR
858 * amdgpu_ttm_tt_get_user_pages - get device accessible pages that back user
859 * memory and start HMM tracking CPU page table update
861 * Calling function must call amdgpu_ttm_tt_userptr_range_done() once and only
862 * once afterwards to stop HMM tracking
864 int amdgpu_ttm_tt_get_user_pages(struct amdgpu_bo *bo, struct page **pages)
866 struct ttm_tt *ttm = bo->tbo.ttm;
867 struct amdgpu_ttm_tt *gtt = (void *)ttm;
868 unsigned long start = gtt->userptr;
869 struct vm_area_struct *vma;
870 struct hmm_range *range;
871 unsigned long timeout;
872 struct mm_struct *mm;
876 mm = bo->notifier.mm;
878 DRM_DEBUG_DRIVER("BO is not registered?\n");
882 /* Another get_user_pages is running at the same time?? */
883 if (WARN_ON(gtt->range))
886 if (!mmget_not_zero(mm)) /* Happens during process shutdown */
889 range = kzalloc(sizeof(*range), GFP_KERNEL);
890 if (unlikely(!range)) {
894 range->notifier = &bo->notifier;
895 range->start = bo->notifier.interval_tree.start;
896 range->end = bo->notifier.interval_tree.last + 1;
897 range->default_flags = HMM_PFN_REQ_FAULT;
898 if (!amdgpu_ttm_tt_is_readonly(ttm))
899 range->default_flags |= HMM_PFN_REQ_WRITE;
901 range->hmm_pfns = kvmalloc_array(ttm->num_pages,
902 sizeof(*range->hmm_pfns), GFP_KERNEL);
903 if (unlikely(!range->hmm_pfns)) {
905 goto out_free_ranges;
909 vma = find_vma(mm, start);
910 if (unlikely(!vma || start < vma->vm_start)) {
914 if (unlikely((gtt->userflags & AMDGPU_GEM_USERPTR_ANONONLY) &&
919 mmap_read_unlock(mm);
920 timeout = jiffies + msecs_to_jiffies(HMM_RANGE_DEFAULT_TIMEOUT);
923 range->notifier_seq = mmu_interval_read_begin(&bo->notifier);
926 r = hmm_range_fault(range);
927 mmap_read_unlock(mm);
930 * FIXME: This timeout should encompass the retry from
931 * mmu_interval_read_retry() as well.
933 if (r == -EBUSY && !time_after(jiffies, timeout))
939 * Due to default_flags, all pages are HMM_PFN_VALID or
940 * hmm_range_fault() fails. FIXME: The pages cannot be touched outside
941 * the notifier_lock, and mmu_interval_read_retry() must be done first.
943 for (i = 0; i < ttm->num_pages; i++)
944 pages[i] = hmm_pfn_to_page(range->hmm_pfns[i]);
952 mmap_read_unlock(mm);
954 kvfree(range->hmm_pfns);
963 * amdgpu_ttm_tt_userptr_range_done - stop HMM track the CPU page table change
964 * Check if the pages backing this ttm range have been invalidated
966 * Returns: true if pages are still valid
968 bool amdgpu_ttm_tt_get_user_pages_done(struct ttm_tt *ttm)
970 struct amdgpu_ttm_tt *gtt = (void *)ttm;
973 if (!gtt || !gtt->userptr)
976 DRM_DEBUG_DRIVER("user_pages_done 0x%llx pages 0x%lx\n",
977 gtt->userptr, ttm->num_pages);
979 WARN_ONCE(!gtt->range || !gtt->range->hmm_pfns,
980 "No user pages to check\n");
984 * FIXME: Must always hold notifier_lock for this, and must
985 * not ignore the return code.
987 r = mmu_interval_read_retry(gtt->range->notifier,
988 gtt->range->notifier_seq);
989 kvfree(gtt->range->hmm_pfns);
999 * amdgpu_ttm_tt_set_user_pages - Copy pages in, putting old pages as necessary.
1001 * Called by amdgpu_cs_list_validate(). This creates the page list
1002 * that backs user memory and will ultimately be mapped into the device
1005 void amdgpu_ttm_tt_set_user_pages(struct ttm_tt *ttm, struct page **pages)
1009 for (i = 0; i < ttm->num_pages; ++i)
1010 ttm->pages[i] = pages ? pages[i] : NULL;
1014 * amdgpu_ttm_tt_pin_userptr - prepare the sg table with the user pages
1016 * Called by amdgpu_ttm_backend_bind()
1018 static int amdgpu_ttm_tt_pin_userptr(struct ttm_bo_device *bdev,
1021 struct amdgpu_device *adev = amdgpu_ttm_adev(bdev);
1022 struct amdgpu_ttm_tt *gtt = (void *)ttm;
1025 int write = !(gtt->userflags & AMDGPU_GEM_USERPTR_READONLY);
1026 enum dma_data_direction direction = write ?
1027 DMA_BIDIRECTIONAL : DMA_TO_DEVICE;
1029 /* Allocate an SG array and squash pages into it */
1030 r = sg_alloc_table_from_pages(ttm->sg, ttm->pages, ttm->num_pages, 0,
1031 ttm->num_pages << PAGE_SHIFT,
1036 /* Map SG to device */
1037 r = dma_map_sgtable(adev->dev, ttm->sg, direction, 0);
1041 /* convert SG to linear array of pages and dma addresses */
1042 drm_prime_sg_to_page_addr_arrays(ttm->sg, ttm->pages,
1043 gtt->ttm.dma_address, ttm->num_pages);
1053 * amdgpu_ttm_tt_unpin_userptr - Unpin and unmap userptr pages
1055 static void amdgpu_ttm_tt_unpin_userptr(struct ttm_bo_device *bdev,
1058 struct amdgpu_device *adev = amdgpu_ttm_adev(bdev);
1059 struct amdgpu_ttm_tt *gtt = (void *)ttm;
1061 int write = !(gtt->userflags & AMDGPU_GEM_USERPTR_READONLY);
1062 enum dma_data_direction direction = write ?
1063 DMA_BIDIRECTIONAL : DMA_TO_DEVICE;
1065 /* double check that we don't free the table twice */
1069 /* unmap the pages mapped to the device */
1070 dma_unmap_sgtable(adev->dev, ttm->sg, direction, 0);
1071 sg_free_table(ttm->sg);
1073 #if IS_ENABLED(CONFIG_DRM_AMDGPU_USERPTR)
1077 for (i = 0; i < ttm->num_pages; i++) {
1078 if (ttm->pages[i] !=
1079 hmm_pfn_to_page(gtt->range->hmm_pfns[i]))
1083 WARN((i == ttm->num_pages), "Missing get_user_page_done\n");
1088 static int amdgpu_ttm_gart_bind(struct amdgpu_device *adev,
1089 struct ttm_buffer_object *tbo,
1092 struct amdgpu_bo *abo = ttm_to_amdgpu_bo(tbo);
1093 struct ttm_tt *ttm = tbo->ttm;
1094 struct amdgpu_ttm_tt *gtt = (void *)ttm;
1097 if (amdgpu_bo_encrypted(abo))
1098 flags |= AMDGPU_PTE_TMZ;
1100 if (abo->flags & AMDGPU_GEM_CREATE_CP_MQD_GFX9) {
1101 uint64_t page_idx = 1;
1103 r = amdgpu_gart_bind(adev, gtt->offset, page_idx,
1104 ttm->pages, gtt->ttm.dma_address, flags);
1106 goto gart_bind_fail;
1108 /* The memory type of the first page defaults to UC. Now
1109 * modify the memory type to NC from the second page of
1112 flags &= ~AMDGPU_PTE_MTYPE_VG10_MASK;
1113 flags |= AMDGPU_PTE_MTYPE_VG10(AMDGPU_MTYPE_NC);
1115 r = amdgpu_gart_bind(adev,
1116 gtt->offset + (page_idx << PAGE_SHIFT),
1117 ttm->num_pages - page_idx,
1118 &ttm->pages[page_idx],
1119 &(gtt->ttm.dma_address[page_idx]), flags);
1121 r = amdgpu_gart_bind(adev, gtt->offset, ttm->num_pages,
1122 ttm->pages, gtt->ttm.dma_address, flags);
1127 DRM_ERROR("failed to bind %lu pages at 0x%08llX\n",
1128 ttm->num_pages, gtt->offset);
1134 * amdgpu_ttm_backend_bind - Bind GTT memory
1136 * Called by ttm_tt_bind() on behalf of ttm_bo_handle_move_mem().
1137 * This handles binding GTT memory to the device address space.
1139 static int amdgpu_ttm_backend_bind(struct ttm_bo_device *bdev,
1141 struct ttm_resource *bo_mem)
1143 struct amdgpu_device *adev = amdgpu_ttm_adev(bdev);
1144 struct amdgpu_ttm_tt *gtt = (void*)ttm;
1155 r = amdgpu_ttm_tt_pin_userptr(bdev, ttm);
1157 DRM_ERROR("failed to pin userptr\n");
1161 if (!ttm->num_pages) {
1162 WARN(1, "nothing to bind %lu pages for mreg %p back %p!\n",
1163 ttm->num_pages, bo_mem, ttm);
1166 if (bo_mem->mem_type == AMDGPU_PL_GDS ||
1167 bo_mem->mem_type == AMDGPU_PL_GWS ||
1168 bo_mem->mem_type == AMDGPU_PL_OA)
1171 if (!amdgpu_gtt_mgr_has_gart_addr(bo_mem)) {
1172 gtt->offset = AMDGPU_BO_INVALID_OFFSET;
1176 /* compute PTE flags relevant to this BO memory */
1177 flags = amdgpu_ttm_tt_pte_flags(adev, ttm, bo_mem);
1179 /* bind pages into GART page tables */
1180 gtt->offset = (u64)bo_mem->start << PAGE_SHIFT;
1181 r = amdgpu_gart_bind(adev, gtt->offset, ttm->num_pages,
1182 ttm->pages, gtt->ttm.dma_address, flags);
1185 DRM_ERROR("failed to bind %lu pages at 0x%08llX\n",
1186 ttm->num_pages, gtt->offset);
1192 * amdgpu_ttm_alloc_gart - Allocate GART memory for buffer object
1194 int amdgpu_ttm_alloc_gart(struct ttm_buffer_object *bo)
1196 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev);
1197 struct ttm_operation_ctx ctx = { false, false };
1198 struct amdgpu_ttm_tt *gtt = (void*)bo->ttm;
1199 struct ttm_resource tmp;
1200 struct ttm_placement placement;
1201 struct ttm_place placements;
1202 uint64_t addr, flags;
1205 if (bo->mem.start != AMDGPU_BO_INVALID_OFFSET)
1208 addr = amdgpu_gmc_agp_addr(bo);
1209 if (addr != AMDGPU_BO_INVALID_OFFSET) {
1210 bo->mem.start = addr >> PAGE_SHIFT;
1213 /* allocate GART space */
1216 placement.num_placement = 1;
1217 placement.placement = &placements;
1218 placement.num_busy_placement = 1;
1219 placement.busy_placement = &placements;
1220 placements.fpfn = 0;
1221 placements.lpfn = adev->gmc.gart_size >> PAGE_SHIFT;
1222 placements.mem_type = TTM_PL_TT;
1223 placements.flags = bo->mem.placement;
1225 r = ttm_bo_mem_space(bo, &placement, &tmp, &ctx);
1229 /* compute PTE flags for this buffer object */
1230 flags = amdgpu_ttm_tt_pte_flags(adev, bo->ttm, &tmp);
1233 gtt->offset = (u64)tmp.start << PAGE_SHIFT;
1234 r = amdgpu_ttm_gart_bind(adev, bo, flags);
1236 ttm_resource_free(bo, &tmp);
1240 ttm_resource_free(bo, &bo->mem);
1248 * amdgpu_ttm_recover_gart - Rebind GTT pages
1250 * Called by amdgpu_gtt_mgr_recover() from amdgpu_device_reset() to
1251 * rebind GTT pages during a GPU reset.
1253 int amdgpu_ttm_recover_gart(struct ttm_buffer_object *tbo)
1255 struct amdgpu_device *adev = amdgpu_ttm_adev(tbo->bdev);
1262 flags = amdgpu_ttm_tt_pte_flags(adev, tbo->ttm, &tbo->mem);
1263 r = amdgpu_ttm_gart_bind(adev, tbo, flags);
1269 * amdgpu_ttm_backend_unbind - Unbind GTT mapped pages
1271 * Called by ttm_tt_unbind() on behalf of ttm_bo_move_ttm() and
1274 static void amdgpu_ttm_backend_unbind(struct ttm_bo_device *bdev,
1277 struct amdgpu_device *adev = amdgpu_ttm_adev(bdev);
1278 struct amdgpu_ttm_tt *gtt = (void *)ttm;
1284 /* if the pages have userptr pinning then clear that first */
1286 amdgpu_ttm_tt_unpin_userptr(bdev, ttm);
1288 if (gtt->offset == AMDGPU_BO_INVALID_OFFSET)
1291 /* unbind shouldn't be done for GDS/GWS/OA in ttm_bo_clean_mm */
1292 r = amdgpu_gart_unbind(adev, gtt->offset, ttm->num_pages);
1294 DRM_ERROR("failed to unbind %lu pages at 0x%08llX\n",
1295 gtt->ttm.ttm.num_pages, gtt->offset);
1299 static void amdgpu_ttm_backend_destroy(struct ttm_bo_device *bdev,
1302 struct amdgpu_ttm_tt *gtt = (void *)ttm;
1304 amdgpu_ttm_backend_unbind(bdev, ttm);
1305 ttm_tt_destroy_common(bdev, ttm);
1307 put_task_struct(gtt->usertask);
1309 ttm_dma_tt_fini(>t->ttm);
1314 * amdgpu_ttm_tt_create - Create a ttm_tt object for a given BO
1316 * @bo: The buffer object to create a GTT ttm_tt object around
1318 * Called by ttm_tt_create().
1320 static struct ttm_tt *amdgpu_ttm_tt_create(struct ttm_buffer_object *bo,
1321 uint32_t page_flags)
1323 struct amdgpu_bo *abo = ttm_to_amdgpu_bo(bo);
1324 struct amdgpu_ttm_tt *gtt;
1325 enum ttm_caching caching;
1327 gtt = kzalloc(sizeof(struct amdgpu_ttm_tt), GFP_KERNEL);
1331 gtt->gobj = &bo->base;
1333 if (abo->flags & AMDGPU_GEM_CREATE_CPU_GTT_USWC)
1334 caching = ttm_write_combined;
1336 caching = ttm_cached;
1338 /* allocate space for the uninitialized page entries */
1339 if (ttm_sg_tt_init(>t->ttm, bo, page_flags, caching)) {
1343 return >t->ttm.ttm;
1347 * amdgpu_ttm_tt_populate - Map GTT pages visible to the device
1349 * Map the pages of a ttm_tt object to an address space visible
1350 * to the underlying device.
1352 static int amdgpu_ttm_tt_populate(struct ttm_bo_device *bdev,
1354 struct ttm_operation_ctx *ctx)
1356 struct amdgpu_device *adev = amdgpu_ttm_adev(bdev);
1357 struct amdgpu_ttm_tt *gtt = (void *)ttm;
1359 /* user pages are bound by amdgpu_ttm_tt_pin_userptr() */
1360 if (gtt && gtt->userptr) {
1361 ttm->sg = kzalloc(sizeof(struct sg_table), GFP_KERNEL);
1365 ttm->page_flags |= TTM_PAGE_FLAG_SG;
1369 if (ttm->page_flags & TTM_PAGE_FLAG_SG) {
1371 struct dma_buf_attachment *attach;
1372 struct sg_table *sgt;
1374 attach = gtt->gobj->import_attach;
1375 sgt = dma_buf_map_attachment(attach, DMA_BIDIRECTIONAL);
1377 return PTR_ERR(sgt);
1382 drm_prime_sg_to_page_addr_arrays(ttm->sg, ttm->pages,
1383 gtt->ttm.dma_address,
1388 #ifdef CONFIG_SWIOTLB
1389 if (adev->need_swiotlb && swiotlb_nr_tbl()) {
1390 return ttm_dma_populate(>t->ttm, adev->dev, ctx);
1394 /* fall back to generic helper to populate the page array
1395 * and map them to the device */
1396 return ttm_populate_and_map_pages(adev->dev, >t->ttm, ctx);
1400 * amdgpu_ttm_tt_unpopulate - unmap GTT pages and unpopulate page arrays
1402 * Unmaps pages of a ttm_tt object from the device address space and
1403 * unpopulates the page array backing it.
1405 static void amdgpu_ttm_tt_unpopulate(struct ttm_bo_device *bdev, struct ttm_tt *ttm)
1407 struct amdgpu_ttm_tt *gtt = (void *)ttm;
1408 struct amdgpu_device *adev;
1410 if (gtt && gtt->userptr) {
1411 amdgpu_ttm_tt_set_user_pages(ttm, NULL);
1413 ttm->page_flags &= ~TTM_PAGE_FLAG_SG;
1417 if (ttm->sg && gtt->gobj->import_attach) {
1418 struct dma_buf_attachment *attach;
1420 attach = gtt->gobj->import_attach;
1421 dma_buf_unmap_attachment(attach, ttm->sg, DMA_BIDIRECTIONAL);
1426 if (ttm->page_flags & TTM_PAGE_FLAG_SG)
1429 adev = amdgpu_ttm_adev(bdev);
1431 #ifdef CONFIG_SWIOTLB
1432 if (adev->need_swiotlb && swiotlb_nr_tbl()) {
1433 ttm_dma_unpopulate(>t->ttm, adev->dev);
1438 /* fall back to generic helper to unmap and unpopulate array */
1439 ttm_unmap_and_unpopulate_pages(adev->dev, >t->ttm);
1443 * amdgpu_ttm_tt_set_userptr - Initialize userptr GTT ttm_tt for the current
1446 * @bo: The ttm_buffer_object to bind this userptr to
1447 * @addr: The address in the current tasks VM space to use
1448 * @flags: Requirements of userptr object.
1450 * Called by amdgpu_gem_userptr_ioctl() to bind userptr pages
1453 int amdgpu_ttm_tt_set_userptr(struct ttm_buffer_object *bo,
1454 uint64_t addr, uint32_t flags)
1456 struct amdgpu_ttm_tt *gtt;
1459 /* TODO: We want a separate TTM object type for userptrs */
1460 bo->ttm = amdgpu_ttm_tt_create(bo, 0);
1461 if (bo->ttm == NULL)
1465 gtt = (void*)bo->ttm;
1466 gtt->userptr = addr;
1467 gtt->userflags = flags;
1470 put_task_struct(gtt->usertask);
1471 gtt->usertask = current->group_leader;
1472 get_task_struct(gtt->usertask);
1478 * amdgpu_ttm_tt_get_usermm - Return memory manager for ttm_tt object
1480 struct mm_struct *amdgpu_ttm_tt_get_usermm(struct ttm_tt *ttm)
1482 struct amdgpu_ttm_tt *gtt = (void *)ttm;
1487 if (gtt->usertask == NULL)
1490 return gtt->usertask->mm;
1494 * amdgpu_ttm_tt_affect_userptr - Determine if a ttm_tt object lays inside an
1495 * address range for the current task.
1498 bool amdgpu_ttm_tt_affect_userptr(struct ttm_tt *ttm, unsigned long start,
1501 struct amdgpu_ttm_tt *gtt = (void *)ttm;
1504 if (gtt == NULL || !gtt->userptr)
1507 /* Return false if no part of the ttm_tt object lies within
1510 size = (unsigned long)gtt->ttm.ttm.num_pages * PAGE_SIZE;
1511 if (gtt->userptr > end || gtt->userptr + size <= start)
1518 * amdgpu_ttm_tt_is_userptr - Have the pages backing by userptr?
1520 bool amdgpu_ttm_tt_is_userptr(struct ttm_tt *ttm)
1522 struct amdgpu_ttm_tt *gtt = (void *)ttm;
1524 if (gtt == NULL || !gtt->userptr)
1531 * amdgpu_ttm_tt_is_readonly - Is the ttm_tt object read only?
1533 bool amdgpu_ttm_tt_is_readonly(struct ttm_tt *ttm)
1535 struct amdgpu_ttm_tt *gtt = (void *)ttm;
1540 return !!(gtt->userflags & AMDGPU_GEM_USERPTR_READONLY);
1544 * amdgpu_ttm_tt_pde_flags - Compute PDE flags for ttm_tt object
1546 * @ttm: The ttm_tt object to compute the flags for
1547 * @mem: The memory registry backing this ttm_tt object
1549 * Figure out the flags to use for a VM PDE (Page Directory Entry).
1551 uint64_t amdgpu_ttm_tt_pde_flags(struct ttm_tt *ttm, struct ttm_resource *mem)
1555 if (mem && mem->mem_type != TTM_PL_SYSTEM)
1556 flags |= AMDGPU_PTE_VALID;
1558 if (mem && mem->mem_type == TTM_PL_TT) {
1559 flags |= AMDGPU_PTE_SYSTEM;
1561 if (ttm->caching == ttm_cached)
1562 flags |= AMDGPU_PTE_SNOOPED;
1569 * amdgpu_ttm_tt_pte_flags - Compute PTE flags for ttm_tt object
1571 * @ttm: The ttm_tt object to compute the flags for
1572 * @mem: The memory registry backing this ttm_tt object
1574 * Figure out the flags to use for a VM PTE (Page Table Entry).
1576 uint64_t amdgpu_ttm_tt_pte_flags(struct amdgpu_device *adev, struct ttm_tt *ttm,
1577 struct ttm_resource *mem)
1579 uint64_t flags = amdgpu_ttm_tt_pde_flags(ttm, mem);
1581 flags |= adev->gart.gart_pte_flags;
1582 flags |= AMDGPU_PTE_READABLE;
1584 if (!amdgpu_ttm_tt_is_readonly(ttm))
1585 flags |= AMDGPU_PTE_WRITEABLE;
1591 * amdgpu_ttm_bo_eviction_valuable - Check to see if we can evict a buffer
1594 * Return true if eviction is sensible. Called by ttm_mem_evict_first() on
1595 * behalf of ttm_bo_mem_force_space() which tries to evict buffer objects until
1596 * it can find space for a new object and by ttm_bo_force_list_clean() which is
1597 * used to clean out a memory space.
1599 static bool amdgpu_ttm_bo_eviction_valuable(struct ttm_buffer_object *bo,
1600 const struct ttm_place *place)
1602 unsigned long num_pages = bo->mem.num_pages;
1603 struct drm_mm_node *node = bo->mem.mm_node;
1604 struct dma_resv_list *flist;
1605 struct dma_fence *f;
1608 if (bo->type == ttm_bo_type_kernel &&
1609 !amdgpu_vm_evictable(ttm_to_amdgpu_bo(bo)))
1612 /* If bo is a KFD BO, check if the bo belongs to the current process.
1613 * If true, then return false as any KFD process needs all its BOs to
1614 * be resident to run successfully
1616 flist = dma_resv_get_list(bo->base.resv);
1618 for (i = 0; i < flist->shared_count; ++i) {
1619 f = rcu_dereference_protected(flist->shared[i],
1620 dma_resv_held(bo->base.resv));
1621 if (amdkfd_fence_check_mm(f, current->mm))
1626 switch (bo->mem.mem_type) {
1628 if (amdgpu_bo_is_amdgpu_bo(bo) &&
1629 amdgpu_bo_encrypted(ttm_to_amdgpu_bo(bo)))
1634 /* Check each drm MM node individually */
1636 if (place->fpfn < (node->start + node->size) &&
1637 !(place->lpfn && place->lpfn <= node->start))
1640 num_pages -= node->size;
1649 return ttm_bo_eviction_valuable(bo, place);
1653 * amdgpu_ttm_access_memory - Read or Write memory that backs a buffer object.
1655 * @bo: The buffer object to read/write
1656 * @offset: Offset into buffer object
1657 * @buf: Secondary buffer to write/read from
1658 * @len: Length in bytes of access
1659 * @write: true if writing
1661 * This is used to access VRAM that backs a buffer object via MMIO
1662 * access for debugging purposes.
1664 static int amdgpu_ttm_access_memory(struct ttm_buffer_object *bo,
1665 unsigned long offset,
1666 void *buf, int len, int write)
1668 struct amdgpu_bo *abo = ttm_to_amdgpu_bo(bo);
1669 struct amdgpu_device *adev = amdgpu_ttm_adev(abo->tbo.bdev);
1670 struct drm_mm_node *nodes;
1674 unsigned long flags;
1676 if (bo->mem.mem_type != TTM_PL_VRAM)
1680 nodes = amdgpu_find_mm_node(&abo->tbo.mem, &pos);
1681 pos += (nodes->start << PAGE_SHIFT);
1683 while (len && pos < adev->gmc.mc_vram_size) {
1684 uint64_t aligned_pos = pos & ~(uint64_t)3;
1685 uint64_t bytes = 4 - (pos & 3);
1686 uint32_t shift = (pos & 3) * 8;
1687 uint32_t mask = 0xffffffff << shift;
1690 mask &= 0xffffffff >> (bytes - len) * 8;
1694 if (mask != 0xffffffff) {
1695 spin_lock_irqsave(&adev->mmio_idx_lock, flags);
1696 WREG32_NO_KIQ(mmMM_INDEX, ((uint32_t)aligned_pos) | 0x80000000);
1697 WREG32_NO_KIQ(mmMM_INDEX_HI, aligned_pos >> 31);
1698 if (!write || mask != 0xffffffff)
1699 value = RREG32_NO_KIQ(mmMM_DATA);
1702 value |= (*(uint32_t *)buf << shift) & mask;
1703 WREG32_NO_KIQ(mmMM_DATA, value);
1705 spin_unlock_irqrestore(&adev->mmio_idx_lock, flags);
1707 value = (value & mask) >> shift;
1708 memcpy(buf, &value, bytes);
1711 bytes = (nodes->start + nodes->size) << PAGE_SHIFT;
1712 bytes = min(bytes - pos, (uint64_t)len & ~0x3ull);
1714 amdgpu_device_vram_access(adev, pos, (uint32_t *)buf,
1719 buf = (uint8_t *)buf + bytes;
1722 if (pos >= (nodes->start + nodes->size) << PAGE_SHIFT) {
1724 pos = (nodes->start << PAGE_SHIFT);
1732 amdgpu_bo_delete_mem_notify(struct ttm_buffer_object *bo)
1734 amdgpu_bo_move_notify(bo, false, NULL);
1737 static struct ttm_bo_driver amdgpu_bo_driver = {
1738 .ttm_tt_create = &amdgpu_ttm_tt_create,
1739 .ttm_tt_populate = &amdgpu_ttm_tt_populate,
1740 .ttm_tt_unpopulate = &amdgpu_ttm_tt_unpopulate,
1741 .ttm_tt_destroy = &amdgpu_ttm_backend_destroy,
1742 .eviction_valuable = amdgpu_ttm_bo_eviction_valuable,
1743 .evict_flags = &amdgpu_evict_flags,
1744 .move = &amdgpu_bo_move,
1745 .verify_access = &amdgpu_verify_access,
1746 .delete_mem_notify = &amdgpu_bo_delete_mem_notify,
1747 .release_notify = &amdgpu_bo_release_notify,
1748 .io_mem_reserve = &amdgpu_ttm_io_mem_reserve,
1749 .io_mem_pfn = amdgpu_ttm_io_mem_pfn,
1750 .access_memory = &amdgpu_ttm_access_memory,
1751 .del_from_lru_notify = &amdgpu_vm_del_from_lru_notify
1755 * Firmware Reservation functions
1758 * amdgpu_ttm_fw_reserve_vram_fini - free fw reserved vram
1760 * @adev: amdgpu_device pointer
1762 * free fw reserved vram if it has been reserved.
1764 static void amdgpu_ttm_fw_reserve_vram_fini(struct amdgpu_device *adev)
1766 amdgpu_bo_free_kernel(&adev->mman.fw_vram_usage_reserved_bo,
1767 NULL, &adev->mman.fw_vram_usage_va);
1771 * amdgpu_ttm_fw_reserve_vram_init - create bo vram reservation from fw
1773 * @adev: amdgpu_device pointer
1775 * create bo vram reservation from fw.
1777 static int amdgpu_ttm_fw_reserve_vram_init(struct amdgpu_device *adev)
1779 uint64_t vram_size = adev->gmc.visible_vram_size;
1781 adev->mman.fw_vram_usage_va = NULL;
1782 adev->mman.fw_vram_usage_reserved_bo = NULL;
1784 if (adev->mman.fw_vram_usage_size == 0 ||
1785 adev->mman.fw_vram_usage_size > vram_size)
1788 return amdgpu_bo_create_kernel_at(adev,
1789 adev->mman.fw_vram_usage_start_offset,
1790 adev->mman.fw_vram_usage_size,
1791 AMDGPU_GEM_DOMAIN_VRAM,
1792 &adev->mman.fw_vram_usage_reserved_bo,
1793 &adev->mman.fw_vram_usage_va);
1797 * Memoy training reservation functions
1801 * amdgpu_ttm_training_reserve_vram_fini - free memory training reserved vram
1803 * @adev: amdgpu_device pointer
1805 * free memory training reserved vram if it has been reserved.
1807 static int amdgpu_ttm_training_reserve_vram_fini(struct amdgpu_device *adev)
1809 struct psp_memory_training_context *ctx = &adev->psp.mem_train_ctx;
1811 ctx->init = PSP_MEM_TRAIN_NOT_SUPPORT;
1812 amdgpu_bo_free_kernel(&ctx->c2p_bo, NULL, NULL);
1818 static void amdgpu_ttm_training_data_block_init(struct amdgpu_device *adev)
1820 struct psp_memory_training_context *ctx = &adev->psp.mem_train_ctx;
1822 memset(ctx, 0, sizeof(*ctx));
1824 ctx->c2p_train_data_offset =
1825 ALIGN((adev->gmc.mc_vram_size - adev->mman.discovery_tmr_size - SZ_1M), SZ_1M);
1826 ctx->p2c_train_data_offset =
1827 (adev->gmc.mc_vram_size - GDDR6_MEM_TRAINING_OFFSET);
1828 ctx->train_data_size =
1829 GDDR6_MEM_TRAINING_DATA_SIZE_IN_BYTES;
1831 DRM_DEBUG("train_data_size:%llx,p2c_train_data_offset:%llx,c2p_train_data_offset:%llx.\n",
1832 ctx->train_data_size,
1833 ctx->p2c_train_data_offset,
1834 ctx->c2p_train_data_offset);
1838 * reserve TMR memory at the top of VRAM which holds
1839 * IP Discovery data and is protected by PSP.
1841 static int amdgpu_ttm_reserve_tmr(struct amdgpu_device *adev)
1844 struct psp_memory_training_context *ctx = &adev->psp.mem_train_ctx;
1845 bool mem_train_support = false;
1847 if (!amdgpu_sriov_vf(adev)) {
1848 ret = amdgpu_mem_train_support(adev);
1850 mem_train_support = true;
1854 DRM_DEBUG("memory training does not support!\n");
1858 * Query reserved tmr size through atom firmwareinfo for Sienna_Cichlid and onwards for all
1859 * the use cases (IP discovery/G6 memory training/profiling/diagnostic data.etc)
1861 * Otherwise, fallback to legacy approach to check and reserve tmr block for ip
1862 * discovery data and G6 memory training data respectively
1864 adev->mman.discovery_tmr_size =
1865 amdgpu_atomfirmware_get_fw_reserved_fb_size(adev);
1866 if (!adev->mman.discovery_tmr_size)
1867 adev->mman.discovery_tmr_size = DISCOVERY_TMR_OFFSET;
1869 if (mem_train_support) {
1870 /* reserve vram for mem train according to TMR location */
1871 amdgpu_ttm_training_data_block_init(adev);
1872 ret = amdgpu_bo_create_kernel_at(adev,
1873 ctx->c2p_train_data_offset,
1874 ctx->train_data_size,
1875 AMDGPU_GEM_DOMAIN_VRAM,
1879 DRM_ERROR("alloc c2p_bo failed(%d)!\n", ret);
1880 amdgpu_ttm_training_reserve_vram_fini(adev);
1883 ctx->init = PSP_MEM_TRAIN_RESERVE_SUCCESS;
1886 ret = amdgpu_bo_create_kernel_at(adev,
1887 adev->gmc.real_vram_size - adev->mman.discovery_tmr_size,
1888 adev->mman.discovery_tmr_size,
1889 AMDGPU_GEM_DOMAIN_VRAM,
1890 &adev->mman.discovery_memory,
1893 DRM_ERROR("alloc tmr failed(%d)!\n", ret);
1894 amdgpu_bo_free_kernel(&adev->mman.discovery_memory, NULL, NULL);
1902 * amdgpu_ttm_init - Init the memory management (ttm) as well as various
1903 * gtt/vram related fields.
1905 * This initializes all of the memory space pools that the TTM layer
1906 * will need such as the GTT space (system memory mapped to the device),
1907 * VRAM (on-board memory), and on-chip memories (GDS, GWS, OA) which
1908 * can be mapped per VMID.
1910 int amdgpu_ttm_init(struct amdgpu_device *adev)
1916 mutex_init(&adev->mman.gtt_window_lock);
1918 /* No others user of address space so set it to 0 */
1919 r = ttm_bo_device_init(&adev->mman.bdev,
1921 adev_to_drm(adev)->anon_inode->i_mapping,
1922 adev_to_drm(adev)->vma_offset_manager,
1923 dma_addressing_limited(adev->dev));
1925 DRM_ERROR("failed initializing buffer object driver(%d).\n", r);
1928 adev->mman.initialized = true;
1930 /* We opt to avoid OOM on system pages allocations */
1931 adev->mman.bdev.no_retry = true;
1933 /* Initialize VRAM pool with all of VRAM divided into pages */
1934 r = amdgpu_vram_mgr_init(adev);
1936 DRM_ERROR("Failed initializing VRAM heap.\n");
1940 /* Reduce size of CPU-visible VRAM if requested */
1941 vis_vram_limit = (u64)amdgpu_vis_vram_limit * 1024 * 1024;
1942 if (amdgpu_vis_vram_limit > 0 &&
1943 vis_vram_limit <= adev->gmc.visible_vram_size)
1944 adev->gmc.visible_vram_size = vis_vram_limit;
1946 /* Change the size here instead of the init above so only lpfn is affected */
1947 amdgpu_ttm_set_buffer_funcs_status(adev, false);
1949 adev->mman.aper_base_kaddr = ioremap_wc(adev->gmc.aper_base,
1950 adev->gmc.visible_vram_size);
1954 *The reserved vram for firmware must be pinned to the specified
1955 *place on the VRAM, so reserve it early.
1957 r = amdgpu_ttm_fw_reserve_vram_init(adev);
1963 * only NAVI10 and onwards ASIC support for IP discovery.
1964 * If IP discovery enabled, a block of memory should be
1965 * reserved for IP discovey.
1967 if (adev->mman.discovery_bin) {
1968 r = amdgpu_ttm_reserve_tmr(adev);
1973 /* allocate memory as required for VGA
1974 * This is used for VGA emulation and pre-OS scanout buffers to
1975 * avoid display artifacts while transitioning between pre-OS
1977 r = amdgpu_bo_create_kernel_at(adev, 0, adev->mman.stolen_vga_size,
1978 AMDGPU_GEM_DOMAIN_VRAM,
1979 &adev->mman.stolen_vga_memory,
1983 r = amdgpu_bo_create_kernel_at(adev, adev->mman.stolen_vga_size,
1984 adev->mman.stolen_extended_size,
1985 AMDGPU_GEM_DOMAIN_VRAM,
1986 &adev->mman.stolen_extended_memory,
1991 DRM_INFO("amdgpu: %uM of VRAM memory ready\n",
1992 (unsigned) (adev->gmc.real_vram_size / (1024 * 1024)));
1994 /* Compute GTT size, either bsaed on 3/4th the size of RAM size
1995 * or whatever the user passed on module init */
1996 if (amdgpu_gtt_size == -1) {
2000 gtt_size = min(max((AMDGPU_DEFAULT_GTT_SIZE_MB << 20),
2001 adev->gmc.mc_vram_size),
2002 ((uint64_t)si.totalram * si.mem_unit * 3/4));
2005 gtt_size = (uint64_t)amdgpu_gtt_size << 20;
2007 /* Initialize GTT memory pool */
2008 r = amdgpu_gtt_mgr_init(adev, gtt_size);
2010 DRM_ERROR("Failed initializing GTT heap.\n");
2013 DRM_INFO("amdgpu: %uM of GTT memory ready.\n",
2014 (unsigned)(gtt_size / (1024 * 1024)));
2016 /* Initialize various on-chip memory pools */
2017 r = amdgpu_ttm_init_on_chip(adev, AMDGPU_PL_GDS, adev->gds.gds_size);
2019 DRM_ERROR("Failed initializing GDS heap.\n");
2023 r = amdgpu_ttm_init_on_chip(adev, AMDGPU_PL_GWS, adev->gds.gws_size);
2025 DRM_ERROR("Failed initializing gws heap.\n");
2029 r = amdgpu_ttm_init_on_chip(adev, AMDGPU_PL_OA, adev->gds.oa_size);
2031 DRM_ERROR("Failed initializing oa heap.\n");
2039 * amdgpu_ttm_late_init - Handle any late initialization for amdgpu_ttm
2041 void amdgpu_ttm_late_init(struct amdgpu_device *adev)
2043 /* return the VGA stolen memory (if any) back to VRAM */
2044 if (!adev->mman.keep_stolen_vga_memory)
2045 amdgpu_bo_free_kernel(&adev->mman.stolen_vga_memory, NULL, NULL);
2046 amdgpu_bo_free_kernel(&adev->mman.stolen_extended_memory, NULL, NULL);
2050 * amdgpu_ttm_fini - De-initialize the TTM memory pools
2052 void amdgpu_ttm_fini(struct amdgpu_device *adev)
2054 if (!adev->mman.initialized)
2057 amdgpu_ttm_training_reserve_vram_fini(adev);
2058 /* return the stolen vga memory back to VRAM */
2059 if (adev->mman.keep_stolen_vga_memory)
2060 amdgpu_bo_free_kernel(&adev->mman.stolen_vga_memory, NULL, NULL);
2061 /* return the IP Discovery TMR memory back to VRAM */
2062 amdgpu_bo_free_kernel(&adev->mman.discovery_memory, NULL, NULL);
2063 amdgpu_ttm_fw_reserve_vram_fini(adev);
2065 if (adev->mman.aper_base_kaddr)
2066 iounmap(adev->mman.aper_base_kaddr);
2067 adev->mman.aper_base_kaddr = NULL;
2069 amdgpu_vram_mgr_fini(adev);
2070 amdgpu_gtt_mgr_fini(adev);
2071 ttm_range_man_fini(&adev->mman.bdev, AMDGPU_PL_GDS);
2072 ttm_range_man_fini(&adev->mman.bdev, AMDGPU_PL_GWS);
2073 ttm_range_man_fini(&adev->mman.bdev, AMDGPU_PL_OA);
2074 ttm_bo_device_release(&adev->mman.bdev);
2075 adev->mman.initialized = false;
2076 DRM_INFO("amdgpu: ttm finalized\n");
2080 * amdgpu_ttm_set_buffer_funcs_status - enable/disable use of buffer functions
2082 * @adev: amdgpu_device pointer
2083 * @enable: true when we can use buffer functions.
2085 * Enable/disable use of buffer functions during suspend/resume. This should
2086 * only be called at bootup or when userspace isn't running.
2088 void amdgpu_ttm_set_buffer_funcs_status(struct amdgpu_device *adev, bool enable)
2090 struct ttm_resource_manager *man = ttm_manager_type(&adev->mman.bdev, TTM_PL_VRAM);
2094 if (!adev->mman.initialized || amdgpu_in_reset(adev) ||
2095 adev->mman.buffer_funcs_enabled == enable)
2099 struct amdgpu_ring *ring;
2100 struct drm_gpu_scheduler *sched;
2102 ring = adev->mman.buffer_funcs_ring;
2103 sched = &ring->sched;
2104 r = drm_sched_entity_init(&adev->mman.entity,
2105 DRM_SCHED_PRIORITY_KERNEL, &sched,
2108 DRM_ERROR("Failed setting up TTM BO move entity (%d)\n",
2113 drm_sched_entity_destroy(&adev->mman.entity);
2114 dma_fence_put(man->move);
2118 /* this just adjusts TTM size idea, which sets lpfn to the correct value */
2120 size = adev->gmc.real_vram_size;
2122 size = adev->gmc.visible_vram_size;
2123 man->size = size >> PAGE_SHIFT;
2124 adev->mman.buffer_funcs_enabled = enable;
2127 static vm_fault_t amdgpu_ttm_fault(struct vm_fault *vmf)
2129 struct ttm_buffer_object *bo = vmf->vma->vm_private_data;
2132 ret = ttm_bo_vm_reserve(bo, vmf);
2136 ret = amdgpu_bo_fault_reserve_notify(bo);
2140 ret = ttm_bo_vm_fault_reserved(vmf, vmf->vma->vm_page_prot,
2141 TTM_BO_VM_NUM_PREFAULT, 1);
2142 if (ret == VM_FAULT_RETRY && !(vmf->flags & FAULT_FLAG_RETRY_NOWAIT))
2146 dma_resv_unlock(bo->base.resv);
2150 static struct vm_operations_struct amdgpu_ttm_vm_ops = {
2151 .fault = amdgpu_ttm_fault,
2152 .open = ttm_bo_vm_open,
2153 .close = ttm_bo_vm_close,
2154 .access = ttm_bo_vm_access
2157 int amdgpu_mmap(struct file *filp, struct vm_area_struct *vma)
2159 struct drm_file *file_priv = filp->private_data;
2160 struct amdgpu_device *adev = drm_to_adev(file_priv->minor->dev);
2163 r = ttm_bo_mmap(filp, vma, &adev->mman.bdev);
2164 if (unlikely(r != 0))
2167 vma->vm_ops = &amdgpu_ttm_vm_ops;
2171 int amdgpu_copy_buffer(struct amdgpu_ring *ring, uint64_t src_offset,
2172 uint64_t dst_offset, uint32_t byte_count,
2173 struct dma_resv *resv,
2174 struct dma_fence **fence, bool direct_submit,
2175 bool vm_needs_flush, bool tmz)
2177 enum amdgpu_ib_pool_type pool = direct_submit ? AMDGPU_IB_POOL_DIRECT :
2178 AMDGPU_IB_POOL_DELAYED;
2179 struct amdgpu_device *adev = ring->adev;
2180 struct amdgpu_job *job;
2183 unsigned num_loops, num_dw;
2187 if (direct_submit && !ring->sched.ready) {
2188 DRM_ERROR("Trying to move memory with ring turned off.\n");
2192 max_bytes = adev->mman.buffer_funcs->copy_max_bytes;
2193 num_loops = DIV_ROUND_UP(byte_count, max_bytes);
2194 num_dw = ALIGN(num_loops * adev->mman.buffer_funcs->copy_num_dw, 8);
2196 r = amdgpu_job_alloc_with_ib(adev, num_dw * 4, pool, &job);
2200 if (vm_needs_flush) {
2201 job->vm_pd_addr = amdgpu_gmc_pd_addr(adev->gart.bo);
2202 job->vm_needs_flush = true;
2205 r = amdgpu_sync_resv(adev, &job->sync, resv,
2207 AMDGPU_FENCE_OWNER_UNDEFINED);
2209 DRM_ERROR("sync failed (%d).\n", r);
2214 for (i = 0; i < num_loops; i++) {
2215 uint32_t cur_size_in_bytes = min(byte_count, max_bytes);
2217 amdgpu_emit_copy_buffer(adev, &job->ibs[0], src_offset,
2218 dst_offset, cur_size_in_bytes, tmz);
2220 src_offset += cur_size_in_bytes;
2221 dst_offset += cur_size_in_bytes;
2222 byte_count -= cur_size_in_bytes;
2225 amdgpu_ring_pad_ib(ring, &job->ibs[0]);
2226 WARN_ON(job->ibs[0].length_dw > num_dw);
2228 r = amdgpu_job_submit_direct(job, ring, fence);
2230 r = amdgpu_job_submit(job, &adev->mman.entity,
2231 AMDGPU_FENCE_OWNER_UNDEFINED, fence);
2238 amdgpu_job_free(job);
2239 DRM_ERROR("Error scheduling IBs (%d)\n", r);
2243 int amdgpu_fill_buffer(struct amdgpu_bo *bo,
2245 struct dma_resv *resv,
2246 struct dma_fence **fence)
2248 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
2249 uint32_t max_bytes = adev->mman.buffer_funcs->fill_max_bytes;
2250 struct amdgpu_ring *ring = adev->mman.buffer_funcs_ring;
2252 struct drm_mm_node *mm_node;
2253 unsigned long num_pages;
2254 unsigned int num_loops, num_dw;
2256 struct amdgpu_job *job;
2259 if (!adev->mman.buffer_funcs_enabled) {
2260 DRM_ERROR("Trying to clear memory with ring turned off.\n");
2264 if (bo->tbo.mem.mem_type == TTM_PL_TT) {
2265 r = amdgpu_ttm_alloc_gart(&bo->tbo);
2270 num_pages = bo->tbo.num_pages;
2271 mm_node = bo->tbo.mem.mm_node;
2274 uint64_t byte_count = mm_node->size << PAGE_SHIFT;
2276 num_loops += DIV_ROUND_UP_ULL(byte_count, max_bytes);
2277 num_pages -= mm_node->size;
2280 num_dw = num_loops * adev->mman.buffer_funcs->fill_num_dw;
2282 /* for IB padding */
2285 r = amdgpu_job_alloc_with_ib(adev, num_dw * 4, AMDGPU_IB_POOL_DELAYED,
2291 r = amdgpu_sync_resv(adev, &job->sync, resv,
2293 AMDGPU_FENCE_OWNER_UNDEFINED);
2295 DRM_ERROR("sync failed (%d).\n", r);
2300 num_pages = bo->tbo.num_pages;
2301 mm_node = bo->tbo.mem.mm_node;
2304 uint64_t byte_count = mm_node->size << PAGE_SHIFT;
2307 dst_addr = amdgpu_mm_node_addr(&bo->tbo, mm_node, &bo->tbo.mem);
2308 while (byte_count) {
2309 uint32_t cur_size_in_bytes = min_t(uint64_t, byte_count,
2312 amdgpu_emit_fill_buffer(adev, &job->ibs[0], src_data,
2313 dst_addr, cur_size_in_bytes);
2315 dst_addr += cur_size_in_bytes;
2316 byte_count -= cur_size_in_bytes;
2319 num_pages -= mm_node->size;
2323 amdgpu_ring_pad_ib(ring, &job->ibs[0]);
2324 WARN_ON(job->ibs[0].length_dw > num_dw);
2325 r = amdgpu_job_submit(job, &adev->mman.entity,
2326 AMDGPU_FENCE_OWNER_UNDEFINED, fence);
2333 amdgpu_job_free(job);
2337 #if defined(CONFIG_DEBUG_FS)
2339 static int amdgpu_mm_dump_table(struct seq_file *m, void *data)
2341 struct drm_info_node *node = (struct drm_info_node *)m->private;
2342 unsigned ttm_pl = (uintptr_t)node->info_ent->data;
2343 struct drm_device *dev = node->minor->dev;
2344 struct amdgpu_device *adev = drm_to_adev(dev);
2345 struct ttm_resource_manager *man = ttm_manager_type(&adev->mman.bdev, ttm_pl);
2346 struct drm_printer p = drm_seq_file_printer(m);
2348 man->func->debug(man, &p);
2352 static const struct drm_info_list amdgpu_ttm_debugfs_list[] = {
2353 {"amdgpu_vram_mm", amdgpu_mm_dump_table, 0, (void *)TTM_PL_VRAM},
2354 {"amdgpu_gtt_mm", amdgpu_mm_dump_table, 0, (void *)TTM_PL_TT},
2355 {"amdgpu_gds_mm", amdgpu_mm_dump_table, 0, (void *)AMDGPU_PL_GDS},
2356 {"amdgpu_gws_mm", amdgpu_mm_dump_table, 0, (void *)AMDGPU_PL_GWS},
2357 {"amdgpu_oa_mm", amdgpu_mm_dump_table, 0, (void *)AMDGPU_PL_OA},
2358 {"ttm_page_pool", ttm_page_alloc_debugfs, 0, NULL},
2359 #ifdef CONFIG_SWIOTLB
2360 {"ttm_dma_page_pool", ttm_dma_page_alloc_debugfs, 0, NULL}
2365 * amdgpu_ttm_vram_read - Linear read access to VRAM
2367 * Accesses VRAM via MMIO for debugging purposes.
2369 static ssize_t amdgpu_ttm_vram_read(struct file *f, char __user *buf,
2370 size_t size, loff_t *pos)
2372 struct amdgpu_device *adev = file_inode(f)->i_private;
2375 if (size & 0x3 || *pos & 0x3)
2378 if (*pos >= adev->gmc.mc_vram_size)
2381 size = min(size, (size_t)(adev->gmc.mc_vram_size - *pos));
2383 size_t bytes = min(size, AMDGPU_TTM_VRAM_MAX_DW_READ * 4);
2384 uint32_t value[AMDGPU_TTM_VRAM_MAX_DW_READ];
2386 amdgpu_device_vram_access(adev, *pos, value, bytes, false);
2387 if (copy_to_user(buf, value, bytes))
2400 * amdgpu_ttm_vram_write - Linear write access to VRAM
2402 * Accesses VRAM via MMIO for debugging purposes.
2404 static ssize_t amdgpu_ttm_vram_write(struct file *f, const char __user *buf,
2405 size_t size, loff_t *pos)
2407 struct amdgpu_device *adev = file_inode(f)->i_private;
2411 if (size & 0x3 || *pos & 0x3)
2414 if (*pos >= adev->gmc.mc_vram_size)
2418 unsigned long flags;
2421 if (*pos >= adev->gmc.mc_vram_size)
2424 r = get_user(value, (uint32_t *)buf);
2428 spin_lock_irqsave(&adev->mmio_idx_lock, flags);
2429 WREG32_NO_KIQ(mmMM_INDEX, ((uint32_t)*pos) | 0x80000000);
2430 WREG32_NO_KIQ(mmMM_INDEX_HI, *pos >> 31);
2431 WREG32_NO_KIQ(mmMM_DATA, value);
2432 spin_unlock_irqrestore(&adev->mmio_idx_lock, flags);
2443 static const struct file_operations amdgpu_ttm_vram_fops = {
2444 .owner = THIS_MODULE,
2445 .read = amdgpu_ttm_vram_read,
2446 .write = amdgpu_ttm_vram_write,
2447 .llseek = default_llseek,
2450 #ifdef CONFIG_DRM_AMDGPU_GART_DEBUGFS
2453 * amdgpu_ttm_gtt_read - Linear read access to GTT memory
2455 static ssize_t amdgpu_ttm_gtt_read(struct file *f, char __user *buf,
2456 size_t size, loff_t *pos)
2458 struct amdgpu_device *adev = file_inode(f)->i_private;
2463 loff_t p = *pos / PAGE_SIZE;
2464 unsigned off = *pos & ~PAGE_MASK;
2465 size_t cur_size = min_t(size_t, size, PAGE_SIZE - off);
2469 if (p >= adev->gart.num_cpu_pages)
2472 page = adev->gart.pages[p];
2477 r = copy_to_user(buf, ptr, cur_size);
2478 kunmap(adev->gart.pages[p]);
2480 r = clear_user(buf, cur_size);
2494 static const struct file_operations amdgpu_ttm_gtt_fops = {
2495 .owner = THIS_MODULE,
2496 .read = amdgpu_ttm_gtt_read,
2497 .llseek = default_llseek
2503 * amdgpu_iomem_read - Virtual read access to GPU mapped memory
2505 * This function is used to read memory that has been mapped to the
2506 * GPU and the known addresses are not physical addresses but instead
2507 * bus addresses (e.g., what you'd put in an IB or ring buffer).
2509 static ssize_t amdgpu_iomem_read(struct file *f, char __user *buf,
2510 size_t size, loff_t *pos)
2512 struct amdgpu_device *adev = file_inode(f)->i_private;
2513 struct iommu_domain *dom;
2517 /* retrieve the IOMMU domain if any for this device */
2518 dom = iommu_get_domain_for_dev(adev->dev);
2521 phys_addr_t addr = *pos & PAGE_MASK;
2522 loff_t off = *pos & ~PAGE_MASK;
2523 size_t bytes = PAGE_SIZE - off;
2528 bytes = bytes < size ? bytes : size;
2530 /* Translate the bus address to a physical address. If
2531 * the domain is NULL it means there is no IOMMU active
2532 * and the address translation is the identity
2534 addr = dom ? iommu_iova_to_phys(dom, addr) : addr;
2536 pfn = addr >> PAGE_SHIFT;
2537 if (!pfn_valid(pfn))
2540 p = pfn_to_page(pfn);
2541 if (p->mapping != adev->mman.bdev.dev_mapping)
2545 r = copy_to_user(buf, ptr + off, bytes);
2559 * amdgpu_iomem_write - Virtual write access to GPU mapped memory
2561 * This function is used to write memory that has been mapped to the
2562 * GPU and the known addresses are not physical addresses but instead
2563 * bus addresses (e.g., what you'd put in an IB or ring buffer).
2565 static ssize_t amdgpu_iomem_write(struct file *f, const char __user *buf,
2566 size_t size, loff_t *pos)
2568 struct amdgpu_device *adev = file_inode(f)->i_private;
2569 struct iommu_domain *dom;
2573 dom = iommu_get_domain_for_dev(adev->dev);
2576 phys_addr_t addr = *pos & PAGE_MASK;
2577 loff_t off = *pos & ~PAGE_MASK;
2578 size_t bytes = PAGE_SIZE - off;
2583 bytes = bytes < size ? bytes : size;
2585 addr = dom ? iommu_iova_to_phys(dom, addr) : addr;
2587 pfn = addr >> PAGE_SHIFT;
2588 if (!pfn_valid(pfn))
2591 p = pfn_to_page(pfn);
2592 if (p->mapping != adev->mman.bdev.dev_mapping)
2596 r = copy_from_user(ptr + off, buf, bytes);
2609 static const struct file_operations amdgpu_ttm_iomem_fops = {
2610 .owner = THIS_MODULE,
2611 .read = amdgpu_iomem_read,
2612 .write = amdgpu_iomem_write,
2613 .llseek = default_llseek
2616 static const struct {
2618 const struct file_operations *fops;
2620 } ttm_debugfs_entries[] = {
2621 { "amdgpu_vram", &amdgpu_ttm_vram_fops, TTM_PL_VRAM },
2622 #ifdef CONFIG_DRM_AMDGPU_GART_DEBUGFS
2623 { "amdgpu_gtt", &amdgpu_ttm_gtt_fops, TTM_PL_TT },
2625 { "amdgpu_iomem", &amdgpu_ttm_iomem_fops, TTM_PL_SYSTEM },
2630 int amdgpu_ttm_debugfs_init(struct amdgpu_device *adev)
2632 #if defined(CONFIG_DEBUG_FS)
2635 struct drm_minor *minor = adev_to_drm(adev)->primary;
2636 struct dentry *ent, *root = minor->debugfs_root;
2638 for (count = 0; count < ARRAY_SIZE(ttm_debugfs_entries); count++) {
2639 ent = debugfs_create_file(
2640 ttm_debugfs_entries[count].name,
2641 S_IFREG | S_IRUGO, root,
2643 ttm_debugfs_entries[count].fops);
2645 return PTR_ERR(ent);
2646 if (ttm_debugfs_entries[count].domain == TTM_PL_VRAM)
2647 i_size_write(ent->d_inode, adev->gmc.mc_vram_size);
2648 else if (ttm_debugfs_entries[count].domain == TTM_PL_TT)
2649 i_size_write(ent->d_inode, adev->gmc.gart_size);
2650 adev->mman.debugfs_entries[count] = ent;
2653 count = ARRAY_SIZE(amdgpu_ttm_debugfs_list);
2655 #ifdef CONFIG_SWIOTLB
2656 if (!(adev->need_swiotlb && swiotlb_nr_tbl()))
2660 return amdgpu_debugfs_add_files(adev, amdgpu_ttm_debugfs_list, count);