drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c

   1 /*
   2  * Copyright 2009 Jerome Glisse.
   3  * All Rights Reserved.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the
   7  * "Software"), to deal in the Software without restriction, including
   8  * without limitation the rights to use, copy, modify, merge, publish,
   9  * distribute, sub license, and/or sell copies of the Software, and to
  10  * permit persons to whom the Software is furnished to do so, subject to
  11  * the following conditions:
  12  *
  13  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  14  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  15  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  16  * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
  17  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  18  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  19  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  20  *
  21  * The above copyright notice and this permission notice (including the
  22  * next paragraph) shall be included in all copies or substantial portions
  23  * of the Software.
  24  *
  25  */
  26 /*
  27  * Authors:
  28  *    Jerome Glisse <glisse@freedesktop.org>
  29  *    Thomas Hellstrom <thomas-at-tungstengraphics-dot-com>
  30  *    Dave Airlie
  31  */
  32
  33 #include <linux/dma-mapping.h>
  34 #include <linux/iommu.h>
  35 #include <linux/hmm.h>
  36 #include <linux/pagemap.h>
  37 #include <linux/sched/task.h>
  38 #include <linux/sched/mm.h>
  39 #include <linux/seq_file.h>
  40 #include <linux/slab.h>
  41 #include <linux/swap.h>
  42 #include <linux/swiotlb.h>
  43 #include <linux/dma-buf.h>
  44 #include <linux/sizes.h>
  45
  46 #include <drm/ttm/ttm_bo_api.h>
  47 #include <drm/ttm/ttm_bo_driver.h>
  48 #include <drm/ttm/ttm_placement.h>
  49 #include <drm/ttm/ttm_module.h>
  50
  51 #include <drm/drm_debugfs.h>
  52 #include <drm/amdgpu_drm.h>
  53
  54 #include "amdgpu.h"
  55 #include "amdgpu_object.h"
  56 #include "amdgpu_trace.h"
  57 #include "amdgpu_amdkfd.h"
  58 #include "amdgpu_sdma.h"
  59 #include "amdgpu_ras.h"
  60 #include "amdgpu_atomfirmware.h"
  61 #include "bif/bif_4_1_d.h"
  62
  63 #define AMDGPU_TTM_VRAM_MAX_DW_READ     (size_t)128
  64
  65 static int amdgpu_ttm_backend_bind(struct ttm_bo_device *bdev,
  66                                    struct ttm_tt *ttm,
  67                                    struct ttm_resource *bo_mem);
  68 static void amdgpu_ttm_backend_unbind(struct ttm_bo_device *bdev,
  69                                       struct ttm_tt *ttm);
  70
  71 static int amdgpu_ttm_init_on_chip(struct amdgpu_device *adev,
  72                                     unsigned int type,
  73                                     uint64_t size_in_page)
  74 {
  75         return ttm_range_man_init(&adev->mman.bdev, type,
  76                                   false, size_in_page);
  77 }
  78
  79 /**
  80  * amdgpu_evict_flags - Compute placement flags
  81  *
  82  * @bo: The buffer object to evict
  83  * @placement: Possible destination(s) for evicted BO
  84  *
  85  * Fill in placement data when ttm_bo_evict() is called
  86  */
  87 static void amdgpu_evict_flags(struct ttm_buffer_object *bo,
  88                                 struct ttm_placement *placement)
  89 {
  90         struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev);
  91         struct amdgpu_bo *abo;
  92         static const struct ttm_place placements = {
  93                 .fpfn = 0,
  94                 .lpfn = 0,
  95                 .mem_type = TTM_PL_SYSTEM,
  96                 .flags = 0
  97         };
  98
  99         /* Don't handle scatter gather BOs */
 100         if (bo->type == ttm_bo_type_sg) {
 101                 placement->num_placement = 0;
 102                 placement->num_busy_placement = 0;
 103                 return;
 104         }
 105
 106         /* Object isn't an AMDGPU object so ignore */
 107         if (!amdgpu_bo_is_amdgpu_bo(bo)) {
 108                 placement->placement = &placements;
 109                 placement->busy_placement = &placements;
 110                 placement->num_placement = 1;
 111                 placement->num_busy_placement = 1;
 112                 return;
 113         }
 114
 115         abo = ttm_to_amdgpu_bo(bo);
 116         switch (bo->mem.mem_type) {
 117         case AMDGPU_PL_GDS:
 118         case AMDGPU_PL_GWS:
 119         case AMDGPU_PL_OA:
 120                 placement->num_placement = 0;
 121                 placement->num_busy_placement = 0;
 122                 return;
 123
 124         case TTM_PL_VRAM:
 125                 if (!adev->mman.buffer_funcs_enabled) {
 126                         /* Move to system memory */
 127                         amdgpu_bo_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_CPU);
 128                 } else if (!amdgpu_gmc_vram_full_visible(&adev->gmc) &&
 129                            !(abo->flags & AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED) &&
 130                            amdgpu_bo_in_cpu_visible_vram(abo)) {
 131
 132                         /* Try evicting to the CPU inaccessible part of VRAM
 133                          * first, but only set GTT as busy placement, so this
 134                          * BO will be evicted to GTT rather than causing other
 135                          * BOs to be evicted from VRAM
 136                          */
 137                         amdgpu_bo_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_VRAM |
 138                                                          AMDGPU_GEM_DOMAIN_GTT);
 139                         abo->placements[0].fpfn = adev->gmc.visible_vram_size >> PAGE_SHIFT;
 140                         abo->placements[0].lpfn = 0;
 141                         abo->placement.busy_placement = &abo->placements[1];
 142                         abo->placement.num_busy_placement = 1;
 143                 } else {
 144                         /* Move to GTT memory */
 145                         amdgpu_bo_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_GTT);
 146                 }
 147                 break;
 148         case TTM_PL_TT:
 149         default:
 150                 amdgpu_bo_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_CPU);
 151                 break;
 152         }
 153         *placement = abo->placement;
 154 }
 155
 156 /**
 157  * amdgpu_verify_access - Verify access for a mmap call
 158  *
 159  * @bo: The buffer object to map
 160  * @filp: The file pointer from the process performing the mmap
 161  *
 162  * This is called by ttm_bo_mmap() to verify whether a process
 163  * has the right to mmap a BO to their process space.
 164  */
 165 static int amdgpu_verify_access(struct ttm_buffer_object *bo, struct file *filp)
 166 {
 167         struct amdgpu_bo *abo = ttm_to_amdgpu_bo(bo);
 168
 169         /*
 170          * Don't verify access for KFD BOs. They don't have a GEM
 171          * object associated with them.
 172          */
 173         if (abo->kfd_bo)
 174                 return 0;
 175
 176         if (amdgpu_ttm_tt_get_usermm(bo->ttm))
 177                 return -EPERM;
 178         return drm_vma_node_verify_access(&abo->tbo.base.vma_node,
 179                                           filp->private_data);
 180 }
 181
 182 /**
 183  * amdgpu_mm_node_addr - Compute the GPU relative offset of a GTT buffer.
 184  *
 185  * @bo: The bo to assign the memory to.
 186  * @mm_node: Memory manager node for drm allocator.
 187  * @mem: The region where the bo resides.
 188  *
 189  */
 190 static uint64_t amdgpu_mm_node_addr(struct ttm_buffer_object *bo,
 191                                     struct drm_mm_node *mm_node,
 192                                     struct ttm_resource *mem)
 193 {
 194         uint64_t addr = 0;
 195
 196         if (mm_node->start != AMDGPU_BO_INVALID_OFFSET) {
 197                 addr = mm_node->start << PAGE_SHIFT;
 198                 addr += amdgpu_ttm_domain_start(amdgpu_ttm_adev(bo->bdev),
 199                                                 mem->mem_type);
 200         }
 201         return addr;
 202 }
 203
 204 /**
 205  * amdgpu_find_mm_node - Helper function finds the drm_mm_node corresponding to
 206  * @offset. It also modifies the offset to be within the drm_mm_node returned
 207  *
 208  * @mem: The region where the bo resides.
 209  * @offset: The offset that drm_mm_node is used for finding.
 210  *
 211  */
 212 static struct drm_mm_node *amdgpu_find_mm_node(struct ttm_resource *mem,
 213                                                uint64_t *offset)
 214 {
 215         struct drm_mm_node *mm_node = mem->mm_node;
 216
 217         while (*offset >= (mm_node->size << PAGE_SHIFT)) {
 218                 *offset -= (mm_node->size << PAGE_SHIFT);
 219                 ++mm_node;
 220         }
 221         return mm_node;
 222 }
 223
 224 /**
 225  * amdgpu_ttm_map_buffer - Map memory into the GART windows
 226  * @bo: buffer object to map
 227  * @mem: memory object to map
 228  * @mm_node: drm_mm node object to map
 229  * @num_pages: number of pages to map
 230  * @offset: offset into @mm_node where to start
 231  * @window: which GART window to use
 232  * @ring: DMA ring to use for the copy
 233  * @tmz: if we should setup a TMZ enabled mapping
 234  * @addr: resulting address inside the MC address space
 235  *
 236  * Setup one of the GART windows to access a specific piece of memory or return
 237  * the physical address for local memory.
 238  */
 239 static int amdgpu_ttm_map_buffer(struct ttm_buffer_object *bo,
 240                                  struct ttm_resource *mem,
 241                                  struct drm_mm_node *mm_node,
 242                                  unsigned num_pages, uint64_t offset,
 243                                  unsigned window, struct amdgpu_ring *ring,
 244                                  bool tmz, uint64_t *addr)
 245 {
 246         struct amdgpu_device *adev = ring->adev;
 247         struct amdgpu_job *job;
 248         unsigned num_dw, num_bytes;
 249         struct dma_fence *fence;
 250         uint64_t src_addr, dst_addr;
 251         void *cpu_addr;
 252         uint64_t flags;
 253         unsigned int i;
 254         int r;
 255
 256         BUG_ON(adev->mman.buffer_funcs->copy_max_bytes <
 257                AMDGPU_GTT_MAX_TRANSFER_SIZE * 8);
 258
 259         /* Map only what can't be accessed directly */
 260         if (!tmz && mem->start != AMDGPU_BO_INVALID_OFFSET) {
 261                 *addr = amdgpu_mm_node_addr(bo, mm_node, mem) + offset;
 262                 return 0;
 263         }
 264
 265         *addr = adev->gmc.gart_start;
 266         *addr += (u64)window * AMDGPU_GTT_MAX_TRANSFER_SIZE *
 267                 AMDGPU_GPU_PAGE_SIZE;
 268         *addr += offset & ~PAGE_MASK;
 269
 270         num_dw = ALIGN(adev->mman.buffer_funcs->copy_num_dw, 8);
 271         num_bytes = num_pages * 8;
 272
 273         r = amdgpu_job_alloc_with_ib(adev, num_dw * 4 + num_bytes,
 274                                      AMDGPU_IB_POOL_DELAYED, &job);
 275         if (r)
 276                 return r;
 277
 278         src_addr = num_dw * 4;
 279         src_addr += job->ibs[0].gpu_addr;
 280
 281         dst_addr = amdgpu_bo_gpu_offset(adev->gart.bo);
 282         dst_addr += window * AMDGPU_GTT_MAX_TRANSFER_SIZE * 8;
 283         amdgpu_emit_copy_buffer(adev, &job->ibs[0], src_addr,
 284                                 dst_addr, num_bytes, false);
 285
 286         amdgpu_ring_pad_ib(ring, &job->ibs[0]);
 287         WARN_ON(job->ibs[0].length_dw > num_dw);
 288
 289         flags = amdgpu_ttm_tt_pte_flags(adev, bo->ttm, mem);
 290         if (tmz)
 291                 flags |= AMDGPU_PTE_TMZ;
 292
 293         cpu_addr = &job->ibs[0].ptr[num_dw];
 294
 295         if (mem->mem_type == TTM_PL_TT) {
 296                 dma_addr_t *dma_address;
 297
 298                 dma_address = &bo->ttm->dma_address[offset >> PAGE_SHIFT];
 299                 r = amdgpu_gart_map(adev, 0, num_pages, dma_address, flags,
 300                                     cpu_addr);
 301                 if (r)
 302                         goto error_free;
 303         } else {
 304                 dma_addr_t dma_address;
 305
 306                 dma_address = (mm_node->start << PAGE_SHIFT) + offset;
 307                 dma_address += adev->vm_manager.vram_base_offset;
 308
 309                 for (i = 0; i < num_pages; ++i) {
 310                         r = amdgpu_gart_map(adev, i << PAGE_SHIFT, 1,
 311                                             &dma_address, flags, cpu_addr);
 312                         if (r)
 313                                 goto error_free;
 314
 315                         dma_address += PAGE_SIZE;
 316                 }
 317         }
 318
 319         r = amdgpu_job_submit(job, &adev->mman.entity,
 320                               AMDGPU_FENCE_OWNER_UNDEFINED, &fence);
 321         if (r)
 322                 goto error_free;
 323
 324         dma_fence_put(fence);
 325
 326         return r;
 327
 328 error_free:
 329         amdgpu_job_free(job);
 330         return r;
 331 }
 332
 333 /**
 334  * amdgpu_copy_ttm_mem_to_mem - Helper function for copy
 335  * @adev: amdgpu device
 336  * @src: buffer/address where to read from
 337  * @dst: buffer/address where to write to
 338  * @size: number of bytes to copy
 339  * @tmz: if a secure copy should be used
 340  * @resv: resv object to sync to
 341  * @f: Returns the last fence if multiple jobs are submitted.
 342  *
 343  * The function copies @size bytes from {src->mem + src->offset} to
 344  * {dst->mem + dst->offset}. src->bo and dst->bo could be same BO for a
 345  * move and different for a BO to BO copy.
 346  *
 347  */
 348 int amdgpu_ttm_copy_mem_to_mem(struct amdgpu_device *adev,
 349                                const struct amdgpu_copy_mem *src,
 350                                const struct amdgpu_copy_mem *dst,
 351                                uint64_t size, bool tmz,
 352                                struct dma_resv *resv,
 353                                struct dma_fence **f)
 354 {
 355         const uint32_t GTT_MAX_BYTES = (AMDGPU_GTT_MAX_TRANSFER_SIZE *
 356                                         AMDGPU_GPU_PAGE_SIZE);
 357
 358         uint64_t src_node_size, dst_node_size, src_offset, dst_offset;
 359         struct amdgpu_ring *ring = adev->mman.buffer_funcs_ring;
 360         struct drm_mm_node *src_mm, *dst_mm;
 361         struct dma_fence *fence = NULL;
 362         int r = 0;
 363
 364         if (!adev->mman.buffer_funcs_enabled) {
 365                 DRM_ERROR("Trying to move memory with ring turned off.\n");
 366                 return -EINVAL;
 367         }
 368
 369         src_offset = src->offset;
 370         if (src->mem->mm_node) {
 371                 src_mm = amdgpu_find_mm_node(src->mem, &src_offset);
 372                 src_node_size = (src_mm->size << PAGE_SHIFT) - src_offset;
 373         } else {
 374                 src_mm = NULL;
 375                 src_node_size = ULLONG_MAX;
 376         }
 377
 378         dst_offset = dst->offset;
 379         if (dst->mem->mm_node) {
 380                 dst_mm = amdgpu_find_mm_node(dst->mem, &dst_offset);
 381                 dst_node_size = (dst_mm->size << PAGE_SHIFT) - dst_offset;
 382         } else {
 383                 dst_mm = NULL;
 384                 dst_node_size = ULLONG_MAX;
 385         }
 386
 387         mutex_lock(&adev->mman.gtt_window_lock);
 388
 389         while (size) {
 390                 uint32_t src_page_offset = src_offset & ~PAGE_MASK;
 391                 uint32_t dst_page_offset = dst_offset & ~PAGE_MASK;
 392                 struct dma_fence *next;
 393                 uint32_t cur_size;
 394                 uint64_t from, to;
 395
 396                 /* Copy size cannot exceed GTT_MAX_BYTES. So if src or dst
 397                  * begins at an offset, then adjust the size accordingly
 398                  */
 399                 cur_size = max(src_page_offset, dst_page_offset);
 400                 cur_size = min(min3(src_node_size, dst_node_size, size),
 401                                (uint64_t)(GTT_MAX_BYTES - cur_size));
 402
 403                 /* Map src to window 0 and dst to window 1. */
 404                 r = amdgpu_ttm_map_buffer(src->bo, src->mem, src_mm,
 405                                           PFN_UP(cur_size + src_page_offset),
 406                                           src_offset, 0, ring, tmz, &from);
 407                 if (r)
 408                         goto error;
 409
 410                 r = amdgpu_ttm_map_buffer(dst->bo, dst->mem, dst_mm,
 411                                           PFN_UP(cur_size + dst_page_offset),
 412                                           dst_offset, 1, ring, tmz, &to);
 413                 if (r)
 414                         goto error;
 415
 416                 r = amdgpu_copy_buffer(ring, from, to, cur_size,
 417                                        resv, &next, false, true, tmz);
 418                 if (r)
 419                         goto error;
 420
 421                 dma_fence_put(fence);
 422                 fence = next;
 423
 424                 size -= cur_size;
 425                 if (!size)
 426                         break;
 427
 428                 src_node_size -= cur_size;
 429                 if (!src_node_size) {
 430                         ++src_mm;
 431                         src_node_size = src_mm->size << PAGE_SHIFT;
 432                         src_offset = 0;
 433                 } else {
 434                         src_offset += cur_size;
 435                 }
 436
 437                 dst_node_size -= cur_size;
 438                 if (!dst_node_size) {
 439                         ++dst_mm;
 440                         dst_node_size = dst_mm->size << PAGE_SHIFT;
 441                         dst_offset = 0;
 442                 } else {
 443                         dst_offset += cur_size;
 444                 }
 445         }
 446 error:
 447         mutex_unlock(&adev->mman.gtt_window_lock);
 448         if (f)
 449                 *f = dma_fence_get(fence);
 450         dma_fence_put(fence);
 451         return r;
 452 }
 453
 454 /**
 455  * amdgpu_move_blit - Copy an entire buffer to another buffer
 456  *
 457  * This is a helper called by amdgpu_bo_move() and amdgpu_move_vram_ram() to
 458  * help move buffers to and from VRAM.
 459  */
 460 static int amdgpu_move_blit(struct ttm_buffer_object *bo,
 461                             bool evict,
 462                             struct ttm_resource *new_mem,
 463                             struct ttm_resource *old_mem)
 464 {
 465         struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev);
 466         struct amdgpu_bo *abo = ttm_to_amdgpu_bo(bo);
 467         struct amdgpu_copy_mem src, dst;
 468         struct dma_fence *fence = NULL;
 469         int r;
 470
 471         src.bo = bo;
 472         dst.bo = bo;
 473         src.mem = old_mem;
 474         dst.mem = new_mem;
 475         src.offset = 0;
 476         dst.offset = 0;
 477
 478         r = amdgpu_ttm_copy_mem_to_mem(adev, &src, &dst,
 479                                        new_mem->num_pages << PAGE_SHIFT,
 480                                        amdgpu_bo_encrypted(abo),
 481                                        bo->base.resv, &fence);
 482         if (r)
 483                 goto error;
 484
 485         /* clear the space being freed */
 486         if (old_mem->mem_type == TTM_PL_VRAM &&
 487             (abo->flags & AMDGPU_GEM_CREATE_VRAM_WIPE_ON_RELEASE)) {
 488                 struct dma_fence *wipe_fence = NULL;
 489
 490                 r = amdgpu_fill_buffer(ttm_to_amdgpu_bo(bo), AMDGPU_POISON,
 491                                        NULL, &wipe_fence);
 492                 if (r) {
 493                         goto error;
 494                 } else if (wipe_fence) {
 495                         dma_fence_put(fence);
 496                         fence = wipe_fence;
 497                 }
 498         }
 499
 500         /* Always block for VM page tables before committing the new location */
 501         if (bo->type == ttm_bo_type_kernel)
 502                 r = ttm_bo_move_accel_cleanup(bo, fence, true, false, new_mem);
 503         else
 504                 r = ttm_bo_move_accel_cleanup(bo, fence, evict, true, new_mem);
 505         dma_fence_put(fence);
 506         return r;
 507
 508 error:
 509         if (fence)
 510                 dma_fence_wait(fence, false);
 511         dma_fence_put(fence);
 512         return r;
 513 }
 514
 515 /**
 516  * amdgpu_mem_visible - Check that memory can be accessed by ttm_bo_move_memcpy
 517  *
 518  * Called by amdgpu_bo_move()
 519  */
 520 static bool amdgpu_mem_visible(struct amdgpu_device *adev,
 521                                struct ttm_resource *mem)
 522 {
 523         struct drm_mm_node *nodes = mem->mm_node;
 524
 525         if (mem->mem_type == TTM_PL_SYSTEM ||
 526             mem->mem_type == TTM_PL_TT)
 527                 return true;
 528         if (mem->mem_type != TTM_PL_VRAM)
 529                 return false;
 530
 531         /* ttm_resource_ioremap only supports contiguous memory */
 532         if (nodes->size != mem->num_pages)
 533                 return false;
 534
 535         return ((nodes->start + nodes->size) << PAGE_SHIFT)
 536                 <= adev->gmc.visible_vram_size;
 537 }
 538
 539 /**
 540  * amdgpu_bo_move - Move a buffer object to a new memory location
 541  *
 542  * Called by ttm_bo_handle_move_mem()
 543  */
 544 static int amdgpu_bo_move(struct ttm_buffer_object *bo, bool evict,
 545                           struct ttm_operation_ctx *ctx,
 546                           struct ttm_resource *new_mem,
 547                           struct ttm_place *hop)
 548 {
 549         struct amdgpu_device *adev;
 550         struct amdgpu_bo *abo;
 551         struct ttm_resource *old_mem = &bo->mem;
 552         int r;
 553
 554         if (new_mem->mem_type == TTM_PL_TT) {
 555                 r = amdgpu_ttm_backend_bind(bo->bdev, bo->ttm, new_mem);
 556                 if (r)
 557                         return r;
 558         }
 559
 560         /* Can't move a pinned BO */
 561         abo = ttm_to_amdgpu_bo(bo);
 562         if (WARN_ON_ONCE(abo->tbo.pin_count > 0))
 563                 return -EINVAL;
 564
 565         adev = amdgpu_ttm_adev(bo->bdev);
 566
 567         if (old_mem->mem_type == TTM_PL_SYSTEM && bo->ttm == NULL) {
 568                 ttm_bo_move_null(bo, new_mem);
 569                 goto out;
 570         }
 571         if (old_mem->mem_type == TTM_PL_SYSTEM &&
 572             new_mem->mem_type == TTM_PL_TT) {
 573                 ttm_bo_move_null(bo, new_mem);
 574                 goto out;
 575         }
 576         if (old_mem->mem_type == TTM_PL_TT &&
 577             new_mem->mem_type == TTM_PL_SYSTEM) {
 578                 r = ttm_bo_wait_ctx(bo, ctx);
 579                 if (r)
 580                         return r;
 581
 582                 amdgpu_ttm_backend_unbind(bo->bdev, bo->ttm);
 583                 ttm_resource_free(bo, &bo->mem);
 584                 ttm_bo_assign_mem(bo, new_mem);
 585                 goto out;
 586         }
 587
 588         if (old_mem->mem_type == AMDGPU_PL_GDS ||
 589             old_mem->mem_type == AMDGPU_PL_GWS ||
 590             old_mem->mem_type == AMDGPU_PL_OA ||
 591             new_mem->mem_type == AMDGPU_PL_GDS ||
 592             new_mem->mem_type == AMDGPU_PL_GWS ||
 593             new_mem->mem_type == AMDGPU_PL_OA) {
 594                 /* Nothing to save here */
 595                 ttm_bo_move_null(bo, new_mem);
 596                 goto out;
 597         }
 598
 599         if (adev->mman.buffer_funcs_enabled) {
 600                 if (((old_mem->mem_type == TTM_PL_SYSTEM &&
 601                       new_mem->mem_type == TTM_PL_VRAM) ||
 602                      (old_mem->mem_type == TTM_PL_VRAM &&
 603                       new_mem->mem_type == TTM_PL_SYSTEM))) {
 604                         hop->fpfn = 0;
 605                         hop->lpfn = 0;
 606                         hop->mem_type = TTM_PL_TT;
 607                         hop->flags = 0;
 608                         return -EMULTIHOP;
 609                 }
 610
 611                 r = amdgpu_move_blit(bo, evict, new_mem, old_mem);
 612         } else {
 613                 r = -ENODEV;
 614         }
 615
 616         if (r) {
 617                 /* Check that all memory is CPU accessible */
 618                 if (!amdgpu_mem_visible(adev, old_mem) ||
 619                     !amdgpu_mem_visible(adev, new_mem)) {
 620                         pr_err("Move buffer fallback to memcpy unavailable\n");
 621                         return r;
 622                 }
 623
 624                 r = ttm_bo_move_memcpy(bo, ctx, new_mem);
 625                 if (r)
 626                         return r;
 627         }
 628
 629         if (bo->type == ttm_bo_type_device &&
 630             new_mem->mem_type == TTM_PL_VRAM &&
 631             old_mem->mem_type != TTM_PL_VRAM) {
 632                 /* amdgpu_bo_fault_reserve_notify will re-set this if the CPU
 633                  * accesses the BO after it's moved.
 634                  */
 635                 abo->flags &= ~AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED;
 636         }
 637
 638 out:
 639         /* update statistics */
 640         atomic64_add((u64)bo->num_pages << PAGE_SHIFT, &adev->num_bytes_moved);
 641         amdgpu_bo_move_notify(bo, evict, new_mem);
 642         return 0;
 643 }
 644
 645 /**
 646  * amdgpu_ttm_io_mem_reserve - Reserve a block of memory during a fault
 647  *
 648  * Called by ttm_mem_io_reserve() ultimately via ttm_bo_vm_fault()
 649  */
 650 static int amdgpu_ttm_io_mem_reserve(struct ttm_bo_device *bdev, struct ttm_resource *mem)
 651 {
 652         struct amdgpu_device *adev = amdgpu_ttm_adev(bdev);
 653         struct drm_mm_node *mm_node = mem->mm_node;
 654         size_t bus_size = (size_t)mem->num_pages << PAGE_SHIFT;
 655
 656         switch (mem->mem_type) {
 657         case TTM_PL_SYSTEM:
 658                 /* system memory */
 659                 return 0;
 660         case TTM_PL_TT:
 661                 break;
 662         case TTM_PL_VRAM:
 663                 mem->bus.offset = mem->start << PAGE_SHIFT;
 664                 /* check if it's visible */
 665                 if ((mem->bus.offset + bus_size) > adev->gmc.visible_vram_size)
 666                         return -EINVAL;
 667                 /* Only physically contiguous buffers apply. In a contiguous
 668                  * buffer, size of the first mm_node would match the number of
 669                  * pages in ttm_resource.
 670                  */
 671                 if (adev->mman.aper_base_kaddr &&
 672                     (mm_node->size == mem->num_pages))
 673                         mem->bus.addr = (u8 *)adev->mman.aper_base_kaddr +
 674                                         mem->bus.offset;
 675
 676                 mem->bus.offset += adev->gmc.aper_base;
 677                 mem->bus.is_iomem = true;
 678                 mem->bus.caching = ttm_write_combined;
 679                 break;
 680         default:
 681                 return -EINVAL;
 682         }
 683         return 0;
 684 }
 685
 686 static unsigned long amdgpu_ttm_io_mem_pfn(struct ttm_buffer_object *bo,
 687                                            unsigned long page_offset)
 688 {
 689         struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev);
 690         uint64_t offset = (page_offset << PAGE_SHIFT);
 691         struct drm_mm_node *mm;
 692
 693         mm = amdgpu_find_mm_node(&bo->mem, &offset);
 694         offset += adev->gmc.aper_base;
 695         return mm->start + (offset >> PAGE_SHIFT);
 696 }
 697
 698 /**
 699  * amdgpu_ttm_domain_start - Returns GPU start address
 700  * @adev: amdgpu device object
 701  * @type: type of the memory
 702  *
 703  * Returns:
 704  * GPU start address of a memory domain
 705  */
 706
 707 uint64_t amdgpu_ttm_domain_start(struct amdgpu_device *adev, uint32_t type)
 708 {
 709         switch (type) {
 710         case TTM_PL_TT:
 711                 return adev->gmc.gart_start;
 712         case TTM_PL_VRAM:
 713                 return adev->gmc.vram_start;
 714         }
 715
 716         return 0;
 717 }
 718
 719 /*
 720  * TTM backend functions.
 721  */
 722 struct amdgpu_ttm_tt {
 723         struct ttm_tt   ttm;
 724         struct drm_gem_object   *gobj;
 725         u64                     offset;
 726         uint64_t                userptr;
 727         struct task_struct      *usertask;
 728         uint32_t                userflags;
 729         bool                    bound;
 730 #if IS_ENABLED(CONFIG_DRM_AMDGPU_USERPTR)
 731         struct hmm_range        *range;
 732 #endif
 733 };
 734
 735 #ifdef CONFIG_DRM_AMDGPU_USERPTR
 736 /**
 737  * amdgpu_ttm_tt_get_user_pages - get device accessible pages that back user
 738  * memory and start HMM tracking CPU page table update
 739  *
 740  * Calling function must call amdgpu_ttm_tt_userptr_range_done() once and only
 741  * once afterwards to stop HMM tracking
 742  */
 743 int amdgpu_ttm_tt_get_user_pages(struct amdgpu_bo *bo, struct page **pages)
 744 {
 745         struct ttm_tt *ttm = bo->tbo.ttm;
 746         struct amdgpu_ttm_tt *gtt = (void *)ttm;
 747         unsigned long start = gtt->userptr;
 748         struct vm_area_struct *vma;
 749         struct hmm_range *range;
 750         unsigned long timeout;
 751         struct mm_struct *mm;
 752         unsigned long i;
 753         int r = 0;
 754
 755         mm = bo->notifier.mm;
 756         if (unlikely(!mm)) {
 757                 DRM_DEBUG_DRIVER("BO is not registered?\n");
 758                 return -EFAULT;
 759         }
 760
 761         /* Another get_user_pages is running at the same time?? */
 762         if (WARN_ON(gtt->range))
 763                 return -EFAULT;
 764
 765         if (!mmget_not_zero(mm)) /* Happens during process shutdown */
 766                 return -ESRCH;
 767
 768         range = kzalloc(sizeof(*range), GFP_KERNEL);
 769         if (unlikely(!range)) {
 770                 r = -ENOMEM;
 771                 goto out;
 772         }
 773         range->notifier = &bo->notifier;
 774         range->start = bo->notifier.interval_tree.start;
 775         range->end = bo->notifier.interval_tree.last + 1;
 776         range->default_flags = HMM_PFN_REQ_FAULT;
 777         if (!amdgpu_ttm_tt_is_readonly(ttm))
 778                 range->default_flags |= HMM_PFN_REQ_WRITE;
 779
 780         range->hmm_pfns = kvmalloc_array(ttm->num_pages,
 781                                          sizeof(*range->hmm_pfns), GFP_KERNEL);
 782         if (unlikely(!range->hmm_pfns)) {
 783                 r = -ENOMEM;
 784                 goto out_free_ranges;
 785         }
 786
 787         mmap_read_lock(mm);
 788         vma = find_vma(mm, start);
 789         if (unlikely(!vma || start < vma->vm_start)) {
 790                 r = -EFAULT;
 791                 goto out_unlock;
 792         }
 793         if (unlikely((gtt->userflags & AMDGPU_GEM_USERPTR_ANONONLY) &&
 794                 vma->vm_file)) {
 795                 r = -EPERM;
 796                 goto out_unlock;
 797         }
 798         mmap_read_unlock(mm);
 799         timeout = jiffies + msecs_to_jiffies(HMM_RANGE_DEFAULT_TIMEOUT);
 800
 801 retry:
 802         range->notifier_seq = mmu_interval_read_begin(&bo->notifier);
 803
 804         mmap_read_lock(mm);
 805         r = hmm_range_fault(range);
 806         mmap_read_unlock(mm);
 807         if (unlikely(r)) {
 808                 /*
 809                  * FIXME: This timeout should encompass the retry from
 810                  * mmu_interval_read_retry() as well.
 811                  */
 812                 if (r == -EBUSY && !time_after(jiffies, timeout))
 813                         goto retry;
 814                 goto out_free_pfns;
 815         }
 816
 817         /*
 818          * Due to default_flags, all pages are HMM_PFN_VALID or
 819          * hmm_range_fault() fails. FIXME: The pages cannot be touched outside
 820          * the notifier_lock, and mmu_interval_read_retry() must be done first.
 821          */
 822         for (i = 0; i < ttm->num_pages; i++)
 823                 pages[i] = hmm_pfn_to_page(range->hmm_pfns[i]);
 824
 825         gtt->range = range;
 826         mmput(mm);
 827
 828         return 0;
 829
 830 out_unlock:
 831         mmap_read_unlock(mm);
 832 out_free_pfns:
 833         kvfree(range->hmm_pfns);
 834 out_free_ranges:
 835         kfree(range);
 836 out:
 837         mmput(mm);
 838         return r;
 839 }
 840
 841 /**
 842  * amdgpu_ttm_tt_userptr_range_done - stop HMM track the CPU page table change
 843  * Check if the pages backing this ttm range have been invalidated
 844  *
 845  * Returns: true if pages are still valid
 846  */
 847 bool amdgpu_ttm_tt_get_user_pages_done(struct ttm_tt *ttm)
 848 {
 849         struct amdgpu_ttm_tt *gtt = (void *)ttm;
 850         bool r = false;
 851
 852         if (!gtt || !gtt->userptr)
 853                 return false;
 854
 855         DRM_DEBUG_DRIVER("user_pages_done 0x%llx pages 0x%x\n",
 856                 gtt->userptr, ttm->num_pages);
 857
 858         WARN_ONCE(!gtt->range || !gtt->range->hmm_pfns,
 859                 "No user pages to check\n");
 860
 861         if (gtt->range) {
 862                 /*
 863                  * FIXME: Must always hold notifier_lock for this, and must
 864                  * not ignore the return code.
 865                  */
 866                 r = mmu_interval_read_retry(gtt->range->notifier,
 867                                          gtt->range->notifier_seq);
 868                 kvfree(gtt->range->hmm_pfns);
 869                 kfree(gtt->range);
 870                 gtt->range = NULL;
 871         }
 872
 873         return !r;
 874 }
 875 #endif
 876
 877 /**
 878  * amdgpu_ttm_tt_set_user_pages - Copy pages in, putting old pages as necessary.
 879  *
 880  * Called by amdgpu_cs_list_validate(). This creates the page list
 881  * that backs user memory and will ultimately be mapped into the device
 882  * address space.
 883  */
 884 void amdgpu_ttm_tt_set_user_pages(struct ttm_tt *ttm, struct page **pages)
 885 {
 886         unsigned long i;
 887
 888         for (i = 0; i < ttm->num_pages; ++i)
 889                 ttm->pages[i] = pages ? pages[i] : NULL;
 890 }
 891
 892 /**
 893  * amdgpu_ttm_tt_pin_userptr - prepare the sg table with the user pages
 894  *
 895  * Called by amdgpu_ttm_backend_bind()
 896  **/
 897 static int amdgpu_ttm_tt_pin_userptr(struct ttm_bo_device *bdev,
 898                                      struct ttm_tt *ttm)
 899 {
 900         struct amdgpu_device *adev = amdgpu_ttm_adev(bdev);
 901         struct amdgpu_ttm_tt *gtt = (void *)ttm;
 902         int r;
 903
 904         int write = !(gtt->userflags & AMDGPU_GEM_USERPTR_READONLY);
 905         enum dma_data_direction direction = write ?
 906                 DMA_BIDIRECTIONAL : DMA_TO_DEVICE;
 907
 908         /* Allocate an SG array and squash pages into it */
 909         r = sg_alloc_table_from_pages(ttm->sg, ttm->pages, ttm->num_pages, 0,
 910                                       ttm->num_pages << PAGE_SHIFT,
 911                                       GFP_KERNEL);
 912         if (r)
 913                 goto release_sg;
 914
 915         /* Map SG to device */
 916         r = dma_map_sgtable(adev->dev, ttm->sg, direction, 0);
 917         if (r)
 918                 goto release_sg;
 919
 920         /* convert SG to linear array of pages and dma addresses */
 921         drm_prime_sg_to_page_addr_arrays(ttm->sg, ttm->pages,
 922                                          gtt->ttm.dma_address, ttm->num_pages);
 923
 924         return 0;
 925
 926 release_sg:
 927         kfree(ttm->sg);
 928         ttm->sg = NULL;
 929         return r;
 930 }
 931
 932 /**
 933  * amdgpu_ttm_tt_unpin_userptr - Unpin and unmap userptr pages
 934  */
 935 static void amdgpu_ttm_tt_unpin_userptr(struct ttm_bo_device *bdev,
 936                                         struct ttm_tt *ttm)
 937 {
 938         struct amdgpu_device *adev = amdgpu_ttm_adev(bdev);
 939         struct amdgpu_ttm_tt *gtt = (void *)ttm;
 940
 941         int write = !(gtt->userflags & AMDGPU_GEM_USERPTR_READONLY);
 942         enum dma_data_direction direction = write ?
 943                 DMA_BIDIRECTIONAL : DMA_TO_DEVICE;
 944
 945         /* double check that we don't free the table twice */
 946         if (!ttm->sg->sgl)
 947                 return;
 948
 949         /* unmap the pages mapped to the device */
 950         dma_unmap_sgtable(adev->dev, ttm->sg, direction, 0);
 951         sg_free_table(ttm->sg);
 952
 953 #if IS_ENABLED(CONFIG_DRM_AMDGPU_USERPTR)
 954         if (gtt->range) {
 955                 unsigned long i;
 956
 957                 for (i = 0; i < ttm->num_pages; i++) {
 958                         if (ttm->pages[i] !=
 959                             hmm_pfn_to_page(gtt->range->hmm_pfns[i]))
 960                                 break;
 961                 }
 962
 963                 WARN((i == ttm->num_pages), "Missing get_user_page_done\n");
 964         }
 965 #endif
 966 }
 967
 968 static int amdgpu_ttm_gart_bind(struct amdgpu_device *adev,
 969                                 struct ttm_buffer_object *tbo,
 970                                 uint64_t flags)
 971 {
 972         struct amdgpu_bo *abo = ttm_to_amdgpu_bo(tbo);
 973         struct ttm_tt *ttm = tbo->ttm;
 974         struct amdgpu_ttm_tt *gtt = (void *)ttm;
 975         int r;
 976
 977         if (amdgpu_bo_encrypted(abo))
 978                 flags |= AMDGPU_PTE_TMZ;
 979
 980         if (abo->flags & AMDGPU_GEM_CREATE_CP_MQD_GFX9) {
 981                 uint64_t page_idx = 1;
 982
 983                 r = amdgpu_gart_bind(adev, gtt->offset, page_idx,
 984                                 ttm->pages, gtt->ttm.dma_address, flags);
 985                 if (r)
 986                         goto gart_bind_fail;
 987
 988                 /* The memory type of the first page defaults to UC. Now
 989                  * modify the memory type to NC from the second page of
 990                  * the BO onward.
 991                  */
 992                 flags &= ~AMDGPU_PTE_MTYPE_VG10_MASK;
 993                 flags |= AMDGPU_PTE_MTYPE_VG10(AMDGPU_MTYPE_NC);
 994
 995                 r = amdgpu_gart_bind(adev,
 996                                 gtt->offset + (page_idx << PAGE_SHIFT),
 997                                 ttm->num_pages - page_idx,
 998                                 &ttm->pages[page_idx],
 999                                 &(gtt->ttm.dma_address[page_idx]), flags);
1000         } else {
1001                 r = amdgpu_gart_bind(adev, gtt->offset, ttm->num_pages,
1002                                      ttm->pages, gtt->ttm.dma_address, flags);
1003         }
1004
1005 gart_bind_fail:
1006         if (r)
1007                 DRM_ERROR("failed to bind %u pages at 0x%08llX\n",
1008                           ttm->num_pages, gtt->offset);
1009
1010         return r;
1011 }
1012
1013 /**
1014  * amdgpu_ttm_backend_bind - Bind GTT memory
1015  *
1016  * Called by ttm_tt_bind() on behalf of ttm_bo_handle_move_mem().
1017  * This handles binding GTT memory to the device address space.
1018  */
1019 static int amdgpu_ttm_backend_bind(struct ttm_bo_device *bdev,
1020                                    struct ttm_tt *ttm,
1021                                    struct ttm_resource *bo_mem)
1022 {
1023         struct amdgpu_device *adev = amdgpu_ttm_adev(bdev);
1024         struct amdgpu_ttm_tt *gtt = (void*)ttm;
1025         uint64_t flags;
1026         int r = 0;
1027
1028         if (!bo_mem)
1029                 return -EINVAL;
1030
1031         if (gtt->bound)
1032                 return 0;
1033
1034         if (gtt->userptr) {
1035                 r = amdgpu_ttm_tt_pin_userptr(bdev, ttm);
1036                 if (r) {
1037                         DRM_ERROR("failed to pin userptr\n");
1038                         return r;
1039                 }
1040         }
1041         if (!ttm->num_pages) {
1042                 WARN(1, "nothing to bind %u pages for mreg %p back %p!\n",
1043                      ttm->num_pages, bo_mem, ttm);
1044         }
1045
1046         if (bo_mem->mem_type == AMDGPU_PL_GDS ||
1047             bo_mem->mem_type == AMDGPU_PL_GWS ||
1048             bo_mem->mem_type == AMDGPU_PL_OA)
1049                 return -EINVAL;
1050
1051         if (!amdgpu_gtt_mgr_has_gart_addr(bo_mem)) {
1052                 gtt->offset = AMDGPU_BO_INVALID_OFFSET;
1053                 return 0;
1054         }
1055
1056         /* compute PTE flags relevant to this BO memory */
1057         flags = amdgpu_ttm_tt_pte_flags(adev, ttm, bo_mem);
1058
1059         /* bind pages into GART page tables */
1060         gtt->offset = (u64)bo_mem->start << PAGE_SHIFT;
1061         r = amdgpu_gart_bind(adev, gtt->offset, ttm->num_pages,
1062                 ttm->pages, gtt->ttm.dma_address, flags);
1063
1064         if (r)
1065                 DRM_ERROR("failed to bind %u pages at 0x%08llX\n",
1066                           ttm->num_pages, gtt->offset);
1067         gtt->bound = true;
1068         return r;
1069 }
1070
1071 /**
1072  * amdgpu_ttm_alloc_gart - Make sure buffer object is accessible either
1073  * through AGP or GART aperture.
1074  *
1075  * If bo is accessible through AGP aperture, then use AGP aperture
1076  * to access bo; otherwise allocate logical space in GART aperture
1077  * and map bo to GART aperture.
1078  */
1079 int amdgpu_ttm_alloc_gart(struct ttm_buffer_object *bo)
1080 {
1081         struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev);
1082         struct ttm_operation_ctx ctx = { false, false };
1083         struct amdgpu_ttm_tt *gtt = (void *)bo->ttm;
1084         struct ttm_resource tmp;
1085         struct ttm_placement placement;
1086         struct ttm_place placements;
1087         uint64_t addr, flags;
1088         int r;
1089
1090         if (bo->mem.start != AMDGPU_BO_INVALID_OFFSET)
1091                 return 0;
1092
1093         addr = amdgpu_gmc_agp_addr(bo);
1094         if (addr != AMDGPU_BO_INVALID_OFFSET) {
1095                 bo->mem.start = addr >> PAGE_SHIFT;
1096         } else {
1097
1098                 /* allocate GART space */
1099                 tmp = bo->mem;
1100                 tmp.mm_node = NULL;
1101                 placement.num_placement = 1;
1102                 placement.placement = &placements;
1103                 placement.num_busy_placement = 1;
1104                 placement.busy_placement = &placements;
1105                 placements.fpfn = 0;
1106                 placements.lpfn = adev->gmc.gart_size >> PAGE_SHIFT;
1107                 placements.mem_type = TTM_PL_TT;
1108                 placements.flags = bo->mem.placement;
1109
1110                 r = ttm_bo_mem_space(bo, &placement, &tmp, &ctx);
1111                 if (unlikely(r))
1112                         return r;
1113
1114                 /* compute PTE flags for this buffer object */
1115                 flags = amdgpu_ttm_tt_pte_flags(adev, bo->ttm, &tmp);
1116
1117                 /* Bind pages */
1118                 gtt->offset = (u64)tmp.start << PAGE_SHIFT;
1119                 r = amdgpu_ttm_gart_bind(adev, bo, flags);
1120                 if (unlikely(r)) {
1121                         ttm_resource_free(bo, &tmp);
1122                         return r;
1123                 }
1124
1125                 ttm_resource_free(bo, &bo->mem);
1126                 bo->mem = tmp;
1127         }
1128
1129         return 0;
1130 }
1131
1132 /**
1133  * amdgpu_ttm_recover_gart - Rebind GTT pages
1134  *
1135  * Called by amdgpu_gtt_mgr_recover() from amdgpu_device_reset() to
1136  * rebind GTT pages during a GPU reset.
1137  */
1138 int amdgpu_ttm_recover_gart(struct ttm_buffer_object *tbo)
1139 {
1140         struct amdgpu_device *adev = amdgpu_ttm_adev(tbo->bdev);
1141         uint64_t flags;
1142         int r;
1143
1144         if (!tbo->ttm)
1145                 return 0;
1146
1147         flags = amdgpu_ttm_tt_pte_flags(adev, tbo->ttm, &tbo->mem);
1148         r = amdgpu_ttm_gart_bind(adev, tbo, flags);
1149
1150         return r;
1151 }
1152
1153 /**
1154  * amdgpu_ttm_backend_unbind - Unbind GTT mapped pages
1155  *
1156  * Called by ttm_tt_unbind() on behalf of ttm_bo_move_ttm() and
1157  * ttm_tt_destroy().
1158  */
1159 static void amdgpu_ttm_backend_unbind(struct ttm_bo_device *bdev,
1160                                       struct ttm_tt *ttm)
1161 {
1162         struct amdgpu_device *adev = amdgpu_ttm_adev(bdev);
1163         struct amdgpu_ttm_tt *gtt = (void *)ttm;
1164         int r;
1165
1166         if (!gtt->bound)
1167                 return;
1168
1169         /* if the pages have userptr pinning then clear that first */
1170         if (gtt->userptr)
1171                 amdgpu_ttm_tt_unpin_userptr(bdev, ttm);
1172
1173         if (gtt->offset == AMDGPU_BO_INVALID_OFFSET)
1174                 return;
1175
1176         /* unbind shouldn't be done for GDS/GWS/OA in ttm_bo_clean_mm */
1177         r = amdgpu_gart_unbind(adev, gtt->offset, ttm->num_pages);
1178         if (r)
1179                 DRM_ERROR("failed to unbind %u pages at 0x%08llX\n",
1180                           gtt->ttm.num_pages, gtt->offset);
1181         gtt->bound = false;
1182 }
1183
1184 static void amdgpu_ttm_backend_destroy(struct ttm_bo_device *bdev,
1185                                        struct ttm_tt *ttm)
1186 {
1187         struct amdgpu_ttm_tt *gtt = (void *)ttm;
1188
1189         amdgpu_ttm_backend_unbind(bdev, ttm);
1190         ttm_tt_destroy_common(bdev, ttm);
1191         if (gtt->usertask)
1192                 put_task_struct(gtt->usertask);
1193
1194         ttm_tt_fini(&gtt->ttm);
1195         kfree(gtt);
1196 }
1197
1198 /**
1199  * amdgpu_ttm_tt_create - Create a ttm_tt object for a given BO
1200  *
1201  * @bo: The buffer object to create a GTT ttm_tt object around
1202  *
1203  * Called by ttm_tt_create().
1204  */
1205 static struct ttm_tt *amdgpu_ttm_tt_create(struct ttm_buffer_object *bo,
1206                                            uint32_t page_flags)
1207 {
1208         struct amdgpu_bo *abo = ttm_to_amdgpu_bo(bo);
1209         struct amdgpu_ttm_tt *gtt;
1210         enum ttm_caching caching;
1211
1212         gtt = kzalloc(sizeof(struct amdgpu_ttm_tt), GFP_KERNEL);
1213         if (gtt == NULL) {
1214                 return NULL;
1215         }
1216         gtt->gobj = &bo->base;
1217
1218         if (abo->flags & AMDGPU_GEM_CREATE_CPU_GTT_USWC)
1219                 caching = ttm_write_combined;
1220         else
1221                 caching = ttm_cached;
1222
1223         /* allocate space for the uninitialized page entries */
1224         if (ttm_sg_tt_init(&gtt->ttm, bo, page_flags, caching)) {
1225                 kfree(gtt);
1226                 return NULL;
1227         }
1228         return &gtt->ttm;
1229 }
1230
1231 /**
1232  * amdgpu_ttm_tt_populate - Map GTT pages visible to the device
1233  *
1234  * Map the pages of a ttm_tt object to an address space visible
1235  * to the underlying device.
1236  */
1237 static int amdgpu_ttm_tt_populate(struct ttm_bo_device *bdev,
1238                                   struct ttm_tt *ttm,
1239                                   struct ttm_operation_ctx *ctx)
1240 {
1241         struct amdgpu_device *adev = amdgpu_ttm_adev(bdev);
1242         struct amdgpu_ttm_tt *gtt = (void *)ttm;
1243
1244         /* user pages are bound by amdgpu_ttm_tt_pin_userptr() */
1245         if (gtt && gtt->userptr) {
1246                 ttm->sg = kzalloc(sizeof(struct sg_table), GFP_KERNEL);
1247                 if (!ttm->sg)
1248                         return -ENOMEM;
1249
1250                 ttm->page_flags |= TTM_PAGE_FLAG_SG;
1251                 return 0;
1252         }
1253
1254         if (ttm->page_flags & TTM_PAGE_FLAG_SG) {
1255                 if (!ttm->sg) {
1256                         struct dma_buf_attachment *attach;
1257                         struct sg_table *sgt;
1258
1259                         attach = gtt->gobj->import_attach;
1260                         sgt = dma_buf_map_attachment(attach, DMA_BIDIRECTIONAL);
1261                         if (IS_ERR(sgt))
1262                                 return PTR_ERR(sgt);
1263
1264                         ttm->sg = sgt;
1265                 }
1266
1267                 drm_prime_sg_to_page_addr_arrays(ttm->sg, ttm->pages,
1268                                                  gtt->ttm.dma_address,
1269                                                  ttm->num_pages);
1270                 return 0;
1271         }
1272
1273         return ttm_pool_alloc(&adev->mman.bdev.pool, ttm, ctx);
1274 }
1275
1276 /**
1277  * amdgpu_ttm_tt_unpopulate - unmap GTT pages and unpopulate page arrays
1278  *
1279  * Unmaps pages of a ttm_tt object from the device address space and
1280  * unpopulates the page array backing it.
1281  */
1282 static void amdgpu_ttm_tt_unpopulate(struct ttm_bo_device *bdev,
1283                                      struct ttm_tt *ttm)
1284 {
1285         struct amdgpu_ttm_tt *gtt = (void *)ttm;
1286         struct amdgpu_device *adev;
1287
1288         if (gtt && gtt->userptr) {
1289                 amdgpu_ttm_tt_set_user_pages(ttm, NULL);
1290                 kfree(ttm->sg);
1291                 ttm->page_flags &= ~TTM_PAGE_FLAG_SG;
1292                 return;
1293         }
1294
1295         if (ttm->sg && gtt->gobj->import_attach) {
1296                 struct dma_buf_attachment *attach;
1297
1298                 attach = gtt->gobj->import_attach;
1299                 dma_buf_unmap_attachment(attach, ttm->sg, DMA_BIDIRECTIONAL);
1300                 ttm->sg = NULL;
1301                 return;
1302         }
1303
1304         if (ttm->page_flags & TTM_PAGE_FLAG_SG)
1305                 return;
1306
1307         adev = amdgpu_ttm_adev(bdev);
1308         return ttm_pool_free(&adev->mman.bdev.pool, ttm);
1309 }
1310
1311 /**
1312  * amdgpu_ttm_tt_set_userptr - Initialize userptr GTT ttm_tt for the current
1313  * task
1314  *
1315  * @bo: The ttm_buffer_object to bind this userptr to
1316  * @addr:  The address in the current tasks VM space to use
1317  * @flags: Requirements of userptr object.
1318  *
1319  * Called by amdgpu_gem_userptr_ioctl() to bind userptr pages
1320  * to current task
1321  */
1322 int amdgpu_ttm_tt_set_userptr(struct ttm_buffer_object *bo,
1323                               uint64_t addr, uint32_t flags)
1324 {
1325         struct amdgpu_ttm_tt *gtt;
1326
1327         if (!bo->ttm) {
1328                 /* TODO: We want a separate TTM object type for userptrs */
1329                 bo->ttm = amdgpu_ttm_tt_create(bo, 0);
1330                 if (bo->ttm == NULL)
1331                         return -ENOMEM;
1332         }
1333
1334         gtt = (void *)bo->ttm;
1335         gtt->userptr = addr;
1336         gtt->userflags = flags;
1337
1338         if (gtt->usertask)
1339                 put_task_struct(gtt->usertask);
1340         gtt->usertask = current->group_leader;
1341         get_task_struct(gtt->usertask);
1342
1343         return 0;
1344 }
1345
1346 /**
1347  * amdgpu_ttm_tt_get_usermm - Return memory manager for ttm_tt object
1348  */
1349 struct mm_struct *amdgpu_ttm_tt_get_usermm(struct ttm_tt *ttm)
1350 {
1351         struct amdgpu_ttm_tt *gtt = (void *)ttm;
1352
1353         if (gtt == NULL)
1354                 return NULL;
1355
1356         if (gtt->usertask == NULL)
1357                 return NULL;
1358
1359         return gtt->usertask->mm;
1360 }
1361
1362 /**
1363  * amdgpu_ttm_tt_affect_userptr - Determine if a ttm_tt object lays inside an
1364  * address range for the current task.
1365  *
1366  */
1367 bool amdgpu_ttm_tt_affect_userptr(struct ttm_tt *ttm, unsigned long start,
1368                                   unsigned long end)
1369 {
1370         struct amdgpu_ttm_tt *gtt = (void *)ttm;
1371         unsigned long size;
1372
1373         if (gtt == NULL || !gtt->userptr)
1374                 return false;
1375
1376         /* Return false if no part of the ttm_tt object lies within
1377          * the range
1378          */
1379         size = (unsigned long)gtt->ttm.num_pages * PAGE_SIZE;
1380         if (gtt->userptr > end || gtt->userptr + size <= start)
1381                 return false;
1382
1383         return true;
1384 }
1385
1386 /**
1387  * amdgpu_ttm_tt_is_userptr - Have the pages backing by userptr?
1388  */
1389 bool amdgpu_ttm_tt_is_userptr(struct ttm_tt *ttm)
1390 {
1391         struct amdgpu_ttm_tt *gtt = (void *)ttm;
1392
1393         if (gtt == NULL || !gtt->userptr)
1394                 return false;
1395
1396         return true;
1397 }
1398
1399 /**
1400  * amdgpu_ttm_tt_is_readonly - Is the ttm_tt object read only?
1401  */
1402 bool amdgpu_ttm_tt_is_readonly(struct ttm_tt *ttm)
1403 {
1404         struct amdgpu_ttm_tt *gtt = (void *)ttm;
1405
1406         if (gtt == NULL)
1407                 return false;
1408
1409         return !!(gtt->userflags & AMDGPU_GEM_USERPTR_READONLY);
1410 }
1411
1412 /**
1413  * amdgpu_ttm_tt_pde_flags - Compute PDE flags for ttm_tt object
1414  *
1415  * @ttm: The ttm_tt object to compute the flags for
1416  * @mem: The memory registry backing this ttm_tt object
1417  *
1418  * Figure out the flags to use for a VM PDE (Page Directory Entry).
1419  */
1420 uint64_t amdgpu_ttm_tt_pde_flags(struct ttm_tt *ttm, struct ttm_resource *mem)
1421 {
1422         uint64_t flags = 0;
1423
1424         if (mem && mem->mem_type != TTM_PL_SYSTEM)
1425                 flags |= AMDGPU_PTE_VALID;
1426
1427         if (mem && mem->mem_type == TTM_PL_TT) {
1428                 flags |= AMDGPU_PTE_SYSTEM;
1429
1430                 if (ttm->caching == ttm_cached)
1431                         flags |= AMDGPU_PTE_SNOOPED;
1432         }
1433
1434         return flags;
1435 }
1436
1437 /**
1438  * amdgpu_ttm_tt_pte_flags - Compute PTE flags for ttm_tt object
1439  *
1440  * @ttm: The ttm_tt object to compute the flags for
1441  * @mem: The memory registry backing this ttm_tt object
1442
1443  * Figure out the flags to use for a VM PTE (Page Table Entry).
1444  */
1445 uint64_t amdgpu_ttm_tt_pte_flags(struct amdgpu_device *adev, struct ttm_tt *ttm,
1446                                  struct ttm_resource *mem)
1447 {
1448         uint64_t flags = amdgpu_ttm_tt_pde_flags(ttm, mem);
1449
1450         flags |= adev->gart.gart_pte_flags;
1451         flags |= AMDGPU_PTE_READABLE;
1452
1453         if (!amdgpu_ttm_tt_is_readonly(ttm))
1454                 flags |= AMDGPU_PTE_WRITEABLE;
1455
1456         return flags;
1457 }
1458
1459 /**
1460  * amdgpu_ttm_bo_eviction_valuable - Check to see if we can evict a buffer
1461  * object.
1462  *
1463  * Return true if eviction is sensible. Called by ttm_mem_evict_first() on
1464  * behalf of ttm_bo_mem_force_space() which tries to evict buffer objects until
1465  * it can find space for a new object and by ttm_bo_force_list_clean() which is
1466  * used to clean out a memory space.
1467  */
1468 static bool amdgpu_ttm_bo_eviction_valuable(struct ttm_buffer_object *bo,
1469                                             const struct ttm_place *place)
1470 {
1471         unsigned long num_pages = bo->mem.num_pages;
1472         struct drm_mm_node *node = bo->mem.mm_node;
1473         struct dma_resv_list *flist;
1474         struct dma_fence *f;
1475         int i;
1476
1477         if (bo->type == ttm_bo_type_kernel &&
1478             !amdgpu_vm_evictable(ttm_to_amdgpu_bo(bo)))
1479                 return false;
1480
1481         /* If bo is a KFD BO, check if the bo belongs to the current process.
1482          * If true, then return false as any KFD process needs all its BOs to
1483          * be resident to run successfully
1484          */
1485         flist = dma_resv_get_list(bo->base.resv);
1486         if (flist) {
1487                 for (i = 0; i < flist->shared_count; ++i) {
1488                         f = rcu_dereference_protected(flist->shared[i],
1489                                 dma_resv_held(bo->base.resv));
1490                         if (amdkfd_fence_check_mm(f, current->mm))
1491                                 return false;
1492                 }
1493         }
1494
1495         switch (bo->mem.mem_type) {
1496         case TTM_PL_TT:
1497                 if (amdgpu_bo_is_amdgpu_bo(bo) &&
1498                     amdgpu_bo_encrypted(ttm_to_amdgpu_bo(bo)))
1499                         return false;
1500                 return true;
1501
1502         case TTM_PL_VRAM:
1503                 /* Check each drm MM node individually */
1504                 while (num_pages) {
1505                         if (place->fpfn < (node->start + node->size) &&
1506                             !(place->lpfn && place->lpfn <= node->start))
1507                                 return true;
1508
1509                         num_pages -= node->size;
1510                         ++node;
1511                 }
1512                 return false;
1513
1514         default:
1515                 break;
1516         }
1517
1518         return ttm_bo_eviction_valuable(bo, place);
1519 }
1520
1521 /**
1522  * amdgpu_ttm_access_memory - Read or Write memory that backs a buffer object.
1523  *
1524  * @bo:  The buffer object to read/write
1525  * @offset:  Offset into buffer object
1526  * @buf:  Secondary buffer to write/read from
1527  * @len: Length in bytes of access
1528  * @write:  true if writing
1529  *
1530  * This is used to access VRAM that backs a buffer object via MMIO
1531  * access for debugging purposes.
1532  */
1533 static int amdgpu_ttm_access_memory(struct ttm_buffer_object *bo,
1534                                     unsigned long offset,
1535                                     void *buf, int len, int write)
1536 {
1537         struct amdgpu_bo *abo = ttm_to_amdgpu_bo(bo);
1538         struct amdgpu_device *adev = amdgpu_ttm_adev(abo->tbo.bdev);
1539         struct drm_mm_node *nodes;
1540         uint32_t value = 0;
1541         int ret = 0;
1542         uint64_t pos;
1543         unsigned long flags;
1544
1545         if (bo->mem.mem_type != TTM_PL_VRAM)
1546                 return -EIO;
1547
1548         pos = offset;
1549         nodes = amdgpu_find_mm_node(&abo->tbo.mem, &pos);
1550         pos += (nodes->start << PAGE_SHIFT);
1551
1552         while (len && pos < adev->gmc.mc_vram_size) {
1553                 uint64_t aligned_pos = pos & ~(uint64_t)3;
1554                 uint64_t bytes = 4 - (pos & 3);
1555                 uint32_t shift = (pos & 3) * 8;
1556                 uint32_t mask = 0xffffffff << shift;
1557
1558                 if (len < bytes) {
1559                         mask &= 0xffffffff >> (bytes - len) * 8;
1560                         bytes = len;
1561                 }
1562
1563                 if (mask != 0xffffffff) {
1564                         spin_lock_irqsave(&adev->mmio_idx_lock, flags);
1565                         WREG32_NO_KIQ(mmMM_INDEX, ((uint32_t)aligned_pos) | 0x80000000);
1566                         WREG32_NO_KIQ(mmMM_INDEX_HI, aligned_pos >> 31);
1567                         if (!write || mask != 0xffffffff)
1568                                 value = RREG32_NO_KIQ(mmMM_DATA);
1569                         if (write) {
1570                                 value &= ~mask;
1571                                 value |= (*(uint32_t *)buf << shift) & mask;
1572                                 WREG32_NO_KIQ(mmMM_DATA, value);
1573                         }
1574                         spin_unlock_irqrestore(&adev->mmio_idx_lock, flags);
1575                         if (!write) {
1576                                 value = (value & mask) >> shift;
1577                                 memcpy(buf, &value, bytes);
1578                         }
1579                 } else {
1580                         bytes = (nodes->start + nodes->size) << PAGE_SHIFT;
1581                         bytes = min(bytes - pos, (uint64_t)len & ~0x3ull);
1582
1583                         amdgpu_device_vram_access(adev, pos, (uint32_t *)buf,
1584                                                   bytes, write);
1585                 }
1586
1587                 ret += bytes;
1588                 buf = (uint8_t *)buf + bytes;
1589                 pos += bytes;
1590                 len -= bytes;
1591                 if (pos >= (nodes->start + nodes->size) << PAGE_SHIFT) {
1592                         ++nodes;
1593                         pos = (nodes->start << PAGE_SHIFT);
1594                 }
1595         }
1596
1597         return ret;
1598 }
1599
1600 static void
1601 amdgpu_bo_delete_mem_notify(struct ttm_buffer_object *bo)
1602 {
1603         amdgpu_bo_move_notify(bo, false, NULL);
1604 }
1605
1606 static struct ttm_bo_driver amdgpu_bo_driver = {
1607         .ttm_tt_create = &amdgpu_ttm_tt_create,
1608         .ttm_tt_populate = &amdgpu_ttm_tt_populate,
1609         .ttm_tt_unpopulate = &amdgpu_ttm_tt_unpopulate,
1610         .ttm_tt_destroy = &amdgpu_ttm_backend_destroy,
1611         .eviction_valuable = amdgpu_ttm_bo_eviction_valuable,
1612         .evict_flags = &amdgpu_evict_flags,
1613         .move = &amdgpu_bo_move,
1614         .verify_access = &amdgpu_verify_access,
1615         .delete_mem_notify = &amdgpu_bo_delete_mem_notify,
1616         .release_notify = &amdgpu_bo_release_notify,
1617         .io_mem_reserve = &amdgpu_ttm_io_mem_reserve,
1618         .io_mem_pfn = amdgpu_ttm_io_mem_pfn,
1619         .access_memory = &amdgpu_ttm_access_memory,
1620         .del_from_lru_notify = &amdgpu_vm_del_from_lru_notify
1621 };
1622
1623 /*
1624  * Firmware Reservation functions
1625  */
1626 /**
1627  * amdgpu_ttm_fw_reserve_vram_fini - free fw reserved vram
1628  *
1629  * @adev: amdgpu_device pointer
1630  *
1631  * free fw reserved vram if it has been reserved.
1632  */
1633 static void amdgpu_ttm_fw_reserve_vram_fini(struct amdgpu_device *adev)
1634 {
1635         amdgpu_bo_free_kernel(&adev->mman.fw_vram_usage_reserved_bo,
1636                 NULL, &adev->mman.fw_vram_usage_va);
1637 }
1638
1639 /**
1640  * amdgpu_ttm_fw_reserve_vram_init - create bo vram reservation from fw
1641  *
1642  * @adev: amdgpu_device pointer
1643  *
1644  * create bo vram reservation from fw.
1645  */
1646 static int amdgpu_ttm_fw_reserve_vram_init(struct amdgpu_device *adev)
1647 {
1648         uint64_t vram_size = adev->gmc.visible_vram_size;
1649
1650         adev->mman.fw_vram_usage_va = NULL;
1651         adev->mman.fw_vram_usage_reserved_bo = NULL;
1652
1653         if (adev->mman.fw_vram_usage_size == 0 ||
1654             adev->mman.fw_vram_usage_size > vram_size)
1655                 return 0;
1656
1657         return amdgpu_bo_create_kernel_at(adev,
1658                                           adev->mman.fw_vram_usage_start_offset,
1659                                           adev->mman.fw_vram_usage_size,
1660                                           AMDGPU_GEM_DOMAIN_VRAM,
1661                                           &adev->mman.fw_vram_usage_reserved_bo,
1662                                           &adev->mman.fw_vram_usage_va);
1663 }
1664
1665 /*
1666  * Memoy training reservation functions
1667  */
1668
1669 /**
1670  * amdgpu_ttm_training_reserve_vram_fini - free memory training reserved vram
1671  *
1672  * @adev: amdgpu_device pointer
1673  *
1674  * free memory training reserved vram if it has been reserved.
1675  */
1676 static int amdgpu_ttm_training_reserve_vram_fini(struct amdgpu_device *adev)
1677 {
1678         struct psp_memory_training_context *ctx = &adev->psp.mem_train_ctx;
1679
1680         ctx->init = PSP_MEM_TRAIN_NOT_SUPPORT;
1681         amdgpu_bo_free_kernel(&ctx->c2p_bo, NULL, NULL);
1682         ctx->c2p_bo = NULL;
1683
1684         return 0;
1685 }
1686
1687 static void amdgpu_ttm_training_data_block_init(struct amdgpu_device *adev)
1688 {
1689         struct psp_memory_training_context *ctx = &adev->psp.mem_train_ctx;
1690
1691         memset(ctx, 0, sizeof(*ctx));
1692
1693         ctx->c2p_train_data_offset =
1694                 ALIGN((adev->gmc.mc_vram_size - adev->mman.discovery_tmr_size - SZ_1M), SZ_1M);
1695         ctx->p2c_train_data_offset =
1696                 (adev->gmc.mc_vram_size - GDDR6_MEM_TRAINING_OFFSET);
1697         ctx->train_data_size =
1698                 GDDR6_MEM_TRAINING_DATA_SIZE_IN_BYTES;
1699
1700         DRM_DEBUG("train_data_size:%llx,p2c_train_data_offset:%llx,c2p_train_data_offset:%llx.\n",
1701                         ctx->train_data_size,
1702                         ctx->p2c_train_data_offset,
1703                         ctx->c2p_train_data_offset);
1704 }
1705
1706 /*
1707  * reserve TMR memory at the top of VRAM which holds
1708  * IP Discovery data and is protected by PSP.
1709  */
1710 static int amdgpu_ttm_reserve_tmr(struct amdgpu_device *adev)
1711 {
1712         int ret;
1713         struct psp_memory_training_context *ctx = &adev->psp.mem_train_ctx;
1714         bool mem_train_support = false;
1715
1716         if (!amdgpu_sriov_vf(adev)) {
1717                 ret = amdgpu_mem_train_support(adev);
1718                 if (ret == 1)
1719                         mem_train_support = true;
1720                 else if (ret == -1)
1721                         return -EINVAL;
1722                 else
1723                         DRM_DEBUG("memory training does not support!\n");
1724         }
1725
1726         /*
1727          * Query reserved tmr size through atom firmwareinfo for Sienna_Cichlid and onwards for all
1728          * the use cases (IP discovery/G6 memory training/profiling/diagnostic data.etc)
1729          *
1730          * Otherwise, fallback to legacy approach to check and reserve tmr block for ip
1731          * discovery data and G6 memory training data respectively
1732          */
1733         adev->mman.discovery_tmr_size =
1734                 amdgpu_atomfirmware_get_fw_reserved_fb_size(adev);
1735         if (!adev->mman.discovery_tmr_size)
1736                 adev->mman.discovery_tmr_size = DISCOVERY_TMR_OFFSET;
1737
1738         if (mem_train_support) {
1739                 /* reserve vram for mem train according to TMR location */
1740                 amdgpu_ttm_training_data_block_init(adev);
1741                 ret = amdgpu_bo_create_kernel_at(adev,
1742                                          ctx->c2p_train_data_offset,
1743                                          ctx->train_data_size,
1744                                          AMDGPU_GEM_DOMAIN_VRAM,
1745                                          &ctx->c2p_bo,
1746                                          NULL);
1747                 if (ret) {
1748                         DRM_ERROR("alloc c2p_bo failed(%d)!\n", ret);
1749                         amdgpu_ttm_training_reserve_vram_fini(adev);
1750                         return ret;
1751                 }
1752                 ctx->init = PSP_MEM_TRAIN_RESERVE_SUCCESS;
1753         }
1754
1755         ret = amdgpu_bo_create_kernel_at(adev,
1756                                 adev->gmc.real_vram_size - adev->mman.discovery_tmr_size,
1757                                 adev->mman.discovery_tmr_size,
1758                                 AMDGPU_GEM_DOMAIN_VRAM,
1759                                 &adev->mman.discovery_memory,
1760                                 NULL);
1761         if (ret) {
1762                 DRM_ERROR("alloc tmr failed(%d)!\n", ret);
1763                 amdgpu_bo_free_kernel(&adev->mman.discovery_memory, NULL, NULL);
1764                 return ret;
1765         }
1766
1767         return 0;
1768 }
1769
1770 /**
1771  * amdgpu_ttm_init - Init the memory management (ttm) as well as various
1772  * gtt/vram related fields.
1773  *
1774  * This initializes all of the memory space pools that the TTM layer
1775  * will need such as the GTT space (system memory mapped to the device),
1776  * VRAM (on-board memory), and on-chip memories (GDS, GWS, OA) which
1777  * can be mapped per VMID.
1778  */
1779 int amdgpu_ttm_init(struct amdgpu_device *adev)
1780 {
1781         uint64_t gtt_size;
1782         int r;
1783         u64 vis_vram_limit;
1784
1785         mutex_init(&adev->mman.gtt_window_lock);
1786
1787         /* No others user of address space so set it to 0 */
1788         r = ttm_bo_device_init(&adev->mman.bdev, &amdgpu_bo_driver, adev->dev,
1789                                adev_to_drm(adev)->anon_inode->i_mapping,
1790                                adev_to_drm(adev)->vma_offset_manager,
1791                                adev->need_swiotlb,
1792                                dma_addressing_limited(adev->dev));
1793         if (r) {
1794                 DRM_ERROR("failed initializing buffer object driver(%d).\n", r);
1795                 return r;
1796         }
1797         adev->mman.initialized = true;
1798
1799         /* Initialize VRAM pool with all of VRAM divided into pages */
1800         r = amdgpu_vram_mgr_init(adev);
1801         if (r) {
1802                 DRM_ERROR("Failed initializing VRAM heap.\n");
1803                 return r;
1804         }
1805
1806         /* Reduce size of CPU-visible VRAM if requested */
1807         vis_vram_limit = (u64)amdgpu_vis_vram_limit * 1024 * 1024;
1808         if (amdgpu_vis_vram_limit > 0 &&
1809             vis_vram_limit <= adev->gmc.visible_vram_size)
1810                 adev->gmc.visible_vram_size = vis_vram_limit;
1811
1812         /* Change the size here instead of the init above so only lpfn is affected */
1813         amdgpu_ttm_set_buffer_funcs_status(adev, false);
1814 #ifdef CONFIG_64BIT
1815         adev->mman.aper_base_kaddr = ioremap_wc(adev->gmc.aper_base,
1816                                                 adev->gmc.visible_vram_size);
1817 #endif
1818
1819         /*
1820          *The reserved vram for firmware must be pinned to the specified
1821          *place on the VRAM, so reserve it early.
1822          */
1823         r = amdgpu_ttm_fw_reserve_vram_init(adev);
1824         if (r) {
1825                 return r;
1826         }
1827
1828         /*
1829          * only NAVI10 and onwards ASIC support for IP discovery.
1830          * If IP discovery enabled, a block of memory should be
1831          * reserved for IP discovey.
1832          */
1833         if (adev->mman.discovery_bin) {
1834                 r = amdgpu_ttm_reserve_tmr(adev);
1835                 if (r)
1836                         return r;
1837         }
1838
1839         /* allocate memory as required for VGA
1840          * This is used for VGA emulation and pre-OS scanout buffers to
1841          * avoid display artifacts while transitioning between pre-OS
1842          * and driver.  */
1843         r = amdgpu_bo_create_kernel_at(adev, 0, adev->mman.stolen_vga_size,
1844                                        AMDGPU_GEM_DOMAIN_VRAM,
1845                                        &adev->mman.stolen_vga_memory,
1846                                        NULL);
1847         if (r)
1848                 return r;
1849         r = amdgpu_bo_create_kernel_at(adev, adev->mman.stolen_vga_size,
1850                                        adev->mman.stolen_extended_size,
1851                                        AMDGPU_GEM_DOMAIN_VRAM,
1852                                        &adev->mman.stolen_extended_memory,
1853                                        NULL);
1854         if (r)
1855                 return r;
1856
1857         DRM_INFO("amdgpu: %uM of VRAM memory ready\n",
1858                  (unsigned) (adev->gmc.real_vram_size / (1024 * 1024)));
1859
1860         /* Compute GTT size, either bsaed on 3/4th the size of RAM size
1861          * or whatever the user passed on module init */
1862         if (amdgpu_gtt_size == -1) {
1863                 struct sysinfo si;
1864
1865                 si_meminfo(&si);
1866                 gtt_size = min(max((AMDGPU_DEFAULT_GTT_SIZE_MB << 20),
1867                                adev->gmc.mc_vram_size),
1868                                ((uint64_t)si.totalram * si.mem_unit * 3/4));
1869         }
1870         else
1871                 gtt_size = (uint64_t)amdgpu_gtt_size << 20;
1872
1873         /* Initialize GTT memory pool */
1874         r = amdgpu_gtt_mgr_init(adev, gtt_size);
1875         if (r) {
1876                 DRM_ERROR("Failed initializing GTT heap.\n");
1877                 return r;
1878         }
1879         DRM_INFO("amdgpu: %uM of GTT memory ready.\n",
1880                  (unsigned)(gtt_size / (1024 * 1024)));
1881
1882         /* Initialize various on-chip memory pools */
1883         r = amdgpu_ttm_init_on_chip(adev, AMDGPU_PL_GDS, adev->gds.gds_size);
1884         if (r) {
1885                 DRM_ERROR("Failed initializing GDS heap.\n");
1886                 return r;
1887         }
1888
1889         r = amdgpu_ttm_init_on_chip(adev, AMDGPU_PL_GWS, adev->gds.gws_size);
1890         if (r) {
1891                 DRM_ERROR("Failed initializing gws heap.\n");
1892                 return r;
1893         }
1894
1895         r = amdgpu_ttm_init_on_chip(adev, AMDGPU_PL_OA, adev->gds.oa_size);
1896         if (r) {
1897                 DRM_ERROR("Failed initializing oa heap.\n");
1898                 return r;
1899         }
1900
1901         return 0;
1902 }
1903
1904 /**
1905  * amdgpu_ttm_late_init - Handle any late initialization for amdgpu_ttm
1906  */
1907 void amdgpu_ttm_late_init(struct amdgpu_device *adev)
1908 {
1909         /* return the VGA stolen memory (if any) back to VRAM */
1910         if (!adev->mman.keep_stolen_vga_memory)
1911                 amdgpu_bo_free_kernel(&adev->mman.stolen_vga_memory, NULL, NULL);
1912         amdgpu_bo_free_kernel(&adev->mman.stolen_extended_memory, NULL, NULL);
1913 }
1914
1915 /**
1916  * amdgpu_ttm_fini - De-initialize the TTM memory pools
1917  */
1918 void amdgpu_ttm_fini(struct amdgpu_device *adev)
1919 {
1920         if (!adev->mman.initialized)
1921                 return;
1922
1923         amdgpu_ttm_training_reserve_vram_fini(adev);
1924         /* return the stolen vga memory back to VRAM */
1925         if (adev->mman.keep_stolen_vga_memory)
1926                 amdgpu_bo_free_kernel(&adev->mman.stolen_vga_memory, NULL, NULL);
1927         /* return the IP Discovery TMR memory back to VRAM */
1928         amdgpu_bo_free_kernel(&adev->mman.discovery_memory, NULL, NULL);
1929         amdgpu_ttm_fw_reserve_vram_fini(adev);
1930
1931         if (adev->mman.aper_base_kaddr)
1932                 iounmap(adev->mman.aper_base_kaddr);
1933         adev->mman.aper_base_kaddr = NULL;
1934
1935         amdgpu_vram_mgr_fini(adev);
1936         amdgpu_gtt_mgr_fini(adev);
1937         ttm_range_man_fini(&adev->mman.bdev, AMDGPU_PL_GDS);
1938         ttm_range_man_fini(&adev->mman.bdev, AMDGPU_PL_GWS);
1939         ttm_range_man_fini(&adev->mman.bdev, AMDGPU_PL_OA);
1940         ttm_bo_device_release(&adev->mman.bdev);
1941         adev->mman.initialized = false;
1942         DRM_INFO("amdgpu: ttm finalized\n");
1943 }
1944
1945 /**
1946  * amdgpu_ttm_set_buffer_funcs_status - enable/disable use of buffer functions
1947  *
1948  * @adev: amdgpu_device pointer
1949  * @enable: true when we can use buffer functions.
1950  *
1951  * Enable/disable use of buffer functions during suspend/resume. This should
1952  * only be called at bootup or when userspace isn't running.
1953  */
1954 void amdgpu_ttm_set_buffer_funcs_status(struct amdgpu_device *adev, bool enable)
1955 {
1956         struct ttm_resource_manager *man = ttm_manager_type(&adev->mman.bdev, TTM_PL_VRAM);
1957         uint64_t size;
1958         int r;
1959
1960         if (!adev->mman.initialized || amdgpu_in_reset(adev) ||
1961             adev->mman.buffer_funcs_enabled == enable)
1962                 return;
1963
1964         if (enable) {
1965                 struct amdgpu_ring *ring;
1966                 struct drm_gpu_scheduler *sched;
1967
1968                 ring = adev->mman.buffer_funcs_ring;
1969                 sched = &ring->sched;
1970                 r = drm_sched_entity_init(&adev->mman.entity,
1971                                           DRM_SCHED_PRIORITY_KERNEL, &sched,
1972                                           1, NULL);
1973                 if (r) {
1974                         DRM_ERROR("Failed setting up TTM BO move entity (%d)\n",
1975                                   r);
1976                         return;
1977                 }
1978         } else {
1979                 drm_sched_entity_destroy(&adev->mman.entity);
1980                 dma_fence_put(man->move);
1981                 man->move = NULL;
1982         }
1983
1984         /* this just adjusts TTM size idea, which sets lpfn to the correct value */
1985         if (enable)
1986                 size = adev->gmc.real_vram_size;
1987         else
1988                 size = adev->gmc.visible_vram_size;
1989         man->size = size >> PAGE_SHIFT;
1990         adev->mman.buffer_funcs_enabled = enable;
1991 }
1992
1993 static vm_fault_t amdgpu_ttm_fault(struct vm_fault *vmf)
1994 {
1995         struct ttm_buffer_object *bo = vmf->vma->vm_private_data;
1996         vm_fault_t ret;
1997
1998         ret = ttm_bo_vm_reserve(bo, vmf);
1999         if (ret)
2000                 return ret;
2001
2002         ret = amdgpu_bo_fault_reserve_notify(bo);
2003         if (ret)
2004                 goto unlock;
2005
2006         ret = ttm_bo_vm_fault_reserved(vmf, vmf->vma->vm_page_prot,
2007                                        TTM_BO_VM_NUM_PREFAULT, 1);
2008         if (ret == VM_FAULT_RETRY && !(vmf->flags & FAULT_FLAG_RETRY_NOWAIT))
2009                 return ret;
2010
2011 unlock:
2012         dma_resv_unlock(bo->base.resv);
2013         return ret;
2014 }
2015
2016 static struct vm_operations_struct amdgpu_ttm_vm_ops = {
2017         .fault = amdgpu_ttm_fault,
2018         .open = ttm_bo_vm_open,
2019         .close = ttm_bo_vm_close,
2020         .access = ttm_bo_vm_access
2021 };
2022
2023 int amdgpu_mmap(struct file *filp, struct vm_area_struct *vma)
2024 {
2025         struct drm_file *file_priv = filp->private_data;
2026         struct amdgpu_device *adev = drm_to_adev(file_priv->minor->dev);
2027         int r;
2028
2029         r = ttm_bo_mmap(filp, vma, &adev->mman.bdev);
2030         if (unlikely(r != 0))
2031                 return r;
2032
2033         vma->vm_ops = &amdgpu_ttm_vm_ops;
2034         return 0;
2035 }
2036
2037 int amdgpu_copy_buffer(struct amdgpu_ring *ring, uint64_t src_offset,
2038                        uint64_t dst_offset, uint32_t byte_count,
2039                        struct dma_resv *resv,
2040                        struct dma_fence **fence, bool direct_submit,
2041                        bool vm_needs_flush, bool tmz)
2042 {
2043         enum amdgpu_ib_pool_type pool = direct_submit ? AMDGPU_IB_POOL_DIRECT :
2044                 AMDGPU_IB_POOL_DELAYED;
2045         struct amdgpu_device *adev = ring->adev;
2046         struct amdgpu_job *job;
2047
2048         uint32_t max_bytes;
2049         unsigned num_loops, num_dw;
2050         unsigned i;
2051         int r;
2052
2053         if (direct_submit && !ring->sched.ready) {
2054                 DRM_ERROR("Trying to move memory with ring turned off.\n");
2055                 return -EINVAL;
2056         }
2057
2058         max_bytes = adev->mman.buffer_funcs->copy_max_bytes;
2059         num_loops = DIV_ROUND_UP(byte_count, max_bytes);
2060         num_dw = ALIGN(num_loops * adev->mman.buffer_funcs->copy_num_dw, 8);
2061
2062         r = amdgpu_job_alloc_with_ib(adev, num_dw * 4, pool, &job);
2063         if (r)
2064                 return r;
2065
2066         if (vm_needs_flush) {
2067                 job->vm_pd_addr = amdgpu_gmc_pd_addr(adev->gart.bo);
2068                 job->vm_needs_flush = true;
2069         }
2070         if (resv) {
2071                 r = amdgpu_sync_resv(adev, &job->sync, resv,
2072                                      AMDGPU_SYNC_ALWAYS,
2073                                      AMDGPU_FENCE_OWNER_UNDEFINED);
2074                 if (r) {
2075                         DRM_ERROR("sync failed (%d).\n", r);
2076                         goto error_free;
2077                 }
2078         }
2079
2080         for (i = 0; i < num_loops; i++) {
2081                 uint32_t cur_size_in_bytes = min(byte_count, max_bytes);
2082
2083                 amdgpu_emit_copy_buffer(adev, &job->ibs[0], src_offset,
2084                                         dst_offset, cur_size_in_bytes, tmz);
2085
2086                 src_offset += cur_size_in_bytes;
2087                 dst_offset += cur_size_in_bytes;
2088                 byte_count -= cur_size_in_bytes;
2089         }
2090
2091         amdgpu_ring_pad_ib(ring, &job->ibs[0]);
2092         WARN_ON(job->ibs[0].length_dw > num_dw);
2093         if (direct_submit)
2094                 r = amdgpu_job_submit_direct(job, ring, fence);
2095         else
2096                 r = amdgpu_job_submit(job, &adev->mman.entity,
2097                                       AMDGPU_FENCE_OWNER_UNDEFINED, fence);
2098         if (r)
2099                 goto error_free;
2100
2101         return r;
2102
2103 error_free:
2104         amdgpu_job_free(job);
2105         DRM_ERROR("Error scheduling IBs (%d)\n", r);
2106         return r;
2107 }
2108
2109 int amdgpu_fill_buffer(struct amdgpu_bo *bo,
2110                        uint32_t src_data,
2111                        struct dma_resv *resv,
2112                        struct dma_fence **fence)
2113 {
2114         struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
2115         uint32_t max_bytes = adev->mman.buffer_funcs->fill_max_bytes;
2116         struct amdgpu_ring *ring = adev->mman.buffer_funcs_ring;
2117
2118         struct drm_mm_node *mm_node;
2119         unsigned long num_pages;
2120         unsigned int num_loops, num_dw;
2121
2122         struct amdgpu_job *job;
2123         int r;
2124
2125         if (!adev->mman.buffer_funcs_enabled) {
2126                 DRM_ERROR("Trying to clear memory with ring turned off.\n");
2127                 return -EINVAL;
2128         }
2129
2130         if (bo->tbo.mem.mem_type == TTM_PL_TT) {
2131                 r = amdgpu_ttm_alloc_gart(&bo->tbo);
2132                 if (r)
2133                         return r;
2134         }
2135
2136         num_pages = bo->tbo.num_pages;
2137         mm_node = bo->tbo.mem.mm_node;
2138         num_loops = 0;
2139         while (num_pages) {
2140                 uint64_t byte_count = mm_node->size << PAGE_SHIFT;
2141
2142                 num_loops += DIV_ROUND_UP_ULL(byte_count, max_bytes);
2143                 num_pages -= mm_node->size;
2144                 ++mm_node;
2145         }
2146         num_dw = num_loops * adev->mman.buffer_funcs->fill_num_dw;
2147
2148         /* for IB padding */
2149         num_dw += 64;
2150
2151         r = amdgpu_job_alloc_with_ib(adev, num_dw * 4, AMDGPU_IB_POOL_DELAYED,
2152                                      &job);
2153         if (r)
2154                 return r;
2155
2156         if (resv) {
2157                 r = amdgpu_sync_resv(adev, &job->sync, resv,
2158                                      AMDGPU_SYNC_ALWAYS,
2159                                      AMDGPU_FENCE_OWNER_UNDEFINED);
2160                 if (r) {
2161                         DRM_ERROR("sync failed (%d).\n", r);
2162                         goto error_free;
2163                 }
2164         }
2165
2166         num_pages = bo->tbo.num_pages;
2167         mm_node = bo->tbo.mem.mm_node;
2168
2169         while (num_pages) {
2170                 uint64_t byte_count = mm_node->size << PAGE_SHIFT;
2171                 uint64_t dst_addr;
2172
2173                 dst_addr = amdgpu_mm_node_addr(&bo->tbo, mm_node, &bo->tbo.mem);
2174                 while (byte_count) {
2175                         uint32_t cur_size_in_bytes = min_t(uint64_t, byte_count,
2176                                                            max_bytes);
2177
2178                         amdgpu_emit_fill_buffer(adev, &job->ibs[0], src_data,
2179                                                 dst_addr, cur_size_in_bytes);
2180
2181                         dst_addr += cur_size_in_bytes;
2182                         byte_count -= cur_size_in_bytes;
2183                 }
2184
2185                 num_pages -= mm_node->size;
2186                 ++mm_node;
2187         }
2188
2189         amdgpu_ring_pad_ib(ring, &job->ibs[0]);
2190         WARN_ON(job->ibs[0].length_dw > num_dw);
2191         r = amdgpu_job_submit(job, &adev->mman.entity,
2192                               AMDGPU_FENCE_OWNER_UNDEFINED, fence);
2193         if (r)
2194                 goto error_free;
2195
2196         return 0;
2197
2198 error_free:
2199         amdgpu_job_free(job);
2200         return r;
2201 }
2202
2203 #if defined(CONFIG_DEBUG_FS)
2204
2205 static int amdgpu_mm_dump_table(struct seq_file *m, void *data)
2206 {
2207         struct drm_info_node *node = (struct drm_info_node *)m->private;
2208         unsigned ttm_pl = (uintptr_t)node->info_ent->data;
2209         struct drm_device *dev = node->minor->dev;
2210         struct amdgpu_device *adev = drm_to_adev(dev);
2211         struct ttm_resource_manager *man = ttm_manager_type(&adev->mman.bdev, ttm_pl);
2212         struct drm_printer p = drm_seq_file_printer(m);
2213
2214         man->func->debug(man, &p);
2215         return 0;
2216 }
2217
2218 static int amdgpu_ttm_pool_debugfs(struct seq_file *m, void *data)
2219 {
2220         struct drm_info_node *node = (struct drm_info_node *)m->private;
2221         struct drm_device *dev = node->minor->dev;
2222         struct amdgpu_device *adev = drm_to_adev(dev);
2223
2224         return ttm_pool_debugfs(&adev->mman.bdev.pool, m);
2225 }
2226
2227 static const struct drm_info_list amdgpu_ttm_debugfs_list[] = {
2228         {"amdgpu_vram_mm", amdgpu_mm_dump_table, 0, (void *)TTM_PL_VRAM},
2229         {"amdgpu_gtt_mm", amdgpu_mm_dump_table, 0, (void *)TTM_PL_TT},
2230         {"amdgpu_gds_mm", amdgpu_mm_dump_table, 0, (void *)AMDGPU_PL_GDS},
2231         {"amdgpu_gws_mm", amdgpu_mm_dump_table, 0, (void *)AMDGPU_PL_GWS},
2232         {"amdgpu_oa_mm", amdgpu_mm_dump_table, 0, (void *)AMDGPU_PL_OA},
2233         {"ttm_page_pool", amdgpu_ttm_pool_debugfs, 0, NULL},
2234 };
2235
2236 /**
2237  * amdgpu_ttm_vram_read - Linear read access to VRAM
2238  *
2239  * Accesses VRAM via MMIO for debugging purposes.
2240  */
2241 static ssize_t amdgpu_ttm_vram_read(struct file *f, char __user *buf,
2242                                     size_t size, loff_t *pos)
2243 {
2244         struct amdgpu_device *adev = file_inode(f)->i_private;
2245         ssize_t result = 0;
2246
2247         if (size & 0x3 || *pos & 0x3)
2248                 return -EINVAL;
2249
2250         if (*pos >= adev->gmc.mc_vram_size)
2251                 return -ENXIO;
2252
2253         size = min(size, (size_t)(adev->gmc.mc_vram_size - *pos));
2254         while (size) {
2255                 size_t bytes = min(size, AMDGPU_TTM_VRAM_MAX_DW_READ * 4);
2256                 uint32_t value[AMDGPU_TTM_VRAM_MAX_DW_READ];
2257
2258                 amdgpu_device_vram_access(adev, *pos, value, bytes, false);
2259                 if (copy_to_user(buf, value, bytes))
2260                         return -EFAULT;
2261
2262                 result += bytes;
2263                 buf += bytes;
2264                 *pos += bytes;
2265                 size -= bytes;
2266         }
2267
2268         return result;
2269 }
2270
2271 /**
2272  * amdgpu_ttm_vram_write - Linear write access to VRAM
2273  *
2274  * Accesses VRAM via MMIO for debugging purposes.
2275  */
2276 static ssize_t amdgpu_ttm_vram_write(struct file *f, const char __user *buf,
2277                                     size_t size, loff_t *pos)
2278 {
2279         struct amdgpu_device *adev = file_inode(f)->i_private;
2280         ssize_t result = 0;
2281         int r;
2282
2283         if (size & 0x3 || *pos & 0x3)
2284                 return -EINVAL;
2285
2286         if (*pos >= adev->gmc.mc_vram_size)
2287                 return -ENXIO;
2288
2289         while (size) {
2290                 unsigned long flags;
2291                 uint32_t value;
2292
2293                 if (*pos >= adev->gmc.mc_vram_size)
2294                         return result;
2295
2296                 r = get_user(value, (uint32_t *)buf);
2297                 if (r)
2298                         return r;
2299
2300                 spin_lock_irqsave(&adev->mmio_idx_lock, flags);
2301                 WREG32_NO_KIQ(mmMM_INDEX, ((uint32_t)*pos) | 0x80000000);
2302                 WREG32_NO_KIQ(mmMM_INDEX_HI, *pos >> 31);
2303                 WREG32_NO_KIQ(mmMM_DATA, value);
2304                 spin_unlock_irqrestore(&adev->mmio_idx_lock, flags);
2305
2306                 result += 4;
2307                 buf += 4;
2308                 *pos += 4;
2309                 size -= 4;
2310         }
2311
2312         return result;
2313 }
2314
2315 static const struct file_operations amdgpu_ttm_vram_fops = {
2316         .owner = THIS_MODULE,
2317         .read = amdgpu_ttm_vram_read,
2318         .write = amdgpu_ttm_vram_write,
2319         .llseek = default_llseek,
2320 };
2321
2322 #ifdef CONFIG_DRM_AMDGPU_GART_DEBUGFS
2323
2324 /**
2325  * amdgpu_ttm_gtt_read - Linear read access to GTT memory
2326  */
2327 static ssize_t amdgpu_ttm_gtt_read(struct file *f, char __user *buf,
2328                                    size_t size, loff_t *pos)
2329 {
2330         struct amdgpu_device *adev = file_inode(f)->i_private;
2331         ssize_t result = 0;
2332         int r;
2333
2334         while (size) {
2335                 loff_t p = *pos / PAGE_SIZE;
2336                 unsigned off = *pos & ~PAGE_MASK;
2337                 size_t cur_size = min_t(size_t, size, PAGE_SIZE - off);
2338                 struct page *page;
2339                 void *ptr;
2340
2341                 if (p >= adev->gart.num_cpu_pages)
2342                         return result;
2343
2344                 page = adev->gart.pages[p];
2345                 if (page) {
2346                         ptr = kmap(page);
2347                         ptr += off;
2348
2349                         r = copy_to_user(buf, ptr, cur_size);
2350                         kunmap(adev->gart.pages[p]);
2351                 } else
2352                         r = clear_user(buf, cur_size);
2353
2354                 if (r)
2355                         return -EFAULT;
2356
2357                 result += cur_size;
2358                 buf += cur_size;
2359                 *pos += cur_size;
2360                 size -= cur_size;
2361         }
2362
2363         return result;
2364 }
2365
2366 static const struct file_operations amdgpu_ttm_gtt_fops = {
2367         .owner = THIS_MODULE,
2368         .read = amdgpu_ttm_gtt_read,
2369         .llseek = default_llseek
2370 };
2371
2372 #endif
2373
2374 /**
2375  * amdgpu_iomem_read - Virtual read access to GPU mapped memory
2376  *
2377  * This function is used to read memory that has been mapped to the
2378  * GPU and the known addresses are not physical addresses but instead
2379  * bus addresses (e.g., what you'd put in an IB or ring buffer).
2380  */
2381 static ssize_t amdgpu_iomem_read(struct file *f, char __user *buf,
2382                                  size_t size, loff_t *pos)
2383 {
2384         struct amdgpu_device *adev = file_inode(f)->i_private;
2385         struct iommu_domain *dom;
2386         ssize_t result = 0;
2387         int r;
2388
2389         /* retrieve the IOMMU domain if any for this device */
2390         dom = iommu_get_domain_for_dev(adev->dev);
2391
2392         while (size) {
2393                 phys_addr_t addr = *pos & PAGE_MASK;
2394                 loff_t off = *pos & ~PAGE_MASK;
2395                 size_t bytes = PAGE_SIZE - off;
2396                 unsigned long pfn;
2397                 struct page *p;
2398                 void *ptr;
2399
2400                 bytes = bytes < size ? bytes : size;
2401
2402                 /* Translate the bus address to a physical address.  If
2403                  * the domain is NULL it means there is no IOMMU active
2404                  * and the address translation is the identity
2405                  */
2406                 addr = dom ? iommu_iova_to_phys(dom, addr) : addr;
2407
2408                 pfn = addr >> PAGE_SHIFT;
2409                 if (!pfn_valid(pfn))
2410                         return -EPERM;
2411
2412                 p = pfn_to_page(pfn);
2413                 if (p->mapping != adev->mman.bdev.dev_mapping)
2414                         return -EPERM;
2415
2416                 ptr = kmap(p);
2417                 r = copy_to_user(buf, ptr + off, bytes);
2418                 kunmap(p);
2419                 if (r)
2420                         return -EFAULT;
2421
2422                 size -= bytes;
2423                 *pos += bytes;
2424                 result += bytes;
2425         }
2426
2427         return result;
2428 }
2429
2430 /**
2431  * amdgpu_iomem_write - Virtual write access to GPU mapped memory
2432  *
2433  * This function is used to write memory that has been mapped to the
2434  * GPU and the known addresses are not physical addresses but instead
2435  * bus addresses (e.g., what you'd put in an IB or ring buffer).
2436  */
2437 static ssize_t amdgpu_iomem_write(struct file *f, const char __user *buf,
2438                                  size_t size, loff_t *pos)
2439 {
2440         struct amdgpu_device *adev = file_inode(f)->i_private;
2441         struct iommu_domain *dom;
2442         ssize_t result = 0;
2443         int r;
2444
2445         dom = iommu_get_domain_for_dev(adev->dev);
2446
2447         while (size) {
2448                 phys_addr_t addr = *pos & PAGE_MASK;
2449                 loff_t off = *pos & ~PAGE_MASK;
2450                 size_t bytes = PAGE_SIZE - off;
2451                 unsigned long pfn;
2452                 struct page *p;
2453                 void *ptr;
2454
2455                 bytes = bytes < size ? bytes : size;
2456
2457                 addr = dom ? iommu_iova_to_phys(dom, addr) : addr;
2458
2459                 pfn = addr >> PAGE_SHIFT;
2460                 if (!pfn_valid(pfn))
2461                         return -EPERM;
2462
2463                 p = pfn_to_page(pfn);
2464                 if (p->mapping != adev->mman.bdev.dev_mapping)
2465                         return -EPERM;
2466
2467                 ptr = kmap(p);
2468                 r = copy_from_user(ptr + off, buf, bytes);
2469                 kunmap(p);
2470                 if (r)
2471                         return -EFAULT;
2472
2473                 size -= bytes;
2474                 *pos += bytes;
2475                 result += bytes;
2476         }
2477
2478         return result;
2479 }
2480
2481 static const struct file_operations amdgpu_ttm_iomem_fops = {
2482         .owner = THIS_MODULE,
2483         .read = amdgpu_iomem_read,
2484         .write = amdgpu_iomem_write,
2485         .llseek = default_llseek
2486 };
2487
2488 static const struct {
2489         char *name;
2490         const struct file_operations *fops;
2491         int domain;
2492 } ttm_debugfs_entries[] = {
2493         { "amdgpu_vram", &amdgpu_ttm_vram_fops, TTM_PL_VRAM },
2494 #ifdef CONFIG_DRM_AMDGPU_GART_DEBUGFS
2495         { "amdgpu_gtt", &amdgpu_ttm_gtt_fops, TTM_PL_TT },
2496 #endif
2497         { "amdgpu_iomem", &amdgpu_ttm_iomem_fops, TTM_PL_SYSTEM },
2498 };
2499
2500 #endif
2501
2502 int amdgpu_ttm_debugfs_init(struct amdgpu_device *adev)
2503 {
2504 #if defined(CONFIG_DEBUG_FS)
2505         unsigned count;
2506
2507         struct drm_minor *minor = adev_to_drm(adev)->primary;
2508         struct dentry *ent, *root = minor->debugfs_root;
2509
2510         for (count = 0; count < ARRAY_SIZE(ttm_debugfs_entries); count++) {
2511                 ent = debugfs_create_file(
2512                                 ttm_debugfs_entries[count].name,
2513                                 S_IFREG | S_IRUGO, root,
2514                                 adev,
2515                                 ttm_debugfs_entries[count].fops);
2516                 if (IS_ERR(ent))
2517                         return PTR_ERR(ent);
2518                 if (ttm_debugfs_entries[count].domain == TTM_PL_VRAM)
2519                         i_size_write(ent->d_inode, adev->gmc.mc_vram_size);
2520                 else if (ttm_debugfs_entries[count].domain == TTM_PL_TT)
2521                         i_size_write(ent->d_inode, adev->gmc.gart_size);
2522                 adev->mman.debugfs_entries[count] = ent;
2523         }
2524
2525         count = ARRAY_SIZE(amdgpu_ttm_debugfs_list);
2526         return amdgpu_debugfs_add_files(adev, amdgpu_ttm_debugfs_list, count);
2527 #else
2528         return 0;
2529 #endif
2530 }