2 * Copyright 2009 Jerome Glisse.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the
7 * "Software"), to deal in the Software without restriction, including
8 * without limitation the rights to use, copy, modify, merge, publish,
9 * distribute, sub license, and/or sell copies of the Software, and to
10 * permit persons to whom the Software is furnished to do so, subject to
11 * the following conditions:
13 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
14 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
15 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
16 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
17 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
18 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
19 * USE OR OTHER DEALINGS IN THE SOFTWARE.
21 * The above copyright notice and this permission notice (including the
22 * next paragraph) shall be included in all copies or substantial portions
28 * Jerome Glisse <glisse@freedesktop.org>
29 * Thomas Hellstrom <thomas-at-tungstengraphics-dot-com>
33 #include <linux/dma-mapping.h>
34 #include <linux/iommu.h>
35 #include <linux/pagemap.h>
36 #include <linux/sched/task.h>
37 #include <linux/sched/mm.h>
38 #include <linux/seq_file.h>
39 #include <linux/slab.h>
40 #include <linux/swap.h>
41 #include <linux/swiotlb.h>
42 #include <linux/dma-buf.h>
43 #include <linux/sizes.h>
45 #include <drm/ttm/ttm_bo_api.h>
46 #include <drm/ttm/ttm_bo_driver.h>
47 #include <drm/ttm/ttm_placement.h>
48 #include <drm/ttm/ttm_range_manager.h>
50 #include <drm/amdgpu_drm.h>
53 #include "amdgpu_object.h"
54 #include "amdgpu_trace.h"
55 #include "amdgpu_amdkfd.h"
56 #include "amdgpu_sdma.h"
57 #include "amdgpu_ras.h"
58 #include "amdgpu_atomfirmware.h"
59 #include "amdgpu_res_cursor.h"
60 #include "bif/bif_4_1_d.h"
62 #define AMDGPU_TTM_VRAM_MAX_DW_READ (size_t)128
64 static int amdgpu_ttm_backend_bind(struct ttm_device *bdev,
66 struct ttm_resource *bo_mem);
67 static void amdgpu_ttm_backend_unbind(struct ttm_device *bdev,
70 static int amdgpu_ttm_init_on_chip(struct amdgpu_device *adev,
72 uint64_t size_in_page)
74 return ttm_range_man_init(&adev->mman.bdev, type,
79 * amdgpu_evict_flags - Compute placement flags
81 * @bo: The buffer object to evict
82 * @placement: Possible destination(s) for evicted BO
84 * Fill in placement data when ttm_bo_evict() is called
86 static void amdgpu_evict_flags(struct ttm_buffer_object *bo,
87 struct ttm_placement *placement)
89 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev);
90 struct amdgpu_bo *abo;
91 static const struct ttm_place placements = {
94 .mem_type = TTM_PL_SYSTEM,
98 /* Don't handle scatter gather BOs */
99 if (bo->type == ttm_bo_type_sg) {
100 placement->num_placement = 0;
101 placement->num_busy_placement = 0;
105 /* Object isn't an AMDGPU object so ignore */
106 if (!amdgpu_bo_is_amdgpu_bo(bo)) {
107 placement->placement = &placements;
108 placement->busy_placement = &placements;
109 placement->num_placement = 1;
110 placement->num_busy_placement = 1;
114 abo = ttm_to_amdgpu_bo(bo);
115 if (abo->flags & AMDGPU_AMDKFD_CREATE_SVM_BO) {
116 struct dma_fence *fence;
117 struct dma_resv *resv = &bo->base._resv;
120 fence = rcu_dereference(resv->fence_excl);
121 if (fence && !fence->ops->signaled)
122 dma_fence_enable_sw_signaling(fence);
124 placement->num_placement = 0;
125 placement->num_busy_placement = 0;
130 switch (bo->resource->mem_type) {
134 placement->num_placement = 0;
135 placement->num_busy_placement = 0;
139 if (!adev->mman.buffer_funcs_enabled) {
140 /* Move to system memory */
141 amdgpu_bo_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_CPU);
142 } else if (!amdgpu_gmc_vram_full_visible(&adev->gmc) &&
143 !(abo->flags & AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED) &&
144 amdgpu_bo_in_cpu_visible_vram(abo)) {
146 /* Try evicting to the CPU inaccessible part of VRAM
147 * first, but only set GTT as busy placement, so this
148 * BO will be evicted to GTT rather than causing other
149 * BOs to be evicted from VRAM
151 amdgpu_bo_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_VRAM |
152 AMDGPU_GEM_DOMAIN_GTT |
153 AMDGPU_GEM_DOMAIN_CPU);
154 abo->placements[0].fpfn = adev->gmc.visible_vram_size >> PAGE_SHIFT;
155 abo->placements[0].lpfn = 0;
156 abo->placement.busy_placement = &abo->placements[1];
157 abo->placement.num_busy_placement = 1;
159 /* Move to GTT memory */
160 amdgpu_bo_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_GTT |
161 AMDGPU_GEM_DOMAIN_CPU);
165 case AMDGPU_PL_PREEMPT:
167 amdgpu_bo_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_CPU);
170 *placement = abo->placement;
174 * amdgpu_ttm_map_buffer - Map memory into the GART windows
175 * @bo: buffer object to map
176 * @mem: memory object to map
177 * @mm_cur: range to map
178 * @num_pages: number of pages to map
179 * @window: which GART window to use
180 * @ring: DMA ring to use for the copy
181 * @tmz: if we should setup a TMZ enabled mapping
182 * @addr: resulting address inside the MC address space
184 * Setup one of the GART windows to access a specific piece of memory or return
185 * the physical address for local memory.
187 static int amdgpu_ttm_map_buffer(struct ttm_buffer_object *bo,
188 struct ttm_resource *mem,
189 struct amdgpu_res_cursor *mm_cur,
190 unsigned num_pages, unsigned window,
191 struct amdgpu_ring *ring, bool tmz,
194 struct amdgpu_device *adev = ring->adev;
195 struct amdgpu_job *job;
196 unsigned num_dw, num_bytes;
197 struct dma_fence *fence;
198 uint64_t src_addr, dst_addr;
204 BUG_ON(adev->mman.buffer_funcs->copy_max_bytes <
205 AMDGPU_GTT_MAX_TRANSFER_SIZE * 8);
206 BUG_ON(mem->mem_type == AMDGPU_PL_PREEMPT);
208 /* Map only what can't be accessed directly */
209 if (!tmz && mem->start != AMDGPU_BO_INVALID_OFFSET) {
210 *addr = amdgpu_ttm_domain_start(adev, mem->mem_type) +
215 *addr = adev->gmc.gart_start;
216 *addr += (u64)window * AMDGPU_GTT_MAX_TRANSFER_SIZE *
217 AMDGPU_GPU_PAGE_SIZE;
218 *addr += mm_cur->start & ~PAGE_MASK;
220 num_dw = ALIGN(adev->mman.buffer_funcs->copy_num_dw, 8);
221 num_bytes = num_pages * 8 * AMDGPU_GPU_PAGES_IN_CPU_PAGE;
223 r = amdgpu_job_alloc_with_ib(adev, num_dw * 4 + num_bytes,
224 AMDGPU_IB_POOL_DELAYED, &job);
228 src_addr = num_dw * 4;
229 src_addr += job->ibs[0].gpu_addr;
231 dst_addr = amdgpu_bo_gpu_offset(adev->gart.bo);
232 dst_addr += window * AMDGPU_GTT_MAX_TRANSFER_SIZE * 8;
233 amdgpu_emit_copy_buffer(adev, &job->ibs[0], src_addr,
234 dst_addr, num_bytes, false);
236 amdgpu_ring_pad_ib(ring, &job->ibs[0]);
237 WARN_ON(job->ibs[0].length_dw > num_dw);
239 flags = amdgpu_ttm_tt_pte_flags(adev, bo->ttm, mem);
241 flags |= AMDGPU_PTE_TMZ;
243 cpu_addr = &job->ibs[0].ptr[num_dw];
245 if (mem->mem_type == TTM_PL_TT) {
246 dma_addr_t *dma_addr;
248 dma_addr = &bo->ttm->dma_address[mm_cur->start >> PAGE_SHIFT];
249 r = amdgpu_gart_map(adev, 0, num_pages, dma_addr, flags,
254 dma_addr_t dma_address;
256 dma_address = mm_cur->start;
257 dma_address += adev->vm_manager.vram_base_offset;
259 for (i = 0; i < num_pages; ++i) {
260 r = amdgpu_gart_map(adev, i << PAGE_SHIFT, 1,
261 &dma_address, flags, cpu_addr);
265 dma_address += PAGE_SIZE;
269 r = amdgpu_job_submit(job, &adev->mman.entity,
270 AMDGPU_FENCE_OWNER_UNDEFINED, &fence);
274 dma_fence_put(fence);
279 amdgpu_job_free(job);
284 * amdgpu_ttm_copy_mem_to_mem - Helper function for copy
285 * @adev: amdgpu device
286 * @src: buffer/address where to read from
287 * @dst: buffer/address where to write to
288 * @size: number of bytes to copy
289 * @tmz: if a secure copy should be used
290 * @resv: resv object to sync to
291 * @f: Returns the last fence if multiple jobs are submitted.
293 * The function copies @size bytes from {src->mem + src->offset} to
294 * {dst->mem + dst->offset}. src->bo and dst->bo could be same BO for a
295 * move and different for a BO to BO copy.
298 int amdgpu_ttm_copy_mem_to_mem(struct amdgpu_device *adev,
299 const struct amdgpu_copy_mem *src,
300 const struct amdgpu_copy_mem *dst,
301 uint64_t size, bool tmz,
302 struct dma_resv *resv,
303 struct dma_fence **f)
305 const uint32_t GTT_MAX_BYTES = (AMDGPU_GTT_MAX_TRANSFER_SIZE *
306 AMDGPU_GPU_PAGE_SIZE);
308 struct amdgpu_ring *ring = adev->mman.buffer_funcs_ring;
309 struct amdgpu_res_cursor src_mm, dst_mm;
310 struct dma_fence *fence = NULL;
313 if (!adev->mman.buffer_funcs_enabled) {
314 DRM_ERROR("Trying to move memory with ring turned off.\n");
318 amdgpu_res_first(src->mem, src->offset, size, &src_mm);
319 amdgpu_res_first(dst->mem, dst->offset, size, &dst_mm);
321 mutex_lock(&adev->mman.gtt_window_lock);
322 while (src_mm.remaining) {
323 uint32_t src_page_offset = src_mm.start & ~PAGE_MASK;
324 uint32_t dst_page_offset = dst_mm.start & ~PAGE_MASK;
325 struct dma_fence *next;
329 /* Copy size cannot exceed GTT_MAX_BYTES. So if src or dst
330 * begins at an offset, then adjust the size accordingly
332 cur_size = max(src_page_offset, dst_page_offset);
333 cur_size = min(min3(src_mm.size, dst_mm.size, size),
334 (uint64_t)(GTT_MAX_BYTES - cur_size));
336 /* Map src to window 0 and dst to window 1. */
337 r = amdgpu_ttm_map_buffer(src->bo, src->mem, &src_mm,
338 PFN_UP(cur_size + src_page_offset),
339 0, ring, tmz, &from);
343 r = amdgpu_ttm_map_buffer(dst->bo, dst->mem, &dst_mm,
344 PFN_UP(cur_size + dst_page_offset),
349 r = amdgpu_copy_buffer(ring, from, to, cur_size,
350 resv, &next, false, true, tmz);
354 dma_fence_put(fence);
357 amdgpu_res_next(&src_mm, cur_size);
358 amdgpu_res_next(&dst_mm, cur_size);
361 mutex_unlock(&adev->mman.gtt_window_lock);
363 *f = dma_fence_get(fence);
364 dma_fence_put(fence);
369 * amdgpu_move_blit - Copy an entire buffer to another buffer
371 * This is a helper called by amdgpu_bo_move() and amdgpu_move_vram_ram() to
372 * help move buffers to and from VRAM.
374 static int amdgpu_move_blit(struct ttm_buffer_object *bo,
376 struct ttm_resource *new_mem,
377 struct ttm_resource *old_mem)
379 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev);
380 struct amdgpu_bo *abo = ttm_to_amdgpu_bo(bo);
381 struct amdgpu_copy_mem src, dst;
382 struct dma_fence *fence = NULL;
392 r = amdgpu_ttm_copy_mem_to_mem(adev, &src, &dst,
393 new_mem->num_pages << PAGE_SHIFT,
394 amdgpu_bo_encrypted(abo),
395 bo->base.resv, &fence);
399 /* clear the space being freed */
400 if (old_mem->mem_type == TTM_PL_VRAM &&
401 (abo->flags & AMDGPU_GEM_CREATE_VRAM_WIPE_ON_RELEASE)) {
402 struct dma_fence *wipe_fence = NULL;
404 r = amdgpu_fill_buffer(ttm_to_amdgpu_bo(bo), AMDGPU_POISON,
408 } else if (wipe_fence) {
409 dma_fence_put(fence);
414 /* Always block for VM page tables before committing the new location */
415 if (bo->type == ttm_bo_type_kernel)
416 r = ttm_bo_move_accel_cleanup(bo, fence, true, false, new_mem);
418 r = ttm_bo_move_accel_cleanup(bo, fence, evict, true, new_mem);
419 dma_fence_put(fence);
424 dma_fence_wait(fence, false);
425 dma_fence_put(fence);
430 * amdgpu_mem_visible - Check that memory can be accessed by ttm_bo_move_memcpy
432 * Called by amdgpu_bo_move()
434 static bool amdgpu_mem_visible(struct amdgpu_device *adev,
435 struct ttm_resource *mem)
437 uint64_t mem_size = (u64)mem->num_pages << PAGE_SHIFT;
438 struct amdgpu_res_cursor cursor;
440 if (mem->mem_type == TTM_PL_SYSTEM ||
441 mem->mem_type == TTM_PL_TT)
443 if (mem->mem_type != TTM_PL_VRAM)
446 amdgpu_res_first(mem, 0, mem_size, &cursor);
448 /* ttm_resource_ioremap only supports contiguous memory */
449 if (cursor.size != mem_size)
452 return cursor.start + cursor.size <= adev->gmc.visible_vram_size;
456 * amdgpu_bo_move - Move a buffer object to a new memory location
458 * Called by ttm_bo_handle_move_mem()
460 static int amdgpu_bo_move(struct ttm_buffer_object *bo, bool evict,
461 struct ttm_operation_ctx *ctx,
462 struct ttm_resource *new_mem,
463 struct ttm_place *hop)
465 struct amdgpu_device *adev;
466 struct amdgpu_bo *abo;
467 struct ttm_resource *old_mem = bo->resource;
470 if (new_mem->mem_type == TTM_PL_TT ||
471 new_mem->mem_type == AMDGPU_PL_PREEMPT) {
472 r = amdgpu_ttm_backend_bind(bo->bdev, bo->ttm, new_mem);
477 /* Can't move a pinned BO */
478 abo = ttm_to_amdgpu_bo(bo);
479 if (WARN_ON_ONCE(abo->tbo.pin_count > 0))
482 adev = amdgpu_ttm_adev(bo->bdev);
484 if (old_mem->mem_type == TTM_PL_SYSTEM && bo->ttm == NULL) {
485 ttm_bo_move_null(bo, new_mem);
488 if (old_mem->mem_type == TTM_PL_SYSTEM &&
489 (new_mem->mem_type == TTM_PL_TT ||
490 new_mem->mem_type == AMDGPU_PL_PREEMPT)) {
491 ttm_bo_move_null(bo, new_mem);
494 if ((old_mem->mem_type == TTM_PL_TT ||
495 old_mem->mem_type == AMDGPU_PL_PREEMPT) &&
496 new_mem->mem_type == TTM_PL_SYSTEM) {
497 r = ttm_bo_wait_ctx(bo, ctx);
501 amdgpu_ttm_backend_unbind(bo->bdev, bo->ttm);
502 ttm_resource_free(bo, &bo->resource);
503 ttm_bo_assign_mem(bo, new_mem);
507 if (old_mem->mem_type == AMDGPU_PL_GDS ||
508 old_mem->mem_type == AMDGPU_PL_GWS ||
509 old_mem->mem_type == AMDGPU_PL_OA ||
510 new_mem->mem_type == AMDGPU_PL_GDS ||
511 new_mem->mem_type == AMDGPU_PL_GWS ||
512 new_mem->mem_type == AMDGPU_PL_OA) {
513 /* Nothing to save here */
514 ttm_bo_move_null(bo, new_mem);
518 if (bo->type == ttm_bo_type_device &&
519 new_mem->mem_type == TTM_PL_VRAM &&
520 old_mem->mem_type != TTM_PL_VRAM) {
521 /* amdgpu_bo_fault_reserve_notify will re-set this if the CPU
522 * accesses the BO after it's moved.
524 abo->flags &= ~AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED;
527 if (adev->mman.buffer_funcs_enabled) {
528 if (((old_mem->mem_type == TTM_PL_SYSTEM &&
529 new_mem->mem_type == TTM_PL_VRAM) ||
530 (old_mem->mem_type == TTM_PL_VRAM &&
531 new_mem->mem_type == TTM_PL_SYSTEM))) {
534 hop->mem_type = TTM_PL_TT;
535 hop->flags = TTM_PL_FLAG_TEMPORARY;
539 r = amdgpu_move_blit(bo, evict, new_mem, old_mem);
545 /* Check that all memory is CPU accessible */
546 if (!amdgpu_mem_visible(adev, old_mem) ||
547 !amdgpu_mem_visible(adev, new_mem)) {
548 pr_err("Move buffer fallback to memcpy unavailable\n");
552 r = ttm_bo_move_memcpy(bo, ctx, new_mem);
558 /* update statistics */
559 atomic64_add(bo->base.size, &adev->num_bytes_moved);
560 amdgpu_bo_move_notify(bo, evict, new_mem);
565 * amdgpu_ttm_io_mem_reserve - Reserve a block of memory during a fault
567 * Called by ttm_mem_io_reserve() ultimately via ttm_bo_vm_fault()
569 static int amdgpu_ttm_io_mem_reserve(struct ttm_device *bdev,
570 struct ttm_resource *mem)
572 struct amdgpu_device *adev = amdgpu_ttm_adev(bdev);
573 size_t bus_size = (size_t)mem->num_pages << PAGE_SHIFT;
575 switch (mem->mem_type) {
580 case AMDGPU_PL_PREEMPT:
583 mem->bus.offset = mem->start << PAGE_SHIFT;
584 /* check if it's visible */
585 if ((mem->bus.offset + bus_size) > adev->gmc.visible_vram_size)
588 if (adev->mman.aper_base_kaddr &&
589 mem->placement & TTM_PL_FLAG_CONTIGUOUS)
590 mem->bus.addr = (u8 *)adev->mman.aper_base_kaddr +
593 mem->bus.offset += adev->gmc.aper_base;
594 mem->bus.is_iomem = true;
602 static unsigned long amdgpu_ttm_io_mem_pfn(struct ttm_buffer_object *bo,
603 unsigned long page_offset)
605 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev);
606 struct amdgpu_res_cursor cursor;
608 amdgpu_res_first(bo->resource, (u64)page_offset << PAGE_SHIFT, 0,
610 return (adev->gmc.aper_base + cursor.start) >> PAGE_SHIFT;
614 * amdgpu_ttm_domain_start - Returns GPU start address
615 * @adev: amdgpu device object
616 * @type: type of the memory
619 * GPU start address of a memory domain
622 uint64_t amdgpu_ttm_domain_start(struct amdgpu_device *adev, uint32_t type)
626 return adev->gmc.gart_start;
628 return adev->gmc.vram_start;
635 * TTM backend functions.
637 struct amdgpu_ttm_tt {
639 struct drm_gem_object *gobj;
642 struct task_struct *usertask;
645 #if IS_ENABLED(CONFIG_DRM_AMDGPU_USERPTR)
646 struct hmm_range *range;
650 #ifdef CONFIG_DRM_AMDGPU_USERPTR
652 * amdgpu_ttm_tt_get_user_pages - get device accessible pages that back user
653 * memory and start HMM tracking CPU page table update
655 * Calling function must call amdgpu_ttm_tt_userptr_range_done() once and only
656 * once afterwards to stop HMM tracking
658 int amdgpu_ttm_tt_get_user_pages(struct amdgpu_bo *bo, struct page **pages)
660 struct ttm_tt *ttm = bo->tbo.ttm;
661 struct amdgpu_ttm_tt *gtt = (void *)ttm;
662 unsigned long start = gtt->userptr;
663 struct vm_area_struct *vma;
664 struct mm_struct *mm;
668 mm = bo->notifier.mm;
670 DRM_DEBUG_DRIVER("BO is not registered?\n");
674 /* Another get_user_pages is running at the same time?? */
675 if (WARN_ON(gtt->range))
678 if (!mmget_not_zero(mm)) /* Happens during process shutdown */
682 vma = vma_lookup(mm, start);
683 if (unlikely(!vma)) {
687 if (unlikely((gtt->userflags & AMDGPU_GEM_USERPTR_ANONONLY) &&
693 readonly = amdgpu_ttm_tt_is_readonly(ttm);
694 r = amdgpu_hmm_range_get_pages(&bo->notifier, mm, pages, start,
695 ttm->num_pages, >t->range, readonly,
698 mmap_read_unlock(mm);
705 * amdgpu_ttm_tt_userptr_range_done - stop HMM track the CPU page table change
706 * Check if the pages backing this ttm range have been invalidated
708 * Returns: true if pages are still valid
710 bool amdgpu_ttm_tt_get_user_pages_done(struct ttm_tt *ttm)
712 struct amdgpu_ttm_tt *gtt = (void *)ttm;
715 if (!gtt || !gtt->userptr)
718 DRM_DEBUG_DRIVER("user_pages_done 0x%llx pages 0x%x\n",
719 gtt->userptr, ttm->num_pages);
721 WARN_ONCE(!gtt->range || !gtt->range->hmm_pfns,
722 "No user pages to check\n");
726 * FIXME: Must always hold notifier_lock for this, and must
727 * not ignore the return code.
729 r = amdgpu_hmm_range_get_pages_done(gtt->range);
738 * amdgpu_ttm_tt_set_user_pages - Copy pages in, putting old pages as necessary.
740 * Called by amdgpu_cs_list_validate(). This creates the page list
741 * that backs user memory and will ultimately be mapped into the device
744 void amdgpu_ttm_tt_set_user_pages(struct ttm_tt *ttm, struct page **pages)
748 for (i = 0; i < ttm->num_pages; ++i)
749 ttm->pages[i] = pages ? pages[i] : NULL;
753 * amdgpu_ttm_tt_pin_userptr - prepare the sg table with the user pages
755 * Called by amdgpu_ttm_backend_bind()
757 static int amdgpu_ttm_tt_pin_userptr(struct ttm_device *bdev,
760 struct amdgpu_device *adev = amdgpu_ttm_adev(bdev);
761 struct amdgpu_ttm_tt *gtt = (void *)ttm;
762 int write = !(gtt->userflags & AMDGPU_GEM_USERPTR_READONLY);
763 enum dma_data_direction direction = write ?
764 DMA_BIDIRECTIONAL : DMA_TO_DEVICE;
767 /* Allocate an SG array and squash pages into it */
768 r = sg_alloc_table_from_pages(ttm->sg, ttm->pages, ttm->num_pages, 0,
769 (u64)ttm->num_pages << PAGE_SHIFT,
774 /* Map SG to device */
775 r = dma_map_sgtable(adev->dev, ttm->sg, direction, 0);
779 /* convert SG to linear array of pages and dma addresses */
780 drm_prime_sg_to_dma_addr_array(ttm->sg, gtt->ttm.dma_address,
792 * amdgpu_ttm_tt_unpin_userptr - Unpin and unmap userptr pages
794 static void amdgpu_ttm_tt_unpin_userptr(struct ttm_device *bdev,
797 struct amdgpu_device *adev = amdgpu_ttm_adev(bdev);
798 struct amdgpu_ttm_tt *gtt = (void *)ttm;
799 int write = !(gtt->userflags & AMDGPU_GEM_USERPTR_READONLY);
800 enum dma_data_direction direction = write ?
801 DMA_BIDIRECTIONAL : DMA_TO_DEVICE;
803 /* double check that we don't free the table twice */
804 if (!ttm->sg || !ttm->sg->sgl)
807 /* unmap the pages mapped to the device */
808 dma_unmap_sgtable(adev->dev, ttm->sg, direction, 0);
809 sg_free_table(ttm->sg);
811 #if IS_ENABLED(CONFIG_DRM_AMDGPU_USERPTR)
815 for (i = 0; i < ttm->num_pages; i++) {
817 hmm_pfn_to_page(gtt->range->hmm_pfns[i]))
821 WARN((i == ttm->num_pages), "Missing get_user_page_done\n");
826 static int amdgpu_ttm_gart_bind(struct amdgpu_device *adev,
827 struct ttm_buffer_object *tbo,
830 struct amdgpu_bo *abo = ttm_to_amdgpu_bo(tbo);
831 struct ttm_tt *ttm = tbo->ttm;
832 struct amdgpu_ttm_tt *gtt = (void *)ttm;
835 if (amdgpu_bo_encrypted(abo))
836 flags |= AMDGPU_PTE_TMZ;
838 if (abo->flags & AMDGPU_GEM_CREATE_CP_MQD_GFX9) {
839 uint64_t page_idx = 1;
841 r = amdgpu_gart_bind(adev, gtt->offset, page_idx,
842 gtt->ttm.dma_address, flags);
846 /* The memory type of the first page defaults to UC. Now
847 * modify the memory type to NC from the second page of
850 flags &= ~AMDGPU_PTE_MTYPE_VG10_MASK;
851 flags |= AMDGPU_PTE_MTYPE_VG10(AMDGPU_MTYPE_NC);
853 r = amdgpu_gart_bind(adev,
854 gtt->offset + (page_idx << PAGE_SHIFT),
855 ttm->num_pages - page_idx,
856 &(gtt->ttm.dma_address[page_idx]), flags);
858 r = amdgpu_gart_bind(adev, gtt->offset, ttm->num_pages,
859 gtt->ttm.dma_address, flags);
864 DRM_ERROR("failed to bind %u pages at 0x%08llX\n",
865 ttm->num_pages, gtt->offset);
871 * amdgpu_ttm_backend_bind - Bind GTT memory
873 * Called by ttm_tt_bind() on behalf of ttm_bo_handle_move_mem().
874 * This handles binding GTT memory to the device address space.
876 static int amdgpu_ttm_backend_bind(struct ttm_device *bdev,
878 struct ttm_resource *bo_mem)
880 struct amdgpu_device *adev = amdgpu_ttm_adev(bdev);
881 struct amdgpu_ttm_tt *gtt = (void*)ttm;
892 r = amdgpu_ttm_tt_pin_userptr(bdev, ttm);
894 DRM_ERROR("failed to pin userptr\n");
897 } else if (ttm->page_flags & TTM_PAGE_FLAG_SG) {
899 struct dma_buf_attachment *attach;
900 struct sg_table *sgt;
902 attach = gtt->gobj->import_attach;
903 sgt = dma_buf_map_attachment(attach, DMA_BIDIRECTIONAL);
910 drm_prime_sg_to_dma_addr_array(ttm->sg, gtt->ttm.dma_address,
914 if (!ttm->num_pages) {
915 WARN(1, "nothing to bind %u pages for mreg %p back %p!\n",
916 ttm->num_pages, bo_mem, ttm);
919 if (bo_mem->mem_type == AMDGPU_PL_GDS ||
920 bo_mem->mem_type == AMDGPU_PL_GWS ||
921 bo_mem->mem_type == AMDGPU_PL_OA)
924 if (bo_mem->mem_type != TTM_PL_TT ||
925 !amdgpu_gtt_mgr_has_gart_addr(bo_mem)) {
926 gtt->offset = AMDGPU_BO_INVALID_OFFSET;
930 /* compute PTE flags relevant to this BO memory */
931 flags = amdgpu_ttm_tt_pte_flags(adev, ttm, bo_mem);
933 /* bind pages into GART page tables */
934 gtt->offset = (u64)bo_mem->start << PAGE_SHIFT;
935 r = amdgpu_gart_bind(adev, gtt->offset, ttm->num_pages,
936 gtt->ttm.dma_address, flags);
939 DRM_ERROR("failed to bind %u pages at 0x%08llX\n",
940 ttm->num_pages, gtt->offset);
946 * amdgpu_ttm_alloc_gart - Make sure buffer object is accessible either
947 * through AGP or GART aperture.
949 * If bo is accessible through AGP aperture, then use AGP aperture
950 * to access bo; otherwise allocate logical space in GART aperture
951 * and map bo to GART aperture.
953 int amdgpu_ttm_alloc_gart(struct ttm_buffer_object *bo)
955 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev);
956 struct ttm_operation_ctx ctx = { false, false };
957 struct amdgpu_ttm_tt *gtt = (void *)bo->ttm;
958 struct ttm_placement placement;
959 struct ttm_place placements;
960 struct ttm_resource *tmp;
961 uint64_t addr, flags;
964 if (bo->resource->start != AMDGPU_BO_INVALID_OFFSET)
967 addr = amdgpu_gmc_agp_addr(bo);
968 if (addr != AMDGPU_BO_INVALID_OFFSET) {
969 bo->resource->start = addr >> PAGE_SHIFT;
973 /* allocate GART space */
974 placement.num_placement = 1;
975 placement.placement = &placements;
976 placement.num_busy_placement = 1;
977 placement.busy_placement = &placements;
979 placements.lpfn = adev->gmc.gart_size >> PAGE_SHIFT;
980 placements.mem_type = TTM_PL_TT;
981 placements.flags = bo->resource->placement;
983 r = ttm_bo_mem_space(bo, &placement, &tmp, &ctx);
987 /* compute PTE flags for this buffer object */
988 flags = amdgpu_ttm_tt_pte_flags(adev, bo->ttm, tmp);
991 gtt->offset = (u64)tmp->start << PAGE_SHIFT;
992 r = amdgpu_ttm_gart_bind(adev, bo, flags);
994 ttm_resource_free(bo, &tmp);
998 amdgpu_gart_invalidate_tlb(adev);
999 ttm_resource_free(bo, &bo->resource);
1000 ttm_bo_assign_mem(bo, tmp);
1006 * amdgpu_ttm_recover_gart - Rebind GTT pages
1008 * Called by amdgpu_gtt_mgr_recover() from amdgpu_device_reset() to
1009 * rebind GTT pages during a GPU reset.
1011 int amdgpu_ttm_recover_gart(struct ttm_buffer_object *tbo)
1013 struct amdgpu_device *adev = amdgpu_ttm_adev(tbo->bdev);
1020 flags = amdgpu_ttm_tt_pte_flags(adev, tbo->ttm, tbo->resource);
1021 r = amdgpu_ttm_gart_bind(adev, tbo, flags);
1027 * amdgpu_ttm_backend_unbind - Unbind GTT mapped pages
1029 * Called by ttm_tt_unbind() on behalf of ttm_bo_move_ttm() and
1032 static void amdgpu_ttm_backend_unbind(struct ttm_device *bdev,
1035 struct amdgpu_device *adev = amdgpu_ttm_adev(bdev);
1036 struct amdgpu_ttm_tt *gtt = (void *)ttm;
1039 /* if the pages have userptr pinning then clear that first */
1041 amdgpu_ttm_tt_unpin_userptr(bdev, ttm);
1042 } else if (ttm->sg && gtt->gobj->import_attach) {
1043 struct dma_buf_attachment *attach;
1045 attach = gtt->gobj->import_attach;
1046 dma_buf_unmap_attachment(attach, ttm->sg, DMA_BIDIRECTIONAL);
1053 if (gtt->offset == AMDGPU_BO_INVALID_OFFSET)
1056 /* unbind shouldn't be done for GDS/GWS/OA in ttm_bo_clean_mm */
1057 r = amdgpu_gart_unbind(adev, gtt->offset, ttm->num_pages);
1059 DRM_ERROR("failed to unbind %u pages at 0x%08llX\n",
1060 gtt->ttm.num_pages, gtt->offset);
1064 static void amdgpu_ttm_backend_destroy(struct ttm_device *bdev,
1067 struct amdgpu_ttm_tt *gtt = (void *)ttm;
1069 amdgpu_ttm_backend_unbind(bdev, ttm);
1070 ttm_tt_destroy_common(bdev, ttm);
1072 put_task_struct(gtt->usertask);
1074 ttm_tt_fini(>t->ttm);
1079 * amdgpu_ttm_tt_create - Create a ttm_tt object for a given BO
1081 * @bo: The buffer object to create a GTT ttm_tt object around
1082 * @page_flags: Page flags to be added to the ttm_tt object
1084 * Called by ttm_tt_create().
1086 static struct ttm_tt *amdgpu_ttm_tt_create(struct ttm_buffer_object *bo,
1087 uint32_t page_flags)
1089 struct amdgpu_bo *abo = ttm_to_amdgpu_bo(bo);
1090 struct amdgpu_ttm_tt *gtt;
1091 enum ttm_caching caching;
1093 gtt = kzalloc(sizeof(struct amdgpu_ttm_tt), GFP_KERNEL);
1097 gtt->gobj = &bo->base;
1099 if (abo->flags & AMDGPU_GEM_CREATE_CPU_GTT_USWC)
1100 caching = ttm_write_combined;
1102 caching = ttm_cached;
1104 /* allocate space for the uninitialized page entries */
1105 if (ttm_sg_tt_init(>t->ttm, bo, page_flags, caching)) {
1113 * amdgpu_ttm_tt_populate - Map GTT pages visible to the device
1115 * Map the pages of a ttm_tt object to an address space visible
1116 * to the underlying device.
1118 static int amdgpu_ttm_tt_populate(struct ttm_device *bdev,
1120 struct ttm_operation_ctx *ctx)
1122 struct amdgpu_device *adev = amdgpu_ttm_adev(bdev);
1123 struct amdgpu_ttm_tt *gtt = (void *)ttm;
1125 /* user pages are bound by amdgpu_ttm_tt_pin_userptr() */
1127 ttm->sg = kzalloc(sizeof(struct sg_table), GFP_KERNEL);
1133 if (ttm->page_flags & TTM_PAGE_FLAG_SG)
1136 return ttm_pool_alloc(&adev->mman.bdev.pool, ttm, ctx);
1140 * amdgpu_ttm_tt_unpopulate - unmap GTT pages and unpopulate page arrays
1142 * Unmaps pages of a ttm_tt object from the device address space and
1143 * unpopulates the page array backing it.
1145 static void amdgpu_ttm_tt_unpopulate(struct ttm_device *bdev,
1148 struct amdgpu_ttm_tt *gtt = (void *)ttm;
1149 struct amdgpu_device *adev;
1152 amdgpu_ttm_tt_set_user_pages(ttm, NULL);
1158 if (ttm->page_flags & TTM_PAGE_FLAG_SG)
1161 adev = amdgpu_ttm_adev(bdev);
1162 return ttm_pool_free(&adev->mman.bdev.pool, ttm);
1166 * amdgpu_ttm_tt_set_userptr - Initialize userptr GTT ttm_tt for the current
1169 * @bo: The ttm_buffer_object to bind this userptr to
1170 * @addr: The address in the current tasks VM space to use
1171 * @flags: Requirements of userptr object.
1173 * Called by amdgpu_gem_userptr_ioctl() to bind userptr pages
1176 int amdgpu_ttm_tt_set_userptr(struct ttm_buffer_object *bo,
1177 uint64_t addr, uint32_t flags)
1179 struct amdgpu_ttm_tt *gtt;
1182 /* TODO: We want a separate TTM object type for userptrs */
1183 bo->ttm = amdgpu_ttm_tt_create(bo, 0);
1184 if (bo->ttm == NULL)
1188 /* Set TTM_PAGE_FLAG_SG before populate but after create. */
1189 bo->ttm->page_flags |= TTM_PAGE_FLAG_SG;
1191 gtt = (void *)bo->ttm;
1192 gtt->userptr = addr;
1193 gtt->userflags = flags;
1196 put_task_struct(gtt->usertask);
1197 gtt->usertask = current->group_leader;
1198 get_task_struct(gtt->usertask);
1204 * amdgpu_ttm_tt_get_usermm - Return memory manager for ttm_tt object
1206 struct mm_struct *amdgpu_ttm_tt_get_usermm(struct ttm_tt *ttm)
1208 struct amdgpu_ttm_tt *gtt = (void *)ttm;
1213 if (gtt->usertask == NULL)
1216 return gtt->usertask->mm;
1220 * amdgpu_ttm_tt_affect_userptr - Determine if a ttm_tt object lays inside an
1221 * address range for the current task.
1224 bool amdgpu_ttm_tt_affect_userptr(struct ttm_tt *ttm, unsigned long start,
1227 struct amdgpu_ttm_tt *gtt = (void *)ttm;
1230 if (gtt == NULL || !gtt->userptr)
1233 /* Return false if no part of the ttm_tt object lies within
1236 size = (unsigned long)gtt->ttm.num_pages * PAGE_SIZE;
1237 if (gtt->userptr > end || gtt->userptr + size <= start)
1244 * amdgpu_ttm_tt_is_userptr - Have the pages backing by userptr?
1246 bool amdgpu_ttm_tt_is_userptr(struct ttm_tt *ttm)
1248 struct amdgpu_ttm_tt *gtt = (void *)ttm;
1250 if (gtt == NULL || !gtt->userptr)
1257 * amdgpu_ttm_tt_is_readonly - Is the ttm_tt object read only?
1259 bool amdgpu_ttm_tt_is_readonly(struct ttm_tt *ttm)
1261 struct amdgpu_ttm_tt *gtt = (void *)ttm;
1266 return !!(gtt->userflags & AMDGPU_GEM_USERPTR_READONLY);
1270 * amdgpu_ttm_tt_pde_flags - Compute PDE flags for ttm_tt object
1272 * @ttm: The ttm_tt object to compute the flags for
1273 * @mem: The memory registry backing this ttm_tt object
1275 * Figure out the flags to use for a VM PDE (Page Directory Entry).
1277 uint64_t amdgpu_ttm_tt_pde_flags(struct ttm_tt *ttm, struct ttm_resource *mem)
1281 if (mem && mem->mem_type != TTM_PL_SYSTEM)
1282 flags |= AMDGPU_PTE_VALID;
1284 if (mem && (mem->mem_type == TTM_PL_TT ||
1285 mem->mem_type == AMDGPU_PL_PREEMPT)) {
1286 flags |= AMDGPU_PTE_SYSTEM;
1288 if (ttm->caching == ttm_cached)
1289 flags |= AMDGPU_PTE_SNOOPED;
1292 if (mem && mem->mem_type == TTM_PL_VRAM &&
1293 mem->bus.caching == ttm_cached)
1294 flags |= AMDGPU_PTE_SNOOPED;
1300 * amdgpu_ttm_tt_pte_flags - Compute PTE flags for ttm_tt object
1302 * @adev: amdgpu_device pointer
1303 * @ttm: The ttm_tt object to compute the flags for
1304 * @mem: The memory registry backing this ttm_tt object
1306 * Figure out the flags to use for a VM PTE (Page Table Entry).
1308 uint64_t amdgpu_ttm_tt_pte_flags(struct amdgpu_device *adev, struct ttm_tt *ttm,
1309 struct ttm_resource *mem)
1311 uint64_t flags = amdgpu_ttm_tt_pde_flags(ttm, mem);
1313 flags |= adev->gart.gart_pte_flags;
1314 flags |= AMDGPU_PTE_READABLE;
1316 if (!amdgpu_ttm_tt_is_readonly(ttm))
1317 flags |= AMDGPU_PTE_WRITEABLE;
1323 * amdgpu_ttm_bo_eviction_valuable - Check to see if we can evict a buffer
1326 * Return true if eviction is sensible. Called by ttm_mem_evict_first() on
1327 * behalf of ttm_bo_mem_force_space() which tries to evict buffer objects until
1328 * it can find space for a new object and by ttm_bo_force_list_clean() which is
1329 * used to clean out a memory space.
1331 static bool amdgpu_ttm_bo_eviction_valuable(struct ttm_buffer_object *bo,
1332 const struct ttm_place *place)
1334 unsigned long num_pages = bo->resource->num_pages;
1335 struct amdgpu_res_cursor cursor;
1336 struct dma_resv_list *flist;
1337 struct dma_fence *f;
1341 if (bo->resource->mem_type == TTM_PL_SYSTEM)
1344 if (bo->type == ttm_bo_type_kernel &&
1345 !amdgpu_vm_evictable(ttm_to_amdgpu_bo(bo)))
1348 /* If bo is a KFD BO, check if the bo belongs to the current process.
1349 * If true, then return false as any KFD process needs all its BOs to
1350 * be resident to run successfully
1352 flist = dma_resv_shared_list(bo->base.resv);
1354 for (i = 0; i < flist->shared_count; ++i) {
1355 f = rcu_dereference_protected(flist->shared[i],
1356 dma_resv_held(bo->base.resv));
1357 if (amdkfd_fence_check_mm(f, current->mm))
1362 switch (bo->resource->mem_type) {
1363 case AMDGPU_PL_PREEMPT:
1364 /* Preemptible BOs don't own system resources managed by the
1365 * driver (pages, VRAM, GART space). They point to resources
1366 * owned by someone else (e.g. pageable memory in user mode
1367 * or a DMABuf). They are used in a preemptible context so we
1368 * can guarantee no deadlocks and good QoS in case of MMU
1369 * notifiers or DMABuf move notifiers from the resource owner.
1373 if (amdgpu_bo_is_amdgpu_bo(bo) &&
1374 amdgpu_bo_encrypted(ttm_to_amdgpu_bo(bo)))
1379 /* Check each drm MM node individually */
1380 amdgpu_res_first(bo->resource, 0, (u64)num_pages << PAGE_SHIFT,
1382 while (cursor.remaining) {
1383 if (place->fpfn < PFN_DOWN(cursor.start + cursor.size)
1385 place->lpfn <= PFN_DOWN(cursor.start)))
1388 amdgpu_res_next(&cursor, cursor.size);
1396 return ttm_bo_eviction_valuable(bo, place);
1399 static void amdgpu_ttm_vram_mm_access(struct amdgpu_device *adev, loff_t pos,
1400 void *buf, size_t size, bool write)
1403 uint64_t aligned_pos = ALIGN_DOWN(pos, 4);
1404 uint64_t bytes = 4 - (pos & 0x3);
1405 uint32_t shift = (pos & 0x3) * 8;
1406 uint32_t mask = 0xffffffff << shift;
1410 mask &= 0xffffffff >> (bytes - size) * 8;
1414 if (mask != 0xffffffff) {
1415 amdgpu_device_mm_access(adev, aligned_pos, &value, 4, false);
1418 value |= (*(uint32_t *)buf << shift) & mask;
1419 amdgpu_device_mm_access(adev, aligned_pos, &value, 4, true);
1421 value = (value & mask) >> shift;
1422 memcpy(buf, &value, bytes);
1425 amdgpu_device_mm_access(adev, aligned_pos, buf, 4, write);
1435 * amdgpu_ttm_access_memory - Read or Write memory that backs a buffer object.
1437 * @bo: The buffer object to read/write
1438 * @offset: Offset into buffer object
1439 * @buf: Secondary buffer to write/read from
1440 * @len: Length in bytes of access
1441 * @write: true if writing
1443 * This is used to access VRAM that backs a buffer object via MMIO
1444 * access for debugging purposes.
1446 static int amdgpu_ttm_access_memory(struct ttm_buffer_object *bo,
1447 unsigned long offset, void *buf, int len,
1450 struct amdgpu_bo *abo = ttm_to_amdgpu_bo(bo);
1451 struct amdgpu_device *adev = amdgpu_ttm_adev(abo->tbo.bdev);
1452 struct amdgpu_res_cursor cursor;
1455 if (bo->resource->mem_type != TTM_PL_VRAM)
1458 amdgpu_res_first(bo->resource, offset, len, &cursor);
1459 while (cursor.remaining) {
1460 size_t count, size = cursor.size;
1461 loff_t pos = cursor.start;
1463 count = amdgpu_device_aper_access(adev, pos, buf, size, write);
1466 /* using MM to access rest vram and handle un-aligned address */
1469 amdgpu_ttm_vram_mm_access(adev, pos, buf, size, write);
1474 amdgpu_res_next(&cursor, cursor.size);
1481 amdgpu_bo_delete_mem_notify(struct ttm_buffer_object *bo)
1483 amdgpu_bo_move_notify(bo, false, NULL);
1486 static struct ttm_device_funcs amdgpu_bo_driver = {
1487 .ttm_tt_create = &amdgpu_ttm_tt_create,
1488 .ttm_tt_populate = &amdgpu_ttm_tt_populate,
1489 .ttm_tt_unpopulate = &amdgpu_ttm_tt_unpopulate,
1490 .ttm_tt_destroy = &amdgpu_ttm_backend_destroy,
1491 .eviction_valuable = amdgpu_ttm_bo_eviction_valuable,
1492 .evict_flags = &amdgpu_evict_flags,
1493 .move = &amdgpu_bo_move,
1494 .delete_mem_notify = &amdgpu_bo_delete_mem_notify,
1495 .release_notify = &amdgpu_bo_release_notify,
1496 .io_mem_reserve = &amdgpu_ttm_io_mem_reserve,
1497 .io_mem_pfn = amdgpu_ttm_io_mem_pfn,
1498 .access_memory = &amdgpu_ttm_access_memory,
1499 .del_from_lru_notify = &amdgpu_vm_del_from_lru_notify
1503 * Firmware Reservation functions
1506 * amdgpu_ttm_fw_reserve_vram_fini - free fw reserved vram
1508 * @adev: amdgpu_device pointer
1510 * free fw reserved vram if it has been reserved.
1512 static void amdgpu_ttm_fw_reserve_vram_fini(struct amdgpu_device *adev)
1514 amdgpu_bo_free_kernel(&adev->mman.fw_vram_usage_reserved_bo,
1515 NULL, &adev->mman.fw_vram_usage_va);
1519 * amdgpu_ttm_fw_reserve_vram_init - create bo vram reservation from fw
1521 * @adev: amdgpu_device pointer
1523 * create bo vram reservation from fw.
1525 static int amdgpu_ttm_fw_reserve_vram_init(struct amdgpu_device *adev)
1527 uint64_t vram_size = adev->gmc.visible_vram_size;
1529 adev->mman.fw_vram_usage_va = NULL;
1530 adev->mman.fw_vram_usage_reserved_bo = NULL;
1532 if (adev->mman.fw_vram_usage_size == 0 ||
1533 adev->mman.fw_vram_usage_size > vram_size)
1536 return amdgpu_bo_create_kernel_at(adev,
1537 adev->mman.fw_vram_usage_start_offset,
1538 adev->mman.fw_vram_usage_size,
1539 AMDGPU_GEM_DOMAIN_VRAM,
1540 &adev->mman.fw_vram_usage_reserved_bo,
1541 &adev->mman.fw_vram_usage_va);
1545 * Memoy training reservation functions
1549 * amdgpu_ttm_training_reserve_vram_fini - free memory training reserved vram
1551 * @adev: amdgpu_device pointer
1553 * free memory training reserved vram if it has been reserved.
1555 static int amdgpu_ttm_training_reserve_vram_fini(struct amdgpu_device *adev)
1557 struct psp_memory_training_context *ctx = &adev->psp.mem_train_ctx;
1559 ctx->init = PSP_MEM_TRAIN_NOT_SUPPORT;
1560 amdgpu_bo_free_kernel(&ctx->c2p_bo, NULL, NULL);
1566 static void amdgpu_ttm_training_data_block_init(struct amdgpu_device *adev)
1568 struct psp_memory_training_context *ctx = &adev->psp.mem_train_ctx;
1570 memset(ctx, 0, sizeof(*ctx));
1572 ctx->c2p_train_data_offset =
1573 ALIGN((adev->gmc.mc_vram_size - adev->mman.discovery_tmr_size - SZ_1M), SZ_1M);
1574 ctx->p2c_train_data_offset =
1575 (adev->gmc.mc_vram_size - GDDR6_MEM_TRAINING_OFFSET);
1576 ctx->train_data_size =
1577 GDDR6_MEM_TRAINING_DATA_SIZE_IN_BYTES;
1579 DRM_DEBUG("train_data_size:%llx,p2c_train_data_offset:%llx,c2p_train_data_offset:%llx.\n",
1580 ctx->train_data_size,
1581 ctx->p2c_train_data_offset,
1582 ctx->c2p_train_data_offset);
1586 * reserve TMR memory at the top of VRAM which holds
1587 * IP Discovery data and is protected by PSP.
1589 static int amdgpu_ttm_reserve_tmr(struct amdgpu_device *adev)
1592 struct psp_memory_training_context *ctx = &adev->psp.mem_train_ctx;
1593 bool mem_train_support = false;
1595 if (!amdgpu_sriov_vf(adev)) {
1596 if (amdgpu_atomfirmware_mem_training_supported(adev))
1597 mem_train_support = true;
1599 DRM_DEBUG("memory training does not support!\n");
1603 * Query reserved tmr size through atom firmwareinfo for Sienna_Cichlid and onwards for all
1604 * the use cases (IP discovery/G6 memory training/profiling/diagnostic data.etc)
1606 * Otherwise, fallback to legacy approach to check and reserve tmr block for ip
1607 * discovery data and G6 memory training data respectively
1609 adev->mman.discovery_tmr_size =
1610 amdgpu_atomfirmware_get_fw_reserved_fb_size(adev);
1611 if (!adev->mman.discovery_tmr_size)
1612 adev->mman.discovery_tmr_size = DISCOVERY_TMR_OFFSET;
1614 if (mem_train_support) {
1615 /* reserve vram for mem train according to TMR location */
1616 amdgpu_ttm_training_data_block_init(adev);
1617 ret = amdgpu_bo_create_kernel_at(adev,
1618 ctx->c2p_train_data_offset,
1619 ctx->train_data_size,
1620 AMDGPU_GEM_DOMAIN_VRAM,
1624 DRM_ERROR("alloc c2p_bo failed(%d)!\n", ret);
1625 amdgpu_ttm_training_reserve_vram_fini(adev);
1628 ctx->init = PSP_MEM_TRAIN_RESERVE_SUCCESS;
1631 ret = amdgpu_bo_create_kernel_at(adev,
1632 adev->gmc.real_vram_size - adev->mman.discovery_tmr_size,
1633 adev->mman.discovery_tmr_size,
1634 AMDGPU_GEM_DOMAIN_VRAM,
1635 &adev->mman.discovery_memory,
1638 DRM_ERROR("alloc tmr failed(%d)!\n", ret);
1639 amdgpu_bo_free_kernel(&adev->mman.discovery_memory, NULL, NULL);
1647 * amdgpu_ttm_init - Init the memory management (ttm) as well as various
1648 * gtt/vram related fields.
1650 * This initializes all of the memory space pools that the TTM layer
1651 * will need such as the GTT space (system memory mapped to the device),
1652 * VRAM (on-board memory), and on-chip memories (GDS, GWS, OA) which
1653 * can be mapped per VMID.
1655 int amdgpu_ttm_init(struct amdgpu_device *adev)
1661 mutex_init(&adev->mman.gtt_window_lock);
1663 /* No others user of address space so set it to 0 */
1664 r = ttm_device_init(&adev->mman.bdev, &amdgpu_bo_driver, adev->dev,
1665 adev_to_drm(adev)->anon_inode->i_mapping,
1666 adev_to_drm(adev)->vma_offset_manager,
1668 dma_addressing_limited(adev->dev));
1670 DRM_ERROR("failed initializing buffer object driver(%d).\n", r);
1673 adev->mman.initialized = true;
1675 /* Initialize VRAM pool with all of VRAM divided into pages */
1676 r = amdgpu_vram_mgr_init(adev);
1678 DRM_ERROR("Failed initializing VRAM heap.\n");
1682 /* Reduce size of CPU-visible VRAM if requested */
1683 vis_vram_limit = (u64)amdgpu_vis_vram_limit * 1024 * 1024;
1684 if (amdgpu_vis_vram_limit > 0 &&
1685 vis_vram_limit <= adev->gmc.visible_vram_size)
1686 adev->gmc.visible_vram_size = vis_vram_limit;
1688 /* Change the size here instead of the init above so only lpfn is affected */
1689 amdgpu_ttm_set_buffer_funcs_status(adev, false);
1692 if (adev->gmc.xgmi.connected_to_cpu)
1693 adev->mman.aper_base_kaddr = ioremap_cache(adev->gmc.aper_base,
1694 adev->gmc.visible_vram_size);
1698 adev->mman.aper_base_kaddr = ioremap_wc(adev->gmc.aper_base,
1699 adev->gmc.visible_vram_size);
1703 *The reserved vram for firmware must be pinned to the specified
1704 *place on the VRAM, so reserve it early.
1706 r = amdgpu_ttm_fw_reserve_vram_init(adev);
1712 * only NAVI10 and onwards ASIC support for IP discovery.
1713 * If IP discovery enabled, a block of memory should be
1714 * reserved for IP discovey.
1716 if (adev->mman.discovery_bin) {
1717 r = amdgpu_ttm_reserve_tmr(adev);
1722 /* allocate memory as required for VGA
1723 * This is used for VGA emulation and pre-OS scanout buffers to
1724 * avoid display artifacts while transitioning between pre-OS
1726 r = amdgpu_bo_create_kernel_at(adev, 0, adev->mman.stolen_vga_size,
1727 AMDGPU_GEM_DOMAIN_VRAM,
1728 &adev->mman.stolen_vga_memory,
1732 r = amdgpu_bo_create_kernel_at(adev, adev->mman.stolen_vga_size,
1733 adev->mman.stolen_extended_size,
1734 AMDGPU_GEM_DOMAIN_VRAM,
1735 &adev->mman.stolen_extended_memory,
1739 r = amdgpu_bo_create_kernel_at(adev, adev->mman.stolen_reserved_offset,
1740 adev->mman.stolen_reserved_size,
1741 AMDGPU_GEM_DOMAIN_VRAM,
1742 &adev->mman.stolen_reserved_memory,
1747 DRM_INFO("amdgpu: %uM of VRAM memory ready\n",
1748 (unsigned) (adev->gmc.real_vram_size / (1024 * 1024)));
1750 /* Compute GTT size, either bsaed on 3/4th the size of RAM size
1751 * or whatever the user passed on module init */
1752 if (amdgpu_gtt_size == -1) {
1756 gtt_size = min(max((AMDGPU_DEFAULT_GTT_SIZE_MB << 20),
1757 adev->gmc.mc_vram_size),
1758 ((uint64_t)si.totalram * si.mem_unit * 3/4));
1761 gtt_size = (uint64_t)amdgpu_gtt_size << 20;
1763 /* Initialize GTT memory pool */
1764 r = amdgpu_gtt_mgr_init(adev, gtt_size);
1766 DRM_ERROR("Failed initializing GTT heap.\n");
1769 DRM_INFO("amdgpu: %uM of GTT memory ready.\n",
1770 (unsigned)(gtt_size / (1024 * 1024)));
1772 /* Initialize preemptible memory pool */
1773 r = amdgpu_preempt_mgr_init(adev);
1775 DRM_ERROR("Failed initializing PREEMPT heap.\n");
1779 /* Initialize various on-chip memory pools */
1780 r = amdgpu_ttm_init_on_chip(adev, AMDGPU_PL_GDS, adev->gds.gds_size);
1782 DRM_ERROR("Failed initializing GDS heap.\n");
1786 r = amdgpu_ttm_init_on_chip(adev, AMDGPU_PL_GWS, adev->gds.gws_size);
1788 DRM_ERROR("Failed initializing gws heap.\n");
1792 r = amdgpu_ttm_init_on_chip(adev, AMDGPU_PL_OA, adev->gds.oa_size);
1794 DRM_ERROR("Failed initializing oa heap.\n");
1802 * amdgpu_ttm_fini - De-initialize the TTM memory pools
1804 void amdgpu_ttm_fini(struct amdgpu_device *adev)
1806 if (!adev->mman.initialized)
1809 amdgpu_ttm_training_reserve_vram_fini(adev);
1810 /* return the stolen vga memory back to VRAM */
1811 amdgpu_bo_free_kernel(&adev->mman.stolen_vga_memory, NULL, NULL);
1812 amdgpu_bo_free_kernel(&adev->mman.stolen_extended_memory, NULL, NULL);
1813 /* return the IP Discovery TMR memory back to VRAM */
1814 amdgpu_bo_free_kernel(&adev->mman.discovery_memory, NULL, NULL);
1815 if (adev->mman.stolen_reserved_size)
1816 amdgpu_bo_free_kernel(&adev->mman.stolen_reserved_memory,
1818 amdgpu_ttm_fw_reserve_vram_fini(adev);
1820 amdgpu_vram_mgr_fini(adev);
1821 amdgpu_gtt_mgr_fini(adev);
1822 amdgpu_preempt_mgr_fini(adev);
1823 ttm_range_man_fini(&adev->mman.bdev, AMDGPU_PL_GDS);
1824 ttm_range_man_fini(&adev->mman.bdev, AMDGPU_PL_GWS);
1825 ttm_range_man_fini(&adev->mman.bdev, AMDGPU_PL_OA);
1826 ttm_device_fini(&adev->mman.bdev);
1827 adev->mman.initialized = false;
1828 DRM_INFO("amdgpu: ttm finalized\n");
1832 * amdgpu_ttm_set_buffer_funcs_status - enable/disable use of buffer functions
1834 * @adev: amdgpu_device pointer
1835 * @enable: true when we can use buffer functions.
1837 * Enable/disable use of buffer functions during suspend/resume. This should
1838 * only be called at bootup or when userspace isn't running.
1840 void amdgpu_ttm_set_buffer_funcs_status(struct amdgpu_device *adev, bool enable)
1842 struct ttm_resource_manager *man = ttm_manager_type(&adev->mman.bdev, TTM_PL_VRAM);
1846 if (!adev->mman.initialized || amdgpu_in_reset(adev) ||
1847 adev->mman.buffer_funcs_enabled == enable)
1851 struct amdgpu_ring *ring;
1852 struct drm_gpu_scheduler *sched;
1854 ring = adev->mman.buffer_funcs_ring;
1855 sched = &ring->sched;
1856 r = drm_sched_entity_init(&adev->mman.entity,
1857 DRM_SCHED_PRIORITY_KERNEL, &sched,
1860 DRM_ERROR("Failed setting up TTM BO move entity (%d)\n",
1865 drm_sched_entity_destroy(&adev->mman.entity);
1866 dma_fence_put(man->move);
1870 /* this just adjusts TTM size idea, which sets lpfn to the correct value */
1872 size = adev->gmc.real_vram_size;
1874 size = adev->gmc.visible_vram_size;
1875 man->size = size >> PAGE_SHIFT;
1876 adev->mman.buffer_funcs_enabled = enable;
1879 int amdgpu_copy_buffer(struct amdgpu_ring *ring, uint64_t src_offset,
1880 uint64_t dst_offset, uint32_t byte_count,
1881 struct dma_resv *resv,
1882 struct dma_fence **fence, bool direct_submit,
1883 bool vm_needs_flush, bool tmz)
1885 enum amdgpu_ib_pool_type pool = direct_submit ? AMDGPU_IB_POOL_DIRECT :
1886 AMDGPU_IB_POOL_DELAYED;
1887 struct amdgpu_device *adev = ring->adev;
1888 struct amdgpu_job *job;
1891 unsigned num_loops, num_dw;
1895 if (direct_submit && !ring->sched.ready) {
1896 DRM_ERROR("Trying to move memory with ring turned off.\n");
1900 max_bytes = adev->mman.buffer_funcs->copy_max_bytes;
1901 num_loops = DIV_ROUND_UP(byte_count, max_bytes);
1902 num_dw = ALIGN(num_loops * adev->mman.buffer_funcs->copy_num_dw, 8);
1904 r = amdgpu_job_alloc_with_ib(adev, num_dw * 4, pool, &job);
1908 if (vm_needs_flush) {
1909 job->vm_pd_addr = amdgpu_gmc_pd_addr(adev->gmc.pdb0_bo ?
1910 adev->gmc.pdb0_bo : adev->gart.bo);
1911 job->vm_needs_flush = true;
1914 r = amdgpu_sync_resv(adev, &job->sync, resv,
1916 AMDGPU_FENCE_OWNER_UNDEFINED);
1918 DRM_ERROR("sync failed (%d).\n", r);
1923 for (i = 0; i < num_loops; i++) {
1924 uint32_t cur_size_in_bytes = min(byte_count, max_bytes);
1926 amdgpu_emit_copy_buffer(adev, &job->ibs[0], src_offset,
1927 dst_offset, cur_size_in_bytes, tmz);
1929 src_offset += cur_size_in_bytes;
1930 dst_offset += cur_size_in_bytes;
1931 byte_count -= cur_size_in_bytes;
1934 amdgpu_ring_pad_ib(ring, &job->ibs[0]);
1935 WARN_ON(job->ibs[0].length_dw > num_dw);
1937 r = amdgpu_job_submit_direct(job, ring, fence);
1939 r = amdgpu_job_submit(job, &adev->mman.entity,
1940 AMDGPU_FENCE_OWNER_UNDEFINED, fence);
1947 amdgpu_job_free(job);
1948 DRM_ERROR("Error scheduling IBs (%d)\n", r);
1952 int amdgpu_fill_buffer(struct amdgpu_bo *bo,
1954 struct dma_resv *resv,
1955 struct dma_fence **fence)
1957 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
1958 uint32_t max_bytes = adev->mman.buffer_funcs->fill_max_bytes;
1959 struct amdgpu_ring *ring = adev->mman.buffer_funcs_ring;
1961 struct amdgpu_res_cursor cursor;
1962 unsigned int num_loops, num_dw;
1965 struct amdgpu_job *job;
1968 if (!adev->mman.buffer_funcs_enabled) {
1969 DRM_ERROR("Trying to clear memory with ring turned off.\n");
1973 if (bo->tbo.resource->mem_type == AMDGPU_PL_PREEMPT) {
1974 DRM_ERROR("Trying to clear preemptible memory.\n");
1978 if (bo->tbo.resource->mem_type == TTM_PL_TT) {
1979 r = amdgpu_ttm_alloc_gart(&bo->tbo);
1984 num_bytes = bo->tbo.resource->num_pages << PAGE_SHIFT;
1987 amdgpu_res_first(bo->tbo.resource, 0, num_bytes, &cursor);
1988 while (cursor.remaining) {
1989 num_loops += DIV_ROUND_UP_ULL(cursor.size, max_bytes);
1990 amdgpu_res_next(&cursor, cursor.size);
1992 num_dw = num_loops * adev->mman.buffer_funcs->fill_num_dw;
1994 /* for IB padding */
1997 r = amdgpu_job_alloc_with_ib(adev, num_dw * 4, AMDGPU_IB_POOL_DELAYED,
2003 r = amdgpu_sync_resv(adev, &job->sync, resv,
2005 AMDGPU_FENCE_OWNER_UNDEFINED);
2007 DRM_ERROR("sync failed (%d).\n", r);
2012 amdgpu_res_first(bo->tbo.resource, 0, num_bytes, &cursor);
2013 while (cursor.remaining) {
2014 uint32_t cur_size = min_t(uint64_t, cursor.size, max_bytes);
2015 uint64_t dst_addr = cursor.start;
2017 dst_addr += amdgpu_ttm_domain_start(adev,
2018 bo->tbo.resource->mem_type);
2019 amdgpu_emit_fill_buffer(adev, &job->ibs[0], src_data, dst_addr,
2022 amdgpu_res_next(&cursor, cur_size);
2025 amdgpu_ring_pad_ib(ring, &job->ibs[0]);
2026 WARN_ON(job->ibs[0].length_dw > num_dw);
2027 r = amdgpu_job_submit(job, &adev->mman.entity,
2028 AMDGPU_FENCE_OWNER_UNDEFINED, fence);
2035 amdgpu_job_free(job);
2039 #if defined(CONFIG_DEBUG_FS)
2041 static int amdgpu_mm_vram_table_show(struct seq_file *m, void *unused)
2043 struct amdgpu_device *adev = (struct amdgpu_device *)m->private;
2044 struct ttm_resource_manager *man = ttm_manager_type(&adev->mman.bdev,
2046 struct drm_printer p = drm_seq_file_printer(m);
2048 man->func->debug(man, &p);
2052 static int amdgpu_ttm_page_pool_show(struct seq_file *m, void *unused)
2054 struct amdgpu_device *adev = (struct amdgpu_device *)m->private;
2056 return ttm_pool_debugfs(&adev->mman.bdev.pool, m);
2059 static int amdgpu_mm_tt_table_show(struct seq_file *m, void *unused)
2061 struct amdgpu_device *adev = (struct amdgpu_device *)m->private;
2062 struct ttm_resource_manager *man = ttm_manager_type(&adev->mman.bdev,
2064 struct drm_printer p = drm_seq_file_printer(m);
2066 man->func->debug(man, &p);
2070 static int amdgpu_mm_gds_table_show(struct seq_file *m, void *unused)
2072 struct amdgpu_device *adev = (struct amdgpu_device *)m->private;
2073 struct ttm_resource_manager *man = ttm_manager_type(&adev->mman.bdev,
2075 struct drm_printer p = drm_seq_file_printer(m);
2077 man->func->debug(man, &p);
2081 static int amdgpu_mm_gws_table_show(struct seq_file *m, void *unused)
2083 struct amdgpu_device *adev = (struct amdgpu_device *)m->private;
2084 struct ttm_resource_manager *man = ttm_manager_type(&adev->mman.bdev,
2086 struct drm_printer p = drm_seq_file_printer(m);
2088 man->func->debug(man, &p);
2092 static int amdgpu_mm_oa_table_show(struct seq_file *m, void *unused)
2094 struct amdgpu_device *adev = (struct amdgpu_device *)m->private;
2095 struct ttm_resource_manager *man = ttm_manager_type(&adev->mman.bdev,
2097 struct drm_printer p = drm_seq_file_printer(m);
2099 man->func->debug(man, &p);
2103 DEFINE_SHOW_ATTRIBUTE(amdgpu_mm_vram_table);
2104 DEFINE_SHOW_ATTRIBUTE(amdgpu_mm_tt_table);
2105 DEFINE_SHOW_ATTRIBUTE(amdgpu_mm_gds_table);
2106 DEFINE_SHOW_ATTRIBUTE(amdgpu_mm_gws_table);
2107 DEFINE_SHOW_ATTRIBUTE(amdgpu_mm_oa_table);
2108 DEFINE_SHOW_ATTRIBUTE(amdgpu_ttm_page_pool);
2111 * amdgpu_ttm_vram_read - Linear read access to VRAM
2113 * Accesses VRAM via MMIO for debugging purposes.
2115 static ssize_t amdgpu_ttm_vram_read(struct file *f, char __user *buf,
2116 size_t size, loff_t *pos)
2118 struct amdgpu_device *adev = file_inode(f)->i_private;
2121 if (size & 0x3 || *pos & 0x3)
2124 if (*pos >= adev->gmc.mc_vram_size)
2127 size = min(size, (size_t)(adev->gmc.mc_vram_size - *pos));
2129 size_t bytes = min(size, AMDGPU_TTM_VRAM_MAX_DW_READ * 4);
2130 uint32_t value[AMDGPU_TTM_VRAM_MAX_DW_READ];
2132 amdgpu_device_vram_access(adev, *pos, value, bytes, false);
2133 if (copy_to_user(buf, value, bytes))
2146 * amdgpu_ttm_vram_write - Linear write access to VRAM
2148 * Accesses VRAM via MMIO for debugging purposes.
2150 static ssize_t amdgpu_ttm_vram_write(struct file *f, const char __user *buf,
2151 size_t size, loff_t *pos)
2153 struct amdgpu_device *adev = file_inode(f)->i_private;
2157 if (size & 0x3 || *pos & 0x3)
2160 if (*pos >= adev->gmc.mc_vram_size)
2166 if (*pos >= adev->gmc.mc_vram_size)
2169 r = get_user(value, (uint32_t *)buf);
2173 amdgpu_device_mm_access(adev, *pos, &value, 4, true);
2184 static const struct file_operations amdgpu_ttm_vram_fops = {
2185 .owner = THIS_MODULE,
2186 .read = amdgpu_ttm_vram_read,
2187 .write = amdgpu_ttm_vram_write,
2188 .llseek = default_llseek,
2192 * amdgpu_iomem_read - Virtual read access to GPU mapped memory
2194 * This function is used to read memory that has been mapped to the
2195 * GPU and the known addresses are not physical addresses but instead
2196 * bus addresses (e.g., what you'd put in an IB or ring buffer).
2198 static ssize_t amdgpu_iomem_read(struct file *f, char __user *buf,
2199 size_t size, loff_t *pos)
2201 struct amdgpu_device *adev = file_inode(f)->i_private;
2202 struct iommu_domain *dom;
2206 /* retrieve the IOMMU domain if any for this device */
2207 dom = iommu_get_domain_for_dev(adev->dev);
2210 phys_addr_t addr = *pos & PAGE_MASK;
2211 loff_t off = *pos & ~PAGE_MASK;
2212 size_t bytes = PAGE_SIZE - off;
2217 bytes = bytes < size ? bytes : size;
2219 /* Translate the bus address to a physical address. If
2220 * the domain is NULL it means there is no IOMMU active
2221 * and the address translation is the identity
2223 addr = dom ? iommu_iova_to_phys(dom, addr) : addr;
2225 pfn = addr >> PAGE_SHIFT;
2226 if (!pfn_valid(pfn))
2229 p = pfn_to_page(pfn);
2230 if (p->mapping != adev->mman.bdev.dev_mapping)
2234 r = copy_to_user(buf, ptr + off, bytes);
2248 * amdgpu_iomem_write - Virtual write access to GPU mapped memory
2250 * This function is used to write memory that has been mapped to the
2251 * GPU and the known addresses are not physical addresses but instead
2252 * bus addresses (e.g., what you'd put in an IB or ring buffer).
2254 static ssize_t amdgpu_iomem_write(struct file *f, const char __user *buf,
2255 size_t size, loff_t *pos)
2257 struct amdgpu_device *adev = file_inode(f)->i_private;
2258 struct iommu_domain *dom;
2262 dom = iommu_get_domain_for_dev(adev->dev);
2265 phys_addr_t addr = *pos & PAGE_MASK;
2266 loff_t off = *pos & ~PAGE_MASK;
2267 size_t bytes = PAGE_SIZE - off;
2272 bytes = bytes < size ? bytes : size;
2274 addr = dom ? iommu_iova_to_phys(dom, addr) : addr;
2276 pfn = addr >> PAGE_SHIFT;
2277 if (!pfn_valid(pfn))
2280 p = pfn_to_page(pfn);
2281 if (p->mapping != adev->mman.bdev.dev_mapping)
2285 r = copy_from_user(ptr + off, buf, bytes);
2298 static const struct file_operations amdgpu_ttm_iomem_fops = {
2299 .owner = THIS_MODULE,
2300 .read = amdgpu_iomem_read,
2301 .write = amdgpu_iomem_write,
2302 .llseek = default_llseek
2307 void amdgpu_ttm_debugfs_init(struct amdgpu_device *adev)
2309 #if defined(CONFIG_DEBUG_FS)
2310 struct drm_minor *minor = adev_to_drm(adev)->primary;
2311 struct dentry *root = minor->debugfs_root;
2313 debugfs_create_file_size("amdgpu_vram", 0444, root, adev,
2314 &amdgpu_ttm_vram_fops, adev->gmc.mc_vram_size);
2315 debugfs_create_file("amdgpu_iomem", 0444, root, adev,
2316 &amdgpu_ttm_iomem_fops);
2317 debugfs_create_file("amdgpu_vram_mm", 0444, root, adev,
2318 &amdgpu_mm_vram_table_fops);
2319 debugfs_create_file("amdgpu_gtt_mm", 0444, root, adev,
2320 &amdgpu_mm_tt_table_fops);
2321 debugfs_create_file("amdgpu_gds_mm", 0444, root, adev,
2322 &amdgpu_mm_gds_table_fops);
2323 debugfs_create_file("amdgpu_gws_mm", 0444, root, adev,
2324 &amdgpu_mm_gws_table_fops);
2325 debugfs_create_file("amdgpu_oa_mm", 0444, root, adev,
2326 &amdgpu_mm_oa_table_fops);
2327 debugfs_create_file("ttm_page_pool", 0444, root, adev,
2328 &amdgpu_ttm_page_pool_fops);