drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c

   1 /*
   2  * Copyright 2009 Jerome Glisse.
   3  * All Rights Reserved.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the
   7  * "Software"), to deal in the Software without restriction, including
   8  * without limitation the rights to use, copy, modify, merge, publish,
   9  * distribute, sub license, and/or sell copies of the Software, and to
  10  * permit persons to whom the Software is furnished to do so, subject to
  11  * the following conditions:
  12  *
  13  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  14  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  15  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  16  * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
  17  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  18  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  19  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  20  *
  21  * The above copyright notice and this permission notice (including the
  22  * next paragraph) shall be included in all copies or substantial portions
  23  * of the Software.
  24  *
  25  */
  26 /*
  27  * Authors:
  28  *    Jerome Glisse <glisse@freedesktop.org>
  29  *    Thomas Hellstrom <thomas-at-tungstengraphics-dot-com>
  30  *    Dave Airlie
  31  */
  32
  33 #include <linux/dma-mapping.h>
  34 #include <linux/iommu.h>
  35 #include <linux/pagemap.h>
  36 #include <linux/sched/task.h>
  37 #include <linux/sched/mm.h>
  38 #include <linux/seq_file.h>
  39 #include <linux/slab.h>
  40 #include <linux/swap.h>
  41 #include <linux/swiotlb.h>
  42 #include <linux/dma-buf.h>
  43 #include <linux/sizes.h>
  44
  45 #include <drm/ttm/ttm_bo_api.h>
  46 #include <drm/ttm/ttm_bo_driver.h>
  47 #include <drm/ttm/ttm_placement.h>
  48 #include <drm/ttm/ttm_range_manager.h>
  49
  50 #include <drm/amdgpu_drm.h>
  51
  52 #include "amdgpu.h"
  53 #include "amdgpu_object.h"
  54 #include "amdgpu_trace.h"
  55 #include "amdgpu_amdkfd.h"
  56 #include "amdgpu_sdma.h"
  57 #include "amdgpu_ras.h"
  58 #include "amdgpu_atomfirmware.h"
  59 #include "amdgpu_res_cursor.h"
  60 #include "bif/bif_4_1_d.h"
  61
  62 #define AMDGPU_TTM_VRAM_MAX_DW_READ     (size_t)128
  63
  64 static int amdgpu_ttm_backend_bind(struct ttm_device *bdev,
  65                                    struct ttm_tt *ttm,
  66                                    struct ttm_resource *bo_mem);
  67 static void amdgpu_ttm_backend_unbind(struct ttm_device *bdev,
  68                                       struct ttm_tt *ttm);
  69
  70 static int amdgpu_ttm_init_on_chip(struct amdgpu_device *adev,
  71                                     unsigned int type,
  72                                     uint64_t size_in_page)
  73 {
  74         return ttm_range_man_init(&adev->mman.bdev, type,
  75                                   false, size_in_page);
  76 }
  77
  78 /**
  79  * amdgpu_evict_flags - Compute placement flags
  80  *
  81  * @bo: The buffer object to evict
  82  * @placement: Possible destination(s) for evicted BO
  83  *
  84  * Fill in placement data when ttm_bo_evict() is called
  85  */
  86 static void amdgpu_evict_flags(struct ttm_buffer_object *bo,
  87                                 struct ttm_placement *placement)
  88 {
  89         struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev);
  90         struct amdgpu_bo *abo;
  91         static const struct ttm_place placements = {
  92                 .fpfn = 0,
  93                 .lpfn = 0,
  94                 .mem_type = TTM_PL_SYSTEM,
  95                 .flags = 0
  96         };
  97
  98         /* Don't handle scatter gather BOs */
  99         if (bo->type == ttm_bo_type_sg) {
 100                 placement->num_placement = 0;
 101                 placement->num_busy_placement = 0;
 102                 return;
 103         }
 104
 105         /* Object isn't an AMDGPU object so ignore */
 106         if (!amdgpu_bo_is_amdgpu_bo(bo)) {
 107                 placement->placement = &placements;
 108                 placement->busy_placement = &placements;
 109                 placement->num_placement = 1;
 110                 placement->num_busy_placement = 1;
 111                 return;
 112         }
 113
 114         abo = ttm_to_amdgpu_bo(bo);
 115         if (abo->flags & AMDGPU_AMDKFD_CREATE_SVM_BO) {
 116                 struct dma_fence *fence;
 117                 struct dma_resv *resv = &bo->base._resv;
 118
 119                 rcu_read_lock();
 120                 fence = rcu_dereference(resv->fence_excl);
 121                 if (fence && !fence->ops->signaled)
 122                         dma_fence_enable_sw_signaling(fence);
 123
 124                 placement->num_placement = 0;
 125                 placement->num_busy_placement = 0;
 126                 rcu_read_unlock();
 127                 return;
 128         }
 129
 130         switch (bo->resource->mem_type) {
 131         case AMDGPU_PL_GDS:
 132         case AMDGPU_PL_GWS:
 133         case AMDGPU_PL_OA:
 134                 placement->num_placement = 0;
 135                 placement->num_busy_placement = 0;
 136                 return;
 137
 138         case TTM_PL_VRAM:
 139                 if (!adev->mman.buffer_funcs_enabled) {
 140                         /* Move to system memory */
 141                         amdgpu_bo_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_CPU);
 142                 } else if (!amdgpu_gmc_vram_full_visible(&adev->gmc) &&
 143                            !(abo->flags & AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED) &&
 144                            amdgpu_bo_in_cpu_visible_vram(abo)) {
 145
 146                         /* Try evicting to the CPU inaccessible part of VRAM
 147                          * first, but only set GTT as busy placement, so this
 148                          * BO will be evicted to GTT rather than causing other
 149                          * BOs to be evicted from VRAM
 150                          */
 151                         amdgpu_bo_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_VRAM |
 152                                                          AMDGPU_GEM_DOMAIN_GTT);
 153                         abo->placements[0].fpfn = adev->gmc.visible_vram_size >> PAGE_SHIFT;
 154                         abo->placements[0].lpfn = 0;
 155                         abo->placement.busy_placement = &abo->placements[1];
 156                         abo->placement.num_busy_placement = 1;
 157                 } else {
 158                         /* Move to GTT memory */
 159                         amdgpu_bo_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_GTT);
 160                 }
 161                 break;
 162         case TTM_PL_TT:
 163         case AMDGPU_PL_PREEMPT:
 164         default:
 165                 amdgpu_bo_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_CPU);
 166                 break;
 167         }
 168         *placement = abo->placement;
 169 }
 170
 171 /**
 172  * amdgpu_ttm_map_buffer - Map memory into the GART windows
 173  * @bo: buffer object to map
 174  * @mem: memory object to map
 175  * @mm_cur: range to map
 176  * @num_pages: number of pages to map
 177  * @window: which GART window to use
 178  * @ring: DMA ring to use for the copy
 179  * @tmz: if we should setup a TMZ enabled mapping
 180  * @addr: resulting address inside the MC address space
 181  *
 182  * Setup one of the GART windows to access a specific piece of memory or return
 183  * the physical address for local memory.
 184  */
 185 static int amdgpu_ttm_map_buffer(struct ttm_buffer_object *bo,
 186                                  struct ttm_resource *mem,
 187                                  struct amdgpu_res_cursor *mm_cur,
 188                                  unsigned num_pages, unsigned window,
 189                                  struct amdgpu_ring *ring, bool tmz,
 190                                  uint64_t *addr)
 191 {
 192         struct amdgpu_device *adev = ring->adev;
 193         struct amdgpu_job *job;
 194         unsigned num_dw, num_bytes;
 195         struct dma_fence *fence;
 196         uint64_t src_addr, dst_addr;
 197         void *cpu_addr;
 198         uint64_t flags;
 199         unsigned int i;
 200         int r;
 201
 202         BUG_ON(adev->mman.buffer_funcs->copy_max_bytes <
 203                AMDGPU_GTT_MAX_TRANSFER_SIZE * 8);
 204         BUG_ON(mem->mem_type == AMDGPU_PL_PREEMPT);
 205
 206         /* Map only what can't be accessed directly */
 207         if (!tmz && mem->start != AMDGPU_BO_INVALID_OFFSET) {
 208                 *addr = amdgpu_ttm_domain_start(adev, mem->mem_type) +
 209                         mm_cur->start;
 210                 return 0;
 211         }
 212
 213         *addr = adev->gmc.gart_start;
 214         *addr += (u64)window * AMDGPU_GTT_MAX_TRANSFER_SIZE *
 215                 AMDGPU_GPU_PAGE_SIZE;
 216         *addr += mm_cur->start & ~PAGE_MASK;
 217
 218         num_dw = ALIGN(adev->mman.buffer_funcs->copy_num_dw, 8);
 219         num_bytes = num_pages * 8 * AMDGPU_GPU_PAGES_IN_CPU_PAGE;
 220
 221         r = amdgpu_job_alloc_with_ib(adev, num_dw * 4 + num_bytes,
 222                                      AMDGPU_IB_POOL_DELAYED, &job);
 223         if (r)
 224                 return r;
 225
 226         src_addr = num_dw * 4;
 227         src_addr += job->ibs[0].gpu_addr;
 228
 229         dst_addr = amdgpu_bo_gpu_offset(adev->gart.bo);
 230         dst_addr += window * AMDGPU_GTT_MAX_TRANSFER_SIZE * 8;
 231         amdgpu_emit_copy_buffer(adev, &job->ibs[0], src_addr,
 232                                 dst_addr, num_bytes, false);
 233
 234         amdgpu_ring_pad_ib(ring, &job->ibs[0]);
 235         WARN_ON(job->ibs[0].length_dw > num_dw);
 236
 237         flags = amdgpu_ttm_tt_pte_flags(adev, bo->ttm, mem);
 238         if (tmz)
 239                 flags |= AMDGPU_PTE_TMZ;
 240
 241         cpu_addr = &job->ibs[0].ptr[num_dw];
 242
 243         if (mem->mem_type == TTM_PL_TT) {
 244                 dma_addr_t *dma_addr;
 245
 246                 dma_addr = &bo->ttm->dma_address[mm_cur->start >> PAGE_SHIFT];
 247                 r = amdgpu_gart_map(adev, 0, num_pages, dma_addr, flags,
 248                                     cpu_addr);
 249                 if (r)
 250                         goto error_free;
 251         } else {
 252                 dma_addr_t dma_address;
 253
 254                 dma_address = mm_cur->start;
 255                 dma_address += adev->vm_manager.vram_base_offset;
 256
 257                 for (i = 0; i < num_pages; ++i) {
 258                         r = amdgpu_gart_map(adev, i << PAGE_SHIFT, 1,
 259                                             &dma_address, flags, cpu_addr);
 260                         if (r)
 261                                 goto error_free;
 262
 263                         dma_address += PAGE_SIZE;
 264                 }
 265         }
 266
 267         r = amdgpu_job_submit(job, &adev->mman.entity,
 268                               AMDGPU_FENCE_OWNER_UNDEFINED, &fence);
 269         if (r)
 270                 goto error_free;
 271
 272         dma_fence_put(fence);
 273
 274         return r;
 275
 276 error_free:
 277         amdgpu_job_free(job);
 278         return r;
 279 }
 280
 281 /**
 282  * amdgpu_ttm_copy_mem_to_mem - Helper function for copy
 283  * @adev: amdgpu device
 284  * @src: buffer/address where to read from
 285  * @dst: buffer/address where to write to
 286  * @size: number of bytes to copy
 287  * @tmz: if a secure copy should be used
 288  * @resv: resv object to sync to
 289  * @f: Returns the last fence if multiple jobs are submitted.
 290  *
 291  * The function copies @size bytes from {src->mem + src->offset} to
 292  * {dst->mem + dst->offset}. src->bo and dst->bo could be same BO for a
 293  * move and different for a BO to BO copy.
 294  *
 295  */
 296 int amdgpu_ttm_copy_mem_to_mem(struct amdgpu_device *adev,
 297                                const struct amdgpu_copy_mem *src,
 298                                const struct amdgpu_copy_mem *dst,
 299                                uint64_t size, bool tmz,
 300                                struct dma_resv *resv,
 301                                struct dma_fence **f)
 302 {
 303         const uint32_t GTT_MAX_BYTES = (AMDGPU_GTT_MAX_TRANSFER_SIZE *
 304                                         AMDGPU_GPU_PAGE_SIZE);
 305
 306         struct amdgpu_ring *ring = adev->mman.buffer_funcs_ring;
 307         struct amdgpu_res_cursor src_mm, dst_mm;
 308         struct dma_fence *fence = NULL;
 309         int r = 0;
 310
 311         if (!adev->mman.buffer_funcs_enabled) {
 312                 DRM_ERROR("Trying to move memory with ring turned off.\n");
 313                 return -EINVAL;
 314         }
 315
 316         amdgpu_res_first(src->mem, src->offset, size, &src_mm);
 317         amdgpu_res_first(dst->mem, dst->offset, size, &dst_mm);
 318
 319         mutex_lock(&adev->mman.gtt_window_lock);
 320         while (src_mm.remaining) {
 321                 uint32_t src_page_offset = src_mm.start & ~PAGE_MASK;
 322                 uint32_t dst_page_offset = dst_mm.start & ~PAGE_MASK;
 323                 struct dma_fence *next;
 324                 uint32_t cur_size;
 325                 uint64_t from, to;
 326
 327                 /* Copy size cannot exceed GTT_MAX_BYTES. So if src or dst
 328                  * begins at an offset, then adjust the size accordingly
 329                  */
 330                 cur_size = max(src_page_offset, dst_page_offset);
 331                 cur_size = min(min3(src_mm.size, dst_mm.size, size),
 332                                (uint64_t)(GTT_MAX_BYTES - cur_size));
 333
 334                 /* Map src to window 0 and dst to window 1. */
 335                 r = amdgpu_ttm_map_buffer(src->bo, src->mem, &src_mm,
 336                                           PFN_UP(cur_size + src_page_offset),
 337                                           0, ring, tmz, &from);
 338                 if (r)
 339                         goto error;
 340
 341                 r = amdgpu_ttm_map_buffer(dst->bo, dst->mem, &dst_mm,
 342                                           PFN_UP(cur_size + dst_page_offset),
 343                                           1, ring, tmz, &to);
 344                 if (r)
 345                         goto error;
 346
 347                 r = amdgpu_copy_buffer(ring, from, to, cur_size,
 348                                        resv, &next, false, true, tmz);
 349                 if (r)
 350                         goto error;
 351
 352                 dma_fence_put(fence);
 353                 fence = next;
 354
 355                 amdgpu_res_next(&src_mm, cur_size);
 356                 amdgpu_res_next(&dst_mm, cur_size);
 357         }
 358 error:
 359         mutex_unlock(&adev->mman.gtt_window_lock);
 360         if (f)
 361                 *f = dma_fence_get(fence);
 362         dma_fence_put(fence);
 363         return r;
 364 }
 365
 366 /*
 367  * amdgpu_move_blit - Copy an entire buffer to another buffer
 368  *
 369  * This is a helper called by amdgpu_bo_move() and amdgpu_move_vram_ram() to
 370  * help move buffers to and from VRAM.
 371  */
 372 static int amdgpu_move_blit(struct ttm_buffer_object *bo,
 373                             bool evict,
 374                             struct ttm_resource *new_mem,
 375                             struct ttm_resource *old_mem)
 376 {
 377         struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev);
 378         struct amdgpu_bo *abo = ttm_to_amdgpu_bo(bo);
 379         struct amdgpu_copy_mem src, dst;
 380         struct dma_fence *fence = NULL;
 381         int r;
 382
 383         src.bo = bo;
 384         dst.bo = bo;
 385         src.mem = old_mem;
 386         dst.mem = new_mem;
 387         src.offset = 0;
 388         dst.offset = 0;
 389
 390         r = amdgpu_ttm_copy_mem_to_mem(adev, &src, &dst,
 391                                        new_mem->num_pages << PAGE_SHIFT,
 392                                        amdgpu_bo_encrypted(abo),
 393                                        bo->base.resv, &fence);
 394         if (r)
 395                 goto error;
 396
 397         /* clear the space being freed */
 398         if (old_mem->mem_type == TTM_PL_VRAM &&
 399             (abo->flags & AMDGPU_GEM_CREATE_VRAM_WIPE_ON_RELEASE)) {
 400                 struct dma_fence *wipe_fence = NULL;
 401
 402                 r = amdgpu_fill_buffer(ttm_to_amdgpu_bo(bo), AMDGPU_POISON,
 403                                        NULL, &wipe_fence);
 404                 if (r) {
 405                         goto error;
 406                 } else if (wipe_fence) {
 407                         dma_fence_put(fence);
 408                         fence = wipe_fence;
 409                 }
 410         }
 411
 412         /* Always block for VM page tables before committing the new location */
 413         if (bo->type == ttm_bo_type_kernel)
 414                 r = ttm_bo_move_accel_cleanup(bo, fence, true, false, new_mem);
 415         else
 416                 r = ttm_bo_move_accel_cleanup(bo, fence, evict, true, new_mem);
 417         dma_fence_put(fence);
 418         return r;
 419
 420 error:
 421         if (fence)
 422                 dma_fence_wait(fence, false);
 423         dma_fence_put(fence);
 424         return r;
 425 }
 426
 427 /*
 428  * amdgpu_mem_visible - Check that memory can be accessed by ttm_bo_move_memcpy
 429  *
 430  * Called by amdgpu_bo_move()
 431  */
 432 static bool amdgpu_mem_visible(struct amdgpu_device *adev,
 433                                struct ttm_resource *mem)
 434 {
 435         uint64_t mem_size = (u64)mem->num_pages << PAGE_SHIFT;
 436         struct amdgpu_res_cursor cursor;
 437
 438         if (mem->mem_type == TTM_PL_SYSTEM ||
 439             mem->mem_type == TTM_PL_TT)
 440                 return true;
 441         if (mem->mem_type != TTM_PL_VRAM)
 442                 return false;
 443
 444         amdgpu_res_first(mem, 0, mem_size, &cursor);
 445
 446         /* ttm_resource_ioremap only supports contiguous memory */
 447         if (cursor.size != mem_size)
 448                 return false;
 449
 450         return cursor.start + cursor.size <= adev->gmc.visible_vram_size;
 451 }
 452
 453 /*
 454  * amdgpu_bo_move - Move a buffer object to a new memory location
 455  *
 456  * Called by ttm_bo_handle_move_mem()
 457  */
 458 static int amdgpu_bo_move(struct ttm_buffer_object *bo, bool evict,
 459                           struct ttm_operation_ctx *ctx,
 460                           struct ttm_resource *new_mem,
 461                           struct ttm_place *hop)
 462 {
 463         struct amdgpu_device *adev;
 464         struct amdgpu_bo *abo;
 465         struct ttm_resource *old_mem = bo->resource;
 466         int r;
 467
 468         if (new_mem->mem_type == TTM_PL_TT ||
 469             new_mem->mem_type == AMDGPU_PL_PREEMPT) {
 470                 r = amdgpu_ttm_backend_bind(bo->bdev, bo->ttm, new_mem);
 471                 if (r)
 472                         return r;
 473         }
 474
 475         /* Can't move a pinned BO */
 476         abo = ttm_to_amdgpu_bo(bo);
 477         if (WARN_ON_ONCE(abo->tbo.pin_count > 0))
 478                 return -EINVAL;
 479
 480         adev = amdgpu_ttm_adev(bo->bdev);
 481
 482         if (old_mem->mem_type == TTM_PL_SYSTEM && bo->ttm == NULL) {
 483                 ttm_bo_move_null(bo, new_mem);
 484                 goto out;
 485         }
 486         if (old_mem->mem_type == TTM_PL_SYSTEM &&
 487             (new_mem->mem_type == TTM_PL_TT ||
 488              new_mem->mem_type == AMDGPU_PL_PREEMPT)) {
 489                 ttm_bo_move_null(bo, new_mem);
 490                 goto out;
 491         }
 492         if ((old_mem->mem_type == TTM_PL_TT ||
 493              old_mem->mem_type == AMDGPU_PL_PREEMPT) &&
 494             new_mem->mem_type == TTM_PL_SYSTEM) {
 495                 r = ttm_bo_wait_ctx(bo, ctx);
 496                 if (r)
 497                         return r;
 498
 499                 amdgpu_ttm_backend_unbind(bo->bdev, bo->ttm);
 500                 ttm_resource_free(bo, &bo->resource);
 501                 ttm_bo_assign_mem(bo, new_mem);
 502                 goto out;
 503         }
 504
 505         if (old_mem->mem_type == AMDGPU_PL_GDS ||
 506             old_mem->mem_type == AMDGPU_PL_GWS ||
 507             old_mem->mem_type == AMDGPU_PL_OA ||
 508             new_mem->mem_type == AMDGPU_PL_GDS ||
 509             new_mem->mem_type == AMDGPU_PL_GWS ||
 510             new_mem->mem_type == AMDGPU_PL_OA) {
 511                 /* Nothing to save here */
 512                 ttm_bo_move_null(bo, new_mem);
 513                 goto out;
 514         }
 515
 516         if (adev->mman.buffer_funcs_enabled) {
 517                 if (((old_mem->mem_type == TTM_PL_SYSTEM &&
 518                       new_mem->mem_type == TTM_PL_VRAM) ||
 519                      (old_mem->mem_type == TTM_PL_VRAM &&
 520                       new_mem->mem_type == TTM_PL_SYSTEM))) {
 521                         hop->fpfn = 0;
 522                         hop->lpfn = 0;
 523                         hop->mem_type = TTM_PL_TT;
 524                         hop->flags = 0;
 525                         return -EMULTIHOP;
 526                 }
 527
 528                 r = amdgpu_move_blit(bo, evict, new_mem, old_mem);
 529         } else {
 530                 r = -ENODEV;
 531         }
 532
 533         if (r) {
 534                 /* Check that all memory is CPU accessible */
 535                 if (!amdgpu_mem_visible(adev, old_mem) ||
 536                     !amdgpu_mem_visible(adev, new_mem)) {
 537                         pr_err("Move buffer fallback to memcpy unavailable\n");
 538                         return r;
 539                 }
 540
 541                 r = ttm_bo_move_memcpy(bo, ctx, new_mem);
 542                 if (r)
 543                         return r;
 544         }
 545
 546         if (bo->type == ttm_bo_type_device &&
 547             new_mem->mem_type == TTM_PL_VRAM &&
 548             old_mem->mem_type != TTM_PL_VRAM) {
 549                 /* amdgpu_bo_fault_reserve_notify will re-set this if the CPU
 550                  * accesses the BO after it's moved.
 551                  */
 552                 abo->flags &= ~AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED;
 553         }
 554
 555 out:
 556         /* update statistics */
 557         atomic64_add(bo->base.size, &adev->num_bytes_moved);
 558         amdgpu_bo_move_notify(bo, evict, new_mem);
 559         return 0;
 560 }
 561
 562 /*
 563  * amdgpu_ttm_io_mem_reserve - Reserve a block of memory during a fault
 564  *
 565  * Called by ttm_mem_io_reserve() ultimately via ttm_bo_vm_fault()
 566  */
 567 static int amdgpu_ttm_io_mem_reserve(struct ttm_device *bdev,
 568                                      struct ttm_resource *mem)
 569 {
 570         struct amdgpu_device *adev = amdgpu_ttm_adev(bdev);
 571         size_t bus_size = (size_t)mem->num_pages << PAGE_SHIFT;
 572
 573         switch (mem->mem_type) {
 574         case TTM_PL_SYSTEM:
 575                 /* system memory */
 576                 return 0;
 577         case TTM_PL_TT:
 578         case AMDGPU_PL_PREEMPT:
 579                 break;
 580         case TTM_PL_VRAM:
 581                 mem->bus.offset = mem->start << PAGE_SHIFT;
 582                 /* check if it's visible */
 583                 if ((mem->bus.offset + bus_size) > adev->gmc.visible_vram_size)
 584                         return -EINVAL;
 585
 586                 if (adev->mman.aper_base_kaddr &&
 587                     mem->placement & TTM_PL_FLAG_CONTIGUOUS)
 588                         mem->bus.addr = (u8 *)adev->mman.aper_base_kaddr +
 589                                         mem->bus.offset;
 590
 591                 mem->bus.offset += adev->gmc.aper_base;
 592                 mem->bus.is_iomem = true;
 593                 break;
 594         default:
 595                 return -EINVAL;
 596         }
 597         return 0;
 598 }
 599
 600 static unsigned long amdgpu_ttm_io_mem_pfn(struct ttm_buffer_object *bo,
 601                                            unsigned long page_offset)
 602 {
 603         struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev);
 604         struct amdgpu_res_cursor cursor;
 605
 606         amdgpu_res_first(bo->resource, (u64)page_offset << PAGE_SHIFT, 0,
 607                          &cursor);
 608         return (adev->gmc.aper_base + cursor.start) >> PAGE_SHIFT;
 609 }
 610
 611 /**
 612  * amdgpu_ttm_domain_start - Returns GPU start address
 613  * @adev: amdgpu device object
 614  * @type: type of the memory
 615  *
 616  * Returns:
 617  * GPU start address of a memory domain
 618  */
 619
 620 uint64_t amdgpu_ttm_domain_start(struct amdgpu_device *adev, uint32_t type)
 621 {
 622         switch (type) {
 623         case TTM_PL_TT:
 624                 return adev->gmc.gart_start;
 625         case TTM_PL_VRAM:
 626                 return adev->gmc.vram_start;
 627         }
 628
 629         return 0;
 630 }
 631
 632 /*
 633  * TTM backend functions.
 634  */
 635 struct amdgpu_ttm_tt {
 636         struct ttm_tt   ttm;
 637         struct drm_gem_object   *gobj;
 638         u64                     offset;
 639         uint64_t                userptr;
 640         struct task_struct      *usertask;
 641         uint32_t                userflags;
 642         bool                    bound;
 643 #if IS_ENABLED(CONFIG_DRM_AMDGPU_USERPTR)
 644         struct hmm_range        *range;
 645 #endif
 646 };
 647
 648 #ifdef CONFIG_DRM_AMDGPU_USERPTR
 649 /*
 650  * amdgpu_ttm_tt_get_user_pages - get device accessible pages that back user
 651  * memory and start HMM tracking CPU page table update
 652  *
 653  * Calling function must call amdgpu_ttm_tt_userptr_range_done() once and only
 654  * once afterwards to stop HMM tracking
 655  */
 656 int amdgpu_ttm_tt_get_user_pages(struct amdgpu_bo *bo, struct page **pages)
 657 {
 658         struct ttm_tt *ttm = bo->tbo.ttm;
 659         struct amdgpu_ttm_tt *gtt = (void *)ttm;
 660         unsigned long start = gtt->userptr;
 661         struct vm_area_struct *vma;
 662         struct mm_struct *mm;
 663         bool readonly;
 664         int r = 0;
 665
 666         mm = bo->notifier.mm;
 667         if (unlikely(!mm)) {
 668                 DRM_DEBUG_DRIVER("BO is not registered?\n");
 669                 return -EFAULT;
 670         }
 671
 672         /* Another get_user_pages is running at the same time?? */
 673         if (WARN_ON(gtt->range))
 674                 return -EFAULT;
 675
 676         if (!mmget_not_zero(mm)) /* Happens during process shutdown */
 677                 return -ESRCH;
 678
 679         mmap_read_lock(mm);
 680         vma = find_vma(mm, start);
 681         mmap_read_unlock(mm);
 682         if (unlikely(!vma || start < vma->vm_start)) {
 683                 r = -EFAULT;
 684                 goto out_putmm;
 685         }
 686         if (unlikely((gtt->userflags & AMDGPU_GEM_USERPTR_ANONONLY) &&
 687                 vma->vm_file)) {
 688                 r = -EPERM;
 689                 goto out_putmm;
 690         }
 691
 692         readonly = amdgpu_ttm_tt_is_readonly(ttm);
 693         r = amdgpu_hmm_range_get_pages(&bo->notifier, mm, pages, start,
 694                                        ttm->num_pages, &gtt->range, readonly,
 695                                        false, NULL);
 696 out_putmm:
 697         mmput(mm);
 698
 699         return r;
 700 }
 701
 702 /*
 703  * amdgpu_ttm_tt_userptr_range_done - stop HMM track the CPU page table change
 704  * Check if the pages backing this ttm range have been invalidated
 705  *
 706  * Returns: true if pages are still valid
 707  */
 708 bool amdgpu_ttm_tt_get_user_pages_done(struct ttm_tt *ttm)
 709 {
 710         struct amdgpu_ttm_tt *gtt = (void *)ttm;
 711         bool r = false;
 712
 713         if (!gtt || !gtt->userptr)
 714                 return false;
 715
 716         DRM_DEBUG_DRIVER("user_pages_done 0x%llx pages 0x%x\n",
 717                 gtt->userptr, ttm->num_pages);
 718
 719         WARN_ONCE(!gtt->range || !gtt->range->hmm_pfns,
 720                 "No user pages to check\n");
 721
 722         if (gtt->range) {
 723                 /*
 724                  * FIXME: Must always hold notifier_lock for this, and must
 725                  * not ignore the return code.
 726                  */
 727                 r = amdgpu_hmm_range_get_pages_done(gtt->range);
 728                 gtt->range = NULL;
 729         }
 730
 731         return !r;
 732 }
 733 #endif
 734
 735 /*
 736  * amdgpu_ttm_tt_set_user_pages - Copy pages in, putting old pages as necessary.
 737  *
 738  * Called by amdgpu_cs_list_validate(). This creates the page list
 739  * that backs user memory and will ultimately be mapped into the device
 740  * address space.
 741  */
 742 void amdgpu_ttm_tt_set_user_pages(struct ttm_tt *ttm, struct page **pages)
 743 {
 744         unsigned long i;
 745
 746         for (i = 0; i < ttm->num_pages; ++i)
 747                 ttm->pages[i] = pages ? pages[i] : NULL;
 748 }
 749
 750 /*
 751  * amdgpu_ttm_tt_pin_userptr - prepare the sg table with the user pages
 752  *
 753  * Called by amdgpu_ttm_backend_bind()
 754  **/
 755 static int amdgpu_ttm_tt_pin_userptr(struct ttm_device *bdev,
 756                                      struct ttm_tt *ttm)
 757 {
 758         struct amdgpu_device *adev = amdgpu_ttm_adev(bdev);
 759         struct amdgpu_ttm_tt *gtt = (void *)ttm;
 760         int write = !(gtt->userflags & AMDGPU_GEM_USERPTR_READONLY);
 761         enum dma_data_direction direction = write ?
 762                 DMA_BIDIRECTIONAL : DMA_TO_DEVICE;
 763         int r;
 764
 765         /* Allocate an SG array and squash pages into it */
 766         r = sg_alloc_table_from_pages(ttm->sg, ttm->pages, ttm->num_pages, 0,
 767                                       (u64)ttm->num_pages << PAGE_SHIFT,
 768                                       GFP_KERNEL);
 769         if (r)
 770                 goto release_sg;
 771
 772         /* Map SG to device */
 773         r = dma_map_sgtable(adev->dev, ttm->sg, direction, 0);
 774         if (r)
 775                 goto release_sg;
 776
 777         /* convert SG to linear array of pages and dma addresses */
 778         drm_prime_sg_to_dma_addr_array(ttm->sg, gtt->ttm.dma_address,
 779                                        ttm->num_pages);
 780
 781         return 0;
 782
 783 release_sg:
 784         kfree(ttm->sg);
 785         ttm->sg = NULL;
 786         return r;
 787 }
 788
 789 /*
 790  * amdgpu_ttm_tt_unpin_userptr - Unpin and unmap userptr pages
 791  */
 792 static void amdgpu_ttm_tt_unpin_userptr(struct ttm_device *bdev,
 793                                         struct ttm_tt *ttm)
 794 {
 795         struct amdgpu_device *adev = amdgpu_ttm_adev(bdev);
 796         struct amdgpu_ttm_tt *gtt = (void *)ttm;
 797         int write = !(gtt->userflags & AMDGPU_GEM_USERPTR_READONLY);
 798         enum dma_data_direction direction = write ?
 799                 DMA_BIDIRECTIONAL : DMA_TO_DEVICE;
 800
 801         /* double check that we don't free the table twice */
 802         if (!ttm->sg || !ttm->sg->sgl)
 803                 return;
 804
 805         /* unmap the pages mapped to the device */
 806         dma_unmap_sgtable(adev->dev, ttm->sg, direction, 0);
 807         sg_free_table(ttm->sg);
 808
 809 #if IS_ENABLED(CONFIG_DRM_AMDGPU_USERPTR)
 810         if (gtt->range) {
 811                 unsigned long i;
 812
 813                 for (i = 0; i < ttm->num_pages; i++) {
 814                         if (ttm->pages[i] !=
 815                             hmm_pfn_to_page(gtt->range->hmm_pfns[i]))
 816                                 break;
 817                 }
 818
 819                 WARN((i == ttm->num_pages), "Missing get_user_page_done\n");
 820         }
 821 #endif
 822 }
 823
 824 static int amdgpu_ttm_gart_bind(struct amdgpu_device *adev,
 825                                 struct ttm_buffer_object *tbo,
 826                                 uint64_t flags)
 827 {
 828         struct amdgpu_bo *abo = ttm_to_amdgpu_bo(tbo);
 829         struct ttm_tt *ttm = tbo->ttm;
 830         struct amdgpu_ttm_tt *gtt = (void *)ttm;
 831         int r;
 832
 833         if (amdgpu_bo_encrypted(abo))
 834                 flags |= AMDGPU_PTE_TMZ;
 835
 836         if (abo->flags & AMDGPU_GEM_CREATE_CP_MQD_GFX9) {
 837                 uint64_t page_idx = 1;
 838
 839                 r = amdgpu_gart_bind(adev, gtt->offset, page_idx,
 840                                 gtt->ttm.dma_address, flags);
 841                 if (r)
 842                         goto gart_bind_fail;
 843
 844                 /* The memory type of the first page defaults to UC. Now
 845                  * modify the memory type to NC from the second page of
 846                  * the BO onward.
 847                  */
 848                 flags &= ~AMDGPU_PTE_MTYPE_VG10_MASK;
 849                 flags |= AMDGPU_PTE_MTYPE_VG10(AMDGPU_MTYPE_NC);
 850
 851                 r = amdgpu_gart_bind(adev,
 852                                 gtt->offset + (page_idx << PAGE_SHIFT),
 853                                 ttm->num_pages - page_idx,
 854                                 &(gtt->ttm.dma_address[page_idx]), flags);
 855         } else {
 856                 r = amdgpu_gart_bind(adev, gtt->offset, ttm->num_pages,
 857                                      gtt->ttm.dma_address, flags);
 858         }
 859
 860 gart_bind_fail:
 861         if (r)
 862                 DRM_ERROR("failed to bind %u pages at 0x%08llX\n",
 863                           ttm->num_pages, gtt->offset);
 864
 865         return r;
 866 }
 867
 868 /*
 869  * amdgpu_ttm_backend_bind - Bind GTT memory
 870  *
 871  * Called by ttm_tt_bind() on behalf of ttm_bo_handle_move_mem().
 872  * This handles binding GTT memory to the device address space.
 873  */
 874 static int amdgpu_ttm_backend_bind(struct ttm_device *bdev,
 875                                    struct ttm_tt *ttm,
 876                                    struct ttm_resource *bo_mem)
 877 {
 878         struct amdgpu_device *adev = amdgpu_ttm_adev(bdev);
 879         struct amdgpu_ttm_tt *gtt = (void*)ttm;
 880         uint64_t flags;
 881         int r = 0;
 882
 883         if (!bo_mem)
 884                 return -EINVAL;
 885
 886         if (gtt->bound)
 887                 return 0;
 888
 889         if (gtt->userptr) {
 890                 r = amdgpu_ttm_tt_pin_userptr(bdev, ttm);
 891                 if (r) {
 892                         DRM_ERROR("failed to pin userptr\n");
 893                         return r;
 894                 }
 895         } else if (ttm->page_flags & TTM_PAGE_FLAG_SG) {
 896                 if (!ttm->sg) {
 897                         struct dma_buf_attachment *attach;
 898                         struct sg_table *sgt;
 899
 900                         attach = gtt->gobj->import_attach;
 901                         sgt = dma_buf_map_attachment(attach, DMA_BIDIRECTIONAL);
 902                         if (IS_ERR(sgt))
 903                                 return PTR_ERR(sgt);
 904
 905                         ttm->sg = sgt;
 906                 }
 907
 908                 drm_prime_sg_to_dma_addr_array(ttm->sg, gtt->ttm.dma_address,
 909                                                ttm->num_pages);
 910         }
 911
 912         if (!ttm->num_pages) {
 913                 WARN(1, "nothing to bind %u pages for mreg %p back %p!\n",
 914                      ttm->num_pages, bo_mem, ttm);
 915         }
 916
 917         if (bo_mem->mem_type == AMDGPU_PL_GDS ||
 918             bo_mem->mem_type == AMDGPU_PL_GWS ||
 919             bo_mem->mem_type == AMDGPU_PL_OA)
 920                 return -EINVAL;
 921
 922         if (!amdgpu_gtt_mgr_has_gart_addr(bo_mem)) {
 923                 gtt->offset = AMDGPU_BO_INVALID_OFFSET;
 924                 return 0;
 925         }
 926
 927         /* compute PTE flags relevant to this BO memory */
 928         flags = amdgpu_ttm_tt_pte_flags(adev, ttm, bo_mem);
 929
 930         /* bind pages into GART page tables */
 931         gtt->offset = (u64)bo_mem->start << PAGE_SHIFT;
 932         r = amdgpu_gart_bind(adev, gtt->offset, ttm->num_pages,
 933                 gtt->ttm.dma_address, flags);
 934
 935         if (r)
 936                 DRM_ERROR("failed to bind %u pages at 0x%08llX\n",
 937                           ttm->num_pages, gtt->offset);
 938         gtt->bound = true;
 939         return r;
 940 }
 941
 942 /*
 943  * amdgpu_ttm_alloc_gart - Make sure buffer object is accessible either
 944  * through AGP or GART aperture.
 945  *
 946  * If bo is accessible through AGP aperture, then use AGP aperture
 947  * to access bo; otherwise allocate logical space in GART aperture
 948  * and map bo to GART aperture.
 949  */
 950 int amdgpu_ttm_alloc_gart(struct ttm_buffer_object *bo)
 951 {
 952         struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev);
 953         struct ttm_operation_ctx ctx = { false, false };
 954         struct amdgpu_ttm_tt *gtt = (void *)bo->ttm;
 955         struct ttm_placement placement;
 956         struct ttm_place placements;
 957         struct ttm_resource *tmp;
 958         uint64_t addr, flags;
 959         int r;
 960
 961         if (bo->resource->start != AMDGPU_BO_INVALID_OFFSET)
 962                 return 0;
 963
 964         addr = amdgpu_gmc_agp_addr(bo);
 965         if (addr != AMDGPU_BO_INVALID_OFFSET) {
 966                 bo->resource->start = addr >> PAGE_SHIFT;
 967                 return 0;
 968         }
 969
 970         /* allocate GART space */
 971         placement.num_placement = 1;
 972         placement.placement = &placements;
 973         placement.num_busy_placement = 1;
 974         placement.busy_placement = &placements;
 975         placements.fpfn = 0;
 976         placements.lpfn = adev->gmc.gart_size >> PAGE_SHIFT;
 977         placements.mem_type = TTM_PL_TT;
 978         placements.flags = bo->resource->placement;
 979
 980         r = ttm_bo_mem_space(bo, &placement, &tmp, &ctx);
 981         if (unlikely(r))
 982                 return r;
 983
 984         /* compute PTE flags for this buffer object */
 985         flags = amdgpu_ttm_tt_pte_flags(adev, bo->ttm, tmp);
 986
 987         /* Bind pages */
 988         gtt->offset = (u64)tmp->start << PAGE_SHIFT;
 989         r = amdgpu_ttm_gart_bind(adev, bo, flags);
 990         if (unlikely(r)) {
 991                 ttm_resource_free(bo, &tmp);
 992                 return r;
 993         }
 994
 995         amdgpu_gart_invalidate_tlb(adev);
 996         ttm_resource_free(bo, &bo->resource);
 997         ttm_bo_assign_mem(bo, tmp);
 998
 999         return 0;
1000 }
1001
1002 /*
1003  * amdgpu_ttm_recover_gart - Rebind GTT pages
1004  *
1005  * Called by amdgpu_gtt_mgr_recover() from amdgpu_device_reset() to
1006  * rebind GTT pages during a GPU reset.
1007  */
1008 int amdgpu_ttm_recover_gart(struct ttm_buffer_object *tbo)
1009 {
1010         struct amdgpu_device *adev = amdgpu_ttm_adev(tbo->bdev);
1011         uint64_t flags;
1012         int r;
1013
1014         if (!tbo->ttm)
1015                 return 0;
1016
1017         flags = amdgpu_ttm_tt_pte_flags(adev, tbo->ttm, tbo->resource);
1018         r = amdgpu_ttm_gart_bind(adev, tbo, flags);
1019
1020         return r;
1021 }
1022
1023 /*
1024  * amdgpu_ttm_backend_unbind - Unbind GTT mapped pages
1025  *
1026  * Called by ttm_tt_unbind() on behalf of ttm_bo_move_ttm() and
1027  * ttm_tt_destroy().
1028  */
1029 static void amdgpu_ttm_backend_unbind(struct ttm_device *bdev,
1030                                       struct ttm_tt *ttm)
1031 {
1032         struct amdgpu_device *adev = amdgpu_ttm_adev(bdev);
1033         struct amdgpu_ttm_tt *gtt = (void *)ttm;
1034         int r;
1035
1036         /* if the pages have userptr pinning then clear that first */
1037         if (gtt->userptr) {
1038                 amdgpu_ttm_tt_unpin_userptr(bdev, ttm);
1039         } else if (ttm->sg && gtt->gobj->import_attach) {
1040                 struct dma_buf_attachment *attach;
1041
1042                 attach = gtt->gobj->import_attach;
1043                 dma_buf_unmap_attachment(attach, ttm->sg, DMA_BIDIRECTIONAL);
1044                 ttm->sg = NULL;
1045         }
1046
1047         if (!gtt->bound)
1048                 return;
1049
1050         if (gtt->offset == AMDGPU_BO_INVALID_OFFSET)
1051                 return;
1052
1053         /* unbind shouldn't be done for GDS/GWS/OA in ttm_bo_clean_mm */
1054         r = amdgpu_gart_unbind(adev, gtt->offset, ttm->num_pages);
1055         if (r)
1056                 DRM_ERROR("failed to unbind %u pages at 0x%08llX\n",
1057                           gtt->ttm.num_pages, gtt->offset);
1058         gtt->bound = false;
1059 }
1060
1061 static void amdgpu_ttm_backend_destroy(struct ttm_device *bdev,
1062                                        struct ttm_tt *ttm)
1063 {
1064         struct amdgpu_ttm_tt *gtt = (void *)ttm;
1065
1066         amdgpu_ttm_backend_unbind(bdev, ttm);
1067         ttm_tt_destroy_common(bdev, ttm);
1068         if (gtt->usertask)
1069                 put_task_struct(gtt->usertask);
1070
1071         ttm_tt_fini(&gtt->ttm);
1072         kfree(gtt);
1073 }
1074
1075 /**
1076  * amdgpu_ttm_tt_create - Create a ttm_tt object for a given BO
1077  *
1078  * @bo: The buffer object to create a GTT ttm_tt object around
1079  * @page_flags: Page flags to be added to the ttm_tt object
1080  *
1081  * Called by ttm_tt_create().
1082  */
1083 static struct ttm_tt *amdgpu_ttm_tt_create(struct ttm_buffer_object *bo,
1084                                            uint32_t page_flags)
1085 {
1086         struct amdgpu_bo *abo = ttm_to_amdgpu_bo(bo);
1087         struct amdgpu_ttm_tt *gtt;
1088         enum ttm_caching caching;
1089
1090         gtt = kzalloc(sizeof(struct amdgpu_ttm_tt), GFP_KERNEL);
1091         if (gtt == NULL) {
1092                 return NULL;
1093         }
1094         gtt->gobj = &bo->base;
1095
1096         if (abo->flags & AMDGPU_GEM_CREATE_CPU_GTT_USWC)
1097                 caching = ttm_write_combined;
1098         else
1099                 caching = ttm_cached;
1100
1101         /* allocate space for the uninitialized page entries */
1102         if (ttm_sg_tt_init(&gtt->ttm, bo, page_flags, caching)) {
1103                 kfree(gtt);
1104                 return NULL;
1105         }
1106         return &gtt->ttm;
1107 }
1108
1109 /*
1110  * amdgpu_ttm_tt_populate - Map GTT pages visible to the device
1111  *
1112  * Map the pages of a ttm_tt object to an address space visible
1113  * to the underlying device.
1114  */
1115 static int amdgpu_ttm_tt_populate(struct ttm_device *bdev,
1116                                   struct ttm_tt *ttm,
1117                                   struct ttm_operation_ctx *ctx)
1118 {
1119         struct amdgpu_device *adev = amdgpu_ttm_adev(bdev);
1120         struct amdgpu_ttm_tt *gtt = (void *)ttm;
1121
1122         /* user pages are bound by amdgpu_ttm_tt_pin_userptr() */
1123         if (gtt && gtt->userptr) {
1124                 ttm->sg = kzalloc(sizeof(struct sg_table), GFP_KERNEL);
1125                 if (!ttm->sg)
1126                         return -ENOMEM;
1127                 return 0;
1128         }
1129
1130         if (ttm->page_flags & TTM_PAGE_FLAG_SG)
1131                 return 0;
1132
1133         return ttm_pool_alloc(&adev->mman.bdev.pool, ttm, ctx);
1134 }
1135
1136 /*
1137  * amdgpu_ttm_tt_unpopulate - unmap GTT pages and unpopulate page arrays
1138  *
1139  * Unmaps pages of a ttm_tt object from the device address space and
1140  * unpopulates the page array backing it.
1141  */
1142 static void amdgpu_ttm_tt_unpopulate(struct ttm_device *bdev,
1143                                      struct ttm_tt *ttm)
1144 {
1145         struct amdgpu_ttm_tt *gtt = (void *)ttm;
1146         struct amdgpu_device *adev;
1147
1148         if (gtt && gtt->userptr) {
1149                 amdgpu_ttm_tt_set_user_pages(ttm, NULL);
1150                 kfree(ttm->sg);
1151                 ttm->sg = NULL;
1152                 return;
1153         }
1154
1155         if (ttm->page_flags & TTM_PAGE_FLAG_SG)
1156                 return;
1157
1158         adev = amdgpu_ttm_adev(bdev);
1159         return ttm_pool_free(&adev->mman.bdev.pool, ttm);
1160 }
1161
1162 /**
1163  * amdgpu_ttm_tt_set_userptr - Initialize userptr GTT ttm_tt for the current
1164  * task
1165  *
1166  * @bo: The ttm_buffer_object to bind this userptr to
1167  * @addr:  The address in the current tasks VM space to use
1168  * @flags: Requirements of userptr object.
1169  *
1170  * Called by amdgpu_gem_userptr_ioctl() to bind userptr pages
1171  * to current task
1172  */
1173 int amdgpu_ttm_tt_set_userptr(struct ttm_buffer_object *bo,
1174                               uint64_t addr, uint32_t flags)
1175 {
1176         struct amdgpu_ttm_tt *gtt;
1177
1178         if (!bo->ttm) {
1179                 /* TODO: We want a separate TTM object type for userptrs */
1180                 bo->ttm = amdgpu_ttm_tt_create(bo, 0);
1181                 if (bo->ttm == NULL)
1182                         return -ENOMEM;
1183         }
1184
1185         /* Set TTM_PAGE_FLAG_SG before populate but after create. */
1186         bo->ttm->page_flags |= TTM_PAGE_FLAG_SG;
1187
1188         gtt = (void *)bo->ttm;
1189         gtt->userptr = addr;
1190         gtt->userflags = flags;
1191
1192         if (gtt->usertask)
1193                 put_task_struct(gtt->usertask);
1194         gtt->usertask = current->group_leader;
1195         get_task_struct(gtt->usertask);
1196
1197         return 0;
1198 }
1199
1200 /*
1201  * amdgpu_ttm_tt_get_usermm - Return memory manager for ttm_tt object
1202  */
1203 struct mm_struct *amdgpu_ttm_tt_get_usermm(struct ttm_tt *ttm)
1204 {
1205         struct amdgpu_ttm_tt *gtt = (void *)ttm;
1206
1207         if (gtt == NULL)
1208                 return NULL;
1209
1210         if (gtt->usertask == NULL)
1211                 return NULL;
1212
1213         return gtt->usertask->mm;
1214 }
1215
1216 /*
1217  * amdgpu_ttm_tt_affect_userptr - Determine if a ttm_tt object lays inside an
1218  * address range for the current task.
1219  *
1220  */
1221 bool amdgpu_ttm_tt_affect_userptr(struct ttm_tt *ttm, unsigned long start,
1222                                   unsigned long end)
1223 {
1224         struct amdgpu_ttm_tt *gtt = (void *)ttm;
1225         unsigned long size;
1226
1227         if (gtt == NULL || !gtt->userptr)
1228                 return false;
1229
1230         /* Return false if no part of the ttm_tt object lies within
1231          * the range
1232          */
1233         size = (unsigned long)gtt->ttm.num_pages * PAGE_SIZE;
1234         if (gtt->userptr > end || gtt->userptr + size <= start)
1235                 return false;
1236
1237         return true;
1238 }
1239
1240 /*
1241  * amdgpu_ttm_tt_is_userptr - Have the pages backing by userptr?
1242  */
1243 bool amdgpu_ttm_tt_is_userptr(struct ttm_tt *ttm)
1244 {
1245         struct amdgpu_ttm_tt *gtt = (void *)ttm;
1246
1247         if (gtt == NULL || !gtt->userptr)
1248                 return false;
1249
1250         return true;
1251 }
1252
1253 /*
1254  * amdgpu_ttm_tt_is_readonly - Is the ttm_tt object read only?
1255  */
1256 bool amdgpu_ttm_tt_is_readonly(struct ttm_tt *ttm)
1257 {
1258         struct amdgpu_ttm_tt *gtt = (void *)ttm;
1259
1260         if (gtt == NULL)
1261                 return false;
1262
1263         return !!(gtt->userflags & AMDGPU_GEM_USERPTR_READONLY);
1264 }
1265
1266 /**
1267  * amdgpu_ttm_tt_pde_flags - Compute PDE flags for ttm_tt object
1268  *
1269  * @ttm: The ttm_tt object to compute the flags for
1270  * @mem: The memory registry backing this ttm_tt object
1271  *
1272  * Figure out the flags to use for a VM PDE (Page Directory Entry).
1273  */
1274 uint64_t amdgpu_ttm_tt_pde_flags(struct ttm_tt *ttm, struct ttm_resource *mem)
1275 {
1276         uint64_t flags = 0;
1277
1278         if (mem && mem->mem_type != TTM_PL_SYSTEM)
1279                 flags |= AMDGPU_PTE_VALID;
1280
1281         if (mem && (mem->mem_type == TTM_PL_TT ||
1282                     mem->mem_type == AMDGPU_PL_PREEMPT)) {
1283                 flags |= AMDGPU_PTE_SYSTEM;
1284
1285                 if (ttm->caching == ttm_cached)
1286                         flags |= AMDGPU_PTE_SNOOPED;
1287         }
1288
1289         if (mem && mem->mem_type == TTM_PL_VRAM &&
1290                         mem->bus.caching == ttm_cached)
1291                 flags |= AMDGPU_PTE_SNOOPED;
1292
1293         return flags;
1294 }
1295
1296 /**
1297  * amdgpu_ttm_tt_pte_flags - Compute PTE flags for ttm_tt object
1298  *
1299  * @adev: amdgpu_device pointer
1300  * @ttm: The ttm_tt object to compute the flags for
1301  * @mem: The memory registry backing this ttm_tt object
1302  *
1303  * Figure out the flags to use for a VM PTE (Page Table Entry).
1304  */
1305 uint64_t amdgpu_ttm_tt_pte_flags(struct amdgpu_device *adev, struct ttm_tt *ttm,
1306                                  struct ttm_resource *mem)
1307 {
1308         uint64_t flags = amdgpu_ttm_tt_pde_flags(ttm, mem);
1309
1310         flags |= adev->gart.gart_pte_flags;
1311         flags |= AMDGPU_PTE_READABLE;
1312
1313         if (!amdgpu_ttm_tt_is_readonly(ttm))
1314                 flags |= AMDGPU_PTE_WRITEABLE;
1315
1316         return flags;
1317 }
1318
1319 /*
1320  * amdgpu_ttm_bo_eviction_valuable - Check to see if we can evict a buffer
1321  * object.
1322  *
1323  * Return true if eviction is sensible. Called by ttm_mem_evict_first() on
1324  * behalf of ttm_bo_mem_force_space() which tries to evict buffer objects until
1325  * it can find space for a new object and by ttm_bo_force_list_clean() which is
1326  * used to clean out a memory space.
1327  */
1328 static bool amdgpu_ttm_bo_eviction_valuable(struct ttm_buffer_object *bo,
1329                                             const struct ttm_place *place)
1330 {
1331         unsigned long num_pages = bo->resource->num_pages;
1332         struct amdgpu_res_cursor cursor;
1333         struct dma_resv_list *flist;
1334         struct dma_fence *f;
1335         int i;
1336
1337         /* Swapout? */
1338         if (bo->resource->mem_type == TTM_PL_SYSTEM)
1339                 return true;
1340
1341         if (bo->type == ttm_bo_type_kernel &&
1342             !amdgpu_vm_evictable(ttm_to_amdgpu_bo(bo)))
1343                 return false;
1344
1345         /* If bo is a KFD BO, check if the bo belongs to the current process.
1346          * If true, then return false as any KFD process needs all its BOs to
1347          * be resident to run successfully
1348          */
1349         flist = dma_resv_shared_list(bo->base.resv);
1350         if (flist) {
1351                 for (i = 0; i < flist->shared_count; ++i) {
1352                         f = rcu_dereference_protected(flist->shared[i],
1353                                 dma_resv_held(bo->base.resv));
1354                         if (amdkfd_fence_check_mm(f, current->mm))
1355                                 return false;
1356                 }
1357         }
1358
1359         switch (bo->resource->mem_type) {
1360         case AMDGPU_PL_PREEMPT:
1361                 /* Preemptible BOs don't own system resources managed by the
1362                  * driver (pages, VRAM, GART space). They point to resources
1363                  * owned by someone else (e.g. pageable memory in user mode
1364                  * or a DMABuf). They are used in a preemptible context so we
1365                  * can guarantee no deadlocks and good QoS in case of MMU
1366                  * notifiers or DMABuf move notifiers from the resource owner.
1367                  */
1368                 return false;
1369         case TTM_PL_TT:
1370                 if (amdgpu_bo_is_amdgpu_bo(bo) &&
1371                     amdgpu_bo_encrypted(ttm_to_amdgpu_bo(bo)))
1372                         return false;
1373                 return true;
1374
1375         case TTM_PL_VRAM:
1376                 /* Check each drm MM node individually */
1377                 amdgpu_res_first(bo->resource, 0, (u64)num_pages << PAGE_SHIFT,
1378                                  &cursor);
1379                 while (cursor.remaining) {
1380                         if (place->fpfn < PFN_DOWN(cursor.start + cursor.size)
1381                             && !(place->lpfn &&
1382                                  place->lpfn <= PFN_DOWN(cursor.start)))
1383                                 return true;
1384
1385                         amdgpu_res_next(&cursor, cursor.size);
1386                 }
1387                 return false;
1388
1389         default:
1390                 break;
1391         }
1392
1393         return ttm_bo_eviction_valuable(bo, place);
1394 }
1395
1396 /**
1397  * amdgpu_ttm_access_memory - Read or Write memory that backs a buffer object.
1398  *
1399  * @bo:  The buffer object to read/write
1400  * @offset:  Offset into buffer object
1401  * @buf:  Secondary buffer to write/read from
1402  * @len: Length in bytes of access
1403  * @write:  true if writing
1404  *
1405  * This is used to access VRAM that backs a buffer object via MMIO
1406  * access for debugging purposes.
1407  */
1408 static int amdgpu_ttm_access_memory(struct ttm_buffer_object *bo,
1409                                     unsigned long offset, void *buf, int len,
1410                                     int write)
1411 {
1412         struct amdgpu_bo *abo = ttm_to_amdgpu_bo(bo);
1413         struct amdgpu_device *adev = amdgpu_ttm_adev(abo->tbo.bdev);
1414         struct amdgpu_res_cursor cursor;
1415         unsigned long flags;
1416         uint32_t value = 0;
1417         int ret = 0;
1418
1419         if (bo->resource->mem_type != TTM_PL_VRAM)
1420                 return -EIO;
1421
1422         amdgpu_res_first(bo->resource, offset, len, &cursor);
1423         while (cursor.remaining) {
1424                 uint64_t aligned_pos = cursor.start & ~(uint64_t)3;
1425                 uint64_t bytes = 4 - (cursor.start & 3);
1426                 uint32_t shift = (cursor.start & 3) * 8;
1427                 uint32_t mask = 0xffffffff << shift;
1428
1429                 if (cursor.size < bytes) {
1430                         mask &= 0xffffffff >> (bytes - cursor.size) * 8;
1431                         bytes = cursor.size;
1432                 }
1433
1434                 if (mask != 0xffffffff) {
1435                         spin_lock_irqsave(&adev->mmio_idx_lock, flags);
1436                         WREG32_NO_KIQ(mmMM_INDEX, ((uint32_t)aligned_pos) | 0x80000000);
1437                         WREG32_NO_KIQ(mmMM_INDEX_HI, aligned_pos >> 31);
1438                         value = RREG32_NO_KIQ(mmMM_DATA);
1439                         if (write) {
1440                                 value &= ~mask;
1441                                 value |= (*(uint32_t *)buf << shift) & mask;
1442                                 WREG32_NO_KIQ(mmMM_DATA, value);
1443                         }
1444                         spin_unlock_irqrestore(&adev->mmio_idx_lock, flags);
1445                         if (!write) {
1446                                 value = (value & mask) >> shift;
1447                                 memcpy(buf, &value, bytes);
1448                         }
1449                 } else {
1450                         bytes = cursor.size & ~0x3ULL;
1451                         amdgpu_device_vram_access(adev, cursor.start,
1452                                                   (uint32_t *)buf, bytes,
1453                                                   write);
1454                 }
1455
1456                 ret += bytes;
1457                 buf = (uint8_t *)buf + bytes;
1458                 amdgpu_res_next(&cursor, bytes);
1459         }
1460
1461         return ret;
1462 }
1463
1464 static void
1465 amdgpu_bo_delete_mem_notify(struct ttm_buffer_object *bo)
1466 {
1467         amdgpu_bo_move_notify(bo, false, NULL);
1468 }
1469
1470 static struct ttm_device_funcs amdgpu_bo_driver = {
1471         .ttm_tt_create = &amdgpu_ttm_tt_create,
1472         .ttm_tt_populate = &amdgpu_ttm_tt_populate,
1473         .ttm_tt_unpopulate = &amdgpu_ttm_tt_unpopulate,
1474         .ttm_tt_destroy = &amdgpu_ttm_backend_destroy,
1475         .eviction_valuable = amdgpu_ttm_bo_eviction_valuable,
1476         .evict_flags = &amdgpu_evict_flags,
1477         .move = &amdgpu_bo_move,
1478         .delete_mem_notify = &amdgpu_bo_delete_mem_notify,
1479         .release_notify = &amdgpu_bo_release_notify,
1480         .io_mem_reserve = &amdgpu_ttm_io_mem_reserve,
1481         .io_mem_pfn = amdgpu_ttm_io_mem_pfn,
1482         .access_memory = &amdgpu_ttm_access_memory,
1483         .del_from_lru_notify = &amdgpu_vm_del_from_lru_notify
1484 };
1485
1486 /*
1487  * Firmware Reservation functions
1488  */
1489 /**
1490  * amdgpu_ttm_fw_reserve_vram_fini - free fw reserved vram
1491  *
1492  * @adev: amdgpu_device pointer
1493  *
1494  * free fw reserved vram if it has been reserved.
1495  */
1496 static void amdgpu_ttm_fw_reserve_vram_fini(struct amdgpu_device *adev)
1497 {
1498         amdgpu_bo_free_kernel(&adev->mman.fw_vram_usage_reserved_bo,
1499                 NULL, &adev->mman.fw_vram_usage_va);
1500 }
1501
1502 /**
1503  * amdgpu_ttm_fw_reserve_vram_init - create bo vram reservation from fw
1504  *
1505  * @adev: amdgpu_device pointer
1506  *
1507  * create bo vram reservation from fw.
1508  */
1509 static int amdgpu_ttm_fw_reserve_vram_init(struct amdgpu_device *adev)
1510 {
1511         uint64_t vram_size = adev->gmc.visible_vram_size;
1512
1513         adev->mman.fw_vram_usage_va = NULL;
1514         adev->mman.fw_vram_usage_reserved_bo = NULL;
1515
1516         if (adev->mman.fw_vram_usage_size == 0 ||
1517             adev->mman.fw_vram_usage_size > vram_size)
1518                 return 0;
1519
1520         return amdgpu_bo_create_kernel_at(adev,
1521                                           adev->mman.fw_vram_usage_start_offset,
1522                                           adev->mman.fw_vram_usage_size,
1523                                           AMDGPU_GEM_DOMAIN_VRAM,
1524                                           &adev->mman.fw_vram_usage_reserved_bo,
1525                                           &adev->mman.fw_vram_usage_va);
1526 }
1527
1528 /*
1529  * Memoy training reservation functions
1530  */
1531
1532 /**
1533  * amdgpu_ttm_training_reserve_vram_fini - free memory training reserved vram
1534  *
1535  * @adev: amdgpu_device pointer
1536  *
1537  * free memory training reserved vram if it has been reserved.
1538  */
1539 static int amdgpu_ttm_training_reserve_vram_fini(struct amdgpu_device *adev)
1540 {
1541         struct psp_memory_training_context *ctx = &adev->psp.mem_train_ctx;
1542
1543         ctx->init = PSP_MEM_TRAIN_NOT_SUPPORT;
1544         amdgpu_bo_free_kernel(&ctx->c2p_bo, NULL, NULL);
1545         ctx->c2p_bo = NULL;
1546
1547         return 0;
1548 }
1549
1550 static void amdgpu_ttm_training_data_block_init(struct amdgpu_device *adev)
1551 {
1552         struct psp_memory_training_context *ctx = &adev->psp.mem_train_ctx;
1553
1554         memset(ctx, 0, sizeof(*ctx));
1555
1556         ctx->c2p_train_data_offset =
1557                 ALIGN((adev->gmc.mc_vram_size - adev->mman.discovery_tmr_size - SZ_1M), SZ_1M);
1558         ctx->p2c_train_data_offset =
1559                 (adev->gmc.mc_vram_size - GDDR6_MEM_TRAINING_OFFSET);
1560         ctx->train_data_size =
1561                 GDDR6_MEM_TRAINING_DATA_SIZE_IN_BYTES;
1562
1563         DRM_DEBUG("train_data_size:%llx,p2c_train_data_offset:%llx,c2p_train_data_offset:%llx.\n",
1564                         ctx->train_data_size,
1565                         ctx->p2c_train_data_offset,
1566                         ctx->c2p_train_data_offset);
1567 }
1568
1569 /*
1570  * reserve TMR memory at the top of VRAM which holds
1571  * IP Discovery data and is protected by PSP.
1572  */
1573 static int amdgpu_ttm_reserve_tmr(struct amdgpu_device *adev)
1574 {
1575         int ret;
1576         struct psp_memory_training_context *ctx = &adev->psp.mem_train_ctx;
1577         bool mem_train_support = false;
1578
1579         if (!amdgpu_sriov_vf(adev)) {
1580                 if (amdgpu_atomfirmware_mem_training_supported(adev))
1581                         mem_train_support = true;
1582                 else
1583                         DRM_DEBUG("memory training does not support!\n");
1584         }
1585
1586         /*
1587          * Query reserved tmr size through atom firmwareinfo for Sienna_Cichlid and onwards for all
1588          * the use cases (IP discovery/G6 memory training/profiling/diagnostic data.etc)
1589          *
1590          * Otherwise, fallback to legacy approach to check and reserve tmr block for ip
1591          * discovery data and G6 memory training data respectively
1592          */
1593         adev->mman.discovery_tmr_size =
1594                 amdgpu_atomfirmware_get_fw_reserved_fb_size(adev);
1595         if (!adev->mman.discovery_tmr_size)
1596                 adev->mman.discovery_tmr_size = DISCOVERY_TMR_OFFSET;
1597
1598         if (mem_train_support) {
1599                 /* reserve vram for mem train according to TMR location */
1600                 amdgpu_ttm_training_data_block_init(adev);
1601                 ret = amdgpu_bo_create_kernel_at(adev,
1602                                          ctx->c2p_train_data_offset,
1603                                          ctx->train_data_size,
1604                                          AMDGPU_GEM_DOMAIN_VRAM,
1605                                          &ctx->c2p_bo,
1606                                          NULL);
1607                 if (ret) {
1608                         DRM_ERROR("alloc c2p_bo failed(%d)!\n", ret);
1609                         amdgpu_ttm_training_reserve_vram_fini(adev);
1610                         return ret;
1611                 }
1612                 ctx->init = PSP_MEM_TRAIN_RESERVE_SUCCESS;
1613         }
1614
1615         ret = amdgpu_bo_create_kernel_at(adev,
1616                                 adev->gmc.real_vram_size - adev->mman.discovery_tmr_size,
1617                                 adev->mman.discovery_tmr_size,
1618                                 AMDGPU_GEM_DOMAIN_VRAM,
1619                                 &adev->mman.discovery_memory,
1620                                 NULL);
1621         if (ret) {
1622                 DRM_ERROR("alloc tmr failed(%d)!\n", ret);
1623                 amdgpu_bo_free_kernel(&adev->mman.discovery_memory, NULL, NULL);
1624                 return ret;
1625         }
1626
1627         return 0;
1628 }
1629
1630 /*
1631  * amdgpu_ttm_init - Init the memory management (ttm) as well as various
1632  * gtt/vram related fields.
1633  *
1634  * This initializes all of the memory space pools that the TTM layer
1635  * will need such as the GTT space (system memory mapped to the device),
1636  * VRAM (on-board memory), and on-chip memories (GDS, GWS, OA) which
1637  * can be mapped per VMID.
1638  */
1639 int amdgpu_ttm_init(struct amdgpu_device *adev)
1640 {
1641         uint64_t gtt_size;
1642         int r;
1643         u64 vis_vram_limit;
1644
1645         mutex_init(&adev->mman.gtt_window_lock);
1646
1647         /* No others user of address space so set it to 0 */
1648         r = ttm_device_init(&adev->mman.bdev, &amdgpu_bo_driver, adev->dev,
1649                                adev_to_drm(adev)->anon_inode->i_mapping,
1650                                adev_to_drm(adev)->vma_offset_manager,
1651                                adev->need_swiotlb,
1652                                dma_addressing_limited(adev->dev));
1653         if (r) {
1654                 DRM_ERROR("failed initializing buffer object driver(%d).\n", r);
1655                 return r;
1656         }
1657         adev->mman.initialized = true;
1658
1659         /* Initialize VRAM pool with all of VRAM divided into pages */
1660         r = amdgpu_vram_mgr_init(adev);
1661         if (r) {
1662                 DRM_ERROR("Failed initializing VRAM heap.\n");
1663                 return r;
1664         }
1665
1666         /* Reduce size of CPU-visible VRAM if requested */
1667         vis_vram_limit = (u64)amdgpu_vis_vram_limit * 1024 * 1024;
1668         if (amdgpu_vis_vram_limit > 0 &&
1669             vis_vram_limit <= adev->gmc.visible_vram_size)
1670                 adev->gmc.visible_vram_size = vis_vram_limit;
1671
1672         /* Change the size here instead of the init above so only lpfn is affected */
1673         amdgpu_ttm_set_buffer_funcs_status(adev, false);
1674 #ifdef CONFIG_64BIT
1675 #ifdef CONFIG_X86
1676         if (adev->gmc.xgmi.connected_to_cpu)
1677                 adev->mman.aper_base_kaddr = ioremap_cache(adev->gmc.aper_base,
1678                                 adev->gmc.visible_vram_size);
1679
1680         else
1681 #endif
1682                 adev->mman.aper_base_kaddr = ioremap_wc(adev->gmc.aper_base,
1683                                 adev->gmc.visible_vram_size);
1684 #endif
1685
1686         /*
1687          *The reserved vram for firmware must be pinned to the specified
1688          *place on the VRAM, so reserve it early.
1689          */
1690         r = amdgpu_ttm_fw_reserve_vram_init(adev);
1691         if (r) {
1692                 return r;
1693         }
1694
1695         /*
1696          * only NAVI10 and onwards ASIC support for IP discovery.
1697          * If IP discovery enabled, a block of memory should be
1698          * reserved for IP discovey.
1699          */
1700         if (adev->mman.discovery_bin) {
1701                 r = amdgpu_ttm_reserve_tmr(adev);
1702                 if (r)
1703                         return r;
1704         }
1705
1706         /* allocate memory as required for VGA
1707          * This is used for VGA emulation and pre-OS scanout buffers to
1708          * avoid display artifacts while transitioning between pre-OS
1709          * and driver.  */
1710         r = amdgpu_bo_create_kernel_at(adev, 0, adev->mman.stolen_vga_size,
1711                                        AMDGPU_GEM_DOMAIN_VRAM,
1712                                        &adev->mman.stolen_vga_memory,
1713                                        NULL);
1714         if (r)
1715                 return r;
1716         r = amdgpu_bo_create_kernel_at(adev, adev->mman.stolen_vga_size,
1717                                        adev->mman.stolen_extended_size,
1718                                        AMDGPU_GEM_DOMAIN_VRAM,
1719                                        &adev->mman.stolen_extended_memory,
1720                                        NULL);
1721         if (r)
1722                 return r;
1723         r = amdgpu_bo_create_kernel_at(adev, adev->mman.stolen_reserved_offset,
1724                                        adev->mman.stolen_reserved_size,
1725                                        AMDGPU_GEM_DOMAIN_VRAM,
1726                                        &adev->mman.stolen_reserved_memory,
1727                                        NULL);
1728         if (r)
1729                 return r;
1730
1731         DRM_INFO("amdgpu: %uM of VRAM memory ready\n",
1732                  (unsigned) (adev->gmc.real_vram_size / (1024 * 1024)));
1733
1734         /* Compute GTT size, either bsaed on 3/4th the size of RAM size
1735          * or whatever the user passed on module init */
1736         if (amdgpu_gtt_size == -1) {
1737                 struct sysinfo si;
1738
1739                 si_meminfo(&si);
1740                 gtt_size = min(max((AMDGPU_DEFAULT_GTT_SIZE_MB << 20),
1741                                adev->gmc.mc_vram_size),
1742                                ((uint64_t)si.totalram * si.mem_unit * 3/4));
1743         }
1744         else
1745                 gtt_size = (uint64_t)amdgpu_gtt_size << 20;
1746
1747         /* Initialize GTT memory pool */
1748         r = amdgpu_gtt_mgr_init(adev, gtt_size);
1749         if (r) {
1750                 DRM_ERROR("Failed initializing GTT heap.\n");
1751                 return r;
1752         }
1753         DRM_INFO("amdgpu: %uM of GTT memory ready.\n",
1754                  (unsigned)(gtt_size / (1024 * 1024)));
1755
1756         /* Initialize preemptible memory pool */
1757         r = amdgpu_preempt_mgr_init(adev);
1758         if (r) {
1759                 DRM_ERROR("Failed initializing PREEMPT heap.\n");
1760                 return r;
1761         }
1762
1763         /* Initialize various on-chip memory pools */
1764         r = amdgpu_ttm_init_on_chip(adev, AMDGPU_PL_GDS, adev->gds.gds_size);
1765         if (r) {
1766                 DRM_ERROR("Failed initializing GDS heap.\n");
1767                 return r;
1768         }
1769
1770         r = amdgpu_ttm_init_on_chip(adev, AMDGPU_PL_GWS, adev->gds.gws_size);
1771         if (r) {
1772                 DRM_ERROR("Failed initializing gws heap.\n");
1773                 return r;
1774         }
1775
1776         r = amdgpu_ttm_init_on_chip(adev, AMDGPU_PL_OA, adev->gds.oa_size);
1777         if (r) {
1778                 DRM_ERROR("Failed initializing oa heap.\n");
1779                 return r;
1780         }
1781
1782         return 0;
1783 }
1784
1785 /*
1786  * amdgpu_ttm_fini - De-initialize the TTM memory pools
1787  */
1788 void amdgpu_ttm_fini(struct amdgpu_device *adev)
1789 {
1790         if (!adev->mman.initialized)
1791                 return;
1792
1793         amdgpu_ttm_training_reserve_vram_fini(adev);
1794         /* return the stolen vga memory back to VRAM */
1795         amdgpu_bo_free_kernel(&adev->mman.stolen_vga_memory, NULL, NULL);
1796         amdgpu_bo_free_kernel(&adev->mman.stolen_extended_memory, NULL, NULL);
1797         /* return the IP Discovery TMR memory back to VRAM */
1798         amdgpu_bo_free_kernel(&adev->mman.discovery_memory, NULL, NULL);
1799         if (adev->mman.stolen_reserved_size)
1800                 amdgpu_bo_free_kernel(&adev->mman.stolen_reserved_memory,
1801                                       NULL, NULL);
1802         amdgpu_ttm_fw_reserve_vram_fini(adev);
1803
1804         amdgpu_vram_mgr_fini(adev);
1805         amdgpu_gtt_mgr_fini(adev);
1806         amdgpu_preempt_mgr_fini(adev);
1807         ttm_range_man_fini(&adev->mman.bdev, AMDGPU_PL_GDS);
1808         ttm_range_man_fini(&adev->mman.bdev, AMDGPU_PL_GWS);
1809         ttm_range_man_fini(&adev->mman.bdev, AMDGPU_PL_OA);
1810         ttm_device_fini(&adev->mman.bdev);
1811         adev->mman.initialized = false;
1812         DRM_INFO("amdgpu: ttm finalized\n");
1813 }
1814
1815 /**
1816  * amdgpu_ttm_set_buffer_funcs_status - enable/disable use of buffer functions
1817  *
1818  * @adev: amdgpu_device pointer
1819  * @enable: true when we can use buffer functions.
1820  *
1821  * Enable/disable use of buffer functions during suspend/resume. This should
1822  * only be called at bootup or when userspace isn't running.
1823  */
1824 void amdgpu_ttm_set_buffer_funcs_status(struct amdgpu_device *adev, bool enable)
1825 {
1826         struct ttm_resource_manager *man = ttm_manager_type(&adev->mman.bdev, TTM_PL_VRAM);
1827         uint64_t size;
1828         int r;
1829
1830         if (!adev->mman.initialized || amdgpu_in_reset(adev) ||
1831             adev->mman.buffer_funcs_enabled == enable)
1832                 return;
1833
1834         if (enable) {
1835                 struct amdgpu_ring *ring;
1836                 struct drm_gpu_scheduler *sched;
1837
1838                 ring = adev->mman.buffer_funcs_ring;
1839                 sched = &ring->sched;
1840                 r = drm_sched_entity_init(&adev->mman.entity,
1841                                           DRM_SCHED_PRIORITY_KERNEL, &sched,
1842                                           1, NULL);
1843                 if (r) {
1844                         DRM_ERROR("Failed setting up TTM BO move entity (%d)\n",
1845                                   r);
1846                         return;
1847                 }
1848         } else {
1849                 drm_sched_entity_destroy(&adev->mman.entity);
1850                 dma_fence_put(man->move);
1851                 man->move = NULL;
1852         }
1853
1854         /* this just adjusts TTM size idea, which sets lpfn to the correct value */
1855         if (enable)
1856                 size = adev->gmc.real_vram_size;
1857         else
1858                 size = adev->gmc.visible_vram_size;
1859         man->size = size >> PAGE_SHIFT;
1860         adev->mman.buffer_funcs_enabled = enable;
1861 }
1862
1863 int amdgpu_copy_buffer(struct amdgpu_ring *ring, uint64_t src_offset,
1864                        uint64_t dst_offset, uint32_t byte_count,
1865                        struct dma_resv *resv,
1866                        struct dma_fence **fence, bool direct_submit,
1867                        bool vm_needs_flush, bool tmz)
1868 {
1869         enum amdgpu_ib_pool_type pool = direct_submit ? AMDGPU_IB_POOL_DIRECT :
1870                 AMDGPU_IB_POOL_DELAYED;
1871         struct amdgpu_device *adev = ring->adev;
1872         struct amdgpu_job *job;
1873
1874         uint32_t max_bytes;
1875         unsigned num_loops, num_dw;
1876         unsigned i;
1877         int r;
1878
1879         if (direct_submit && !ring->sched.ready) {
1880                 DRM_ERROR("Trying to move memory with ring turned off.\n");
1881                 return -EINVAL;
1882         }
1883
1884         max_bytes = adev->mman.buffer_funcs->copy_max_bytes;
1885         num_loops = DIV_ROUND_UP(byte_count, max_bytes);
1886         num_dw = ALIGN(num_loops * adev->mman.buffer_funcs->copy_num_dw, 8);
1887
1888         r = amdgpu_job_alloc_with_ib(adev, num_dw * 4, pool, &job);
1889         if (r)
1890                 return r;
1891
1892         if (vm_needs_flush) {
1893                 job->vm_pd_addr = amdgpu_gmc_pd_addr(adev->gmc.pdb0_bo ?
1894                                         adev->gmc.pdb0_bo : adev->gart.bo);
1895                 job->vm_needs_flush = true;
1896         }
1897         if (resv) {
1898                 r = amdgpu_sync_resv(adev, &job->sync, resv,
1899                                      AMDGPU_SYNC_ALWAYS,
1900                                      AMDGPU_FENCE_OWNER_UNDEFINED);
1901                 if (r) {
1902                         DRM_ERROR("sync failed (%d).\n", r);
1903                         goto error_free;
1904                 }
1905         }
1906
1907         for (i = 0; i < num_loops; i++) {
1908                 uint32_t cur_size_in_bytes = min(byte_count, max_bytes);
1909
1910                 amdgpu_emit_copy_buffer(adev, &job->ibs[0], src_offset,
1911                                         dst_offset, cur_size_in_bytes, tmz);
1912
1913                 src_offset += cur_size_in_bytes;
1914                 dst_offset += cur_size_in_bytes;
1915                 byte_count -= cur_size_in_bytes;
1916         }
1917
1918         amdgpu_ring_pad_ib(ring, &job->ibs[0]);
1919         WARN_ON(job->ibs[0].length_dw > num_dw);
1920         if (direct_submit)
1921                 r = amdgpu_job_submit_direct(job, ring, fence);
1922         else
1923                 r = amdgpu_job_submit(job, &adev->mman.entity,
1924                                       AMDGPU_FENCE_OWNER_UNDEFINED, fence);
1925         if (r)
1926                 goto error_free;
1927
1928         return r;
1929
1930 error_free:
1931         amdgpu_job_free(job);
1932         DRM_ERROR("Error scheduling IBs (%d)\n", r);
1933         return r;
1934 }
1935
1936 int amdgpu_fill_buffer(struct amdgpu_bo *bo,
1937                        uint32_t src_data,
1938                        struct dma_resv *resv,
1939                        struct dma_fence **fence)
1940 {
1941         struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
1942         uint32_t max_bytes = adev->mman.buffer_funcs->fill_max_bytes;
1943         struct amdgpu_ring *ring = adev->mman.buffer_funcs_ring;
1944
1945         struct amdgpu_res_cursor cursor;
1946         unsigned int num_loops, num_dw;
1947         uint64_t num_bytes;
1948
1949         struct amdgpu_job *job;
1950         int r;
1951
1952         if (!adev->mman.buffer_funcs_enabled) {
1953                 DRM_ERROR("Trying to clear memory with ring turned off.\n");
1954                 return -EINVAL;
1955         }
1956
1957         if (bo->tbo.resource->mem_type == AMDGPU_PL_PREEMPT) {
1958                 DRM_ERROR("Trying to clear preemptible memory.\n");
1959                 return -EINVAL;
1960         }
1961
1962         if (bo->tbo.resource->mem_type == TTM_PL_TT) {
1963                 r = amdgpu_ttm_alloc_gart(&bo->tbo);
1964                 if (r)
1965                         return r;
1966         }
1967
1968         num_bytes = bo->tbo.resource->num_pages << PAGE_SHIFT;
1969         num_loops = 0;
1970
1971         amdgpu_res_first(bo->tbo.resource, 0, num_bytes, &cursor);
1972         while (cursor.remaining) {
1973                 num_loops += DIV_ROUND_UP_ULL(cursor.size, max_bytes);
1974                 amdgpu_res_next(&cursor, cursor.size);
1975         }
1976         num_dw = num_loops * adev->mman.buffer_funcs->fill_num_dw;
1977
1978         /* for IB padding */
1979         num_dw += 64;
1980
1981         r = amdgpu_job_alloc_with_ib(adev, num_dw * 4, AMDGPU_IB_POOL_DELAYED,
1982                                      &job);
1983         if (r)
1984                 return r;
1985
1986         if (resv) {
1987                 r = amdgpu_sync_resv(adev, &job->sync, resv,
1988                                      AMDGPU_SYNC_ALWAYS,
1989                                      AMDGPU_FENCE_OWNER_UNDEFINED);
1990                 if (r) {
1991                         DRM_ERROR("sync failed (%d).\n", r);
1992                         goto error_free;
1993                 }
1994         }
1995
1996         amdgpu_res_first(bo->tbo.resource, 0, num_bytes, &cursor);
1997         while (cursor.remaining) {
1998                 uint32_t cur_size = min_t(uint64_t, cursor.size, max_bytes);
1999                 uint64_t dst_addr = cursor.start;
2000
2001                 dst_addr += amdgpu_ttm_domain_start(adev,
2002                                                     bo->tbo.resource->mem_type);
2003                 amdgpu_emit_fill_buffer(adev, &job->ibs[0], src_data, dst_addr,
2004                                         cur_size);
2005
2006                 amdgpu_res_next(&cursor, cur_size);
2007         }
2008
2009         amdgpu_ring_pad_ib(ring, &job->ibs[0]);
2010         WARN_ON(job->ibs[0].length_dw > num_dw);
2011         r = amdgpu_job_submit(job, &adev->mman.entity,
2012                               AMDGPU_FENCE_OWNER_UNDEFINED, fence);
2013         if (r)
2014                 goto error_free;
2015
2016         return 0;
2017
2018 error_free:
2019         amdgpu_job_free(job);
2020         return r;
2021 }
2022
2023 #if defined(CONFIG_DEBUG_FS)
2024
2025 static int amdgpu_mm_vram_table_show(struct seq_file *m, void *unused)
2026 {
2027         struct amdgpu_device *adev = (struct amdgpu_device *)m->private;
2028         struct ttm_resource_manager *man = ttm_manager_type(&adev->mman.bdev,
2029                                                             TTM_PL_VRAM);
2030         struct drm_printer p = drm_seq_file_printer(m);
2031
2032         man->func->debug(man, &p);
2033         return 0;
2034 }
2035
2036 static int amdgpu_ttm_page_pool_show(struct seq_file *m, void *unused)
2037 {
2038         struct amdgpu_device *adev = (struct amdgpu_device *)m->private;
2039
2040         return ttm_pool_debugfs(&adev->mman.bdev.pool, m);
2041 }
2042
2043 static int amdgpu_mm_tt_table_show(struct seq_file *m, void *unused)
2044 {
2045         struct amdgpu_device *adev = (struct amdgpu_device *)m->private;
2046         struct ttm_resource_manager *man = ttm_manager_type(&adev->mman.bdev,
2047                                                             TTM_PL_TT);
2048         struct drm_printer p = drm_seq_file_printer(m);
2049
2050         man->func->debug(man, &p);
2051         return 0;
2052 }
2053
2054 static int amdgpu_mm_gds_table_show(struct seq_file *m, void *unused)
2055 {
2056         struct amdgpu_device *adev = (struct amdgpu_device *)m->private;
2057         struct ttm_resource_manager *man = ttm_manager_type(&adev->mman.bdev,
2058                                                             AMDGPU_PL_GDS);
2059         struct drm_printer p = drm_seq_file_printer(m);
2060
2061         man->func->debug(man, &p);
2062         return 0;
2063 }
2064
2065 static int amdgpu_mm_gws_table_show(struct seq_file *m, void *unused)
2066 {
2067         struct amdgpu_device *adev = (struct amdgpu_device *)m->private;
2068         struct ttm_resource_manager *man = ttm_manager_type(&adev->mman.bdev,
2069                                                             AMDGPU_PL_GWS);
2070         struct drm_printer p = drm_seq_file_printer(m);
2071
2072         man->func->debug(man, &p);
2073         return 0;
2074 }
2075
2076 static int amdgpu_mm_oa_table_show(struct seq_file *m, void *unused)
2077 {
2078         struct amdgpu_device *adev = (struct amdgpu_device *)m->private;
2079         struct ttm_resource_manager *man = ttm_manager_type(&adev->mman.bdev,
2080                                                             AMDGPU_PL_OA);
2081         struct drm_printer p = drm_seq_file_printer(m);
2082
2083         man->func->debug(man, &p);
2084         return 0;
2085 }
2086
2087 DEFINE_SHOW_ATTRIBUTE(amdgpu_mm_vram_table);
2088 DEFINE_SHOW_ATTRIBUTE(amdgpu_mm_tt_table);
2089 DEFINE_SHOW_ATTRIBUTE(amdgpu_mm_gds_table);
2090 DEFINE_SHOW_ATTRIBUTE(amdgpu_mm_gws_table);
2091 DEFINE_SHOW_ATTRIBUTE(amdgpu_mm_oa_table);
2092 DEFINE_SHOW_ATTRIBUTE(amdgpu_ttm_page_pool);
2093
2094 /*
2095  * amdgpu_ttm_vram_read - Linear read access to VRAM
2096  *
2097  * Accesses VRAM via MMIO for debugging purposes.
2098  */
2099 static ssize_t amdgpu_ttm_vram_read(struct file *f, char __user *buf,
2100                                     size_t size, loff_t *pos)
2101 {
2102         struct amdgpu_device *adev = file_inode(f)->i_private;
2103         ssize_t result = 0;
2104
2105         if (size & 0x3 || *pos & 0x3)
2106                 return -EINVAL;
2107
2108         if (*pos >= adev->gmc.mc_vram_size)
2109                 return -ENXIO;
2110
2111         size = min(size, (size_t)(adev->gmc.mc_vram_size - *pos));
2112         while (size) {
2113                 size_t bytes = min(size, AMDGPU_TTM_VRAM_MAX_DW_READ * 4);
2114                 uint32_t value[AMDGPU_TTM_VRAM_MAX_DW_READ];
2115
2116                 amdgpu_device_vram_access(adev, *pos, value, bytes, false);
2117                 if (copy_to_user(buf, value, bytes))
2118                         return -EFAULT;
2119
2120                 result += bytes;
2121                 buf += bytes;
2122                 *pos += bytes;
2123                 size -= bytes;
2124         }
2125
2126         return result;
2127 }
2128
2129 /*
2130  * amdgpu_ttm_vram_write - Linear write access to VRAM
2131  *
2132  * Accesses VRAM via MMIO for debugging purposes.
2133  */
2134 static ssize_t amdgpu_ttm_vram_write(struct file *f, const char __user *buf,
2135                                     size_t size, loff_t *pos)
2136 {
2137         struct amdgpu_device *adev = file_inode(f)->i_private;
2138         ssize_t result = 0;
2139         int r;
2140
2141         if (size & 0x3 || *pos & 0x3)
2142                 return -EINVAL;
2143
2144         if (*pos >= adev->gmc.mc_vram_size)
2145                 return -ENXIO;
2146
2147         while (size) {
2148                 uint32_t value;
2149
2150                 if (*pos >= adev->gmc.mc_vram_size)
2151                         return result;
2152
2153                 r = get_user(value, (uint32_t *)buf);
2154                 if (r)
2155                         return r;
2156
2157                 amdgpu_device_mm_access(adev, *pos, &value, 4, true);
2158
2159                 result += 4;
2160                 buf += 4;
2161                 *pos += 4;
2162                 size -= 4;
2163         }
2164
2165         return result;
2166 }
2167
2168 static const struct file_operations amdgpu_ttm_vram_fops = {
2169         .owner = THIS_MODULE,
2170         .read = amdgpu_ttm_vram_read,
2171         .write = amdgpu_ttm_vram_write,
2172         .llseek = default_llseek,
2173 };
2174
2175 /*
2176  * amdgpu_iomem_read - Virtual read access to GPU mapped memory
2177  *
2178  * This function is used to read memory that has been mapped to the
2179  * GPU and the known addresses are not physical addresses but instead
2180  * bus addresses (e.g., what you'd put in an IB or ring buffer).
2181  */
2182 static ssize_t amdgpu_iomem_read(struct file *f, char __user *buf,
2183                                  size_t size, loff_t *pos)
2184 {
2185         struct amdgpu_device *adev = file_inode(f)->i_private;
2186         struct iommu_domain *dom;
2187         ssize_t result = 0;
2188         int r;
2189
2190         /* retrieve the IOMMU domain if any for this device */
2191         dom = iommu_get_domain_for_dev(adev->dev);
2192
2193         while (size) {
2194                 phys_addr_t addr = *pos & PAGE_MASK;
2195                 loff_t off = *pos & ~PAGE_MASK;
2196                 size_t bytes = PAGE_SIZE - off;
2197                 unsigned long pfn;
2198                 struct page *p;
2199                 void *ptr;
2200
2201                 bytes = bytes < size ? bytes : size;
2202
2203                 /* Translate the bus address to a physical address.  If
2204                  * the domain is NULL it means there is no IOMMU active
2205                  * and the address translation is the identity
2206                  */
2207                 addr = dom ? iommu_iova_to_phys(dom, addr) : addr;
2208
2209                 pfn = addr >> PAGE_SHIFT;
2210                 if (!pfn_valid(pfn))
2211                         return -EPERM;
2212
2213                 p = pfn_to_page(pfn);
2214                 if (p->mapping != adev->mman.bdev.dev_mapping)
2215                         return -EPERM;
2216
2217                 ptr = kmap(p);
2218                 r = copy_to_user(buf, ptr + off, bytes);
2219                 kunmap(p);
2220                 if (r)
2221                         return -EFAULT;
2222
2223                 size -= bytes;
2224                 *pos += bytes;
2225                 result += bytes;
2226         }
2227
2228         return result;
2229 }
2230
2231 /*
2232  * amdgpu_iomem_write - Virtual write access to GPU mapped memory
2233  *
2234  * This function is used to write memory that has been mapped to the
2235  * GPU and the known addresses are not physical addresses but instead
2236  * bus addresses (e.g., what you'd put in an IB or ring buffer).
2237  */
2238 static ssize_t amdgpu_iomem_write(struct file *f, const char __user *buf,
2239                                  size_t size, loff_t *pos)
2240 {
2241         struct amdgpu_device *adev = file_inode(f)->i_private;
2242         struct iommu_domain *dom;
2243         ssize_t result = 0;
2244         int r;
2245
2246         dom = iommu_get_domain_for_dev(adev->dev);
2247
2248         while (size) {
2249                 phys_addr_t addr = *pos & PAGE_MASK;
2250                 loff_t off = *pos & ~PAGE_MASK;
2251                 size_t bytes = PAGE_SIZE - off;
2252                 unsigned long pfn;
2253                 struct page *p;
2254                 void *ptr;
2255
2256                 bytes = bytes < size ? bytes : size;
2257
2258                 addr = dom ? iommu_iova_to_phys(dom, addr) : addr;
2259
2260                 pfn = addr >> PAGE_SHIFT;
2261                 if (!pfn_valid(pfn))
2262                         return -EPERM;
2263
2264                 p = pfn_to_page(pfn);
2265                 if (p->mapping != adev->mman.bdev.dev_mapping)
2266                         return -EPERM;
2267
2268                 ptr = kmap(p);
2269                 r = copy_from_user(ptr + off, buf, bytes);
2270                 kunmap(p);
2271                 if (r)
2272                         return -EFAULT;
2273
2274                 size -= bytes;
2275                 *pos += bytes;
2276                 result += bytes;
2277         }
2278
2279         return result;
2280 }
2281
2282 static const struct file_operations amdgpu_ttm_iomem_fops = {
2283         .owner = THIS_MODULE,
2284         .read = amdgpu_iomem_read,
2285         .write = amdgpu_iomem_write,
2286         .llseek = default_llseek
2287 };
2288
2289 #endif
2290
2291 void amdgpu_ttm_debugfs_init(struct amdgpu_device *adev)
2292 {
2293 #if defined(CONFIG_DEBUG_FS)
2294         struct drm_minor *minor = adev_to_drm(adev)->primary;
2295         struct dentry *root = minor->debugfs_root;
2296
2297         debugfs_create_file_size("amdgpu_vram", 0444, root, adev,
2298                                  &amdgpu_ttm_vram_fops, adev->gmc.mc_vram_size);
2299         debugfs_create_file("amdgpu_iomem", 0444, root, adev,
2300                             &amdgpu_ttm_iomem_fops);
2301         debugfs_create_file("amdgpu_vram_mm", 0444, root, adev,
2302                             &amdgpu_mm_vram_table_fops);
2303         debugfs_create_file("amdgpu_gtt_mm", 0444, root, adev,
2304                             &amdgpu_mm_tt_table_fops);
2305         debugfs_create_file("amdgpu_gds_mm", 0444, root, adev,
2306                             &amdgpu_mm_gds_table_fops);
2307         debugfs_create_file("amdgpu_gws_mm", 0444, root, adev,
2308                             &amdgpu_mm_gws_table_fops);
2309         debugfs_create_file("amdgpu_oa_mm", 0444, root, adev,
2310                             &amdgpu_mm_oa_table_fops);
2311         debugfs_create_file("ttm_page_pool", 0444, root, adev,
2312                             &amdgpu_ttm_page_pool_fops);
2313 #endif
2314 }