drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c

   1 /*
   2  * Copyright 2009 Jerome Glisse.
   3  * All Rights Reserved.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the
   7  * "Software"), to deal in the Software without restriction, including
   8  * without limitation the rights to use, copy, modify, merge, publish,
   9  * distribute, sub license, and/or sell copies of the Software, and to
  10  * permit persons to whom the Software is furnished to do so, subject to
  11  * the following conditions:
  12  *
  13  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  14  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  15  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  16  * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
  17  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  18  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  19  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  20  *
  21  * The above copyright notice and this permission notice (including the
  22  * next paragraph) shall be included in all copies or substantial portions
  23  * of the Software.
  24  *
  25  */
  26 /*
  27  * Authors:
  28  *    Jerome Glisse <glisse@freedesktop.org>
  29  *    Thomas Hellstrom <thomas-at-tungstengraphics-dot-com>
  30  *    Dave Airlie
  31  */
  32
  33 #include <linux/dma-mapping.h>
  34 #include <linux/iommu.h>
  35 #include <linux/hmm.h>
  36 #include <linux/pagemap.h>
  37 #include <linux/sched/task.h>
  38 #include <linux/sched/mm.h>
  39 #include <linux/seq_file.h>
  40 #include <linux/slab.h>
  41 #include <linux/swap.h>
  42 #include <linux/swiotlb.h>
  43 #include <linux/dma-buf.h>
  44 #include <linux/sizes.h>
  45
  46 #include <drm/ttm/ttm_bo_api.h>
  47 #include <drm/ttm/ttm_bo_driver.h>
  48 #include <drm/ttm/ttm_placement.h>
  49 #include <drm/ttm/ttm_module.h>
  50
  51 #include <drm/drm_debugfs.h>
  52 #include <drm/amdgpu_drm.h>
  53
  54 #include "amdgpu.h"
  55 #include "amdgpu_object.h"
  56 #include "amdgpu_trace.h"
  57 #include "amdgpu_amdkfd.h"
  58 #include "amdgpu_sdma.h"
  59 #include "amdgpu_ras.h"
  60 #include "amdgpu_atomfirmware.h"
  61 #include "bif/bif_4_1_d.h"
  62
  63 #define AMDGPU_TTM_VRAM_MAX_DW_READ     (size_t)128
  64
  65 static int amdgpu_ttm_backend_bind(struct ttm_bo_device *bdev,
  66                                    struct ttm_tt *ttm,
  67                                    struct ttm_resource *bo_mem);
  68 static void amdgpu_ttm_backend_unbind(struct ttm_bo_device *bdev,
  69                                       struct ttm_tt *ttm);
  70
  71 static int amdgpu_ttm_init_on_chip(struct amdgpu_device *adev,
  72                                     unsigned int type,
  73                                     uint64_t size)
  74 {
  75         return ttm_range_man_init(&adev->mman.bdev, type,
  76                                   false, size >> PAGE_SHIFT);
  77 }
  78
  79 /**
  80  * amdgpu_evict_flags - Compute placement flags
  81  *
  82  * @bo: The buffer object to evict
  83  * @placement: Possible destination(s) for evicted BO
  84  *
  85  * Fill in placement data when ttm_bo_evict() is called
  86  */
  87 static void amdgpu_evict_flags(struct ttm_buffer_object *bo,
  88                                 struct ttm_placement *placement)
  89 {
  90         struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev);
  91         struct amdgpu_bo *abo;
  92         static const struct ttm_place placements = {
  93                 .fpfn = 0,
  94                 .lpfn = 0,
  95                 .mem_type = TTM_PL_SYSTEM,
  96                 .flags = 0
  97         };
  98
  99         /* Don't handle scatter gather BOs */
 100         if (bo->type == ttm_bo_type_sg) {
 101                 placement->num_placement = 0;
 102                 placement->num_busy_placement = 0;
 103                 return;
 104         }
 105
 106         /* Object isn't an AMDGPU object so ignore */
 107         if (!amdgpu_bo_is_amdgpu_bo(bo)) {
 108                 placement->placement = &placements;
 109                 placement->busy_placement = &placements;
 110                 placement->num_placement = 1;
 111                 placement->num_busy_placement = 1;
 112                 return;
 113         }
 114
 115         abo = ttm_to_amdgpu_bo(bo);
 116         switch (bo->mem.mem_type) {
 117         case AMDGPU_PL_GDS:
 118         case AMDGPU_PL_GWS:
 119         case AMDGPU_PL_OA:
 120                 placement->num_placement = 0;
 121                 placement->num_busy_placement = 0;
 122                 return;
 123
 124         case TTM_PL_VRAM:
 125                 if (!adev->mman.buffer_funcs_enabled) {
 126                         /* Move to system memory */
 127                         amdgpu_bo_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_CPU);
 128                 } else if (!amdgpu_gmc_vram_full_visible(&adev->gmc) &&
 129                            !(abo->flags & AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED) &&
 130                            amdgpu_bo_in_cpu_visible_vram(abo)) {
 131
 132                         /* Try evicting to the CPU inaccessible part of VRAM
 133                          * first, but only set GTT as busy placement, so this
 134                          * BO will be evicted to GTT rather than causing other
 135                          * BOs to be evicted from VRAM
 136                          */
 137                         amdgpu_bo_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_VRAM |
 138                                                          AMDGPU_GEM_DOMAIN_GTT);
 139                         abo->placements[0].fpfn = adev->gmc.visible_vram_size >> PAGE_SHIFT;
 140                         abo->placements[0].lpfn = 0;
 141                         abo->placement.busy_placement = &abo->placements[1];
 142                         abo->placement.num_busy_placement = 1;
 143                 } else {
 144                         /* Move to GTT memory */
 145                         amdgpu_bo_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_GTT);
 146                 }
 147                 break;
 148         case TTM_PL_TT:
 149         default:
 150                 amdgpu_bo_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_CPU);
 151                 break;
 152         }
 153         *placement = abo->placement;
 154 }
 155
 156 /**
 157  * amdgpu_verify_access - Verify access for a mmap call
 158  *
 159  * @bo: The buffer object to map
 160  * @filp: The file pointer from the process performing the mmap
 161  *
 162  * This is called by ttm_bo_mmap() to verify whether a process
 163  * has the right to mmap a BO to their process space.
 164  */
 165 static int amdgpu_verify_access(struct ttm_buffer_object *bo, struct file *filp)
 166 {
 167         struct amdgpu_bo *abo = ttm_to_amdgpu_bo(bo);
 168
 169         /*
 170          * Don't verify access for KFD BOs. They don't have a GEM
 171          * object associated with them.
 172          */
 173         if (abo->kfd_bo)
 174                 return 0;
 175
 176         if (amdgpu_ttm_tt_get_usermm(bo->ttm))
 177                 return -EPERM;
 178         return drm_vma_node_verify_access(&abo->tbo.base.vma_node,
 179                                           filp->private_data);
 180 }
 181
 182 /**
 183  * amdgpu_mm_node_addr - Compute the GPU relative offset of a GTT buffer.
 184  *
 185  * @bo: The bo to assign the memory to.
 186  * @mm_node: Memory manager node for drm allocator.
 187  * @mem: The region where the bo resides.
 188  *
 189  */
 190 static uint64_t amdgpu_mm_node_addr(struct ttm_buffer_object *bo,
 191                                     struct drm_mm_node *mm_node,
 192                                     struct ttm_resource *mem)
 193 {
 194         uint64_t addr = 0;
 195
 196         if (mm_node->start != AMDGPU_BO_INVALID_OFFSET) {
 197                 addr = mm_node->start << PAGE_SHIFT;
 198                 addr += amdgpu_ttm_domain_start(amdgpu_ttm_adev(bo->bdev),
 199                                                 mem->mem_type);
 200         }
 201         return addr;
 202 }
 203
 204 /**
 205  * amdgpu_find_mm_node - Helper function finds the drm_mm_node corresponding to
 206  * @offset. It also modifies the offset to be within the drm_mm_node returned
 207  *
 208  * @mem: The region where the bo resides.
 209  * @offset: The offset that drm_mm_node is used for finding.
 210  *
 211  */
 212 static struct drm_mm_node *amdgpu_find_mm_node(struct ttm_resource *mem,
 213                                                uint64_t *offset)
 214 {
 215         struct drm_mm_node *mm_node = mem->mm_node;
 216
 217         while (*offset >= (mm_node->size << PAGE_SHIFT)) {
 218                 *offset -= (mm_node->size << PAGE_SHIFT);
 219                 ++mm_node;
 220         }
 221         return mm_node;
 222 }
 223
 224 /**
 225  * amdgpu_ttm_map_buffer - Map memory into the GART windows
 226  * @bo: buffer object to map
 227  * @mem: memory object to map
 228  * @mm_node: drm_mm node object to map
 229  * @num_pages: number of pages to map
 230  * @offset: offset into @mm_node where to start
 231  * @window: which GART window to use
 232  * @ring: DMA ring to use for the copy
 233  * @tmz: if we should setup a TMZ enabled mapping
 234  * @addr: resulting address inside the MC address space
 235  *
 236  * Setup one of the GART windows to access a specific piece of memory or return
 237  * the physical address for local memory.
 238  */
 239 static int amdgpu_ttm_map_buffer(struct ttm_buffer_object *bo,
 240                                  struct ttm_resource *mem,
 241                                  struct drm_mm_node *mm_node,
 242                                  unsigned num_pages, uint64_t offset,
 243                                  unsigned window, struct amdgpu_ring *ring,
 244                                  bool tmz, uint64_t *addr)
 245 {
 246         struct amdgpu_device *adev = ring->adev;
 247         struct amdgpu_job *job;
 248         unsigned num_dw, num_bytes;
 249         struct dma_fence *fence;
 250         uint64_t src_addr, dst_addr;
 251         void *cpu_addr;
 252         uint64_t flags;
 253         unsigned int i;
 254         int r;
 255
 256         BUG_ON(adev->mman.buffer_funcs->copy_max_bytes <
 257                AMDGPU_GTT_MAX_TRANSFER_SIZE * 8);
 258
 259         /* Map only what can't be accessed directly */
 260         if (!tmz && mem->start != AMDGPU_BO_INVALID_OFFSET) {
 261                 *addr = amdgpu_mm_node_addr(bo, mm_node, mem) + offset;
 262                 return 0;
 263         }
 264
 265         *addr = adev->gmc.gart_start;
 266         *addr += (u64)window * AMDGPU_GTT_MAX_TRANSFER_SIZE *
 267                 AMDGPU_GPU_PAGE_SIZE;
 268         *addr += offset & ~PAGE_MASK;
 269
 270         num_dw = ALIGN(adev->mman.buffer_funcs->copy_num_dw, 8);
 271         num_bytes = num_pages * 8;
 272
 273         r = amdgpu_job_alloc_with_ib(adev, num_dw * 4 + num_bytes,
 274                                      AMDGPU_IB_POOL_DELAYED, &job);
 275         if (r)
 276                 return r;
 277
 278         src_addr = num_dw * 4;
 279         src_addr += job->ibs[0].gpu_addr;
 280
 281         dst_addr = amdgpu_bo_gpu_offset(adev->gart.bo);
 282         dst_addr += window * AMDGPU_GTT_MAX_TRANSFER_SIZE * 8;
 283         amdgpu_emit_copy_buffer(adev, &job->ibs[0], src_addr,
 284                                 dst_addr, num_bytes, false);
 285
 286         amdgpu_ring_pad_ib(ring, &job->ibs[0]);
 287         WARN_ON(job->ibs[0].length_dw > num_dw);
 288
 289         flags = amdgpu_ttm_tt_pte_flags(adev, bo->ttm, mem);
 290         if (tmz)
 291                 flags |= AMDGPU_PTE_TMZ;
 292
 293         cpu_addr = &job->ibs[0].ptr[num_dw];
 294
 295         if (mem->mem_type == TTM_PL_TT) {
 296                 dma_addr_t *dma_address;
 297
 298                 dma_address = &bo->ttm->dma_address[offset >> PAGE_SHIFT];
 299                 r = amdgpu_gart_map(adev, 0, num_pages, dma_address, flags,
 300                                     cpu_addr);
 301                 if (r)
 302                         goto error_free;
 303         } else {
 304                 dma_addr_t dma_address;
 305
 306                 dma_address = (mm_node->start << PAGE_SHIFT) + offset;
 307                 dma_address += adev->vm_manager.vram_base_offset;
 308
 309                 for (i = 0; i < num_pages; ++i) {
 310                         r = amdgpu_gart_map(adev, i << PAGE_SHIFT, 1,
 311                                             &dma_address, flags, cpu_addr);
 312                         if (r)
 313                                 goto error_free;
 314
 315                         dma_address += PAGE_SIZE;
 316                 }
 317         }
 318
 319         r = amdgpu_job_submit(job, &adev->mman.entity,
 320                               AMDGPU_FENCE_OWNER_UNDEFINED, &fence);
 321         if (r)
 322                 goto error_free;
 323
 324         dma_fence_put(fence);
 325
 326         return r;
 327
 328 error_free:
 329         amdgpu_job_free(job);
 330         return r;
 331 }
 332
 333 /**
 334  * amdgpu_copy_ttm_mem_to_mem - Helper function for copy
 335  * @adev: amdgpu device
 336  * @src: buffer/address where to read from
 337  * @dst: buffer/address where to write to
 338  * @size: number of bytes to copy
 339  * @tmz: if a secure copy should be used
 340  * @resv: resv object to sync to
 341  * @f: Returns the last fence if multiple jobs are submitted.
 342  *
 343  * The function copies @size bytes from {src->mem + src->offset} to
 344  * {dst->mem + dst->offset}. src->bo and dst->bo could be same BO for a
 345  * move and different for a BO to BO copy.
 346  *
 347  */
 348 int amdgpu_ttm_copy_mem_to_mem(struct amdgpu_device *adev,
 349                                const struct amdgpu_copy_mem *src,
 350                                const struct amdgpu_copy_mem *dst,
 351                                uint64_t size, bool tmz,
 352                                struct dma_resv *resv,
 353                                struct dma_fence **f)
 354 {
 355         const uint32_t GTT_MAX_BYTES = (AMDGPU_GTT_MAX_TRANSFER_SIZE *
 356                                         AMDGPU_GPU_PAGE_SIZE);
 357
 358         uint64_t src_node_size, dst_node_size, src_offset, dst_offset;
 359         struct amdgpu_ring *ring = adev->mman.buffer_funcs_ring;
 360         struct drm_mm_node *src_mm, *dst_mm;
 361         struct dma_fence *fence = NULL;
 362         int r = 0;
 363
 364         if (!adev->mman.buffer_funcs_enabled) {
 365                 DRM_ERROR("Trying to move memory with ring turned off.\n");
 366                 return -EINVAL;
 367         }
 368
 369         src_offset = src->offset;
 370         if (src->mem->mm_node) {
 371                 src_mm = amdgpu_find_mm_node(src->mem, &src_offset);
 372                 src_node_size = (src_mm->size << PAGE_SHIFT) - src_offset;
 373         } else {
 374                 src_mm = NULL;
 375                 src_node_size = ULLONG_MAX;
 376         }
 377
 378         dst_offset = dst->offset;
 379         if (dst->mem->mm_node) {
 380                 dst_mm = amdgpu_find_mm_node(dst->mem, &dst_offset);
 381                 dst_node_size = (dst_mm->size << PAGE_SHIFT) - dst_offset;
 382         } else {
 383                 dst_mm = NULL;
 384                 dst_node_size = ULLONG_MAX;
 385         }
 386
 387         mutex_lock(&adev->mman.gtt_window_lock);
 388
 389         while (size) {
 390                 uint32_t src_page_offset = src_offset & ~PAGE_MASK;
 391                 uint32_t dst_page_offset = dst_offset & ~PAGE_MASK;
 392                 struct dma_fence *next;
 393                 uint32_t cur_size;
 394                 uint64_t from, to;
 395
 396                 /* Copy size cannot exceed GTT_MAX_BYTES. So if src or dst
 397                  * begins at an offset, then adjust the size accordingly
 398                  */
 399                 cur_size = max(src_page_offset, dst_page_offset);
 400                 cur_size = min(min3(src_node_size, dst_node_size, size),
 401                                (uint64_t)(GTT_MAX_BYTES - cur_size));
 402
 403                 /* Map src to window 0 and dst to window 1. */
 404                 r = amdgpu_ttm_map_buffer(src->bo, src->mem, src_mm,
 405                                           PFN_UP(cur_size + src_page_offset),
 406                                           src_offset, 0, ring, tmz, &from);
 407                 if (r)
 408                         goto error;
 409
 410                 r = amdgpu_ttm_map_buffer(dst->bo, dst->mem, dst_mm,
 411                                           PFN_UP(cur_size + dst_page_offset),
 412                                           dst_offset, 1, ring, tmz, &to);
 413                 if (r)
 414                         goto error;
 415
 416                 r = amdgpu_copy_buffer(ring, from, to, cur_size,
 417                                        resv, &next, false, true, tmz);
 418                 if (r)
 419                         goto error;
 420
 421                 dma_fence_put(fence);
 422                 fence = next;
 423
 424                 size -= cur_size;
 425                 if (!size)
 426                         break;
 427
 428                 src_node_size -= cur_size;
 429                 if (!src_node_size) {
 430                         ++src_mm;
 431                         src_node_size = src_mm->size << PAGE_SHIFT;
 432                         src_offset = 0;
 433                 } else {
 434                         src_offset += cur_size;
 435                 }
 436
 437                 dst_node_size -= cur_size;
 438                 if (!dst_node_size) {
 439                         ++dst_mm;
 440                         dst_node_size = dst_mm->size << PAGE_SHIFT;
 441                         dst_offset = 0;
 442                 } else {
 443                         dst_offset += cur_size;
 444                 }
 445         }
 446 error:
 447         mutex_unlock(&adev->mman.gtt_window_lock);
 448         if (f)
 449                 *f = dma_fence_get(fence);
 450         dma_fence_put(fence);
 451         return r;
 452 }
 453
 454 /**
 455  * amdgpu_move_blit - Copy an entire buffer to another buffer
 456  *
 457  * This is a helper called by amdgpu_bo_move() and amdgpu_move_vram_ram() to
 458  * help move buffers to and from VRAM.
 459  */
 460 static int amdgpu_move_blit(struct ttm_buffer_object *bo,
 461                             bool evict,
 462                             struct ttm_resource *new_mem,
 463                             struct ttm_resource *old_mem)
 464 {
 465         struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev);
 466         struct amdgpu_bo *abo = ttm_to_amdgpu_bo(bo);
 467         struct amdgpu_copy_mem src, dst;
 468         struct dma_fence *fence = NULL;
 469         int r;
 470
 471         src.bo = bo;
 472         dst.bo = bo;
 473         src.mem = old_mem;
 474         dst.mem = new_mem;
 475         src.offset = 0;
 476         dst.offset = 0;
 477
 478         r = amdgpu_ttm_copy_mem_to_mem(adev, &src, &dst,
 479                                        new_mem->num_pages << PAGE_SHIFT,
 480                                        amdgpu_bo_encrypted(abo),
 481                                        bo->base.resv, &fence);
 482         if (r)
 483                 goto error;
 484
 485         /* clear the space being freed */
 486         if (old_mem->mem_type == TTM_PL_VRAM &&
 487             (abo->flags & AMDGPU_GEM_CREATE_VRAM_WIPE_ON_RELEASE)) {
 488                 struct dma_fence *wipe_fence = NULL;
 489
 490                 r = amdgpu_fill_buffer(ttm_to_amdgpu_bo(bo), AMDGPU_POISON,
 491                                        NULL, &wipe_fence);
 492                 if (r) {
 493                         goto error;
 494                 } else if (wipe_fence) {
 495                         dma_fence_put(fence);
 496                         fence = wipe_fence;
 497                 }
 498         }
 499
 500         /* Always block for VM page tables before committing the new location */
 501         if (bo->type == ttm_bo_type_kernel)
 502                 r = ttm_bo_move_accel_cleanup(bo, fence, true, false, new_mem);
 503         else
 504                 r = ttm_bo_move_accel_cleanup(bo, fence, evict, true, new_mem);
 505         dma_fence_put(fence);
 506         return r;
 507
 508 error:
 509         if (fence)
 510                 dma_fence_wait(fence, false);
 511         dma_fence_put(fence);
 512         return r;
 513 }
 514
 515 /**
 516  * amdgpu_move_vram_ram - Copy VRAM buffer to RAM buffer
 517  *
 518  * Called by amdgpu_bo_move().
 519  */
 520 static int amdgpu_move_vram_ram(struct ttm_buffer_object *bo, bool evict,
 521                                 struct ttm_operation_ctx *ctx,
 522                                 struct ttm_resource *new_mem)
 523 {
 524         struct ttm_resource *old_mem = &bo->mem;
 525         struct ttm_resource tmp_mem;
 526         struct ttm_place placements;
 527         struct ttm_placement placement;
 528         int r;
 529
 530         /* create space/pages for new_mem in GTT space */
 531         tmp_mem = *new_mem;
 532         tmp_mem.mm_node = NULL;
 533         placement.num_placement = 1;
 534         placement.placement = &placements;
 535         placement.num_busy_placement = 1;
 536         placement.busy_placement = &placements;
 537         placements.fpfn = 0;
 538         placements.lpfn = 0;
 539         placements.mem_type = TTM_PL_TT;
 540         placements.flags = 0;
 541         r = ttm_bo_mem_space(bo, &placement, &tmp_mem, ctx);
 542         if (unlikely(r)) {
 543                 pr_err("Failed to find GTT space for blit from VRAM\n");
 544                 return r;
 545         }
 546
 547         r = ttm_tt_populate(bo->bdev, bo->ttm, ctx);
 548         if (unlikely(r))
 549                 goto out_cleanup;
 550
 551         /* Bind the memory to the GTT space */
 552         r = amdgpu_ttm_backend_bind(bo->bdev, bo->ttm, &tmp_mem);
 553         if (unlikely(r)) {
 554                 goto out_cleanup;
 555         }
 556
 557         /* blit VRAM to GTT */
 558         r = amdgpu_move_blit(bo, evict, &tmp_mem, old_mem);
 559         if (unlikely(r)) {
 560                 goto out_cleanup;
 561         }
 562
 563         r = ttm_bo_wait_ctx(bo, ctx);
 564         if (unlikely(r))
 565                 goto out_cleanup;
 566
 567         amdgpu_ttm_backend_unbind(bo->bdev, bo->ttm);
 568         ttm_resource_free(bo, &bo->mem);
 569         ttm_bo_assign_mem(bo, new_mem);
 570 out_cleanup:
 571         ttm_resource_free(bo, &tmp_mem);
 572         return r;
 573 }
 574
 575 /**
 576  * amdgpu_move_ram_vram - Copy buffer from RAM to VRAM
 577  *
 578  * Called by amdgpu_bo_move().
 579  */
 580 static int amdgpu_move_ram_vram(struct ttm_buffer_object *bo, bool evict,
 581                                 struct ttm_operation_ctx *ctx,
 582                                 struct ttm_resource *new_mem)
 583 {
 584         struct ttm_resource *old_mem = &bo->mem;
 585         struct ttm_resource tmp_mem;
 586         struct ttm_placement placement;
 587         struct ttm_place placements;
 588         int r;
 589
 590         /* make space in GTT for old_mem buffer */
 591         tmp_mem = *new_mem;
 592         tmp_mem.mm_node = NULL;
 593         placement.num_placement = 1;
 594         placement.placement = &placements;
 595         placement.num_busy_placement = 1;
 596         placement.busy_placement = &placements;
 597         placements.fpfn = 0;
 598         placements.lpfn = 0;
 599         placements.mem_type = TTM_PL_TT;
 600         placements.flags = 0;
 601         r = ttm_bo_mem_space(bo, &placement, &tmp_mem, ctx);
 602         if (unlikely(r)) {
 603                 pr_err("Failed to find GTT space for blit to VRAM\n");
 604                 return r;
 605         }
 606
 607         /* move/bind old memory to GTT space */
 608         r = ttm_tt_populate(bo->bdev, bo->ttm, ctx);
 609         if (unlikely(r))
 610                 return r;
 611
 612         r = amdgpu_ttm_backend_bind(bo->bdev, bo->ttm, &tmp_mem);
 613         if (unlikely(r)) {
 614                 goto out_cleanup;
 615         }
 616
 617         ttm_bo_assign_mem(bo, &tmp_mem);
 618         /* copy to VRAM */
 619         r = amdgpu_move_blit(bo, evict, new_mem, old_mem);
 620         if (unlikely(r)) {
 621                 goto out_cleanup;
 622         }
 623 out_cleanup:
 624         ttm_resource_free(bo, &tmp_mem);
 625         return r;
 626 }
 627
 628 /**
 629  * amdgpu_mem_visible - Check that memory can be accessed by ttm_bo_move_memcpy
 630  *
 631  * Called by amdgpu_bo_move()
 632  */
 633 static bool amdgpu_mem_visible(struct amdgpu_device *adev,
 634                                struct ttm_resource *mem)
 635 {
 636         struct drm_mm_node *nodes = mem->mm_node;
 637
 638         if (mem->mem_type == TTM_PL_SYSTEM ||
 639             mem->mem_type == TTM_PL_TT)
 640                 return true;
 641         if (mem->mem_type != TTM_PL_VRAM)
 642                 return false;
 643
 644         /* ttm_resource_ioremap only supports contiguous memory */
 645         if (nodes->size != mem->num_pages)
 646                 return false;
 647
 648         return ((nodes->start + nodes->size) << PAGE_SHIFT)
 649                 <= adev->gmc.visible_vram_size;
 650 }
 651
 652 /**
 653  * amdgpu_bo_move - Move a buffer object to a new memory location
 654  *
 655  * Called by ttm_bo_handle_move_mem()
 656  */
 657 static int amdgpu_bo_move(struct ttm_buffer_object *bo, bool evict,
 658                           struct ttm_operation_ctx *ctx,
 659                           struct ttm_resource *new_mem)
 660 {
 661         struct amdgpu_device *adev;
 662         struct amdgpu_bo *abo;
 663         struct ttm_resource *old_mem = &bo->mem;
 664         int r;
 665
 666         if (new_mem->mem_type == TTM_PL_TT) {
 667                 r = amdgpu_ttm_backend_bind(bo->bdev, bo->ttm, new_mem);
 668                 if (r)
 669                         return r;
 670         }
 671
 672         amdgpu_bo_move_notify(bo, evict, new_mem);
 673
 674         /* Can't move a pinned BO */
 675         abo = ttm_to_amdgpu_bo(bo);
 676         if (WARN_ON_ONCE(abo->tbo.pin_count > 0))
 677                 return -EINVAL;
 678
 679         adev = amdgpu_ttm_adev(bo->bdev);
 680
 681         if (old_mem->mem_type == TTM_PL_SYSTEM && bo->ttm == NULL) {
 682                 ttm_bo_move_null(bo, new_mem);
 683                 return 0;
 684         }
 685         if (old_mem->mem_type == TTM_PL_SYSTEM &&
 686             new_mem->mem_type == TTM_PL_TT) {
 687                 ttm_bo_move_null(bo, new_mem);
 688                 return 0;
 689         }
 690
 691         if (old_mem->mem_type == TTM_PL_TT &&
 692             new_mem->mem_type == TTM_PL_SYSTEM) {
 693                 r = ttm_bo_wait_ctx(bo, ctx);
 694                 if (r)
 695                         goto fail;
 696
 697                 amdgpu_ttm_backend_unbind(bo->bdev, bo->ttm);
 698                 ttm_resource_free(bo, &bo->mem);
 699                 ttm_bo_assign_mem(bo, new_mem);
 700                 return 0;
 701         }
 702
 703         if (old_mem->mem_type == AMDGPU_PL_GDS ||
 704             old_mem->mem_type == AMDGPU_PL_GWS ||
 705             old_mem->mem_type == AMDGPU_PL_OA ||
 706             new_mem->mem_type == AMDGPU_PL_GDS ||
 707             new_mem->mem_type == AMDGPU_PL_GWS ||
 708             new_mem->mem_type == AMDGPU_PL_OA) {
 709                 /* Nothing to save here */
 710                 ttm_bo_move_null(bo, new_mem);
 711                 return 0;
 712         }
 713
 714         if (!adev->mman.buffer_funcs_enabled) {
 715                 r = -ENODEV;
 716                 goto memcpy;
 717         }
 718
 719         if (old_mem->mem_type == TTM_PL_VRAM &&
 720             new_mem->mem_type == TTM_PL_SYSTEM) {
 721                 r = amdgpu_move_vram_ram(bo, evict, ctx, new_mem);
 722         } else if (old_mem->mem_type == TTM_PL_SYSTEM &&
 723                    new_mem->mem_type == TTM_PL_VRAM) {
 724                 r = amdgpu_move_ram_vram(bo, evict, ctx, new_mem);
 725         } else {
 726                 r = amdgpu_move_blit(bo, evict,
 727                                      new_mem, old_mem);
 728         }
 729
 730         if (r) {
 731 memcpy:
 732                 /* Check that all memory is CPU accessible */
 733                 if (!amdgpu_mem_visible(adev, old_mem) ||
 734                     !amdgpu_mem_visible(adev, new_mem)) {
 735                         pr_err("Move buffer fallback to memcpy unavailable\n");
 736                         goto fail;
 737                 }
 738
 739                 r = ttm_bo_move_memcpy(bo, ctx, new_mem);
 740                 if (r)
 741                         goto fail;
 742         }
 743
 744         if (bo->type == ttm_bo_type_device &&
 745             new_mem->mem_type == TTM_PL_VRAM &&
 746             old_mem->mem_type != TTM_PL_VRAM) {
 747                 /* amdgpu_bo_fault_reserve_notify will re-set this if the CPU
 748                  * accesses the BO after it's moved.
 749                  */
 750                 abo->flags &= ~AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED;
 751         }
 752
 753         /* update statistics */
 754         atomic64_add((u64)bo->num_pages << PAGE_SHIFT, &adev->num_bytes_moved);
 755         return 0;
 756 fail:
 757         swap(*new_mem, bo->mem);
 758         amdgpu_bo_move_notify(bo, false, new_mem);
 759         swap(*new_mem, bo->mem);
 760         return r;
 761 }
 762
 763 /**
 764  * amdgpu_ttm_io_mem_reserve - Reserve a block of memory during a fault
 765  *
 766  * Called by ttm_mem_io_reserve() ultimately via ttm_bo_vm_fault()
 767  */
 768 static int amdgpu_ttm_io_mem_reserve(struct ttm_bo_device *bdev, struct ttm_resource *mem)
 769 {
 770         struct amdgpu_device *adev = amdgpu_ttm_adev(bdev);
 771         struct drm_mm_node *mm_node = mem->mm_node;
 772         size_t bus_size = (size_t)mem->num_pages << PAGE_SHIFT;
 773
 774         switch (mem->mem_type) {
 775         case TTM_PL_SYSTEM:
 776                 /* system memory */
 777                 return 0;
 778         case TTM_PL_TT:
 779                 break;
 780         case TTM_PL_VRAM:
 781                 mem->bus.offset = mem->start << PAGE_SHIFT;
 782                 /* check if it's visible */
 783                 if ((mem->bus.offset + bus_size) > adev->gmc.visible_vram_size)
 784                         return -EINVAL;
 785                 /* Only physically contiguous buffers apply. In a contiguous
 786                  * buffer, size of the first mm_node would match the number of
 787                  * pages in ttm_resource.
 788                  */
 789                 if (adev->mman.aper_base_kaddr &&
 790                     (mm_node->size == mem->num_pages))
 791                         mem->bus.addr = (u8 *)adev->mman.aper_base_kaddr +
 792                                         mem->bus.offset;
 793
 794                 mem->bus.offset += adev->gmc.aper_base;
 795                 mem->bus.is_iomem = true;
 796                 mem->bus.caching = ttm_write_combined;
 797                 break;
 798         default:
 799                 return -EINVAL;
 800         }
 801         return 0;
 802 }
 803
 804 static unsigned long amdgpu_ttm_io_mem_pfn(struct ttm_buffer_object *bo,
 805                                            unsigned long page_offset)
 806 {
 807         struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev);
 808         uint64_t offset = (page_offset << PAGE_SHIFT);
 809         struct drm_mm_node *mm;
 810
 811         mm = amdgpu_find_mm_node(&bo->mem, &offset);
 812         offset += adev->gmc.aper_base;
 813         return mm->start + (offset >> PAGE_SHIFT);
 814 }
 815
 816 /**
 817  * amdgpu_ttm_domain_start - Returns GPU start address
 818  * @adev: amdgpu device object
 819  * @type: type of the memory
 820  *
 821  * Returns:
 822  * GPU start address of a memory domain
 823  */
 824
 825 uint64_t amdgpu_ttm_domain_start(struct amdgpu_device *adev, uint32_t type)
 826 {
 827         switch (type) {
 828         case TTM_PL_TT:
 829                 return adev->gmc.gart_start;
 830         case TTM_PL_VRAM:
 831                 return adev->gmc.vram_start;
 832         }
 833
 834         return 0;
 835 }
 836
 837 /*
 838  * TTM backend functions.
 839  */
 840 struct amdgpu_ttm_tt {
 841         struct ttm_tt   ttm;
 842         struct drm_gem_object   *gobj;
 843         u64                     offset;
 844         uint64_t                userptr;
 845         struct task_struct      *usertask;
 846         uint32_t                userflags;
 847         bool                    bound;
 848 #if IS_ENABLED(CONFIG_DRM_AMDGPU_USERPTR)
 849         struct hmm_range        *range;
 850 #endif
 851 };
 852
 853 #ifdef CONFIG_DRM_AMDGPU_USERPTR
 854 /**
 855  * amdgpu_ttm_tt_get_user_pages - get device accessible pages that back user
 856  * memory and start HMM tracking CPU page table update
 857  *
 858  * Calling function must call amdgpu_ttm_tt_userptr_range_done() once and only
 859  * once afterwards to stop HMM tracking
 860  */
 861 int amdgpu_ttm_tt_get_user_pages(struct amdgpu_bo *bo, struct page **pages)
 862 {
 863         struct ttm_tt *ttm = bo->tbo.ttm;
 864         struct amdgpu_ttm_tt *gtt = (void *)ttm;
 865         unsigned long start = gtt->userptr;
 866         struct vm_area_struct *vma;
 867         struct hmm_range *range;
 868         unsigned long timeout;
 869         struct mm_struct *mm;
 870         unsigned long i;
 871         int r = 0;
 872
 873         mm = bo->notifier.mm;
 874         if (unlikely(!mm)) {
 875                 DRM_DEBUG_DRIVER("BO is not registered?\n");
 876                 return -EFAULT;
 877         }
 878
 879         /* Another get_user_pages is running at the same time?? */
 880         if (WARN_ON(gtt->range))
 881                 return -EFAULT;
 882
 883         if (!mmget_not_zero(mm)) /* Happens during process shutdown */
 884                 return -ESRCH;
 885
 886         range = kzalloc(sizeof(*range), GFP_KERNEL);
 887         if (unlikely(!range)) {
 888                 r = -ENOMEM;
 889                 goto out;
 890         }
 891         range->notifier = &bo->notifier;
 892         range->start = bo->notifier.interval_tree.start;
 893         range->end = bo->notifier.interval_tree.last + 1;
 894         range->default_flags = HMM_PFN_REQ_FAULT;
 895         if (!amdgpu_ttm_tt_is_readonly(ttm))
 896                 range->default_flags |= HMM_PFN_REQ_WRITE;
 897
 898         range->hmm_pfns = kvmalloc_array(ttm->num_pages,
 899                                          sizeof(*range->hmm_pfns), GFP_KERNEL);
 900         if (unlikely(!range->hmm_pfns)) {
 901                 r = -ENOMEM;
 902                 goto out_free_ranges;
 903         }
 904
 905         mmap_read_lock(mm);
 906         vma = find_vma(mm, start);
 907         if (unlikely(!vma || start < vma->vm_start)) {
 908                 r = -EFAULT;
 909                 goto out_unlock;
 910         }
 911         if (unlikely((gtt->userflags & AMDGPU_GEM_USERPTR_ANONONLY) &&
 912                 vma->vm_file)) {
 913                 r = -EPERM;
 914                 goto out_unlock;
 915         }
 916         mmap_read_unlock(mm);
 917         timeout = jiffies + msecs_to_jiffies(HMM_RANGE_DEFAULT_TIMEOUT);
 918
 919 retry:
 920         range->notifier_seq = mmu_interval_read_begin(&bo->notifier);
 921
 922         mmap_read_lock(mm);
 923         r = hmm_range_fault(range);
 924         mmap_read_unlock(mm);
 925         if (unlikely(r)) {
 926                 /*
 927                  * FIXME: This timeout should encompass the retry from
 928                  * mmu_interval_read_retry() as well.
 929                  */
 930                 if (r == -EBUSY && !time_after(jiffies, timeout))
 931                         goto retry;
 932                 goto out_free_pfns;
 933         }
 934
 935         /*
 936          * Due to default_flags, all pages are HMM_PFN_VALID or
 937          * hmm_range_fault() fails. FIXME: The pages cannot be touched outside
 938          * the notifier_lock, and mmu_interval_read_retry() must be done first.
 939          */
 940         for (i = 0; i < ttm->num_pages; i++)
 941                 pages[i] = hmm_pfn_to_page(range->hmm_pfns[i]);
 942
 943         gtt->range = range;
 944         mmput(mm);
 945
 946         return 0;
 947
 948 out_unlock:
 949         mmap_read_unlock(mm);
 950 out_free_pfns:
 951         kvfree(range->hmm_pfns);
 952 out_free_ranges:
 953         kfree(range);
 954 out:
 955         mmput(mm);
 956         return r;
 957 }
 958
 959 /**
 960  * amdgpu_ttm_tt_userptr_range_done - stop HMM track the CPU page table change
 961  * Check if the pages backing this ttm range have been invalidated
 962  *
 963  * Returns: true if pages are still valid
 964  */
 965 bool amdgpu_ttm_tt_get_user_pages_done(struct ttm_tt *ttm)
 966 {
 967         struct amdgpu_ttm_tt *gtt = (void *)ttm;
 968         bool r = false;
 969
 970         if (!gtt || !gtt->userptr)
 971                 return false;
 972
 973         DRM_DEBUG_DRIVER("user_pages_done 0x%llx pages 0x%x\n",
 974                 gtt->userptr, ttm->num_pages);
 975
 976         WARN_ONCE(!gtt->range || !gtt->range->hmm_pfns,
 977                 "No user pages to check\n");
 978
 979         if (gtt->range) {
 980                 /*
 981                  * FIXME: Must always hold notifier_lock for this, and must
 982                  * not ignore the return code.
 983                  */
 984                 r = mmu_interval_read_retry(gtt->range->notifier,
 985                                          gtt->range->notifier_seq);
 986                 kvfree(gtt->range->hmm_pfns);
 987                 kfree(gtt->range);
 988                 gtt->range = NULL;
 989         }
 990
 991         return !r;
 992 }
 993 #endif
 994
 995 /**
 996  * amdgpu_ttm_tt_set_user_pages - Copy pages in, putting old pages as necessary.
 997  *
 998  * Called by amdgpu_cs_list_validate(). This creates the page list
 999  * that backs user memory and will ultimately be mapped into the device
1000  * address space.
1001  */
1002 void amdgpu_ttm_tt_set_user_pages(struct ttm_tt *ttm, struct page **pages)
1003 {
1004         unsigned long i;
1005
1006         for (i = 0; i < ttm->num_pages; ++i)
1007                 ttm->pages[i] = pages ? pages[i] : NULL;
1008 }
1009
1010 /**
1011  * amdgpu_ttm_tt_pin_userptr -  prepare the sg table with the user pages
1012  *
1013  * Called by amdgpu_ttm_backend_bind()
1014  **/
1015 static int amdgpu_ttm_tt_pin_userptr(struct ttm_bo_device *bdev,
1016                                      struct ttm_tt *ttm)
1017 {
1018         struct amdgpu_device *adev = amdgpu_ttm_adev(bdev);
1019         struct amdgpu_ttm_tt *gtt = (void *)ttm;
1020         int r;
1021
1022         int write = !(gtt->userflags & AMDGPU_GEM_USERPTR_READONLY);
1023         enum dma_data_direction direction = write ?
1024                 DMA_BIDIRECTIONAL : DMA_TO_DEVICE;
1025
1026         /* Allocate an SG array and squash pages into it */
1027         r = sg_alloc_table_from_pages(ttm->sg, ttm->pages, ttm->num_pages, 0,
1028                                       ttm->num_pages << PAGE_SHIFT,
1029                                       GFP_KERNEL);
1030         if (r)
1031                 goto release_sg;
1032
1033         /* Map SG to device */
1034         r = dma_map_sgtable(adev->dev, ttm->sg, direction, 0);
1035         if (r)
1036                 goto release_sg;
1037
1038         /* convert SG to linear array of pages and dma addresses */
1039         drm_prime_sg_to_page_addr_arrays(ttm->sg, ttm->pages,
1040                                          gtt->ttm.dma_address, ttm->num_pages);
1041
1042         return 0;
1043
1044 release_sg:
1045         kfree(ttm->sg);
1046         ttm->sg = NULL;
1047         return r;
1048 }
1049
1050 /**
1051  * amdgpu_ttm_tt_unpin_userptr - Unpin and unmap userptr pages
1052  */
1053 static void amdgpu_ttm_tt_unpin_userptr(struct ttm_bo_device *bdev,
1054                                         struct ttm_tt *ttm)
1055 {
1056         struct amdgpu_device *adev = amdgpu_ttm_adev(bdev);
1057         struct amdgpu_ttm_tt *gtt = (void *)ttm;
1058
1059         int write = !(gtt->userflags & AMDGPU_GEM_USERPTR_READONLY);
1060         enum dma_data_direction direction = write ?
1061                 DMA_BIDIRECTIONAL : DMA_TO_DEVICE;
1062
1063         /* double check that we don't free the table twice */
1064         if (!ttm->sg->sgl)
1065                 return;
1066
1067         /* unmap the pages mapped to the device */
1068         dma_unmap_sgtable(adev->dev, ttm->sg, direction, 0);
1069         sg_free_table(ttm->sg);
1070
1071 #if IS_ENABLED(CONFIG_DRM_AMDGPU_USERPTR)
1072         if (gtt->range) {
1073                 unsigned long i;
1074
1075                 for (i = 0; i < ttm->num_pages; i++) {
1076                         if (ttm->pages[i] !=
1077                             hmm_pfn_to_page(gtt->range->hmm_pfns[i]))
1078                                 break;
1079                 }
1080
1081                 WARN((i == ttm->num_pages), "Missing get_user_page_done\n");
1082         }
1083 #endif
1084 }
1085
1086 static int amdgpu_ttm_gart_bind(struct amdgpu_device *adev,
1087                                 struct ttm_buffer_object *tbo,
1088                                 uint64_t flags)
1089 {
1090         struct amdgpu_bo *abo = ttm_to_amdgpu_bo(tbo);
1091         struct ttm_tt *ttm = tbo->ttm;
1092         struct amdgpu_ttm_tt *gtt = (void *)ttm;
1093         int r;
1094
1095         if (amdgpu_bo_encrypted(abo))
1096                 flags |= AMDGPU_PTE_TMZ;
1097
1098         if (abo->flags & AMDGPU_GEM_CREATE_CP_MQD_GFX9) {
1099                 uint64_t page_idx = 1;
1100
1101                 r = amdgpu_gart_bind(adev, gtt->offset, page_idx,
1102                                 ttm->pages, gtt->ttm.dma_address, flags);
1103                 if (r)
1104                         goto gart_bind_fail;
1105
1106                 /* The memory type of the first page defaults to UC. Now
1107                  * modify the memory type to NC from the second page of
1108                  * the BO onward.
1109                  */
1110                 flags &= ~AMDGPU_PTE_MTYPE_VG10_MASK;
1111                 flags |= AMDGPU_PTE_MTYPE_VG10(AMDGPU_MTYPE_NC);
1112
1113                 r = amdgpu_gart_bind(adev,
1114                                 gtt->offset + (page_idx << PAGE_SHIFT),
1115                                 ttm->num_pages - page_idx,
1116                                 &ttm->pages[page_idx],
1117                                 &(gtt->ttm.dma_address[page_idx]), flags);
1118         } else {
1119                 r = amdgpu_gart_bind(adev, gtt->offset, ttm->num_pages,
1120                                      ttm->pages, gtt->ttm.dma_address, flags);
1121         }
1122
1123 gart_bind_fail:
1124         if (r)
1125                 DRM_ERROR("failed to bind %u pages at 0x%08llX\n",
1126                           ttm->num_pages, gtt->offset);
1127
1128         return r;
1129 }
1130
1131 /**
1132  * amdgpu_ttm_backend_bind - Bind GTT memory
1133  *
1134  * Called by ttm_tt_bind() on behalf of ttm_bo_handle_move_mem().
1135  * This handles binding GTT memory to the device address space.
1136  */
1137 static int amdgpu_ttm_backend_bind(struct ttm_bo_device *bdev,
1138                                    struct ttm_tt *ttm,
1139                                    struct ttm_resource *bo_mem)
1140 {
1141         struct amdgpu_device *adev = amdgpu_ttm_adev(bdev);
1142         struct amdgpu_ttm_tt *gtt = (void*)ttm;
1143         uint64_t flags;
1144         int r = 0;
1145
1146         if (!bo_mem)
1147                 return -EINVAL;
1148
1149         if (gtt->bound)
1150                 return 0;
1151
1152         if (gtt->userptr) {
1153                 r = amdgpu_ttm_tt_pin_userptr(bdev, ttm);
1154                 if (r) {
1155                         DRM_ERROR("failed to pin userptr\n");
1156                         return r;
1157                 }
1158         }
1159         if (!ttm->num_pages) {
1160                 WARN(1, "nothing to bind %u pages for mreg %p back %p!\n",
1161                      ttm->num_pages, bo_mem, ttm);
1162         }
1163
1164         if (bo_mem->mem_type == AMDGPU_PL_GDS ||
1165             bo_mem->mem_type == AMDGPU_PL_GWS ||
1166             bo_mem->mem_type == AMDGPU_PL_OA)
1167                 return -EINVAL;
1168
1169         if (!amdgpu_gtt_mgr_has_gart_addr(bo_mem)) {
1170                 gtt->offset = AMDGPU_BO_INVALID_OFFSET;
1171                 return 0;
1172         }
1173
1174         /* compute PTE flags relevant to this BO memory */
1175         flags = amdgpu_ttm_tt_pte_flags(adev, ttm, bo_mem);
1176
1177         /* bind pages into GART page tables */
1178         gtt->offset = (u64)bo_mem->start << PAGE_SHIFT;
1179         r = amdgpu_gart_bind(adev, gtt->offset, ttm->num_pages,
1180                 ttm->pages, gtt->ttm.dma_address, flags);
1181
1182         if (r)
1183                 DRM_ERROR("failed to bind %u pages at 0x%08llX\n",
1184                           ttm->num_pages, gtt->offset);
1185         gtt->bound = true;
1186         return r;
1187 }
1188
1189 /**
1190  * amdgpu_ttm_alloc_gart - Make sure buffer object is accessible either
1191  * through AGP or GART aperture.
1192  *
1193  * If bo is accessible through AGP aperture, then use AGP aperture
1194  * to access bo; otherwise allocate logical space in GART aperture
1195  * and map bo to GART aperture.
1196  */
1197 int amdgpu_ttm_alloc_gart(struct ttm_buffer_object *bo)
1198 {
1199         struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev);
1200         struct ttm_operation_ctx ctx = { false, false };
1201         struct amdgpu_ttm_tt *gtt = (void*)bo->ttm;
1202         struct ttm_resource tmp;
1203         struct ttm_placement placement;
1204         struct ttm_place placements;
1205         uint64_t addr, flags;
1206         int r;
1207
1208         if (bo->mem.start != AMDGPU_BO_INVALID_OFFSET)
1209                 return 0;
1210
1211         addr = amdgpu_gmc_agp_addr(bo);
1212         if (addr != AMDGPU_BO_INVALID_OFFSET) {
1213                 bo->mem.start = addr >> PAGE_SHIFT;
1214         } else {
1215
1216                 /* allocate GART space */
1217                 tmp = bo->mem;
1218                 tmp.mm_node = NULL;
1219                 placement.num_placement = 1;
1220                 placement.placement = &placements;
1221                 placement.num_busy_placement = 1;
1222                 placement.busy_placement = &placements;
1223                 placements.fpfn = 0;
1224                 placements.lpfn = adev->gmc.gart_size >> PAGE_SHIFT;
1225                 placements.mem_type = TTM_PL_TT;
1226                 placements.flags = bo->mem.placement;
1227
1228                 r = ttm_bo_mem_space(bo, &placement, &tmp, &ctx);
1229                 if (unlikely(r))
1230                         return r;
1231
1232                 /* compute PTE flags for this buffer object */
1233                 flags = amdgpu_ttm_tt_pte_flags(adev, bo->ttm, &tmp);
1234
1235                 /* Bind pages */
1236                 gtt->offset = (u64)tmp.start << PAGE_SHIFT;
1237                 r = amdgpu_ttm_gart_bind(adev, bo, flags);
1238                 if (unlikely(r)) {
1239                         ttm_resource_free(bo, &tmp);
1240                         return r;
1241                 }
1242
1243                 ttm_resource_free(bo, &bo->mem);
1244                 bo->mem = tmp;
1245         }
1246
1247         return 0;
1248 }
1249
1250 /**
1251  * amdgpu_ttm_recover_gart - Rebind GTT pages
1252  *
1253  * Called by amdgpu_gtt_mgr_recover() from amdgpu_device_reset() to
1254  * rebind GTT pages during a GPU reset.
1255  */
1256 int amdgpu_ttm_recover_gart(struct ttm_buffer_object *tbo)
1257 {
1258         struct amdgpu_device *adev = amdgpu_ttm_adev(tbo->bdev);
1259         uint64_t flags;
1260         int r;
1261
1262         if (!tbo->ttm)
1263                 return 0;
1264
1265         flags = amdgpu_ttm_tt_pte_flags(adev, tbo->ttm, &tbo->mem);
1266         r = amdgpu_ttm_gart_bind(adev, tbo, flags);
1267
1268         return r;
1269 }
1270
1271 /**
1272  * amdgpu_ttm_backend_unbind - Unbind GTT mapped pages
1273  *
1274  * Called by ttm_tt_unbind() on behalf of ttm_bo_move_ttm() and
1275  * ttm_tt_destroy().
1276  */
1277 static void amdgpu_ttm_backend_unbind(struct ttm_bo_device *bdev,
1278                                       struct ttm_tt *ttm)
1279 {
1280         struct amdgpu_device *adev = amdgpu_ttm_adev(bdev);
1281         struct amdgpu_ttm_tt *gtt = (void *)ttm;
1282         int r;
1283
1284         if (!gtt->bound)
1285                 return;
1286
1287         /* if the pages have userptr pinning then clear that first */
1288         if (gtt->userptr)
1289                 amdgpu_ttm_tt_unpin_userptr(bdev, ttm);
1290
1291         if (gtt->offset == AMDGPU_BO_INVALID_OFFSET)
1292                 return;
1293
1294         /* unbind shouldn't be done for GDS/GWS/OA in ttm_bo_clean_mm */
1295         r = amdgpu_gart_unbind(adev, gtt->offset, ttm->num_pages);
1296         if (r)
1297                 DRM_ERROR("failed to unbind %u pages at 0x%08llX\n",
1298                           gtt->ttm.num_pages, gtt->offset);
1299         gtt->bound = false;
1300 }
1301
1302 static void amdgpu_ttm_backend_destroy(struct ttm_bo_device *bdev,
1303                                        struct ttm_tt *ttm)
1304 {
1305         struct amdgpu_ttm_tt *gtt = (void *)ttm;
1306
1307         amdgpu_ttm_backend_unbind(bdev, ttm);
1308         ttm_tt_destroy_common(bdev, ttm);
1309         if (gtt->usertask)
1310                 put_task_struct(gtt->usertask);
1311
1312         ttm_tt_fini(&gtt->ttm);
1313         kfree(gtt);
1314 }
1315
1316 /**
1317  * amdgpu_ttm_tt_create - Create a ttm_tt object for a given BO
1318  *
1319  * @bo: The buffer object to create a GTT ttm_tt object around
1320  *
1321  * Called by ttm_tt_create().
1322  */
1323 static struct ttm_tt *amdgpu_ttm_tt_create(struct ttm_buffer_object *bo,
1324                                            uint32_t page_flags)
1325 {
1326         struct amdgpu_bo *abo = ttm_to_amdgpu_bo(bo);
1327         struct amdgpu_ttm_tt *gtt;
1328         enum ttm_caching caching;
1329
1330         gtt = kzalloc(sizeof(struct amdgpu_ttm_tt), GFP_KERNEL);
1331         if (gtt == NULL) {
1332                 return NULL;
1333         }
1334         gtt->gobj = &bo->base;
1335
1336         if (abo->flags & AMDGPU_GEM_CREATE_CPU_GTT_USWC)
1337                 caching = ttm_write_combined;
1338         else
1339                 caching = ttm_cached;
1340
1341         /* allocate space for the uninitialized page entries */
1342         if (ttm_sg_tt_init(&gtt->ttm, bo, page_flags, caching)) {
1343                 kfree(gtt);
1344                 return NULL;
1345         }
1346         return &gtt->ttm;
1347 }
1348
1349 /**
1350  * amdgpu_ttm_tt_populate - Map GTT pages visible to the device
1351  *
1352  * Map the pages of a ttm_tt object to an address space visible
1353  * to the underlying device.
1354  */
1355 static int amdgpu_ttm_tt_populate(struct ttm_bo_device *bdev,
1356                                   struct ttm_tt *ttm,
1357                                   struct ttm_operation_ctx *ctx)
1358 {
1359         struct amdgpu_device *adev = amdgpu_ttm_adev(bdev);
1360         struct amdgpu_ttm_tt *gtt = (void *)ttm;
1361
1362         /* user pages are bound by amdgpu_ttm_tt_pin_userptr() */
1363         if (gtt && gtt->userptr) {
1364                 ttm->sg = kzalloc(sizeof(struct sg_table), GFP_KERNEL);
1365                 if (!ttm->sg)
1366                         return -ENOMEM;
1367
1368                 ttm->page_flags |= TTM_PAGE_FLAG_SG;
1369                 return 0;
1370         }
1371
1372         if (ttm->page_flags & TTM_PAGE_FLAG_SG) {
1373                 if (!ttm->sg) {
1374                         struct dma_buf_attachment *attach;
1375                         struct sg_table *sgt;
1376
1377                         attach = gtt->gobj->import_attach;
1378                         sgt = dma_buf_map_attachment(attach, DMA_BIDIRECTIONAL);
1379                         if (IS_ERR(sgt))
1380                                 return PTR_ERR(sgt);
1381
1382                         ttm->sg = sgt;
1383                 }
1384
1385                 drm_prime_sg_to_page_addr_arrays(ttm->sg, ttm->pages,
1386                                                  gtt->ttm.dma_address,
1387                                                  ttm->num_pages);
1388                 return 0;
1389         }
1390
1391         return ttm_pool_alloc(&adev->mman.bdev.pool, ttm, ctx);
1392 }
1393
1394 /**
1395  * amdgpu_ttm_tt_unpopulate - unmap GTT pages and unpopulate page arrays
1396  *
1397  * Unmaps pages of a ttm_tt object from the device address space and
1398  * unpopulates the page array backing it.
1399  */
1400 static void amdgpu_ttm_tt_unpopulate(struct ttm_bo_device *bdev,
1401                                      struct ttm_tt *ttm)
1402 {
1403         struct amdgpu_ttm_tt *gtt = (void *)ttm;
1404         struct amdgpu_device *adev;
1405
1406         if (gtt && gtt->userptr) {
1407                 amdgpu_ttm_tt_set_user_pages(ttm, NULL);
1408                 kfree(ttm->sg);
1409                 ttm->page_flags &= ~TTM_PAGE_FLAG_SG;
1410                 return;
1411         }
1412
1413         if (ttm->sg && gtt->gobj->import_attach) {
1414                 struct dma_buf_attachment *attach;
1415
1416                 attach = gtt->gobj->import_attach;
1417                 dma_buf_unmap_attachment(attach, ttm->sg, DMA_BIDIRECTIONAL);
1418                 ttm->sg = NULL;
1419                 return;
1420         }
1421
1422         if (ttm->page_flags & TTM_PAGE_FLAG_SG)
1423                 return;
1424
1425         adev = amdgpu_ttm_adev(bdev);
1426         return ttm_pool_free(&adev->mman.bdev.pool, ttm);
1427 }
1428
1429 /**
1430  * amdgpu_ttm_tt_set_userptr - Initialize userptr GTT ttm_tt for the current
1431  * task
1432  *
1433  * @bo: The ttm_buffer_object to bind this userptr to
1434  * @addr:  The address in the current tasks VM space to use
1435  * @flags: Requirements of userptr object.
1436  *
1437  * Called by amdgpu_gem_userptr_ioctl() to bind userptr pages
1438  * to current task
1439  */
1440 int amdgpu_ttm_tt_set_userptr(struct ttm_buffer_object *bo,
1441                               uint64_t addr, uint32_t flags)
1442 {
1443         struct amdgpu_ttm_tt *gtt;
1444
1445         if (!bo->ttm) {
1446                 /* TODO: We want a separate TTM object type for userptrs */
1447                 bo->ttm = amdgpu_ttm_tt_create(bo, 0);
1448                 if (bo->ttm == NULL)
1449                         return -ENOMEM;
1450         }
1451
1452         gtt = (void*)bo->ttm;
1453         gtt->userptr = addr;
1454         gtt->userflags = flags;
1455
1456         if (gtt->usertask)
1457                 put_task_struct(gtt->usertask);
1458         gtt->usertask = current->group_leader;
1459         get_task_struct(gtt->usertask);
1460
1461         return 0;
1462 }
1463
1464 /**
1465  * amdgpu_ttm_tt_get_usermm - Return memory manager for ttm_tt object
1466  */
1467 struct mm_struct *amdgpu_ttm_tt_get_usermm(struct ttm_tt *ttm)
1468 {
1469         struct amdgpu_ttm_tt *gtt = (void *)ttm;
1470
1471         if (gtt == NULL)
1472                 return NULL;
1473
1474         if (gtt->usertask == NULL)
1475                 return NULL;
1476
1477         return gtt->usertask->mm;
1478 }
1479
1480 /**
1481  * amdgpu_ttm_tt_affect_userptr - Determine if a ttm_tt object lays inside an
1482  * address range for the current task.
1483  *
1484  */
1485 bool amdgpu_ttm_tt_affect_userptr(struct ttm_tt *ttm, unsigned long start,
1486                                   unsigned long end)
1487 {
1488         struct amdgpu_ttm_tt *gtt = (void *)ttm;
1489         unsigned long size;
1490
1491         if (gtt == NULL || !gtt->userptr)
1492                 return false;
1493
1494         /* Return false if no part of the ttm_tt object lies within
1495          * the range
1496          */
1497         size = (unsigned long)gtt->ttm.num_pages * PAGE_SIZE;
1498         if (gtt->userptr > end || gtt->userptr + size <= start)
1499                 return false;
1500
1501         return true;
1502 }
1503
1504 /**
1505  * amdgpu_ttm_tt_is_userptr - Have the pages backing by userptr?
1506  */
1507 bool amdgpu_ttm_tt_is_userptr(struct ttm_tt *ttm)
1508 {
1509         struct amdgpu_ttm_tt *gtt = (void *)ttm;
1510
1511         if (gtt == NULL || !gtt->userptr)
1512                 return false;
1513
1514         return true;
1515 }
1516
1517 /**
1518  * amdgpu_ttm_tt_is_readonly - Is the ttm_tt object read only?
1519  */
1520 bool amdgpu_ttm_tt_is_readonly(struct ttm_tt *ttm)
1521 {
1522         struct amdgpu_ttm_tt *gtt = (void *)ttm;
1523
1524         if (gtt == NULL)
1525                 return false;
1526
1527         return !!(gtt->userflags & AMDGPU_GEM_USERPTR_READONLY);
1528 }
1529
1530 /**
1531  * amdgpu_ttm_tt_pde_flags - Compute PDE flags for ttm_tt object
1532  *
1533  * @ttm: The ttm_tt object to compute the flags for
1534  * @mem: The memory registry backing this ttm_tt object
1535  *
1536  * Figure out the flags to use for a VM PDE (Page Directory Entry).
1537  */
1538 uint64_t amdgpu_ttm_tt_pde_flags(struct ttm_tt *ttm, struct ttm_resource *mem)
1539 {
1540         uint64_t flags = 0;
1541
1542         if (mem && mem->mem_type != TTM_PL_SYSTEM)
1543                 flags |= AMDGPU_PTE_VALID;
1544
1545         if (mem && mem->mem_type == TTM_PL_TT) {
1546                 flags |= AMDGPU_PTE_SYSTEM;
1547
1548                 if (ttm->caching == ttm_cached)
1549                         flags |= AMDGPU_PTE_SNOOPED;
1550         }
1551
1552         return flags;
1553 }
1554
1555 /**
1556  * amdgpu_ttm_tt_pte_flags - Compute PTE flags for ttm_tt object
1557  *
1558  * @ttm: The ttm_tt object to compute the flags for
1559  * @mem: The memory registry backing this ttm_tt object
1560
1561  * Figure out the flags to use for a VM PTE (Page Table Entry).
1562  */
1563 uint64_t amdgpu_ttm_tt_pte_flags(struct amdgpu_device *adev, struct ttm_tt *ttm,
1564                                  struct ttm_resource *mem)
1565 {
1566         uint64_t flags = amdgpu_ttm_tt_pde_flags(ttm, mem);
1567
1568         flags |= adev->gart.gart_pte_flags;
1569         flags |= AMDGPU_PTE_READABLE;
1570
1571         if (!amdgpu_ttm_tt_is_readonly(ttm))
1572                 flags |= AMDGPU_PTE_WRITEABLE;
1573
1574         return flags;
1575 }
1576
1577 /**
1578  * amdgpu_ttm_bo_eviction_valuable - Check to see if we can evict a buffer
1579  * object.
1580  *
1581  * Return true if eviction is sensible. Called by ttm_mem_evict_first() on
1582  * behalf of ttm_bo_mem_force_space() which tries to evict buffer objects until
1583  * it can find space for a new object and by ttm_bo_force_list_clean() which is
1584  * used to clean out a memory space.
1585  */
1586 static bool amdgpu_ttm_bo_eviction_valuable(struct ttm_buffer_object *bo,
1587                                             const struct ttm_place *place)
1588 {
1589         unsigned long num_pages = bo->mem.num_pages;
1590         struct drm_mm_node *node = bo->mem.mm_node;
1591         struct dma_resv_list *flist;
1592         struct dma_fence *f;
1593         int i;
1594
1595         if (bo->type == ttm_bo_type_kernel &&
1596             !amdgpu_vm_evictable(ttm_to_amdgpu_bo(bo)))
1597                 return false;
1598
1599         /* If bo is a KFD BO, check if the bo belongs to the current process.
1600          * If true, then return false as any KFD process needs all its BOs to
1601          * be resident to run successfully
1602          */
1603         flist = dma_resv_get_list(bo->base.resv);
1604         if (flist) {
1605                 for (i = 0; i < flist->shared_count; ++i) {
1606                         f = rcu_dereference_protected(flist->shared[i],
1607                                 dma_resv_held(bo->base.resv));
1608                         if (amdkfd_fence_check_mm(f, current->mm))
1609                                 return false;
1610                 }
1611         }
1612
1613         switch (bo->mem.mem_type) {
1614         case TTM_PL_TT:
1615                 if (amdgpu_bo_is_amdgpu_bo(bo) &&
1616                     amdgpu_bo_encrypted(ttm_to_amdgpu_bo(bo)))
1617                         return false;
1618                 return true;
1619
1620         case TTM_PL_VRAM:
1621                 /* Check each drm MM node individually */
1622                 while (num_pages) {
1623                         if (place->fpfn < (node->start + node->size) &&
1624                             !(place->lpfn && place->lpfn <= node->start))
1625                                 return true;
1626
1627                         num_pages -= node->size;
1628                         ++node;
1629                 }
1630                 return false;
1631
1632         default:
1633                 break;
1634         }
1635
1636         return ttm_bo_eviction_valuable(bo, place);
1637 }
1638
1639 /**
1640  * amdgpu_ttm_access_memory - Read or Write memory that backs a buffer object.
1641  *
1642  * @bo:  The buffer object to read/write
1643  * @offset:  Offset into buffer object
1644  * @buf:  Secondary buffer to write/read from
1645  * @len: Length in bytes of access
1646  * @write:  true if writing
1647  *
1648  * This is used to access VRAM that backs a buffer object via MMIO
1649  * access for debugging purposes.
1650  */
1651 static int amdgpu_ttm_access_memory(struct ttm_buffer_object *bo,
1652                                     unsigned long offset,
1653                                     void *buf, int len, int write)
1654 {
1655         struct amdgpu_bo *abo = ttm_to_amdgpu_bo(bo);
1656         struct amdgpu_device *adev = amdgpu_ttm_adev(abo->tbo.bdev);
1657         struct drm_mm_node *nodes;
1658         uint32_t value = 0;
1659         int ret = 0;
1660         uint64_t pos;
1661         unsigned long flags;
1662
1663         if (bo->mem.mem_type != TTM_PL_VRAM)
1664                 return -EIO;
1665
1666         pos = offset;
1667         nodes = amdgpu_find_mm_node(&abo->tbo.mem, &pos);
1668         pos += (nodes->start << PAGE_SHIFT);
1669
1670         while (len && pos < adev->gmc.mc_vram_size) {
1671                 uint64_t aligned_pos = pos & ~(uint64_t)3;
1672                 uint64_t bytes = 4 - (pos & 3);
1673                 uint32_t shift = (pos & 3) * 8;
1674                 uint32_t mask = 0xffffffff << shift;
1675
1676                 if (len < bytes) {
1677                         mask &= 0xffffffff >> (bytes - len) * 8;
1678                         bytes = len;
1679                 }
1680
1681                 if (mask != 0xffffffff) {
1682                         spin_lock_irqsave(&adev->mmio_idx_lock, flags);
1683                         WREG32_NO_KIQ(mmMM_INDEX, ((uint32_t)aligned_pos) | 0x80000000);
1684                         WREG32_NO_KIQ(mmMM_INDEX_HI, aligned_pos >> 31);
1685                         if (!write || mask != 0xffffffff)
1686                                 value = RREG32_NO_KIQ(mmMM_DATA);
1687                         if (write) {
1688                                 value &= ~mask;
1689                                 value |= (*(uint32_t *)buf << shift) & mask;
1690                                 WREG32_NO_KIQ(mmMM_DATA, value);
1691                         }
1692                         spin_unlock_irqrestore(&adev->mmio_idx_lock, flags);
1693                         if (!write) {
1694                                 value = (value & mask) >> shift;
1695                                 memcpy(buf, &value, bytes);
1696                         }
1697                 } else {
1698                         bytes = (nodes->start + nodes->size) << PAGE_SHIFT;
1699                         bytes = min(bytes - pos, (uint64_t)len & ~0x3ull);
1700
1701                         amdgpu_device_vram_access(adev, pos, (uint32_t *)buf,
1702                                                   bytes, write);
1703                 }
1704
1705                 ret += bytes;
1706                 buf = (uint8_t *)buf + bytes;
1707                 pos += bytes;
1708                 len -= bytes;
1709                 if (pos >= (nodes->start + nodes->size) << PAGE_SHIFT) {
1710                         ++nodes;
1711                         pos = (nodes->start << PAGE_SHIFT);
1712                 }
1713         }
1714
1715         return ret;
1716 }
1717
1718 static void
1719 amdgpu_bo_delete_mem_notify(struct ttm_buffer_object *bo)
1720 {
1721         amdgpu_bo_move_notify(bo, false, NULL);
1722 }
1723
1724 static struct ttm_bo_driver amdgpu_bo_driver = {
1725         .ttm_tt_create = &amdgpu_ttm_tt_create,
1726         .ttm_tt_populate = &amdgpu_ttm_tt_populate,
1727         .ttm_tt_unpopulate = &amdgpu_ttm_tt_unpopulate,
1728         .ttm_tt_destroy = &amdgpu_ttm_backend_destroy,
1729         .eviction_valuable = amdgpu_ttm_bo_eviction_valuable,
1730         .evict_flags = &amdgpu_evict_flags,
1731         .move = &amdgpu_bo_move,
1732         .verify_access = &amdgpu_verify_access,
1733         .delete_mem_notify = &amdgpu_bo_delete_mem_notify,
1734         .release_notify = &amdgpu_bo_release_notify,
1735         .io_mem_reserve = &amdgpu_ttm_io_mem_reserve,
1736         .io_mem_pfn = amdgpu_ttm_io_mem_pfn,
1737         .access_memory = &amdgpu_ttm_access_memory,
1738         .del_from_lru_notify = &amdgpu_vm_del_from_lru_notify
1739 };
1740
1741 /*
1742  * Firmware Reservation functions
1743  */
1744 /**
1745  * amdgpu_ttm_fw_reserve_vram_fini - free fw reserved vram
1746  *
1747  * @adev: amdgpu_device pointer
1748  *
1749  * free fw reserved vram if it has been reserved.
1750  */
1751 static void amdgpu_ttm_fw_reserve_vram_fini(struct amdgpu_device *adev)
1752 {
1753         amdgpu_bo_free_kernel(&adev->mman.fw_vram_usage_reserved_bo,
1754                 NULL, &adev->mman.fw_vram_usage_va);
1755 }
1756
1757 /**
1758  * amdgpu_ttm_fw_reserve_vram_init - create bo vram reservation from fw
1759  *
1760  * @adev: amdgpu_device pointer
1761  *
1762  * create bo vram reservation from fw.
1763  */
1764 static int amdgpu_ttm_fw_reserve_vram_init(struct amdgpu_device *adev)
1765 {
1766         uint64_t vram_size = adev->gmc.visible_vram_size;
1767
1768         adev->mman.fw_vram_usage_va = NULL;
1769         adev->mman.fw_vram_usage_reserved_bo = NULL;
1770
1771         if (adev->mman.fw_vram_usage_size == 0 ||
1772             adev->mman.fw_vram_usage_size > vram_size)
1773                 return 0;
1774
1775         return amdgpu_bo_create_kernel_at(adev,
1776                                           adev->mman.fw_vram_usage_start_offset,
1777                                           adev->mman.fw_vram_usage_size,
1778                                           AMDGPU_GEM_DOMAIN_VRAM,
1779                                           &adev->mman.fw_vram_usage_reserved_bo,
1780                                           &adev->mman.fw_vram_usage_va);
1781 }
1782
1783 /*
1784  * Memoy training reservation functions
1785  */
1786
1787 /**
1788  * amdgpu_ttm_training_reserve_vram_fini - free memory training reserved vram
1789  *
1790  * @adev: amdgpu_device pointer
1791  *
1792  * free memory training reserved vram if it has been reserved.
1793  */
1794 static int amdgpu_ttm_training_reserve_vram_fini(struct amdgpu_device *adev)
1795 {
1796         struct psp_memory_training_context *ctx = &adev->psp.mem_train_ctx;
1797
1798         ctx->init = PSP_MEM_TRAIN_NOT_SUPPORT;
1799         amdgpu_bo_free_kernel(&ctx->c2p_bo, NULL, NULL);
1800         ctx->c2p_bo = NULL;
1801
1802         return 0;
1803 }
1804
1805 static void amdgpu_ttm_training_data_block_init(struct amdgpu_device *adev)
1806 {
1807         struct psp_memory_training_context *ctx = &adev->psp.mem_train_ctx;
1808
1809         memset(ctx, 0, sizeof(*ctx));
1810
1811         ctx->c2p_train_data_offset =
1812                 ALIGN((adev->gmc.mc_vram_size - adev->mman.discovery_tmr_size - SZ_1M), SZ_1M);
1813         ctx->p2c_train_data_offset =
1814                 (adev->gmc.mc_vram_size - GDDR6_MEM_TRAINING_OFFSET);
1815         ctx->train_data_size =
1816                 GDDR6_MEM_TRAINING_DATA_SIZE_IN_BYTES;
1817
1818         DRM_DEBUG("train_data_size:%llx,p2c_train_data_offset:%llx,c2p_train_data_offset:%llx.\n",
1819                         ctx->train_data_size,
1820                         ctx->p2c_train_data_offset,
1821                         ctx->c2p_train_data_offset);
1822 }
1823
1824 /*
1825  * reserve TMR memory at the top of VRAM which holds
1826  * IP Discovery data and is protected by PSP.
1827  */
1828 static int amdgpu_ttm_reserve_tmr(struct amdgpu_device *adev)
1829 {
1830         int ret;
1831         struct psp_memory_training_context *ctx = &adev->psp.mem_train_ctx;
1832         bool mem_train_support = false;
1833
1834         if (!amdgpu_sriov_vf(adev)) {
1835                 ret = amdgpu_mem_train_support(adev);
1836                 if (ret == 1)
1837                         mem_train_support = true;
1838                 else if (ret == -1)
1839                         return -EINVAL;
1840                 else
1841                         DRM_DEBUG("memory training does not support!\n");
1842         }
1843
1844         /*
1845          * Query reserved tmr size through atom firmwareinfo for Sienna_Cichlid and onwards for all
1846          * the use cases (IP discovery/G6 memory training/profiling/diagnostic data.etc)
1847          *
1848          * Otherwise, fallback to legacy approach to check and reserve tmr block for ip
1849          * discovery data and G6 memory training data respectively
1850          */
1851         adev->mman.discovery_tmr_size =
1852                 amdgpu_atomfirmware_get_fw_reserved_fb_size(adev);
1853         if (!adev->mman.discovery_tmr_size)
1854                 adev->mman.discovery_tmr_size = DISCOVERY_TMR_OFFSET;
1855
1856         if (mem_train_support) {
1857                 /* reserve vram for mem train according to TMR location */
1858                 amdgpu_ttm_training_data_block_init(adev);
1859                 ret = amdgpu_bo_create_kernel_at(adev,
1860                                          ctx->c2p_train_data_offset,
1861                                          ctx->train_data_size,
1862                                          AMDGPU_GEM_DOMAIN_VRAM,
1863                                          &ctx->c2p_bo,
1864                                          NULL);
1865                 if (ret) {
1866                         DRM_ERROR("alloc c2p_bo failed(%d)!\n", ret);
1867                         amdgpu_ttm_training_reserve_vram_fini(adev);
1868                         return ret;
1869                 }
1870                 ctx->init = PSP_MEM_TRAIN_RESERVE_SUCCESS;
1871         }
1872
1873         ret = amdgpu_bo_create_kernel_at(adev,
1874                                 adev->gmc.real_vram_size - adev->mman.discovery_tmr_size,
1875                                 adev->mman.discovery_tmr_size,
1876                                 AMDGPU_GEM_DOMAIN_VRAM,
1877                                 &adev->mman.discovery_memory,
1878                                 NULL);
1879         if (ret) {
1880                 DRM_ERROR("alloc tmr failed(%d)!\n", ret);
1881                 amdgpu_bo_free_kernel(&adev->mman.discovery_memory, NULL, NULL);
1882                 return ret;
1883         }
1884
1885         return 0;
1886 }
1887
1888 /**
1889  * amdgpu_ttm_init - Init the memory management (ttm) as well as various
1890  * gtt/vram related fields.
1891  *
1892  * This initializes all of the memory space pools that the TTM layer
1893  * will need such as the GTT space (system memory mapped to the device),
1894  * VRAM (on-board memory), and on-chip memories (GDS, GWS, OA) which
1895  * can be mapped per VMID.
1896  */
1897 int amdgpu_ttm_init(struct amdgpu_device *adev)
1898 {
1899         uint64_t gtt_size;
1900         int r;
1901         u64 vis_vram_limit;
1902
1903         mutex_init(&adev->mman.gtt_window_lock);
1904
1905         /* No others user of address space so set it to 0 */
1906         r = ttm_bo_device_init(&adev->mman.bdev, &amdgpu_bo_driver, adev->dev,
1907                                adev_to_drm(adev)->anon_inode->i_mapping,
1908                                adev_to_drm(adev)->vma_offset_manager,
1909                                adev->need_swiotlb,
1910                                dma_addressing_limited(adev->dev));
1911         if (r) {
1912                 DRM_ERROR("failed initializing buffer object driver(%d).\n", r);
1913                 return r;
1914         }
1915         adev->mman.initialized = true;
1916
1917         /* Initialize VRAM pool with all of VRAM divided into pages */
1918         r = amdgpu_vram_mgr_init(adev);
1919         if (r) {
1920                 DRM_ERROR("Failed initializing VRAM heap.\n");
1921                 return r;
1922         }
1923
1924         /* Reduce size of CPU-visible VRAM if requested */
1925         vis_vram_limit = (u64)amdgpu_vis_vram_limit * 1024 * 1024;
1926         if (amdgpu_vis_vram_limit > 0 &&
1927             vis_vram_limit <= adev->gmc.visible_vram_size)
1928                 adev->gmc.visible_vram_size = vis_vram_limit;
1929
1930         /* Change the size here instead of the init above so only lpfn is affected */
1931         amdgpu_ttm_set_buffer_funcs_status(adev, false);
1932 #ifdef CONFIG_64BIT
1933         adev->mman.aper_base_kaddr = ioremap_wc(adev->gmc.aper_base,
1934                                                 adev->gmc.visible_vram_size);
1935 #endif
1936
1937         /*
1938          *The reserved vram for firmware must be pinned to the specified
1939          *place on the VRAM, so reserve it early.
1940          */
1941         r = amdgpu_ttm_fw_reserve_vram_init(adev);
1942         if (r) {
1943                 return r;
1944         }
1945
1946         /*
1947          * only NAVI10 and onwards ASIC support for IP discovery.
1948          * If IP discovery enabled, a block of memory should be
1949          * reserved for IP discovey.
1950          */
1951         if (adev->mman.discovery_bin) {
1952                 r = amdgpu_ttm_reserve_tmr(adev);
1953                 if (r)
1954                         return r;
1955         }
1956
1957         /* allocate memory as required for VGA
1958          * This is used for VGA emulation and pre-OS scanout buffers to
1959          * avoid display artifacts while transitioning between pre-OS
1960          * and driver.  */
1961         r = amdgpu_bo_create_kernel_at(adev, 0, adev->mman.stolen_vga_size,
1962                                        AMDGPU_GEM_DOMAIN_VRAM,
1963                                        &adev->mman.stolen_vga_memory,
1964                                        NULL);
1965         if (r)
1966                 return r;
1967         r = amdgpu_bo_create_kernel_at(adev, adev->mman.stolen_vga_size,
1968                                        adev->mman.stolen_extended_size,
1969                                        AMDGPU_GEM_DOMAIN_VRAM,
1970                                        &adev->mman.stolen_extended_memory,
1971                                        NULL);
1972         if (r)
1973                 return r;
1974
1975         DRM_INFO("amdgpu: %uM of VRAM memory ready\n",
1976                  (unsigned) (adev->gmc.real_vram_size / (1024 * 1024)));
1977
1978         /* Compute GTT size, either bsaed on 3/4th the size of RAM size
1979          * or whatever the user passed on module init */
1980         if (amdgpu_gtt_size == -1) {
1981                 struct sysinfo si;
1982
1983                 si_meminfo(&si);
1984                 gtt_size = min(max((AMDGPU_DEFAULT_GTT_SIZE_MB << 20),
1985                                adev->gmc.mc_vram_size),
1986                                ((uint64_t)si.totalram * si.mem_unit * 3/4));
1987         }
1988         else
1989                 gtt_size = (uint64_t)amdgpu_gtt_size << 20;
1990
1991         /* Initialize GTT memory pool */
1992         r = amdgpu_gtt_mgr_init(adev, gtt_size);
1993         if (r) {
1994                 DRM_ERROR("Failed initializing GTT heap.\n");
1995                 return r;
1996         }
1997         DRM_INFO("amdgpu: %uM of GTT memory ready.\n",
1998                  (unsigned)(gtt_size / (1024 * 1024)));
1999
2000         /* Initialize various on-chip memory pools */
2001         r = amdgpu_ttm_init_on_chip(adev, AMDGPU_PL_GDS, adev->gds.gds_size);
2002         if (r) {
2003                 DRM_ERROR("Failed initializing GDS heap.\n");
2004                 return r;
2005         }
2006
2007         r = amdgpu_ttm_init_on_chip(adev, AMDGPU_PL_GWS, adev->gds.gws_size);
2008         if (r) {
2009                 DRM_ERROR("Failed initializing gws heap.\n");
2010                 return r;
2011         }
2012
2013         r = amdgpu_ttm_init_on_chip(adev, AMDGPU_PL_OA, adev->gds.oa_size);
2014         if (r) {
2015                 DRM_ERROR("Failed initializing oa heap.\n");
2016                 return r;
2017         }
2018
2019         return 0;
2020 }
2021
2022 /**
2023  * amdgpu_ttm_late_init - Handle any late initialization for amdgpu_ttm
2024  */
2025 void amdgpu_ttm_late_init(struct amdgpu_device *adev)
2026 {
2027         /* return the VGA stolen memory (if any) back to VRAM */
2028         if (!adev->mman.keep_stolen_vga_memory)
2029                 amdgpu_bo_free_kernel(&adev->mman.stolen_vga_memory, NULL, NULL);
2030         amdgpu_bo_free_kernel(&adev->mman.stolen_extended_memory, NULL, NULL);
2031 }
2032
2033 /**
2034  * amdgpu_ttm_fini - De-initialize the TTM memory pools
2035  */
2036 void amdgpu_ttm_fini(struct amdgpu_device *adev)
2037 {
2038         if (!adev->mman.initialized)
2039                 return;
2040
2041         amdgpu_ttm_training_reserve_vram_fini(adev);
2042         /* return the stolen vga memory back to VRAM */
2043         if (adev->mman.keep_stolen_vga_memory)
2044                 amdgpu_bo_free_kernel(&adev->mman.stolen_vga_memory, NULL, NULL);
2045         /* return the IP Discovery TMR memory back to VRAM */
2046         amdgpu_bo_free_kernel(&adev->mman.discovery_memory, NULL, NULL);
2047         amdgpu_ttm_fw_reserve_vram_fini(adev);
2048
2049         if (adev->mman.aper_base_kaddr)
2050                 iounmap(adev->mman.aper_base_kaddr);
2051         adev->mman.aper_base_kaddr = NULL;
2052
2053         amdgpu_vram_mgr_fini(adev);
2054         amdgpu_gtt_mgr_fini(adev);
2055         ttm_range_man_fini(&adev->mman.bdev, AMDGPU_PL_GDS);
2056         ttm_range_man_fini(&adev->mman.bdev, AMDGPU_PL_GWS);
2057         ttm_range_man_fini(&adev->mman.bdev, AMDGPU_PL_OA);
2058         ttm_bo_device_release(&adev->mman.bdev);
2059         adev->mman.initialized = false;
2060         DRM_INFO("amdgpu: ttm finalized\n");
2061 }
2062
2063 /**
2064  * amdgpu_ttm_set_buffer_funcs_status - enable/disable use of buffer functions
2065  *
2066  * @adev: amdgpu_device pointer
2067  * @enable: true when we can use buffer functions.
2068  *
2069  * Enable/disable use of buffer functions during suspend/resume. This should
2070  * only be called at bootup or when userspace isn't running.
2071  */
2072 void amdgpu_ttm_set_buffer_funcs_status(struct amdgpu_device *adev, bool enable)
2073 {
2074         struct ttm_resource_manager *man = ttm_manager_type(&adev->mman.bdev, TTM_PL_VRAM);
2075         uint64_t size;
2076         int r;
2077
2078         if (!adev->mman.initialized || amdgpu_in_reset(adev) ||
2079             adev->mman.buffer_funcs_enabled == enable)
2080                 return;
2081
2082         if (enable) {
2083                 struct amdgpu_ring *ring;
2084                 struct drm_gpu_scheduler *sched;
2085
2086                 ring = adev->mman.buffer_funcs_ring;
2087                 sched = &ring->sched;
2088                 r = drm_sched_entity_init(&adev->mman.entity,
2089                                           DRM_SCHED_PRIORITY_KERNEL, &sched,
2090                                           1, NULL);
2091                 if (r) {
2092                         DRM_ERROR("Failed setting up TTM BO move entity (%d)\n",
2093                                   r);
2094                         return;
2095                 }
2096         } else {
2097                 drm_sched_entity_destroy(&adev->mman.entity);
2098                 dma_fence_put(man->move);
2099                 man->move = NULL;
2100         }
2101
2102         /* this just adjusts TTM size idea, which sets lpfn to the correct value */
2103         if (enable)
2104                 size = adev->gmc.real_vram_size;
2105         else
2106                 size = adev->gmc.visible_vram_size;
2107         man->size = size >> PAGE_SHIFT;
2108         adev->mman.buffer_funcs_enabled = enable;
2109 }
2110
2111 static vm_fault_t amdgpu_ttm_fault(struct vm_fault *vmf)
2112 {
2113         struct ttm_buffer_object *bo = vmf->vma->vm_private_data;
2114         vm_fault_t ret;
2115
2116         ret = ttm_bo_vm_reserve(bo, vmf);
2117         if (ret)
2118                 return ret;
2119
2120         ret = amdgpu_bo_fault_reserve_notify(bo);
2121         if (ret)
2122                 goto unlock;
2123
2124         ret = ttm_bo_vm_fault_reserved(vmf, vmf->vma->vm_page_prot,
2125                                        TTM_BO_VM_NUM_PREFAULT, 1);
2126         if (ret == VM_FAULT_RETRY && !(vmf->flags & FAULT_FLAG_RETRY_NOWAIT))
2127                 return ret;
2128
2129 unlock:
2130         dma_resv_unlock(bo->base.resv);
2131         return ret;
2132 }
2133
2134 static struct vm_operations_struct amdgpu_ttm_vm_ops = {
2135         .fault = amdgpu_ttm_fault,
2136         .open = ttm_bo_vm_open,
2137         .close = ttm_bo_vm_close,
2138         .access = ttm_bo_vm_access
2139 };
2140
2141 int amdgpu_mmap(struct file *filp, struct vm_area_struct *vma)
2142 {
2143         struct drm_file *file_priv = filp->private_data;
2144         struct amdgpu_device *adev = drm_to_adev(file_priv->minor->dev);
2145         int r;
2146
2147         r = ttm_bo_mmap(filp, vma, &adev->mman.bdev);
2148         if (unlikely(r != 0))
2149                 return r;
2150
2151         vma->vm_ops = &amdgpu_ttm_vm_ops;
2152         return 0;
2153 }
2154
2155 int amdgpu_copy_buffer(struct amdgpu_ring *ring, uint64_t src_offset,
2156                        uint64_t dst_offset, uint32_t byte_count,
2157                        struct dma_resv *resv,
2158                        struct dma_fence **fence, bool direct_submit,
2159                        bool vm_needs_flush, bool tmz)
2160 {
2161         enum amdgpu_ib_pool_type pool = direct_submit ? AMDGPU_IB_POOL_DIRECT :
2162                 AMDGPU_IB_POOL_DELAYED;
2163         struct amdgpu_device *adev = ring->adev;
2164         struct amdgpu_job *job;
2165
2166         uint32_t max_bytes;
2167         unsigned num_loops, num_dw;
2168         unsigned i;
2169         int r;
2170
2171         if (direct_submit && !ring->sched.ready) {
2172                 DRM_ERROR("Trying to move memory with ring turned off.\n");
2173                 return -EINVAL;
2174         }
2175
2176         max_bytes = adev->mman.buffer_funcs->copy_max_bytes;
2177         num_loops = DIV_ROUND_UP(byte_count, max_bytes);
2178         num_dw = ALIGN(num_loops * adev->mman.buffer_funcs->copy_num_dw, 8);
2179
2180         r = amdgpu_job_alloc_with_ib(adev, num_dw * 4, pool, &job);
2181         if (r)
2182                 return r;
2183
2184         if (vm_needs_flush) {
2185                 job->vm_pd_addr = amdgpu_gmc_pd_addr(adev->gart.bo);
2186                 job->vm_needs_flush = true;
2187         }
2188         if (resv) {
2189                 r = amdgpu_sync_resv(adev, &job->sync, resv,
2190                                      AMDGPU_SYNC_ALWAYS,
2191                                      AMDGPU_FENCE_OWNER_UNDEFINED);
2192                 if (r) {
2193                         DRM_ERROR("sync failed (%d).\n", r);
2194                         goto error_free;
2195                 }
2196         }
2197
2198         for (i = 0; i < num_loops; i++) {
2199                 uint32_t cur_size_in_bytes = min(byte_count, max_bytes);
2200
2201                 amdgpu_emit_copy_buffer(adev, &job->ibs[0], src_offset,
2202                                         dst_offset, cur_size_in_bytes, tmz);
2203
2204                 src_offset += cur_size_in_bytes;
2205                 dst_offset += cur_size_in_bytes;
2206                 byte_count -= cur_size_in_bytes;
2207         }
2208
2209         amdgpu_ring_pad_ib(ring, &job->ibs[0]);
2210         WARN_ON(job->ibs[0].length_dw > num_dw);
2211         if (direct_submit)
2212                 r = amdgpu_job_submit_direct(job, ring, fence);
2213         else
2214                 r = amdgpu_job_submit(job, &adev->mman.entity,
2215                                       AMDGPU_FENCE_OWNER_UNDEFINED, fence);
2216         if (r)
2217                 goto error_free;
2218
2219         return r;
2220
2221 error_free:
2222         amdgpu_job_free(job);
2223         DRM_ERROR("Error scheduling IBs (%d)\n", r);
2224         return r;
2225 }
2226
2227 int amdgpu_fill_buffer(struct amdgpu_bo *bo,
2228                        uint32_t src_data,
2229                        struct dma_resv *resv,
2230                        struct dma_fence **fence)
2231 {
2232         struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
2233         uint32_t max_bytes = adev->mman.buffer_funcs->fill_max_bytes;
2234         struct amdgpu_ring *ring = adev->mman.buffer_funcs_ring;
2235
2236         struct drm_mm_node *mm_node;
2237         unsigned long num_pages;
2238         unsigned int num_loops, num_dw;
2239
2240         struct amdgpu_job *job;
2241         int r;
2242
2243         if (!adev->mman.buffer_funcs_enabled) {
2244                 DRM_ERROR("Trying to clear memory with ring turned off.\n");
2245                 return -EINVAL;
2246         }
2247
2248         if (bo->tbo.mem.mem_type == TTM_PL_TT) {
2249                 r = amdgpu_ttm_alloc_gart(&bo->tbo);
2250                 if (r)
2251                         return r;
2252         }
2253
2254         num_pages = bo->tbo.num_pages;
2255         mm_node = bo->tbo.mem.mm_node;
2256         num_loops = 0;
2257         while (num_pages) {
2258                 uint64_t byte_count = mm_node->size << PAGE_SHIFT;
2259
2260                 num_loops += DIV_ROUND_UP_ULL(byte_count, max_bytes);
2261                 num_pages -= mm_node->size;
2262                 ++mm_node;
2263         }
2264         num_dw = num_loops * adev->mman.buffer_funcs->fill_num_dw;
2265
2266         /* for IB padding */
2267         num_dw += 64;
2268
2269         r = amdgpu_job_alloc_with_ib(adev, num_dw * 4, AMDGPU_IB_POOL_DELAYED,
2270                                      &job);
2271         if (r)
2272                 return r;
2273
2274         if (resv) {
2275                 r = amdgpu_sync_resv(adev, &job->sync, resv,
2276                                      AMDGPU_SYNC_ALWAYS,
2277                                      AMDGPU_FENCE_OWNER_UNDEFINED);
2278                 if (r) {
2279                         DRM_ERROR("sync failed (%d).\n", r);
2280                         goto error_free;
2281                 }
2282         }
2283
2284         num_pages = bo->tbo.num_pages;
2285         mm_node = bo->tbo.mem.mm_node;
2286
2287         while (num_pages) {
2288                 uint64_t byte_count = mm_node->size << PAGE_SHIFT;
2289                 uint64_t dst_addr;
2290
2291                 dst_addr = amdgpu_mm_node_addr(&bo->tbo, mm_node, &bo->tbo.mem);
2292                 while (byte_count) {
2293                         uint32_t cur_size_in_bytes = min_t(uint64_t, byte_count,
2294                                                            max_bytes);
2295
2296                         amdgpu_emit_fill_buffer(adev, &job->ibs[0], src_data,
2297                                                 dst_addr, cur_size_in_bytes);
2298
2299                         dst_addr += cur_size_in_bytes;
2300                         byte_count -= cur_size_in_bytes;
2301                 }
2302
2303                 num_pages -= mm_node->size;
2304                 ++mm_node;
2305         }
2306
2307         amdgpu_ring_pad_ib(ring, &job->ibs[0]);
2308         WARN_ON(job->ibs[0].length_dw > num_dw);
2309         r = amdgpu_job_submit(job, &adev->mman.entity,
2310                               AMDGPU_FENCE_OWNER_UNDEFINED, fence);
2311         if (r)
2312                 goto error_free;
2313
2314         return 0;
2315
2316 error_free:
2317         amdgpu_job_free(job);
2318         return r;
2319 }
2320
2321 #if defined(CONFIG_DEBUG_FS)
2322
2323 static int amdgpu_mm_dump_table(struct seq_file *m, void *data)
2324 {
2325         struct drm_info_node *node = (struct drm_info_node *)m->private;
2326         unsigned ttm_pl = (uintptr_t)node->info_ent->data;
2327         struct drm_device *dev = node->minor->dev;
2328         struct amdgpu_device *adev = drm_to_adev(dev);
2329         struct ttm_resource_manager *man = ttm_manager_type(&adev->mman.bdev, ttm_pl);
2330         struct drm_printer p = drm_seq_file_printer(m);
2331
2332         man->func->debug(man, &p);
2333         return 0;
2334 }
2335
2336 static int amdgpu_ttm_pool_debugfs(struct seq_file *m, void *data)
2337 {
2338         struct drm_info_node *node = (struct drm_info_node *)m->private;
2339         struct drm_device *dev = node->minor->dev;
2340         struct amdgpu_device *adev = drm_to_adev(dev);
2341
2342         return ttm_pool_debugfs(&adev->mman.bdev.pool, m);
2343 }
2344
2345 static const struct drm_info_list amdgpu_ttm_debugfs_list[] = {
2346         {"amdgpu_vram_mm", amdgpu_mm_dump_table, 0, (void *)TTM_PL_VRAM},
2347         {"amdgpu_gtt_mm", amdgpu_mm_dump_table, 0, (void *)TTM_PL_TT},
2348         {"amdgpu_gds_mm", amdgpu_mm_dump_table, 0, (void *)AMDGPU_PL_GDS},
2349         {"amdgpu_gws_mm", amdgpu_mm_dump_table, 0, (void *)AMDGPU_PL_GWS},
2350         {"amdgpu_oa_mm", amdgpu_mm_dump_table, 0, (void *)AMDGPU_PL_OA},
2351         {"ttm_page_pool", amdgpu_ttm_pool_debugfs, 0, NULL},
2352 };
2353
2354 /**
2355  * amdgpu_ttm_vram_read - Linear read access to VRAM
2356  *
2357  * Accesses VRAM via MMIO for debugging purposes.
2358  */
2359 static ssize_t amdgpu_ttm_vram_read(struct file *f, char __user *buf,
2360                                     size_t size, loff_t *pos)
2361 {
2362         struct amdgpu_device *adev = file_inode(f)->i_private;
2363         ssize_t result = 0;
2364
2365         if (size & 0x3 || *pos & 0x3)
2366                 return -EINVAL;
2367
2368         if (*pos >= adev->gmc.mc_vram_size)
2369                 return -ENXIO;
2370
2371         size = min(size, (size_t)(adev->gmc.mc_vram_size - *pos));
2372         while (size) {
2373                 size_t bytes = min(size, AMDGPU_TTM_VRAM_MAX_DW_READ * 4);
2374                 uint32_t value[AMDGPU_TTM_VRAM_MAX_DW_READ];
2375
2376                 amdgpu_device_vram_access(adev, *pos, value, bytes, false);
2377                 if (copy_to_user(buf, value, bytes))
2378                         return -EFAULT;
2379
2380                 result += bytes;
2381                 buf += bytes;
2382                 *pos += bytes;
2383                 size -= bytes;
2384         }
2385
2386         return result;
2387 }
2388
2389 /**
2390  * amdgpu_ttm_vram_write - Linear write access to VRAM
2391  *
2392  * Accesses VRAM via MMIO for debugging purposes.
2393  */
2394 static ssize_t amdgpu_ttm_vram_write(struct file *f, const char __user *buf,
2395                                     size_t size, loff_t *pos)
2396 {
2397         struct amdgpu_device *adev = file_inode(f)->i_private;
2398         ssize_t result = 0;
2399         int r;
2400
2401         if (size & 0x3 || *pos & 0x3)
2402                 return -EINVAL;
2403
2404         if (*pos >= adev->gmc.mc_vram_size)
2405                 return -ENXIO;
2406
2407         while (size) {
2408                 unsigned long flags;
2409                 uint32_t value;
2410
2411                 if (*pos >= adev->gmc.mc_vram_size)
2412                         return result;
2413
2414                 r = get_user(value, (uint32_t *)buf);
2415                 if (r)
2416                         return r;
2417
2418                 spin_lock_irqsave(&adev->mmio_idx_lock, flags);
2419                 WREG32_NO_KIQ(mmMM_INDEX, ((uint32_t)*pos) | 0x80000000);
2420                 WREG32_NO_KIQ(mmMM_INDEX_HI, *pos >> 31);
2421                 WREG32_NO_KIQ(mmMM_DATA, value);
2422                 spin_unlock_irqrestore(&adev->mmio_idx_lock, flags);
2423
2424                 result += 4;
2425                 buf += 4;
2426                 *pos += 4;
2427                 size -= 4;
2428         }
2429
2430         return result;
2431 }
2432
2433 static const struct file_operations amdgpu_ttm_vram_fops = {
2434         .owner = THIS_MODULE,
2435         .read = amdgpu_ttm_vram_read,
2436         .write = amdgpu_ttm_vram_write,
2437         .llseek = default_llseek,
2438 };
2439
2440 #ifdef CONFIG_DRM_AMDGPU_GART_DEBUGFS
2441
2442 /**
2443  * amdgpu_ttm_gtt_read - Linear read access to GTT memory
2444  */
2445 static ssize_t amdgpu_ttm_gtt_read(struct file *f, char __user *buf,
2446                                    size_t size, loff_t *pos)
2447 {
2448         struct amdgpu_device *adev = file_inode(f)->i_private;
2449         ssize_t result = 0;
2450         int r;
2451
2452         while (size) {
2453                 loff_t p = *pos / PAGE_SIZE;
2454                 unsigned off = *pos & ~PAGE_MASK;
2455                 size_t cur_size = min_t(size_t, size, PAGE_SIZE - off);
2456                 struct page *page;
2457                 void *ptr;
2458
2459                 if (p >= adev->gart.num_cpu_pages)
2460                         return result;
2461
2462                 page = adev->gart.pages[p];
2463                 if (page) {
2464                         ptr = kmap(page);
2465                         ptr += off;
2466
2467                         r = copy_to_user(buf, ptr, cur_size);
2468                         kunmap(adev->gart.pages[p]);
2469                 } else
2470                         r = clear_user(buf, cur_size);
2471
2472                 if (r)
2473                         return -EFAULT;
2474
2475                 result += cur_size;
2476                 buf += cur_size;
2477                 *pos += cur_size;
2478                 size -= cur_size;
2479         }
2480
2481         return result;
2482 }
2483
2484 static const struct file_operations amdgpu_ttm_gtt_fops = {
2485         .owner = THIS_MODULE,
2486         .read = amdgpu_ttm_gtt_read,
2487         .llseek = default_llseek
2488 };
2489
2490 #endif
2491
2492 /**
2493  * amdgpu_iomem_read - Virtual read access to GPU mapped memory
2494  *
2495  * This function is used to read memory that has been mapped to the
2496  * GPU and the known addresses are not physical addresses but instead
2497  * bus addresses (e.g., what you'd put in an IB or ring buffer).
2498  */
2499 static ssize_t amdgpu_iomem_read(struct file *f, char __user *buf,
2500                                  size_t size, loff_t *pos)
2501 {
2502         struct amdgpu_device *adev = file_inode(f)->i_private;
2503         struct iommu_domain *dom;
2504         ssize_t result = 0;
2505         int r;
2506
2507         /* retrieve the IOMMU domain if any for this device */
2508         dom = iommu_get_domain_for_dev(adev->dev);
2509
2510         while (size) {
2511                 phys_addr_t addr = *pos & PAGE_MASK;
2512                 loff_t off = *pos & ~PAGE_MASK;
2513                 size_t bytes = PAGE_SIZE - off;
2514                 unsigned long pfn;
2515                 struct page *p;
2516                 void *ptr;
2517
2518                 bytes = bytes < size ? bytes : size;
2519
2520                 /* Translate the bus address to a physical address.  If
2521                  * the domain is NULL it means there is no IOMMU active
2522                  * and the address translation is the identity
2523                  */
2524                 addr = dom ? iommu_iova_to_phys(dom, addr) : addr;
2525
2526                 pfn = addr >> PAGE_SHIFT;
2527                 if (!pfn_valid(pfn))
2528                         return -EPERM;
2529
2530                 p = pfn_to_page(pfn);
2531                 if (p->mapping != adev->mman.bdev.dev_mapping)
2532                         return -EPERM;
2533
2534                 ptr = kmap(p);
2535                 r = copy_to_user(buf, ptr + off, bytes);
2536                 kunmap(p);
2537                 if (r)
2538                         return -EFAULT;
2539
2540                 size -= bytes;
2541                 *pos += bytes;
2542                 result += bytes;
2543         }
2544
2545         return result;
2546 }
2547
2548 /**
2549  * amdgpu_iomem_write - Virtual write access to GPU mapped memory
2550  *
2551  * This function is used to write memory that has been mapped to the
2552  * GPU and the known addresses are not physical addresses but instead
2553  * bus addresses (e.g., what you'd put in an IB or ring buffer).
2554  */
2555 static ssize_t amdgpu_iomem_write(struct file *f, const char __user *buf,
2556                                  size_t size, loff_t *pos)
2557 {
2558         struct amdgpu_device *adev = file_inode(f)->i_private;
2559         struct iommu_domain *dom;
2560         ssize_t result = 0;
2561         int r;
2562
2563         dom = iommu_get_domain_for_dev(adev->dev);
2564
2565         while (size) {
2566                 phys_addr_t addr = *pos & PAGE_MASK;
2567                 loff_t off = *pos & ~PAGE_MASK;
2568                 size_t bytes = PAGE_SIZE - off;
2569                 unsigned long pfn;
2570                 struct page *p;
2571                 void *ptr;
2572
2573                 bytes = bytes < size ? bytes : size;
2574
2575                 addr = dom ? iommu_iova_to_phys(dom, addr) : addr;
2576
2577                 pfn = addr >> PAGE_SHIFT;
2578                 if (!pfn_valid(pfn))
2579                         return -EPERM;
2580
2581                 p = pfn_to_page(pfn);
2582                 if (p->mapping != adev->mman.bdev.dev_mapping)
2583                         return -EPERM;
2584
2585                 ptr = kmap(p);
2586                 r = copy_from_user(ptr + off, buf, bytes);
2587                 kunmap(p);
2588                 if (r)
2589                         return -EFAULT;
2590
2591                 size -= bytes;
2592                 *pos += bytes;
2593                 result += bytes;
2594         }
2595
2596         return result;
2597 }
2598
2599 static const struct file_operations amdgpu_ttm_iomem_fops = {
2600         .owner = THIS_MODULE,
2601         .read = amdgpu_iomem_read,
2602         .write = amdgpu_iomem_write,
2603         .llseek = default_llseek
2604 };
2605
2606 static const struct {
2607         char *name;
2608         const struct file_operations *fops;
2609         int domain;
2610 } ttm_debugfs_entries[] = {
2611         { "amdgpu_vram", &amdgpu_ttm_vram_fops, TTM_PL_VRAM },
2612 #ifdef CONFIG_DRM_AMDGPU_GART_DEBUGFS
2613         { "amdgpu_gtt", &amdgpu_ttm_gtt_fops, TTM_PL_TT },
2614 #endif
2615         { "amdgpu_iomem", &amdgpu_ttm_iomem_fops, TTM_PL_SYSTEM },
2616 };
2617
2618 #endif
2619
2620 int amdgpu_ttm_debugfs_init(struct amdgpu_device *adev)
2621 {
2622 #if defined(CONFIG_DEBUG_FS)
2623         unsigned count;
2624
2625         struct drm_minor *minor = adev_to_drm(adev)->primary;
2626         struct dentry *ent, *root = minor->debugfs_root;
2627
2628         for (count = 0; count < ARRAY_SIZE(ttm_debugfs_entries); count++) {
2629                 ent = debugfs_create_file(
2630                                 ttm_debugfs_entries[count].name,
2631                                 S_IFREG | S_IRUGO, root,
2632                                 adev,
2633                                 ttm_debugfs_entries[count].fops);
2634                 if (IS_ERR(ent))
2635                         return PTR_ERR(ent);
2636                 if (ttm_debugfs_entries[count].domain == TTM_PL_VRAM)
2637                         i_size_write(ent->d_inode, adev->gmc.mc_vram_size);
2638                 else if (ttm_debugfs_entries[count].domain == TTM_PL_TT)
2639                         i_size_write(ent->d_inode, adev->gmc.gart_size);
2640                 adev->mman.debugfs_entries[count] = ent;
2641         }
2642
2643         count = ARRAY_SIZE(amdgpu_ttm_debugfs_list);
2644         return amdgpu_debugfs_add_files(adev, amdgpu_ttm_debugfs_list, count);
2645 #else
2646         return 0;
2647 #endif
2648 }