drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c

   1 /*
   2  * Copyright 2009 Jerome Glisse.
   3  * All Rights Reserved.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the
   7  * "Software"), to deal in the Software without restriction, including
   8  * without limitation the rights to use, copy, modify, merge, publish,
   9  * distribute, sub license, and/or sell copies of the Software, and to
  10  * permit persons to whom the Software is furnished to do so, subject to
  11  * the following conditions:
  12  *
  13  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  14  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  15  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  16  * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
  17  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  18  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  19  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  20  *
  21  * The above copyright notice and this permission notice (including the
  22  * next paragraph) shall be included in all copies or substantial portions
  23  * of the Software.
  24  *
  25  */
  26 /*
  27  * Authors:
  28  *    Jerome Glisse <glisse@freedesktop.org>
  29  *    Thomas Hellstrom <thomas-at-tungstengraphics-dot-com>
  30  *    Dave Airlie
  31  */
  32
  33 #include <linux/dma-mapping.h>
  34 #include <linux/iommu.h>
  35 #include <linux/hmm.h>
  36 #include <linux/pagemap.h>
  37 #include <linux/sched/task.h>
  38 #include <linux/sched/mm.h>
  39 #include <linux/seq_file.h>
  40 #include <linux/slab.h>
  41 #include <linux/swap.h>
  42 #include <linux/swiotlb.h>
  43 #include <linux/dma-buf.h>
  44 #include <linux/sizes.h>
  45
  46 #include <drm/ttm/ttm_bo_api.h>
  47 #include <drm/ttm/ttm_bo_driver.h>
  48 #include <drm/ttm/ttm_placement.h>
  49 #include <drm/ttm/ttm_module.h>
  50 #include <drm/ttm/ttm_page_alloc.h>
  51
  52 #include <drm/drm_debugfs.h>
  53 #include <drm/amdgpu_drm.h>
  54
  55 #include "amdgpu.h"
  56 #include "amdgpu_object.h"
  57 #include "amdgpu_trace.h"
  58 #include "amdgpu_amdkfd.h"
  59 #include "amdgpu_sdma.h"
  60 #include "amdgpu_ras.h"
  61 #include "bif/bif_4_1_d.h"
  62
  63 #define AMDGPU_TTM_VRAM_MAX_DW_READ     (size_t)128
  64
  65 static int amdgpu_map_buffer(struct ttm_buffer_object *bo,
  66                              struct ttm_mem_reg *mem, unsigned num_pages,
  67                              uint64_t offset, unsigned window,
  68                              struct amdgpu_ring *ring,
  69                              uint64_t *addr);
  70
  71 static int amdgpu_ttm_debugfs_init(struct amdgpu_device *adev);
  72 static void amdgpu_ttm_debugfs_fini(struct amdgpu_device *adev);
  73
  74 static int amdgpu_invalidate_caches(struct ttm_bo_device *bdev, uint32_t flags)
  75 {
  76         return 0;
  77 }
  78
  79 /**
  80  * amdgpu_init_mem_type - Initialize a memory manager for a specific type of
  81  * memory request.
  82  *
  83  * @bdev: The TTM BO device object (contains a reference to amdgpu_device)
  84  * @type: The type of memory requested
  85  * @man: The memory type manager for each domain
  86  *
  87  * This is called by ttm_bo_init_mm() when a buffer object is being
  88  * initialized.
  89  */
  90 static int amdgpu_init_mem_type(struct ttm_bo_device *bdev, uint32_t type,
  91                                 struct ttm_mem_type_manager *man)
  92 {
  93         struct amdgpu_device *adev;
  94
  95         adev = amdgpu_ttm_adev(bdev);
  96
  97         switch (type) {
  98         case TTM_PL_SYSTEM:
  99                 /* System memory */
 100                 man->flags = TTM_MEMTYPE_FLAG_MAPPABLE;
 101                 man->available_caching = TTM_PL_MASK_CACHING;
 102                 man->default_caching = TTM_PL_FLAG_CACHED;
 103                 break;
 104         case TTM_PL_TT:
 105                 /* GTT memory  */
 106                 man->func = &amdgpu_gtt_mgr_func;
 107                 man->gpu_offset = adev->gmc.gart_start;
 108                 man->available_caching = TTM_PL_MASK_CACHING;
 109                 man->default_caching = TTM_PL_FLAG_CACHED;
 110                 man->flags = TTM_MEMTYPE_FLAG_MAPPABLE | TTM_MEMTYPE_FLAG_CMA;
 111                 break;
 112         case TTM_PL_VRAM:
 113                 /* "On-card" video ram */
 114                 man->func = &amdgpu_vram_mgr_func;
 115                 man->gpu_offset = adev->gmc.vram_start;
 116                 man->flags = TTM_MEMTYPE_FLAG_FIXED |
 117                              TTM_MEMTYPE_FLAG_MAPPABLE;
 118                 man->available_caching = TTM_PL_FLAG_UNCACHED | TTM_PL_FLAG_WC;
 119                 man->default_caching = TTM_PL_FLAG_WC;
 120                 break;
 121         case AMDGPU_PL_GDS:
 122         case AMDGPU_PL_GWS:
 123         case AMDGPU_PL_OA:
 124                 /* On-chip GDS memory*/
 125                 man->func = &ttm_bo_manager_func;
 126                 man->gpu_offset = 0;
 127                 man->flags = TTM_MEMTYPE_FLAG_FIXED | TTM_MEMTYPE_FLAG_CMA;
 128                 man->available_caching = TTM_PL_FLAG_UNCACHED;
 129                 man->default_caching = TTM_PL_FLAG_UNCACHED;
 130                 break;
 131         default:
 132                 DRM_ERROR("Unsupported memory type %u\n", (unsigned)type);
 133                 return -EINVAL;
 134         }
 135         return 0;
 136 }
 137
 138 /**
 139  * amdgpu_evict_flags - Compute placement flags
 140  *
 141  * @bo: The buffer object to evict
 142  * @placement: Possible destination(s) for evicted BO
 143  *
 144  * Fill in placement data when ttm_bo_evict() is called
 145  */
 146 static void amdgpu_evict_flags(struct ttm_buffer_object *bo,
 147                                 struct ttm_placement *placement)
 148 {
 149         struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev);
 150         struct amdgpu_bo *abo;
 151         static const struct ttm_place placements = {
 152                 .fpfn = 0,
 153                 .lpfn = 0,
 154                 .flags = TTM_PL_MASK_CACHING | TTM_PL_FLAG_SYSTEM
 155         };
 156
 157         /* Don't handle scatter gather BOs */
 158         if (bo->type == ttm_bo_type_sg) {
 159                 placement->num_placement = 0;
 160                 placement->num_busy_placement = 0;
 161                 return;
 162         }
 163
 164         /* Object isn't an AMDGPU object so ignore */
 165         if (!amdgpu_bo_is_amdgpu_bo(bo)) {
 166                 placement->placement = &placements;
 167                 placement->busy_placement = &placements;
 168                 placement->num_placement = 1;
 169                 placement->num_busy_placement = 1;
 170                 return;
 171         }
 172
 173         abo = ttm_to_amdgpu_bo(bo);
 174         switch (bo->mem.mem_type) {
 175         case AMDGPU_PL_GDS:
 176         case AMDGPU_PL_GWS:
 177         case AMDGPU_PL_OA:
 178                 placement->num_placement = 0;
 179                 placement->num_busy_placement = 0;
 180                 return;
 181
 182         case TTM_PL_VRAM:
 183                 if (!adev->mman.buffer_funcs_enabled) {
 184                         /* Move to system memory */
 185                         amdgpu_bo_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_CPU);
 186                 } else if (!amdgpu_gmc_vram_full_visible(&adev->gmc) &&
 187                            !(abo->flags & AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED) &&
 188                            amdgpu_bo_in_cpu_visible_vram(abo)) {
 189
 190                         /* Try evicting to the CPU inaccessible part of VRAM
 191                          * first, but only set GTT as busy placement, so this
 192                          * BO will be evicted to GTT rather than causing other
 193                          * BOs to be evicted from VRAM
 194                          */
 195                         amdgpu_bo_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_VRAM |
 196                                                          AMDGPU_GEM_DOMAIN_GTT);
 197                         abo->placements[0].fpfn = adev->gmc.visible_vram_size >> PAGE_SHIFT;
 198                         abo->placements[0].lpfn = 0;
 199                         abo->placement.busy_placement = &abo->placements[1];
 200                         abo->placement.num_busy_placement = 1;
 201                 } else {
 202                         /* Move to GTT memory */
 203                         amdgpu_bo_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_GTT);
 204                 }
 205                 break;
 206         case TTM_PL_TT:
 207         default:
 208                 amdgpu_bo_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_CPU);
 209                 break;
 210         }
 211         *placement = abo->placement;
 212 }
 213
 214 /**
 215  * amdgpu_verify_access - Verify access for a mmap call
 216  *
 217  * @bo: The buffer object to map
 218  * @filp: The file pointer from the process performing the mmap
 219  *
 220  * This is called by ttm_bo_mmap() to verify whether a process
 221  * has the right to mmap a BO to their process space.
 222  */
 223 static int amdgpu_verify_access(struct ttm_buffer_object *bo, struct file *filp)
 224 {
 225         struct amdgpu_bo *abo = ttm_to_amdgpu_bo(bo);
 226
 227         /*
 228          * Don't verify access for KFD BOs. They don't have a GEM
 229          * object associated with them.
 230          */
 231         if (abo->kfd_bo)
 232                 return 0;
 233
 234         if (amdgpu_ttm_tt_get_usermm(bo->ttm))
 235                 return -EPERM;
 236         return drm_vma_node_verify_access(&abo->tbo.base.vma_node,
 237                                           filp->private_data);
 238 }
 239
 240 /**
 241  * amdgpu_move_null - Register memory for a buffer object
 242  *
 243  * @bo: The bo to assign the memory to
 244  * @new_mem: The memory to be assigned.
 245  *
 246  * Assign the memory from new_mem to the memory of the buffer object bo.
 247  */
 248 static void amdgpu_move_null(struct ttm_buffer_object *bo,
 249                              struct ttm_mem_reg *new_mem)
 250 {
 251         struct ttm_mem_reg *old_mem = &bo->mem;
 252
 253         BUG_ON(old_mem->mm_node != NULL);
 254         *old_mem = *new_mem;
 255         new_mem->mm_node = NULL;
 256 }
 257
 258 /**
 259  * amdgpu_mm_node_addr - Compute the GPU relative offset of a GTT buffer.
 260  *
 261  * @bo: The bo to assign the memory to.
 262  * @mm_node: Memory manager node for drm allocator.
 263  * @mem: The region where the bo resides.
 264  *
 265  */
 266 static uint64_t amdgpu_mm_node_addr(struct ttm_buffer_object *bo,
 267                                     struct drm_mm_node *mm_node,
 268                                     struct ttm_mem_reg *mem)
 269 {
 270         uint64_t addr = 0;
 271
 272         if (mm_node->start != AMDGPU_BO_INVALID_OFFSET) {
 273                 addr = mm_node->start << PAGE_SHIFT;
 274                 addr += bo->bdev->man[mem->mem_type].gpu_offset;
 275         }
 276         return addr;
 277 }
 278
 279 /**
 280  * amdgpu_find_mm_node - Helper function finds the drm_mm_node corresponding to
 281  * @offset. It also modifies the offset to be within the drm_mm_node returned
 282  *
 283  * @mem: The region where the bo resides.
 284  * @offset: The offset that drm_mm_node is used for finding.
 285  *
 286  */
 287 static struct drm_mm_node *amdgpu_find_mm_node(struct ttm_mem_reg *mem,
 288                                                unsigned long *offset)
 289 {
 290         struct drm_mm_node *mm_node = mem->mm_node;
 291
 292         while (*offset >= (mm_node->size << PAGE_SHIFT)) {
 293                 *offset -= (mm_node->size << PAGE_SHIFT);
 294                 ++mm_node;
 295         }
 296         return mm_node;
 297 }
 298
 299 /**
 300  * amdgpu_copy_ttm_mem_to_mem - Helper function for copy
 301  *
 302  * The function copies @size bytes from {src->mem + src->offset} to
 303  * {dst->mem + dst->offset}. src->bo and dst->bo could be same BO for a
 304  * move and different for a BO to BO copy.
 305  *
 306  * @f: Returns the last fence if multiple jobs are submitted.
 307  */
 308 int amdgpu_ttm_copy_mem_to_mem(struct amdgpu_device *adev,
 309                                struct amdgpu_copy_mem *src,
 310                                struct amdgpu_copy_mem *dst,
 311                                uint64_t size,
 312                                struct dma_resv *resv,
 313                                struct dma_fence **f)
 314 {
 315         struct amdgpu_ring *ring = adev->mman.buffer_funcs_ring;
 316         struct drm_mm_node *src_mm, *dst_mm;
 317         uint64_t src_node_start, dst_node_start, src_node_size,
 318                  dst_node_size, src_page_offset, dst_page_offset;
 319         struct dma_fence *fence = NULL;
 320         int r = 0;
 321         const uint64_t GTT_MAX_BYTES = (AMDGPU_GTT_MAX_TRANSFER_SIZE *
 322                                         AMDGPU_GPU_PAGE_SIZE);
 323
 324         if (!adev->mman.buffer_funcs_enabled) {
 325                 DRM_ERROR("Trying to move memory with ring turned off.\n");
 326                 return -EINVAL;
 327         }
 328
 329         src_mm = amdgpu_find_mm_node(src->mem, &src->offset);
 330         src_node_start = amdgpu_mm_node_addr(src->bo, src_mm, src->mem) +
 331                                              src->offset;
 332         src_node_size = (src_mm->size << PAGE_SHIFT) - src->offset;
 333         src_page_offset = src_node_start & (PAGE_SIZE - 1);
 334
 335         dst_mm = amdgpu_find_mm_node(dst->mem, &dst->offset);
 336         dst_node_start = amdgpu_mm_node_addr(dst->bo, dst_mm, dst->mem) +
 337                                              dst->offset;
 338         dst_node_size = (dst_mm->size << PAGE_SHIFT) - dst->offset;
 339         dst_page_offset = dst_node_start & (PAGE_SIZE - 1);
 340
 341         mutex_lock(&adev->mman.gtt_window_lock);
 342
 343         while (size) {
 344                 unsigned long cur_size;
 345                 uint64_t from = src_node_start, to = dst_node_start;
 346                 struct dma_fence *next;
 347
 348                 /* Copy size cannot exceed GTT_MAX_BYTES. So if src or dst
 349                  * begins at an offset, then adjust the size accordingly
 350                  */
 351                 cur_size = min3(min(src_node_size, dst_node_size), size,
 352                                 GTT_MAX_BYTES);
 353                 if (cur_size + src_page_offset > GTT_MAX_BYTES ||
 354                     cur_size + dst_page_offset > GTT_MAX_BYTES)
 355                         cur_size -= max(src_page_offset, dst_page_offset);
 356
 357                 /* Map only what needs to be accessed. Map src to window 0 and
 358                  * dst to window 1
 359                  */
 360                 if (src->mem->start == AMDGPU_BO_INVALID_OFFSET) {
 361                         r = amdgpu_map_buffer(src->bo, src->mem,
 362                                         PFN_UP(cur_size + src_page_offset),
 363                                         src_node_start, 0, ring,
 364                                         &from);
 365                         if (r)
 366                                 goto error;
 367                         /* Adjust the offset because amdgpu_map_buffer returns
 368                          * start of mapped page
 369                          */
 370                         from += src_page_offset;
 371                 }
 372
 373                 if (dst->mem->start == AMDGPU_BO_INVALID_OFFSET) {
 374                         r = amdgpu_map_buffer(dst->bo, dst->mem,
 375                                         PFN_UP(cur_size + dst_page_offset),
 376                                         dst_node_start, 1, ring,
 377                                         &to);
 378                         if (r)
 379                                 goto error;
 380                         to += dst_page_offset;
 381                 }
 382
 383                 r = amdgpu_copy_buffer(ring, from, to, cur_size,
 384                                        resv, &next, false, true);
 385                 if (r)
 386                         goto error;
 387
 388                 dma_fence_put(fence);
 389                 fence = next;
 390
 391                 size -= cur_size;
 392                 if (!size)
 393                         break;
 394
 395                 src_node_size -= cur_size;
 396                 if (!src_node_size) {
 397                         src_node_start = amdgpu_mm_node_addr(src->bo, ++src_mm,
 398                                                              src->mem);
 399                         src_node_size = (src_mm->size << PAGE_SHIFT);
 400                         src_page_offset = 0;
 401                 } else {
 402                         src_node_start += cur_size;
 403                         src_page_offset = src_node_start & (PAGE_SIZE - 1);
 404                 }
 405                 dst_node_size -= cur_size;
 406                 if (!dst_node_size) {
 407                         dst_node_start = amdgpu_mm_node_addr(dst->bo, ++dst_mm,
 408                                                              dst->mem);
 409                         dst_node_size = (dst_mm->size << PAGE_SHIFT);
 410                         dst_page_offset = 0;
 411                 } else {
 412                         dst_node_start += cur_size;
 413                         dst_page_offset = dst_node_start & (PAGE_SIZE - 1);
 414                 }
 415         }
 416 error:
 417         mutex_unlock(&adev->mman.gtt_window_lock);
 418         if (f)
 419                 *f = dma_fence_get(fence);
 420         dma_fence_put(fence);
 421         return r;
 422 }
 423
 424 /**
 425  * amdgpu_move_blit - Copy an entire buffer to another buffer
 426  *
 427  * This is a helper called by amdgpu_bo_move() and amdgpu_move_vram_ram() to
 428  * help move buffers to and from VRAM.
 429  */
 430 static int amdgpu_move_blit(struct ttm_buffer_object *bo,
 431                             bool evict, bool no_wait_gpu,
 432                             struct ttm_mem_reg *new_mem,
 433                             struct ttm_mem_reg *old_mem)
 434 {
 435         struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev);
 436         struct amdgpu_copy_mem src, dst;
 437         struct dma_fence *fence = NULL;
 438         int r;
 439
 440         src.bo = bo;
 441         dst.bo = bo;
 442         src.mem = old_mem;
 443         dst.mem = new_mem;
 444         src.offset = 0;
 445         dst.offset = 0;
 446
 447         r = amdgpu_ttm_copy_mem_to_mem(adev, &src, &dst,
 448                                        new_mem->num_pages << PAGE_SHIFT,
 449                                        bo->base.resv, &fence);
 450         if (r)
 451                 goto error;
 452
 453         /* clear the space being freed */
 454         if (old_mem->mem_type == TTM_PL_VRAM &&
 455             (ttm_to_amdgpu_bo(bo)->flags &
 456              AMDGPU_GEM_CREATE_VRAM_WIPE_ON_RELEASE)) {
 457                 struct dma_fence *wipe_fence = NULL;
 458
 459                 r = amdgpu_fill_buffer(ttm_to_amdgpu_bo(bo), AMDGPU_POISON,
 460                                        NULL, &wipe_fence);
 461                 if (r) {
 462                         goto error;
 463                 } else if (wipe_fence) {
 464                         dma_fence_put(fence);
 465                         fence = wipe_fence;
 466                 }
 467         }
 468
 469         /* Always block for VM page tables before committing the new location */
 470         if (bo->type == ttm_bo_type_kernel)
 471                 r = ttm_bo_move_accel_cleanup(bo, fence, true, new_mem);
 472         else
 473                 r = ttm_bo_pipeline_move(bo, fence, evict, new_mem);
 474         dma_fence_put(fence);
 475         return r;
 476
 477 error:
 478         if (fence)
 479                 dma_fence_wait(fence, false);
 480         dma_fence_put(fence);
 481         return r;
 482 }
 483
 484 /**
 485  * amdgpu_move_vram_ram - Copy VRAM buffer to RAM buffer
 486  *
 487  * Called by amdgpu_bo_move().
 488  */
 489 static int amdgpu_move_vram_ram(struct ttm_buffer_object *bo, bool evict,
 490                                 struct ttm_operation_ctx *ctx,
 491                                 struct ttm_mem_reg *new_mem)
 492 {
 493         struct ttm_mem_reg *old_mem = &bo->mem;
 494         struct ttm_mem_reg tmp_mem;
 495         struct ttm_place placements;
 496         struct ttm_placement placement;
 497         int r;
 498
 499         /* create space/pages for new_mem in GTT space */
 500         tmp_mem = *new_mem;
 501         tmp_mem.mm_node = NULL;
 502         placement.num_placement = 1;
 503         placement.placement = &placements;
 504         placement.num_busy_placement = 1;
 505         placement.busy_placement = &placements;
 506         placements.fpfn = 0;
 507         placements.lpfn = 0;
 508         placements.flags = TTM_PL_MASK_CACHING | TTM_PL_FLAG_TT;
 509         r = ttm_bo_mem_space(bo, &placement, &tmp_mem, ctx);
 510         if (unlikely(r)) {
 511                 pr_err("Failed to find GTT space for blit from VRAM\n");
 512                 return r;
 513         }
 514
 515         /* set caching flags */
 516         r = ttm_tt_set_placement_caching(bo->ttm, tmp_mem.placement);
 517         if (unlikely(r)) {
 518                 goto out_cleanup;
 519         }
 520
 521         /* Bind the memory to the GTT space */
 522         r = ttm_tt_bind(bo->ttm, &tmp_mem, ctx);
 523         if (unlikely(r)) {
 524                 goto out_cleanup;
 525         }
 526
 527         /* blit VRAM to GTT */
 528         r = amdgpu_move_blit(bo, evict, ctx->no_wait_gpu, &tmp_mem, old_mem);
 529         if (unlikely(r)) {
 530                 goto out_cleanup;
 531         }
 532
 533         /* move BO (in tmp_mem) to new_mem */
 534         r = ttm_bo_move_ttm(bo, ctx, new_mem);
 535 out_cleanup:
 536         ttm_bo_mem_put(bo, &tmp_mem);
 537         return r;
 538 }
 539
 540 /**
 541  * amdgpu_move_ram_vram - Copy buffer from RAM to VRAM
 542  *
 543  * Called by amdgpu_bo_move().
 544  */
 545 static int amdgpu_move_ram_vram(struct ttm_buffer_object *bo, bool evict,
 546                                 struct ttm_operation_ctx *ctx,
 547                                 struct ttm_mem_reg *new_mem)
 548 {
 549         struct ttm_mem_reg *old_mem = &bo->mem;
 550         struct ttm_mem_reg tmp_mem;
 551         struct ttm_placement placement;
 552         struct ttm_place placements;
 553         int r;
 554
 555         /* make space in GTT for old_mem buffer */
 556         tmp_mem = *new_mem;
 557         tmp_mem.mm_node = NULL;
 558         placement.num_placement = 1;
 559         placement.placement = &placements;
 560         placement.num_busy_placement = 1;
 561         placement.busy_placement = &placements;
 562         placements.fpfn = 0;
 563         placements.lpfn = 0;
 564         placements.flags = TTM_PL_MASK_CACHING | TTM_PL_FLAG_TT;
 565         r = ttm_bo_mem_space(bo, &placement, &tmp_mem, ctx);
 566         if (unlikely(r)) {
 567                 pr_err("Failed to find GTT space for blit to VRAM\n");
 568                 return r;
 569         }
 570
 571         /* move/bind old memory to GTT space */
 572         r = ttm_bo_move_ttm(bo, ctx, &tmp_mem);
 573         if (unlikely(r)) {
 574                 goto out_cleanup;
 575         }
 576
 577         /* copy to VRAM */
 578         r = amdgpu_move_blit(bo, evict, ctx->no_wait_gpu, new_mem, old_mem);
 579         if (unlikely(r)) {
 580                 goto out_cleanup;
 581         }
 582 out_cleanup:
 583         ttm_bo_mem_put(bo, &tmp_mem);
 584         return r;
 585 }
 586
 587 /**
 588  * amdgpu_mem_visible - Check that memory can be accessed by ttm_bo_move_memcpy
 589  *
 590  * Called by amdgpu_bo_move()
 591  */
 592 static bool amdgpu_mem_visible(struct amdgpu_device *adev,
 593                                struct ttm_mem_reg *mem)
 594 {
 595         struct drm_mm_node *nodes = mem->mm_node;
 596
 597         if (mem->mem_type == TTM_PL_SYSTEM ||
 598             mem->mem_type == TTM_PL_TT)
 599                 return true;
 600         if (mem->mem_type != TTM_PL_VRAM)
 601                 return false;
 602
 603         /* ttm_mem_reg_ioremap only supports contiguous memory */
 604         if (nodes->size != mem->num_pages)
 605                 return false;
 606
 607         return ((nodes->start + nodes->size) << PAGE_SHIFT)
 608                 <= adev->gmc.visible_vram_size;
 609 }
 610
 611 /**
 612  * amdgpu_bo_move - Move a buffer object to a new memory location
 613  *
 614  * Called by ttm_bo_handle_move_mem()
 615  */
 616 static int amdgpu_bo_move(struct ttm_buffer_object *bo, bool evict,
 617                           struct ttm_operation_ctx *ctx,
 618                           struct ttm_mem_reg *new_mem)
 619 {
 620         struct amdgpu_device *adev;
 621         struct amdgpu_bo *abo;
 622         struct ttm_mem_reg *old_mem = &bo->mem;
 623         int r;
 624
 625         /* Can't move a pinned BO */
 626         abo = ttm_to_amdgpu_bo(bo);
 627         if (WARN_ON_ONCE(abo->pin_count > 0))
 628                 return -EINVAL;
 629
 630         adev = amdgpu_ttm_adev(bo->bdev);
 631
 632         if (old_mem->mem_type == TTM_PL_SYSTEM && bo->ttm == NULL) {
 633                 amdgpu_move_null(bo, new_mem);
 634                 return 0;
 635         }
 636         if ((old_mem->mem_type == TTM_PL_TT &&
 637              new_mem->mem_type == TTM_PL_SYSTEM) ||
 638             (old_mem->mem_type == TTM_PL_SYSTEM &&
 639              new_mem->mem_type == TTM_PL_TT)) {
 640                 /* bind is enough */
 641                 amdgpu_move_null(bo, new_mem);
 642                 return 0;
 643         }
 644         if (old_mem->mem_type == AMDGPU_PL_GDS ||
 645             old_mem->mem_type == AMDGPU_PL_GWS ||
 646             old_mem->mem_type == AMDGPU_PL_OA ||
 647             new_mem->mem_type == AMDGPU_PL_GDS ||
 648             new_mem->mem_type == AMDGPU_PL_GWS ||
 649             new_mem->mem_type == AMDGPU_PL_OA) {
 650                 /* Nothing to save here */
 651                 amdgpu_move_null(bo, new_mem);
 652                 return 0;
 653         }
 654
 655         if (!adev->mman.buffer_funcs_enabled) {
 656                 r = -ENODEV;
 657                 goto memcpy;
 658         }
 659
 660         if (old_mem->mem_type == TTM_PL_VRAM &&
 661             new_mem->mem_type == TTM_PL_SYSTEM) {
 662                 r = amdgpu_move_vram_ram(bo, evict, ctx, new_mem);
 663         } else if (old_mem->mem_type == TTM_PL_SYSTEM &&
 664                    new_mem->mem_type == TTM_PL_VRAM) {
 665                 r = amdgpu_move_ram_vram(bo, evict, ctx, new_mem);
 666         } else {
 667                 r = amdgpu_move_blit(bo, evict, ctx->no_wait_gpu,
 668                                      new_mem, old_mem);
 669         }
 670
 671         if (r) {
 672 memcpy:
 673                 /* Check that all memory is CPU accessible */
 674                 if (!amdgpu_mem_visible(adev, old_mem) ||
 675                     !amdgpu_mem_visible(adev, new_mem)) {
 676                         pr_err("Move buffer fallback to memcpy unavailable\n");
 677                         return r;
 678                 }
 679
 680                 r = ttm_bo_move_memcpy(bo, ctx, new_mem);
 681                 if (r)
 682                         return r;
 683         }
 684
 685         if (bo->type == ttm_bo_type_device &&
 686             new_mem->mem_type == TTM_PL_VRAM &&
 687             old_mem->mem_type != TTM_PL_VRAM) {
 688                 /* amdgpu_bo_fault_reserve_notify will re-set this if the CPU
 689                  * accesses the BO after it's moved.
 690                  */
 691                 abo->flags &= ~AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED;
 692         }
 693
 694         /* update statistics */
 695         atomic64_add((u64)bo->num_pages << PAGE_SHIFT, &adev->num_bytes_moved);
 696         return 0;
 697 }
 698
 699 /**
 700  * amdgpu_ttm_io_mem_reserve - Reserve a block of memory during a fault
 701  *
 702  * Called by ttm_mem_io_reserve() ultimately via ttm_bo_vm_fault()
 703  */
 704 static int amdgpu_ttm_io_mem_reserve(struct ttm_bo_device *bdev, struct ttm_mem_reg *mem)
 705 {
 706         struct ttm_mem_type_manager *man = &bdev->man[mem->mem_type];
 707         struct amdgpu_device *adev = amdgpu_ttm_adev(bdev);
 708         struct drm_mm_node *mm_node = mem->mm_node;
 709
 710         mem->bus.addr = NULL;
 711         mem->bus.offset = 0;
 712         mem->bus.size = mem->num_pages << PAGE_SHIFT;
 713         mem->bus.base = 0;
 714         mem->bus.is_iomem = false;
 715         if (!(man->flags & TTM_MEMTYPE_FLAG_MAPPABLE))
 716                 return -EINVAL;
 717         switch (mem->mem_type) {
 718         case TTM_PL_SYSTEM:
 719                 /* system memory */
 720                 return 0;
 721         case TTM_PL_TT:
 722                 break;
 723         case TTM_PL_VRAM:
 724                 mem->bus.offset = mem->start << PAGE_SHIFT;
 725                 /* check if it's visible */
 726                 if ((mem->bus.offset + mem->bus.size) > adev->gmc.visible_vram_size)
 727                         return -EINVAL;
 728                 /* Only physically contiguous buffers apply. In a contiguous
 729                  * buffer, size of the first mm_node would match the number of
 730                  * pages in ttm_mem_reg.
 731                  */
 732                 if (adev->mman.aper_base_kaddr &&
 733                     (mm_node->size == mem->num_pages))
 734                         mem->bus.addr = (u8 *)adev->mman.aper_base_kaddr +
 735                                         mem->bus.offset;
 736
 737                 mem->bus.base = adev->gmc.aper_base;
 738                 mem->bus.is_iomem = true;
 739                 break;
 740         default:
 741                 return -EINVAL;
 742         }
 743         return 0;
 744 }
 745
 746 static void amdgpu_ttm_io_mem_free(struct ttm_bo_device *bdev, struct ttm_mem_reg *mem)
 747 {
 748 }
 749
 750 static unsigned long amdgpu_ttm_io_mem_pfn(struct ttm_buffer_object *bo,
 751                                            unsigned long page_offset)
 752 {
 753         struct drm_mm_node *mm;
 754         unsigned long offset = (page_offset << PAGE_SHIFT);
 755
 756         mm = amdgpu_find_mm_node(&bo->mem, &offset);
 757         return (bo->mem.bus.base >> PAGE_SHIFT) + mm->start +
 758                 (offset >> PAGE_SHIFT);
 759 }
 760
 761 /*
 762  * TTM backend functions.
 763  */
 764 struct amdgpu_ttm_tt {
 765         struct ttm_dma_tt       ttm;
 766         struct drm_gem_object   *gobj;
 767         u64                     offset;
 768         uint64_t                userptr;
 769         struct task_struct      *usertask;
 770         uint32_t                userflags;
 771 #if IS_ENABLED(CONFIG_DRM_AMDGPU_USERPTR)
 772         struct hmm_range        *range;
 773 #endif
 774 };
 775
 776 #ifdef CONFIG_DRM_AMDGPU_USERPTR
 777 /* flags used by HMM internal, not related to CPU/GPU PTE flags */
 778 static const uint64_t hmm_range_flags[HMM_PFN_FLAG_MAX] = {
 779         (1 << 0), /* HMM_PFN_VALID */
 780         (1 << 1), /* HMM_PFN_WRITE */
 781         0 /* HMM_PFN_DEVICE_PRIVATE */
 782 };
 783
 784 static const uint64_t hmm_range_values[HMM_PFN_VALUE_MAX] = {
 785         0xfffffffffffffffeUL, /* HMM_PFN_ERROR */
 786         0, /* HMM_PFN_NONE */
 787         0xfffffffffffffffcUL /* HMM_PFN_SPECIAL */
 788 };
 789
 790 /**
 791  * amdgpu_ttm_tt_get_user_pages - get device accessible pages that back user
 792  * memory and start HMM tracking CPU page table update
 793  *
 794  * Calling function must call amdgpu_ttm_tt_userptr_range_done() once and only
 795  * once afterwards to stop HMM tracking
 796  */
 797 int amdgpu_ttm_tt_get_user_pages(struct amdgpu_bo *bo, struct page **pages)
 798 {
 799         struct ttm_tt *ttm = bo->tbo.ttm;
 800         struct amdgpu_ttm_tt *gtt = (void *)ttm;
 801         unsigned long start = gtt->userptr;
 802         struct vm_area_struct *vma;
 803         struct hmm_range *range;
 804         unsigned long timeout;
 805         struct mm_struct *mm;
 806         unsigned long i;
 807         int r = 0;
 808
 809         mm = bo->notifier.mm;
 810         if (unlikely(!mm)) {
 811                 DRM_DEBUG_DRIVER("BO is not registered?\n");
 812                 return -EFAULT;
 813         }
 814
 815         /* Another get_user_pages is running at the same time?? */
 816         if (WARN_ON(gtt->range))
 817                 return -EFAULT;
 818
 819         if (!mmget_not_zero(mm)) /* Happens during process shutdown */
 820                 return -ESRCH;
 821
 822         range = kzalloc(sizeof(*range), GFP_KERNEL);
 823         if (unlikely(!range)) {
 824                 r = -ENOMEM;
 825                 goto out;
 826         }
 827         range->notifier = &bo->notifier;
 828         range->flags = hmm_range_flags;
 829         range->values = hmm_range_values;
 830         range->pfn_shift = PAGE_SHIFT;
 831         range->start = bo->notifier.interval_tree.start;
 832         range->end = bo->notifier.interval_tree.last + 1;
 833         range->default_flags = hmm_range_flags[HMM_PFN_VALID];
 834         if (!amdgpu_ttm_tt_is_readonly(ttm))
 835                 range->default_flags |= range->flags[HMM_PFN_WRITE];
 836
 837         range->pfns = kvmalloc_array(ttm->num_pages, sizeof(*range->pfns),
 838                                      GFP_KERNEL);
 839         if (unlikely(!range->pfns)) {
 840                 r = -ENOMEM;
 841                 goto out_free_ranges;
 842         }
 843
 844         down_read(&mm->mmap_sem);
 845         vma = find_vma(mm, start);
 846         if (unlikely(!vma || start < vma->vm_start)) {
 847                 r = -EFAULT;
 848                 goto out_unlock;
 849         }
 850         if (unlikely((gtt->userflags & AMDGPU_GEM_USERPTR_ANONONLY) &&
 851                 vma->vm_file)) {
 852                 r = -EPERM;
 853                 goto out_unlock;
 854         }
 855         up_read(&mm->mmap_sem);
 856         timeout = jiffies + msecs_to_jiffies(HMM_RANGE_DEFAULT_TIMEOUT);
 857
 858 retry:
 859         range->notifier_seq = mmu_interval_read_begin(&bo->notifier);
 860
 861         down_read(&mm->mmap_sem);
 862         r = hmm_range_fault(range, 0);
 863         up_read(&mm->mmap_sem);
 864         if (unlikely(r <= 0)) {
 865                 /*
 866                  * FIXME: This timeout should encompass the retry from
 867                  * mmu_interval_read_retry() as well.
 868                  */
 869                 if ((r == 0 || r == -EBUSY) && !time_after(jiffies, timeout))
 870                         goto retry;
 871                 goto out_free_pfns;
 872         }
 873
 874         for (i = 0; i < ttm->num_pages; i++) {
 875                 /* FIXME: The pages cannot be touched outside the notifier_lock */
 876                 pages[i] = hmm_device_entry_to_page(range, range->pfns[i]);
 877                 if (unlikely(!pages[i])) {
 878                         pr_err("Page fault failed for pfn[%lu] = 0x%llx\n",
 879                                i, range->pfns[i]);
 880                         r = -ENOMEM;
 881
 882                         goto out_free_pfns;
 883                 }
 884         }
 885
 886         gtt->range = range;
 887         mmput(mm);
 888
 889         return 0;
 890
 891 out_unlock:
 892         up_read(&mm->mmap_sem);
 893 out_free_pfns:
 894         kvfree(range->pfns);
 895 out_free_ranges:
 896         kfree(range);
 897 out:
 898         mmput(mm);
 899         return r;
 900 }
 901
 902 /**
 903  * amdgpu_ttm_tt_userptr_range_done - stop HMM track the CPU page table change
 904  * Check if the pages backing this ttm range have been invalidated
 905  *
 906  * Returns: true if pages are still valid
 907  */
 908 bool amdgpu_ttm_tt_get_user_pages_done(struct ttm_tt *ttm)
 909 {
 910         struct amdgpu_ttm_tt *gtt = (void *)ttm;
 911         bool r = false;
 912
 913         if (!gtt || !gtt->userptr)
 914                 return false;
 915
 916         DRM_DEBUG_DRIVER("user_pages_done 0x%llx pages 0x%lx\n",
 917                 gtt->userptr, ttm->num_pages);
 918
 919         WARN_ONCE(!gtt->range || !gtt->range->pfns,
 920                 "No user pages to check\n");
 921
 922         if (gtt->range) {
 923                 /*
 924                  * FIXME: Must always hold notifier_lock for this, and must
 925                  * not ignore the return code.
 926                  */
 927                 r = mmu_interval_read_retry(gtt->range->notifier,
 928                                          gtt->range->notifier_seq);
 929                 kvfree(gtt->range->pfns);
 930                 kfree(gtt->range);
 931                 gtt->range = NULL;
 932         }
 933
 934         return !r;
 935 }
 936 #endif
 937
 938 /**
 939  * amdgpu_ttm_tt_set_user_pages - Copy pages in, putting old pages as necessary.
 940  *
 941  * Called by amdgpu_cs_list_validate(). This creates the page list
 942  * that backs user memory and will ultimately be mapped into the device
 943  * address space.
 944  */
 945 void amdgpu_ttm_tt_set_user_pages(struct ttm_tt *ttm, struct page **pages)
 946 {
 947         unsigned long i;
 948
 949         for (i = 0; i < ttm->num_pages; ++i)
 950                 ttm->pages[i] = pages ? pages[i] : NULL;
 951 }
 952
 953 /**
 954  * amdgpu_ttm_tt_pin_userptr -  prepare the sg table with the user pages
 955  *
 956  * Called by amdgpu_ttm_backend_bind()
 957  **/
 958 static int amdgpu_ttm_tt_pin_userptr(struct ttm_tt *ttm)
 959 {
 960         struct amdgpu_device *adev = amdgpu_ttm_adev(ttm->bdev);
 961         struct amdgpu_ttm_tt *gtt = (void *)ttm;
 962         unsigned nents;
 963         int r;
 964
 965         int write = !(gtt->userflags & AMDGPU_GEM_USERPTR_READONLY);
 966         enum dma_data_direction direction = write ?
 967                 DMA_BIDIRECTIONAL : DMA_TO_DEVICE;
 968
 969         /* Allocate an SG array and squash pages into it */
 970         r = sg_alloc_table_from_pages(ttm->sg, ttm->pages, ttm->num_pages, 0,
 971                                       ttm->num_pages << PAGE_SHIFT,
 972                                       GFP_KERNEL);
 973         if (r)
 974                 goto release_sg;
 975
 976         /* Map SG to device */
 977         r = -ENOMEM;
 978         nents = dma_map_sg(adev->dev, ttm->sg->sgl, ttm->sg->nents, direction);
 979         if (nents != ttm->sg->nents)
 980                 goto release_sg;
 981
 982         /* convert SG to linear array of pages and dma addresses */
 983         drm_prime_sg_to_page_addr_arrays(ttm->sg, ttm->pages,
 984                                          gtt->ttm.dma_address, ttm->num_pages);
 985
 986         return 0;
 987
 988 release_sg:
 989         kfree(ttm->sg);
 990         return r;
 991 }
 992
 993 /**
 994  * amdgpu_ttm_tt_unpin_userptr - Unpin and unmap userptr pages
 995  */
 996 static void amdgpu_ttm_tt_unpin_userptr(struct ttm_tt *ttm)
 997 {
 998         struct amdgpu_device *adev = amdgpu_ttm_adev(ttm->bdev);
 999         struct amdgpu_ttm_tt *gtt = (void *)ttm;
1000
1001         int write = !(gtt->userflags & AMDGPU_GEM_USERPTR_READONLY);
1002         enum dma_data_direction direction = write ?
1003                 DMA_BIDIRECTIONAL : DMA_TO_DEVICE;
1004
1005         /* double check that we don't free the table twice */
1006         if (!ttm->sg->sgl)
1007                 return;
1008
1009         /* unmap the pages mapped to the device */
1010         dma_unmap_sg(adev->dev, ttm->sg->sgl, ttm->sg->nents, direction);
1011
1012         sg_free_table(ttm->sg);
1013
1014 #if IS_ENABLED(CONFIG_DRM_AMDGPU_USERPTR)
1015         if (gtt->range) {
1016                 unsigned long i;
1017
1018                 for (i = 0; i < ttm->num_pages; i++) {
1019                         if (ttm->pages[i] !=
1020                                 hmm_device_entry_to_page(gtt->range,
1021                                               gtt->range->pfns[i]))
1022                                 break;
1023                 }
1024
1025                 WARN((i == ttm->num_pages), "Missing get_user_page_done\n");
1026         }
1027 #endif
1028 }
1029
1030 int amdgpu_ttm_gart_bind(struct amdgpu_device *adev,
1031                                 struct ttm_buffer_object *tbo,
1032                                 uint64_t flags)
1033 {
1034         struct amdgpu_bo *abo = ttm_to_amdgpu_bo(tbo);
1035         struct ttm_tt *ttm = tbo->ttm;
1036         struct amdgpu_ttm_tt *gtt = (void *)ttm;
1037         int r;
1038
1039         if (abo->flags & AMDGPU_GEM_CREATE_MQD_GFX9) {
1040                 uint64_t page_idx = 1;
1041
1042                 r = amdgpu_gart_bind(adev, gtt->offset, page_idx,
1043                                 ttm->pages, gtt->ttm.dma_address, flags);
1044                 if (r)
1045                         goto gart_bind_fail;
1046
1047                 /* Patch mtype of the second part BO */
1048                 flags &= ~AMDGPU_PTE_MTYPE_VG10_MASK;
1049                 flags |= AMDGPU_PTE_MTYPE_VG10(AMDGPU_MTYPE_NC);
1050
1051                 r = amdgpu_gart_bind(adev,
1052                                 gtt->offset + (page_idx << PAGE_SHIFT),
1053                                 ttm->num_pages - page_idx,
1054                                 &ttm->pages[page_idx],
1055                                 &(gtt->ttm.dma_address[page_idx]), flags);
1056         } else {
1057                 r = amdgpu_gart_bind(adev, gtt->offset, ttm->num_pages,
1058                                      ttm->pages, gtt->ttm.dma_address, flags);
1059         }
1060
1061 gart_bind_fail:
1062         if (r)
1063                 DRM_ERROR("failed to bind %lu pages at 0x%08llX\n",
1064                           ttm->num_pages, gtt->offset);
1065
1066         return r;
1067 }
1068
1069 /**
1070  * amdgpu_ttm_backend_bind - Bind GTT memory
1071  *
1072  * Called by ttm_tt_bind() on behalf of ttm_bo_handle_move_mem().
1073  * This handles binding GTT memory to the device address space.
1074  */
1075 static int amdgpu_ttm_backend_bind(struct ttm_tt *ttm,
1076                                    struct ttm_mem_reg *bo_mem)
1077 {
1078         struct amdgpu_device *adev = amdgpu_ttm_adev(ttm->bdev);
1079         struct amdgpu_ttm_tt *gtt = (void*)ttm;
1080         uint64_t flags;
1081         int r = 0;
1082
1083         if (gtt->userptr) {
1084                 r = amdgpu_ttm_tt_pin_userptr(ttm);
1085                 if (r) {
1086                         DRM_ERROR("failed to pin userptr\n");
1087                         return r;
1088                 }
1089         }
1090         if (!ttm->num_pages) {
1091                 WARN(1, "nothing to bind %lu pages for mreg %p back %p!\n",
1092                      ttm->num_pages, bo_mem, ttm);
1093         }
1094
1095         if (bo_mem->mem_type == AMDGPU_PL_GDS ||
1096             bo_mem->mem_type == AMDGPU_PL_GWS ||
1097             bo_mem->mem_type == AMDGPU_PL_OA)
1098                 return -EINVAL;
1099
1100         if (!amdgpu_gtt_mgr_has_gart_addr(bo_mem)) {
1101                 gtt->offset = AMDGPU_BO_INVALID_OFFSET;
1102                 return 0;
1103         }
1104
1105         /* compute PTE flags relevant to this BO memory */
1106         flags = amdgpu_ttm_tt_pte_flags(adev, ttm, bo_mem);
1107
1108         /* bind pages into GART page tables */
1109         gtt->offset = (u64)bo_mem->start << PAGE_SHIFT;
1110         r = amdgpu_gart_bind(adev, gtt->offset, ttm->num_pages,
1111                 ttm->pages, gtt->ttm.dma_address, flags);
1112
1113         if (r)
1114                 DRM_ERROR("failed to bind %lu pages at 0x%08llX\n",
1115                           ttm->num_pages, gtt->offset);
1116         return r;
1117 }
1118
1119 /**
1120  * amdgpu_ttm_alloc_gart - Allocate GART memory for buffer object
1121  */
1122 int amdgpu_ttm_alloc_gart(struct ttm_buffer_object *bo)
1123 {
1124         struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev);
1125         struct ttm_operation_ctx ctx = { false, false };
1126         struct amdgpu_ttm_tt *gtt = (void*)bo->ttm;
1127         struct ttm_mem_reg tmp;
1128         struct ttm_placement placement;
1129         struct ttm_place placements;
1130         uint64_t addr, flags;
1131         int r;
1132
1133         if (bo->mem.start != AMDGPU_BO_INVALID_OFFSET)
1134                 return 0;
1135
1136         addr = amdgpu_gmc_agp_addr(bo);
1137         if (addr != AMDGPU_BO_INVALID_OFFSET) {
1138                 bo->mem.start = addr >> PAGE_SHIFT;
1139         } else {
1140
1141                 /* allocate GART space */
1142                 tmp = bo->mem;
1143                 tmp.mm_node = NULL;
1144                 placement.num_placement = 1;
1145                 placement.placement = &placements;
1146                 placement.num_busy_placement = 1;
1147                 placement.busy_placement = &placements;
1148                 placements.fpfn = 0;
1149                 placements.lpfn = adev->gmc.gart_size >> PAGE_SHIFT;
1150                 placements.flags = (bo->mem.placement & ~TTM_PL_MASK_MEM) |
1151                         TTM_PL_FLAG_TT;
1152
1153                 r = ttm_bo_mem_space(bo, &placement, &tmp, &ctx);
1154                 if (unlikely(r))
1155                         return r;
1156
1157                 /* compute PTE flags for this buffer object */
1158                 flags = amdgpu_ttm_tt_pte_flags(adev, bo->ttm, &tmp);
1159
1160                 /* Bind pages */
1161                 gtt->offset = (u64)tmp.start << PAGE_SHIFT;
1162                 r = amdgpu_ttm_gart_bind(adev, bo, flags);
1163                 if (unlikely(r)) {
1164                         ttm_bo_mem_put(bo, &tmp);
1165                         return r;
1166                 }
1167
1168                 ttm_bo_mem_put(bo, &bo->mem);
1169                 bo->mem = tmp;
1170         }
1171
1172         bo->offset = (bo->mem.start << PAGE_SHIFT) +
1173                 bo->bdev->man[bo->mem.mem_type].gpu_offset;
1174
1175         return 0;
1176 }
1177
1178 /**
1179  * amdgpu_ttm_recover_gart - Rebind GTT pages
1180  *
1181  * Called by amdgpu_gtt_mgr_recover() from amdgpu_device_reset() to
1182  * rebind GTT pages during a GPU reset.
1183  */
1184 int amdgpu_ttm_recover_gart(struct ttm_buffer_object *tbo)
1185 {
1186         struct amdgpu_device *adev = amdgpu_ttm_adev(tbo->bdev);
1187         uint64_t flags;
1188         int r;
1189
1190         if (!tbo->ttm)
1191                 return 0;
1192
1193         flags = amdgpu_ttm_tt_pte_flags(adev, tbo->ttm, &tbo->mem);
1194         r = amdgpu_ttm_gart_bind(adev, tbo, flags);
1195
1196         return r;
1197 }
1198
1199 /**
1200  * amdgpu_ttm_backend_unbind - Unbind GTT mapped pages
1201  *
1202  * Called by ttm_tt_unbind() on behalf of ttm_bo_move_ttm() and
1203  * ttm_tt_destroy().
1204  */
1205 static int amdgpu_ttm_backend_unbind(struct ttm_tt *ttm)
1206 {
1207         struct amdgpu_device *adev = amdgpu_ttm_adev(ttm->bdev);
1208         struct amdgpu_ttm_tt *gtt = (void *)ttm;
1209         int r;
1210
1211         /* if the pages have userptr pinning then clear that first */
1212         if (gtt->userptr)
1213                 amdgpu_ttm_tt_unpin_userptr(ttm);
1214
1215         if (gtt->offset == AMDGPU_BO_INVALID_OFFSET)
1216                 return 0;
1217
1218         /* unbind shouldn't be done for GDS/GWS/OA in ttm_bo_clean_mm */
1219         r = amdgpu_gart_unbind(adev, gtt->offset, ttm->num_pages);
1220         if (r)
1221                 DRM_ERROR("failed to unbind %lu pages at 0x%08llX\n",
1222                           gtt->ttm.ttm.num_pages, gtt->offset);
1223         return r;
1224 }
1225
1226 static void amdgpu_ttm_backend_destroy(struct ttm_tt *ttm)
1227 {
1228         struct amdgpu_ttm_tt *gtt = (void *)ttm;
1229
1230         if (gtt->usertask)
1231                 put_task_struct(gtt->usertask);
1232
1233         ttm_dma_tt_fini(&gtt->ttm);
1234         kfree(gtt);
1235 }
1236
1237 static struct ttm_backend_func amdgpu_backend_func = {
1238         .bind = &amdgpu_ttm_backend_bind,
1239         .unbind = &amdgpu_ttm_backend_unbind,
1240         .destroy = &amdgpu_ttm_backend_destroy,
1241 };
1242
1243 /**
1244  * amdgpu_ttm_tt_create - Create a ttm_tt object for a given BO
1245  *
1246  * @bo: The buffer object to create a GTT ttm_tt object around
1247  *
1248  * Called by ttm_tt_create().
1249  */
1250 static struct ttm_tt *amdgpu_ttm_tt_create(struct ttm_buffer_object *bo,
1251                                            uint32_t page_flags)
1252 {
1253         struct amdgpu_ttm_tt *gtt;
1254
1255         gtt = kzalloc(sizeof(struct amdgpu_ttm_tt), GFP_KERNEL);
1256         if (gtt == NULL) {
1257                 return NULL;
1258         }
1259         gtt->ttm.ttm.func = &amdgpu_backend_func;
1260         gtt->gobj = &bo->base;
1261
1262         /* allocate space for the uninitialized page entries */
1263         if (ttm_sg_tt_init(&gtt->ttm, bo, page_flags)) {
1264                 kfree(gtt);
1265                 return NULL;
1266         }
1267         return &gtt->ttm.ttm;
1268 }
1269
1270 /**
1271  * amdgpu_ttm_tt_populate - Map GTT pages visible to the device
1272  *
1273  * Map the pages of a ttm_tt object to an address space visible
1274  * to the underlying device.
1275  */
1276 static int amdgpu_ttm_tt_populate(struct ttm_tt *ttm,
1277                         struct ttm_operation_ctx *ctx)
1278 {
1279         struct amdgpu_device *adev = amdgpu_ttm_adev(ttm->bdev);
1280         struct amdgpu_ttm_tt *gtt = (void *)ttm;
1281
1282         /* user pages are bound by amdgpu_ttm_tt_pin_userptr() */
1283         if (gtt && gtt->userptr) {
1284                 ttm->sg = kzalloc(sizeof(struct sg_table), GFP_KERNEL);
1285                 if (!ttm->sg)
1286                         return -ENOMEM;
1287
1288                 ttm->page_flags |= TTM_PAGE_FLAG_SG;
1289                 ttm->state = tt_unbound;
1290                 return 0;
1291         }
1292
1293         if (ttm->page_flags & TTM_PAGE_FLAG_SG) {
1294                 if (!ttm->sg) {
1295                         struct dma_buf_attachment *attach;
1296                         struct sg_table *sgt;
1297
1298                         attach = gtt->gobj->import_attach;
1299                         sgt = dma_buf_map_attachment(attach, DMA_BIDIRECTIONAL);
1300                         if (IS_ERR(sgt))
1301                                 return PTR_ERR(sgt);
1302
1303                         ttm->sg = sgt;
1304                 }
1305
1306                 drm_prime_sg_to_page_addr_arrays(ttm->sg, ttm->pages,
1307                                                  gtt->ttm.dma_address,
1308                                                  ttm->num_pages);
1309                 ttm->state = tt_unbound;
1310                 return 0;
1311         }
1312
1313 #ifdef CONFIG_SWIOTLB
1314         if (adev->need_swiotlb && swiotlb_nr_tbl()) {
1315                 return ttm_dma_populate(&gtt->ttm, adev->dev, ctx);
1316         }
1317 #endif
1318
1319         /* fall back to generic helper to populate the page array
1320          * and map them to the device */
1321         return ttm_populate_and_map_pages(adev->dev, &gtt->ttm, ctx);
1322 }
1323
1324 /**
1325  * amdgpu_ttm_tt_unpopulate - unmap GTT pages and unpopulate page arrays
1326  *
1327  * Unmaps pages of a ttm_tt object from the device address space and
1328  * unpopulates the page array backing it.
1329  */
1330 static void amdgpu_ttm_tt_unpopulate(struct ttm_tt *ttm)
1331 {
1332         struct amdgpu_ttm_tt *gtt = (void *)ttm;
1333         struct amdgpu_device *adev;
1334
1335         if (gtt && gtt->userptr) {
1336                 amdgpu_ttm_tt_set_user_pages(ttm, NULL);
1337                 kfree(ttm->sg);
1338                 ttm->page_flags &= ~TTM_PAGE_FLAG_SG;
1339                 return;
1340         }
1341
1342         if (ttm->sg && gtt->gobj->import_attach) {
1343                 struct dma_buf_attachment *attach;
1344
1345                 attach = gtt->gobj->import_attach;
1346                 dma_buf_unmap_attachment(attach, ttm->sg, DMA_BIDIRECTIONAL);
1347                 ttm->sg = NULL;
1348                 return;
1349         }
1350
1351         if (ttm->page_flags & TTM_PAGE_FLAG_SG)
1352                 return;
1353
1354         adev = amdgpu_ttm_adev(ttm->bdev);
1355
1356 #ifdef CONFIG_SWIOTLB
1357         if (adev->need_swiotlb && swiotlb_nr_tbl()) {
1358                 ttm_dma_unpopulate(&gtt->ttm, adev->dev);
1359                 return;
1360         }
1361 #endif
1362
1363         /* fall back to generic helper to unmap and unpopulate array */
1364         ttm_unmap_and_unpopulate_pages(adev->dev, &gtt->ttm);
1365 }
1366
1367 /**
1368  * amdgpu_ttm_tt_set_userptr - Initialize userptr GTT ttm_tt for the current
1369  * task
1370  *
1371  * @ttm: The ttm_tt object to bind this userptr object to
1372  * @addr:  The address in the current tasks VM space to use
1373  * @flags: Requirements of userptr object.
1374  *
1375  * Called by amdgpu_gem_userptr_ioctl() to bind userptr pages
1376  * to current task
1377  */
1378 int amdgpu_ttm_tt_set_userptr(struct ttm_tt *ttm, uint64_t addr,
1379                               uint32_t flags)
1380 {
1381         struct amdgpu_ttm_tt *gtt = (void *)ttm;
1382
1383         if (gtt == NULL)
1384                 return -EINVAL;
1385
1386         gtt->userptr = addr;
1387         gtt->userflags = flags;
1388
1389         if (gtt->usertask)
1390                 put_task_struct(gtt->usertask);
1391         gtt->usertask = current->group_leader;
1392         get_task_struct(gtt->usertask);
1393
1394         return 0;
1395 }
1396
1397 /**
1398  * amdgpu_ttm_tt_get_usermm - Return memory manager for ttm_tt object
1399  */
1400 struct mm_struct *amdgpu_ttm_tt_get_usermm(struct ttm_tt *ttm)
1401 {
1402         struct amdgpu_ttm_tt *gtt = (void *)ttm;
1403
1404         if (gtt == NULL)
1405                 return NULL;
1406
1407         if (gtt->usertask == NULL)
1408                 return NULL;
1409
1410         return gtt->usertask->mm;
1411 }
1412
1413 /**
1414  * amdgpu_ttm_tt_affect_userptr - Determine if a ttm_tt object lays inside an
1415  * address range for the current task.
1416  *
1417  */
1418 bool amdgpu_ttm_tt_affect_userptr(struct ttm_tt *ttm, unsigned long start,
1419                                   unsigned long end)
1420 {
1421         struct amdgpu_ttm_tt *gtt = (void *)ttm;
1422         unsigned long size;
1423
1424         if (gtt == NULL || !gtt->userptr)
1425                 return false;
1426
1427         /* Return false if no part of the ttm_tt object lies within
1428          * the range
1429          */
1430         size = (unsigned long)gtt->ttm.ttm.num_pages * PAGE_SIZE;
1431         if (gtt->userptr > end || gtt->userptr + size <= start)
1432                 return false;
1433
1434         return true;
1435 }
1436
1437 /**
1438  * amdgpu_ttm_tt_is_userptr - Have the pages backing by userptr?
1439  */
1440 bool amdgpu_ttm_tt_is_userptr(struct ttm_tt *ttm)
1441 {
1442         struct amdgpu_ttm_tt *gtt = (void *)ttm;
1443
1444         if (gtt == NULL || !gtt->userptr)
1445                 return false;
1446
1447         return true;
1448 }
1449
1450 /**
1451  * amdgpu_ttm_tt_is_readonly - Is the ttm_tt object read only?
1452  */
1453 bool amdgpu_ttm_tt_is_readonly(struct ttm_tt *ttm)
1454 {
1455         struct amdgpu_ttm_tt *gtt = (void *)ttm;
1456
1457         if (gtt == NULL)
1458                 return false;
1459
1460         return !!(gtt->userflags & AMDGPU_GEM_USERPTR_READONLY);
1461 }
1462
1463 /**
1464  * amdgpu_ttm_tt_pde_flags - Compute PDE flags for ttm_tt object
1465  *
1466  * @ttm: The ttm_tt object to compute the flags for
1467  * @mem: The memory registry backing this ttm_tt object
1468  *
1469  * Figure out the flags to use for a VM PDE (Page Directory Entry).
1470  */
1471 uint64_t amdgpu_ttm_tt_pde_flags(struct ttm_tt *ttm, struct ttm_mem_reg *mem)
1472 {
1473         uint64_t flags = 0;
1474
1475         if (mem && mem->mem_type != TTM_PL_SYSTEM)
1476                 flags |= AMDGPU_PTE_VALID;
1477
1478         if (mem && mem->mem_type == TTM_PL_TT) {
1479                 flags |= AMDGPU_PTE_SYSTEM;
1480
1481                 if (ttm->caching_state == tt_cached)
1482                         flags |= AMDGPU_PTE_SNOOPED;
1483         }
1484
1485         return flags;
1486 }
1487
1488 /**
1489  * amdgpu_ttm_tt_pte_flags - Compute PTE flags for ttm_tt object
1490  *
1491  * @ttm: The ttm_tt object to compute the flags for
1492  * @mem: The memory registry backing this ttm_tt object
1493
1494  * Figure out the flags to use for a VM PTE (Page Table Entry).
1495  */
1496 uint64_t amdgpu_ttm_tt_pte_flags(struct amdgpu_device *adev, struct ttm_tt *ttm,
1497                                  struct ttm_mem_reg *mem)
1498 {
1499         uint64_t flags = amdgpu_ttm_tt_pde_flags(ttm, mem);
1500
1501         flags |= adev->gart.gart_pte_flags;
1502         flags |= AMDGPU_PTE_READABLE;
1503
1504         if (!amdgpu_ttm_tt_is_readonly(ttm))
1505                 flags |= AMDGPU_PTE_WRITEABLE;
1506
1507         return flags;
1508 }
1509
1510 /**
1511  * amdgpu_ttm_bo_eviction_valuable - Check to see if we can evict a buffer
1512  * object.
1513  *
1514  * Return true if eviction is sensible. Called by ttm_mem_evict_first() on
1515  * behalf of ttm_bo_mem_force_space() which tries to evict buffer objects until
1516  * it can find space for a new object and by ttm_bo_force_list_clean() which is
1517  * used to clean out a memory space.
1518  */
1519 static bool amdgpu_ttm_bo_eviction_valuable(struct ttm_buffer_object *bo,
1520                                             const struct ttm_place *place)
1521 {
1522         unsigned long num_pages = bo->mem.num_pages;
1523         struct drm_mm_node *node = bo->mem.mm_node;
1524         struct dma_resv_list *flist;
1525         struct dma_fence *f;
1526         int i;
1527
1528         if (bo->type == ttm_bo_type_kernel &&
1529             !amdgpu_vm_evictable(ttm_to_amdgpu_bo(bo)))
1530                 return false;
1531
1532         /* If bo is a KFD BO, check if the bo belongs to the current process.
1533          * If true, then return false as any KFD process needs all its BOs to
1534          * be resident to run successfully
1535          */
1536         flist = dma_resv_get_list(bo->base.resv);
1537         if (flist) {
1538                 for (i = 0; i < flist->shared_count; ++i) {
1539                         f = rcu_dereference_protected(flist->shared[i],
1540                                 dma_resv_held(bo->base.resv));
1541                         if (amdkfd_fence_check_mm(f, current->mm))
1542                                 return false;
1543                 }
1544         }
1545
1546         switch (bo->mem.mem_type) {
1547         case TTM_PL_TT:
1548                 return true;
1549
1550         case TTM_PL_VRAM:
1551                 /* Check each drm MM node individually */
1552                 while (num_pages) {
1553                         if (place->fpfn < (node->start + node->size) &&
1554                             !(place->lpfn && place->lpfn <= node->start))
1555                                 return true;
1556
1557                         num_pages -= node->size;
1558                         ++node;
1559                 }
1560                 return false;
1561
1562         default:
1563                 break;
1564         }
1565
1566         return ttm_bo_eviction_valuable(bo, place);
1567 }
1568
1569 /**
1570  * amdgpu_ttm_access_memory - Read or Write memory that backs a buffer object.
1571  *
1572  * @bo:  The buffer object to read/write
1573  * @offset:  Offset into buffer object
1574  * @buf:  Secondary buffer to write/read from
1575  * @len: Length in bytes of access
1576  * @write:  true if writing
1577  *
1578  * This is used to access VRAM that backs a buffer object via MMIO
1579  * access for debugging purposes.
1580  */
1581 static int amdgpu_ttm_access_memory(struct ttm_buffer_object *bo,
1582                                     unsigned long offset,
1583                                     void *buf, int len, int write)
1584 {
1585         struct amdgpu_bo *abo = ttm_to_amdgpu_bo(bo);
1586         struct amdgpu_device *adev = amdgpu_ttm_adev(abo->tbo.bdev);
1587         struct drm_mm_node *nodes;
1588         uint32_t value = 0;
1589         int ret = 0;
1590         uint64_t pos;
1591         unsigned long flags;
1592
1593         if (bo->mem.mem_type != TTM_PL_VRAM)
1594                 return -EIO;
1595
1596         nodes = amdgpu_find_mm_node(&abo->tbo.mem, &offset);
1597         pos = (nodes->start << PAGE_SHIFT) + offset;
1598
1599         while (len && pos < adev->gmc.mc_vram_size) {
1600                 uint64_t aligned_pos = pos & ~(uint64_t)3;
1601                 uint64_t bytes = 4 - (pos & 3);
1602                 uint32_t shift = (pos & 3) * 8;
1603                 uint32_t mask = 0xffffffff << shift;
1604
1605                 if (len < bytes) {
1606                         mask &= 0xffffffff >> (bytes - len) * 8;
1607                         bytes = len;
1608                 }
1609
1610                 if (mask != 0xffffffff) {
1611                         spin_lock_irqsave(&adev->mmio_idx_lock, flags);
1612                         WREG32_NO_KIQ(mmMM_INDEX, ((uint32_t)aligned_pos) | 0x80000000);
1613                         WREG32_NO_KIQ(mmMM_INDEX_HI, aligned_pos >> 31);
1614                         if (!write || mask != 0xffffffff)
1615                                 value = RREG32_NO_KIQ(mmMM_DATA);
1616                         if (write) {
1617                                 value &= ~mask;
1618                                 value |= (*(uint32_t *)buf << shift) & mask;
1619                                 WREG32_NO_KIQ(mmMM_DATA, value);
1620                         }
1621                         spin_unlock_irqrestore(&adev->mmio_idx_lock, flags);
1622                         if (!write) {
1623                                 value = (value & mask) >> shift;
1624                                 memcpy(buf, &value, bytes);
1625                         }
1626                 } else {
1627                         bytes = (nodes->start + nodes->size) << PAGE_SHIFT;
1628                         bytes = min(bytes - pos, (uint64_t)len & ~0x3ull);
1629
1630                         amdgpu_device_vram_access(adev, pos, (uint32_t *)buf,
1631                                                   bytes, write);
1632                 }
1633
1634                 ret += bytes;
1635                 buf = (uint8_t *)buf + bytes;
1636                 pos += bytes;
1637                 len -= bytes;
1638                 if (pos >= (nodes->start + nodes->size) << PAGE_SHIFT) {
1639                         ++nodes;
1640                         pos = (nodes->start << PAGE_SHIFT);
1641                 }
1642         }
1643
1644         return ret;
1645 }
1646
1647 static struct ttm_bo_driver amdgpu_bo_driver = {
1648         .ttm_tt_create = &amdgpu_ttm_tt_create,
1649         .ttm_tt_populate = &amdgpu_ttm_tt_populate,
1650         .ttm_tt_unpopulate = &amdgpu_ttm_tt_unpopulate,
1651         .invalidate_caches = &amdgpu_invalidate_caches,
1652         .init_mem_type = &amdgpu_init_mem_type,
1653         .eviction_valuable = amdgpu_ttm_bo_eviction_valuable,
1654         .evict_flags = &amdgpu_evict_flags,
1655         .move = &amdgpu_bo_move,
1656         .verify_access = &amdgpu_verify_access,
1657         .move_notify = &amdgpu_bo_move_notify,
1658         .release_notify = &amdgpu_bo_release_notify,
1659         .fault_reserve_notify = &amdgpu_bo_fault_reserve_notify,
1660         .io_mem_reserve = &amdgpu_ttm_io_mem_reserve,
1661         .io_mem_free = &amdgpu_ttm_io_mem_free,
1662         .io_mem_pfn = amdgpu_ttm_io_mem_pfn,
1663         .access_memory = &amdgpu_ttm_access_memory,
1664         .del_from_lru_notify = &amdgpu_vm_del_from_lru_notify
1665 };
1666
1667 /*
1668  * Firmware Reservation functions
1669  */
1670 /**
1671  * amdgpu_ttm_fw_reserve_vram_fini - free fw reserved vram
1672  *
1673  * @adev: amdgpu_device pointer
1674  *
1675  * free fw reserved vram if it has been reserved.
1676  */
1677 static void amdgpu_ttm_fw_reserve_vram_fini(struct amdgpu_device *adev)
1678 {
1679         amdgpu_bo_free_kernel(&adev->fw_vram_usage.reserved_bo,
1680                 NULL, &adev->fw_vram_usage.va);
1681 }
1682
1683 /**
1684  * amdgpu_ttm_fw_reserve_vram_init - create bo vram reservation from fw
1685  *
1686  * @adev: amdgpu_device pointer
1687  *
1688  * create bo vram reservation from fw.
1689  */
1690 static int amdgpu_ttm_fw_reserve_vram_init(struct amdgpu_device *adev)
1691 {
1692         uint64_t vram_size = adev->gmc.visible_vram_size;
1693
1694         adev->fw_vram_usage.va = NULL;
1695         adev->fw_vram_usage.reserved_bo = NULL;
1696
1697         if (adev->fw_vram_usage.size == 0 ||
1698             adev->fw_vram_usage.size > vram_size)
1699                 return 0;
1700
1701         return amdgpu_bo_create_kernel_at(adev,
1702                                           adev->fw_vram_usage.start_offset,
1703                                           adev->fw_vram_usage.size,
1704                                           AMDGPU_GEM_DOMAIN_VRAM,
1705                                           &adev->fw_vram_usage.reserved_bo,
1706                                           &adev->fw_vram_usage.va);
1707 }
1708
1709 /*
1710  * Memoy training reservation functions
1711  */
1712
1713 /**
1714  * amdgpu_ttm_training_reserve_vram_fini - free memory training reserved vram
1715  *
1716  * @adev: amdgpu_device pointer
1717  *
1718  * free memory training reserved vram if it has been reserved.
1719  */
1720 static int amdgpu_ttm_training_reserve_vram_fini(struct amdgpu_device *adev)
1721 {
1722         struct psp_memory_training_context *ctx = &adev->psp.mem_train_ctx;
1723
1724         ctx->init = PSP_MEM_TRAIN_NOT_SUPPORT;
1725         amdgpu_bo_free_kernel(&ctx->c2p_bo, NULL, NULL);
1726         ctx->c2p_bo = NULL;
1727
1728         return 0;
1729 }
1730
1731 static u64 amdgpu_ttm_training_get_c2p_offset(u64 vram_size)
1732 {
1733        if ((vram_size & (SZ_1M - 1)) < (SZ_4K + 1) )
1734                vram_size -= SZ_1M;
1735
1736        return ALIGN(vram_size, SZ_1M);
1737 }
1738
1739 /**
1740  * amdgpu_ttm_training_reserve_vram_init - create bo vram reservation from memory training
1741  *
1742  * @adev: amdgpu_device pointer
1743  *
1744  * create bo vram reservation from memory training.
1745  */
1746 static int amdgpu_ttm_training_reserve_vram_init(struct amdgpu_device *adev)
1747 {
1748         int ret;
1749         struct psp_memory_training_context *ctx = &adev->psp.mem_train_ctx;
1750
1751         memset(ctx, 0, sizeof(*ctx));
1752         if (!adev->fw_vram_usage.mem_train_support) {
1753                 DRM_DEBUG("memory training does not support!\n");
1754                 return 0;
1755         }
1756
1757         ctx->c2p_train_data_offset = amdgpu_ttm_training_get_c2p_offset(adev->gmc.mc_vram_size);
1758         ctx->p2c_train_data_offset = (adev->gmc.mc_vram_size - GDDR6_MEM_TRAINING_OFFSET);
1759         ctx->train_data_size = GDDR6_MEM_TRAINING_DATA_SIZE_IN_BYTES;
1760
1761         DRM_DEBUG("train_data_size:%llx,p2c_train_data_offset:%llx,c2p_train_data_offset:%llx.\n",
1762                   ctx->train_data_size,
1763                   ctx->p2c_train_data_offset,
1764                   ctx->c2p_train_data_offset);
1765
1766         ret = amdgpu_bo_create_kernel_at(adev,
1767                                          ctx->c2p_train_data_offset,
1768                                          ctx->train_data_size,
1769                                          AMDGPU_GEM_DOMAIN_VRAM,
1770                                          &ctx->c2p_bo,
1771                                          NULL);
1772         if (ret) {
1773                 DRM_ERROR("alloc c2p_bo failed(%d)!\n", ret);
1774                 amdgpu_ttm_training_reserve_vram_fini(adev);
1775                 return ret;
1776         }
1777
1778         ctx->init = PSP_MEM_TRAIN_RESERVE_SUCCESS;
1779         return 0;
1780 }
1781
1782 /**
1783  * amdgpu_ttm_init - Init the memory management (ttm) as well as various
1784  * gtt/vram related fields.
1785  *
1786  * This initializes all of the memory space pools that the TTM layer
1787  * will need such as the GTT space (system memory mapped to the device),
1788  * VRAM (on-board memory), and on-chip memories (GDS, GWS, OA) which
1789  * can be mapped per VMID.
1790  */
1791 int amdgpu_ttm_init(struct amdgpu_device *adev)
1792 {
1793         uint64_t gtt_size;
1794         int r;
1795         u64 vis_vram_limit;
1796         void *stolen_vga_buf;
1797
1798         mutex_init(&adev->mman.gtt_window_lock);
1799
1800         /* No others user of address space so set it to 0 */
1801         r = ttm_bo_device_init(&adev->mman.bdev,
1802                                &amdgpu_bo_driver,
1803                                adev->ddev->anon_inode->i_mapping,
1804                                adev->ddev->vma_offset_manager,
1805                                dma_addressing_limited(adev->dev));
1806         if (r) {
1807                 DRM_ERROR("failed initializing buffer object driver(%d).\n", r);
1808                 return r;
1809         }
1810         adev->mman.initialized = true;
1811
1812         /* We opt to avoid OOM on system pages allocations */
1813         adev->mman.bdev.no_retry = true;
1814
1815         /* Initialize VRAM pool with all of VRAM divided into pages */
1816         r = ttm_bo_init_mm(&adev->mman.bdev, TTM_PL_VRAM,
1817                                 adev->gmc.real_vram_size >> PAGE_SHIFT);
1818         if (r) {
1819                 DRM_ERROR("Failed initializing VRAM heap.\n");
1820                 return r;
1821         }
1822
1823         /* Reduce size of CPU-visible VRAM if requested */
1824         vis_vram_limit = (u64)amdgpu_vis_vram_limit * 1024 * 1024;
1825         if (amdgpu_vis_vram_limit > 0 &&
1826             vis_vram_limit <= adev->gmc.visible_vram_size)
1827                 adev->gmc.visible_vram_size = vis_vram_limit;
1828
1829         /* Change the size here instead of the init above so only lpfn is affected */
1830         amdgpu_ttm_set_buffer_funcs_status(adev, false);
1831 #ifdef CONFIG_64BIT
1832         adev->mman.aper_base_kaddr = ioremap_wc(adev->gmc.aper_base,
1833                                                 adev->gmc.visible_vram_size);
1834 #endif
1835
1836         /*
1837          *The reserved vram for firmware must be pinned to the specified
1838          *place on the VRAM, so reserve it early.
1839          */
1840         r = amdgpu_ttm_fw_reserve_vram_init(adev);
1841         if (r) {
1842                 return r;
1843         }
1844
1845         /*
1846          *The reserved vram for memory training must be pinned to the specified
1847          *place on the VRAM, so reserve it early.
1848          */
1849         r = amdgpu_ttm_training_reserve_vram_init(adev);
1850         if (r)
1851                 return r;
1852
1853         /* allocate memory as required for VGA
1854          * This is used for VGA emulation and pre-OS scanout buffers to
1855          * avoid display artifacts while transitioning between pre-OS
1856          * and driver.  */
1857         r = amdgpu_bo_create_kernel(adev, adev->gmc.stolen_size, PAGE_SIZE,
1858                                     AMDGPU_GEM_DOMAIN_VRAM,
1859                                     &adev->stolen_vga_memory,
1860                                     NULL, &stolen_vga_buf);
1861         if (r)
1862                 return r;
1863
1864         /*
1865          * reserve one TMR (64K) memory at the top of VRAM which holds
1866          * IP Discovery data and is protected by PSP.
1867          */
1868         r = amdgpu_bo_create_kernel_at(adev,
1869                                        adev->gmc.real_vram_size - DISCOVERY_TMR_SIZE,
1870                                        DISCOVERY_TMR_SIZE,
1871                                        AMDGPU_GEM_DOMAIN_VRAM,
1872                                        &adev->discovery_memory,
1873                                        NULL);
1874         if (r)
1875                 return r;
1876
1877         DRM_INFO("amdgpu: %uM of VRAM memory ready\n",
1878                  (unsigned) (adev->gmc.real_vram_size / (1024 * 1024)));
1879
1880         /* Compute GTT size, either bsaed on 3/4th the size of RAM size
1881          * or whatever the user passed on module init */
1882         if (amdgpu_gtt_size == -1) {
1883                 struct sysinfo si;
1884
1885                 si_meminfo(&si);
1886                 gtt_size = min(max((AMDGPU_DEFAULT_GTT_SIZE_MB << 20),
1887                                adev->gmc.mc_vram_size),
1888                                ((uint64_t)si.totalram * si.mem_unit * 3/4));
1889         }
1890         else
1891                 gtt_size = (uint64_t)amdgpu_gtt_size << 20;
1892
1893         /* Initialize GTT memory pool */
1894         r = ttm_bo_init_mm(&adev->mman.bdev, TTM_PL_TT, gtt_size >> PAGE_SHIFT);
1895         if (r) {
1896                 DRM_ERROR("Failed initializing GTT heap.\n");
1897                 return r;
1898         }
1899         DRM_INFO("amdgpu: %uM of GTT memory ready.\n",
1900                  (unsigned)(gtt_size / (1024 * 1024)));
1901
1902         /* Initialize various on-chip memory pools */
1903         r = ttm_bo_init_mm(&adev->mman.bdev, AMDGPU_PL_GDS,
1904                            adev->gds.gds_size);
1905         if (r) {
1906                 DRM_ERROR("Failed initializing GDS heap.\n");
1907                 return r;
1908         }
1909
1910         r = ttm_bo_init_mm(&adev->mman.bdev, AMDGPU_PL_GWS,
1911                            adev->gds.gws_size);
1912         if (r) {
1913                 DRM_ERROR("Failed initializing gws heap.\n");
1914                 return r;
1915         }
1916
1917         r = ttm_bo_init_mm(&adev->mman.bdev, AMDGPU_PL_OA,
1918                            adev->gds.oa_size);
1919         if (r) {
1920                 DRM_ERROR("Failed initializing oa heap.\n");
1921                 return r;
1922         }
1923
1924         /* Register debugfs entries for amdgpu_ttm */
1925         r = amdgpu_ttm_debugfs_init(adev);
1926         if (r) {
1927                 DRM_ERROR("Failed to init debugfs\n");
1928                 return r;
1929         }
1930         return 0;
1931 }
1932
1933 /**
1934  * amdgpu_ttm_late_init - Handle any late initialization for amdgpu_ttm
1935  */
1936 void amdgpu_ttm_late_init(struct amdgpu_device *adev)
1937 {
1938         void *stolen_vga_buf;
1939         /* return the VGA stolen memory (if any) back to VRAM */
1940         amdgpu_bo_free_kernel(&adev->stolen_vga_memory, NULL, &stolen_vga_buf);
1941 }
1942
1943 /**
1944  * amdgpu_ttm_fini - De-initialize the TTM memory pools
1945  */
1946 void amdgpu_ttm_fini(struct amdgpu_device *adev)
1947 {
1948         if (!adev->mman.initialized)
1949                 return;
1950
1951         amdgpu_ttm_debugfs_fini(adev);
1952         amdgpu_ttm_training_reserve_vram_fini(adev);
1953         /* return the IP Discovery TMR memory back to VRAM */
1954         amdgpu_bo_free_kernel(&adev->discovery_memory, NULL, NULL);
1955         amdgpu_ttm_fw_reserve_vram_fini(adev);
1956
1957         if (adev->mman.aper_base_kaddr)
1958                 iounmap(adev->mman.aper_base_kaddr);
1959         adev->mman.aper_base_kaddr = NULL;
1960
1961         ttm_bo_clean_mm(&adev->mman.bdev, TTM_PL_VRAM);
1962         ttm_bo_clean_mm(&adev->mman.bdev, TTM_PL_TT);
1963         ttm_bo_clean_mm(&adev->mman.bdev, AMDGPU_PL_GDS);
1964         ttm_bo_clean_mm(&adev->mman.bdev, AMDGPU_PL_GWS);
1965         ttm_bo_clean_mm(&adev->mman.bdev, AMDGPU_PL_OA);
1966         ttm_bo_device_release(&adev->mman.bdev);
1967         adev->mman.initialized = false;
1968         DRM_INFO("amdgpu: ttm finalized\n");
1969 }
1970
1971 /**
1972  * amdgpu_ttm_set_buffer_funcs_status - enable/disable use of buffer functions
1973  *
1974  * @adev: amdgpu_device pointer
1975  * @enable: true when we can use buffer functions.
1976  *
1977  * Enable/disable use of buffer functions during suspend/resume. This should
1978  * only be called at bootup or when userspace isn't running.
1979  */
1980 void amdgpu_ttm_set_buffer_funcs_status(struct amdgpu_device *adev, bool enable)
1981 {
1982         struct ttm_mem_type_manager *man = &adev->mman.bdev.man[TTM_PL_VRAM];
1983         uint64_t size;
1984         int r;
1985
1986         if (!adev->mman.initialized || adev->in_gpu_reset ||
1987             adev->mman.buffer_funcs_enabled == enable)
1988                 return;
1989
1990         if (enable) {
1991                 struct amdgpu_ring *ring;
1992                 struct drm_gpu_scheduler *sched;
1993
1994                 ring = adev->mman.buffer_funcs_ring;
1995                 sched = &ring->sched;
1996                 r = drm_sched_entity_init(&adev->mman.entity,
1997                                           DRM_SCHED_PRIORITY_KERNEL, &sched,
1998                                           1, NULL);
1999                 if (r) {
2000                         DRM_ERROR("Failed setting up TTM BO move entity (%d)\n",
2001                                   r);
2002                         return;
2003                 }
2004         } else {
2005                 drm_sched_entity_destroy(&adev->mman.entity);
2006                 dma_fence_put(man->move);
2007                 man->move = NULL;
2008         }
2009
2010         /* this just adjusts TTM size idea, which sets lpfn to the correct value */
2011         if (enable)
2012                 size = adev->gmc.real_vram_size;
2013         else
2014                 size = adev->gmc.visible_vram_size;
2015         man->size = size >> PAGE_SHIFT;
2016         adev->mman.buffer_funcs_enabled = enable;
2017 }
2018
2019 int amdgpu_mmap(struct file *filp, struct vm_area_struct *vma)
2020 {
2021         struct drm_file *file_priv = filp->private_data;
2022         struct amdgpu_device *adev = file_priv->minor->dev->dev_private;
2023
2024         if (adev == NULL)
2025                 return -EINVAL;
2026
2027         return ttm_bo_mmap(filp, vma, &adev->mman.bdev);
2028 }
2029
2030 static int amdgpu_map_buffer(struct ttm_buffer_object *bo,
2031                              struct ttm_mem_reg *mem, unsigned num_pages,
2032                              uint64_t offset, unsigned window,
2033                              struct amdgpu_ring *ring,
2034                              uint64_t *addr)
2035 {
2036         struct amdgpu_ttm_tt *gtt = (void *)bo->ttm;
2037         struct amdgpu_device *adev = ring->adev;
2038         struct ttm_tt *ttm = bo->ttm;
2039         struct amdgpu_job *job;
2040         unsigned num_dw, num_bytes;
2041         dma_addr_t *dma_address;
2042         struct dma_fence *fence;
2043         uint64_t src_addr, dst_addr;
2044         uint64_t flags;
2045         int r;
2046
2047         BUG_ON(adev->mman.buffer_funcs->copy_max_bytes <
2048                AMDGPU_GTT_MAX_TRANSFER_SIZE * 8);
2049
2050         *addr = adev->gmc.gart_start;
2051         *addr += (u64)window * AMDGPU_GTT_MAX_TRANSFER_SIZE *
2052                 AMDGPU_GPU_PAGE_SIZE;
2053
2054         num_dw = ALIGN(adev->mman.buffer_funcs->copy_num_dw, 8);
2055         num_bytes = num_pages * 8;
2056
2057         r = amdgpu_job_alloc_with_ib(adev, num_dw * 4 + num_bytes, &job);
2058         if (r)
2059                 return r;
2060
2061         src_addr = num_dw * 4;
2062         src_addr += job->ibs[0].gpu_addr;
2063
2064         dst_addr = amdgpu_bo_gpu_offset(adev->gart.bo);
2065         dst_addr += window * AMDGPU_GTT_MAX_TRANSFER_SIZE * 8;
2066         amdgpu_emit_copy_buffer(adev, &job->ibs[0], src_addr,
2067                                 dst_addr, num_bytes);
2068
2069         amdgpu_ring_pad_ib(ring, &job->ibs[0]);
2070         WARN_ON(job->ibs[0].length_dw > num_dw);
2071
2072         dma_address = &gtt->ttm.dma_address[offset >> PAGE_SHIFT];
2073         flags = amdgpu_ttm_tt_pte_flags(adev, ttm, mem);
2074         r = amdgpu_gart_map(adev, 0, num_pages, dma_address, flags,
2075                             &job->ibs[0].ptr[num_dw]);
2076         if (r)
2077                 goto error_free;
2078
2079         r = amdgpu_job_submit(job, &adev->mman.entity,
2080                               AMDGPU_FENCE_OWNER_UNDEFINED, &fence);
2081         if (r)
2082                 goto error_free;
2083
2084         dma_fence_put(fence);
2085
2086         return r;
2087
2088 error_free:
2089         amdgpu_job_free(job);
2090         return r;
2091 }
2092
2093 int amdgpu_copy_buffer(struct amdgpu_ring *ring, uint64_t src_offset,
2094                        uint64_t dst_offset, uint32_t byte_count,
2095                        struct dma_resv *resv,
2096                        struct dma_fence **fence, bool direct_submit,
2097                        bool vm_needs_flush)
2098 {
2099         struct amdgpu_device *adev = ring->adev;
2100         struct amdgpu_job *job;
2101
2102         uint32_t max_bytes;
2103         unsigned num_loops, num_dw;
2104         unsigned i;
2105         int r;
2106
2107         if (direct_submit && !ring->sched.ready) {
2108                 DRM_ERROR("Trying to move memory with ring turned off.\n");
2109                 return -EINVAL;
2110         }
2111
2112         max_bytes = adev->mman.buffer_funcs->copy_max_bytes;
2113         num_loops = DIV_ROUND_UP(byte_count, max_bytes);
2114         num_dw = ALIGN(num_loops * adev->mman.buffer_funcs->copy_num_dw, 8);
2115
2116         r = amdgpu_job_alloc_with_ib(adev, num_dw * 4, &job);
2117         if (r)
2118                 return r;
2119
2120         if (vm_needs_flush) {
2121                 job->vm_pd_addr = amdgpu_gmc_pd_addr(adev->gart.bo);
2122                 job->vm_needs_flush = true;
2123         }
2124         if (resv) {
2125                 r = amdgpu_sync_resv(adev, &job->sync, resv,
2126                                      AMDGPU_SYNC_ALWAYS,
2127                                      AMDGPU_FENCE_OWNER_UNDEFINED);
2128                 if (r) {
2129                         DRM_ERROR("sync failed (%d).\n", r);
2130                         goto error_free;
2131                 }
2132         }
2133
2134         for (i = 0; i < num_loops; i++) {
2135                 uint32_t cur_size_in_bytes = min(byte_count, max_bytes);
2136
2137                 amdgpu_emit_copy_buffer(adev, &job->ibs[0], src_offset,
2138                                         dst_offset, cur_size_in_bytes);
2139
2140                 src_offset += cur_size_in_bytes;
2141                 dst_offset += cur_size_in_bytes;
2142                 byte_count -= cur_size_in_bytes;
2143         }
2144
2145         amdgpu_ring_pad_ib(ring, &job->ibs[0]);
2146         WARN_ON(job->ibs[0].length_dw > num_dw);
2147         if (direct_submit)
2148                 r = amdgpu_job_submit_direct(job, ring, fence);
2149         else
2150                 r = amdgpu_job_submit(job, &adev->mman.entity,
2151                                       AMDGPU_FENCE_OWNER_UNDEFINED, fence);
2152         if (r)
2153                 goto error_free;
2154
2155         return r;
2156
2157 error_free:
2158         amdgpu_job_free(job);
2159         DRM_ERROR("Error scheduling IBs (%d)\n", r);
2160         return r;
2161 }
2162
2163 int amdgpu_fill_buffer(struct amdgpu_bo *bo,
2164                        uint32_t src_data,
2165                        struct dma_resv *resv,
2166                        struct dma_fence **fence)
2167 {
2168         struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
2169         uint32_t max_bytes = adev->mman.buffer_funcs->fill_max_bytes;
2170         struct amdgpu_ring *ring = adev->mman.buffer_funcs_ring;
2171
2172         struct drm_mm_node *mm_node;
2173         unsigned long num_pages;
2174         unsigned int num_loops, num_dw;
2175
2176         struct amdgpu_job *job;
2177         int r;
2178
2179         if (!adev->mman.buffer_funcs_enabled) {
2180                 DRM_ERROR("Trying to clear memory with ring turned off.\n");
2181                 return -EINVAL;
2182         }
2183
2184         if (bo->tbo.mem.mem_type == TTM_PL_TT) {
2185                 r = amdgpu_ttm_alloc_gart(&bo->tbo);
2186                 if (r)
2187                         return r;
2188         }
2189
2190         num_pages = bo->tbo.num_pages;
2191         mm_node = bo->tbo.mem.mm_node;
2192         num_loops = 0;
2193         while (num_pages) {
2194                 uint64_t byte_count = mm_node->size << PAGE_SHIFT;
2195
2196                 num_loops += DIV_ROUND_UP_ULL(byte_count, max_bytes);
2197                 num_pages -= mm_node->size;
2198                 ++mm_node;
2199         }
2200         num_dw = num_loops * adev->mman.buffer_funcs->fill_num_dw;
2201
2202         /* for IB padding */
2203         num_dw += 64;
2204
2205         r = amdgpu_job_alloc_with_ib(adev, num_dw * 4, &job);
2206         if (r)
2207                 return r;
2208
2209         if (resv) {
2210                 r = amdgpu_sync_resv(adev, &job->sync, resv,
2211                                      AMDGPU_SYNC_ALWAYS,
2212                                      AMDGPU_FENCE_OWNER_UNDEFINED);
2213                 if (r) {
2214                         DRM_ERROR("sync failed (%d).\n", r);
2215                         goto error_free;
2216                 }
2217         }
2218
2219         num_pages = bo->tbo.num_pages;
2220         mm_node = bo->tbo.mem.mm_node;
2221
2222         while (num_pages) {
2223                 uint64_t byte_count = mm_node->size << PAGE_SHIFT;
2224                 uint64_t dst_addr;
2225
2226                 dst_addr = amdgpu_mm_node_addr(&bo->tbo, mm_node, &bo->tbo.mem);
2227                 while (byte_count) {
2228                         uint32_t cur_size_in_bytes = min_t(uint64_t, byte_count,
2229                                                            max_bytes);
2230
2231                         amdgpu_emit_fill_buffer(adev, &job->ibs[0], src_data,
2232                                                 dst_addr, cur_size_in_bytes);
2233
2234                         dst_addr += cur_size_in_bytes;
2235                         byte_count -= cur_size_in_bytes;
2236                 }
2237
2238                 num_pages -= mm_node->size;
2239                 ++mm_node;
2240         }
2241
2242         amdgpu_ring_pad_ib(ring, &job->ibs[0]);
2243         WARN_ON(job->ibs[0].length_dw > num_dw);
2244         r = amdgpu_job_submit(job, &adev->mman.entity,
2245                               AMDGPU_FENCE_OWNER_UNDEFINED, fence);
2246         if (r)
2247                 goto error_free;
2248
2249         return 0;
2250
2251 error_free:
2252         amdgpu_job_free(job);
2253         return r;
2254 }
2255
2256 #if defined(CONFIG_DEBUG_FS)
2257
2258 static int amdgpu_mm_dump_table(struct seq_file *m, void *data)
2259 {
2260         struct drm_info_node *node = (struct drm_info_node *)m->private;
2261         unsigned ttm_pl = (uintptr_t)node->info_ent->data;
2262         struct drm_device *dev = node->minor->dev;
2263         struct amdgpu_device *adev = dev->dev_private;
2264         struct ttm_mem_type_manager *man = &adev->mman.bdev.man[ttm_pl];
2265         struct drm_printer p = drm_seq_file_printer(m);
2266
2267         man->func->debug(man, &p);
2268         return 0;
2269 }
2270
2271 static const struct drm_info_list amdgpu_ttm_debugfs_list[] = {
2272         {"amdgpu_vram_mm", amdgpu_mm_dump_table, 0, (void *)TTM_PL_VRAM},
2273         {"amdgpu_gtt_mm", amdgpu_mm_dump_table, 0, (void *)TTM_PL_TT},
2274         {"amdgpu_gds_mm", amdgpu_mm_dump_table, 0, (void *)AMDGPU_PL_GDS},
2275         {"amdgpu_gws_mm", amdgpu_mm_dump_table, 0, (void *)AMDGPU_PL_GWS},
2276         {"amdgpu_oa_mm", amdgpu_mm_dump_table, 0, (void *)AMDGPU_PL_OA},
2277         {"ttm_page_pool", ttm_page_alloc_debugfs, 0, NULL},
2278 #ifdef CONFIG_SWIOTLB
2279         {"ttm_dma_page_pool", ttm_dma_page_alloc_debugfs, 0, NULL}
2280 #endif
2281 };
2282
2283 /**
2284  * amdgpu_ttm_vram_read - Linear read access to VRAM
2285  *
2286  * Accesses VRAM via MMIO for debugging purposes.
2287  */
2288 static ssize_t amdgpu_ttm_vram_read(struct file *f, char __user *buf,
2289                                     size_t size, loff_t *pos)
2290 {
2291         struct amdgpu_device *adev = file_inode(f)->i_private;
2292         ssize_t result = 0;
2293
2294         if (size & 0x3 || *pos & 0x3)
2295                 return -EINVAL;
2296
2297         if (*pos >= adev->gmc.mc_vram_size)
2298                 return -ENXIO;
2299
2300         size = min(size, (size_t)(adev->gmc.mc_vram_size - *pos));
2301         while (size) {
2302                 size_t bytes = min(size, AMDGPU_TTM_VRAM_MAX_DW_READ * 4);
2303                 uint32_t value[AMDGPU_TTM_VRAM_MAX_DW_READ];
2304
2305                 amdgpu_device_vram_access(adev, *pos, value, bytes, false);
2306                 if (copy_to_user(buf, value, bytes))
2307                         return -EFAULT;
2308
2309                 result += bytes;
2310                 buf += bytes;
2311                 *pos += bytes;
2312                 size -= bytes;
2313         }
2314
2315         return result;
2316 }
2317
2318 /**
2319  * amdgpu_ttm_vram_write - Linear write access to VRAM
2320  *
2321  * Accesses VRAM via MMIO for debugging purposes.
2322  */
2323 static ssize_t amdgpu_ttm_vram_write(struct file *f, const char __user *buf,
2324                                     size_t size, loff_t *pos)
2325 {
2326         struct amdgpu_device *adev = file_inode(f)->i_private;
2327         ssize_t result = 0;
2328         int r;
2329
2330         if (size & 0x3 || *pos & 0x3)
2331                 return -EINVAL;
2332
2333         if (*pos >= adev->gmc.mc_vram_size)
2334                 return -ENXIO;
2335
2336         while (size) {
2337                 unsigned long flags;
2338                 uint32_t value;
2339
2340                 if (*pos >= adev->gmc.mc_vram_size)
2341                         return result;
2342
2343                 r = get_user(value, (uint32_t *)buf);
2344                 if (r)
2345                         return r;
2346
2347                 spin_lock_irqsave(&adev->mmio_idx_lock, flags);
2348                 WREG32_NO_KIQ(mmMM_INDEX, ((uint32_t)*pos) | 0x80000000);
2349                 WREG32_NO_KIQ(mmMM_INDEX_HI, *pos >> 31);
2350                 WREG32_NO_KIQ(mmMM_DATA, value);
2351                 spin_unlock_irqrestore(&adev->mmio_idx_lock, flags);
2352
2353                 result += 4;
2354                 buf += 4;
2355                 *pos += 4;
2356                 size -= 4;
2357         }
2358
2359         return result;
2360 }
2361
2362 static const struct file_operations amdgpu_ttm_vram_fops = {
2363         .owner = THIS_MODULE,
2364         .read = amdgpu_ttm_vram_read,
2365         .write = amdgpu_ttm_vram_write,
2366         .llseek = default_llseek,
2367 };
2368
2369 #ifdef CONFIG_DRM_AMDGPU_GART_DEBUGFS
2370
2371 /**
2372  * amdgpu_ttm_gtt_read - Linear read access to GTT memory
2373  */
2374 static ssize_t amdgpu_ttm_gtt_read(struct file *f, char __user *buf,
2375                                    size_t size, loff_t *pos)
2376 {
2377         struct amdgpu_device *adev = file_inode(f)->i_private;
2378         ssize_t result = 0;
2379         int r;
2380
2381         while (size) {
2382                 loff_t p = *pos / PAGE_SIZE;
2383                 unsigned off = *pos & ~PAGE_MASK;
2384                 size_t cur_size = min_t(size_t, size, PAGE_SIZE - off);
2385                 struct page *page;
2386                 void *ptr;
2387
2388                 if (p >= adev->gart.num_cpu_pages)
2389                         return result;
2390
2391                 page = adev->gart.pages[p];
2392                 if (page) {
2393                         ptr = kmap(page);
2394                         ptr += off;
2395
2396                         r = copy_to_user(buf, ptr, cur_size);
2397                         kunmap(adev->gart.pages[p]);
2398                 } else
2399                         r = clear_user(buf, cur_size);
2400
2401                 if (r)
2402                         return -EFAULT;
2403
2404                 result += cur_size;
2405                 buf += cur_size;
2406                 *pos += cur_size;
2407                 size -= cur_size;
2408         }
2409
2410         return result;
2411 }
2412
2413 static const struct file_operations amdgpu_ttm_gtt_fops = {
2414         .owner = THIS_MODULE,
2415         .read = amdgpu_ttm_gtt_read,
2416         .llseek = default_llseek
2417 };
2418
2419 #endif
2420
2421 /**
2422  * amdgpu_iomem_read - Virtual read access to GPU mapped memory
2423  *
2424  * This function is used to read memory that has been mapped to the
2425  * GPU and the known addresses are not physical addresses but instead
2426  * bus addresses (e.g., what you'd put in an IB or ring buffer).
2427  */
2428 static ssize_t amdgpu_iomem_read(struct file *f, char __user *buf,
2429                                  size_t size, loff_t *pos)
2430 {
2431         struct amdgpu_device *adev = file_inode(f)->i_private;
2432         struct iommu_domain *dom;
2433         ssize_t result = 0;
2434         int r;
2435
2436         /* retrieve the IOMMU domain if any for this device */
2437         dom = iommu_get_domain_for_dev(adev->dev);
2438
2439         while (size) {
2440                 phys_addr_t addr = *pos & PAGE_MASK;
2441                 loff_t off = *pos & ~PAGE_MASK;
2442                 size_t bytes = PAGE_SIZE - off;
2443                 unsigned long pfn;
2444                 struct page *p;
2445                 void *ptr;
2446
2447                 bytes = bytes < size ? bytes : size;
2448
2449                 /* Translate the bus address to a physical address.  If
2450                  * the domain is NULL it means there is no IOMMU active
2451                  * and the address translation is the identity
2452                  */
2453                 addr = dom ? iommu_iova_to_phys(dom, addr) : addr;
2454
2455                 pfn = addr >> PAGE_SHIFT;
2456                 if (!pfn_valid(pfn))
2457                         return -EPERM;
2458
2459                 p = pfn_to_page(pfn);
2460                 if (p->mapping != adev->mman.bdev.dev_mapping)
2461                         return -EPERM;
2462
2463                 ptr = kmap(p);
2464                 r = copy_to_user(buf, ptr + off, bytes);
2465                 kunmap(p);
2466                 if (r)
2467                         return -EFAULT;
2468
2469                 size -= bytes;
2470                 *pos += bytes;
2471                 result += bytes;
2472         }
2473
2474         return result;
2475 }
2476
2477 /**
2478  * amdgpu_iomem_write - Virtual write access to GPU mapped memory
2479  *
2480  * This function is used to write memory that has been mapped to the
2481  * GPU and the known addresses are not physical addresses but instead
2482  * bus addresses (e.g., what you'd put in an IB or ring buffer).
2483  */
2484 static ssize_t amdgpu_iomem_write(struct file *f, const char __user *buf,
2485                                  size_t size, loff_t *pos)
2486 {
2487         struct amdgpu_device *adev = file_inode(f)->i_private;
2488         struct iommu_domain *dom;
2489         ssize_t result = 0;
2490         int r;
2491
2492         dom = iommu_get_domain_for_dev(adev->dev);
2493
2494         while (size) {
2495                 phys_addr_t addr = *pos & PAGE_MASK;
2496                 loff_t off = *pos & ~PAGE_MASK;
2497                 size_t bytes = PAGE_SIZE - off;
2498                 unsigned long pfn;
2499                 struct page *p;
2500                 void *ptr;
2501
2502                 bytes = bytes < size ? bytes : size;
2503
2504                 addr = dom ? iommu_iova_to_phys(dom, addr) : addr;
2505
2506                 pfn = addr >> PAGE_SHIFT;
2507                 if (!pfn_valid(pfn))
2508                         return -EPERM;
2509
2510                 p = pfn_to_page(pfn);
2511                 if (p->mapping != adev->mman.bdev.dev_mapping)
2512                         return -EPERM;
2513
2514                 ptr = kmap(p);
2515                 r = copy_from_user(ptr + off, buf, bytes);
2516                 kunmap(p);
2517                 if (r)
2518                         return -EFAULT;
2519
2520                 size -= bytes;
2521                 *pos += bytes;
2522                 result += bytes;
2523         }
2524
2525         return result;
2526 }
2527
2528 static const struct file_operations amdgpu_ttm_iomem_fops = {
2529         .owner = THIS_MODULE,
2530         .read = amdgpu_iomem_read,
2531         .write = amdgpu_iomem_write,
2532         .llseek = default_llseek
2533 };
2534
2535 static const struct {
2536         char *name;
2537         const struct file_operations *fops;
2538         int domain;
2539 } ttm_debugfs_entries[] = {
2540         { "amdgpu_vram", &amdgpu_ttm_vram_fops, TTM_PL_VRAM },
2541 #ifdef CONFIG_DRM_AMDGPU_GART_DEBUGFS
2542         { "amdgpu_gtt", &amdgpu_ttm_gtt_fops, TTM_PL_TT },
2543 #endif
2544         { "amdgpu_iomem", &amdgpu_ttm_iomem_fops, TTM_PL_SYSTEM },
2545 };
2546
2547 #endif
2548
2549 static int amdgpu_ttm_debugfs_init(struct amdgpu_device *adev)
2550 {
2551 #if defined(CONFIG_DEBUG_FS)
2552         unsigned count;
2553
2554         struct drm_minor *minor = adev->ddev->primary;
2555         struct dentry *ent, *root = minor->debugfs_root;
2556
2557         for (count = 0; count < ARRAY_SIZE(ttm_debugfs_entries); count++) {
2558                 ent = debugfs_create_file(
2559                                 ttm_debugfs_entries[count].name,
2560                                 S_IFREG | S_IRUGO, root,
2561                                 adev,
2562                                 ttm_debugfs_entries[count].fops);
2563                 if (IS_ERR(ent))
2564                         return PTR_ERR(ent);
2565                 if (ttm_debugfs_entries[count].domain == TTM_PL_VRAM)
2566                         i_size_write(ent->d_inode, adev->gmc.mc_vram_size);
2567                 else if (ttm_debugfs_entries[count].domain == TTM_PL_TT)
2568                         i_size_write(ent->d_inode, adev->gmc.gart_size);
2569                 adev->mman.debugfs_entries[count] = ent;
2570         }
2571
2572         count = ARRAY_SIZE(amdgpu_ttm_debugfs_list);
2573
2574 #ifdef CONFIG_SWIOTLB
2575         if (!(adev->need_swiotlb && swiotlb_nr_tbl()))
2576                 --count;
2577 #endif
2578
2579         return amdgpu_debugfs_add_files(adev, amdgpu_ttm_debugfs_list, count);
2580 #else
2581         return 0;
2582 #endif
2583 }
2584
2585 static void amdgpu_ttm_debugfs_fini(struct amdgpu_device *adev)
2586 {
2587 #if defined(CONFIG_DEBUG_FS)
2588         unsigned i;
2589
2590         for (i = 0; i < ARRAY_SIZE(ttm_debugfs_entries); i++)
2591                 debugfs_remove(adev->mman.debugfs_entries[i]);
2592 #endif
2593 }