drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c

   1 /*
   2  * Copyright 2009 Jerome Glisse.
   3  * All Rights Reserved.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the
   7  * "Software"), to deal in the Software without restriction, including
   8  * without limitation the rights to use, copy, modify, merge, publish,
   9  * distribute, sub license, and/or sell copies of the Software, and to
  10  * permit persons to whom the Software is furnished to do so, subject to
  11  * the following conditions:
  12  *
  13  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  14  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  15  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  16  * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
  17  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  18  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  19  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  20  *
  21  * The above copyright notice and this permission notice (including the
  22  * next paragraph) shall be included in all copies or substantial portions
  23  * of the Software.
  24  *
  25  */
  26 /*
  27  * Authors:
  28  *    Jerome Glisse <glisse@freedesktop.org>
  29  *    Thomas Hellstrom <thomas-at-tungstengraphics-dot-com>
  30  *    Dave Airlie
  31  */
  32
  33 #include <linux/dma-mapping.h>
  34 #include <linux/iommu.h>
  35 #include <linux/hmm.h>
  36 #include <linux/pagemap.h>
  37 #include <linux/sched/task.h>
  38 #include <linux/sched/mm.h>
  39 #include <linux/seq_file.h>
  40 #include <linux/slab.h>
  41 #include <linux/swap.h>
  42 #include <linux/swiotlb.h>
  43 #include <linux/dma-buf.h>
  44 #include <linux/sizes.h>
  45
  46 #include <drm/ttm/ttm_bo_api.h>
  47 #include <drm/ttm/ttm_bo_driver.h>
  48 #include <drm/ttm/ttm_placement.h>
  49 #include <drm/ttm/ttm_module.h>
  50 #include <drm/ttm/ttm_page_alloc.h>
  51
  52 #include <drm/drm_debugfs.h>
  53 #include <drm/amdgpu_drm.h>
  54
  55 #include "amdgpu.h"
  56 #include "amdgpu_object.h"
  57 #include "amdgpu_trace.h"
  58 #include "amdgpu_amdkfd.h"
  59 #include "amdgpu_sdma.h"
  60 #include "amdgpu_ras.h"
  61 #include "amdgpu_atomfirmware.h"
  62 #include "bif/bif_4_1_d.h"
  63
  64 #define AMDGPU_TTM_VRAM_MAX_DW_READ     (size_t)128
  65
  66 static int amdgpu_ttm_init_on_chip(struct amdgpu_device *adev,
  67                                     unsigned int type,
  68                                     uint64_t size)
  69 {
  70         return ttm_range_man_init(&adev->mman.bdev, type,
  71                                   TTM_PL_FLAG_UNCACHED, TTM_PL_FLAG_UNCACHED,
  72                                   false, size >> PAGE_SHIFT);
  73 }
  74
  75 /**
  76  * amdgpu_evict_flags - Compute placement flags
  77  *
  78  * @bo: The buffer object to evict
  79  * @placement: Possible destination(s) for evicted BO
  80  *
  81  * Fill in placement data when ttm_bo_evict() is called
  82  */
  83 static void amdgpu_evict_flags(struct ttm_buffer_object *bo,
  84                                 struct ttm_placement *placement)
  85 {
  86         struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev);
  87         struct amdgpu_bo *abo;
  88         static const struct ttm_place placements = {
  89                 .fpfn = 0,
  90                 .lpfn = 0,
  91                 .flags = TTM_PL_MASK_CACHING | TTM_PL_FLAG_SYSTEM
  92         };
  93
  94         /* Don't handle scatter gather BOs */
  95         if (bo->type == ttm_bo_type_sg) {
  96                 placement->num_placement = 0;
  97                 placement->num_busy_placement = 0;
  98                 return;
  99         }
 100
 101         /* Object isn't an AMDGPU object so ignore */
 102         if (!amdgpu_bo_is_amdgpu_bo(bo)) {
 103                 placement->placement = &placements;
 104                 placement->busy_placement = &placements;
 105                 placement->num_placement = 1;
 106                 placement->num_busy_placement = 1;
 107                 return;
 108         }
 109
 110         abo = ttm_to_amdgpu_bo(bo);
 111         switch (bo->mem.mem_type) {
 112         case AMDGPU_PL_GDS:
 113         case AMDGPU_PL_GWS:
 114         case AMDGPU_PL_OA:
 115                 placement->num_placement = 0;
 116                 placement->num_busy_placement = 0;
 117                 return;
 118
 119         case TTM_PL_VRAM:
 120                 if (!adev->mman.buffer_funcs_enabled) {
 121                         /* Move to system memory */
 122                         amdgpu_bo_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_CPU);
 123                 } else if (!amdgpu_gmc_vram_full_visible(&adev->gmc) &&
 124                            !(abo->flags & AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED) &&
 125                            amdgpu_bo_in_cpu_visible_vram(abo)) {
 126
 127                         /* Try evicting to the CPU inaccessible part of VRAM
 128                          * first, but only set GTT as busy placement, so this
 129                          * BO will be evicted to GTT rather than causing other
 130                          * BOs to be evicted from VRAM
 131                          */
 132                         amdgpu_bo_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_VRAM |
 133                                                          AMDGPU_GEM_DOMAIN_GTT);
 134                         abo->placements[0].fpfn = adev->gmc.visible_vram_size >> PAGE_SHIFT;
 135                         abo->placements[0].lpfn = 0;
 136                         abo->placement.busy_placement = &abo->placements[1];
 137                         abo->placement.num_busy_placement = 1;
 138                 } else {
 139                         /* Move to GTT memory */
 140                         amdgpu_bo_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_GTT);
 141                 }
 142                 break;
 143         case TTM_PL_TT:
 144         default:
 145                 amdgpu_bo_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_CPU);
 146                 break;
 147         }
 148         *placement = abo->placement;
 149 }
 150
 151 /**
 152  * amdgpu_verify_access - Verify access for a mmap call
 153  *
 154  * @bo: The buffer object to map
 155  * @filp: The file pointer from the process performing the mmap
 156  *
 157  * This is called by ttm_bo_mmap() to verify whether a process
 158  * has the right to mmap a BO to their process space.
 159  */
 160 static int amdgpu_verify_access(struct ttm_buffer_object *bo, struct file *filp)
 161 {
 162         struct amdgpu_bo *abo = ttm_to_amdgpu_bo(bo);
 163
 164         /*
 165          * Don't verify access for KFD BOs. They don't have a GEM
 166          * object associated with them.
 167          */
 168         if (abo->kfd_bo)
 169                 return 0;
 170
 171         if (amdgpu_ttm_tt_get_usermm(bo->ttm))
 172                 return -EPERM;
 173         return drm_vma_node_verify_access(&abo->tbo.base.vma_node,
 174                                           filp->private_data);
 175 }
 176
 177 /**
 178  * amdgpu_move_null - Register memory for a buffer object
 179  *
 180  * @bo: The bo to assign the memory to
 181  * @new_mem: The memory to be assigned.
 182  *
 183  * Assign the memory from new_mem to the memory of the buffer object bo.
 184  */
 185 static void amdgpu_move_null(struct ttm_buffer_object *bo,
 186                              struct ttm_resource *new_mem)
 187 {
 188         struct ttm_resource *old_mem = &bo->mem;
 189
 190         BUG_ON(old_mem->mm_node != NULL);
 191         *old_mem = *new_mem;
 192         new_mem->mm_node = NULL;
 193 }
 194
 195 /**
 196  * amdgpu_mm_node_addr - Compute the GPU relative offset of a GTT buffer.
 197  *
 198  * @bo: The bo to assign the memory to.
 199  * @mm_node: Memory manager node for drm allocator.
 200  * @mem: The region where the bo resides.
 201  *
 202  */
 203 static uint64_t amdgpu_mm_node_addr(struct ttm_buffer_object *bo,
 204                                     struct drm_mm_node *mm_node,
 205                                     struct ttm_resource *mem)
 206 {
 207         uint64_t addr = 0;
 208
 209         if (mm_node->start != AMDGPU_BO_INVALID_OFFSET) {
 210                 addr = mm_node->start << PAGE_SHIFT;
 211                 addr += amdgpu_ttm_domain_start(amdgpu_ttm_adev(bo->bdev),
 212                                                 mem->mem_type);
 213         }
 214         return addr;
 215 }
 216
 217 /**
 218  * amdgpu_find_mm_node - Helper function finds the drm_mm_node corresponding to
 219  * @offset. It also modifies the offset to be within the drm_mm_node returned
 220  *
 221  * @mem: The region where the bo resides.
 222  * @offset: The offset that drm_mm_node is used for finding.
 223  *
 224  */
 225 static struct drm_mm_node *amdgpu_find_mm_node(struct ttm_resource *mem,
 226                                                uint64_t *offset)
 227 {
 228         struct drm_mm_node *mm_node = mem->mm_node;
 229
 230         while (*offset >= (mm_node->size << PAGE_SHIFT)) {
 231                 *offset -= (mm_node->size << PAGE_SHIFT);
 232                 ++mm_node;
 233         }
 234         return mm_node;
 235 }
 236
 237 /**
 238  * amdgpu_ttm_map_buffer - Map memory into the GART windows
 239  * @bo: buffer object to map
 240  * @mem: memory object to map
 241  * @mm_node: drm_mm node object to map
 242  * @num_pages: number of pages to map
 243  * @offset: offset into @mm_node where to start
 244  * @window: which GART window to use
 245  * @ring: DMA ring to use for the copy
 246  * @tmz: if we should setup a TMZ enabled mapping
 247  * @addr: resulting address inside the MC address space
 248  *
 249  * Setup one of the GART windows to access a specific piece of memory or return
 250  * the physical address for local memory.
 251  */
 252 static int amdgpu_ttm_map_buffer(struct ttm_buffer_object *bo,
 253                                  struct ttm_resource *mem,
 254                                  struct drm_mm_node *mm_node,
 255                                  unsigned num_pages, uint64_t offset,
 256                                  unsigned window, struct amdgpu_ring *ring,
 257                                  bool tmz, uint64_t *addr)
 258 {
 259         struct amdgpu_device *adev = ring->adev;
 260         struct amdgpu_job *job;
 261         unsigned num_dw, num_bytes;
 262         struct dma_fence *fence;
 263         uint64_t src_addr, dst_addr;
 264         void *cpu_addr;
 265         uint64_t flags;
 266         unsigned int i;
 267         int r;
 268
 269         BUG_ON(adev->mman.buffer_funcs->copy_max_bytes <
 270                AMDGPU_GTT_MAX_TRANSFER_SIZE * 8);
 271
 272         /* Map only what can't be accessed directly */
 273         if (!tmz && mem->start != AMDGPU_BO_INVALID_OFFSET) {
 274                 *addr = amdgpu_mm_node_addr(bo, mm_node, mem) + offset;
 275                 return 0;
 276         }
 277
 278         *addr = adev->gmc.gart_start;
 279         *addr += (u64)window * AMDGPU_GTT_MAX_TRANSFER_SIZE *
 280                 AMDGPU_GPU_PAGE_SIZE;
 281         *addr += offset & ~PAGE_MASK;
 282
 283         num_dw = ALIGN(adev->mman.buffer_funcs->copy_num_dw, 8);
 284         num_bytes = num_pages * 8;
 285
 286         r = amdgpu_job_alloc_with_ib(adev, num_dw * 4 + num_bytes,
 287                                      AMDGPU_IB_POOL_DELAYED, &job);
 288         if (r)
 289                 return r;
 290
 291         src_addr = num_dw * 4;
 292         src_addr += job->ibs[0].gpu_addr;
 293
 294         dst_addr = amdgpu_bo_gpu_offset(adev->gart.bo);
 295         dst_addr += window * AMDGPU_GTT_MAX_TRANSFER_SIZE * 8;
 296         amdgpu_emit_copy_buffer(adev, &job->ibs[0], src_addr,
 297                                 dst_addr, num_bytes, false);
 298
 299         amdgpu_ring_pad_ib(ring, &job->ibs[0]);
 300         WARN_ON(job->ibs[0].length_dw > num_dw);
 301
 302         flags = amdgpu_ttm_tt_pte_flags(adev, bo->ttm, mem);
 303         if (tmz)
 304                 flags |= AMDGPU_PTE_TMZ;
 305
 306         cpu_addr = &job->ibs[0].ptr[num_dw];
 307
 308         if (mem->mem_type == TTM_PL_TT) {
 309                 struct ttm_dma_tt *dma;
 310                 dma_addr_t *dma_address;
 311
 312                 dma = container_of(bo->ttm, struct ttm_dma_tt, ttm);
 313                 dma_address = &dma->dma_address[offset >> PAGE_SHIFT];
 314                 r = amdgpu_gart_map(adev, 0, num_pages, dma_address, flags,
 315                                     cpu_addr);
 316                 if (r)
 317                         goto error_free;
 318         } else {
 319                 dma_addr_t dma_address;
 320
 321                 dma_address = (mm_node->start << PAGE_SHIFT) + offset;
 322                 dma_address += adev->vm_manager.vram_base_offset;
 323
 324                 for (i = 0; i < num_pages; ++i) {
 325                         r = amdgpu_gart_map(adev, i << PAGE_SHIFT, 1,
 326                                             &dma_address, flags, cpu_addr);
 327                         if (r)
 328                                 goto error_free;
 329
 330                         dma_address += PAGE_SIZE;
 331                 }
 332         }
 333
 334         r = amdgpu_job_submit(job, &adev->mman.entity,
 335                               AMDGPU_FENCE_OWNER_UNDEFINED, &fence);
 336         if (r)
 337                 goto error_free;
 338
 339         dma_fence_put(fence);
 340
 341         return r;
 342
 343 error_free:
 344         amdgpu_job_free(job);
 345         return r;
 346 }
 347
 348 /**
 349  * amdgpu_copy_ttm_mem_to_mem - Helper function for copy
 350  * @adev: amdgpu device
 351  * @src: buffer/address where to read from
 352  * @dst: buffer/address where to write to
 353  * @size: number of bytes to copy
 354  * @tmz: if a secure copy should be used
 355  * @resv: resv object to sync to
 356  * @f: Returns the last fence if multiple jobs are submitted.
 357  *
 358  * The function copies @size bytes from {src->mem + src->offset} to
 359  * {dst->mem + dst->offset}. src->bo and dst->bo could be same BO for a
 360  * move and different for a BO to BO copy.
 361  *
 362  */
 363 int amdgpu_ttm_copy_mem_to_mem(struct amdgpu_device *adev,
 364                                const struct amdgpu_copy_mem *src,
 365                                const struct amdgpu_copy_mem *dst,
 366                                uint64_t size, bool tmz,
 367                                struct dma_resv *resv,
 368                                struct dma_fence **f)
 369 {
 370         const uint32_t GTT_MAX_BYTES = (AMDGPU_GTT_MAX_TRANSFER_SIZE *
 371                                         AMDGPU_GPU_PAGE_SIZE);
 372
 373         uint64_t src_node_size, dst_node_size, src_offset, dst_offset;
 374         struct amdgpu_ring *ring = adev->mman.buffer_funcs_ring;
 375         struct drm_mm_node *src_mm, *dst_mm;
 376         struct dma_fence *fence = NULL;
 377         int r = 0;
 378
 379         if (!adev->mman.buffer_funcs_enabled) {
 380                 DRM_ERROR("Trying to move memory with ring turned off.\n");
 381                 return -EINVAL;
 382         }
 383
 384         src_offset = src->offset;
 385         if (src->mem->mm_node) {
 386                 src_mm = amdgpu_find_mm_node(src->mem, &src_offset);
 387                 src_node_size = (src_mm->size << PAGE_SHIFT) - src_offset;
 388         } else {
 389                 src_mm = NULL;
 390                 src_node_size = ULLONG_MAX;
 391         }
 392
 393         dst_offset = dst->offset;
 394         if (dst->mem->mm_node) {
 395                 dst_mm = amdgpu_find_mm_node(dst->mem, &dst_offset);
 396                 dst_node_size = (dst_mm->size << PAGE_SHIFT) - dst_offset;
 397         } else {
 398                 dst_mm = NULL;
 399                 dst_node_size = ULLONG_MAX;
 400         }
 401
 402         mutex_lock(&adev->mman.gtt_window_lock);
 403
 404         while (size) {
 405                 uint32_t src_page_offset = src_offset & ~PAGE_MASK;
 406                 uint32_t dst_page_offset = dst_offset & ~PAGE_MASK;
 407                 struct dma_fence *next;
 408                 uint32_t cur_size;
 409                 uint64_t from, to;
 410
 411                 /* Copy size cannot exceed GTT_MAX_BYTES. So if src or dst
 412                  * begins at an offset, then adjust the size accordingly
 413                  */
 414                 cur_size = max(src_page_offset, dst_page_offset);
 415                 cur_size = min(min3(src_node_size, dst_node_size, size),
 416                                (uint64_t)(GTT_MAX_BYTES - cur_size));
 417
 418                 /* Map src to window 0 and dst to window 1. */
 419                 r = amdgpu_ttm_map_buffer(src->bo, src->mem, src_mm,
 420                                           PFN_UP(cur_size + src_page_offset),
 421                                           src_offset, 0, ring, tmz, &from);
 422                 if (r)
 423                         goto error;
 424
 425                 r = amdgpu_ttm_map_buffer(dst->bo, dst->mem, dst_mm,
 426                                           PFN_UP(cur_size + dst_page_offset),
 427                                           dst_offset, 1, ring, tmz, &to);
 428                 if (r)
 429                         goto error;
 430
 431                 r = amdgpu_copy_buffer(ring, from, to, cur_size,
 432                                        resv, &next, false, true, tmz);
 433                 if (r)
 434                         goto error;
 435
 436                 dma_fence_put(fence);
 437                 fence = next;
 438
 439                 size -= cur_size;
 440                 if (!size)
 441                         break;
 442
 443                 src_node_size -= cur_size;
 444                 if (!src_node_size) {
 445                         ++src_mm;
 446                         src_node_size = src_mm->size << PAGE_SHIFT;
 447                         src_offset = 0;
 448                 } else {
 449                         src_offset += cur_size;
 450                 }
 451
 452                 dst_node_size -= cur_size;
 453                 if (!dst_node_size) {
 454                         ++dst_mm;
 455                         dst_node_size = dst_mm->size << PAGE_SHIFT;
 456                         dst_offset = 0;
 457                 } else {
 458                         dst_offset += cur_size;
 459                 }
 460         }
 461 error:
 462         mutex_unlock(&adev->mman.gtt_window_lock);
 463         if (f)
 464                 *f = dma_fence_get(fence);
 465         dma_fence_put(fence);
 466         return r;
 467 }
 468
 469 /**
 470  * amdgpu_move_blit - Copy an entire buffer to another buffer
 471  *
 472  * This is a helper called by amdgpu_bo_move() and amdgpu_move_vram_ram() to
 473  * help move buffers to and from VRAM.
 474  */
 475 static int amdgpu_move_blit(struct ttm_buffer_object *bo,
 476                             bool evict, bool no_wait_gpu,
 477                             struct ttm_resource *new_mem,
 478                             struct ttm_resource *old_mem)
 479 {
 480         struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev);
 481         struct amdgpu_bo *abo = ttm_to_amdgpu_bo(bo);
 482         struct amdgpu_copy_mem src, dst;
 483         struct dma_fence *fence = NULL;
 484         int r;
 485
 486         src.bo = bo;
 487         dst.bo = bo;
 488         src.mem = old_mem;
 489         dst.mem = new_mem;
 490         src.offset = 0;
 491         dst.offset = 0;
 492
 493         r = amdgpu_ttm_copy_mem_to_mem(adev, &src, &dst,
 494                                        new_mem->num_pages << PAGE_SHIFT,
 495                                        amdgpu_bo_encrypted(abo),
 496                                        bo->base.resv, &fence);
 497         if (r)
 498                 goto error;
 499
 500         /* clear the space being freed */
 501         if (old_mem->mem_type == TTM_PL_VRAM &&
 502             (abo->flags & AMDGPU_GEM_CREATE_VRAM_WIPE_ON_RELEASE)) {
 503                 struct dma_fence *wipe_fence = NULL;
 504
 505                 r = amdgpu_fill_buffer(ttm_to_amdgpu_bo(bo), AMDGPU_POISON,
 506                                        NULL, &wipe_fence);
 507                 if (r) {
 508                         goto error;
 509                 } else if (wipe_fence) {
 510                         dma_fence_put(fence);
 511                         fence = wipe_fence;
 512                 }
 513         }
 514
 515         /* Always block for VM page tables before committing the new location */
 516         if (bo->type == ttm_bo_type_kernel)
 517                 r = ttm_bo_move_accel_cleanup(bo, fence, true, new_mem);
 518         else
 519                 r = ttm_bo_pipeline_move(bo, fence, evict, new_mem);
 520         dma_fence_put(fence);
 521         return r;
 522
 523 error:
 524         if (fence)
 525                 dma_fence_wait(fence, false);
 526         dma_fence_put(fence);
 527         return r;
 528 }
 529
 530 /**
 531  * amdgpu_move_vram_ram - Copy VRAM buffer to RAM buffer
 532  *
 533  * Called by amdgpu_bo_move().
 534  */
 535 static int amdgpu_move_vram_ram(struct ttm_buffer_object *bo, bool evict,
 536                                 struct ttm_operation_ctx *ctx,
 537                                 struct ttm_resource *new_mem)
 538 {
 539         struct ttm_resource *old_mem = &bo->mem;
 540         struct ttm_resource tmp_mem;
 541         struct ttm_place placements;
 542         struct ttm_placement placement;
 543         int r;
 544
 545         /* create space/pages for new_mem in GTT space */
 546         tmp_mem = *new_mem;
 547         tmp_mem.mm_node = NULL;
 548         placement.num_placement = 1;
 549         placement.placement = &placements;
 550         placement.num_busy_placement = 1;
 551         placement.busy_placement = &placements;
 552         placements.fpfn = 0;
 553         placements.lpfn = 0;
 554         placements.flags = TTM_PL_MASK_CACHING | TTM_PL_FLAG_TT;
 555         r = ttm_bo_mem_space(bo, &placement, &tmp_mem, ctx);
 556         if (unlikely(r)) {
 557                 pr_err("Failed to find GTT space for blit from VRAM\n");
 558                 return r;
 559         }
 560
 561         /* set caching flags */
 562         r = ttm_tt_set_placement_caching(bo->ttm, tmp_mem.placement);
 563         if (unlikely(r)) {
 564                 goto out_cleanup;
 565         }
 566
 567         /* Bind the memory to the GTT space */
 568         r = ttm_tt_bind(bo->ttm, &tmp_mem, ctx);
 569         if (unlikely(r)) {
 570                 goto out_cleanup;
 571         }
 572
 573         /* blit VRAM to GTT */
 574         r = amdgpu_move_blit(bo, evict, ctx->no_wait_gpu, &tmp_mem, old_mem);
 575         if (unlikely(r)) {
 576                 goto out_cleanup;
 577         }
 578
 579         /* move BO (in tmp_mem) to new_mem */
 580         r = ttm_bo_move_ttm(bo, ctx, new_mem);
 581 out_cleanup:
 582         ttm_resource_free(bo, &tmp_mem);
 583         return r;
 584 }
 585
 586 /**
 587  * amdgpu_move_ram_vram - Copy buffer from RAM to VRAM
 588  *
 589  * Called by amdgpu_bo_move().
 590  */
 591 static int amdgpu_move_ram_vram(struct ttm_buffer_object *bo, bool evict,
 592                                 struct ttm_operation_ctx *ctx,
 593                                 struct ttm_resource *new_mem)
 594 {
 595         struct ttm_resource *old_mem = &bo->mem;
 596         struct ttm_resource tmp_mem;
 597         struct ttm_placement placement;
 598         struct ttm_place placements;
 599         int r;
 600
 601         /* make space in GTT for old_mem buffer */
 602         tmp_mem = *new_mem;
 603         tmp_mem.mm_node = NULL;
 604         placement.num_placement = 1;
 605         placement.placement = &placements;
 606         placement.num_busy_placement = 1;
 607         placement.busy_placement = &placements;
 608         placements.fpfn = 0;
 609         placements.lpfn = 0;
 610         placements.flags = TTM_PL_MASK_CACHING | TTM_PL_FLAG_TT;
 611         r = ttm_bo_mem_space(bo, &placement, &tmp_mem, ctx);
 612         if (unlikely(r)) {
 613                 pr_err("Failed to find GTT space for blit to VRAM\n");
 614                 return r;
 615         }
 616
 617         /* move/bind old memory to GTT space */
 618         r = ttm_bo_move_ttm(bo, ctx, &tmp_mem);
 619         if (unlikely(r)) {
 620                 goto out_cleanup;
 621         }
 622
 623         /* copy to VRAM */
 624         r = amdgpu_move_blit(bo, evict, ctx->no_wait_gpu, new_mem, old_mem);
 625         if (unlikely(r)) {
 626                 goto out_cleanup;
 627         }
 628 out_cleanup:
 629         ttm_resource_free(bo, &tmp_mem);
 630         return r;
 631 }
 632
 633 /**
 634  * amdgpu_mem_visible - Check that memory can be accessed by ttm_bo_move_memcpy
 635  *
 636  * Called by amdgpu_bo_move()
 637  */
 638 static bool amdgpu_mem_visible(struct amdgpu_device *adev,
 639                                struct ttm_resource *mem)
 640 {
 641         struct drm_mm_node *nodes = mem->mm_node;
 642
 643         if (mem->mem_type == TTM_PL_SYSTEM ||
 644             mem->mem_type == TTM_PL_TT)
 645                 return true;
 646         if (mem->mem_type != TTM_PL_VRAM)
 647                 return false;
 648
 649         /* ttm_resource_ioremap only supports contiguous memory */
 650         if (nodes->size != mem->num_pages)
 651                 return false;
 652
 653         return ((nodes->start + nodes->size) << PAGE_SHIFT)
 654                 <= adev->gmc.visible_vram_size;
 655 }
 656
 657 /**
 658  * amdgpu_bo_move - Move a buffer object to a new memory location
 659  *
 660  * Called by ttm_bo_handle_move_mem()
 661  */
 662 static int amdgpu_bo_move(struct ttm_buffer_object *bo, bool evict,
 663                           struct ttm_operation_ctx *ctx,
 664                           struct ttm_resource *new_mem)
 665 {
 666         struct amdgpu_device *adev;
 667         struct amdgpu_bo *abo;
 668         struct ttm_resource *old_mem = &bo->mem;
 669         int r;
 670
 671         /* Can't move a pinned BO */
 672         abo = ttm_to_amdgpu_bo(bo);
 673         if (WARN_ON_ONCE(abo->pin_count > 0))
 674                 return -EINVAL;
 675
 676         adev = amdgpu_ttm_adev(bo->bdev);
 677
 678         if (old_mem->mem_type == TTM_PL_SYSTEM && bo->ttm == NULL) {
 679                 amdgpu_move_null(bo, new_mem);
 680                 return 0;
 681         }
 682         if ((old_mem->mem_type == TTM_PL_TT &&
 683              new_mem->mem_type == TTM_PL_SYSTEM) ||
 684             (old_mem->mem_type == TTM_PL_SYSTEM &&
 685              new_mem->mem_type == TTM_PL_TT)) {
 686                 /* bind is enough */
 687                 amdgpu_move_null(bo, new_mem);
 688                 return 0;
 689         }
 690         if (old_mem->mem_type == AMDGPU_PL_GDS ||
 691             old_mem->mem_type == AMDGPU_PL_GWS ||
 692             old_mem->mem_type == AMDGPU_PL_OA ||
 693             new_mem->mem_type == AMDGPU_PL_GDS ||
 694             new_mem->mem_type == AMDGPU_PL_GWS ||
 695             new_mem->mem_type == AMDGPU_PL_OA) {
 696                 /* Nothing to save here */
 697                 amdgpu_move_null(bo, new_mem);
 698                 return 0;
 699         }
 700
 701         if (!adev->mman.buffer_funcs_enabled) {
 702                 r = -ENODEV;
 703                 goto memcpy;
 704         }
 705
 706         if (old_mem->mem_type == TTM_PL_VRAM &&
 707             new_mem->mem_type == TTM_PL_SYSTEM) {
 708                 r = amdgpu_move_vram_ram(bo, evict, ctx, new_mem);
 709         } else if (old_mem->mem_type == TTM_PL_SYSTEM &&
 710                    new_mem->mem_type == TTM_PL_VRAM) {
 711                 r = amdgpu_move_ram_vram(bo, evict, ctx, new_mem);
 712         } else {
 713                 r = amdgpu_move_blit(bo, evict, ctx->no_wait_gpu,
 714                                      new_mem, old_mem);
 715         }
 716
 717         if (r) {
 718 memcpy:
 719                 /* Check that all memory is CPU accessible */
 720                 if (!amdgpu_mem_visible(adev, old_mem) ||
 721                     !amdgpu_mem_visible(adev, new_mem)) {
 722                         pr_err("Move buffer fallback to memcpy unavailable\n");
 723                         return r;
 724                 }
 725
 726                 r = ttm_bo_move_memcpy(bo, ctx, new_mem);
 727                 if (r)
 728                         return r;
 729         }
 730
 731         if (bo->type == ttm_bo_type_device &&
 732             new_mem->mem_type == TTM_PL_VRAM &&
 733             old_mem->mem_type != TTM_PL_VRAM) {
 734                 /* amdgpu_bo_fault_reserve_notify will re-set this if the CPU
 735                  * accesses the BO after it's moved.
 736                  */
 737                 abo->flags &= ~AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED;
 738         }
 739
 740         /* update statistics */
 741         atomic64_add((u64)bo->num_pages << PAGE_SHIFT, &adev->num_bytes_moved);
 742         return 0;
 743 }
 744
 745 /**
 746  * amdgpu_ttm_io_mem_reserve - Reserve a block of memory during a fault
 747  *
 748  * Called by ttm_mem_io_reserve() ultimately via ttm_bo_vm_fault()
 749  */
 750 static int amdgpu_ttm_io_mem_reserve(struct ttm_bo_device *bdev, struct ttm_resource *mem)
 751 {
 752         struct amdgpu_device *adev = amdgpu_ttm_adev(bdev);
 753         struct drm_mm_node *mm_node = mem->mm_node;
 754         size_t bus_size = (size_t)mem->num_pages << PAGE_SHIFT;
 755
 756         switch (mem->mem_type) {
 757         case TTM_PL_SYSTEM:
 758                 /* system memory */
 759                 return 0;
 760         case TTM_PL_TT:
 761                 break;
 762         case TTM_PL_VRAM:
 763                 mem->bus.offset = mem->start << PAGE_SHIFT;
 764                 /* check if it's visible */
 765                 if ((mem->bus.offset + bus_size) > adev->gmc.visible_vram_size)
 766                         return -EINVAL;
 767                 /* Only physically contiguous buffers apply. In a contiguous
 768                  * buffer, size of the first mm_node would match the number of
 769                  * pages in ttm_resource.
 770                  */
 771                 if (adev->mman.aper_base_kaddr &&
 772                     (mm_node->size == mem->num_pages))
 773                         mem->bus.addr = (u8 *)adev->mman.aper_base_kaddr +
 774                                         mem->bus.offset;
 775
 776                 mem->bus.base = adev->gmc.aper_base;
 777                 mem->bus.is_iomem = true;
 778                 break;
 779         default:
 780                 return -EINVAL;
 781         }
 782         return 0;
 783 }
 784
 785 static unsigned long amdgpu_ttm_io_mem_pfn(struct ttm_buffer_object *bo,
 786                                            unsigned long page_offset)
 787 {
 788         uint64_t offset = (page_offset << PAGE_SHIFT);
 789         struct drm_mm_node *mm;
 790
 791         mm = amdgpu_find_mm_node(&bo->mem, &offset);
 792         return (bo->mem.bus.base >> PAGE_SHIFT) + mm->start +
 793                 (offset >> PAGE_SHIFT);
 794 }
 795
 796 /**
 797  * amdgpu_ttm_domain_start - Returns GPU start address
 798  * @adev: amdgpu device object
 799  * @type: type of the memory
 800  *
 801  * Returns:
 802  * GPU start address of a memory domain
 803  */
 804
 805 uint64_t amdgpu_ttm_domain_start(struct amdgpu_device *adev, uint32_t type)
 806 {
 807         switch (type) {
 808         case TTM_PL_TT:
 809                 return adev->gmc.gart_start;
 810         case TTM_PL_VRAM:
 811                 return adev->gmc.vram_start;
 812         }
 813
 814         return 0;
 815 }
 816
 817 /*
 818  * TTM backend functions.
 819  */
 820 struct amdgpu_ttm_tt {
 821         struct ttm_dma_tt       ttm;
 822         struct drm_gem_object   *gobj;
 823         u64                     offset;
 824         uint64_t                userptr;
 825         struct task_struct      *usertask;
 826         uint32_t                userflags;
 827 #if IS_ENABLED(CONFIG_DRM_AMDGPU_USERPTR)
 828         struct hmm_range        *range;
 829 #endif
 830 };
 831
 832 #ifdef CONFIG_DRM_AMDGPU_USERPTR
 833 /**
 834  * amdgpu_ttm_tt_get_user_pages - get device accessible pages that back user
 835  * memory and start HMM tracking CPU page table update
 836  *
 837  * Calling function must call amdgpu_ttm_tt_userptr_range_done() once and only
 838  * once afterwards to stop HMM tracking
 839  */
 840 int amdgpu_ttm_tt_get_user_pages(struct amdgpu_bo *bo, struct page **pages)
 841 {
 842         struct ttm_tt *ttm = bo->tbo.ttm;
 843         struct amdgpu_ttm_tt *gtt = (void *)ttm;
 844         unsigned long start = gtt->userptr;
 845         struct vm_area_struct *vma;
 846         struct hmm_range *range;
 847         unsigned long timeout;
 848         struct mm_struct *mm;
 849         unsigned long i;
 850         int r = 0;
 851
 852         mm = bo->notifier.mm;
 853         if (unlikely(!mm)) {
 854                 DRM_DEBUG_DRIVER("BO is not registered?\n");
 855                 return -EFAULT;
 856         }
 857
 858         /* Another get_user_pages is running at the same time?? */
 859         if (WARN_ON(gtt->range))
 860                 return -EFAULT;
 861
 862         if (!mmget_not_zero(mm)) /* Happens during process shutdown */
 863                 return -ESRCH;
 864
 865         range = kzalloc(sizeof(*range), GFP_KERNEL);
 866         if (unlikely(!range)) {
 867                 r = -ENOMEM;
 868                 goto out;
 869         }
 870         range->notifier = &bo->notifier;
 871         range->start = bo->notifier.interval_tree.start;
 872         range->end = bo->notifier.interval_tree.last + 1;
 873         range->default_flags = HMM_PFN_REQ_FAULT;
 874         if (!amdgpu_ttm_tt_is_readonly(ttm))
 875                 range->default_flags |= HMM_PFN_REQ_WRITE;
 876
 877         range->hmm_pfns = kvmalloc_array(ttm->num_pages,
 878                                          sizeof(*range->hmm_pfns), GFP_KERNEL);
 879         if (unlikely(!range->hmm_pfns)) {
 880                 r = -ENOMEM;
 881                 goto out_free_ranges;
 882         }
 883
 884         mmap_read_lock(mm);
 885         vma = find_vma(mm, start);
 886         if (unlikely(!vma || start < vma->vm_start)) {
 887                 r = -EFAULT;
 888                 goto out_unlock;
 889         }
 890         if (unlikely((gtt->userflags & AMDGPU_GEM_USERPTR_ANONONLY) &&
 891                 vma->vm_file)) {
 892                 r = -EPERM;
 893                 goto out_unlock;
 894         }
 895         mmap_read_unlock(mm);
 896         timeout = jiffies + msecs_to_jiffies(HMM_RANGE_DEFAULT_TIMEOUT);
 897
 898 retry:
 899         range->notifier_seq = mmu_interval_read_begin(&bo->notifier);
 900
 901         mmap_read_lock(mm);
 902         r = hmm_range_fault(range);
 903         mmap_read_unlock(mm);
 904         if (unlikely(r)) {
 905                 /*
 906                  * FIXME: This timeout should encompass the retry from
 907                  * mmu_interval_read_retry() as well.
 908                  */
 909                 if (r == -EBUSY && !time_after(jiffies, timeout))
 910                         goto retry;
 911                 goto out_free_pfns;
 912         }
 913
 914         /*
 915          * Due to default_flags, all pages are HMM_PFN_VALID or
 916          * hmm_range_fault() fails. FIXME: The pages cannot be touched outside
 917          * the notifier_lock, and mmu_interval_read_retry() must be done first.
 918          */
 919         for (i = 0; i < ttm->num_pages; i++)
 920                 pages[i] = hmm_pfn_to_page(range->hmm_pfns[i]);
 921
 922         gtt->range = range;
 923         mmput(mm);
 924
 925         return 0;
 926
 927 out_unlock:
 928         mmap_read_unlock(mm);
 929 out_free_pfns:
 930         kvfree(range->hmm_pfns);
 931 out_free_ranges:
 932         kfree(range);
 933 out:
 934         mmput(mm);
 935         return r;
 936 }
 937
 938 /**
 939  * amdgpu_ttm_tt_userptr_range_done - stop HMM track the CPU page table change
 940  * Check if the pages backing this ttm range have been invalidated
 941  *
 942  * Returns: true if pages are still valid
 943  */
 944 bool amdgpu_ttm_tt_get_user_pages_done(struct ttm_tt *ttm)
 945 {
 946         struct amdgpu_ttm_tt *gtt = (void *)ttm;
 947         bool r = false;
 948
 949         if (!gtt || !gtt->userptr)
 950                 return false;
 951
 952         DRM_DEBUG_DRIVER("user_pages_done 0x%llx pages 0x%lx\n",
 953                 gtt->userptr, ttm->num_pages);
 954
 955         WARN_ONCE(!gtt->range || !gtt->range->hmm_pfns,
 956                 "No user pages to check\n");
 957
 958         if (gtt->range) {
 959                 /*
 960                  * FIXME: Must always hold notifier_lock for this, and must
 961                  * not ignore the return code.
 962                  */
 963                 r = mmu_interval_read_retry(gtt->range->notifier,
 964                                          gtt->range->notifier_seq);
 965                 kvfree(gtt->range->hmm_pfns);
 966                 kfree(gtt->range);
 967                 gtt->range = NULL;
 968         }
 969
 970         return !r;
 971 }
 972 #endif
 973
 974 /**
 975  * amdgpu_ttm_tt_set_user_pages - Copy pages in, putting old pages as necessary.
 976  *
 977  * Called by amdgpu_cs_list_validate(). This creates the page list
 978  * that backs user memory and will ultimately be mapped into the device
 979  * address space.
 980  */
 981 void amdgpu_ttm_tt_set_user_pages(struct ttm_tt *ttm, struct page **pages)
 982 {
 983         unsigned long i;
 984
 985         for (i = 0; i < ttm->num_pages; ++i)
 986                 ttm->pages[i] = pages ? pages[i] : NULL;
 987 }
 988
 989 /**
 990  * amdgpu_ttm_tt_pin_userptr -  prepare the sg table with the user pages
 991  *
 992  * Called by amdgpu_ttm_backend_bind()
 993  **/
 994 static int amdgpu_ttm_tt_pin_userptr(struct ttm_tt *ttm)
 995 {
 996         struct amdgpu_device *adev = amdgpu_ttm_adev(ttm->bdev);
 997         struct amdgpu_ttm_tt *gtt = (void *)ttm;
 998         int r;
 999
1000         int write = !(gtt->userflags & AMDGPU_GEM_USERPTR_READONLY);
1001         enum dma_data_direction direction = write ?
1002                 DMA_BIDIRECTIONAL : DMA_TO_DEVICE;
1003
1004         /* Allocate an SG array and squash pages into it */
1005         r = sg_alloc_table_from_pages(ttm->sg, ttm->pages, ttm->num_pages, 0,
1006                                       ttm->num_pages << PAGE_SHIFT,
1007                                       GFP_KERNEL);
1008         if (r)
1009                 goto release_sg;
1010
1011         /* Map SG to device */
1012         r = dma_map_sgtable(adev->dev, ttm->sg, direction, 0);
1013         if (r)
1014                 goto release_sg;
1015
1016         /* convert SG to linear array of pages and dma addresses */
1017         drm_prime_sg_to_page_addr_arrays(ttm->sg, ttm->pages,
1018                                          gtt->ttm.dma_address, ttm->num_pages);
1019
1020         return 0;
1021
1022 release_sg:
1023         kfree(ttm->sg);
1024         return r;
1025 }
1026
1027 /**
1028  * amdgpu_ttm_tt_unpin_userptr - Unpin and unmap userptr pages
1029  */
1030 static void amdgpu_ttm_tt_unpin_userptr(struct ttm_tt *ttm)
1031 {
1032         struct amdgpu_device *adev = amdgpu_ttm_adev(ttm->bdev);
1033         struct amdgpu_ttm_tt *gtt = (void *)ttm;
1034
1035         int write = !(gtt->userflags & AMDGPU_GEM_USERPTR_READONLY);
1036         enum dma_data_direction direction = write ?
1037                 DMA_BIDIRECTIONAL : DMA_TO_DEVICE;
1038
1039         /* double check that we don't free the table twice */
1040         if (!ttm->sg->sgl)
1041                 return;
1042
1043         /* unmap the pages mapped to the device */
1044         dma_unmap_sgtable(adev->dev, ttm->sg, direction, 0);
1045         sg_free_table(ttm->sg);
1046
1047 #if IS_ENABLED(CONFIG_DRM_AMDGPU_USERPTR)
1048         if (gtt->range) {
1049                 unsigned long i;
1050
1051                 for (i = 0; i < ttm->num_pages; i++) {
1052                         if (ttm->pages[i] !=
1053                             hmm_pfn_to_page(gtt->range->hmm_pfns[i]))
1054                                 break;
1055                 }
1056
1057                 WARN((i == ttm->num_pages), "Missing get_user_page_done\n");
1058         }
1059 #endif
1060 }
1061
1062 static int amdgpu_ttm_gart_bind(struct amdgpu_device *adev,
1063                                 struct ttm_buffer_object *tbo,
1064                                 uint64_t flags)
1065 {
1066         struct amdgpu_bo *abo = ttm_to_amdgpu_bo(tbo);
1067         struct ttm_tt *ttm = tbo->ttm;
1068         struct amdgpu_ttm_tt *gtt = (void *)ttm;
1069         int r;
1070
1071         if (amdgpu_bo_encrypted(abo))
1072                 flags |= AMDGPU_PTE_TMZ;
1073
1074         if (abo->flags & AMDGPU_GEM_CREATE_CP_MQD_GFX9) {
1075                 uint64_t page_idx = 1;
1076
1077                 r = amdgpu_gart_bind(adev, gtt->offset, page_idx,
1078                                 ttm->pages, gtt->ttm.dma_address, flags);
1079                 if (r)
1080                         goto gart_bind_fail;
1081
1082                 /* The memory type of the first page defaults to UC. Now
1083                  * modify the memory type to NC from the second page of
1084                  * the BO onward.
1085                  */
1086                 flags &= ~AMDGPU_PTE_MTYPE_VG10_MASK;
1087                 flags |= AMDGPU_PTE_MTYPE_VG10(AMDGPU_MTYPE_NC);
1088
1089                 r = amdgpu_gart_bind(adev,
1090                                 gtt->offset + (page_idx << PAGE_SHIFT),
1091                                 ttm->num_pages - page_idx,
1092                                 &ttm->pages[page_idx],
1093                                 &(gtt->ttm.dma_address[page_idx]), flags);
1094         } else {
1095                 r = amdgpu_gart_bind(adev, gtt->offset, ttm->num_pages,
1096                                      ttm->pages, gtt->ttm.dma_address, flags);
1097         }
1098
1099 gart_bind_fail:
1100         if (r)
1101                 DRM_ERROR("failed to bind %lu pages at 0x%08llX\n",
1102                           ttm->num_pages, gtt->offset);
1103
1104         return r;
1105 }
1106
1107 /**
1108  * amdgpu_ttm_backend_bind - Bind GTT memory
1109  *
1110  * Called by ttm_tt_bind() on behalf of ttm_bo_handle_move_mem().
1111  * This handles binding GTT memory to the device address space.
1112  */
1113 static int amdgpu_ttm_backend_bind(struct ttm_tt *ttm,
1114                                    struct ttm_resource *bo_mem)
1115 {
1116         struct amdgpu_device *adev = amdgpu_ttm_adev(ttm->bdev);
1117         struct amdgpu_ttm_tt *gtt = (void*)ttm;
1118         uint64_t flags;
1119         int r = 0;
1120
1121         if (gtt->userptr) {
1122                 r = amdgpu_ttm_tt_pin_userptr(ttm);
1123                 if (r) {
1124                         DRM_ERROR("failed to pin userptr\n");
1125                         return r;
1126                 }
1127         }
1128         if (!ttm->num_pages) {
1129                 WARN(1, "nothing to bind %lu pages for mreg %p back %p!\n",
1130                      ttm->num_pages, bo_mem, ttm);
1131         }
1132
1133         if (bo_mem->mem_type == AMDGPU_PL_GDS ||
1134             bo_mem->mem_type == AMDGPU_PL_GWS ||
1135             bo_mem->mem_type == AMDGPU_PL_OA)
1136                 return -EINVAL;
1137
1138         if (!amdgpu_gtt_mgr_has_gart_addr(bo_mem)) {
1139                 gtt->offset = AMDGPU_BO_INVALID_OFFSET;
1140                 return 0;
1141         }
1142
1143         /* compute PTE flags relevant to this BO memory */
1144         flags = amdgpu_ttm_tt_pte_flags(adev, ttm, bo_mem);
1145
1146         /* bind pages into GART page tables */
1147         gtt->offset = (u64)bo_mem->start << PAGE_SHIFT;
1148         r = amdgpu_gart_bind(adev, gtt->offset, ttm->num_pages,
1149                 ttm->pages, gtt->ttm.dma_address, flags);
1150
1151         if (r)
1152                 DRM_ERROR("failed to bind %lu pages at 0x%08llX\n",
1153                           ttm->num_pages, gtt->offset);
1154         return r;
1155 }
1156
1157 /**
1158  * amdgpu_ttm_alloc_gart - Allocate GART memory for buffer object
1159  */
1160 int amdgpu_ttm_alloc_gart(struct ttm_buffer_object *bo)
1161 {
1162         struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev);
1163         struct ttm_operation_ctx ctx = { false, false };
1164         struct amdgpu_ttm_tt *gtt = (void*)bo->ttm;
1165         struct ttm_resource tmp;
1166         struct ttm_placement placement;
1167         struct ttm_place placements;
1168         uint64_t addr, flags;
1169         int r;
1170
1171         if (bo->mem.start != AMDGPU_BO_INVALID_OFFSET)
1172                 return 0;
1173
1174         addr = amdgpu_gmc_agp_addr(bo);
1175         if (addr != AMDGPU_BO_INVALID_OFFSET) {
1176                 bo->mem.start = addr >> PAGE_SHIFT;
1177         } else {
1178
1179                 /* allocate GART space */
1180                 tmp = bo->mem;
1181                 tmp.mm_node = NULL;
1182                 placement.num_placement = 1;
1183                 placement.placement = &placements;
1184                 placement.num_busy_placement = 1;
1185                 placement.busy_placement = &placements;
1186                 placements.fpfn = 0;
1187                 placements.lpfn = adev->gmc.gart_size >> PAGE_SHIFT;
1188                 placements.flags = (bo->mem.placement & ~TTM_PL_MASK_MEM) |
1189                         TTM_PL_FLAG_TT;
1190
1191                 r = ttm_bo_mem_space(bo, &placement, &tmp, &ctx);
1192                 if (unlikely(r))
1193                         return r;
1194
1195                 /* compute PTE flags for this buffer object */
1196                 flags = amdgpu_ttm_tt_pte_flags(adev, bo->ttm, &tmp);
1197
1198                 /* Bind pages */
1199                 gtt->offset = (u64)tmp.start << PAGE_SHIFT;
1200                 r = amdgpu_ttm_gart_bind(adev, bo, flags);
1201                 if (unlikely(r)) {
1202                         ttm_resource_free(bo, &tmp);
1203                         return r;
1204                 }
1205
1206                 ttm_resource_free(bo, &bo->mem);
1207                 bo->mem = tmp;
1208         }
1209
1210         return 0;
1211 }
1212
1213 /**
1214  * amdgpu_ttm_recover_gart - Rebind GTT pages
1215  *
1216  * Called by amdgpu_gtt_mgr_recover() from amdgpu_device_reset() to
1217  * rebind GTT pages during a GPU reset.
1218  */
1219 int amdgpu_ttm_recover_gart(struct ttm_buffer_object *tbo)
1220 {
1221         struct amdgpu_device *adev = amdgpu_ttm_adev(tbo->bdev);
1222         uint64_t flags;
1223         int r;
1224
1225         if (!tbo->ttm)
1226                 return 0;
1227
1228         flags = amdgpu_ttm_tt_pte_flags(adev, tbo->ttm, &tbo->mem);
1229         r = amdgpu_ttm_gart_bind(adev, tbo, flags);
1230
1231         return r;
1232 }
1233
1234 /**
1235  * amdgpu_ttm_backend_unbind - Unbind GTT mapped pages
1236  *
1237  * Called by ttm_tt_unbind() on behalf of ttm_bo_move_ttm() and
1238  * ttm_tt_destroy().
1239  */
1240 static void amdgpu_ttm_backend_unbind(struct ttm_tt *ttm)
1241 {
1242         struct amdgpu_device *adev = amdgpu_ttm_adev(ttm->bdev);
1243         struct amdgpu_ttm_tt *gtt = (void *)ttm;
1244         int r;
1245
1246         /* if the pages have userptr pinning then clear that first */
1247         if (gtt->userptr)
1248                 amdgpu_ttm_tt_unpin_userptr(ttm);
1249
1250         if (gtt->offset == AMDGPU_BO_INVALID_OFFSET)
1251                 return;
1252
1253         /* unbind shouldn't be done for GDS/GWS/OA in ttm_bo_clean_mm */
1254         r = amdgpu_gart_unbind(adev, gtt->offset, ttm->num_pages);
1255         if (r)
1256                 DRM_ERROR("failed to unbind %lu pages at 0x%08llX\n",
1257                           gtt->ttm.ttm.num_pages, gtt->offset);
1258 }
1259
1260 static void amdgpu_ttm_backend_destroy(struct ttm_tt *ttm)
1261 {
1262         struct amdgpu_ttm_tt *gtt = (void *)ttm;
1263
1264         if (gtt->usertask)
1265                 put_task_struct(gtt->usertask);
1266
1267         ttm_dma_tt_fini(&gtt->ttm);
1268         kfree(gtt);
1269 }
1270
1271 static struct ttm_backend_func amdgpu_backend_func = {
1272         .bind = &amdgpu_ttm_backend_bind,
1273         .unbind = &amdgpu_ttm_backend_unbind,
1274         .destroy = &amdgpu_ttm_backend_destroy,
1275 };
1276
1277 /**
1278  * amdgpu_ttm_tt_create - Create a ttm_tt object for a given BO
1279  *
1280  * @bo: The buffer object to create a GTT ttm_tt object around
1281  *
1282  * Called by ttm_tt_create().
1283  */
1284 static struct ttm_tt *amdgpu_ttm_tt_create(struct ttm_buffer_object *bo,
1285                                            uint32_t page_flags)
1286 {
1287         struct amdgpu_ttm_tt *gtt;
1288
1289         gtt = kzalloc(sizeof(struct amdgpu_ttm_tt), GFP_KERNEL);
1290         if (gtt == NULL) {
1291                 return NULL;
1292         }
1293         gtt->ttm.ttm.func = &amdgpu_backend_func;
1294         gtt->gobj = &bo->base;
1295
1296         /* allocate space for the uninitialized page entries */
1297         if (ttm_sg_tt_init(&gtt->ttm, bo, page_flags)) {
1298                 kfree(gtt);
1299                 return NULL;
1300         }
1301         return &gtt->ttm.ttm;
1302 }
1303
1304 /**
1305  * amdgpu_ttm_tt_populate - Map GTT pages visible to the device
1306  *
1307  * Map the pages of a ttm_tt object to an address space visible
1308  * to the underlying device.
1309  */
1310 static int amdgpu_ttm_tt_populate(struct ttm_tt *ttm,
1311                         struct ttm_operation_ctx *ctx)
1312 {
1313         struct amdgpu_device *adev = amdgpu_ttm_adev(ttm->bdev);
1314         struct amdgpu_ttm_tt *gtt = (void *)ttm;
1315
1316         /* user pages are bound by amdgpu_ttm_tt_pin_userptr() */
1317         if (gtt && gtt->userptr) {
1318                 ttm->sg = kzalloc(sizeof(struct sg_table), GFP_KERNEL);
1319                 if (!ttm->sg)
1320                         return -ENOMEM;
1321
1322                 ttm->page_flags |= TTM_PAGE_FLAG_SG;
1323                 ttm->state = tt_unbound;
1324                 return 0;
1325         }
1326
1327         if (ttm->page_flags & TTM_PAGE_FLAG_SG) {
1328                 if (!ttm->sg) {
1329                         struct dma_buf_attachment *attach;
1330                         struct sg_table *sgt;
1331
1332                         attach = gtt->gobj->import_attach;
1333                         sgt = dma_buf_map_attachment(attach, DMA_BIDIRECTIONAL);
1334                         if (IS_ERR(sgt))
1335                                 return PTR_ERR(sgt);
1336
1337                         ttm->sg = sgt;
1338                 }
1339
1340                 drm_prime_sg_to_page_addr_arrays(ttm->sg, ttm->pages,
1341                                                  gtt->ttm.dma_address,
1342                                                  ttm->num_pages);
1343                 ttm->state = tt_unbound;
1344                 return 0;
1345         }
1346
1347 #ifdef CONFIG_SWIOTLB
1348         if (adev->need_swiotlb && swiotlb_nr_tbl()) {
1349                 return ttm_dma_populate(&gtt->ttm, adev->dev, ctx);
1350         }
1351 #endif
1352
1353         /* fall back to generic helper to populate the page array
1354          * and map them to the device */
1355         return ttm_populate_and_map_pages(adev->dev, &gtt->ttm, ctx);
1356 }
1357
1358 /**
1359  * amdgpu_ttm_tt_unpopulate - unmap GTT pages and unpopulate page arrays
1360  *
1361  * Unmaps pages of a ttm_tt object from the device address space and
1362  * unpopulates the page array backing it.
1363  */
1364 static void amdgpu_ttm_tt_unpopulate(struct ttm_tt *ttm)
1365 {
1366         struct amdgpu_ttm_tt *gtt = (void *)ttm;
1367         struct amdgpu_device *adev;
1368
1369         if (gtt && gtt->userptr) {
1370                 amdgpu_ttm_tt_set_user_pages(ttm, NULL);
1371                 kfree(ttm->sg);
1372                 ttm->page_flags &= ~TTM_PAGE_FLAG_SG;
1373                 return;
1374         }
1375
1376         if (ttm->sg && gtt->gobj->import_attach) {
1377                 struct dma_buf_attachment *attach;
1378
1379                 attach = gtt->gobj->import_attach;
1380                 dma_buf_unmap_attachment(attach, ttm->sg, DMA_BIDIRECTIONAL);
1381                 ttm->sg = NULL;
1382                 return;
1383         }
1384
1385         if (ttm->page_flags & TTM_PAGE_FLAG_SG)
1386                 return;
1387
1388         adev = amdgpu_ttm_adev(ttm->bdev);
1389
1390 #ifdef CONFIG_SWIOTLB
1391         if (adev->need_swiotlb && swiotlb_nr_tbl()) {
1392                 ttm_dma_unpopulate(&gtt->ttm, adev->dev);
1393                 return;
1394         }
1395 #endif
1396
1397         /* fall back to generic helper to unmap and unpopulate array */
1398         ttm_unmap_and_unpopulate_pages(adev->dev, &gtt->ttm);
1399 }
1400
1401 /**
1402  * amdgpu_ttm_tt_set_userptr - Initialize userptr GTT ttm_tt for the current
1403  * task
1404  *
1405  * @bo: The ttm_buffer_object to bind this userptr to
1406  * @addr:  The address in the current tasks VM space to use
1407  * @flags: Requirements of userptr object.
1408  *
1409  * Called by amdgpu_gem_userptr_ioctl() to bind userptr pages
1410  * to current task
1411  */
1412 int amdgpu_ttm_tt_set_userptr(struct ttm_buffer_object *bo,
1413                               uint64_t addr, uint32_t flags)
1414 {
1415         struct amdgpu_ttm_tt *gtt;
1416
1417         if (!bo->ttm) {
1418                 /* TODO: We want a separate TTM object type for userptrs */
1419                 bo->ttm = amdgpu_ttm_tt_create(bo, 0);
1420                 if (bo->ttm == NULL)
1421                         return -ENOMEM;
1422         }
1423
1424         gtt = (void*)bo->ttm;
1425         gtt->userptr = addr;
1426         gtt->userflags = flags;
1427
1428         if (gtt->usertask)
1429                 put_task_struct(gtt->usertask);
1430         gtt->usertask = current->group_leader;
1431         get_task_struct(gtt->usertask);
1432
1433         return 0;
1434 }
1435
1436 /**
1437  * amdgpu_ttm_tt_get_usermm - Return memory manager for ttm_tt object
1438  */
1439 struct mm_struct *amdgpu_ttm_tt_get_usermm(struct ttm_tt *ttm)
1440 {
1441         struct amdgpu_ttm_tt *gtt = (void *)ttm;
1442
1443         if (gtt == NULL)
1444                 return NULL;
1445
1446         if (gtt->usertask == NULL)
1447                 return NULL;
1448
1449         return gtt->usertask->mm;
1450 }
1451
1452 /**
1453  * amdgpu_ttm_tt_affect_userptr - Determine if a ttm_tt object lays inside an
1454  * address range for the current task.
1455  *
1456  */
1457 bool amdgpu_ttm_tt_affect_userptr(struct ttm_tt *ttm, unsigned long start,
1458                                   unsigned long end)
1459 {
1460         struct amdgpu_ttm_tt *gtt = (void *)ttm;
1461         unsigned long size;
1462
1463         if (gtt == NULL || !gtt->userptr)
1464                 return false;
1465
1466         /* Return false if no part of the ttm_tt object lies within
1467          * the range
1468          */
1469         size = (unsigned long)gtt->ttm.ttm.num_pages * PAGE_SIZE;
1470         if (gtt->userptr > end || gtt->userptr + size <= start)
1471                 return false;
1472
1473         return true;
1474 }
1475
1476 /**
1477  * amdgpu_ttm_tt_is_userptr - Have the pages backing by userptr?
1478  */
1479 bool amdgpu_ttm_tt_is_userptr(struct ttm_tt *ttm)
1480 {
1481         struct amdgpu_ttm_tt *gtt = (void *)ttm;
1482
1483         if (gtt == NULL || !gtt->userptr)
1484                 return false;
1485
1486         return true;
1487 }
1488
1489 /**
1490  * amdgpu_ttm_tt_is_readonly - Is the ttm_tt object read only?
1491  */
1492 bool amdgpu_ttm_tt_is_readonly(struct ttm_tt *ttm)
1493 {
1494         struct amdgpu_ttm_tt *gtt = (void *)ttm;
1495
1496         if (gtt == NULL)
1497                 return false;
1498
1499         return !!(gtt->userflags & AMDGPU_GEM_USERPTR_READONLY);
1500 }
1501
1502 /**
1503  * amdgpu_ttm_tt_pde_flags - Compute PDE flags for ttm_tt object
1504  *
1505  * @ttm: The ttm_tt object to compute the flags for
1506  * @mem: The memory registry backing this ttm_tt object
1507  *
1508  * Figure out the flags to use for a VM PDE (Page Directory Entry).
1509  */
1510 uint64_t amdgpu_ttm_tt_pde_flags(struct ttm_tt *ttm, struct ttm_resource *mem)
1511 {
1512         uint64_t flags = 0;
1513
1514         if (mem && mem->mem_type != TTM_PL_SYSTEM)
1515                 flags |= AMDGPU_PTE_VALID;
1516
1517         if (mem && mem->mem_type == TTM_PL_TT) {
1518                 flags |= AMDGPU_PTE_SYSTEM;
1519
1520                 if (ttm->caching_state == tt_cached)
1521                         flags |= AMDGPU_PTE_SNOOPED;
1522         }
1523
1524         return flags;
1525 }
1526
1527 /**
1528  * amdgpu_ttm_tt_pte_flags - Compute PTE flags for ttm_tt object
1529  *
1530  * @ttm: The ttm_tt object to compute the flags for
1531  * @mem: The memory registry backing this ttm_tt object
1532
1533  * Figure out the flags to use for a VM PTE (Page Table Entry).
1534  */
1535 uint64_t amdgpu_ttm_tt_pte_flags(struct amdgpu_device *adev, struct ttm_tt *ttm,
1536                                  struct ttm_resource *mem)
1537 {
1538         uint64_t flags = amdgpu_ttm_tt_pde_flags(ttm, mem);
1539
1540         flags |= adev->gart.gart_pte_flags;
1541         flags |= AMDGPU_PTE_READABLE;
1542
1543         if (!amdgpu_ttm_tt_is_readonly(ttm))
1544                 flags |= AMDGPU_PTE_WRITEABLE;
1545
1546         return flags;
1547 }
1548
1549 /**
1550  * amdgpu_ttm_bo_eviction_valuable - Check to see if we can evict a buffer
1551  * object.
1552  *
1553  * Return true if eviction is sensible. Called by ttm_mem_evict_first() on
1554  * behalf of ttm_bo_mem_force_space() which tries to evict buffer objects until
1555  * it can find space for a new object and by ttm_bo_force_list_clean() which is
1556  * used to clean out a memory space.
1557  */
1558 static bool amdgpu_ttm_bo_eviction_valuable(struct ttm_buffer_object *bo,
1559                                             const struct ttm_place *place)
1560 {
1561         unsigned long num_pages = bo->mem.num_pages;
1562         struct drm_mm_node *node = bo->mem.mm_node;
1563         struct dma_resv_list *flist;
1564         struct dma_fence *f;
1565         int i;
1566
1567         if (bo->type == ttm_bo_type_kernel &&
1568             !amdgpu_vm_evictable(ttm_to_amdgpu_bo(bo)))
1569                 return false;
1570
1571         /* If bo is a KFD BO, check if the bo belongs to the current process.
1572          * If true, then return false as any KFD process needs all its BOs to
1573          * be resident to run successfully
1574          */
1575         flist = dma_resv_get_list(bo->base.resv);
1576         if (flist) {
1577                 for (i = 0; i < flist->shared_count; ++i) {
1578                         f = rcu_dereference_protected(flist->shared[i],
1579                                 dma_resv_held(bo->base.resv));
1580                         if (amdkfd_fence_check_mm(f, current->mm))
1581                                 return false;
1582                 }
1583         }
1584
1585         switch (bo->mem.mem_type) {
1586         case TTM_PL_TT:
1587                 if (amdgpu_bo_is_amdgpu_bo(bo) &&
1588                     amdgpu_bo_encrypted(ttm_to_amdgpu_bo(bo)))
1589                         return false;
1590                 return true;
1591
1592         case TTM_PL_VRAM:
1593                 /* Check each drm MM node individually */
1594                 while (num_pages) {
1595                         if (place->fpfn < (node->start + node->size) &&
1596                             !(place->lpfn && place->lpfn <= node->start))
1597                                 return true;
1598
1599                         num_pages -= node->size;
1600                         ++node;
1601                 }
1602                 return false;
1603
1604         default:
1605                 break;
1606         }
1607
1608         return ttm_bo_eviction_valuable(bo, place);
1609 }
1610
1611 /**
1612  * amdgpu_ttm_access_memory - Read or Write memory that backs a buffer object.
1613  *
1614  * @bo:  The buffer object to read/write
1615  * @offset:  Offset into buffer object
1616  * @buf:  Secondary buffer to write/read from
1617  * @len: Length in bytes of access
1618  * @write:  true if writing
1619  *
1620  * This is used to access VRAM that backs a buffer object via MMIO
1621  * access for debugging purposes.
1622  */
1623 static int amdgpu_ttm_access_memory(struct ttm_buffer_object *bo,
1624                                     unsigned long offset,
1625                                     void *buf, int len, int write)
1626 {
1627         struct amdgpu_bo *abo = ttm_to_amdgpu_bo(bo);
1628         struct amdgpu_device *adev = amdgpu_ttm_adev(abo->tbo.bdev);
1629         struct drm_mm_node *nodes;
1630         uint32_t value = 0;
1631         int ret = 0;
1632         uint64_t pos;
1633         unsigned long flags;
1634
1635         if (bo->mem.mem_type != TTM_PL_VRAM)
1636                 return -EIO;
1637
1638         pos = offset;
1639         nodes = amdgpu_find_mm_node(&abo->tbo.mem, &pos);
1640         pos += (nodes->start << PAGE_SHIFT);
1641
1642         while (len && pos < adev->gmc.mc_vram_size) {
1643                 uint64_t aligned_pos = pos & ~(uint64_t)3;
1644                 uint64_t bytes = 4 - (pos & 3);
1645                 uint32_t shift = (pos & 3) * 8;
1646                 uint32_t mask = 0xffffffff << shift;
1647
1648                 if (len < bytes) {
1649                         mask &= 0xffffffff >> (bytes - len) * 8;
1650                         bytes = len;
1651                 }
1652
1653                 if (mask != 0xffffffff) {
1654                         spin_lock_irqsave(&adev->mmio_idx_lock, flags);
1655                         WREG32_NO_KIQ(mmMM_INDEX, ((uint32_t)aligned_pos) | 0x80000000);
1656                         WREG32_NO_KIQ(mmMM_INDEX_HI, aligned_pos >> 31);
1657                         if (!write || mask != 0xffffffff)
1658                                 value = RREG32_NO_KIQ(mmMM_DATA);
1659                         if (write) {
1660                                 value &= ~mask;
1661                                 value |= (*(uint32_t *)buf << shift) & mask;
1662                                 WREG32_NO_KIQ(mmMM_DATA, value);
1663                         }
1664                         spin_unlock_irqrestore(&adev->mmio_idx_lock, flags);
1665                         if (!write) {
1666                                 value = (value & mask) >> shift;
1667                                 memcpy(buf, &value, bytes);
1668                         }
1669                 } else {
1670                         bytes = (nodes->start + nodes->size) << PAGE_SHIFT;
1671                         bytes = min(bytes - pos, (uint64_t)len & ~0x3ull);
1672
1673                         amdgpu_device_vram_access(adev, pos, (uint32_t *)buf,
1674                                                   bytes, write);
1675                 }
1676
1677                 ret += bytes;
1678                 buf = (uint8_t *)buf + bytes;
1679                 pos += bytes;
1680                 len -= bytes;
1681                 if (pos >= (nodes->start + nodes->size) << PAGE_SHIFT) {
1682                         ++nodes;
1683                         pos = (nodes->start << PAGE_SHIFT);
1684                 }
1685         }
1686
1687         return ret;
1688 }
1689
1690 static struct ttm_bo_driver amdgpu_bo_driver = {
1691         .ttm_tt_create = &amdgpu_ttm_tt_create,
1692         .ttm_tt_populate = &amdgpu_ttm_tt_populate,
1693         .ttm_tt_unpopulate = &amdgpu_ttm_tt_unpopulate,
1694         .eviction_valuable = amdgpu_ttm_bo_eviction_valuable,
1695         .evict_flags = &amdgpu_evict_flags,
1696         .move = &amdgpu_bo_move,
1697         .verify_access = &amdgpu_verify_access,
1698         .move_notify = &amdgpu_bo_move_notify,
1699         .release_notify = &amdgpu_bo_release_notify,
1700         .fault_reserve_notify = &amdgpu_bo_fault_reserve_notify,
1701         .io_mem_reserve = &amdgpu_ttm_io_mem_reserve,
1702         .io_mem_pfn = amdgpu_ttm_io_mem_pfn,
1703         .access_memory = &amdgpu_ttm_access_memory,
1704         .del_from_lru_notify = &amdgpu_vm_del_from_lru_notify
1705 };
1706
1707 /*
1708  * Firmware Reservation functions
1709  */
1710 /**
1711  * amdgpu_ttm_fw_reserve_vram_fini - free fw reserved vram
1712  *
1713  * @adev: amdgpu_device pointer
1714  *
1715  * free fw reserved vram if it has been reserved.
1716  */
1717 static void amdgpu_ttm_fw_reserve_vram_fini(struct amdgpu_device *adev)
1718 {
1719         amdgpu_bo_free_kernel(&adev->mman.fw_vram_usage_reserved_bo,
1720                 NULL, &adev->mman.fw_vram_usage_va);
1721 }
1722
1723 /**
1724  * amdgpu_ttm_fw_reserve_vram_init - create bo vram reservation from fw
1725  *
1726  * @adev: amdgpu_device pointer
1727  *
1728  * create bo vram reservation from fw.
1729  */
1730 static int amdgpu_ttm_fw_reserve_vram_init(struct amdgpu_device *adev)
1731 {
1732         uint64_t vram_size = adev->gmc.visible_vram_size;
1733
1734         adev->mman.fw_vram_usage_va = NULL;
1735         adev->mman.fw_vram_usage_reserved_bo = NULL;
1736
1737         if (adev->mman.fw_vram_usage_size == 0 ||
1738             adev->mman.fw_vram_usage_size > vram_size)
1739                 return 0;
1740
1741         return amdgpu_bo_create_kernel_at(adev,
1742                                           adev->mman.fw_vram_usage_start_offset,
1743                                           adev->mman.fw_vram_usage_size,
1744                                           AMDGPU_GEM_DOMAIN_VRAM,
1745                                           &adev->mman.fw_vram_usage_reserved_bo,
1746                                           &adev->mman.fw_vram_usage_va);
1747 }
1748
1749 /*
1750  * Memoy training reservation functions
1751  */
1752
1753 /**
1754  * amdgpu_ttm_training_reserve_vram_fini - free memory training reserved vram
1755  *
1756  * @adev: amdgpu_device pointer
1757  *
1758  * free memory training reserved vram if it has been reserved.
1759  */
1760 static int amdgpu_ttm_training_reserve_vram_fini(struct amdgpu_device *adev)
1761 {
1762         struct psp_memory_training_context *ctx = &adev->psp.mem_train_ctx;
1763
1764         ctx->init = PSP_MEM_TRAIN_NOT_SUPPORT;
1765         amdgpu_bo_free_kernel(&ctx->c2p_bo, NULL, NULL);
1766         ctx->c2p_bo = NULL;
1767
1768         return 0;
1769 }
1770
1771 static void amdgpu_ttm_training_data_block_init(struct amdgpu_device *adev)
1772 {
1773         struct psp_memory_training_context *ctx = &adev->psp.mem_train_ctx;
1774
1775         memset(ctx, 0, sizeof(*ctx));
1776
1777         ctx->c2p_train_data_offset =
1778                 ALIGN((adev->gmc.mc_vram_size - adev->mman.discovery_tmr_size - SZ_1M), SZ_1M);
1779         ctx->p2c_train_data_offset =
1780                 (adev->gmc.mc_vram_size - GDDR6_MEM_TRAINING_OFFSET);
1781         ctx->train_data_size =
1782                 GDDR6_MEM_TRAINING_DATA_SIZE_IN_BYTES;
1783
1784         DRM_DEBUG("train_data_size:%llx,p2c_train_data_offset:%llx,c2p_train_data_offset:%llx.\n",
1785                         ctx->train_data_size,
1786                         ctx->p2c_train_data_offset,
1787                         ctx->c2p_train_data_offset);
1788 }
1789
1790 /*
1791  * reserve TMR memory at the top of VRAM which holds
1792  * IP Discovery data and is protected by PSP.
1793  */
1794 static int amdgpu_ttm_reserve_tmr(struct amdgpu_device *adev)
1795 {
1796         int ret;
1797         struct psp_memory_training_context *ctx = &adev->psp.mem_train_ctx;
1798         bool mem_train_support = false;
1799
1800         if (!amdgpu_sriov_vf(adev)) {
1801                 ret = amdgpu_mem_train_support(adev);
1802                 if (ret == 1)
1803                         mem_train_support = true;
1804                 else if (ret == -1)
1805                         return -EINVAL;
1806                 else
1807                         DRM_DEBUG("memory training does not support!\n");
1808         }
1809
1810         /*
1811          * Query reserved tmr size through atom firmwareinfo for Sienna_Cichlid and onwards for all
1812          * the use cases (IP discovery/G6 memory training/profiling/diagnostic data.etc)
1813          *
1814          * Otherwise, fallback to legacy approach to check and reserve tmr block for ip
1815          * discovery data and G6 memory training data respectively
1816          */
1817         adev->mman.discovery_tmr_size =
1818                 amdgpu_atomfirmware_get_fw_reserved_fb_size(adev);
1819         if (!adev->mman.discovery_tmr_size)
1820                 adev->mman.discovery_tmr_size = DISCOVERY_TMR_OFFSET;
1821
1822         if (mem_train_support) {
1823                 /* reserve vram for mem train according to TMR location */
1824                 amdgpu_ttm_training_data_block_init(adev);
1825                 ret = amdgpu_bo_create_kernel_at(adev,
1826                                          ctx->c2p_train_data_offset,
1827                                          ctx->train_data_size,
1828                                          AMDGPU_GEM_DOMAIN_VRAM,
1829                                          &ctx->c2p_bo,
1830                                          NULL);
1831                 if (ret) {
1832                         DRM_ERROR("alloc c2p_bo failed(%d)!\n", ret);
1833                         amdgpu_ttm_training_reserve_vram_fini(adev);
1834                         return ret;
1835                 }
1836                 ctx->init = PSP_MEM_TRAIN_RESERVE_SUCCESS;
1837         }
1838
1839         ret = amdgpu_bo_create_kernel_at(adev,
1840                                 adev->gmc.real_vram_size - adev->mman.discovery_tmr_size,
1841                                 adev->mman.discovery_tmr_size,
1842                                 AMDGPU_GEM_DOMAIN_VRAM,
1843                                 &adev->mman.discovery_memory,
1844                                 NULL);
1845         if (ret) {
1846                 DRM_ERROR("alloc tmr failed(%d)!\n", ret);
1847                 amdgpu_bo_free_kernel(&adev->mman.discovery_memory, NULL, NULL);
1848                 return ret;
1849         }
1850
1851         return 0;
1852 }
1853
1854 /**
1855  * amdgpu_ttm_init - Init the memory management (ttm) as well as various
1856  * gtt/vram related fields.
1857  *
1858  * This initializes all of the memory space pools that the TTM layer
1859  * will need such as the GTT space (system memory mapped to the device),
1860  * VRAM (on-board memory), and on-chip memories (GDS, GWS, OA) which
1861  * can be mapped per VMID.
1862  */
1863 int amdgpu_ttm_init(struct amdgpu_device *adev)
1864 {
1865         uint64_t gtt_size;
1866         int r;
1867         u64 vis_vram_limit;
1868
1869         mutex_init(&adev->mman.gtt_window_lock);
1870
1871         /* No others user of address space so set it to 0 */
1872         r = ttm_bo_device_init(&adev->mman.bdev,
1873                                &amdgpu_bo_driver,
1874                                adev_to_drm(adev)->anon_inode->i_mapping,
1875                                adev_to_drm(adev)->vma_offset_manager,
1876                                dma_addressing_limited(adev->dev));
1877         if (r) {
1878                 DRM_ERROR("failed initializing buffer object driver(%d).\n", r);
1879                 return r;
1880         }
1881         adev->mman.initialized = true;
1882
1883         /* We opt to avoid OOM on system pages allocations */
1884         adev->mman.bdev.no_retry = true;
1885
1886         /* Initialize VRAM pool with all of VRAM divided into pages */
1887         r = amdgpu_vram_mgr_init(adev);
1888         if (r) {
1889                 DRM_ERROR("Failed initializing VRAM heap.\n");
1890                 return r;
1891         }
1892
1893         /* Reduce size of CPU-visible VRAM if requested */
1894         vis_vram_limit = (u64)amdgpu_vis_vram_limit * 1024 * 1024;
1895         if (amdgpu_vis_vram_limit > 0 &&
1896             vis_vram_limit <= adev->gmc.visible_vram_size)
1897                 adev->gmc.visible_vram_size = vis_vram_limit;
1898
1899         /* Change the size here instead of the init above so only lpfn is affected */
1900         amdgpu_ttm_set_buffer_funcs_status(adev, false);
1901 #ifdef CONFIG_64BIT
1902         adev->mman.aper_base_kaddr = ioremap_wc(adev->gmc.aper_base,
1903                                                 adev->gmc.visible_vram_size);
1904 #endif
1905
1906         /*
1907          *The reserved vram for firmware must be pinned to the specified
1908          *place on the VRAM, so reserve it early.
1909          */
1910         r = amdgpu_ttm_fw_reserve_vram_init(adev);
1911         if (r) {
1912                 return r;
1913         }
1914
1915         /*
1916          * only NAVI10 and onwards ASIC support for IP discovery.
1917          * If IP discovery enabled, a block of memory should be
1918          * reserved for IP discovey.
1919          */
1920         if (adev->mman.discovery_bin) {
1921                 r = amdgpu_ttm_reserve_tmr(adev);
1922                 if (r)
1923                         return r;
1924         }
1925
1926         /* allocate memory as required for VGA
1927          * This is used for VGA emulation and pre-OS scanout buffers to
1928          * avoid display artifacts while transitioning between pre-OS
1929          * and driver.  */
1930         r = amdgpu_bo_create_kernel_at(adev, 0, adev->mman.stolen_vga_size,
1931                                        AMDGPU_GEM_DOMAIN_VRAM,
1932                                        &adev->mman.stolen_vga_memory,
1933                                        NULL);
1934         if (r)
1935                 return r;
1936         r = amdgpu_bo_create_kernel_at(adev, adev->mman.stolen_vga_size,
1937                                        adev->mman.stolen_extended_size,
1938                                        AMDGPU_GEM_DOMAIN_VRAM,
1939                                        &adev->mman.stolen_extended_memory,
1940                                        NULL);
1941         if (r)
1942                 return r;
1943
1944         DRM_INFO("amdgpu: %uM of VRAM memory ready\n",
1945                  (unsigned) (adev->gmc.real_vram_size / (1024 * 1024)));
1946
1947         /* Compute GTT size, either bsaed on 3/4th the size of RAM size
1948          * or whatever the user passed on module init */
1949         if (amdgpu_gtt_size == -1) {
1950                 struct sysinfo si;
1951
1952                 si_meminfo(&si);
1953                 gtt_size = min(max((AMDGPU_DEFAULT_GTT_SIZE_MB << 20),
1954                                adev->gmc.mc_vram_size),
1955                                ((uint64_t)si.totalram * si.mem_unit * 3/4));
1956         }
1957         else
1958                 gtt_size = (uint64_t)amdgpu_gtt_size << 20;
1959
1960         /* Initialize GTT memory pool */
1961         r = amdgpu_gtt_mgr_init(adev, gtt_size);
1962         if (r) {
1963                 DRM_ERROR("Failed initializing GTT heap.\n");
1964                 return r;
1965         }
1966         DRM_INFO("amdgpu: %uM of GTT memory ready.\n",
1967                  (unsigned)(gtt_size / (1024 * 1024)));
1968
1969         /* Initialize various on-chip memory pools */
1970         r = amdgpu_ttm_init_on_chip(adev, AMDGPU_PL_GDS, adev->gds.gds_size);
1971         if (r) {
1972                 DRM_ERROR("Failed initializing GDS heap.\n");
1973                 return r;
1974         }
1975
1976         r = amdgpu_ttm_init_on_chip(adev, AMDGPU_PL_GWS, adev->gds.gws_size);
1977         if (r) {
1978                 DRM_ERROR("Failed initializing gws heap.\n");
1979                 return r;
1980         }
1981
1982         r = amdgpu_ttm_init_on_chip(adev, AMDGPU_PL_OA, adev->gds.oa_size);
1983         if (r) {
1984                 DRM_ERROR("Failed initializing oa heap.\n");
1985                 return r;
1986         }
1987
1988         return 0;
1989 }
1990
1991 /**
1992  * amdgpu_ttm_late_init - Handle any late initialization for amdgpu_ttm
1993  */
1994 void amdgpu_ttm_late_init(struct amdgpu_device *adev)
1995 {
1996         /* return the VGA stolen memory (if any) back to VRAM */
1997         if (!adev->mman.keep_stolen_vga_memory)
1998                 amdgpu_bo_free_kernel(&adev->mman.stolen_vga_memory, NULL, NULL);
1999         amdgpu_bo_free_kernel(&adev->mman.stolen_extended_memory, NULL, NULL);
2000 }
2001
2002 /**
2003  * amdgpu_ttm_fini - De-initialize the TTM memory pools
2004  */
2005 void amdgpu_ttm_fini(struct amdgpu_device *adev)
2006 {
2007         if (!adev->mman.initialized)
2008                 return;
2009
2010         amdgpu_ttm_training_reserve_vram_fini(adev);
2011         /* return the stolen vga memory back to VRAM */
2012         if (adev->mman.keep_stolen_vga_memory)
2013                 amdgpu_bo_free_kernel(&adev->mman.stolen_vga_memory, NULL, NULL);
2014         /* return the IP Discovery TMR memory back to VRAM */
2015         amdgpu_bo_free_kernel(&adev->mman.discovery_memory, NULL, NULL);
2016         amdgpu_ttm_fw_reserve_vram_fini(adev);
2017
2018         if (adev->mman.aper_base_kaddr)
2019                 iounmap(adev->mman.aper_base_kaddr);
2020         adev->mman.aper_base_kaddr = NULL;
2021
2022         amdgpu_vram_mgr_fini(adev);
2023         amdgpu_gtt_mgr_fini(adev);
2024         ttm_range_man_fini(&adev->mman.bdev, AMDGPU_PL_GDS);
2025         ttm_range_man_fini(&adev->mman.bdev, AMDGPU_PL_GWS);
2026         ttm_range_man_fini(&adev->mman.bdev, AMDGPU_PL_OA);
2027         ttm_bo_device_release(&adev->mman.bdev);
2028         adev->mman.initialized = false;
2029         DRM_INFO("amdgpu: ttm finalized\n");
2030 }
2031
2032 /**
2033  * amdgpu_ttm_set_buffer_funcs_status - enable/disable use of buffer functions
2034  *
2035  * @adev: amdgpu_device pointer
2036  * @enable: true when we can use buffer functions.
2037  *
2038  * Enable/disable use of buffer functions during suspend/resume. This should
2039  * only be called at bootup or when userspace isn't running.
2040  */
2041 void amdgpu_ttm_set_buffer_funcs_status(struct amdgpu_device *adev, bool enable)
2042 {
2043         struct ttm_resource_manager *man = ttm_manager_type(&adev->mman.bdev, TTM_PL_VRAM);
2044         uint64_t size;
2045         int r;
2046
2047         if (!adev->mman.initialized || amdgpu_in_reset(adev) ||
2048             adev->mman.buffer_funcs_enabled == enable)
2049                 return;
2050
2051         if (enable) {
2052                 struct amdgpu_ring *ring;
2053                 struct drm_gpu_scheduler *sched;
2054
2055                 ring = adev->mman.buffer_funcs_ring;
2056                 sched = &ring->sched;
2057                 r = drm_sched_entity_init(&adev->mman.entity,
2058                                           DRM_SCHED_PRIORITY_KERNEL, &sched,
2059                                           1, NULL);
2060                 if (r) {
2061                         DRM_ERROR("Failed setting up TTM BO move entity (%d)\n",
2062                                   r);
2063                         return;
2064                 }
2065         } else {
2066                 drm_sched_entity_destroy(&adev->mman.entity);
2067                 dma_fence_put(man->move);
2068                 man->move = NULL;
2069         }
2070
2071         /* this just adjusts TTM size idea, which sets lpfn to the correct value */
2072         if (enable)
2073                 size = adev->gmc.real_vram_size;
2074         else
2075                 size = adev->gmc.visible_vram_size;
2076         man->size = size >> PAGE_SHIFT;
2077         adev->mman.buffer_funcs_enabled = enable;
2078 }
2079
2080 int amdgpu_mmap(struct file *filp, struct vm_area_struct *vma)
2081 {
2082         struct drm_file *file_priv = filp->private_data;
2083         struct amdgpu_device *adev = drm_to_adev(file_priv->minor->dev);
2084
2085         if (adev == NULL)
2086                 return -EINVAL;
2087
2088         return ttm_bo_mmap(filp, vma, &adev->mman.bdev);
2089 }
2090
2091 int amdgpu_copy_buffer(struct amdgpu_ring *ring, uint64_t src_offset,
2092                        uint64_t dst_offset, uint32_t byte_count,
2093                        struct dma_resv *resv,
2094                        struct dma_fence **fence, bool direct_submit,
2095                        bool vm_needs_flush, bool tmz)
2096 {
2097         enum amdgpu_ib_pool_type pool = direct_submit ? AMDGPU_IB_POOL_DIRECT :
2098                 AMDGPU_IB_POOL_DELAYED;
2099         struct amdgpu_device *adev = ring->adev;
2100         struct amdgpu_job *job;
2101
2102         uint32_t max_bytes;
2103         unsigned num_loops, num_dw;
2104         unsigned i;
2105         int r;
2106
2107         if (direct_submit && !ring->sched.ready) {
2108                 DRM_ERROR("Trying to move memory with ring turned off.\n");
2109                 return -EINVAL;
2110         }
2111
2112         max_bytes = adev->mman.buffer_funcs->copy_max_bytes;
2113         num_loops = DIV_ROUND_UP(byte_count, max_bytes);
2114         num_dw = ALIGN(num_loops * adev->mman.buffer_funcs->copy_num_dw, 8);
2115
2116         r = amdgpu_job_alloc_with_ib(adev, num_dw * 4, pool, &job);
2117         if (r)
2118                 return r;
2119
2120         if (vm_needs_flush) {
2121                 job->vm_pd_addr = amdgpu_gmc_pd_addr(adev->gart.bo);
2122                 job->vm_needs_flush = true;
2123         }
2124         if (resv) {
2125                 r = amdgpu_sync_resv(adev, &job->sync, resv,
2126                                      AMDGPU_SYNC_ALWAYS,
2127                                      AMDGPU_FENCE_OWNER_UNDEFINED);
2128                 if (r) {
2129                         DRM_ERROR("sync failed (%d).\n", r);
2130                         goto error_free;
2131                 }
2132         }
2133
2134         for (i = 0; i < num_loops; i++) {
2135                 uint32_t cur_size_in_bytes = min(byte_count, max_bytes);
2136
2137                 amdgpu_emit_copy_buffer(adev, &job->ibs[0], src_offset,
2138                                         dst_offset, cur_size_in_bytes, tmz);
2139
2140                 src_offset += cur_size_in_bytes;
2141                 dst_offset += cur_size_in_bytes;
2142                 byte_count -= cur_size_in_bytes;
2143         }
2144
2145         amdgpu_ring_pad_ib(ring, &job->ibs[0]);
2146         WARN_ON(job->ibs[0].length_dw > num_dw);
2147         if (direct_submit)
2148                 r = amdgpu_job_submit_direct(job, ring, fence);
2149         else
2150                 r = amdgpu_job_submit(job, &adev->mman.entity,
2151                                       AMDGPU_FENCE_OWNER_UNDEFINED, fence);
2152         if (r)
2153                 goto error_free;
2154
2155         return r;
2156
2157 error_free:
2158         amdgpu_job_free(job);
2159         DRM_ERROR("Error scheduling IBs (%d)\n", r);
2160         return r;
2161 }
2162
2163 int amdgpu_fill_buffer(struct amdgpu_bo *bo,
2164                        uint32_t src_data,
2165                        struct dma_resv *resv,
2166                        struct dma_fence **fence)
2167 {
2168         struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
2169         uint32_t max_bytes = adev->mman.buffer_funcs->fill_max_bytes;
2170         struct amdgpu_ring *ring = adev->mman.buffer_funcs_ring;
2171
2172         struct drm_mm_node *mm_node;
2173         unsigned long num_pages;
2174         unsigned int num_loops, num_dw;
2175
2176         struct amdgpu_job *job;
2177         int r;
2178
2179         if (!adev->mman.buffer_funcs_enabled) {
2180                 DRM_ERROR("Trying to clear memory with ring turned off.\n");
2181                 return -EINVAL;
2182         }
2183
2184         if (bo->tbo.mem.mem_type == TTM_PL_TT) {
2185                 r = amdgpu_ttm_alloc_gart(&bo->tbo);
2186                 if (r)
2187                         return r;
2188         }
2189
2190         num_pages = bo->tbo.num_pages;
2191         mm_node = bo->tbo.mem.mm_node;
2192         num_loops = 0;
2193         while (num_pages) {
2194                 uint64_t byte_count = mm_node->size << PAGE_SHIFT;
2195
2196                 num_loops += DIV_ROUND_UP_ULL(byte_count, max_bytes);
2197                 num_pages -= mm_node->size;
2198                 ++mm_node;
2199         }
2200         num_dw = num_loops * adev->mman.buffer_funcs->fill_num_dw;
2201
2202         /* for IB padding */
2203         num_dw += 64;
2204
2205         r = amdgpu_job_alloc_with_ib(adev, num_dw * 4, AMDGPU_IB_POOL_DELAYED,
2206                                      &job);
2207         if (r)
2208                 return r;
2209
2210         if (resv) {
2211                 r = amdgpu_sync_resv(adev, &job->sync, resv,
2212                                      AMDGPU_SYNC_ALWAYS,
2213                                      AMDGPU_FENCE_OWNER_UNDEFINED);
2214                 if (r) {
2215                         DRM_ERROR("sync failed (%d).\n", r);
2216                         goto error_free;
2217                 }
2218         }
2219
2220         num_pages = bo->tbo.num_pages;
2221         mm_node = bo->tbo.mem.mm_node;
2222
2223         while (num_pages) {
2224                 uint64_t byte_count = mm_node->size << PAGE_SHIFT;
2225                 uint64_t dst_addr;
2226
2227                 dst_addr = amdgpu_mm_node_addr(&bo->tbo, mm_node, &bo->tbo.mem);
2228                 while (byte_count) {
2229                         uint32_t cur_size_in_bytes = min_t(uint64_t, byte_count,
2230                                                            max_bytes);
2231
2232                         amdgpu_emit_fill_buffer(adev, &job->ibs[0], src_data,
2233                                                 dst_addr, cur_size_in_bytes);
2234
2235                         dst_addr += cur_size_in_bytes;
2236                         byte_count -= cur_size_in_bytes;
2237                 }
2238
2239                 num_pages -= mm_node->size;
2240                 ++mm_node;
2241         }
2242
2243         amdgpu_ring_pad_ib(ring, &job->ibs[0]);
2244         WARN_ON(job->ibs[0].length_dw > num_dw);
2245         r = amdgpu_job_submit(job, &adev->mman.entity,
2246                               AMDGPU_FENCE_OWNER_UNDEFINED, fence);
2247         if (r)
2248                 goto error_free;
2249
2250         return 0;
2251
2252 error_free:
2253         amdgpu_job_free(job);
2254         return r;
2255 }
2256
2257 #if defined(CONFIG_DEBUG_FS)
2258
2259 static int amdgpu_mm_dump_table(struct seq_file *m, void *data)
2260 {
2261         struct drm_info_node *node = (struct drm_info_node *)m->private;
2262         unsigned ttm_pl = (uintptr_t)node->info_ent->data;
2263         struct drm_device *dev = node->minor->dev;
2264         struct amdgpu_device *adev = drm_to_adev(dev);
2265         struct ttm_resource_manager *man = ttm_manager_type(&adev->mman.bdev, ttm_pl);
2266         struct drm_printer p = drm_seq_file_printer(m);
2267
2268         man->func->debug(man, &p);
2269         return 0;
2270 }
2271
2272 static const struct drm_info_list amdgpu_ttm_debugfs_list[] = {
2273         {"amdgpu_vram_mm", amdgpu_mm_dump_table, 0, (void *)TTM_PL_VRAM},
2274         {"amdgpu_gtt_mm", amdgpu_mm_dump_table, 0, (void *)TTM_PL_TT},
2275         {"amdgpu_gds_mm", amdgpu_mm_dump_table, 0, (void *)AMDGPU_PL_GDS},
2276         {"amdgpu_gws_mm", amdgpu_mm_dump_table, 0, (void *)AMDGPU_PL_GWS},
2277         {"amdgpu_oa_mm", amdgpu_mm_dump_table, 0, (void *)AMDGPU_PL_OA},
2278         {"ttm_page_pool", ttm_page_alloc_debugfs, 0, NULL},
2279 #ifdef CONFIG_SWIOTLB
2280         {"ttm_dma_page_pool", ttm_dma_page_alloc_debugfs, 0, NULL}
2281 #endif
2282 };
2283
2284 /**
2285  * amdgpu_ttm_vram_read - Linear read access to VRAM
2286  *
2287  * Accesses VRAM via MMIO for debugging purposes.
2288  */
2289 static ssize_t amdgpu_ttm_vram_read(struct file *f, char __user *buf,
2290                                     size_t size, loff_t *pos)
2291 {
2292         struct amdgpu_device *adev = file_inode(f)->i_private;
2293         ssize_t result = 0;
2294
2295         if (size & 0x3 || *pos & 0x3)
2296                 return -EINVAL;
2297
2298         if (*pos >= adev->gmc.mc_vram_size)
2299                 return -ENXIO;
2300
2301         size = min(size, (size_t)(adev->gmc.mc_vram_size - *pos));
2302         while (size) {
2303                 size_t bytes = min(size, AMDGPU_TTM_VRAM_MAX_DW_READ * 4);
2304                 uint32_t value[AMDGPU_TTM_VRAM_MAX_DW_READ];
2305
2306                 amdgpu_device_vram_access(adev, *pos, value, bytes, false);
2307                 if (copy_to_user(buf, value, bytes))
2308                         return -EFAULT;
2309
2310                 result += bytes;
2311                 buf += bytes;
2312                 *pos += bytes;
2313                 size -= bytes;
2314         }
2315
2316         return result;
2317 }
2318
2319 /**
2320  * amdgpu_ttm_vram_write - Linear write access to VRAM
2321  *
2322  * Accesses VRAM via MMIO for debugging purposes.
2323  */
2324 static ssize_t amdgpu_ttm_vram_write(struct file *f, const char __user *buf,
2325                                     size_t size, loff_t *pos)
2326 {
2327         struct amdgpu_device *adev = file_inode(f)->i_private;
2328         ssize_t result = 0;
2329         int r;
2330
2331         if (size & 0x3 || *pos & 0x3)
2332                 return -EINVAL;
2333
2334         if (*pos >= adev->gmc.mc_vram_size)
2335                 return -ENXIO;
2336
2337         while (size) {
2338                 unsigned long flags;
2339                 uint32_t value;
2340
2341                 if (*pos >= adev->gmc.mc_vram_size)
2342                         return result;
2343
2344                 r = get_user(value, (uint32_t *)buf);
2345                 if (r)
2346                         return r;
2347
2348                 spin_lock_irqsave(&adev->mmio_idx_lock, flags);
2349                 WREG32_NO_KIQ(mmMM_INDEX, ((uint32_t)*pos) | 0x80000000);
2350                 WREG32_NO_KIQ(mmMM_INDEX_HI, *pos >> 31);
2351                 WREG32_NO_KIQ(mmMM_DATA, value);
2352                 spin_unlock_irqrestore(&adev->mmio_idx_lock, flags);
2353
2354                 result += 4;
2355                 buf += 4;
2356                 *pos += 4;
2357                 size -= 4;
2358         }
2359
2360         return result;
2361 }
2362
2363 static const struct file_operations amdgpu_ttm_vram_fops = {
2364         .owner = THIS_MODULE,
2365         .read = amdgpu_ttm_vram_read,
2366         .write = amdgpu_ttm_vram_write,
2367         .llseek = default_llseek,
2368 };
2369
2370 #ifdef CONFIG_DRM_AMDGPU_GART_DEBUGFS
2371
2372 /**
2373  * amdgpu_ttm_gtt_read - Linear read access to GTT memory
2374  */
2375 static ssize_t amdgpu_ttm_gtt_read(struct file *f, char __user *buf,
2376                                    size_t size, loff_t *pos)
2377 {
2378         struct amdgpu_device *adev = file_inode(f)->i_private;
2379         ssize_t result = 0;
2380         int r;
2381
2382         while (size) {
2383                 loff_t p = *pos / PAGE_SIZE;
2384                 unsigned off = *pos & ~PAGE_MASK;
2385                 size_t cur_size = min_t(size_t, size, PAGE_SIZE - off);
2386                 struct page *page;
2387                 void *ptr;
2388
2389                 if (p >= adev->gart.num_cpu_pages)
2390                         return result;
2391
2392                 page = adev->gart.pages[p];
2393                 if (page) {
2394                         ptr = kmap(page);
2395                         ptr += off;
2396
2397                         r = copy_to_user(buf, ptr, cur_size);
2398                         kunmap(adev->gart.pages[p]);
2399                 } else
2400                         r = clear_user(buf, cur_size);
2401
2402                 if (r)
2403                         return -EFAULT;
2404
2405                 result += cur_size;
2406                 buf += cur_size;
2407                 *pos += cur_size;
2408                 size -= cur_size;
2409         }
2410
2411         return result;
2412 }
2413
2414 static const struct file_operations amdgpu_ttm_gtt_fops = {
2415         .owner = THIS_MODULE,
2416         .read = amdgpu_ttm_gtt_read,
2417         .llseek = default_llseek
2418 };
2419
2420 #endif
2421
2422 /**
2423  * amdgpu_iomem_read - Virtual read access to GPU mapped memory
2424  *
2425  * This function is used to read memory that has been mapped to the
2426  * GPU and the known addresses are not physical addresses but instead
2427  * bus addresses (e.g., what you'd put in an IB or ring buffer).
2428  */
2429 static ssize_t amdgpu_iomem_read(struct file *f, char __user *buf,
2430                                  size_t size, loff_t *pos)
2431 {
2432         struct amdgpu_device *adev = file_inode(f)->i_private;
2433         struct iommu_domain *dom;
2434         ssize_t result = 0;
2435         int r;
2436
2437         /* retrieve the IOMMU domain if any for this device */
2438         dom = iommu_get_domain_for_dev(adev->dev);
2439
2440         while (size) {
2441                 phys_addr_t addr = *pos & PAGE_MASK;
2442                 loff_t off = *pos & ~PAGE_MASK;
2443                 size_t bytes = PAGE_SIZE - off;
2444                 unsigned long pfn;
2445                 struct page *p;
2446                 void *ptr;
2447
2448                 bytes = bytes < size ? bytes : size;
2449
2450                 /* Translate the bus address to a physical address.  If
2451                  * the domain is NULL it means there is no IOMMU active
2452                  * and the address translation is the identity
2453                  */
2454                 addr = dom ? iommu_iova_to_phys(dom, addr) : addr;
2455
2456                 pfn = addr >> PAGE_SHIFT;
2457                 if (!pfn_valid(pfn))
2458                         return -EPERM;
2459
2460                 p = pfn_to_page(pfn);
2461                 if (p->mapping != adev->mman.bdev.dev_mapping)
2462                         return -EPERM;
2463
2464                 ptr = kmap(p);
2465                 r = copy_to_user(buf, ptr + off, bytes);
2466                 kunmap(p);
2467                 if (r)
2468                         return -EFAULT;
2469
2470                 size -= bytes;
2471                 *pos += bytes;
2472                 result += bytes;
2473         }
2474
2475         return result;
2476 }
2477
2478 /**
2479  * amdgpu_iomem_write - Virtual write access to GPU mapped memory
2480  *
2481  * This function is used to write memory that has been mapped to the
2482  * GPU and the known addresses are not physical addresses but instead
2483  * bus addresses (e.g., what you'd put in an IB or ring buffer).
2484  */
2485 static ssize_t amdgpu_iomem_write(struct file *f, const char __user *buf,
2486                                  size_t size, loff_t *pos)
2487 {
2488         struct amdgpu_device *adev = file_inode(f)->i_private;
2489         struct iommu_domain *dom;
2490         ssize_t result = 0;
2491         int r;
2492
2493         dom = iommu_get_domain_for_dev(adev->dev);
2494
2495         while (size) {
2496                 phys_addr_t addr = *pos & PAGE_MASK;
2497                 loff_t off = *pos & ~PAGE_MASK;
2498                 size_t bytes = PAGE_SIZE - off;
2499                 unsigned long pfn;
2500                 struct page *p;
2501                 void *ptr;
2502
2503                 bytes = bytes < size ? bytes : size;
2504
2505                 addr = dom ? iommu_iova_to_phys(dom, addr) : addr;
2506
2507                 pfn = addr >> PAGE_SHIFT;
2508                 if (!pfn_valid(pfn))
2509                         return -EPERM;
2510
2511                 p = pfn_to_page(pfn);
2512                 if (p->mapping != adev->mman.bdev.dev_mapping)
2513                         return -EPERM;
2514
2515                 ptr = kmap(p);
2516                 r = copy_from_user(ptr + off, buf, bytes);
2517                 kunmap(p);
2518                 if (r)
2519                         return -EFAULT;
2520
2521                 size -= bytes;
2522                 *pos += bytes;
2523                 result += bytes;
2524         }
2525
2526         return result;
2527 }
2528
2529 static const struct file_operations amdgpu_ttm_iomem_fops = {
2530         .owner = THIS_MODULE,
2531         .read = amdgpu_iomem_read,
2532         .write = amdgpu_iomem_write,
2533         .llseek = default_llseek
2534 };
2535
2536 static const struct {
2537         char *name;
2538         const struct file_operations *fops;
2539         int domain;
2540 } ttm_debugfs_entries[] = {
2541         { "amdgpu_vram", &amdgpu_ttm_vram_fops, TTM_PL_VRAM },
2542 #ifdef CONFIG_DRM_AMDGPU_GART_DEBUGFS
2543         { "amdgpu_gtt", &amdgpu_ttm_gtt_fops, TTM_PL_TT },
2544 #endif
2545         { "amdgpu_iomem", &amdgpu_ttm_iomem_fops, TTM_PL_SYSTEM },
2546 };
2547
2548 #endif
2549
2550 int amdgpu_ttm_debugfs_init(struct amdgpu_device *adev)
2551 {
2552 #if defined(CONFIG_DEBUG_FS)
2553         unsigned count;
2554
2555         struct drm_minor *minor = adev_to_drm(adev)->primary;
2556         struct dentry *ent, *root = minor->debugfs_root;
2557
2558         for (count = 0; count < ARRAY_SIZE(ttm_debugfs_entries); count++) {
2559                 ent = debugfs_create_file(
2560                                 ttm_debugfs_entries[count].name,
2561                                 S_IFREG | S_IRUGO, root,
2562                                 adev,
2563                                 ttm_debugfs_entries[count].fops);
2564                 if (IS_ERR(ent))
2565                         return PTR_ERR(ent);
2566                 if (ttm_debugfs_entries[count].domain == TTM_PL_VRAM)
2567                         i_size_write(ent->d_inode, adev->gmc.mc_vram_size);
2568                 else if (ttm_debugfs_entries[count].domain == TTM_PL_TT)
2569                         i_size_write(ent->d_inode, adev->gmc.gart_size);
2570                 adev->mman.debugfs_entries[count] = ent;
2571         }
2572
2573         count = ARRAY_SIZE(amdgpu_ttm_debugfs_list);
2574
2575 #ifdef CONFIG_SWIOTLB
2576         if (!(adev->need_swiotlb && swiotlb_nr_tbl()))
2577                 --count;
2578 #endif
2579
2580         return amdgpu_debugfs_add_files(adev, amdgpu_ttm_debugfs_list, count);
2581 #else
2582         return 0;
2583 #endif
2584 }