2 * Copyright 2009 Jerome Glisse.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the
7 * "Software"), to deal in the Software without restriction, including
8 * without limitation the rights to use, copy, modify, merge, publish,
9 * distribute, sub license, and/or sell copies of the Software, and to
10 * permit persons to whom the Software is furnished to do so, subject to
11 * the following conditions:
13 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
14 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
15 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
16 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
17 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
18 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
19 * USE OR OTHER DEALINGS IN THE SOFTWARE.
21 * The above copyright notice and this permission notice (including the
22 * next paragraph) shall be included in all copies or substantial portions
28 * Jerome Glisse <glisse@freedesktop.org>
29 * Thomas Hellstrom <thomas-at-tungstengraphics-dot-com>
33 #include <linux/dma-mapping.h>
34 #include <linux/iommu.h>
35 #include <linux/hmm.h>
36 #include <linux/pagemap.h>
37 #include <linux/sched/task.h>
38 #include <linux/sched/mm.h>
39 #include <linux/seq_file.h>
40 #include <linux/slab.h>
41 #include <linux/swap.h>
42 #include <linux/swiotlb.h>
43 #include <linux/dma-buf.h>
44 #include <linux/sizes.h>
46 #include <drm/ttm/ttm_bo_api.h>
47 #include <drm/ttm/ttm_bo_driver.h>
48 #include <drm/ttm/ttm_placement.h>
49 #include <drm/ttm/ttm_module.h>
50 #include <drm/ttm/ttm_page_alloc.h>
52 #include <drm/drm_debugfs.h>
53 #include <drm/amdgpu_drm.h>
56 #include "amdgpu_object.h"
57 #include "amdgpu_trace.h"
58 #include "amdgpu_amdkfd.h"
59 #include "amdgpu_sdma.h"
60 #include "amdgpu_ras.h"
61 #include "amdgpu_atomfirmware.h"
62 #include "bif/bif_4_1_d.h"
64 #define AMDGPU_TTM_VRAM_MAX_DW_READ (size_t)128
66 static int amdgpu_ttm_init_on_chip(struct amdgpu_device *adev,
70 return ttm_range_man_init(&adev->mman.bdev, type,
71 TTM_PL_FLAG_UNCACHED, TTM_PL_FLAG_UNCACHED,
72 false, size >> PAGE_SHIFT);
76 * amdgpu_evict_flags - Compute placement flags
78 * @bo: The buffer object to evict
79 * @placement: Possible destination(s) for evicted BO
81 * Fill in placement data when ttm_bo_evict() is called
83 static void amdgpu_evict_flags(struct ttm_buffer_object *bo,
84 struct ttm_placement *placement)
86 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev);
87 struct amdgpu_bo *abo;
88 static const struct ttm_place placements = {
91 .mem_type = TTM_PL_SYSTEM,
92 .flags = TTM_PL_MASK_CACHING
95 /* Don't handle scatter gather BOs */
96 if (bo->type == ttm_bo_type_sg) {
97 placement->num_placement = 0;
98 placement->num_busy_placement = 0;
102 /* Object isn't an AMDGPU object so ignore */
103 if (!amdgpu_bo_is_amdgpu_bo(bo)) {
104 placement->placement = &placements;
105 placement->busy_placement = &placements;
106 placement->num_placement = 1;
107 placement->num_busy_placement = 1;
111 abo = ttm_to_amdgpu_bo(bo);
112 switch (bo->mem.mem_type) {
116 placement->num_placement = 0;
117 placement->num_busy_placement = 0;
121 if (!adev->mman.buffer_funcs_enabled) {
122 /* Move to system memory */
123 amdgpu_bo_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_CPU);
124 } else if (!amdgpu_gmc_vram_full_visible(&adev->gmc) &&
125 !(abo->flags & AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED) &&
126 amdgpu_bo_in_cpu_visible_vram(abo)) {
128 /* Try evicting to the CPU inaccessible part of VRAM
129 * first, but only set GTT as busy placement, so this
130 * BO will be evicted to GTT rather than causing other
131 * BOs to be evicted from VRAM
133 amdgpu_bo_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_VRAM |
134 AMDGPU_GEM_DOMAIN_GTT);
135 abo->placements[0].fpfn = adev->gmc.visible_vram_size >> PAGE_SHIFT;
136 abo->placements[0].lpfn = 0;
137 abo->placement.busy_placement = &abo->placements[1];
138 abo->placement.num_busy_placement = 1;
140 /* Move to GTT memory */
141 amdgpu_bo_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_GTT);
146 amdgpu_bo_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_CPU);
149 *placement = abo->placement;
153 * amdgpu_verify_access - Verify access for a mmap call
155 * @bo: The buffer object to map
156 * @filp: The file pointer from the process performing the mmap
158 * This is called by ttm_bo_mmap() to verify whether a process
159 * has the right to mmap a BO to their process space.
161 static int amdgpu_verify_access(struct ttm_buffer_object *bo, struct file *filp)
163 struct amdgpu_bo *abo = ttm_to_amdgpu_bo(bo);
166 * Don't verify access for KFD BOs. They don't have a GEM
167 * object associated with them.
172 if (amdgpu_ttm_tt_get_usermm(bo->ttm))
174 return drm_vma_node_verify_access(&abo->tbo.base.vma_node,
179 * amdgpu_mm_node_addr - Compute the GPU relative offset of a GTT buffer.
181 * @bo: The bo to assign the memory to.
182 * @mm_node: Memory manager node for drm allocator.
183 * @mem: The region where the bo resides.
186 static uint64_t amdgpu_mm_node_addr(struct ttm_buffer_object *bo,
187 struct drm_mm_node *mm_node,
188 struct ttm_resource *mem)
192 if (mm_node->start != AMDGPU_BO_INVALID_OFFSET) {
193 addr = mm_node->start << PAGE_SHIFT;
194 addr += amdgpu_ttm_domain_start(amdgpu_ttm_adev(bo->bdev),
201 * amdgpu_find_mm_node - Helper function finds the drm_mm_node corresponding to
202 * @offset. It also modifies the offset to be within the drm_mm_node returned
204 * @mem: The region where the bo resides.
205 * @offset: The offset that drm_mm_node is used for finding.
208 static struct drm_mm_node *amdgpu_find_mm_node(struct ttm_resource *mem,
211 struct drm_mm_node *mm_node = mem->mm_node;
213 while (*offset >= (mm_node->size << PAGE_SHIFT)) {
214 *offset -= (mm_node->size << PAGE_SHIFT);
221 * amdgpu_ttm_map_buffer - Map memory into the GART windows
222 * @bo: buffer object to map
223 * @mem: memory object to map
224 * @mm_node: drm_mm node object to map
225 * @num_pages: number of pages to map
226 * @offset: offset into @mm_node where to start
227 * @window: which GART window to use
228 * @ring: DMA ring to use for the copy
229 * @tmz: if we should setup a TMZ enabled mapping
230 * @addr: resulting address inside the MC address space
232 * Setup one of the GART windows to access a specific piece of memory or return
233 * the physical address for local memory.
235 static int amdgpu_ttm_map_buffer(struct ttm_buffer_object *bo,
236 struct ttm_resource *mem,
237 struct drm_mm_node *mm_node,
238 unsigned num_pages, uint64_t offset,
239 unsigned window, struct amdgpu_ring *ring,
240 bool tmz, uint64_t *addr)
242 struct amdgpu_device *adev = ring->adev;
243 struct amdgpu_job *job;
244 unsigned num_dw, num_bytes;
245 struct dma_fence *fence;
246 uint64_t src_addr, dst_addr;
252 BUG_ON(adev->mman.buffer_funcs->copy_max_bytes <
253 AMDGPU_GTT_MAX_TRANSFER_SIZE * 8);
255 /* Map only what can't be accessed directly */
256 if (!tmz && mem->start != AMDGPU_BO_INVALID_OFFSET) {
257 *addr = amdgpu_mm_node_addr(bo, mm_node, mem) + offset;
261 *addr = adev->gmc.gart_start;
262 *addr += (u64)window * AMDGPU_GTT_MAX_TRANSFER_SIZE *
263 AMDGPU_GPU_PAGE_SIZE;
264 *addr += offset & ~PAGE_MASK;
266 num_dw = ALIGN(adev->mman.buffer_funcs->copy_num_dw, 8);
267 num_bytes = num_pages * 8;
269 r = amdgpu_job_alloc_with_ib(adev, num_dw * 4 + num_bytes,
270 AMDGPU_IB_POOL_DELAYED, &job);
274 src_addr = num_dw * 4;
275 src_addr += job->ibs[0].gpu_addr;
277 dst_addr = amdgpu_bo_gpu_offset(adev->gart.bo);
278 dst_addr += window * AMDGPU_GTT_MAX_TRANSFER_SIZE * 8;
279 amdgpu_emit_copy_buffer(adev, &job->ibs[0], src_addr,
280 dst_addr, num_bytes, false);
282 amdgpu_ring_pad_ib(ring, &job->ibs[0]);
283 WARN_ON(job->ibs[0].length_dw > num_dw);
285 flags = amdgpu_ttm_tt_pte_flags(adev, bo->ttm, mem);
287 flags |= AMDGPU_PTE_TMZ;
289 cpu_addr = &job->ibs[0].ptr[num_dw];
291 if (mem->mem_type == TTM_PL_TT) {
292 struct ttm_dma_tt *dma;
293 dma_addr_t *dma_address;
295 dma = container_of(bo->ttm, struct ttm_dma_tt, ttm);
296 dma_address = &dma->dma_address[offset >> PAGE_SHIFT];
297 r = amdgpu_gart_map(adev, 0, num_pages, dma_address, flags,
302 dma_addr_t dma_address;
304 dma_address = (mm_node->start << PAGE_SHIFT) + offset;
305 dma_address += adev->vm_manager.vram_base_offset;
307 for (i = 0; i < num_pages; ++i) {
308 r = amdgpu_gart_map(adev, i << PAGE_SHIFT, 1,
309 &dma_address, flags, cpu_addr);
313 dma_address += PAGE_SIZE;
317 r = amdgpu_job_submit(job, &adev->mman.entity,
318 AMDGPU_FENCE_OWNER_UNDEFINED, &fence);
322 dma_fence_put(fence);
327 amdgpu_job_free(job);
332 * amdgpu_copy_ttm_mem_to_mem - Helper function for copy
333 * @adev: amdgpu device
334 * @src: buffer/address where to read from
335 * @dst: buffer/address where to write to
336 * @size: number of bytes to copy
337 * @tmz: if a secure copy should be used
338 * @resv: resv object to sync to
339 * @f: Returns the last fence if multiple jobs are submitted.
341 * The function copies @size bytes from {src->mem + src->offset} to
342 * {dst->mem + dst->offset}. src->bo and dst->bo could be same BO for a
343 * move and different for a BO to BO copy.
346 int amdgpu_ttm_copy_mem_to_mem(struct amdgpu_device *adev,
347 const struct amdgpu_copy_mem *src,
348 const struct amdgpu_copy_mem *dst,
349 uint64_t size, bool tmz,
350 struct dma_resv *resv,
351 struct dma_fence **f)
353 const uint32_t GTT_MAX_BYTES = (AMDGPU_GTT_MAX_TRANSFER_SIZE *
354 AMDGPU_GPU_PAGE_SIZE);
356 uint64_t src_node_size, dst_node_size, src_offset, dst_offset;
357 struct amdgpu_ring *ring = adev->mman.buffer_funcs_ring;
358 struct drm_mm_node *src_mm, *dst_mm;
359 struct dma_fence *fence = NULL;
362 if (!adev->mman.buffer_funcs_enabled) {
363 DRM_ERROR("Trying to move memory with ring turned off.\n");
367 src_offset = src->offset;
368 if (src->mem->mm_node) {
369 src_mm = amdgpu_find_mm_node(src->mem, &src_offset);
370 src_node_size = (src_mm->size << PAGE_SHIFT) - src_offset;
373 src_node_size = ULLONG_MAX;
376 dst_offset = dst->offset;
377 if (dst->mem->mm_node) {
378 dst_mm = amdgpu_find_mm_node(dst->mem, &dst_offset);
379 dst_node_size = (dst_mm->size << PAGE_SHIFT) - dst_offset;
382 dst_node_size = ULLONG_MAX;
385 mutex_lock(&adev->mman.gtt_window_lock);
388 uint32_t src_page_offset = src_offset & ~PAGE_MASK;
389 uint32_t dst_page_offset = dst_offset & ~PAGE_MASK;
390 struct dma_fence *next;
394 /* Copy size cannot exceed GTT_MAX_BYTES. So if src or dst
395 * begins at an offset, then adjust the size accordingly
397 cur_size = max(src_page_offset, dst_page_offset);
398 cur_size = min(min3(src_node_size, dst_node_size, size),
399 (uint64_t)(GTT_MAX_BYTES - cur_size));
401 /* Map src to window 0 and dst to window 1. */
402 r = amdgpu_ttm_map_buffer(src->bo, src->mem, src_mm,
403 PFN_UP(cur_size + src_page_offset),
404 src_offset, 0, ring, tmz, &from);
408 r = amdgpu_ttm_map_buffer(dst->bo, dst->mem, dst_mm,
409 PFN_UP(cur_size + dst_page_offset),
410 dst_offset, 1, ring, tmz, &to);
414 r = amdgpu_copy_buffer(ring, from, to, cur_size,
415 resv, &next, false, true, tmz);
419 dma_fence_put(fence);
426 src_node_size -= cur_size;
427 if (!src_node_size) {
429 src_node_size = src_mm->size << PAGE_SHIFT;
432 src_offset += cur_size;
435 dst_node_size -= cur_size;
436 if (!dst_node_size) {
438 dst_node_size = dst_mm->size << PAGE_SHIFT;
441 dst_offset += cur_size;
445 mutex_unlock(&adev->mman.gtt_window_lock);
447 *f = dma_fence_get(fence);
448 dma_fence_put(fence);
453 * amdgpu_move_blit - Copy an entire buffer to another buffer
455 * This is a helper called by amdgpu_bo_move() and amdgpu_move_vram_ram() to
456 * help move buffers to and from VRAM.
458 static int amdgpu_move_blit(struct ttm_buffer_object *bo,
460 struct ttm_resource *new_mem,
461 struct ttm_resource *old_mem)
463 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev);
464 struct amdgpu_bo *abo = ttm_to_amdgpu_bo(bo);
465 struct amdgpu_copy_mem src, dst;
466 struct dma_fence *fence = NULL;
476 r = amdgpu_ttm_copy_mem_to_mem(adev, &src, &dst,
477 new_mem->num_pages << PAGE_SHIFT,
478 amdgpu_bo_encrypted(abo),
479 bo->base.resv, &fence);
483 /* clear the space being freed */
484 if (old_mem->mem_type == TTM_PL_VRAM &&
485 (abo->flags & AMDGPU_GEM_CREATE_VRAM_WIPE_ON_RELEASE)) {
486 struct dma_fence *wipe_fence = NULL;
488 r = amdgpu_fill_buffer(ttm_to_amdgpu_bo(bo), AMDGPU_POISON,
492 } else if (wipe_fence) {
493 dma_fence_put(fence);
498 /* Always block for VM page tables before committing the new location */
499 if (bo->type == ttm_bo_type_kernel)
500 r = ttm_bo_move_accel_cleanup(bo, fence, true, new_mem);
502 r = ttm_bo_pipeline_move(bo, fence, evict, new_mem);
503 dma_fence_put(fence);
508 dma_fence_wait(fence, false);
509 dma_fence_put(fence);
514 * amdgpu_move_vram_ram - Copy VRAM buffer to RAM buffer
516 * Called by amdgpu_bo_move().
518 static int amdgpu_move_vram_ram(struct ttm_buffer_object *bo, bool evict,
519 struct ttm_operation_ctx *ctx,
520 struct ttm_resource *new_mem)
522 struct ttm_resource *old_mem = &bo->mem;
523 struct ttm_resource tmp_mem;
524 struct ttm_place placements;
525 struct ttm_placement placement;
528 /* create space/pages for new_mem in GTT space */
530 tmp_mem.mm_node = NULL;
531 placement.num_placement = 1;
532 placement.placement = &placements;
533 placement.num_busy_placement = 1;
534 placement.busy_placement = &placements;
537 placements.mem_type = TTM_PL_TT;
538 placements.flags = TTM_PL_MASK_CACHING;
539 r = ttm_bo_mem_space(bo, &placement, &tmp_mem, ctx);
541 pr_err("Failed to find GTT space for blit from VRAM\n");
545 /* set caching flags */
546 r = ttm_tt_set_placement_caching(bo->ttm, tmp_mem.placement);
551 /* Bind the memory to the GTT space */
552 r = ttm_tt_bind(bo->bdev, bo->ttm, &tmp_mem, ctx);
557 /* blit VRAM to GTT */
558 r = amdgpu_move_blit(bo, evict, &tmp_mem, old_mem);
563 /* move BO (in tmp_mem) to new_mem */
564 r = ttm_bo_move_ttm(bo, ctx, new_mem);
566 ttm_resource_free(bo, &tmp_mem);
571 * amdgpu_move_ram_vram - Copy buffer from RAM to VRAM
573 * Called by amdgpu_bo_move().
575 static int amdgpu_move_ram_vram(struct ttm_buffer_object *bo, bool evict,
576 struct ttm_operation_ctx *ctx,
577 struct ttm_resource *new_mem)
579 struct ttm_resource *old_mem = &bo->mem;
580 struct ttm_resource tmp_mem;
581 struct ttm_placement placement;
582 struct ttm_place placements;
585 /* make space in GTT for old_mem buffer */
587 tmp_mem.mm_node = NULL;
588 placement.num_placement = 1;
589 placement.placement = &placements;
590 placement.num_busy_placement = 1;
591 placement.busy_placement = &placements;
594 placements.mem_type = TTM_PL_TT;
595 placements.flags = TTM_PL_MASK_CACHING;
596 r = ttm_bo_mem_space(bo, &placement, &tmp_mem, ctx);
598 pr_err("Failed to find GTT space for blit to VRAM\n");
602 /* move/bind old memory to GTT space */
603 r = ttm_bo_move_ttm(bo, ctx, &tmp_mem);
609 r = amdgpu_move_blit(bo, evict, new_mem, old_mem);
614 ttm_resource_free(bo, &tmp_mem);
619 * amdgpu_mem_visible - Check that memory can be accessed by ttm_bo_move_memcpy
621 * Called by amdgpu_bo_move()
623 static bool amdgpu_mem_visible(struct amdgpu_device *adev,
624 struct ttm_resource *mem)
626 struct drm_mm_node *nodes = mem->mm_node;
628 if (mem->mem_type == TTM_PL_SYSTEM ||
629 mem->mem_type == TTM_PL_TT)
631 if (mem->mem_type != TTM_PL_VRAM)
634 /* ttm_resource_ioremap only supports contiguous memory */
635 if (nodes->size != mem->num_pages)
638 return ((nodes->start + nodes->size) << PAGE_SHIFT)
639 <= adev->gmc.visible_vram_size;
643 * amdgpu_bo_move - Move a buffer object to a new memory location
645 * Called by ttm_bo_handle_move_mem()
647 static int amdgpu_bo_move(struct ttm_buffer_object *bo, bool evict,
648 struct ttm_operation_ctx *ctx,
649 struct ttm_resource *new_mem)
651 struct amdgpu_device *adev;
652 struct amdgpu_bo *abo;
653 struct ttm_resource *old_mem = &bo->mem;
656 /* Can't move a pinned BO */
657 abo = ttm_to_amdgpu_bo(bo);
658 if (WARN_ON_ONCE(abo->pin_count > 0))
661 adev = amdgpu_ttm_adev(bo->bdev);
663 if (old_mem->mem_type == TTM_PL_SYSTEM && bo->ttm == NULL) {
664 ttm_bo_move_null(bo, new_mem);
667 if ((old_mem->mem_type == TTM_PL_TT &&
668 new_mem->mem_type == TTM_PL_SYSTEM) ||
669 (old_mem->mem_type == TTM_PL_SYSTEM &&
670 new_mem->mem_type == TTM_PL_TT)) {
672 ttm_bo_move_null(bo, new_mem);
675 if (old_mem->mem_type == AMDGPU_PL_GDS ||
676 old_mem->mem_type == AMDGPU_PL_GWS ||
677 old_mem->mem_type == AMDGPU_PL_OA ||
678 new_mem->mem_type == AMDGPU_PL_GDS ||
679 new_mem->mem_type == AMDGPU_PL_GWS ||
680 new_mem->mem_type == AMDGPU_PL_OA) {
681 /* Nothing to save here */
682 ttm_bo_move_null(bo, new_mem);
686 if (!adev->mman.buffer_funcs_enabled) {
691 if (old_mem->mem_type == TTM_PL_VRAM &&
692 new_mem->mem_type == TTM_PL_SYSTEM) {
693 r = amdgpu_move_vram_ram(bo, evict, ctx, new_mem);
694 } else if (old_mem->mem_type == TTM_PL_SYSTEM &&
695 new_mem->mem_type == TTM_PL_VRAM) {
696 r = amdgpu_move_ram_vram(bo, evict, ctx, new_mem);
698 r = amdgpu_move_blit(bo, evict,
704 /* Check that all memory is CPU accessible */
705 if (!amdgpu_mem_visible(adev, old_mem) ||
706 !amdgpu_mem_visible(adev, new_mem)) {
707 pr_err("Move buffer fallback to memcpy unavailable\n");
711 r = ttm_bo_move_memcpy(bo, ctx, new_mem);
716 if (bo->type == ttm_bo_type_device &&
717 new_mem->mem_type == TTM_PL_VRAM &&
718 old_mem->mem_type != TTM_PL_VRAM) {
719 /* amdgpu_bo_fault_reserve_notify will re-set this if the CPU
720 * accesses the BO after it's moved.
722 abo->flags &= ~AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED;
725 /* update statistics */
726 atomic64_add((u64)bo->num_pages << PAGE_SHIFT, &adev->num_bytes_moved);
731 * amdgpu_ttm_io_mem_reserve - Reserve a block of memory during a fault
733 * Called by ttm_mem_io_reserve() ultimately via ttm_bo_vm_fault()
735 static int amdgpu_ttm_io_mem_reserve(struct ttm_bo_device *bdev, struct ttm_resource *mem)
737 struct amdgpu_device *adev = amdgpu_ttm_adev(bdev);
738 struct drm_mm_node *mm_node = mem->mm_node;
739 size_t bus_size = (size_t)mem->num_pages << PAGE_SHIFT;
741 switch (mem->mem_type) {
748 mem->bus.offset = mem->start << PAGE_SHIFT;
749 /* check if it's visible */
750 if ((mem->bus.offset + bus_size) > adev->gmc.visible_vram_size)
752 /* Only physically contiguous buffers apply. In a contiguous
753 * buffer, size of the first mm_node would match the number of
754 * pages in ttm_resource.
756 if (adev->mman.aper_base_kaddr &&
757 (mm_node->size == mem->num_pages))
758 mem->bus.addr = (u8 *)adev->mman.aper_base_kaddr +
761 mem->bus.offset += adev->gmc.aper_base;
762 mem->bus.is_iomem = true;
770 static unsigned long amdgpu_ttm_io_mem_pfn(struct ttm_buffer_object *bo,
771 unsigned long page_offset)
773 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev);
774 uint64_t offset = (page_offset << PAGE_SHIFT);
775 struct drm_mm_node *mm;
777 mm = amdgpu_find_mm_node(&bo->mem, &offset);
778 offset += adev->gmc.aper_base;
779 return mm->start + (offset >> PAGE_SHIFT);
783 * amdgpu_ttm_domain_start - Returns GPU start address
784 * @adev: amdgpu device object
785 * @type: type of the memory
788 * GPU start address of a memory domain
791 uint64_t amdgpu_ttm_domain_start(struct amdgpu_device *adev, uint32_t type)
795 return adev->gmc.gart_start;
797 return adev->gmc.vram_start;
804 * TTM backend functions.
806 struct amdgpu_ttm_tt {
807 struct ttm_dma_tt ttm;
808 struct drm_gem_object *gobj;
811 struct task_struct *usertask;
813 #if IS_ENABLED(CONFIG_DRM_AMDGPU_USERPTR)
814 struct hmm_range *range;
818 #ifdef CONFIG_DRM_AMDGPU_USERPTR
820 * amdgpu_ttm_tt_get_user_pages - get device accessible pages that back user
821 * memory and start HMM tracking CPU page table update
823 * Calling function must call amdgpu_ttm_tt_userptr_range_done() once and only
824 * once afterwards to stop HMM tracking
826 int amdgpu_ttm_tt_get_user_pages(struct amdgpu_bo *bo, struct page **pages)
828 struct ttm_tt *ttm = bo->tbo.ttm;
829 struct amdgpu_ttm_tt *gtt = (void *)ttm;
830 unsigned long start = gtt->userptr;
831 struct vm_area_struct *vma;
832 struct hmm_range *range;
833 unsigned long timeout;
834 struct mm_struct *mm;
838 mm = bo->notifier.mm;
840 DRM_DEBUG_DRIVER("BO is not registered?\n");
844 /* Another get_user_pages is running at the same time?? */
845 if (WARN_ON(gtt->range))
848 if (!mmget_not_zero(mm)) /* Happens during process shutdown */
851 range = kzalloc(sizeof(*range), GFP_KERNEL);
852 if (unlikely(!range)) {
856 range->notifier = &bo->notifier;
857 range->start = bo->notifier.interval_tree.start;
858 range->end = bo->notifier.interval_tree.last + 1;
859 range->default_flags = HMM_PFN_REQ_FAULT;
860 if (!amdgpu_ttm_tt_is_readonly(ttm))
861 range->default_flags |= HMM_PFN_REQ_WRITE;
863 range->hmm_pfns = kvmalloc_array(ttm->num_pages,
864 sizeof(*range->hmm_pfns), GFP_KERNEL);
865 if (unlikely(!range->hmm_pfns)) {
867 goto out_free_ranges;
871 vma = find_vma(mm, start);
872 if (unlikely(!vma || start < vma->vm_start)) {
876 if (unlikely((gtt->userflags & AMDGPU_GEM_USERPTR_ANONONLY) &&
881 mmap_read_unlock(mm);
882 timeout = jiffies + msecs_to_jiffies(HMM_RANGE_DEFAULT_TIMEOUT);
885 range->notifier_seq = mmu_interval_read_begin(&bo->notifier);
888 r = hmm_range_fault(range);
889 mmap_read_unlock(mm);
892 * FIXME: This timeout should encompass the retry from
893 * mmu_interval_read_retry() as well.
895 if (r == -EBUSY && !time_after(jiffies, timeout))
901 * Due to default_flags, all pages are HMM_PFN_VALID or
902 * hmm_range_fault() fails. FIXME: The pages cannot be touched outside
903 * the notifier_lock, and mmu_interval_read_retry() must be done first.
905 for (i = 0; i < ttm->num_pages; i++)
906 pages[i] = hmm_pfn_to_page(range->hmm_pfns[i]);
914 mmap_read_unlock(mm);
916 kvfree(range->hmm_pfns);
925 * amdgpu_ttm_tt_userptr_range_done - stop HMM track the CPU page table change
926 * Check if the pages backing this ttm range have been invalidated
928 * Returns: true if pages are still valid
930 bool amdgpu_ttm_tt_get_user_pages_done(struct ttm_tt *ttm)
932 struct amdgpu_ttm_tt *gtt = (void *)ttm;
935 if (!gtt || !gtt->userptr)
938 DRM_DEBUG_DRIVER("user_pages_done 0x%llx pages 0x%lx\n",
939 gtt->userptr, ttm->num_pages);
941 WARN_ONCE(!gtt->range || !gtt->range->hmm_pfns,
942 "No user pages to check\n");
946 * FIXME: Must always hold notifier_lock for this, and must
947 * not ignore the return code.
949 r = mmu_interval_read_retry(gtt->range->notifier,
950 gtt->range->notifier_seq);
951 kvfree(gtt->range->hmm_pfns);
961 * amdgpu_ttm_tt_set_user_pages - Copy pages in, putting old pages as necessary.
963 * Called by amdgpu_cs_list_validate(). This creates the page list
964 * that backs user memory and will ultimately be mapped into the device
967 void amdgpu_ttm_tt_set_user_pages(struct ttm_tt *ttm, struct page **pages)
971 for (i = 0; i < ttm->num_pages; ++i)
972 ttm->pages[i] = pages ? pages[i] : NULL;
976 * amdgpu_ttm_tt_pin_userptr - prepare the sg table with the user pages
978 * Called by amdgpu_ttm_backend_bind()
980 static int amdgpu_ttm_tt_pin_userptr(struct ttm_bo_device *bdev,
983 struct amdgpu_device *adev = amdgpu_ttm_adev(bdev);
984 struct amdgpu_ttm_tt *gtt = (void *)ttm;
987 int write = !(gtt->userflags & AMDGPU_GEM_USERPTR_READONLY);
988 enum dma_data_direction direction = write ?
989 DMA_BIDIRECTIONAL : DMA_TO_DEVICE;
991 /* Allocate an SG array and squash pages into it */
992 r = sg_alloc_table_from_pages(ttm->sg, ttm->pages, ttm->num_pages, 0,
993 ttm->num_pages << PAGE_SHIFT,
998 /* Map SG to device */
999 r = dma_map_sgtable(adev->dev, ttm->sg, direction, 0);
1003 /* convert SG to linear array of pages and dma addresses */
1004 drm_prime_sg_to_page_addr_arrays(ttm->sg, ttm->pages,
1005 gtt->ttm.dma_address, ttm->num_pages);
1015 * amdgpu_ttm_tt_unpin_userptr - Unpin and unmap userptr pages
1017 static void amdgpu_ttm_tt_unpin_userptr(struct ttm_bo_device *bdev,
1020 struct amdgpu_device *adev = amdgpu_ttm_adev(bdev);
1021 struct amdgpu_ttm_tt *gtt = (void *)ttm;
1023 int write = !(gtt->userflags & AMDGPU_GEM_USERPTR_READONLY);
1024 enum dma_data_direction direction = write ?
1025 DMA_BIDIRECTIONAL : DMA_TO_DEVICE;
1027 /* double check that we don't free the table twice */
1031 /* unmap the pages mapped to the device */
1032 dma_unmap_sgtable(adev->dev, ttm->sg, direction, 0);
1033 sg_free_table(ttm->sg);
1035 #if IS_ENABLED(CONFIG_DRM_AMDGPU_USERPTR)
1039 for (i = 0; i < ttm->num_pages; i++) {
1040 if (ttm->pages[i] !=
1041 hmm_pfn_to_page(gtt->range->hmm_pfns[i]))
1045 WARN((i == ttm->num_pages), "Missing get_user_page_done\n");
1050 static int amdgpu_ttm_gart_bind(struct amdgpu_device *adev,
1051 struct ttm_buffer_object *tbo,
1054 struct amdgpu_bo *abo = ttm_to_amdgpu_bo(tbo);
1055 struct ttm_tt *ttm = tbo->ttm;
1056 struct amdgpu_ttm_tt *gtt = (void *)ttm;
1059 if (amdgpu_bo_encrypted(abo))
1060 flags |= AMDGPU_PTE_TMZ;
1062 if (abo->flags & AMDGPU_GEM_CREATE_CP_MQD_GFX9) {
1063 uint64_t page_idx = 1;
1065 r = amdgpu_gart_bind(adev, gtt->offset, page_idx,
1066 ttm->pages, gtt->ttm.dma_address, flags);
1068 goto gart_bind_fail;
1070 /* The memory type of the first page defaults to UC. Now
1071 * modify the memory type to NC from the second page of
1074 flags &= ~AMDGPU_PTE_MTYPE_VG10_MASK;
1075 flags |= AMDGPU_PTE_MTYPE_VG10(AMDGPU_MTYPE_NC);
1077 r = amdgpu_gart_bind(adev,
1078 gtt->offset + (page_idx << PAGE_SHIFT),
1079 ttm->num_pages - page_idx,
1080 &ttm->pages[page_idx],
1081 &(gtt->ttm.dma_address[page_idx]), flags);
1083 r = amdgpu_gart_bind(adev, gtt->offset, ttm->num_pages,
1084 ttm->pages, gtt->ttm.dma_address, flags);
1089 DRM_ERROR("failed to bind %lu pages at 0x%08llX\n",
1090 ttm->num_pages, gtt->offset);
1096 * amdgpu_ttm_backend_bind - Bind GTT memory
1098 * Called by ttm_tt_bind() on behalf of ttm_bo_handle_move_mem().
1099 * This handles binding GTT memory to the device address space.
1101 static int amdgpu_ttm_backend_bind(struct ttm_bo_device *bdev,
1103 struct ttm_resource *bo_mem)
1105 struct amdgpu_device *adev = amdgpu_ttm_adev(bdev);
1106 struct amdgpu_ttm_tt *gtt = (void*)ttm;
1111 r = amdgpu_ttm_tt_pin_userptr(bdev, ttm);
1113 DRM_ERROR("failed to pin userptr\n");
1117 if (!ttm->num_pages) {
1118 WARN(1, "nothing to bind %lu pages for mreg %p back %p!\n",
1119 ttm->num_pages, bo_mem, ttm);
1122 if (bo_mem->mem_type == AMDGPU_PL_GDS ||
1123 bo_mem->mem_type == AMDGPU_PL_GWS ||
1124 bo_mem->mem_type == AMDGPU_PL_OA)
1127 if (!amdgpu_gtt_mgr_has_gart_addr(bo_mem)) {
1128 gtt->offset = AMDGPU_BO_INVALID_OFFSET;
1132 /* compute PTE flags relevant to this BO memory */
1133 flags = amdgpu_ttm_tt_pte_flags(adev, ttm, bo_mem);
1135 /* bind pages into GART page tables */
1136 gtt->offset = (u64)bo_mem->start << PAGE_SHIFT;
1137 r = amdgpu_gart_bind(adev, gtt->offset, ttm->num_pages,
1138 ttm->pages, gtt->ttm.dma_address, flags);
1141 DRM_ERROR("failed to bind %lu pages at 0x%08llX\n",
1142 ttm->num_pages, gtt->offset);
1147 * amdgpu_ttm_alloc_gart - Allocate GART memory for buffer object
1149 int amdgpu_ttm_alloc_gart(struct ttm_buffer_object *bo)
1151 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev);
1152 struct ttm_operation_ctx ctx = { false, false };
1153 struct amdgpu_ttm_tt *gtt = (void*)bo->ttm;
1154 struct ttm_resource tmp;
1155 struct ttm_placement placement;
1156 struct ttm_place placements;
1157 uint64_t addr, flags;
1160 if (bo->mem.start != AMDGPU_BO_INVALID_OFFSET)
1163 addr = amdgpu_gmc_agp_addr(bo);
1164 if (addr != AMDGPU_BO_INVALID_OFFSET) {
1165 bo->mem.start = addr >> PAGE_SHIFT;
1168 /* allocate GART space */
1171 placement.num_placement = 1;
1172 placement.placement = &placements;
1173 placement.num_busy_placement = 1;
1174 placement.busy_placement = &placements;
1175 placements.fpfn = 0;
1176 placements.lpfn = adev->gmc.gart_size >> PAGE_SHIFT;
1177 placements.mem_type = TTM_PL_TT;
1178 placements.flags = bo->mem.placement;
1180 r = ttm_bo_mem_space(bo, &placement, &tmp, &ctx);
1184 /* compute PTE flags for this buffer object */
1185 flags = amdgpu_ttm_tt_pte_flags(adev, bo->ttm, &tmp);
1188 gtt->offset = (u64)tmp.start << PAGE_SHIFT;
1189 r = amdgpu_ttm_gart_bind(adev, bo, flags);
1191 ttm_resource_free(bo, &tmp);
1195 ttm_resource_free(bo, &bo->mem);
1203 * amdgpu_ttm_recover_gart - Rebind GTT pages
1205 * Called by amdgpu_gtt_mgr_recover() from amdgpu_device_reset() to
1206 * rebind GTT pages during a GPU reset.
1208 int amdgpu_ttm_recover_gart(struct ttm_buffer_object *tbo)
1210 struct amdgpu_device *adev = amdgpu_ttm_adev(tbo->bdev);
1217 flags = amdgpu_ttm_tt_pte_flags(adev, tbo->ttm, &tbo->mem);
1218 r = amdgpu_ttm_gart_bind(adev, tbo, flags);
1224 * amdgpu_ttm_backend_unbind - Unbind GTT mapped pages
1226 * Called by ttm_tt_unbind() on behalf of ttm_bo_move_ttm() and
1229 static void amdgpu_ttm_backend_unbind(struct ttm_bo_device *bdev,
1232 struct amdgpu_device *adev = amdgpu_ttm_adev(bdev);
1233 struct amdgpu_ttm_tt *gtt = (void *)ttm;
1236 /* if the pages have userptr pinning then clear that first */
1238 amdgpu_ttm_tt_unpin_userptr(bdev, ttm);
1240 if (gtt->offset == AMDGPU_BO_INVALID_OFFSET)
1243 /* unbind shouldn't be done for GDS/GWS/OA in ttm_bo_clean_mm */
1244 r = amdgpu_gart_unbind(adev, gtt->offset, ttm->num_pages);
1246 DRM_ERROR("failed to unbind %lu pages at 0x%08llX\n",
1247 gtt->ttm.ttm.num_pages, gtt->offset);
1250 static void amdgpu_ttm_backend_destroy(struct ttm_bo_device *bdev,
1253 struct amdgpu_ttm_tt *gtt = (void *)ttm;
1256 put_task_struct(gtt->usertask);
1258 ttm_dma_tt_fini(>t->ttm);
1263 * amdgpu_ttm_tt_create - Create a ttm_tt object for a given BO
1265 * @bo: The buffer object to create a GTT ttm_tt object around
1267 * Called by ttm_tt_create().
1269 static struct ttm_tt *amdgpu_ttm_tt_create(struct ttm_buffer_object *bo,
1270 uint32_t page_flags)
1272 struct amdgpu_ttm_tt *gtt;
1274 gtt = kzalloc(sizeof(struct amdgpu_ttm_tt), GFP_KERNEL);
1278 gtt->gobj = &bo->base;
1280 /* allocate space for the uninitialized page entries */
1281 if (ttm_sg_tt_init(>t->ttm, bo, page_flags)) {
1285 return >t->ttm.ttm;
1289 * amdgpu_ttm_tt_populate - Map GTT pages visible to the device
1291 * Map the pages of a ttm_tt object to an address space visible
1292 * to the underlying device.
1294 static int amdgpu_ttm_tt_populate(struct ttm_bo_device *bdev,
1296 struct ttm_operation_ctx *ctx)
1298 struct amdgpu_device *adev = amdgpu_ttm_adev(bdev);
1299 struct amdgpu_ttm_tt *gtt = (void *)ttm;
1301 /* user pages are bound by amdgpu_ttm_tt_pin_userptr() */
1302 if (gtt && gtt->userptr) {
1303 ttm->sg = kzalloc(sizeof(struct sg_table), GFP_KERNEL);
1307 ttm->page_flags |= TTM_PAGE_FLAG_SG;
1308 ttm->state = tt_unbound;
1312 if (ttm->page_flags & TTM_PAGE_FLAG_SG) {
1314 struct dma_buf_attachment *attach;
1315 struct sg_table *sgt;
1317 attach = gtt->gobj->import_attach;
1318 sgt = dma_buf_map_attachment(attach, DMA_BIDIRECTIONAL);
1320 return PTR_ERR(sgt);
1325 drm_prime_sg_to_page_addr_arrays(ttm->sg, ttm->pages,
1326 gtt->ttm.dma_address,
1328 ttm->state = tt_unbound;
1332 #ifdef CONFIG_SWIOTLB
1333 if (adev->need_swiotlb && swiotlb_nr_tbl()) {
1334 return ttm_dma_populate(>t->ttm, adev->dev, ctx);
1338 /* fall back to generic helper to populate the page array
1339 * and map them to the device */
1340 return ttm_populate_and_map_pages(adev->dev, >t->ttm, ctx);
1344 * amdgpu_ttm_tt_unpopulate - unmap GTT pages and unpopulate page arrays
1346 * Unmaps pages of a ttm_tt object from the device address space and
1347 * unpopulates the page array backing it.
1349 static void amdgpu_ttm_tt_unpopulate(struct ttm_bo_device *bdev, struct ttm_tt *ttm)
1351 struct amdgpu_ttm_tt *gtt = (void *)ttm;
1352 struct amdgpu_device *adev;
1354 if (gtt && gtt->userptr) {
1355 amdgpu_ttm_tt_set_user_pages(ttm, NULL);
1357 ttm->page_flags &= ~TTM_PAGE_FLAG_SG;
1361 if (ttm->sg && gtt->gobj->import_attach) {
1362 struct dma_buf_attachment *attach;
1364 attach = gtt->gobj->import_attach;
1365 dma_buf_unmap_attachment(attach, ttm->sg, DMA_BIDIRECTIONAL);
1370 if (ttm->page_flags & TTM_PAGE_FLAG_SG)
1373 adev = amdgpu_ttm_adev(bdev);
1375 #ifdef CONFIG_SWIOTLB
1376 if (adev->need_swiotlb && swiotlb_nr_tbl()) {
1377 ttm_dma_unpopulate(>t->ttm, adev->dev);
1382 /* fall back to generic helper to unmap and unpopulate array */
1383 ttm_unmap_and_unpopulate_pages(adev->dev, >t->ttm);
1387 * amdgpu_ttm_tt_set_userptr - Initialize userptr GTT ttm_tt for the current
1390 * @bo: The ttm_buffer_object to bind this userptr to
1391 * @addr: The address in the current tasks VM space to use
1392 * @flags: Requirements of userptr object.
1394 * Called by amdgpu_gem_userptr_ioctl() to bind userptr pages
1397 int amdgpu_ttm_tt_set_userptr(struct ttm_buffer_object *bo,
1398 uint64_t addr, uint32_t flags)
1400 struct amdgpu_ttm_tt *gtt;
1403 /* TODO: We want a separate TTM object type for userptrs */
1404 bo->ttm = amdgpu_ttm_tt_create(bo, 0);
1405 if (bo->ttm == NULL)
1409 gtt = (void*)bo->ttm;
1410 gtt->userptr = addr;
1411 gtt->userflags = flags;
1414 put_task_struct(gtt->usertask);
1415 gtt->usertask = current->group_leader;
1416 get_task_struct(gtt->usertask);
1422 * amdgpu_ttm_tt_get_usermm - Return memory manager for ttm_tt object
1424 struct mm_struct *amdgpu_ttm_tt_get_usermm(struct ttm_tt *ttm)
1426 struct amdgpu_ttm_tt *gtt = (void *)ttm;
1431 if (gtt->usertask == NULL)
1434 return gtt->usertask->mm;
1438 * amdgpu_ttm_tt_affect_userptr - Determine if a ttm_tt object lays inside an
1439 * address range for the current task.
1442 bool amdgpu_ttm_tt_affect_userptr(struct ttm_tt *ttm, unsigned long start,
1445 struct amdgpu_ttm_tt *gtt = (void *)ttm;
1448 if (gtt == NULL || !gtt->userptr)
1451 /* Return false if no part of the ttm_tt object lies within
1454 size = (unsigned long)gtt->ttm.ttm.num_pages * PAGE_SIZE;
1455 if (gtt->userptr > end || gtt->userptr + size <= start)
1462 * amdgpu_ttm_tt_is_userptr - Have the pages backing by userptr?
1464 bool amdgpu_ttm_tt_is_userptr(struct ttm_tt *ttm)
1466 struct amdgpu_ttm_tt *gtt = (void *)ttm;
1468 if (gtt == NULL || !gtt->userptr)
1475 * amdgpu_ttm_tt_is_readonly - Is the ttm_tt object read only?
1477 bool amdgpu_ttm_tt_is_readonly(struct ttm_tt *ttm)
1479 struct amdgpu_ttm_tt *gtt = (void *)ttm;
1484 return !!(gtt->userflags & AMDGPU_GEM_USERPTR_READONLY);
1488 * amdgpu_ttm_tt_pde_flags - Compute PDE flags for ttm_tt object
1490 * @ttm: The ttm_tt object to compute the flags for
1491 * @mem: The memory registry backing this ttm_tt object
1493 * Figure out the flags to use for a VM PDE (Page Directory Entry).
1495 uint64_t amdgpu_ttm_tt_pde_flags(struct ttm_tt *ttm, struct ttm_resource *mem)
1499 if (mem && mem->mem_type != TTM_PL_SYSTEM)
1500 flags |= AMDGPU_PTE_VALID;
1502 if (mem && mem->mem_type == TTM_PL_TT) {
1503 flags |= AMDGPU_PTE_SYSTEM;
1505 if (ttm->caching_state == tt_cached)
1506 flags |= AMDGPU_PTE_SNOOPED;
1513 * amdgpu_ttm_tt_pte_flags - Compute PTE flags for ttm_tt object
1515 * @ttm: The ttm_tt object to compute the flags for
1516 * @mem: The memory registry backing this ttm_tt object
1518 * Figure out the flags to use for a VM PTE (Page Table Entry).
1520 uint64_t amdgpu_ttm_tt_pte_flags(struct amdgpu_device *adev, struct ttm_tt *ttm,
1521 struct ttm_resource *mem)
1523 uint64_t flags = amdgpu_ttm_tt_pde_flags(ttm, mem);
1525 flags |= adev->gart.gart_pte_flags;
1526 flags |= AMDGPU_PTE_READABLE;
1528 if (!amdgpu_ttm_tt_is_readonly(ttm))
1529 flags |= AMDGPU_PTE_WRITEABLE;
1535 * amdgpu_ttm_bo_eviction_valuable - Check to see if we can evict a buffer
1538 * Return true if eviction is sensible. Called by ttm_mem_evict_first() on
1539 * behalf of ttm_bo_mem_force_space() which tries to evict buffer objects until
1540 * it can find space for a new object and by ttm_bo_force_list_clean() which is
1541 * used to clean out a memory space.
1543 static bool amdgpu_ttm_bo_eviction_valuable(struct ttm_buffer_object *bo,
1544 const struct ttm_place *place)
1546 unsigned long num_pages = bo->mem.num_pages;
1547 struct drm_mm_node *node = bo->mem.mm_node;
1548 struct dma_resv_list *flist;
1549 struct dma_fence *f;
1552 if (bo->type == ttm_bo_type_kernel &&
1553 !amdgpu_vm_evictable(ttm_to_amdgpu_bo(bo)))
1556 /* If bo is a KFD BO, check if the bo belongs to the current process.
1557 * If true, then return false as any KFD process needs all its BOs to
1558 * be resident to run successfully
1560 flist = dma_resv_get_list(bo->base.resv);
1562 for (i = 0; i < flist->shared_count; ++i) {
1563 f = rcu_dereference_protected(flist->shared[i],
1564 dma_resv_held(bo->base.resv));
1565 if (amdkfd_fence_check_mm(f, current->mm))
1570 switch (bo->mem.mem_type) {
1572 if (amdgpu_bo_is_amdgpu_bo(bo) &&
1573 amdgpu_bo_encrypted(ttm_to_amdgpu_bo(bo)))
1578 /* Check each drm MM node individually */
1580 if (place->fpfn < (node->start + node->size) &&
1581 !(place->lpfn && place->lpfn <= node->start))
1584 num_pages -= node->size;
1593 return ttm_bo_eviction_valuable(bo, place);
1597 * amdgpu_ttm_access_memory - Read or Write memory that backs a buffer object.
1599 * @bo: The buffer object to read/write
1600 * @offset: Offset into buffer object
1601 * @buf: Secondary buffer to write/read from
1602 * @len: Length in bytes of access
1603 * @write: true if writing
1605 * This is used to access VRAM that backs a buffer object via MMIO
1606 * access for debugging purposes.
1608 static int amdgpu_ttm_access_memory(struct ttm_buffer_object *bo,
1609 unsigned long offset,
1610 void *buf, int len, int write)
1612 struct amdgpu_bo *abo = ttm_to_amdgpu_bo(bo);
1613 struct amdgpu_device *adev = amdgpu_ttm_adev(abo->tbo.bdev);
1614 struct drm_mm_node *nodes;
1618 unsigned long flags;
1620 if (bo->mem.mem_type != TTM_PL_VRAM)
1624 nodes = amdgpu_find_mm_node(&abo->tbo.mem, &pos);
1625 pos += (nodes->start << PAGE_SHIFT);
1627 while (len && pos < adev->gmc.mc_vram_size) {
1628 uint64_t aligned_pos = pos & ~(uint64_t)3;
1629 uint64_t bytes = 4 - (pos & 3);
1630 uint32_t shift = (pos & 3) * 8;
1631 uint32_t mask = 0xffffffff << shift;
1634 mask &= 0xffffffff >> (bytes - len) * 8;
1638 if (mask != 0xffffffff) {
1639 spin_lock_irqsave(&adev->mmio_idx_lock, flags);
1640 WREG32_NO_KIQ(mmMM_INDEX, ((uint32_t)aligned_pos) | 0x80000000);
1641 WREG32_NO_KIQ(mmMM_INDEX_HI, aligned_pos >> 31);
1642 if (!write || mask != 0xffffffff)
1643 value = RREG32_NO_KIQ(mmMM_DATA);
1646 value |= (*(uint32_t *)buf << shift) & mask;
1647 WREG32_NO_KIQ(mmMM_DATA, value);
1649 spin_unlock_irqrestore(&adev->mmio_idx_lock, flags);
1651 value = (value & mask) >> shift;
1652 memcpy(buf, &value, bytes);
1655 bytes = (nodes->start + nodes->size) << PAGE_SHIFT;
1656 bytes = min(bytes - pos, (uint64_t)len & ~0x3ull);
1658 amdgpu_device_vram_access(adev, pos, (uint32_t *)buf,
1663 buf = (uint8_t *)buf + bytes;
1666 if (pos >= (nodes->start + nodes->size) << PAGE_SHIFT) {
1668 pos = (nodes->start << PAGE_SHIFT);
1675 static struct ttm_bo_driver amdgpu_bo_driver = {
1676 .ttm_tt_create = &amdgpu_ttm_tt_create,
1677 .ttm_tt_populate = &amdgpu_ttm_tt_populate,
1678 .ttm_tt_unpopulate = &amdgpu_ttm_tt_unpopulate,
1679 .ttm_tt_bind = &amdgpu_ttm_backend_bind,
1680 .ttm_tt_unbind = &amdgpu_ttm_backend_unbind,
1681 .ttm_tt_destroy = &amdgpu_ttm_backend_destroy,
1682 .eviction_valuable = amdgpu_ttm_bo_eviction_valuable,
1683 .evict_flags = &amdgpu_evict_flags,
1684 .move = &amdgpu_bo_move,
1685 .verify_access = &amdgpu_verify_access,
1686 .move_notify = &amdgpu_bo_move_notify,
1687 .release_notify = &amdgpu_bo_release_notify,
1688 .fault_reserve_notify = &amdgpu_bo_fault_reserve_notify,
1689 .io_mem_reserve = &amdgpu_ttm_io_mem_reserve,
1690 .io_mem_pfn = amdgpu_ttm_io_mem_pfn,
1691 .access_memory = &amdgpu_ttm_access_memory,
1692 .del_from_lru_notify = &amdgpu_vm_del_from_lru_notify
1696 * Firmware Reservation functions
1699 * amdgpu_ttm_fw_reserve_vram_fini - free fw reserved vram
1701 * @adev: amdgpu_device pointer
1703 * free fw reserved vram if it has been reserved.
1705 static void amdgpu_ttm_fw_reserve_vram_fini(struct amdgpu_device *adev)
1707 amdgpu_bo_free_kernel(&adev->mman.fw_vram_usage_reserved_bo,
1708 NULL, &adev->mman.fw_vram_usage_va);
1712 * amdgpu_ttm_fw_reserve_vram_init - create bo vram reservation from fw
1714 * @adev: amdgpu_device pointer
1716 * create bo vram reservation from fw.
1718 static int amdgpu_ttm_fw_reserve_vram_init(struct amdgpu_device *adev)
1720 uint64_t vram_size = adev->gmc.visible_vram_size;
1722 adev->mman.fw_vram_usage_va = NULL;
1723 adev->mman.fw_vram_usage_reserved_bo = NULL;
1725 if (adev->mman.fw_vram_usage_size == 0 ||
1726 adev->mman.fw_vram_usage_size > vram_size)
1729 return amdgpu_bo_create_kernel_at(adev,
1730 adev->mman.fw_vram_usage_start_offset,
1731 adev->mman.fw_vram_usage_size,
1732 AMDGPU_GEM_DOMAIN_VRAM,
1733 &adev->mman.fw_vram_usage_reserved_bo,
1734 &adev->mman.fw_vram_usage_va);
1738 * Memoy training reservation functions
1742 * amdgpu_ttm_training_reserve_vram_fini - free memory training reserved vram
1744 * @adev: amdgpu_device pointer
1746 * free memory training reserved vram if it has been reserved.
1748 static int amdgpu_ttm_training_reserve_vram_fini(struct amdgpu_device *adev)
1750 struct psp_memory_training_context *ctx = &adev->psp.mem_train_ctx;
1752 ctx->init = PSP_MEM_TRAIN_NOT_SUPPORT;
1753 amdgpu_bo_free_kernel(&ctx->c2p_bo, NULL, NULL);
1759 static void amdgpu_ttm_training_data_block_init(struct amdgpu_device *adev)
1761 struct psp_memory_training_context *ctx = &adev->psp.mem_train_ctx;
1763 memset(ctx, 0, sizeof(*ctx));
1765 ctx->c2p_train_data_offset =
1766 ALIGN((adev->gmc.mc_vram_size - adev->mman.discovery_tmr_size - SZ_1M), SZ_1M);
1767 ctx->p2c_train_data_offset =
1768 (adev->gmc.mc_vram_size - GDDR6_MEM_TRAINING_OFFSET);
1769 ctx->train_data_size =
1770 GDDR6_MEM_TRAINING_DATA_SIZE_IN_BYTES;
1772 DRM_DEBUG("train_data_size:%llx,p2c_train_data_offset:%llx,c2p_train_data_offset:%llx.\n",
1773 ctx->train_data_size,
1774 ctx->p2c_train_data_offset,
1775 ctx->c2p_train_data_offset);
1779 * reserve TMR memory at the top of VRAM which holds
1780 * IP Discovery data and is protected by PSP.
1782 static int amdgpu_ttm_reserve_tmr(struct amdgpu_device *adev)
1785 struct psp_memory_training_context *ctx = &adev->psp.mem_train_ctx;
1786 bool mem_train_support = false;
1788 if (!amdgpu_sriov_vf(adev)) {
1789 ret = amdgpu_mem_train_support(adev);
1791 mem_train_support = true;
1795 DRM_DEBUG("memory training does not support!\n");
1799 * Query reserved tmr size through atom firmwareinfo for Sienna_Cichlid and onwards for all
1800 * the use cases (IP discovery/G6 memory training/profiling/diagnostic data.etc)
1802 * Otherwise, fallback to legacy approach to check and reserve tmr block for ip
1803 * discovery data and G6 memory training data respectively
1805 adev->mman.discovery_tmr_size =
1806 amdgpu_atomfirmware_get_fw_reserved_fb_size(adev);
1807 if (!adev->mman.discovery_tmr_size)
1808 adev->mman.discovery_tmr_size = DISCOVERY_TMR_OFFSET;
1810 if (mem_train_support) {
1811 /* reserve vram for mem train according to TMR location */
1812 amdgpu_ttm_training_data_block_init(adev);
1813 ret = amdgpu_bo_create_kernel_at(adev,
1814 ctx->c2p_train_data_offset,
1815 ctx->train_data_size,
1816 AMDGPU_GEM_DOMAIN_VRAM,
1820 DRM_ERROR("alloc c2p_bo failed(%d)!\n", ret);
1821 amdgpu_ttm_training_reserve_vram_fini(adev);
1824 ctx->init = PSP_MEM_TRAIN_RESERVE_SUCCESS;
1827 ret = amdgpu_bo_create_kernel_at(adev,
1828 adev->gmc.real_vram_size - adev->mman.discovery_tmr_size,
1829 adev->mman.discovery_tmr_size,
1830 AMDGPU_GEM_DOMAIN_VRAM,
1831 &adev->mman.discovery_memory,
1834 DRM_ERROR("alloc tmr failed(%d)!\n", ret);
1835 amdgpu_bo_free_kernel(&adev->mman.discovery_memory, NULL, NULL);
1843 * amdgpu_ttm_init - Init the memory management (ttm) as well as various
1844 * gtt/vram related fields.
1846 * This initializes all of the memory space pools that the TTM layer
1847 * will need such as the GTT space (system memory mapped to the device),
1848 * VRAM (on-board memory), and on-chip memories (GDS, GWS, OA) which
1849 * can be mapped per VMID.
1851 int amdgpu_ttm_init(struct amdgpu_device *adev)
1857 mutex_init(&adev->mman.gtt_window_lock);
1859 /* No others user of address space so set it to 0 */
1860 r = ttm_bo_device_init(&adev->mman.bdev,
1862 adev_to_drm(adev)->anon_inode->i_mapping,
1863 adev_to_drm(adev)->vma_offset_manager,
1864 dma_addressing_limited(adev->dev));
1866 DRM_ERROR("failed initializing buffer object driver(%d).\n", r);
1869 adev->mman.initialized = true;
1871 /* We opt to avoid OOM on system pages allocations */
1872 adev->mman.bdev.no_retry = true;
1874 /* Initialize VRAM pool with all of VRAM divided into pages */
1875 r = amdgpu_vram_mgr_init(adev);
1877 DRM_ERROR("Failed initializing VRAM heap.\n");
1881 /* Reduce size of CPU-visible VRAM if requested */
1882 vis_vram_limit = (u64)amdgpu_vis_vram_limit * 1024 * 1024;
1883 if (amdgpu_vis_vram_limit > 0 &&
1884 vis_vram_limit <= adev->gmc.visible_vram_size)
1885 adev->gmc.visible_vram_size = vis_vram_limit;
1887 /* Change the size here instead of the init above so only lpfn is affected */
1888 amdgpu_ttm_set_buffer_funcs_status(adev, false);
1890 adev->mman.aper_base_kaddr = ioremap_wc(adev->gmc.aper_base,
1891 adev->gmc.visible_vram_size);
1895 *The reserved vram for firmware must be pinned to the specified
1896 *place on the VRAM, so reserve it early.
1898 r = amdgpu_ttm_fw_reserve_vram_init(adev);
1904 * only NAVI10 and onwards ASIC support for IP discovery.
1905 * If IP discovery enabled, a block of memory should be
1906 * reserved for IP discovey.
1908 if (adev->mman.discovery_bin) {
1909 r = amdgpu_ttm_reserve_tmr(adev);
1914 /* allocate memory as required for VGA
1915 * This is used for VGA emulation and pre-OS scanout buffers to
1916 * avoid display artifacts while transitioning between pre-OS
1918 r = amdgpu_bo_create_kernel_at(adev, 0, adev->mman.stolen_vga_size,
1919 AMDGPU_GEM_DOMAIN_VRAM,
1920 &adev->mman.stolen_vga_memory,
1924 r = amdgpu_bo_create_kernel_at(adev, adev->mman.stolen_vga_size,
1925 adev->mman.stolen_extended_size,
1926 AMDGPU_GEM_DOMAIN_VRAM,
1927 &adev->mman.stolen_extended_memory,
1932 DRM_INFO("amdgpu: %uM of VRAM memory ready\n",
1933 (unsigned) (adev->gmc.real_vram_size / (1024 * 1024)));
1935 /* Compute GTT size, either bsaed on 3/4th the size of RAM size
1936 * or whatever the user passed on module init */
1937 if (amdgpu_gtt_size == -1) {
1941 gtt_size = min(max((AMDGPU_DEFAULT_GTT_SIZE_MB << 20),
1942 adev->gmc.mc_vram_size),
1943 ((uint64_t)si.totalram * si.mem_unit * 3/4));
1946 gtt_size = (uint64_t)amdgpu_gtt_size << 20;
1948 /* Initialize GTT memory pool */
1949 r = amdgpu_gtt_mgr_init(adev, gtt_size);
1951 DRM_ERROR("Failed initializing GTT heap.\n");
1954 DRM_INFO("amdgpu: %uM of GTT memory ready.\n",
1955 (unsigned)(gtt_size / (1024 * 1024)));
1957 /* Initialize various on-chip memory pools */
1958 r = amdgpu_ttm_init_on_chip(adev, AMDGPU_PL_GDS, adev->gds.gds_size);
1960 DRM_ERROR("Failed initializing GDS heap.\n");
1964 r = amdgpu_ttm_init_on_chip(adev, AMDGPU_PL_GWS, adev->gds.gws_size);
1966 DRM_ERROR("Failed initializing gws heap.\n");
1970 r = amdgpu_ttm_init_on_chip(adev, AMDGPU_PL_OA, adev->gds.oa_size);
1972 DRM_ERROR("Failed initializing oa heap.\n");
1980 * amdgpu_ttm_late_init - Handle any late initialization for amdgpu_ttm
1982 void amdgpu_ttm_late_init(struct amdgpu_device *adev)
1984 /* return the VGA stolen memory (if any) back to VRAM */
1985 if (!adev->mman.keep_stolen_vga_memory)
1986 amdgpu_bo_free_kernel(&adev->mman.stolen_vga_memory, NULL, NULL);
1987 amdgpu_bo_free_kernel(&adev->mman.stolen_extended_memory, NULL, NULL);
1991 * amdgpu_ttm_fini - De-initialize the TTM memory pools
1993 void amdgpu_ttm_fini(struct amdgpu_device *adev)
1995 if (!adev->mman.initialized)
1998 amdgpu_ttm_training_reserve_vram_fini(adev);
1999 /* return the stolen vga memory back to VRAM */
2000 if (adev->mman.keep_stolen_vga_memory)
2001 amdgpu_bo_free_kernel(&adev->mman.stolen_vga_memory, NULL, NULL);
2002 /* return the IP Discovery TMR memory back to VRAM */
2003 amdgpu_bo_free_kernel(&adev->mman.discovery_memory, NULL, NULL);
2004 amdgpu_ttm_fw_reserve_vram_fini(adev);
2006 if (adev->mman.aper_base_kaddr)
2007 iounmap(adev->mman.aper_base_kaddr);
2008 adev->mman.aper_base_kaddr = NULL;
2010 amdgpu_vram_mgr_fini(adev);
2011 amdgpu_gtt_mgr_fini(adev);
2012 ttm_range_man_fini(&adev->mman.bdev, AMDGPU_PL_GDS);
2013 ttm_range_man_fini(&adev->mman.bdev, AMDGPU_PL_GWS);
2014 ttm_range_man_fini(&adev->mman.bdev, AMDGPU_PL_OA);
2015 ttm_bo_device_release(&adev->mman.bdev);
2016 adev->mman.initialized = false;
2017 DRM_INFO("amdgpu: ttm finalized\n");
2021 * amdgpu_ttm_set_buffer_funcs_status - enable/disable use of buffer functions
2023 * @adev: amdgpu_device pointer
2024 * @enable: true when we can use buffer functions.
2026 * Enable/disable use of buffer functions during suspend/resume. This should
2027 * only be called at bootup or when userspace isn't running.
2029 void amdgpu_ttm_set_buffer_funcs_status(struct amdgpu_device *adev, bool enable)
2031 struct ttm_resource_manager *man = ttm_manager_type(&adev->mman.bdev, TTM_PL_VRAM);
2035 if (!adev->mman.initialized || amdgpu_in_reset(adev) ||
2036 adev->mman.buffer_funcs_enabled == enable)
2040 struct amdgpu_ring *ring;
2041 struct drm_gpu_scheduler *sched;
2043 ring = adev->mman.buffer_funcs_ring;
2044 sched = &ring->sched;
2045 r = drm_sched_entity_init(&adev->mman.entity,
2046 DRM_SCHED_PRIORITY_KERNEL, &sched,
2049 DRM_ERROR("Failed setting up TTM BO move entity (%d)\n",
2054 drm_sched_entity_destroy(&adev->mman.entity);
2055 dma_fence_put(man->move);
2059 /* this just adjusts TTM size idea, which sets lpfn to the correct value */
2061 size = adev->gmc.real_vram_size;
2063 size = adev->gmc.visible_vram_size;
2064 man->size = size >> PAGE_SHIFT;
2065 adev->mman.buffer_funcs_enabled = enable;
2068 int amdgpu_mmap(struct file *filp, struct vm_area_struct *vma)
2070 struct drm_file *file_priv = filp->private_data;
2071 struct amdgpu_device *adev = drm_to_adev(file_priv->minor->dev);
2076 return ttm_bo_mmap(filp, vma, &adev->mman.bdev);
2079 int amdgpu_copy_buffer(struct amdgpu_ring *ring, uint64_t src_offset,
2080 uint64_t dst_offset, uint32_t byte_count,
2081 struct dma_resv *resv,
2082 struct dma_fence **fence, bool direct_submit,
2083 bool vm_needs_flush, bool tmz)
2085 enum amdgpu_ib_pool_type pool = direct_submit ? AMDGPU_IB_POOL_DIRECT :
2086 AMDGPU_IB_POOL_DELAYED;
2087 struct amdgpu_device *adev = ring->adev;
2088 struct amdgpu_job *job;
2091 unsigned num_loops, num_dw;
2095 if (direct_submit && !ring->sched.ready) {
2096 DRM_ERROR("Trying to move memory with ring turned off.\n");
2100 max_bytes = adev->mman.buffer_funcs->copy_max_bytes;
2101 num_loops = DIV_ROUND_UP(byte_count, max_bytes);
2102 num_dw = ALIGN(num_loops * adev->mman.buffer_funcs->copy_num_dw, 8);
2104 r = amdgpu_job_alloc_with_ib(adev, num_dw * 4, pool, &job);
2108 if (vm_needs_flush) {
2109 job->vm_pd_addr = amdgpu_gmc_pd_addr(adev->gart.bo);
2110 job->vm_needs_flush = true;
2113 r = amdgpu_sync_resv(adev, &job->sync, resv,
2115 AMDGPU_FENCE_OWNER_UNDEFINED);
2117 DRM_ERROR("sync failed (%d).\n", r);
2122 for (i = 0; i < num_loops; i++) {
2123 uint32_t cur_size_in_bytes = min(byte_count, max_bytes);
2125 amdgpu_emit_copy_buffer(adev, &job->ibs[0], src_offset,
2126 dst_offset, cur_size_in_bytes, tmz);
2128 src_offset += cur_size_in_bytes;
2129 dst_offset += cur_size_in_bytes;
2130 byte_count -= cur_size_in_bytes;
2133 amdgpu_ring_pad_ib(ring, &job->ibs[0]);
2134 WARN_ON(job->ibs[0].length_dw > num_dw);
2136 r = amdgpu_job_submit_direct(job, ring, fence);
2138 r = amdgpu_job_submit(job, &adev->mman.entity,
2139 AMDGPU_FENCE_OWNER_UNDEFINED, fence);
2146 amdgpu_job_free(job);
2147 DRM_ERROR("Error scheduling IBs (%d)\n", r);
2151 int amdgpu_fill_buffer(struct amdgpu_bo *bo,
2153 struct dma_resv *resv,
2154 struct dma_fence **fence)
2156 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
2157 uint32_t max_bytes = adev->mman.buffer_funcs->fill_max_bytes;
2158 struct amdgpu_ring *ring = adev->mman.buffer_funcs_ring;
2160 struct drm_mm_node *mm_node;
2161 unsigned long num_pages;
2162 unsigned int num_loops, num_dw;
2164 struct amdgpu_job *job;
2167 if (!adev->mman.buffer_funcs_enabled) {
2168 DRM_ERROR("Trying to clear memory with ring turned off.\n");
2172 if (bo->tbo.mem.mem_type == TTM_PL_TT) {
2173 r = amdgpu_ttm_alloc_gart(&bo->tbo);
2178 num_pages = bo->tbo.num_pages;
2179 mm_node = bo->tbo.mem.mm_node;
2182 uint64_t byte_count = mm_node->size << PAGE_SHIFT;
2184 num_loops += DIV_ROUND_UP_ULL(byte_count, max_bytes);
2185 num_pages -= mm_node->size;
2188 num_dw = num_loops * adev->mman.buffer_funcs->fill_num_dw;
2190 /* for IB padding */
2193 r = amdgpu_job_alloc_with_ib(adev, num_dw * 4, AMDGPU_IB_POOL_DELAYED,
2199 r = amdgpu_sync_resv(adev, &job->sync, resv,
2201 AMDGPU_FENCE_OWNER_UNDEFINED);
2203 DRM_ERROR("sync failed (%d).\n", r);
2208 num_pages = bo->tbo.num_pages;
2209 mm_node = bo->tbo.mem.mm_node;
2212 uint64_t byte_count = mm_node->size << PAGE_SHIFT;
2215 dst_addr = amdgpu_mm_node_addr(&bo->tbo, mm_node, &bo->tbo.mem);
2216 while (byte_count) {
2217 uint32_t cur_size_in_bytes = min_t(uint64_t, byte_count,
2220 amdgpu_emit_fill_buffer(adev, &job->ibs[0], src_data,
2221 dst_addr, cur_size_in_bytes);
2223 dst_addr += cur_size_in_bytes;
2224 byte_count -= cur_size_in_bytes;
2227 num_pages -= mm_node->size;
2231 amdgpu_ring_pad_ib(ring, &job->ibs[0]);
2232 WARN_ON(job->ibs[0].length_dw > num_dw);
2233 r = amdgpu_job_submit(job, &adev->mman.entity,
2234 AMDGPU_FENCE_OWNER_UNDEFINED, fence);
2241 amdgpu_job_free(job);
2245 #if defined(CONFIG_DEBUG_FS)
2247 static int amdgpu_mm_dump_table(struct seq_file *m, void *data)
2249 struct drm_info_node *node = (struct drm_info_node *)m->private;
2250 unsigned ttm_pl = (uintptr_t)node->info_ent->data;
2251 struct drm_device *dev = node->minor->dev;
2252 struct amdgpu_device *adev = drm_to_adev(dev);
2253 struct ttm_resource_manager *man = ttm_manager_type(&adev->mman.bdev, ttm_pl);
2254 struct drm_printer p = drm_seq_file_printer(m);
2256 man->func->debug(man, &p);
2260 static const struct drm_info_list amdgpu_ttm_debugfs_list[] = {
2261 {"amdgpu_vram_mm", amdgpu_mm_dump_table, 0, (void *)TTM_PL_VRAM},
2262 {"amdgpu_gtt_mm", amdgpu_mm_dump_table, 0, (void *)TTM_PL_TT},
2263 {"amdgpu_gds_mm", amdgpu_mm_dump_table, 0, (void *)AMDGPU_PL_GDS},
2264 {"amdgpu_gws_mm", amdgpu_mm_dump_table, 0, (void *)AMDGPU_PL_GWS},
2265 {"amdgpu_oa_mm", amdgpu_mm_dump_table, 0, (void *)AMDGPU_PL_OA},
2266 {"ttm_page_pool", ttm_page_alloc_debugfs, 0, NULL},
2267 #ifdef CONFIG_SWIOTLB
2268 {"ttm_dma_page_pool", ttm_dma_page_alloc_debugfs, 0, NULL}
2273 * amdgpu_ttm_vram_read - Linear read access to VRAM
2275 * Accesses VRAM via MMIO for debugging purposes.
2277 static ssize_t amdgpu_ttm_vram_read(struct file *f, char __user *buf,
2278 size_t size, loff_t *pos)
2280 struct amdgpu_device *adev = file_inode(f)->i_private;
2283 if (size & 0x3 || *pos & 0x3)
2286 if (*pos >= adev->gmc.mc_vram_size)
2289 size = min(size, (size_t)(adev->gmc.mc_vram_size - *pos));
2291 size_t bytes = min(size, AMDGPU_TTM_VRAM_MAX_DW_READ * 4);
2292 uint32_t value[AMDGPU_TTM_VRAM_MAX_DW_READ];
2294 amdgpu_device_vram_access(adev, *pos, value, bytes, false);
2295 if (copy_to_user(buf, value, bytes))
2308 * amdgpu_ttm_vram_write - Linear write access to VRAM
2310 * Accesses VRAM via MMIO for debugging purposes.
2312 static ssize_t amdgpu_ttm_vram_write(struct file *f, const char __user *buf,
2313 size_t size, loff_t *pos)
2315 struct amdgpu_device *adev = file_inode(f)->i_private;
2319 if (size & 0x3 || *pos & 0x3)
2322 if (*pos >= adev->gmc.mc_vram_size)
2326 unsigned long flags;
2329 if (*pos >= adev->gmc.mc_vram_size)
2332 r = get_user(value, (uint32_t *)buf);
2336 spin_lock_irqsave(&adev->mmio_idx_lock, flags);
2337 WREG32_NO_KIQ(mmMM_INDEX, ((uint32_t)*pos) | 0x80000000);
2338 WREG32_NO_KIQ(mmMM_INDEX_HI, *pos >> 31);
2339 WREG32_NO_KIQ(mmMM_DATA, value);
2340 spin_unlock_irqrestore(&adev->mmio_idx_lock, flags);
2351 static const struct file_operations amdgpu_ttm_vram_fops = {
2352 .owner = THIS_MODULE,
2353 .read = amdgpu_ttm_vram_read,
2354 .write = amdgpu_ttm_vram_write,
2355 .llseek = default_llseek,
2358 #ifdef CONFIG_DRM_AMDGPU_GART_DEBUGFS
2361 * amdgpu_ttm_gtt_read - Linear read access to GTT memory
2363 static ssize_t amdgpu_ttm_gtt_read(struct file *f, char __user *buf,
2364 size_t size, loff_t *pos)
2366 struct amdgpu_device *adev = file_inode(f)->i_private;
2371 loff_t p = *pos / PAGE_SIZE;
2372 unsigned off = *pos & ~PAGE_MASK;
2373 size_t cur_size = min_t(size_t, size, PAGE_SIZE - off);
2377 if (p >= adev->gart.num_cpu_pages)
2380 page = adev->gart.pages[p];
2385 r = copy_to_user(buf, ptr, cur_size);
2386 kunmap(adev->gart.pages[p]);
2388 r = clear_user(buf, cur_size);
2402 static const struct file_operations amdgpu_ttm_gtt_fops = {
2403 .owner = THIS_MODULE,
2404 .read = amdgpu_ttm_gtt_read,
2405 .llseek = default_llseek
2411 * amdgpu_iomem_read - Virtual read access to GPU mapped memory
2413 * This function is used to read memory that has been mapped to the
2414 * GPU and the known addresses are not physical addresses but instead
2415 * bus addresses (e.g., what you'd put in an IB or ring buffer).
2417 static ssize_t amdgpu_iomem_read(struct file *f, char __user *buf,
2418 size_t size, loff_t *pos)
2420 struct amdgpu_device *adev = file_inode(f)->i_private;
2421 struct iommu_domain *dom;
2425 /* retrieve the IOMMU domain if any for this device */
2426 dom = iommu_get_domain_for_dev(adev->dev);
2429 phys_addr_t addr = *pos & PAGE_MASK;
2430 loff_t off = *pos & ~PAGE_MASK;
2431 size_t bytes = PAGE_SIZE - off;
2436 bytes = bytes < size ? bytes : size;
2438 /* Translate the bus address to a physical address. If
2439 * the domain is NULL it means there is no IOMMU active
2440 * and the address translation is the identity
2442 addr = dom ? iommu_iova_to_phys(dom, addr) : addr;
2444 pfn = addr >> PAGE_SHIFT;
2445 if (!pfn_valid(pfn))
2448 p = pfn_to_page(pfn);
2449 if (p->mapping != adev->mman.bdev.dev_mapping)
2453 r = copy_to_user(buf, ptr + off, bytes);
2467 * amdgpu_iomem_write - Virtual write access to GPU mapped memory
2469 * This function is used to write memory that has been mapped to the
2470 * GPU and the known addresses are not physical addresses but instead
2471 * bus addresses (e.g., what you'd put in an IB or ring buffer).
2473 static ssize_t amdgpu_iomem_write(struct file *f, const char __user *buf,
2474 size_t size, loff_t *pos)
2476 struct amdgpu_device *adev = file_inode(f)->i_private;
2477 struct iommu_domain *dom;
2481 dom = iommu_get_domain_for_dev(adev->dev);
2484 phys_addr_t addr = *pos & PAGE_MASK;
2485 loff_t off = *pos & ~PAGE_MASK;
2486 size_t bytes = PAGE_SIZE - off;
2491 bytes = bytes < size ? bytes : size;
2493 addr = dom ? iommu_iova_to_phys(dom, addr) : addr;
2495 pfn = addr >> PAGE_SHIFT;
2496 if (!pfn_valid(pfn))
2499 p = pfn_to_page(pfn);
2500 if (p->mapping != adev->mman.bdev.dev_mapping)
2504 r = copy_from_user(ptr + off, buf, bytes);
2517 static const struct file_operations amdgpu_ttm_iomem_fops = {
2518 .owner = THIS_MODULE,
2519 .read = amdgpu_iomem_read,
2520 .write = amdgpu_iomem_write,
2521 .llseek = default_llseek
2524 static const struct {
2526 const struct file_operations *fops;
2528 } ttm_debugfs_entries[] = {
2529 { "amdgpu_vram", &amdgpu_ttm_vram_fops, TTM_PL_VRAM },
2530 #ifdef CONFIG_DRM_AMDGPU_GART_DEBUGFS
2531 { "amdgpu_gtt", &amdgpu_ttm_gtt_fops, TTM_PL_TT },
2533 { "amdgpu_iomem", &amdgpu_ttm_iomem_fops, TTM_PL_SYSTEM },
2538 int amdgpu_ttm_debugfs_init(struct amdgpu_device *adev)
2540 #if defined(CONFIG_DEBUG_FS)
2543 struct drm_minor *minor = adev_to_drm(adev)->primary;
2544 struct dentry *ent, *root = minor->debugfs_root;
2546 for (count = 0; count < ARRAY_SIZE(ttm_debugfs_entries); count++) {
2547 ent = debugfs_create_file(
2548 ttm_debugfs_entries[count].name,
2549 S_IFREG | S_IRUGO, root,
2551 ttm_debugfs_entries[count].fops);
2553 return PTR_ERR(ent);
2554 if (ttm_debugfs_entries[count].domain == TTM_PL_VRAM)
2555 i_size_write(ent->d_inode, adev->gmc.mc_vram_size);
2556 else if (ttm_debugfs_entries[count].domain == TTM_PL_TT)
2557 i_size_write(ent->d_inode, adev->gmc.gart_size);
2558 adev->mman.debugfs_entries[count] = ent;
2561 count = ARRAY_SIZE(amdgpu_ttm_debugfs_list);
2563 #ifdef CONFIG_SWIOTLB
2564 if (!(adev->need_swiotlb && swiotlb_nr_tbl()))
2568 return amdgpu_debugfs_add_files(adev, amdgpu_ttm_debugfs_list, count);