drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c

   1 /*
   2  * Copyright 2009 Jerome Glisse.
   3  * All Rights Reserved.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the
   7  * "Software"), to deal in the Software without restriction, including
   8  * without limitation the rights to use, copy, modify, merge, publish,
   9  * distribute, sub license, and/or sell copies of the Software, and to
  10  * permit persons to whom the Software is furnished to do so, subject to
  11  * the following conditions:
  12  *
  13  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  14  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  15  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  16  * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
  17  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  18  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  19  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  20  *
  21  * The above copyright notice and this permission notice (including the
  22  * next paragraph) shall be included in all copies or substantial portions
  23  * of the Software.
  24  *
  25  */
  26 /*
  27  * Authors:
  28  *    Jerome Glisse <glisse@freedesktop.org>
  29  *    Thomas Hellstrom <thomas-at-tungstengraphics-dot-com>
  30  *    Dave Airlie
  31  */
  32
  33 #include <linux/dma-mapping.h>
  34 #include <linux/iommu.h>
  35 #include <linux/hmm.h>
  36 #include <linux/pagemap.h>
  37 #include <linux/sched/task.h>
  38 #include <linux/sched/mm.h>
  39 #include <linux/seq_file.h>
  40 #include <linux/slab.h>
  41 #include <linux/swap.h>
  42 #include <linux/swiotlb.h>
  43 #include <linux/dma-buf.h>
  44 #include <linux/sizes.h>
  45
  46 #include <drm/ttm/ttm_bo_api.h>
  47 #include <drm/ttm/ttm_bo_driver.h>
  48 #include <drm/ttm/ttm_placement.h>
  49
  50 #include <drm/amdgpu_drm.h>
  51
  52 #include "amdgpu.h"
  53 #include "amdgpu_object.h"
  54 #include "amdgpu_trace.h"
  55 #include "amdgpu_amdkfd.h"
  56 #include "amdgpu_sdma.h"
  57 #include "amdgpu_ras.h"
  58 #include "amdgpu_atomfirmware.h"
  59 #include "amdgpu_res_cursor.h"
  60 #include "bif/bif_4_1_d.h"
  61
  62 #define AMDGPU_TTM_VRAM_MAX_DW_READ     (size_t)128
  63
  64 static int amdgpu_ttm_backend_bind(struct ttm_bo_device *bdev,
  65                                    struct ttm_tt *ttm,
  66                                    struct ttm_resource *bo_mem);
  67 static void amdgpu_ttm_backend_unbind(struct ttm_bo_device *bdev,
  68                                       struct ttm_tt *ttm);
  69
  70 static int amdgpu_ttm_init_on_chip(struct amdgpu_device *adev,
  71                                     unsigned int type,
  72                                     uint64_t size_in_page)
  73 {
  74         return ttm_range_man_init(&adev->mman.bdev, type,
  75                                   false, size_in_page);
  76 }
  77
  78 /**
  79  * amdgpu_evict_flags - Compute placement flags
  80  *
  81  * @bo: The buffer object to evict
  82  * @placement: Possible destination(s) for evicted BO
  83  *
  84  * Fill in placement data when ttm_bo_evict() is called
  85  */
  86 static void amdgpu_evict_flags(struct ttm_buffer_object *bo,
  87                                 struct ttm_placement *placement)
  88 {
  89         struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev);
  90         struct amdgpu_bo *abo;
  91         static const struct ttm_place placements = {
  92                 .fpfn = 0,
  93                 .lpfn = 0,
  94                 .mem_type = TTM_PL_SYSTEM,
  95                 .flags = 0
  96         };
  97
  98         /* Don't handle scatter gather BOs */
  99         if (bo->type == ttm_bo_type_sg) {
 100                 placement->num_placement = 0;
 101                 placement->num_busy_placement = 0;
 102                 return;
 103         }
 104
 105         /* Object isn't an AMDGPU object so ignore */
 106         if (!amdgpu_bo_is_amdgpu_bo(bo)) {
 107                 placement->placement = &placements;
 108                 placement->busy_placement = &placements;
 109                 placement->num_placement = 1;
 110                 placement->num_busy_placement = 1;
 111                 return;
 112         }
 113
 114         abo = ttm_to_amdgpu_bo(bo);
 115         switch (bo->mem.mem_type) {
 116         case AMDGPU_PL_GDS:
 117         case AMDGPU_PL_GWS:
 118         case AMDGPU_PL_OA:
 119                 placement->num_placement = 0;
 120                 placement->num_busy_placement = 0;
 121                 return;
 122
 123         case TTM_PL_VRAM:
 124                 if (!adev->mman.buffer_funcs_enabled) {
 125                         /* Move to system memory */
 126                         amdgpu_bo_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_CPU);
 127                 } else if (!amdgpu_gmc_vram_full_visible(&adev->gmc) &&
 128                            !(abo->flags & AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED) &&
 129                            amdgpu_bo_in_cpu_visible_vram(abo)) {
 130
 131                         /* Try evicting to the CPU inaccessible part of VRAM
 132                          * first, but only set GTT as busy placement, so this
 133                          * BO will be evicted to GTT rather than causing other
 134                          * BOs to be evicted from VRAM
 135                          */
 136                         amdgpu_bo_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_VRAM |
 137                                                          AMDGPU_GEM_DOMAIN_GTT);
 138                         abo->placements[0].fpfn = adev->gmc.visible_vram_size >> PAGE_SHIFT;
 139                         abo->placements[0].lpfn = 0;
 140                         abo->placement.busy_placement = &abo->placements[1];
 141                         abo->placement.num_busy_placement = 1;
 142                 } else {
 143                         /* Move to GTT memory */
 144                         amdgpu_bo_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_GTT);
 145                 }
 146                 break;
 147         case TTM_PL_TT:
 148         default:
 149                 amdgpu_bo_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_CPU);
 150                 break;
 151         }
 152         *placement = abo->placement;
 153 }
 154
 155 /**
 156  * amdgpu_verify_access - Verify access for a mmap call
 157  *
 158  * @bo: The buffer object to map
 159  * @filp: The file pointer from the process performing the mmap
 160  *
 161  * This is called by ttm_bo_mmap() to verify whether a process
 162  * has the right to mmap a BO to their process space.
 163  */
 164 static int amdgpu_verify_access(struct ttm_buffer_object *bo, struct file *filp)
 165 {
 166         struct amdgpu_bo *abo = ttm_to_amdgpu_bo(bo);
 167
 168         /*
 169          * Don't verify access for KFD BOs. They don't have a GEM
 170          * object associated with them.
 171          */
 172         if (abo->kfd_bo)
 173                 return 0;
 174
 175         if (amdgpu_ttm_tt_get_usermm(bo->ttm))
 176                 return -EPERM;
 177         return drm_vma_node_verify_access(&abo->tbo.base.vma_node,
 178                                           filp->private_data);
 179 }
 180
 181 /**
 182  * amdgpu_mm_node_addr - Compute the GPU relative offset of a GTT buffer.
 183  *
 184  * @bo: The bo to assign the memory to.
 185  * @mm_node: Memory manager node for drm allocator.
 186  * @mem: The region where the bo resides.
 187  *
 188  */
 189 static uint64_t amdgpu_mm_node_addr(struct ttm_buffer_object *bo,
 190                                     struct drm_mm_node *mm_node,
 191                                     struct ttm_resource *mem)
 192 {
 193         uint64_t addr = 0;
 194
 195         if (mm_node->start != AMDGPU_BO_INVALID_OFFSET) {
 196                 addr = mm_node->start << PAGE_SHIFT;
 197                 addr += amdgpu_ttm_domain_start(amdgpu_ttm_adev(bo->bdev),
 198                                                 mem->mem_type);
 199         }
 200         return addr;
 201 }
 202
 203 /**
 204  * amdgpu_find_mm_node - Helper function finds the drm_mm_node corresponding to
 205  * @offset. It also modifies the offset to be within the drm_mm_node returned
 206  *
 207  * @mem: The region where the bo resides.
 208  * @offset: The offset that drm_mm_node is used for finding.
 209  *
 210  */
 211 static struct drm_mm_node *amdgpu_find_mm_node(struct ttm_resource *mem,
 212                                                uint64_t *offset)
 213 {
 214         struct drm_mm_node *mm_node = mem->mm_node;
 215
 216         while (*offset >= (mm_node->size << PAGE_SHIFT)) {
 217                 *offset -= (mm_node->size << PAGE_SHIFT);
 218                 ++mm_node;
 219         }
 220         return mm_node;
 221 }
 222
 223 /**
 224  * amdgpu_ttm_map_buffer - Map memory into the GART windows
 225  * @bo: buffer object to map
 226  * @mem: memory object to map
 227  * @mm_cur: range to map
 228  * @num_pages: number of pages to map
 229  * @window: which GART window to use
 230  * @ring: DMA ring to use for the copy
 231  * @tmz: if we should setup a TMZ enabled mapping
 232  * @addr: resulting address inside the MC address space
 233  *
 234  * Setup one of the GART windows to access a specific piece of memory or return
 235  * the physical address for local memory.
 236  */
 237 static int amdgpu_ttm_map_buffer(struct ttm_buffer_object *bo,
 238                                  struct ttm_resource *mem,
 239                                  struct amdgpu_res_cursor *mm_cur,
 240                                  unsigned num_pages, unsigned window,
 241                                  struct amdgpu_ring *ring, bool tmz,
 242                                  uint64_t *addr)
 243 {
 244         struct amdgpu_device *adev = ring->adev;
 245         struct amdgpu_job *job;
 246         unsigned num_dw, num_bytes;
 247         struct dma_fence *fence;
 248         uint64_t src_addr, dst_addr;
 249         void *cpu_addr;
 250         uint64_t flags;
 251         unsigned int i;
 252         int r;
 253
 254         BUG_ON(adev->mman.buffer_funcs->copy_max_bytes <
 255                AMDGPU_GTT_MAX_TRANSFER_SIZE * 8);
 256
 257         /* Map only what can't be accessed directly */
 258         if (!tmz && mem->start != AMDGPU_BO_INVALID_OFFSET) {
 259                 *addr = amdgpu_ttm_domain_start(adev, mem->mem_type) +
 260                         mm_cur->start;
 261                 return 0;
 262         }
 263
 264         *addr = adev->gmc.gart_start;
 265         *addr += (u64)window * AMDGPU_GTT_MAX_TRANSFER_SIZE *
 266                 AMDGPU_GPU_PAGE_SIZE;
 267         *addr += mm_cur->start & ~PAGE_MASK;
 268
 269         num_dw = ALIGN(adev->mman.buffer_funcs->copy_num_dw, 8);
 270         num_bytes = num_pages * 8;
 271
 272         r = amdgpu_job_alloc_with_ib(adev, num_dw * 4 + num_bytes,
 273                                      AMDGPU_IB_POOL_DELAYED, &job);
 274         if (r)
 275                 return r;
 276
 277         src_addr = num_dw * 4;
 278         src_addr += job->ibs[0].gpu_addr;
 279
 280         dst_addr = amdgpu_bo_gpu_offset(adev->gart.bo);
 281         dst_addr += window * AMDGPU_GTT_MAX_TRANSFER_SIZE * 8;
 282         amdgpu_emit_copy_buffer(adev, &job->ibs[0], src_addr,
 283                                 dst_addr, num_bytes, false);
 284
 285         amdgpu_ring_pad_ib(ring, &job->ibs[0]);
 286         WARN_ON(job->ibs[0].length_dw > num_dw);
 287
 288         flags = amdgpu_ttm_tt_pte_flags(adev, bo->ttm, mem);
 289         if (tmz)
 290                 flags |= AMDGPU_PTE_TMZ;
 291
 292         cpu_addr = &job->ibs[0].ptr[num_dw];
 293
 294         if (mem->mem_type == TTM_PL_TT) {
 295                 dma_addr_t *dma_addr;
 296
 297                 dma_addr = &bo->ttm->dma_address[mm_cur->start >> PAGE_SHIFT];
 298                 r = amdgpu_gart_map(adev, 0, num_pages, dma_addr, flags,
 299                                     cpu_addr);
 300                 if (r)
 301                         goto error_free;
 302         } else {
 303                 dma_addr_t dma_address;
 304
 305                 dma_address = mm_cur->start;
 306                 dma_address += adev->vm_manager.vram_base_offset;
 307
 308                 for (i = 0; i < num_pages; ++i) {
 309                         r = amdgpu_gart_map(adev, i << PAGE_SHIFT, 1,
 310                                             &dma_address, flags, cpu_addr);
 311                         if (r)
 312                                 goto error_free;
 313
 314                         dma_address += PAGE_SIZE;
 315                 }
 316         }
 317
 318         r = amdgpu_job_submit(job, &adev->mman.entity,
 319                               AMDGPU_FENCE_OWNER_UNDEFINED, &fence);
 320         if (r)
 321                 goto error_free;
 322
 323         dma_fence_put(fence);
 324
 325         return r;
 326
 327 error_free:
 328         amdgpu_job_free(job);
 329         return r;
 330 }
 331
 332 /**
 333  * amdgpu_copy_ttm_mem_to_mem - Helper function for copy
 334  * @adev: amdgpu device
 335  * @src: buffer/address where to read from
 336  * @dst: buffer/address where to write to
 337  * @size: number of bytes to copy
 338  * @tmz: if a secure copy should be used
 339  * @resv: resv object to sync to
 340  * @f: Returns the last fence if multiple jobs are submitted.
 341  *
 342  * The function copies @size bytes from {src->mem + src->offset} to
 343  * {dst->mem + dst->offset}. src->bo and dst->bo could be same BO for a
 344  * move and different for a BO to BO copy.
 345  *
 346  */
 347 int amdgpu_ttm_copy_mem_to_mem(struct amdgpu_device *adev,
 348                                const struct amdgpu_copy_mem *src,
 349                                const struct amdgpu_copy_mem *dst,
 350                                uint64_t size, bool tmz,
 351                                struct dma_resv *resv,
 352                                struct dma_fence **f)
 353 {
 354         const uint32_t GTT_MAX_BYTES = (AMDGPU_GTT_MAX_TRANSFER_SIZE *
 355                                         AMDGPU_GPU_PAGE_SIZE);
 356
 357         struct amdgpu_ring *ring = adev->mman.buffer_funcs_ring;
 358         struct amdgpu_res_cursor src_mm, dst_mm;
 359         struct dma_fence *fence = NULL;
 360         int r = 0;
 361
 362         if (!adev->mman.buffer_funcs_enabled) {
 363                 DRM_ERROR("Trying to move memory with ring turned off.\n");
 364                 return -EINVAL;
 365         }
 366
 367         amdgpu_res_first(src->mem, src->offset, size, &src_mm);
 368         amdgpu_res_first(dst->mem, dst->offset, size, &dst_mm);
 369
 370         mutex_lock(&adev->mman.gtt_window_lock);
 371         while (src_mm.remaining) {
 372                 uint32_t src_page_offset = src_mm.start & ~PAGE_MASK;
 373                 uint32_t dst_page_offset = dst_mm.start & ~PAGE_MASK;
 374                 struct dma_fence *next;
 375                 uint32_t cur_size;
 376                 uint64_t from, to;
 377
 378                 /* Copy size cannot exceed GTT_MAX_BYTES. So if src or dst
 379                  * begins at an offset, then adjust the size accordingly
 380                  */
 381                 cur_size = max(src_page_offset, dst_page_offset);
 382                 cur_size = min(min3(src_mm.size, dst_mm.size, size),
 383                                (uint64_t)(GTT_MAX_BYTES - cur_size));
 384
 385                 /* Map src to window 0 and dst to window 1. */
 386                 r = amdgpu_ttm_map_buffer(src->bo, src->mem, &src_mm,
 387                                           PFN_UP(cur_size + src_page_offset),
 388                                           0, ring, tmz, &from);
 389                 if (r)
 390                         goto error;
 391
 392                 r = amdgpu_ttm_map_buffer(dst->bo, dst->mem, &dst_mm,
 393                                           PFN_UP(cur_size + dst_page_offset),
 394                                           1, ring, tmz, &to);
 395                 if (r)
 396                         goto error;
 397
 398                 r = amdgpu_copy_buffer(ring, from, to, cur_size,
 399                                        resv, &next, false, true, tmz);
 400                 if (r)
 401                         goto error;
 402
 403                 dma_fence_put(fence);
 404                 fence = next;
 405
 406                 amdgpu_res_next(&src_mm, cur_size);
 407                 amdgpu_res_next(&dst_mm, cur_size);
 408         }
 409 error:
 410         mutex_unlock(&adev->mman.gtt_window_lock);
 411         if (f)
 412                 *f = dma_fence_get(fence);
 413         dma_fence_put(fence);
 414         return r;
 415 }
 416
 417 /*
 418  * amdgpu_move_blit - Copy an entire buffer to another buffer
 419  *
 420  * This is a helper called by amdgpu_bo_move() and amdgpu_move_vram_ram() to
 421  * help move buffers to and from VRAM.
 422  */
 423 static int amdgpu_move_blit(struct ttm_buffer_object *bo,
 424                             bool evict,
 425                             struct ttm_resource *new_mem,
 426                             struct ttm_resource *old_mem)
 427 {
 428         struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev);
 429         struct amdgpu_bo *abo = ttm_to_amdgpu_bo(bo);
 430         struct amdgpu_copy_mem src, dst;
 431         struct dma_fence *fence = NULL;
 432         int r;
 433
 434         src.bo = bo;
 435         dst.bo = bo;
 436         src.mem = old_mem;
 437         dst.mem = new_mem;
 438         src.offset = 0;
 439         dst.offset = 0;
 440
 441         r = amdgpu_ttm_copy_mem_to_mem(adev, &src, &dst,
 442                                        new_mem->num_pages << PAGE_SHIFT,
 443                                        amdgpu_bo_encrypted(abo),
 444                                        bo->base.resv, &fence);
 445         if (r)
 446                 goto error;
 447
 448         /* clear the space being freed */
 449         if (old_mem->mem_type == TTM_PL_VRAM &&
 450             (abo->flags & AMDGPU_GEM_CREATE_VRAM_WIPE_ON_RELEASE)) {
 451                 struct dma_fence *wipe_fence = NULL;
 452
 453                 r = amdgpu_fill_buffer(ttm_to_amdgpu_bo(bo), AMDGPU_POISON,
 454                                        NULL, &wipe_fence);
 455                 if (r) {
 456                         goto error;
 457                 } else if (wipe_fence) {
 458                         dma_fence_put(fence);
 459                         fence = wipe_fence;
 460                 }
 461         }
 462
 463         /* Always block for VM page tables before committing the new location */
 464         if (bo->type == ttm_bo_type_kernel)
 465                 r = ttm_bo_move_accel_cleanup(bo, fence, true, false, new_mem);
 466         else
 467                 r = ttm_bo_move_accel_cleanup(bo, fence, evict, true, new_mem);
 468         dma_fence_put(fence);
 469         return r;
 470
 471 error:
 472         if (fence)
 473                 dma_fence_wait(fence, false);
 474         dma_fence_put(fence);
 475         return r;
 476 }
 477
 478 /*
 479  * amdgpu_mem_visible - Check that memory can be accessed by ttm_bo_move_memcpy
 480  *
 481  * Called by amdgpu_bo_move()
 482  */
 483 static bool amdgpu_mem_visible(struct amdgpu_device *adev,
 484                                struct ttm_resource *mem)
 485 {
 486         struct drm_mm_node *nodes = mem->mm_node;
 487
 488         if (mem->mem_type == TTM_PL_SYSTEM ||
 489             mem->mem_type == TTM_PL_TT)
 490                 return true;
 491         if (mem->mem_type != TTM_PL_VRAM)
 492                 return false;
 493
 494         /* ttm_resource_ioremap only supports contiguous memory */
 495         if (nodes->size != mem->num_pages)
 496                 return false;
 497
 498         return ((nodes->start + nodes->size) << PAGE_SHIFT)
 499                 <= adev->gmc.visible_vram_size;
 500 }
 501
 502 /*
 503  * amdgpu_bo_move - Move a buffer object to a new memory location
 504  *
 505  * Called by ttm_bo_handle_move_mem()
 506  */
 507 static int amdgpu_bo_move(struct ttm_buffer_object *bo, bool evict,
 508                           struct ttm_operation_ctx *ctx,
 509                           struct ttm_resource *new_mem,
 510                           struct ttm_place *hop)
 511 {
 512         struct amdgpu_device *adev;
 513         struct amdgpu_bo *abo;
 514         struct ttm_resource *old_mem = &bo->mem;
 515         int r;
 516
 517         if (new_mem->mem_type == TTM_PL_TT) {
 518                 r = amdgpu_ttm_backend_bind(bo->bdev, bo->ttm, new_mem);
 519                 if (r)
 520                         return r;
 521         }
 522
 523         /* Can't move a pinned BO */
 524         abo = ttm_to_amdgpu_bo(bo);
 525         if (WARN_ON_ONCE(abo->tbo.pin_count > 0))
 526                 return -EINVAL;
 527
 528         adev = amdgpu_ttm_adev(bo->bdev);
 529
 530         if (old_mem->mem_type == TTM_PL_SYSTEM && bo->ttm == NULL) {
 531                 ttm_bo_move_null(bo, new_mem);
 532                 goto out;
 533         }
 534         if (old_mem->mem_type == TTM_PL_SYSTEM &&
 535             new_mem->mem_type == TTM_PL_TT) {
 536                 ttm_bo_move_null(bo, new_mem);
 537                 goto out;
 538         }
 539         if (old_mem->mem_type == TTM_PL_TT &&
 540             new_mem->mem_type == TTM_PL_SYSTEM) {
 541                 r = ttm_bo_wait_ctx(bo, ctx);
 542                 if (r)
 543                         return r;
 544
 545                 amdgpu_ttm_backend_unbind(bo->bdev, bo->ttm);
 546                 ttm_resource_free(bo, &bo->mem);
 547                 ttm_bo_assign_mem(bo, new_mem);
 548                 goto out;
 549         }
 550
 551         if (old_mem->mem_type == AMDGPU_PL_GDS ||
 552             old_mem->mem_type == AMDGPU_PL_GWS ||
 553             old_mem->mem_type == AMDGPU_PL_OA ||
 554             new_mem->mem_type == AMDGPU_PL_GDS ||
 555             new_mem->mem_type == AMDGPU_PL_GWS ||
 556             new_mem->mem_type == AMDGPU_PL_OA) {
 557                 /* Nothing to save here */
 558                 ttm_bo_move_null(bo, new_mem);
 559                 goto out;
 560         }
 561
 562         if (adev->mman.buffer_funcs_enabled) {
 563                 if (((old_mem->mem_type == TTM_PL_SYSTEM &&
 564                       new_mem->mem_type == TTM_PL_VRAM) ||
 565                      (old_mem->mem_type == TTM_PL_VRAM &&
 566                       new_mem->mem_type == TTM_PL_SYSTEM))) {
 567                         hop->fpfn = 0;
 568                         hop->lpfn = 0;
 569                         hop->mem_type = TTM_PL_TT;
 570                         hop->flags = 0;
 571                         return -EMULTIHOP;
 572                 }
 573
 574                 r = amdgpu_move_blit(bo, evict, new_mem, old_mem);
 575         } else {
 576                 r = -ENODEV;
 577         }
 578
 579         if (r) {
 580                 /* Check that all memory is CPU accessible */
 581                 if (!amdgpu_mem_visible(adev, old_mem) ||
 582                     !amdgpu_mem_visible(adev, new_mem)) {
 583                         pr_err("Move buffer fallback to memcpy unavailable\n");
 584                         return r;
 585                 }
 586
 587                 r = ttm_bo_move_memcpy(bo, ctx, new_mem);
 588                 if (r)
 589                         return r;
 590         }
 591
 592         if (bo->type == ttm_bo_type_device &&
 593             new_mem->mem_type == TTM_PL_VRAM &&
 594             old_mem->mem_type != TTM_PL_VRAM) {
 595                 /* amdgpu_bo_fault_reserve_notify will re-set this if the CPU
 596                  * accesses the BO after it's moved.
 597                  */
 598                 abo->flags &= ~AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED;
 599         }
 600
 601 out:
 602         /* update statistics */
 603         atomic64_add(bo->base.size, &adev->num_bytes_moved);
 604         amdgpu_bo_move_notify(bo, evict, new_mem);
 605         return 0;
 606 }
 607
 608 /*
 609  * amdgpu_ttm_io_mem_reserve - Reserve a block of memory during a fault
 610  *
 611  * Called by ttm_mem_io_reserve() ultimately via ttm_bo_vm_fault()
 612  */
 613 static int amdgpu_ttm_io_mem_reserve(struct ttm_bo_device *bdev, struct ttm_resource *mem)
 614 {
 615         struct amdgpu_device *adev = amdgpu_ttm_adev(bdev);
 616         struct drm_mm_node *mm_node = mem->mm_node;
 617         size_t bus_size = (size_t)mem->num_pages << PAGE_SHIFT;
 618
 619         switch (mem->mem_type) {
 620         case TTM_PL_SYSTEM:
 621                 /* system memory */
 622                 return 0;
 623         case TTM_PL_TT:
 624                 break;
 625         case TTM_PL_VRAM:
 626                 mem->bus.offset = mem->start << PAGE_SHIFT;
 627                 /* check if it's visible */
 628                 if ((mem->bus.offset + bus_size) > adev->gmc.visible_vram_size)
 629                         return -EINVAL;
 630                 /* Only physically contiguous buffers apply. In a contiguous
 631                  * buffer, size of the first mm_node would match the number of
 632                  * pages in ttm_resource.
 633                  */
 634                 if (adev->mman.aper_base_kaddr &&
 635                     (mm_node->size == mem->num_pages))
 636                         mem->bus.addr = (u8 *)adev->mman.aper_base_kaddr +
 637                                         mem->bus.offset;
 638
 639                 mem->bus.offset += adev->gmc.aper_base;
 640                 mem->bus.is_iomem = true;
 641                 if (adev->gmc.xgmi.connected_to_cpu)
 642                         mem->bus.caching = ttm_cached;
 643                 else
 644                         mem->bus.caching = ttm_write_combined;
 645                 break;
 646         default:
 647                 return -EINVAL;
 648         }
 649         return 0;
 650 }
 651
 652 static unsigned long amdgpu_ttm_io_mem_pfn(struct ttm_buffer_object *bo,
 653                                            unsigned long page_offset)
 654 {
 655         struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev);
 656         uint64_t offset = (page_offset << PAGE_SHIFT);
 657         struct drm_mm_node *mm;
 658
 659         mm = amdgpu_find_mm_node(&bo->mem, &offset);
 660         offset += adev->gmc.aper_base;
 661         return mm->start + (offset >> PAGE_SHIFT);
 662 }
 663
 664 /**
 665  * amdgpu_ttm_domain_start - Returns GPU start address
 666  * @adev: amdgpu device object
 667  * @type: type of the memory
 668  *
 669  * Returns:
 670  * GPU start address of a memory domain
 671  */
 672
 673 uint64_t amdgpu_ttm_domain_start(struct amdgpu_device *adev, uint32_t type)
 674 {
 675         switch (type) {
 676         case TTM_PL_TT:
 677                 return adev->gmc.gart_start;
 678         case TTM_PL_VRAM:
 679                 return adev->gmc.vram_start;
 680         }
 681
 682         return 0;
 683 }
 684
 685 /*
 686  * TTM backend functions.
 687  */
 688 struct amdgpu_ttm_tt {
 689         struct ttm_tt   ttm;
 690         struct drm_gem_object   *gobj;
 691         u64                     offset;
 692         uint64_t                userptr;
 693         struct task_struct      *usertask;
 694         uint32_t                userflags;
 695         bool                    bound;
 696 #if IS_ENABLED(CONFIG_DRM_AMDGPU_USERPTR)
 697         struct hmm_range        *range;
 698 #endif
 699 };
 700
 701 #ifdef CONFIG_DRM_AMDGPU_USERPTR
 702 /*
 703  * amdgpu_ttm_tt_get_user_pages - get device accessible pages that back user
 704  * memory and start HMM tracking CPU page table update
 705  *
 706  * Calling function must call amdgpu_ttm_tt_userptr_range_done() once and only
 707  * once afterwards to stop HMM tracking
 708  */
 709 int amdgpu_ttm_tt_get_user_pages(struct amdgpu_bo *bo, struct page **pages)
 710 {
 711         struct ttm_tt *ttm = bo->tbo.ttm;
 712         struct amdgpu_ttm_tt *gtt = (void *)ttm;
 713         unsigned long start = gtt->userptr;
 714         struct vm_area_struct *vma;
 715         struct hmm_range *range;
 716         unsigned long timeout;
 717         struct mm_struct *mm;
 718         unsigned long i;
 719         int r = 0;
 720
 721         mm = bo->notifier.mm;
 722         if (unlikely(!mm)) {
 723                 DRM_DEBUG_DRIVER("BO is not registered?\n");
 724                 return -EFAULT;
 725         }
 726
 727         /* Another get_user_pages is running at the same time?? */
 728         if (WARN_ON(gtt->range))
 729                 return -EFAULT;
 730
 731         if (!mmget_not_zero(mm)) /* Happens during process shutdown */
 732                 return -ESRCH;
 733
 734         range = kzalloc(sizeof(*range), GFP_KERNEL);
 735         if (unlikely(!range)) {
 736                 r = -ENOMEM;
 737                 goto out;
 738         }
 739         range->notifier = &bo->notifier;
 740         range->start = bo->notifier.interval_tree.start;
 741         range->end = bo->notifier.interval_tree.last + 1;
 742         range->default_flags = HMM_PFN_REQ_FAULT;
 743         if (!amdgpu_ttm_tt_is_readonly(ttm))
 744                 range->default_flags |= HMM_PFN_REQ_WRITE;
 745
 746         range->hmm_pfns = kvmalloc_array(ttm->num_pages,
 747                                          sizeof(*range->hmm_pfns), GFP_KERNEL);
 748         if (unlikely(!range->hmm_pfns)) {
 749                 r = -ENOMEM;
 750                 goto out_free_ranges;
 751         }
 752
 753         mmap_read_lock(mm);
 754         vma = find_vma(mm, start);
 755         if (unlikely(!vma || start < vma->vm_start)) {
 756                 r = -EFAULT;
 757                 goto out_unlock;
 758         }
 759         if (unlikely((gtt->userflags & AMDGPU_GEM_USERPTR_ANONONLY) &&
 760                 vma->vm_file)) {
 761                 r = -EPERM;
 762                 goto out_unlock;
 763         }
 764         mmap_read_unlock(mm);
 765         timeout = jiffies + msecs_to_jiffies(HMM_RANGE_DEFAULT_TIMEOUT);
 766
 767 retry:
 768         range->notifier_seq = mmu_interval_read_begin(&bo->notifier);
 769
 770         mmap_read_lock(mm);
 771         r = hmm_range_fault(range);
 772         mmap_read_unlock(mm);
 773         if (unlikely(r)) {
 774                 /*
 775                  * FIXME: This timeout should encompass the retry from
 776                  * mmu_interval_read_retry() as well.
 777                  */
 778                 if (r == -EBUSY && !time_after(jiffies, timeout))
 779                         goto retry;
 780                 goto out_free_pfns;
 781         }
 782
 783         /*
 784          * Due to default_flags, all pages are HMM_PFN_VALID or
 785          * hmm_range_fault() fails. FIXME: The pages cannot be touched outside
 786          * the notifier_lock, and mmu_interval_read_retry() must be done first.
 787          */
 788         for (i = 0; i < ttm->num_pages; i++)
 789                 pages[i] = hmm_pfn_to_page(range->hmm_pfns[i]);
 790
 791         gtt->range = range;
 792         mmput(mm);
 793
 794         return 0;
 795
 796 out_unlock:
 797         mmap_read_unlock(mm);
 798 out_free_pfns:
 799         kvfree(range->hmm_pfns);
 800 out_free_ranges:
 801         kfree(range);
 802 out:
 803         mmput(mm);
 804         return r;
 805 }
 806
 807 /*
 808  * amdgpu_ttm_tt_userptr_range_done - stop HMM track the CPU page table change
 809  * Check if the pages backing this ttm range have been invalidated
 810  *
 811  * Returns: true if pages are still valid
 812  */
 813 bool amdgpu_ttm_tt_get_user_pages_done(struct ttm_tt *ttm)
 814 {
 815         struct amdgpu_ttm_tt *gtt = (void *)ttm;
 816         bool r = false;
 817
 818         if (!gtt || !gtt->userptr)
 819                 return false;
 820
 821         DRM_DEBUG_DRIVER("user_pages_done 0x%llx pages 0x%x\n",
 822                 gtt->userptr, ttm->num_pages);
 823
 824         WARN_ONCE(!gtt->range || !gtt->range->hmm_pfns,
 825                 "No user pages to check\n");
 826
 827         if (gtt->range) {
 828                 /*
 829                  * FIXME: Must always hold notifier_lock for this, and must
 830                  * not ignore the return code.
 831                  */
 832                 r = mmu_interval_read_retry(gtt->range->notifier,
 833                                          gtt->range->notifier_seq);
 834                 kvfree(gtt->range->hmm_pfns);
 835                 kfree(gtt->range);
 836                 gtt->range = NULL;
 837         }
 838
 839         return !r;
 840 }
 841 #endif
 842
 843 /*
 844  * amdgpu_ttm_tt_set_user_pages - Copy pages in, putting old pages as necessary.
 845  *
 846  * Called by amdgpu_cs_list_validate(). This creates the page list
 847  * that backs user memory and will ultimately be mapped into the device
 848  * address space.
 849  */
 850 void amdgpu_ttm_tt_set_user_pages(struct ttm_tt *ttm, struct page **pages)
 851 {
 852         unsigned long i;
 853
 854         for (i = 0; i < ttm->num_pages; ++i)
 855                 ttm->pages[i] = pages ? pages[i] : NULL;
 856 }
 857
 858 /*
 859  * amdgpu_ttm_tt_pin_userptr - prepare the sg table with the user pages
 860  *
 861  * Called by amdgpu_ttm_backend_bind()
 862  **/
 863 static int amdgpu_ttm_tt_pin_userptr(struct ttm_bo_device *bdev,
 864                                      struct ttm_tt *ttm)
 865 {
 866         struct amdgpu_device *adev = amdgpu_ttm_adev(bdev);
 867         struct amdgpu_ttm_tt *gtt = (void *)ttm;
 868         int r;
 869
 870         int write = !(gtt->userflags & AMDGPU_GEM_USERPTR_READONLY);
 871         enum dma_data_direction direction = write ?
 872                 DMA_BIDIRECTIONAL : DMA_TO_DEVICE;
 873
 874         /* Allocate an SG array and squash pages into it */
 875         r = sg_alloc_table_from_pages(ttm->sg, ttm->pages, ttm->num_pages, 0,
 876                                       ttm->num_pages << PAGE_SHIFT,
 877                                       GFP_KERNEL);
 878         if (r)
 879                 goto release_sg;
 880
 881         /* Map SG to device */
 882         r = dma_map_sgtable(adev->dev, ttm->sg, direction, 0);
 883         if (r)
 884                 goto release_sg;
 885
 886         /* convert SG to linear array of pages and dma addresses */
 887         drm_prime_sg_to_dma_addr_array(ttm->sg, gtt->ttm.dma_address,
 888                                        ttm->num_pages);
 889
 890         return 0;
 891
 892 release_sg:
 893         kfree(ttm->sg);
 894         ttm->sg = NULL;
 895         return r;
 896 }
 897
 898 /*
 899  * amdgpu_ttm_tt_unpin_userptr - Unpin and unmap userptr pages
 900  */
 901 static void amdgpu_ttm_tt_unpin_userptr(struct ttm_bo_device *bdev,
 902                                         struct ttm_tt *ttm)
 903 {
 904         struct amdgpu_device *adev = amdgpu_ttm_adev(bdev);
 905         struct amdgpu_ttm_tt *gtt = (void *)ttm;
 906
 907         int write = !(gtt->userflags & AMDGPU_GEM_USERPTR_READONLY);
 908         enum dma_data_direction direction = write ?
 909                 DMA_BIDIRECTIONAL : DMA_TO_DEVICE;
 910
 911         /* double check that we don't free the table twice */
 912         if (!ttm->sg->sgl)
 913                 return;
 914
 915         /* unmap the pages mapped to the device */
 916         dma_unmap_sgtable(adev->dev, ttm->sg, direction, 0);
 917         sg_free_table(ttm->sg);
 918
 919 #if IS_ENABLED(CONFIG_DRM_AMDGPU_USERPTR)
 920         if (gtt->range) {
 921                 unsigned long i;
 922
 923                 for (i = 0; i < ttm->num_pages; i++) {
 924                         if (ttm->pages[i] !=
 925                             hmm_pfn_to_page(gtt->range->hmm_pfns[i]))
 926                                 break;
 927                 }
 928
 929                 WARN((i == ttm->num_pages), "Missing get_user_page_done\n");
 930         }
 931 #endif
 932 }
 933
 934 static int amdgpu_ttm_gart_bind(struct amdgpu_device *adev,
 935                                 struct ttm_buffer_object *tbo,
 936                                 uint64_t flags)
 937 {
 938         struct amdgpu_bo *abo = ttm_to_amdgpu_bo(tbo);
 939         struct ttm_tt *ttm = tbo->ttm;
 940         struct amdgpu_ttm_tt *gtt = (void *)ttm;
 941         int r;
 942
 943         if (amdgpu_bo_encrypted(abo))
 944                 flags |= AMDGPU_PTE_TMZ;
 945
 946         if (abo->flags & AMDGPU_GEM_CREATE_CP_MQD_GFX9) {
 947                 uint64_t page_idx = 1;
 948
 949                 r = amdgpu_gart_bind(adev, gtt->offset, page_idx,
 950                                 ttm->pages, gtt->ttm.dma_address, flags);
 951                 if (r)
 952                         goto gart_bind_fail;
 953
 954                 /* The memory type of the first page defaults to UC. Now
 955                  * modify the memory type to NC from the second page of
 956                  * the BO onward.
 957                  */
 958                 flags &= ~AMDGPU_PTE_MTYPE_VG10_MASK;
 959                 flags |= AMDGPU_PTE_MTYPE_VG10(AMDGPU_MTYPE_NC);
 960
 961                 r = amdgpu_gart_bind(adev,
 962                                 gtt->offset + (page_idx << PAGE_SHIFT),
 963                                 ttm->num_pages - page_idx,
 964                                 &ttm->pages[page_idx],
 965                                 &(gtt->ttm.dma_address[page_idx]), flags);
 966         } else {
 967                 r = amdgpu_gart_bind(adev, gtt->offset, ttm->num_pages,
 968                                      ttm->pages, gtt->ttm.dma_address, flags);
 969         }
 970
 971 gart_bind_fail:
 972         if (r)
 973                 DRM_ERROR("failed to bind %u pages at 0x%08llX\n",
 974                           ttm->num_pages, gtt->offset);
 975
 976         return r;
 977 }
 978
 979 /*
 980  * amdgpu_ttm_backend_bind - Bind GTT memory
 981  *
 982  * Called by ttm_tt_bind() on behalf of ttm_bo_handle_move_mem().
 983  * This handles binding GTT memory to the device address space.
 984  */
 985 static int amdgpu_ttm_backend_bind(struct ttm_bo_device *bdev,
 986                                    struct ttm_tt *ttm,
 987                                    struct ttm_resource *bo_mem)
 988 {
 989         struct amdgpu_device *adev = amdgpu_ttm_adev(bdev);
 990         struct amdgpu_ttm_tt *gtt = (void*)ttm;
 991         uint64_t flags;
 992         int r = 0;
 993
 994         if (!bo_mem)
 995                 return -EINVAL;
 996
 997         if (gtt->bound)
 998                 return 0;
 999
1000         if (gtt->userptr) {
1001                 r = amdgpu_ttm_tt_pin_userptr(bdev, ttm);
1002                 if (r) {
1003                         DRM_ERROR("failed to pin userptr\n");
1004                         return r;
1005                 }
1006         }
1007         if (!ttm->num_pages) {
1008                 WARN(1, "nothing to bind %u pages for mreg %p back %p!\n",
1009                      ttm->num_pages, bo_mem, ttm);
1010         }
1011
1012         if (bo_mem->mem_type == AMDGPU_PL_GDS ||
1013             bo_mem->mem_type == AMDGPU_PL_GWS ||
1014             bo_mem->mem_type == AMDGPU_PL_OA)
1015                 return -EINVAL;
1016
1017         if (!amdgpu_gtt_mgr_has_gart_addr(bo_mem)) {
1018                 gtt->offset = AMDGPU_BO_INVALID_OFFSET;
1019                 return 0;
1020         }
1021
1022         /* compute PTE flags relevant to this BO memory */
1023         flags = amdgpu_ttm_tt_pte_flags(adev, ttm, bo_mem);
1024
1025         /* bind pages into GART page tables */
1026         gtt->offset = (u64)bo_mem->start << PAGE_SHIFT;
1027         r = amdgpu_gart_bind(adev, gtt->offset, ttm->num_pages,
1028                 ttm->pages, gtt->ttm.dma_address, flags);
1029
1030         if (r)
1031                 DRM_ERROR("failed to bind %u pages at 0x%08llX\n",
1032                           ttm->num_pages, gtt->offset);
1033         gtt->bound = true;
1034         return r;
1035 }
1036
1037 /*
1038  * amdgpu_ttm_alloc_gart - Make sure buffer object is accessible either
1039  * through AGP or GART aperture.
1040  *
1041  * If bo is accessible through AGP aperture, then use AGP aperture
1042  * to access bo; otherwise allocate logical space in GART aperture
1043  * and map bo to GART aperture.
1044  */
1045 int amdgpu_ttm_alloc_gart(struct ttm_buffer_object *bo)
1046 {
1047         struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev);
1048         struct ttm_operation_ctx ctx = { false, false };
1049         struct amdgpu_ttm_tt *gtt = (void *)bo->ttm;
1050         struct ttm_resource tmp;
1051         struct ttm_placement placement;
1052         struct ttm_place placements;
1053         uint64_t addr, flags;
1054         int r;
1055
1056         if (bo->mem.start != AMDGPU_BO_INVALID_OFFSET)
1057                 return 0;
1058
1059         addr = amdgpu_gmc_agp_addr(bo);
1060         if (addr != AMDGPU_BO_INVALID_OFFSET) {
1061                 bo->mem.start = addr >> PAGE_SHIFT;
1062         } else {
1063
1064                 /* allocate GART space */
1065                 tmp = bo->mem;
1066                 tmp.mm_node = NULL;
1067                 placement.num_placement = 1;
1068                 placement.placement = &placements;
1069                 placement.num_busy_placement = 1;
1070                 placement.busy_placement = &placements;
1071                 placements.fpfn = 0;
1072                 placements.lpfn = adev->gmc.gart_size >> PAGE_SHIFT;
1073                 placements.mem_type = TTM_PL_TT;
1074                 placements.flags = bo->mem.placement;
1075
1076                 r = ttm_bo_mem_space(bo, &placement, &tmp, &ctx);
1077                 if (unlikely(r))
1078                         return r;
1079
1080                 /* compute PTE flags for this buffer object */
1081                 flags = amdgpu_ttm_tt_pte_flags(adev, bo->ttm, &tmp);
1082
1083                 /* Bind pages */
1084                 gtt->offset = (u64)tmp.start << PAGE_SHIFT;
1085                 r = amdgpu_ttm_gart_bind(adev, bo, flags);
1086                 if (unlikely(r)) {
1087                         ttm_resource_free(bo, &tmp);
1088                         return r;
1089                 }
1090
1091                 ttm_resource_free(bo, &bo->mem);
1092                 bo->mem = tmp;
1093         }
1094
1095         return 0;
1096 }
1097
1098 /*
1099  * amdgpu_ttm_recover_gart - Rebind GTT pages
1100  *
1101  * Called by amdgpu_gtt_mgr_recover() from amdgpu_device_reset() to
1102  * rebind GTT pages during a GPU reset.
1103  */
1104 int amdgpu_ttm_recover_gart(struct ttm_buffer_object *tbo)
1105 {
1106         struct amdgpu_device *adev = amdgpu_ttm_adev(tbo->bdev);
1107         uint64_t flags;
1108         int r;
1109
1110         if (!tbo->ttm)
1111                 return 0;
1112
1113         flags = amdgpu_ttm_tt_pte_flags(adev, tbo->ttm, &tbo->mem);
1114         r = amdgpu_ttm_gart_bind(adev, tbo, flags);
1115
1116         return r;
1117 }
1118
1119 /*
1120  * amdgpu_ttm_backend_unbind - Unbind GTT mapped pages
1121  *
1122  * Called by ttm_tt_unbind() on behalf of ttm_bo_move_ttm() and
1123  * ttm_tt_destroy().
1124  */
1125 static void amdgpu_ttm_backend_unbind(struct ttm_bo_device *bdev,
1126                                       struct ttm_tt *ttm)
1127 {
1128         struct amdgpu_device *adev = amdgpu_ttm_adev(bdev);
1129         struct amdgpu_ttm_tt *gtt = (void *)ttm;
1130         int r;
1131
1132         if (!gtt->bound)
1133                 return;
1134
1135         /* if the pages have userptr pinning then clear that first */
1136         if (gtt->userptr)
1137                 amdgpu_ttm_tt_unpin_userptr(bdev, ttm);
1138
1139         if (gtt->offset == AMDGPU_BO_INVALID_OFFSET)
1140                 return;
1141
1142         /* unbind shouldn't be done for GDS/GWS/OA in ttm_bo_clean_mm */
1143         r = amdgpu_gart_unbind(adev, gtt->offset, ttm->num_pages);
1144         if (r)
1145                 DRM_ERROR("failed to unbind %u pages at 0x%08llX\n",
1146                           gtt->ttm.num_pages, gtt->offset);
1147         gtt->bound = false;
1148 }
1149
1150 static void amdgpu_ttm_backend_destroy(struct ttm_bo_device *bdev,
1151                                        struct ttm_tt *ttm)
1152 {
1153         struct amdgpu_ttm_tt *gtt = (void *)ttm;
1154
1155         amdgpu_ttm_backend_unbind(bdev, ttm);
1156         ttm_tt_destroy_common(bdev, ttm);
1157         if (gtt->usertask)
1158                 put_task_struct(gtt->usertask);
1159
1160         ttm_tt_fini(&gtt->ttm);
1161         kfree(gtt);
1162 }
1163
1164 /**
1165  * amdgpu_ttm_tt_create - Create a ttm_tt object for a given BO
1166  *
1167  * @bo: The buffer object to create a GTT ttm_tt object around
1168  * @page_flags: Page flags to be added to the ttm_tt object
1169  *
1170  * Called by ttm_tt_create().
1171  */
1172 static struct ttm_tt *amdgpu_ttm_tt_create(struct ttm_buffer_object *bo,
1173                                            uint32_t page_flags)
1174 {
1175         struct amdgpu_bo *abo = ttm_to_amdgpu_bo(bo);
1176         struct amdgpu_ttm_tt *gtt;
1177         enum ttm_caching caching;
1178
1179         gtt = kzalloc(sizeof(struct amdgpu_ttm_tt), GFP_KERNEL);
1180         if (gtt == NULL) {
1181                 return NULL;
1182         }
1183         gtt->gobj = &bo->base;
1184
1185         if (abo->flags & AMDGPU_GEM_CREATE_CPU_GTT_USWC)
1186                 caching = ttm_write_combined;
1187         else
1188                 caching = ttm_cached;
1189
1190         /* allocate space for the uninitialized page entries */
1191         if (ttm_sg_tt_init(&gtt->ttm, bo, page_flags, caching)) {
1192                 kfree(gtt);
1193                 return NULL;
1194         }
1195         return &gtt->ttm;
1196 }
1197
1198 /*
1199  * amdgpu_ttm_tt_populate - Map GTT pages visible to the device
1200  *
1201  * Map the pages of a ttm_tt object to an address space visible
1202  * to the underlying device.
1203  */
1204 static int amdgpu_ttm_tt_populate(struct ttm_bo_device *bdev,
1205                                   struct ttm_tt *ttm,
1206                                   struct ttm_operation_ctx *ctx)
1207 {
1208         struct amdgpu_device *adev = amdgpu_ttm_adev(bdev);
1209         struct amdgpu_ttm_tt *gtt = (void *)ttm;
1210
1211         /* user pages are bound by amdgpu_ttm_tt_pin_userptr() */
1212         if (gtt && gtt->userptr) {
1213                 ttm->sg = kzalloc(sizeof(struct sg_table), GFP_KERNEL);
1214                 if (!ttm->sg)
1215                         return -ENOMEM;
1216
1217                 ttm->page_flags |= TTM_PAGE_FLAG_SG;
1218                 return 0;
1219         }
1220
1221         if (ttm->page_flags & TTM_PAGE_FLAG_SG) {
1222                 if (!ttm->sg) {
1223                         struct dma_buf_attachment *attach;
1224                         struct sg_table *sgt;
1225
1226                         attach = gtt->gobj->import_attach;
1227                         sgt = dma_buf_map_attachment(attach, DMA_BIDIRECTIONAL);
1228                         if (IS_ERR(sgt))
1229                                 return PTR_ERR(sgt);
1230
1231                         ttm->sg = sgt;
1232                 }
1233
1234                 drm_prime_sg_to_dma_addr_array(ttm->sg, gtt->ttm.dma_address,
1235                                                ttm->num_pages);
1236                 return 0;
1237         }
1238
1239         return ttm_pool_alloc(&adev->mman.bdev.pool, ttm, ctx);
1240 }
1241
1242 /*
1243  * amdgpu_ttm_tt_unpopulate - unmap GTT pages and unpopulate page arrays
1244  *
1245  * Unmaps pages of a ttm_tt object from the device address space and
1246  * unpopulates the page array backing it.
1247  */
1248 static void amdgpu_ttm_tt_unpopulate(struct ttm_bo_device *bdev,
1249                                      struct ttm_tt *ttm)
1250 {
1251         struct amdgpu_ttm_tt *gtt = (void *)ttm;
1252         struct amdgpu_device *adev;
1253
1254         if (gtt && gtt->userptr) {
1255                 amdgpu_ttm_tt_set_user_pages(ttm, NULL);
1256                 kfree(ttm->sg);
1257                 ttm->page_flags &= ~TTM_PAGE_FLAG_SG;
1258                 return;
1259         }
1260
1261         if (ttm->sg && gtt->gobj->import_attach) {
1262                 struct dma_buf_attachment *attach;
1263
1264                 attach = gtt->gobj->import_attach;
1265                 dma_buf_unmap_attachment(attach, ttm->sg, DMA_BIDIRECTIONAL);
1266                 ttm->sg = NULL;
1267                 return;
1268         }
1269
1270         if (ttm->page_flags & TTM_PAGE_FLAG_SG)
1271                 return;
1272
1273         adev = amdgpu_ttm_adev(bdev);
1274         return ttm_pool_free(&adev->mman.bdev.pool, ttm);
1275 }
1276
1277 /**
1278  * amdgpu_ttm_tt_set_userptr - Initialize userptr GTT ttm_tt for the current
1279  * task
1280  *
1281  * @bo: The ttm_buffer_object to bind this userptr to
1282  * @addr:  The address in the current tasks VM space to use
1283  * @flags: Requirements of userptr object.
1284  *
1285  * Called by amdgpu_gem_userptr_ioctl() to bind userptr pages
1286  * to current task
1287  */
1288 int amdgpu_ttm_tt_set_userptr(struct ttm_buffer_object *bo,
1289                               uint64_t addr, uint32_t flags)
1290 {
1291         struct amdgpu_ttm_tt *gtt;
1292
1293         if (!bo->ttm) {
1294                 /* TODO: We want a separate TTM object type for userptrs */
1295                 bo->ttm = amdgpu_ttm_tt_create(bo, 0);
1296                 if (bo->ttm == NULL)
1297                         return -ENOMEM;
1298         }
1299
1300         gtt = (void *)bo->ttm;
1301         gtt->userptr = addr;
1302         gtt->userflags = flags;
1303
1304         if (gtt->usertask)
1305                 put_task_struct(gtt->usertask);
1306         gtt->usertask = current->group_leader;
1307         get_task_struct(gtt->usertask);
1308
1309         return 0;
1310 }
1311
1312 /*
1313  * amdgpu_ttm_tt_get_usermm - Return memory manager for ttm_tt object
1314  */
1315 struct mm_struct *amdgpu_ttm_tt_get_usermm(struct ttm_tt *ttm)
1316 {
1317         struct amdgpu_ttm_tt *gtt = (void *)ttm;
1318
1319         if (gtt == NULL)
1320                 return NULL;
1321
1322         if (gtt->usertask == NULL)
1323                 return NULL;
1324
1325         return gtt->usertask->mm;
1326 }
1327
1328 /*
1329  * amdgpu_ttm_tt_affect_userptr - Determine if a ttm_tt object lays inside an
1330  * address range for the current task.
1331  *
1332  */
1333 bool amdgpu_ttm_tt_affect_userptr(struct ttm_tt *ttm, unsigned long start,
1334                                   unsigned long end)
1335 {
1336         struct amdgpu_ttm_tt *gtt = (void *)ttm;
1337         unsigned long size;
1338
1339         if (gtt == NULL || !gtt->userptr)
1340                 return false;
1341
1342         /* Return false if no part of the ttm_tt object lies within
1343          * the range
1344          */
1345         size = (unsigned long)gtt->ttm.num_pages * PAGE_SIZE;
1346         if (gtt->userptr > end || gtt->userptr + size <= start)
1347                 return false;
1348
1349         return true;
1350 }
1351
1352 /*
1353  * amdgpu_ttm_tt_is_userptr - Have the pages backing by userptr?
1354  */
1355 bool amdgpu_ttm_tt_is_userptr(struct ttm_tt *ttm)
1356 {
1357         struct amdgpu_ttm_tt *gtt = (void *)ttm;
1358
1359         if (gtt == NULL || !gtt->userptr)
1360                 return false;
1361
1362         return true;
1363 }
1364
1365 /*
1366  * amdgpu_ttm_tt_is_readonly - Is the ttm_tt object read only?
1367  */
1368 bool amdgpu_ttm_tt_is_readonly(struct ttm_tt *ttm)
1369 {
1370         struct amdgpu_ttm_tt *gtt = (void *)ttm;
1371
1372         if (gtt == NULL)
1373                 return false;
1374
1375         return !!(gtt->userflags & AMDGPU_GEM_USERPTR_READONLY);
1376 }
1377
1378 /**
1379  * amdgpu_ttm_tt_pde_flags - Compute PDE flags for ttm_tt object
1380  *
1381  * @ttm: The ttm_tt object to compute the flags for
1382  * @mem: The memory registry backing this ttm_tt object
1383  *
1384  * Figure out the flags to use for a VM PDE (Page Directory Entry).
1385  */
1386 uint64_t amdgpu_ttm_tt_pde_flags(struct ttm_tt *ttm, struct ttm_resource *mem)
1387 {
1388         uint64_t flags = 0;
1389
1390         if (mem && mem->mem_type != TTM_PL_SYSTEM)
1391                 flags |= AMDGPU_PTE_VALID;
1392
1393         if (mem && mem->mem_type == TTM_PL_TT) {
1394                 flags |= AMDGPU_PTE_SYSTEM;
1395
1396                 if (ttm->caching == ttm_cached)
1397                         flags |= AMDGPU_PTE_SNOOPED;
1398         }
1399
1400         if (mem && mem->mem_type == TTM_PL_VRAM &&
1401                         mem->bus.caching == ttm_cached)
1402                 flags |= AMDGPU_PTE_SNOOPED;
1403
1404         return flags;
1405 }
1406
1407 /**
1408  * amdgpu_ttm_tt_pte_flags - Compute PTE flags for ttm_tt object
1409  *
1410  * @adev: amdgpu_device pointer
1411  * @ttm: The ttm_tt object to compute the flags for
1412  * @mem: The memory registry backing this ttm_tt object
1413  *
1414  * Figure out the flags to use for a VM PTE (Page Table Entry).
1415  */
1416 uint64_t amdgpu_ttm_tt_pte_flags(struct amdgpu_device *adev, struct ttm_tt *ttm,
1417                                  struct ttm_resource *mem)
1418 {
1419         uint64_t flags = amdgpu_ttm_tt_pde_flags(ttm, mem);
1420
1421         flags |= adev->gart.gart_pte_flags;
1422         flags |= AMDGPU_PTE_READABLE;
1423
1424         if (!amdgpu_ttm_tt_is_readonly(ttm))
1425                 flags |= AMDGPU_PTE_WRITEABLE;
1426
1427         return flags;
1428 }
1429
1430 /*
1431  * amdgpu_ttm_bo_eviction_valuable - Check to see if we can evict a buffer
1432  * object.
1433  *
1434  * Return true if eviction is sensible. Called by ttm_mem_evict_first() on
1435  * behalf of ttm_bo_mem_force_space() which tries to evict buffer objects until
1436  * it can find space for a new object and by ttm_bo_force_list_clean() which is
1437  * used to clean out a memory space.
1438  */
1439 static bool amdgpu_ttm_bo_eviction_valuable(struct ttm_buffer_object *bo,
1440                                             const struct ttm_place *place)
1441 {
1442         unsigned long num_pages = bo->mem.num_pages;
1443         struct drm_mm_node *node = bo->mem.mm_node;
1444         struct dma_resv_list *flist;
1445         struct dma_fence *f;
1446         int i;
1447
1448         if (bo->type == ttm_bo_type_kernel &&
1449             !amdgpu_vm_evictable(ttm_to_amdgpu_bo(bo)))
1450                 return false;
1451
1452         /* If bo is a KFD BO, check if the bo belongs to the current process.
1453          * If true, then return false as any KFD process needs all its BOs to
1454          * be resident to run successfully
1455          */
1456         flist = dma_resv_get_list(bo->base.resv);
1457         if (flist) {
1458                 for (i = 0; i < flist->shared_count; ++i) {
1459                         f = rcu_dereference_protected(flist->shared[i],
1460                                 dma_resv_held(bo->base.resv));
1461                         if (amdkfd_fence_check_mm(f, current->mm))
1462                                 return false;
1463                 }
1464         }
1465
1466         switch (bo->mem.mem_type) {
1467         case TTM_PL_TT:
1468                 if (amdgpu_bo_is_amdgpu_bo(bo) &&
1469                     amdgpu_bo_encrypted(ttm_to_amdgpu_bo(bo)))
1470                         return false;
1471                 return true;
1472
1473         case TTM_PL_VRAM:
1474                 /* Check each drm MM node individually */
1475                 while (num_pages) {
1476                         if (place->fpfn < (node->start + node->size) &&
1477                             !(place->lpfn && place->lpfn <= node->start))
1478                                 return true;
1479
1480                         num_pages -= node->size;
1481                         ++node;
1482                 }
1483                 return false;
1484
1485         default:
1486                 break;
1487         }
1488
1489         return ttm_bo_eviction_valuable(bo, place);
1490 }
1491
1492 /**
1493  * amdgpu_ttm_access_memory - Read or Write memory that backs a buffer object.
1494  *
1495  * @bo:  The buffer object to read/write
1496  * @offset:  Offset into buffer object
1497  * @buf:  Secondary buffer to write/read from
1498  * @len: Length in bytes of access
1499  * @write:  true if writing
1500  *
1501  * This is used to access VRAM that backs a buffer object via MMIO
1502  * access for debugging purposes.
1503  */
1504 static int amdgpu_ttm_access_memory(struct ttm_buffer_object *bo,
1505                                     unsigned long offset,
1506                                     void *buf, int len, int write)
1507 {
1508         struct amdgpu_bo *abo = ttm_to_amdgpu_bo(bo);
1509         struct amdgpu_device *adev = amdgpu_ttm_adev(abo->tbo.bdev);
1510         struct drm_mm_node *nodes;
1511         uint32_t value = 0;
1512         int ret = 0;
1513         uint64_t pos;
1514         unsigned long flags;
1515
1516         if (bo->mem.mem_type != TTM_PL_VRAM)
1517                 return -EIO;
1518
1519         pos = offset;
1520         nodes = amdgpu_find_mm_node(&abo->tbo.mem, &pos);
1521         pos += (nodes->start << PAGE_SHIFT);
1522
1523         while (len && pos < adev->gmc.mc_vram_size) {
1524                 uint64_t aligned_pos = pos & ~(uint64_t)3;
1525                 uint64_t bytes = 4 - (pos & 3);
1526                 uint32_t shift = (pos & 3) * 8;
1527                 uint32_t mask = 0xffffffff << shift;
1528
1529                 if (len < bytes) {
1530                         mask &= 0xffffffff >> (bytes - len) * 8;
1531                         bytes = len;
1532                 }
1533
1534                 if (mask != 0xffffffff) {
1535                         spin_lock_irqsave(&adev->mmio_idx_lock, flags);
1536                         WREG32_NO_KIQ(mmMM_INDEX, ((uint32_t)aligned_pos) | 0x80000000);
1537                         WREG32_NO_KIQ(mmMM_INDEX_HI, aligned_pos >> 31);
1538                         if (!write || mask != 0xffffffff)
1539                                 value = RREG32_NO_KIQ(mmMM_DATA);
1540                         if (write) {
1541                                 value &= ~mask;
1542                                 value |= (*(uint32_t *)buf << shift) & mask;
1543                                 WREG32_NO_KIQ(mmMM_DATA, value);
1544                         }
1545                         spin_unlock_irqrestore(&adev->mmio_idx_lock, flags);
1546                         if (!write) {
1547                                 value = (value & mask) >> shift;
1548                                 memcpy(buf, &value, bytes);
1549                         }
1550                 } else {
1551                         bytes = (nodes->start + nodes->size) << PAGE_SHIFT;
1552                         bytes = min(bytes - pos, (uint64_t)len & ~0x3ull);
1553
1554                         amdgpu_device_vram_access(adev, pos, (uint32_t *)buf,
1555                                                   bytes, write);
1556                 }
1557
1558                 ret += bytes;
1559                 buf = (uint8_t *)buf + bytes;
1560                 pos += bytes;
1561                 len -= bytes;
1562                 if (pos >= (nodes->start + nodes->size) << PAGE_SHIFT) {
1563                         ++nodes;
1564                         pos = (nodes->start << PAGE_SHIFT);
1565                 }
1566         }
1567
1568         return ret;
1569 }
1570
1571 static void
1572 amdgpu_bo_delete_mem_notify(struct ttm_buffer_object *bo)
1573 {
1574         amdgpu_bo_move_notify(bo, false, NULL);
1575 }
1576
1577 static struct ttm_bo_driver amdgpu_bo_driver = {
1578         .ttm_tt_create = &amdgpu_ttm_tt_create,
1579         .ttm_tt_populate = &amdgpu_ttm_tt_populate,
1580         .ttm_tt_unpopulate = &amdgpu_ttm_tt_unpopulate,
1581         .ttm_tt_destroy = &amdgpu_ttm_backend_destroy,
1582         .eviction_valuable = amdgpu_ttm_bo_eviction_valuable,
1583         .evict_flags = &amdgpu_evict_flags,
1584         .move = &amdgpu_bo_move,
1585         .verify_access = &amdgpu_verify_access,
1586         .delete_mem_notify = &amdgpu_bo_delete_mem_notify,
1587         .release_notify = &amdgpu_bo_release_notify,
1588         .io_mem_reserve = &amdgpu_ttm_io_mem_reserve,
1589         .io_mem_pfn = amdgpu_ttm_io_mem_pfn,
1590         .access_memory = &amdgpu_ttm_access_memory,
1591         .del_from_lru_notify = &amdgpu_vm_del_from_lru_notify
1592 };
1593
1594 /*
1595  * Firmware Reservation functions
1596  */
1597 /**
1598  * amdgpu_ttm_fw_reserve_vram_fini - free fw reserved vram
1599  *
1600  * @adev: amdgpu_device pointer
1601  *
1602  * free fw reserved vram if it has been reserved.
1603  */
1604 static void amdgpu_ttm_fw_reserve_vram_fini(struct amdgpu_device *adev)
1605 {
1606         amdgpu_bo_free_kernel(&adev->mman.fw_vram_usage_reserved_bo,
1607                 NULL, &adev->mman.fw_vram_usage_va);
1608 }
1609
1610 /**
1611  * amdgpu_ttm_fw_reserve_vram_init - create bo vram reservation from fw
1612  *
1613  * @adev: amdgpu_device pointer
1614  *
1615  * create bo vram reservation from fw.
1616  */
1617 static int amdgpu_ttm_fw_reserve_vram_init(struct amdgpu_device *adev)
1618 {
1619         uint64_t vram_size = adev->gmc.visible_vram_size;
1620
1621         adev->mman.fw_vram_usage_va = NULL;
1622         adev->mman.fw_vram_usage_reserved_bo = NULL;
1623
1624         if (adev->mman.fw_vram_usage_size == 0 ||
1625             adev->mman.fw_vram_usage_size > vram_size)
1626                 return 0;
1627
1628         return amdgpu_bo_create_kernel_at(adev,
1629                                           adev->mman.fw_vram_usage_start_offset,
1630                                           adev->mman.fw_vram_usage_size,
1631                                           AMDGPU_GEM_DOMAIN_VRAM,
1632                                           &adev->mman.fw_vram_usage_reserved_bo,
1633                                           &adev->mman.fw_vram_usage_va);
1634 }
1635
1636 /*
1637  * Memoy training reservation functions
1638  */
1639
1640 /**
1641  * amdgpu_ttm_training_reserve_vram_fini - free memory training reserved vram
1642  *
1643  * @adev: amdgpu_device pointer
1644  *
1645  * free memory training reserved vram if it has been reserved.
1646  */
1647 static int amdgpu_ttm_training_reserve_vram_fini(struct amdgpu_device *adev)
1648 {
1649         struct psp_memory_training_context *ctx = &adev->psp.mem_train_ctx;
1650
1651         ctx->init = PSP_MEM_TRAIN_NOT_SUPPORT;
1652         amdgpu_bo_free_kernel(&ctx->c2p_bo, NULL, NULL);
1653         ctx->c2p_bo = NULL;
1654
1655         return 0;
1656 }
1657
1658 static void amdgpu_ttm_training_data_block_init(struct amdgpu_device *adev)
1659 {
1660         struct psp_memory_training_context *ctx = &adev->psp.mem_train_ctx;
1661
1662         memset(ctx, 0, sizeof(*ctx));
1663
1664         ctx->c2p_train_data_offset =
1665                 ALIGN((adev->gmc.mc_vram_size - adev->mman.discovery_tmr_size - SZ_1M), SZ_1M);
1666         ctx->p2c_train_data_offset =
1667                 (adev->gmc.mc_vram_size - GDDR6_MEM_TRAINING_OFFSET);
1668         ctx->train_data_size =
1669                 GDDR6_MEM_TRAINING_DATA_SIZE_IN_BYTES;
1670
1671         DRM_DEBUG("train_data_size:%llx,p2c_train_data_offset:%llx,c2p_train_data_offset:%llx.\n",
1672                         ctx->train_data_size,
1673                         ctx->p2c_train_data_offset,
1674                         ctx->c2p_train_data_offset);
1675 }
1676
1677 /*
1678  * reserve TMR memory at the top of VRAM which holds
1679  * IP Discovery data and is protected by PSP.
1680  */
1681 static int amdgpu_ttm_reserve_tmr(struct amdgpu_device *adev)
1682 {
1683         int ret;
1684         struct psp_memory_training_context *ctx = &adev->psp.mem_train_ctx;
1685         bool mem_train_support = false;
1686
1687         if (!amdgpu_sriov_vf(adev)) {
1688                 ret = amdgpu_mem_train_support(adev);
1689                 if (ret == 1)
1690                         mem_train_support = true;
1691                 else if (ret == -1)
1692                         return -EINVAL;
1693                 else
1694                         DRM_DEBUG("memory training does not support!\n");
1695         }
1696
1697         /*
1698          * Query reserved tmr size through atom firmwareinfo for Sienna_Cichlid and onwards for all
1699          * the use cases (IP discovery/G6 memory training/profiling/diagnostic data.etc)
1700          *
1701          * Otherwise, fallback to legacy approach to check and reserve tmr block for ip
1702          * discovery data and G6 memory training data respectively
1703          */
1704         adev->mman.discovery_tmr_size =
1705                 amdgpu_atomfirmware_get_fw_reserved_fb_size(adev);
1706         if (!adev->mman.discovery_tmr_size)
1707                 adev->mman.discovery_tmr_size = DISCOVERY_TMR_OFFSET;
1708
1709         if (mem_train_support) {
1710                 /* reserve vram for mem train according to TMR location */
1711                 amdgpu_ttm_training_data_block_init(adev);
1712                 ret = amdgpu_bo_create_kernel_at(adev,
1713                                          ctx->c2p_train_data_offset,
1714                                          ctx->train_data_size,
1715                                          AMDGPU_GEM_DOMAIN_VRAM,
1716                                          &ctx->c2p_bo,
1717                                          NULL);
1718                 if (ret) {
1719                         DRM_ERROR("alloc c2p_bo failed(%d)!\n", ret);
1720                         amdgpu_ttm_training_reserve_vram_fini(adev);
1721                         return ret;
1722                 }
1723                 ctx->init = PSP_MEM_TRAIN_RESERVE_SUCCESS;
1724         }
1725
1726         ret = amdgpu_bo_create_kernel_at(adev,
1727                                 adev->gmc.real_vram_size - adev->mman.discovery_tmr_size,
1728                                 adev->mman.discovery_tmr_size,
1729                                 AMDGPU_GEM_DOMAIN_VRAM,
1730                                 &adev->mman.discovery_memory,
1731                                 NULL);
1732         if (ret) {
1733                 DRM_ERROR("alloc tmr failed(%d)!\n", ret);
1734                 amdgpu_bo_free_kernel(&adev->mman.discovery_memory, NULL, NULL);
1735                 return ret;
1736         }
1737
1738         return 0;
1739 }
1740
1741 /*
1742  * amdgpu_ttm_init - Init the memory management (ttm) as well as various
1743  * gtt/vram related fields.
1744  *
1745  * This initializes all of the memory space pools that the TTM layer
1746  * will need such as the GTT space (system memory mapped to the device),
1747  * VRAM (on-board memory), and on-chip memories (GDS, GWS, OA) which
1748  * can be mapped per VMID.
1749  */
1750 int amdgpu_ttm_init(struct amdgpu_device *adev)
1751 {
1752         uint64_t gtt_size;
1753         int r;
1754         u64 vis_vram_limit;
1755
1756         mutex_init(&adev->mman.gtt_window_lock);
1757
1758         /* No others user of address space so set it to 0 */
1759         r = ttm_bo_device_init(&adev->mman.bdev, &amdgpu_bo_driver, adev->dev,
1760                                adev_to_drm(adev)->anon_inode->i_mapping,
1761                                adev_to_drm(adev)->vma_offset_manager,
1762                                adev->need_swiotlb,
1763                                dma_addressing_limited(adev->dev));
1764         if (r) {
1765                 DRM_ERROR("failed initializing buffer object driver(%d).\n", r);
1766                 return r;
1767         }
1768         adev->mman.initialized = true;
1769
1770         /* Initialize VRAM pool with all of VRAM divided into pages */
1771         r = amdgpu_vram_mgr_init(adev);
1772         if (r) {
1773                 DRM_ERROR("Failed initializing VRAM heap.\n");
1774                 return r;
1775         }
1776
1777         /* Reduce size of CPU-visible VRAM if requested */
1778         vis_vram_limit = (u64)amdgpu_vis_vram_limit * 1024 * 1024;
1779         if (amdgpu_vis_vram_limit > 0 &&
1780             vis_vram_limit <= adev->gmc.visible_vram_size)
1781                 adev->gmc.visible_vram_size = vis_vram_limit;
1782
1783         /* Change the size here instead of the init above so only lpfn is affected */
1784         amdgpu_ttm_set_buffer_funcs_status(adev, false);
1785 #ifdef CONFIG_64BIT
1786 #ifdef CONFIG_X86
1787         if (adev->gmc.xgmi.connected_to_cpu)
1788                 adev->mman.aper_base_kaddr = ioremap_cache(adev->gmc.aper_base,
1789                                 adev->gmc.visible_vram_size);
1790
1791         else
1792 #endif
1793                 adev->mman.aper_base_kaddr = ioremap_wc(adev->gmc.aper_base,
1794                                 adev->gmc.visible_vram_size);
1795 #endif
1796
1797         /*
1798          *The reserved vram for firmware must be pinned to the specified
1799          *place on the VRAM, so reserve it early.
1800          */
1801         r = amdgpu_ttm_fw_reserve_vram_init(adev);
1802         if (r) {
1803                 return r;
1804         }
1805
1806         /*
1807          * only NAVI10 and onwards ASIC support for IP discovery.
1808          * If IP discovery enabled, a block of memory should be
1809          * reserved for IP discovey.
1810          */
1811         if (adev->mman.discovery_bin) {
1812                 r = amdgpu_ttm_reserve_tmr(adev);
1813                 if (r)
1814                         return r;
1815         }
1816
1817         /* allocate memory as required for VGA
1818          * This is used for VGA emulation and pre-OS scanout buffers to
1819          * avoid display artifacts while transitioning between pre-OS
1820          * and driver.  */
1821         r = amdgpu_bo_create_kernel_at(adev, 0, adev->mman.stolen_vga_size,
1822                                        AMDGPU_GEM_DOMAIN_VRAM,
1823                                        &adev->mman.stolen_vga_memory,
1824                                        NULL);
1825         if (r)
1826                 return r;
1827         r = amdgpu_bo_create_kernel_at(adev, adev->mman.stolen_vga_size,
1828                                        adev->mman.stolen_extended_size,
1829                                        AMDGPU_GEM_DOMAIN_VRAM,
1830                                        &adev->mman.stolen_extended_memory,
1831                                        NULL);
1832         if (r)
1833                 return r;
1834
1835         DRM_INFO("amdgpu: %uM of VRAM memory ready\n",
1836                  (unsigned) (adev->gmc.real_vram_size / (1024 * 1024)));
1837
1838         /* Compute GTT size, either bsaed on 3/4th the size of RAM size
1839          * or whatever the user passed on module init */
1840         if (amdgpu_gtt_size == -1) {
1841                 struct sysinfo si;
1842
1843                 si_meminfo(&si);
1844                 gtt_size = min(max((AMDGPU_DEFAULT_GTT_SIZE_MB << 20),
1845                                adev->gmc.mc_vram_size),
1846                                ((uint64_t)si.totalram * si.mem_unit * 3/4));
1847         }
1848         else
1849                 gtt_size = (uint64_t)amdgpu_gtt_size << 20;
1850
1851         /* Initialize GTT memory pool */
1852         r = amdgpu_gtt_mgr_init(adev, gtt_size);
1853         if (r) {
1854                 DRM_ERROR("Failed initializing GTT heap.\n");
1855                 return r;
1856         }
1857         DRM_INFO("amdgpu: %uM of GTT memory ready.\n",
1858                  (unsigned)(gtt_size / (1024 * 1024)));
1859
1860         /* Initialize various on-chip memory pools */
1861         r = amdgpu_ttm_init_on_chip(adev, AMDGPU_PL_GDS, adev->gds.gds_size);
1862         if (r) {
1863                 DRM_ERROR("Failed initializing GDS heap.\n");
1864                 return r;
1865         }
1866
1867         r = amdgpu_ttm_init_on_chip(adev, AMDGPU_PL_GWS, adev->gds.gws_size);
1868         if (r) {
1869                 DRM_ERROR("Failed initializing gws heap.\n");
1870                 return r;
1871         }
1872
1873         r = amdgpu_ttm_init_on_chip(adev, AMDGPU_PL_OA, adev->gds.oa_size);
1874         if (r) {
1875                 DRM_ERROR("Failed initializing oa heap.\n");
1876                 return r;
1877         }
1878
1879         return 0;
1880 }
1881
1882 /*
1883  * amdgpu_ttm_fini - De-initialize the TTM memory pools
1884  */
1885 void amdgpu_ttm_fini(struct amdgpu_device *adev)
1886 {
1887         if (!adev->mman.initialized)
1888                 return;
1889
1890         amdgpu_ttm_training_reserve_vram_fini(adev);
1891         /* return the stolen vga memory back to VRAM */
1892         amdgpu_bo_free_kernel(&adev->mman.stolen_vga_memory, NULL, NULL);
1893         amdgpu_bo_free_kernel(&adev->mman.stolen_extended_memory, NULL, NULL);
1894         /* return the IP Discovery TMR memory back to VRAM */
1895         amdgpu_bo_free_kernel(&adev->mman.discovery_memory, NULL, NULL);
1896         amdgpu_ttm_fw_reserve_vram_fini(adev);
1897
1898         if (adev->mman.aper_base_kaddr)
1899                 iounmap(adev->mman.aper_base_kaddr);
1900         adev->mman.aper_base_kaddr = NULL;
1901
1902         amdgpu_vram_mgr_fini(adev);
1903         amdgpu_gtt_mgr_fini(adev);
1904         ttm_range_man_fini(&adev->mman.bdev, AMDGPU_PL_GDS);
1905         ttm_range_man_fini(&adev->mman.bdev, AMDGPU_PL_GWS);
1906         ttm_range_man_fini(&adev->mman.bdev, AMDGPU_PL_OA);
1907         ttm_bo_device_release(&adev->mman.bdev);
1908         adev->mman.initialized = false;
1909         DRM_INFO("amdgpu: ttm finalized\n");
1910 }
1911
1912 /**
1913  * amdgpu_ttm_set_buffer_funcs_status - enable/disable use of buffer functions
1914  *
1915  * @adev: amdgpu_device pointer
1916  * @enable: true when we can use buffer functions.
1917  *
1918  * Enable/disable use of buffer functions during suspend/resume. This should
1919  * only be called at bootup or when userspace isn't running.
1920  */
1921 void amdgpu_ttm_set_buffer_funcs_status(struct amdgpu_device *adev, bool enable)
1922 {
1923         struct ttm_resource_manager *man = ttm_manager_type(&adev->mman.bdev, TTM_PL_VRAM);
1924         uint64_t size;
1925         int r;
1926
1927         if (!adev->mman.initialized || amdgpu_in_reset(adev) ||
1928             adev->mman.buffer_funcs_enabled == enable)
1929                 return;
1930
1931         if (enable) {
1932                 struct amdgpu_ring *ring;
1933                 struct drm_gpu_scheduler *sched;
1934
1935                 ring = adev->mman.buffer_funcs_ring;
1936                 sched = &ring->sched;
1937                 r = drm_sched_entity_init(&adev->mman.entity,
1938                                           DRM_SCHED_PRIORITY_KERNEL, &sched,
1939                                           1, NULL);
1940                 if (r) {
1941                         DRM_ERROR("Failed setting up TTM BO move entity (%d)\n",
1942                                   r);
1943                         return;
1944                 }
1945         } else {
1946                 drm_sched_entity_destroy(&adev->mman.entity);
1947                 dma_fence_put(man->move);
1948                 man->move = NULL;
1949         }
1950
1951         /* this just adjusts TTM size idea, which sets lpfn to the correct value */
1952         if (enable)
1953                 size = adev->gmc.real_vram_size;
1954         else
1955                 size = adev->gmc.visible_vram_size;
1956         man->size = size >> PAGE_SHIFT;
1957         adev->mman.buffer_funcs_enabled = enable;
1958 }
1959
1960 static vm_fault_t amdgpu_ttm_fault(struct vm_fault *vmf)
1961 {
1962         struct ttm_buffer_object *bo = vmf->vma->vm_private_data;
1963         vm_fault_t ret;
1964
1965         ret = ttm_bo_vm_reserve(bo, vmf);
1966         if (ret)
1967                 return ret;
1968
1969         ret = amdgpu_bo_fault_reserve_notify(bo);
1970         if (ret)
1971                 goto unlock;
1972
1973         ret = ttm_bo_vm_fault_reserved(vmf, vmf->vma->vm_page_prot,
1974                                        TTM_BO_VM_NUM_PREFAULT, 1);
1975         if (ret == VM_FAULT_RETRY && !(vmf->flags & FAULT_FLAG_RETRY_NOWAIT))
1976                 return ret;
1977
1978 unlock:
1979         dma_resv_unlock(bo->base.resv);
1980         return ret;
1981 }
1982
1983 static struct vm_operations_struct amdgpu_ttm_vm_ops = {
1984         .fault = amdgpu_ttm_fault,
1985         .open = ttm_bo_vm_open,
1986         .close = ttm_bo_vm_close,
1987         .access = ttm_bo_vm_access
1988 };
1989
1990 int amdgpu_mmap(struct file *filp, struct vm_area_struct *vma)
1991 {
1992         struct drm_file *file_priv = filp->private_data;
1993         struct amdgpu_device *adev = drm_to_adev(file_priv->minor->dev);
1994         int r;
1995
1996         r = ttm_bo_mmap(filp, vma, &adev->mman.bdev);
1997         if (unlikely(r != 0))
1998                 return r;
1999
2000         vma->vm_ops = &amdgpu_ttm_vm_ops;
2001         return 0;
2002 }
2003
2004 int amdgpu_copy_buffer(struct amdgpu_ring *ring, uint64_t src_offset,
2005                        uint64_t dst_offset, uint32_t byte_count,
2006                        struct dma_resv *resv,
2007                        struct dma_fence **fence, bool direct_submit,
2008                        bool vm_needs_flush, bool tmz)
2009 {
2010         enum amdgpu_ib_pool_type pool = direct_submit ? AMDGPU_IB_POOL_DIRECT :
2011                 AMDGPU_IB_POOL_DELAYED;
2012         struct amdgpu_device *adev = ring->adev;
2013         struct amdgpu_job *job;
2014
2015         uint32_t max_bytes;
2016         unsigned num_loops, num_dw;
2017         unsigned i;
2018         int r;
2019
2020         if (direct_submit && !ring->sched.ready) {
2021                 DRM_ERROR("Trying to move memory with ring turned off.\n");
2022                 return -EINVAL;
2023         }
2024
2025         max_bytes = adev->mman.buffer_funcs->copy_max_bytes;
2026         num_loops = DIV_ROUND_UP(byte_count, max_bytes);
2027         num_dw = ALIGN(num_loops * adev->mman.buffer_funcs->copy_num_dw, 8);
2028
2029         r = amdgpu_job_alloc_with_ib(adev, num_dw * 4, pool, &job);
2030         if (r)
2031                 return r;
2032
2033         if (vm_needs_flush) {
2034                 job->vm_pd_addr = amdgpu_gmc_pd_addr(adev->gmc.pdb0_bo ?
2035                                         adev->gmc.pdb0_bo : adev->gart.bo);
2036                 job->vm_needs_flush = true;
2037         }
2038         if (resv) {
2039                 r = amdgpu_sync_resv(adev, &job->sync, resv,
2040                                      AMDGPU_SYNC_ALWAYS,
2041                                      AMDGPU_FENCE_OWNER_UNDEFINED);
2042                 if (r) {
2043                         DRM_ERROR("sync failed (%d).\n", r);
2044                         goto error_free;
2045                 }
2046         }
2047
2048         for (i = 0; i < num_loops; i++) {
2049                 uint32_t cur_size_in_bytes = min(byte_count, max_bytes);
2050
2051                 amdgpu_emit_copy_buffer(adev, &job->ibs[0], src_offset,
2052                                         dst_offset, cur_size_in_bytes, tmz);
2053
2054                 src_offset += cur_size_in_bytes;
2055                 dst_offset += cur_size_in_bytes;
2056                 byte_count -= cur_size_in_bytes;
2057         }
2058
2059         amdgpu_ring_pad_ib(ring, &job->ibs[0]);
2060         WARN_ON(job->ibs[0].length_dw > num_dw);
2061         if (direct_submit)
2062                 r = amdgpu_job_submit_direct(job, ring, fence);
2063         else
2064                 r = amdgpu_job_submit(job, &adev->mman.entity,
2065                                       AMDGPU_FENCE_OWNER_UNDEFINED, fence);
2066         if (r)
2067                 goto error_free;
2068
2069         return r;
2070
2071 error_free:
2072         amdgpu_job_free(job);
2073         DRM_ERROR("Error scheduling IBs (%d)\n", r);
2074         return r;
2075 }
2076
2077 int amdgpu_fill_buffer(struct amdgpu_bo *bo,
2078                        uint32_t src_data,
2079                        struct dma_resv *resv,
2080                        struct dma_fence **fence)
2081 {
2082         struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
2083         uint32_t max_bytes = adev->mman.buffer_funcs->fill_max_bytes;
2084         struct amdgpu_ring *ring = adev->mman.buffer_funcs_ring;
2085
2086         struct drm_mm_node *mm_node;
2087         unsigned long num_pages;
2088         unsigned int num_loops, num_dw;
2089
2090         struct amdgpu_job *job;
2091         int r;
2092
2093         if (!adev->mman.buffer_funcs_enabled) {
2094                 DRM_ERROR("Trying to clear memory with ring turned off.\n");
2095                 return -EINVAL;
2096         }
2097
2098         if (bo->tbo.mem.mem_type == TTM_PL_TT) {
2099                 r = amdgpu_ttm_alloc_gart(&bo->tbo);
2100                 if (r)
2101                         return r;
2102         }
2103
2104         num_pages = bo->tbo.mem.num_pages;
2105         mm_node = bo->tbo.mem.mm_node;
2106         num_loops = 0;
2107         while (num_pages) {
2108                 uint64_t byte_count = mm_node->size << PAGE_SHIFT;
2109
2110                 num_loops += DIV_ROUND_UP_ULL(byte_count, max_bytes);
2111                 num_pages -= mm_node->size;
2112                 ++mm_node;
2113         }
2114         num_dw = num_loops * adev->mman.buffer_funcs->fill_num_dw;
2115
2116         /* for IB padding */
2117         num_dw += 64;
2118
2119         r = amdgpu_job_alloc_with_ib(adev, num_dw * 4, AMDGPU_IB_POOL_DELAYED,
2120                                      &job);
2121         if (r)
2122                 return r;
2123
2124         if (resv) {
2125                 r = amdgpu_sync_resv(adev, &job->sync, resv,
2126                                      AMDGPU_SYNC_ALWAYS,
2127                                      AMDGPU_FENCE_OWNER_UNDEFINED);
2128                 if (r) {
2129                         DRM_ERROR("sync failed (%d).\n", r);
2130                         goto error_free;
2131                 }
2132         }
2133
2134         num_pages = bo->tbo.mem.num_pages;
2135         mm_node = bo->tbo.mem.mm_node;
2136
2137         while (num_pages) {
2138                 uint64_t byte_count = mm_node->size << PAGE_SHIFT;
2139                 uint64_t dst_addr;
2140
2141                 dst_addr = amdgpu_mm_node_addr(&bo->tbo, mm_node, &bo->tbo.mem);
2142                 while (byte_count) {
2143                         uint32_t cur_size_in_bytes = min_t(uint64_t, byte_count,
2144                                                            max_bytes);
2145
2146                         amdgpu_emit_fill_buffer(adev, &job->ibs[0], src_data,
2147                                                 dst_addr, cur_size_in_bytes);
2148
2149                         dst_addr += cur_size_in_bytes;
2150                         byte_count -= cur_size_in_bytes;
2151                 }
2152
2153                 num_pages -= mm_node->size;
2154                 ++mm_node;
2155         }
2156
2157         amdgpu_ring_pad_ib(ring, &job->ibs[0]);
2158         WARN_ON(job->ibs[0].length_dw > num_dw);
2159         r = amdgpu_job_submit(job, &adev->mman.entity,
2160                               AMDGPU_FENCE_OWNER_UNDEFINED, fence);
2161         if (r)
2162                 goto error_free;
2163
2164         return 0;
2165
2166 error_free:
2167         amdgpu_job_free(job);
2168         return r;
2169 }
2170
2171 #if defined(CONFIG_DEBUG_FS)
2172
2173 static int amdgpu_mm_vram_table_show(struct seq_file *m, void *unused)
2174 {
2175         struct amdgpu_device *adev = (struct amdgpu_device *)m->private;
2176         struct ttm_resource_manager *man = ttm_manager_type(&adev->mman.bdev,
2177                                                             TTM_PL_VRAM);
2178         struct drm_printer p = drm_seq_file_printer(m);
2179
2180         man->func->debug(man, &p);
2181         return 0;
2182 }
2183
2184 static int amdgpu_ttm_page_pool_show(struct seq_file *m, void *unused)
2185 {
2186         struct amdgpu_device *adev = (struct amdgpu_device *)m->private;
2187
2188         return ttm_pool_debugfs(&adev->mman.bdev.pool, m);
2189 }
2190
2191 static int amdgpu_mm_tt_table_show(struct seq_file *m, void *unused)
2192 {
2193         struct amdgpu_device *adev = (struct amdgpu_device *)m->private;
2194         struct ttm_resource_manager *man = ttm_manager_type(&adev->mman.bdev,
2195                                                             TTM_PL_TT);
2196         struct drm_printer p = drm_seq_file_printer(m);
2197
2198         man->func->debug(man, &p);
2199         return 0;
2200 }
2201
2202 static int amdgpu_mm_gds_table_show(struct seq_file *m, void *unused)
2203 {
2204         struct amdgpu_device *adev = (struct amdgpu_device *)m->private;
2205         struct ttm_resource_manager *man = ttm_manager_type(&adev->mman.bdev,
2206                                                             AMDGPU_PL_GDS);
2207         struct drm_printer p = drm_seq_file_printer(m);
2208
2209         man->func->debug(man, &p);
2210         return 0;
2211 }
2212
2213 static int amdgpu_mm_gws_table_show(struct seq_file *m, void *unused)
2214 {
2215         struct amdgpu_device *adev = (struct amdgpu_device *)m->private;
2216         struct ttm_resource_manager *man = ttm_manager_type(&adev->mman.bdev,
2217                                                             AMDGPU_PL_GWS);
2218         struct drm_printer p = drm_seq_file_printer(m);
2219
2220         man->func->debug(man, &p);
2221         return 0;
2222 }
2223
2224 static int amdgpu_mm_oa_table_show(struct seq_file *m, void *unused)
2225 {
2226         struct amdgpu_device *adev = (struct amdgpu_device *)m->private;
2227         struct ttm_resource_manager *man = ttm_manager_type(&adev->mman.bdev,
2228                                                             AMDGPU_PL_OA);
2229         struct drm_printer p = drm_seq_file_printer(m);
2230
2231         man->func->debug(man, &p);
2232         return 0;
2233 }
2234
2235 DEFINE_SHOW_ATTRIBUTE(amdgpu_mm_vram_table);
2236 DEFINE_SHOW_ATTRIBUTE(amdgpu_mm_tt_table);
2237 DEFINE_SHOW_ATTRIBUTE(amdgpu_mm_gds_table);
2238 DEFINE_SHOW_ATTRIBUTE(amdgpu_mm_gws_table);
2239 DEFINE_SHOW_ATTRIBUTE(amdgpu_mm_oa_table);
2240 DEFINE_SHOW_ATTRIBUTE(amdgpu_ttm_page_pool);
2241
2242 /*
2243  * amdgpu_ttm_vram_read - Linear read access to VRAM
2244  *
2245  * Accesses VRAM via MMIO for debugging purposes.
2246  */
2247 static ssize_t amdgpu_ttm_vram_read(struct file *f, char __user *buf,
2248                                     size_t size, loff_t *pos)
2249 {
2250         struct amdgpu_device *adev = file_inode(f)->i_private;
2251         ssize_t result = 0;
2252
2253         if (size & 0x3 || *pos & 0x3)
2254                 return -EINVAL;
2255
2256         if (*pos >= adev->gmc.mc_vram_size)
2257                 return -ENXIO;
2258
2259         size = min(size, (size_t)(adev->gmc.mc_vram_size - *pos));
2260         while (size) {
2261                 size_t bytes = min(size, AMDGPU_TTM_VRAM_MAX_DW_READ * 4);
2262                 uint32_t value[AMDGPU_TTM_VRAM_MAX_DW_READ];
2263
2264                 amdgpu_device_vram_access(adev, *pos, value, bytes, false);
2265                 if (copy_to_user(buf, value, bytes))
2266                         return -EFAULT;
2267
2268                 result += bytes;
2269                 buf += bytes;
2270                 *pos += bytes;
2271                 size -= bytes;
2272         }
2273
2274         return result;
2275 }
2276
2277 /*
2278  * amdgpu_ttm_vram_write - Linear write access to VRAM
2279  *
2280  * Accesses VRAM via MMIO for debugging purposes.
2281  */
2282 static ssize_t amdgpu_ttm_vram_write(struct file *f, const char __user *buf,
2283                                     size_t size, loff_t *pos)
2284 {
2285         struct amdgpu_device *adev = file_inode(f)->i_private;
2286         ssize_t result = 0;
2287         int r;
2288
2289         if (size & 0x3 || *pos & 0x3)
2290                 return -EINVAL;
2291
2292         if (*pos >= adev->gmc.mc_vram_size)
2293                 return -ENXIO;
2294
2295         while (size) {
2296                 unsigned long flags;
2297                 uint32_t value;
2298
2299                 if (*pos >= adev->gmc.mc_vram_size)
2300                         return result;
2301
2302                 r = get_user(value, (uint32_t *)buf);
2303                 if (r)
2304                         return r;
2305
2306                 spin_lock_irqsave(&adev->mmio_idx_lock, flags);
2307                 WREG32_NO_KIQ(mmMM_INDEX, ((uint32_t)*pos) | 0x80000000);
2308                 WREG32_NO_KIQ(mmMM_INDEX_HI, *pos >> 31);
2309                 WREG32_NO_KIQ(mmMM_DATA, value);
2310                 spin_unlock_irqrestore(&adev->mmio_idx_lock, flags);
2311
2312                 result += 4;
2313                 buf += 4;
2314                 *pos += 4;
2315                 size -= 4;
2316         }
2317
2318         return result;
2319 }
2320
2321 static const struct file_operations amdgpu_ttm_vram_fops = {
2322         .owner = THIS_MODULE,
2323         .read = amdgpu_ttm_vram_read,
2324         .write = amdgpu_ttm_vram_write,
2325         .llseek = default_llseek,
2326 };
2327
2328 /*
2329  * amdgpu_iomem_read - Virtual read access to GPU mapped memory
2330  *
2331  * This function is used to read memory that has been mapped to the
2332  * GPU and the known addresses are not physical addresses but instead
2333  * bus addresses (e.g., what you'd put in an IB or ring buffer).
2334  */
2335 static ssize_t amdgpu_iomem_read(struct file *f, char __user *buf,
2336                                  size_t size, loff_t *pos)
2337 {
2338         struct amdgpu_device *adev = file_inode(f)->i_private;
2339         struct iommu_domain *dom;
2340         ssize_t result = 0;
2341         int r;
2342
2343         /* retrieve the IOMMU domain if any for this device */
2344         dom = iommu_get_domain_for_dev(adev->dev);
2345
2346         while (size) {
2347                 phys_addr_t addr = *pos & PAGE_MASK;
2348                 loff_t off = *pos & ~PAGE_MASK;
2349                 size_t bytes = PAGE_SIZE - off;
2350                 unsigned long pfn;
2351                 struct page *p;
2352                 void *ptr;
2353
2354                 bytes = bytes < size ? bytes : size;
2355
2356                 /* Translate the bus address to a physical address.  If
2357                  * the domain is NULL it means there is no IOMMU active
2358                  * and the address translation is the identity
2359                  */
2360                 addr = dom ? iommu_iova_to_phys(dom, addr) : addr;
2361
2362                 pfn = addr >> PAGE_SHIFT;
2363                 if (!pfn_valid(pfn))
2364                         return -EPERM;
2365
2366                 p = pfn_to_page(pfn);
2367                 if (p->mapping != adev->mman.bdev.dev_mapping)
2368                         return -EPERM;
2369
2370                 ptr = kmap(p);
2371                 r = copy_to_user(buf, ptr + off, bytes);
2372                 kunmap(p);
2373                 if (r)
2374                         return -EFAULT;
2375
2376                 size -= bytes;
2377                 *pos += bytes;
2378                 result += bytes;
2379         }
2380
2381         return result;
2382 }
2383
2384 /*
2385  * amdgpu_iomem_write - Virtual write access to GPU mapped memory
2386  *
2387  * This function is used to write memory that has been mapped to the
2388  * GPU and the known addresses are not physical addresses but instead
2389  * bus addresses (e.g., what you'd put in an IB or ring buffer).
2390  */
2391 static ssize_t amdgpu_iomem_write(struct file *f, const char __user *buf,
2392                                  size_t size, loff_t *pos)
2393 {
2394         struct amdgpu_device *adev = file_inode(f)->i_private;
2395         struct iommu_domain *dom;
2396         ssize_t result = 0;
2397         int r;
2398
2399         dom = iommu_get_domain_for_dev(adev->dev);
2400
2401         while (size) {
2402                 phys_addr_t addr = *pos & PAGE_MASK;
2403                 loff_t off = *pos & ~PAGE_MASK;
2404                 size_t bytes = PAGE_SIZE - off;
2405                 unsigned long pfn;
2406                 struct page *p;
2407                 void *ptr;
2408
2409                 bytes = bytes < size ? bytes : size;
2410
2411                 addr = dom ? iommu_iova_to_phys(dom, addr) : addr;
2412
2413                 pfn = addr >> PAGE_SHIFT;
2414                 if (!pfn_valid(pfn))
2415                         return -EPERM;
2416
2417                 p = pfn_to_page(pfn);
2418                 if (p->mapping != adev->mman.bdev.dev_mapping)
2419                         return -EPERM;
2420
2421                 ptr = kmap(p);
2422                 r = copy_from_user(ptr + off, buf, bytes);
2423                 kunmap(p);
2424                 if (r)
2425                         return -EFAULT;
2426
2427                 size -= bytes;
2428                 *pos += bytes;
2429                 result += bytes;
2430         }
2431
2432         return result;
2433 }
2434
2435 static const struct file_operations amdgpu_ttm_iomem_fops = {
2436         .owner = THIS_MODULE,
2437         .read = amdgpu_iomem_read,
2438         .write = amdgpu_iomem_write,
2439         .llseek = default_llseek
2440 };
2441
2442 #endif
2443
2444 void amdgpu_ttm_debugfs_init(struct amdgpu_device *adev)
2445 {
2446 #if defined(CONFIG_DEBUG_FS)
2447         struct drm_minor *minor = adev_to_drm(adev)->primary;
2448         struct dentry *root = minor->debugfs_root;
2449
2450         debugfs_create_file_size("amdgpu_vram", 0444, root, adev,
2451                                  &amdgpu_ttm_vram_fops, adev->gmc.mc_vram_size);
2452         debugfs_create_file("amdgpu_iomem", 0444, root, adev,
2453                             &amdgpu_ttm_iomem_fops);
2454         debugfs_create_file("amdgpu_vram_mm", 0444, root, adev,
2455                             &amdgpu_mm_vram_table_fops);
2456         debugfs_create_file("amdgpu_gtt_mm", 0444, root, adev,
2457                             &amdgpu_mm_tt_table_fops);
2458         debugfs_create_file("amdgpu_gds_mm", 0444, root, adev,
2459                             &amdgpu_mm_gds_table_fops);
2460         debugfs_create_file("amdgpu_gws_mm", 0444, root, adev,
2461                             &amdgpu_mm_gws_table_fops);
2462         debugfs_create_file("amdgpu_oa_mm", 0444, root, adev,
2463                             &amdgpu_mm_oa_table_fops);
2464         debugfs_create_file("ttm_page_pool", 0444, root, adev,
2465                             &amdgpu_ttm_page_pool_fops);
2466 #endif
2467 }