drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c

   1 /*
   2  * Copyright 2009 Jerome Glisse.
   3  * All Rights Reserved.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the
   7  * "Software"), to deal in the Software without restriction, including
   8  * without limitation the rights to use, copy, modify, merge, publish,
   9  * distribute, sub license, and/or sell copies of the Software, and to
  10  * permit persons to whom the Software is furnished to do so, subject to
  11  * the following conditions:
  12  *
  13  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  14  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  15  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  16  * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
  17  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  18  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  19  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  20  *
  21  * The above copyright notice and this permission notice (including the
  22  * next paragraph) shall be included in all copies or substantial portions
  23  * of the Software.
  24  *
  25  */
  26 /*
  27  * Authors:
  28  *    Jerome Glisse <glisse@freedesktop.org>
  29  *    Thomas Hellstrom <thomas-at-tungstengraphics-dot-com>
  30  *    Dave Airlie
  31  */
  32
  33 #include <linux/dma-mapping.h>
  34 #include <linux/iommu.h>
  35 #include <linux/hmm.h>
  36 #include <linux/pagemap.h>
  37 #include <linux/sched/task.h>
  38 #include <linux/sched/mm.h>
  39 #include <linux/seq_file.h>
  40 #include <linux/slab.h>
  41 #include <linux/swap.h>
  42 #include <linux/swiotlb.h>
  43 #include <linux/dma-buf.h>
  44 #include <linux/sizes.h>
  45
  46 #include <drm/ttm/ttm_bo_api.h>
  47 #include <drm/ttm/ttm_bo_driver.h>
  48 #include <drm/ttm/ttm_placement.h>
  49 #include <drm/ttm/ttm_module.h>
  50 #include <drm/ttm/ttm_page_alloc.h>
  51
  52 #include <drm/drm_debugfs.h>
  53 #include <drm/amdgpu_drm.h>
  54
  55 #include "amdgpu.h"
  56 #include "amdgpu_object.h"
  57 #include "amdgpu_trace.h"
  58 #include "amdgpu_amdkfd.h"
  59 #include "amdgpu_sdma.h"
  60 #include "amdgpu_ras.h"
  61 #include "amdgpu_atomfirmware.h"
  62 #include "bif/bif_4_1_d.h"
  63
  64 #define AMDGPU_TTM_VRAM_MAX_DW_READ     (size_t)128
  65
  66 static int amdgpu_ttm_init_on_chip(struct amdgpu_device *adev,
  67                                     unsigned int type,
  68                                     uint64_t size)
  69 {
  70         return ttm_range_man_init(&adev->mman.bdev, type,
  71                                   TTM_PL_FLAG_UNCACHED, TTM_PL_FLAG_UNCACHED,
  72                                   false, size >> PAGE_SHIFT);
  73 }
  74
  75 /**
  76  * amdgpu_evict_flags - Compute placement flags
  77  *
  78  * @bo: The buffer object to evict
  79  * @placement: Possible destination(s) for evicted BO
  80  *
  81  * Fill in placement data when ttm_bo_evict() is called
  82  */
  83 static void amdgpu_evict_flags(struct ttm_buffer_object *bo,
  84                                 struct ttm_placement *placement)
  85 {
  86         struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev);
  87         struct amdgpu_bo *abo;
  88         static const struct ttm_place placements = {
  89                 .fpfn = 0,
  90                 .lpfn = 0,
  91                 .flags = TTM_PL_MASK_CACHING | TTM_PL_FLAG_SYSTEM
  92         };
  93
  94         /* Don't handle scatter gather BOs */
  95         if (bo->type == ttm_bo_type_sg) {
  96                 placement->num_placement = 0;
  97                 placement->num_busy_placement = 0;
  98                 return;
  99         }
 100
 101         /* Object isn't an AMDGPU object so ignore */
 102         if (!amdgpu_bo_is_amdgpu_bo(bo)) {
 103                 placement->placement = &placements;
 104                 placement->busy_placement = &placements;
 105                 placement->num_placement = 1;
 106                 placement->num_busy_placement = 1;
 107                 return;
 108         }
 109
 110         abo = ttm_to_amdgpu_bo(bo);
 111         switch (bo->mem.mem_type) {
 112         case AMDGPU_PL_GDS:
 113         case AMDGPU_PL_GWS:
 114         case AMDGPU_PL_OA:
 115                 placement->num_placement = 0;
 116                 placement->num_busy_placement = 0;
 117                 return;
 118
 119         case TTM_PL_VRAM:
 120                 if (!adev->mman.buffer_funcs_enabled) {
 121                         /* Move to system memory */
 122                         amdgpu_bo_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_CPU);
 123                 } else if (!amdgpu_gmc_vram_full_visible(&adev->gmc) &&
 124                            !(abo->flags & AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED) &&
 125                            amdgpu_bo_in_cpu_visible_vram(abo)) {
 126
 127                         /* Try evicting to the CPU inaccessible part of VRAM
 128                          * first, but only set GTT as busy placement, so this
 129                          * BO will be evicted to GTT rather than causing other
 130                          * BOs to be evicted from VRAM
 131                          */
 132                         amdgpu_bo_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_VRAM |
 133                                                          AMDGPU_GEM_DOMAIN_GTT);
 134                         abo->placements[0].fpfn = adev->gmc.visible_vram_size >> PAGE_SHIFT;
 135                         abo->placements[0].lpfn = 0;
 136                         abo->placement.busy_placement = &abo->placements[1];
 137                         abo->placement.num_busy_placement = 1;
 138                 } else {
 139                         /* Move to GTT memory */
 140                         amdgpu_bo_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_GTT);
 141                 }
 142                 break;
 143         case TTM_PL_TT:
 144         default:
 145                 amdgpu_bo_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_CPU);
 146                 break;
 147         }
 148         *placement = abo->placement;
 149 }
 150
 151 /**
 152  * amdgpu_verify_access - Verify access for a mmap call
 153  *
 154  * @bo: The buffer object to map
 155  * @filp: The file pointer from the process performing the mmap
 156  *
 157  * This is called by ttm_bo_mmap() to verify whether a process
 158  * has the right to mmap a BO to their process space.
 159  */
 160 static int amdgpu_verify_access(struct ttm_buffer_object *bo, struct file *filp)
 161 {
 162         struct amdgpu_bo *abo = ttm_to_amdgpu_bo(bo);
 163
 164         /*
 165          * Don't verify access for KFD BOs. They don't have a GEM
 166          * object associated with them.
 167          */
 168         if (abo->kfd_bo)
 169                 return 0;
 170
 171         if (amdgpu_ttm_tt_get_usermm(bo->ttm))
 172                 return -EPERM;
 173         return drm_vma_node_verify_access(&abo->tbo.base.vma_node,
 174                                           filp->private_data);
 175 }
 176
 177 /**
 178  * amdgpu_mm_node_addr - Compute the GPU relative offset of a GTT buffer.
 179  *
 180  * @bo: The bo to assign the memory to.
 181  * @mm_node: Memory manager node for drm allocator.
 182  * @mem: The region where the bo resides.
 183  *
 184  */
 185 static uint64_t amdgpu_mm_node_addr(struct ttm_buffer_object *bo,
 186                                     struct drm_mm_node *mm_node,
 187                                     struct ttm_resource *mem)
 188 {
 189         uint64_t addr = 0;
 190
 191         if (mm_node->start != AMDGPU_BO_INVALID_OFFSET) {
 192                 addr = mm_node->start << PAGE_SHIFT;
 193                 addr += amdgpu_ttm_domain_start(amdgpu_ttm_adev(bo->bdev),
 194                                                 mem->mem_type);
 195         }
 196         return addr;
 197 }
 198
 199 /**
 200  * amdgpu_find_mm_node - Helper function finds the drm_mm_node corresponding to
 201  * @offset. It also modifies the offset to be within the drm_mm_node returned
 202  *
 203  * @mem: The region where the bo resides.
 204  * @offset: The offset that drm_mm_node is used for finding.
 205  *
 206  */
 207 static struct drm_mm_node *amdgpu_find_mm_node(struct ttm_resource *mem,
 208                                                uint64_t *offset)
 209 {
 210         struct drm_mm_node *mm_node = mem->mm_node;
 211
 212         while (*offset >= (mm_node->size << PAGE_SHIFT)) {
 213                 *offset -= (mm_node->size << PAGE_SHIFT);
 214                 ++mm_node;
 215         }
 216         return mm_node;
 217 }
 218
 219 /**
 220  * amdgpu_ttm_map_buffer - Map memory into the GART windows
 221  * @bo: buffer object to map
 222  * @mem: memory object to map
 223  * @mm_node: drm_mm node object to map
 224  * @num_pages: number of pages to map
 225  * @offset: offset into @mm_node where to start
 226  * @window: which GART window to use
 227  * @ring: DMA ring to use for the copy
 228  * @tmz: if we should setup a TMZ enabled mapping
 229  * @addr: resulting address inside the MC address space
 230  *
 231  * Setup one of the GART windows to access a specific piece of memory or return
 232  * the physical address for local memory.
 233  */
 234 static int amdgpu_ttm_map_buffer(struct ttm_buffer_object *bo,
 235                                  struct ttm_resource *mem,
 236                                  struct drm_mm_node *mm_node,
 237                                  unsigned num_pages, uint64_t offset,
 238                                  unsigned window, struct amdgpu_ring *ring,
 239                                  bool tmz, uint64_t *addr)
 240 {
 241         struct amdgpu_device *adev = ring->adev;
 242         struct amdgpu_job *job;
 243         unsigned num_dw, num_bytes;
 244         struct dma_fence *fence;
 245         uint64_t src_addr, dst_addr;
 246         void *cpu_addr;
 247         uint64_t flags;
 248         unsigned int i;
 249         int r;
 250
 251         BUG_ON(adev->mman.buffer_funcs->copy_max_bytes <
 252                AMDGPU_GTT_MAX_TRANSFER_SIZE * 8);
 253
 254         /* Map only what can't be accessed directly */
 255         if (!tmz && mem->start != AMDGPU_BO_INVALID_OFFSET) {
 256                 *addr = amdgpu_mm_node_addr(bo, mm_node, mem) + offset;
 257                 return 0;
 258         }
 259
 260         *addr = adev->gmc.gart_start;
 261         *addr += (u64)window * AMDGPU_GTT_MAX_TRANSFER_SIZE *
 262                 AMDGPU_GPU_PAGE_SIZE;
 263         *addr += offset & ~PAGE_MASK;
 264
 265         num_dw = ALIGN(adev->mman.buffer_funcs->copy_num_dw, 8);
 266         num_bytes = num_pages * 8;
 267
 268         r = amdgpu_job_alloc_with_ib(adev, num_dw * 4 + num_bytes,
 269                                      AMDGPU_IB_POOL_DELAYED, &job);
 270         if (r)
 271                 return r;
 272
 273         src_addr = num_dw * 4;
 274         src_addr += job->ibs[0].gpu_addr;
 275
 276         dst_addr = amdgpu_bo_gpu_offset(adev->gart.bo);
 277         dst_addr += window * AMDGPU_GTT_MAX_TRANSFER_SIZE * 8;
 278         amdgpu_emit_copy_buffer(adev, &job->ibs[0], src_addr,
 279                                 dst_addr, num_bytes, false);
 280
 281         amdgpu_ring_pad_ib(ring, &job->ibs[0]);
 282         WARN_ON(job->ibs[0].length_dw > num_dw);
 283
 284         flags = amdgpu_ttm_tt_pte_flags(adev, bo->ttm, mem);
 285         if (tmz)
 286                 flags |= AMDGPU_PTE_TMZ;
 287
 288         cpu_addr = &job->ibs[0].ptr[num_dw];
 289
 290         if (mem->mem_type == TTM_PL_TT) {
 291                 struct ttm_dma_tt *dma;
 292                 dma_addr_t *dma_address;
 293
 294                 dma = container_of(bo->ttm, struct ttm_dma_tt, ttm);
 295                 dma_address = &dma->dma_address[offset >> PAGE_SHIFT];
 296                 r = amdgpu_gart_map(adev, 0, num_pages, dma_address, flags,
 297                                     cpu_addr);
 298                 if (r)
 299                         goto error_free;
 300         } else {
 301                 dma_addr_t dma_address;
 302
 303                 dma_address = (mm_node->start << PAGE_SHIFT) + offset;
 304                 dma_address += adev->vm_manager.vram_base_offset;
 305
 306                 for (i = 0; i < num_pages; ++i) {
 307                         r = amdgpu_gart_map(adev, i << PAGE_SHIFT, 1,
 308                                             &dma_address, flags, cpu_addr);
 309                         if (r)
 310                                 goto error_free;
 311
 312                         dma_address += PAGE_SIZE;
 313                 }
 314         }
 315
 316         r = amdgpu_job_submit(job, &adev->mman.entity,
 317                               AMDGPU_FENCE_OWNER_UNDEFINED, &fence);
 318         if (r)
 319                 goto error_free;
 320
 321         dma_fence_put(fence);
 322
 323         return r;
 324
 325 error_free:
 326         amdgpu_job_free(job);
 327         return r;
 328 }
 329
 330 /**
 331  * amdgpu_copy_ttm_mem_to_mem - Helper function for copy
 332  * @adev: amdgpu device
 333  * @src: buffer/address where to read from
 334  * @dst: buffer/address where to write to
 335  * @size: number of bytes to copy
 336  * @tmz: if a secure copy should be used
 337  * @resv: resv object to sync to
 338  * @f: Returns the last fence if multiple jobs are submitted.
 339  *
 340  * The function copies @size bytes from {src->mem + src->offset} to
 341  * {dst->mem + dst->offset}. src->bo and dst->bo could be same BO for a
 342  * move and different for a BO to BO copy.
 343  *
 344  */
 345 int amdgpu_ttm_copy_mem_to_mem(struct amdgpu_device *adev,
 346                                const struct amdgpu_copy_mem *src,
 347                                const struct amdgpu_copy_mem *dst,
 348                                uint64_t size, bool tmz,
 349                                struct dma_resv *resv,
 350                                struct dma_fence **f)
 351 {
 352         const uint32_t GTT_MAX_BYTES = (AMDGPU_GTT_MAX_TRANSFER_SIZE *
 353                                         AMDGPU_GPU_PAGE_SIZE);
 354
 355         uint64_t src_node_size, dst_node_size, src_offset, dst_offset;
 356         struct amdgpu_ring *ring = adev->mman.buffer_funcs_ring;
 357         struct drm_mm_node *src_mm, *dst_mm;
 358         struct dma_fence *fence = NULL;
 359         int r = 0;
 360
 361         if (!adev->mman.buffer_funcs_enabled) {
 362                 DRM_ERROR("Trying to move memory with ring turned off.\n");
 363                 return -EINVAL;
 364         }
 365
 366         src_offset = src->offset;
 367         if (src->mem->mm_node) {
 368                 src_mm = amdgpu_find_mm_node(src->mem, &src_offset);
 369                 src_node_size = (src_mm->size << PAGE_SHIFT) - src_offset;
 370         } else {
 371                 src_mm = NULL;
 372                 src_node_size = ULLONG_MAX;
 373         }
 374
 375         dst_offset = dst->offset;
 376         if (dst->mem->mm_node) {
 377                 dst_mm = amdgpu_find_mm_node(dst->mem, &dst_offset);
 378                 dst_node_size = (dst_mm->size << PAGE_SHIFT) - dst_offset;
 379         } else {
 380                 dst_mm = NULL;
 381                 dst_node_size = ULLONG_MAX;
 382         }
 383
 384         mutex_lock(&adev->mman.gtt_window_lock);
 385
 386         while (size) {
 387                 uint32_t src_page_offset = src_offset & ~PAGE_MASK;
 388                 uint32_t dst_page_offset = dst_offset & ~PAGE_MASK;
 389                 struct dma_fence *next;
 390                 uint32_t cur_size;
 391                 uint64_t from, to;
 392
 393                 /* Copy size cannot exceed GTT_MAX_BYTES. So if src or dst
 394                  * begins at an offset, then adjust the size accordingly
 395                  */
 396                 cur_size = max(src_page_offset, dst_page_offset);
 397                 cur_size = min(min3(src_node_size, dst_node_size, size),
 398                                (uint64_t)(GTT_MAX_BYTES - cur_size));
 399
 400                 /* Map src to window 0 and dst to window 1. */
 401                 r = amdgpu_ttm_map_buffer(src->bo, src->mem, src_mm,
 402                                           PFN_UP(cur_size + src_page_offset),
 403                                           src_offset, 0, ring, tmz, &from);
 404                 if (r)
 405                         goto error;
 406
 407                 r = amdgpu_ttm_map_buffer(dst->bo, dst->mem, dst_mm,
 408                                           PFN_UP(cur_size + dst_page_offset),
 409                                           dst_offset, 1, ring, tmz, &to);
 410                 if (r)
 411                         goto error;
 412
 413                 r = amdgpu_copy_buffer(ring, from, to, cur_size,
 414                                        resv, &next, false, true, tmz);
 415                 if (r)
 416                         goto error;
 417
 418                 dma_fence_put(fence);
 419                 fence = next;
 420
 421                 size -= cur_size;
 422                 if (!size)
 423                         break;
 424
 425                 src_node_size -= cur_size;
 426                 if (!src_node_size) {
 427                         ++src_mm;
 428                         src_node_size = src_mm->size << PAGE_SHIFT;
 429                         src_offset = 0;
 430                 } else {
 431                         src_offset += cur_size;
 432                 }
 433
 434                 dst_node_size -= cur_size;
 435                 if (!dst_node_size) {
 436                         ++dst_mm;
 437                         dst_node_size = dst_mm->size << PAGE_SHIFT;
 438                         dst_offset = 0;
 439                 } else {
 440                         dst_offset += cur_size;
 441                 }
 442         }
 443 error:
 444         mutex_unlock(&adev->mman.gtt_window_lock);
 445         if (f)
 446                 *f = dma_fence_get(fence);
 447         dma_fence_put(fence);
 448         return r;
 449 }
 450
 451 /**
 452  * amdgpu_move_blit - Copy an entire buffer to another buffer
 453  *
 454  * This is a helper called by amdgpu_bo_move() and amdgpu_move_vram_ram() to
 455  * help move buffers to and from VRAM.
 456  */
 457 static int amdgpu_move_blit(struct ttm_buffer_object *bo,
 458                             bool evict,
 459                             struct ttm_resource *new_mem,
 460                             struct ttm_resource *old_mem)
 461 {
 462         struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev);
 463         struct amdgpu_bo *abo = ttm_to_amdgpu_bo(bo);
 464         struct amdgpu_copy_mem src, dst;
 465         struct dma_fence *fence = NULL;
 466         int r;
 467
 468         src.bo = bo;
 469         dst.bo = bo;
 470         src.mem = old_mem;
 471         dst.mem = new_mem;
 472         src.offset = 0;
 473         dst.offset = 0;
 474
 475         r = amdgpu_ttm_copy_mem_to_mem(adev, &src, &dst,
 476                                        new_mem->num_pages << PAGE_SHIFT,
 477                                        amdgpu_bo_encrypted(abo),
 478                                        bo->base.resv, &fence);
 479         if (r)
 480                 goto error;
 481
 482         /* clear the space being freed */
 483         if (old_mem->mem_type == TTM_PL_VRAM &&
 484             (abo->flags & AMDGPU_GEM_CREATE_VRAM_WIPE_ON_RELEASE)) {
 485                 struct dma_fence *wipe_fence = NULL;
 486
 487                 r = amdgpu_fill_buffer(ttm_to_amdgpu_bo(bo), AMDGPU_POISON,
 488                                        NULL, &wipe_fence);
 489                 if (r) {
 490                         goto error;
 491                 } else if (wipe_fence) {
 492                         dma_fence_put(fence);
 493                         fence = wipe_fence;
 494                 }
 495         }
 496
 497         /* Always block for VM page tables before committing the new location */
 498         if (bo->type == ttm_bo_type_kernel)
 499                 r = ttm_bo_move_accel_cleanup(bo, fence, true, new_mem);
 500         else
 501                 r = ttm_bo_pipeline_move(bo, fence, evict, new_mem);
 502         dma_fence_put(fence);
 503         return r;
 504
 505 error:
 506         if (fence)
 507                 dma_fence_wait(fence, false);
 508         dma_fence_put(fence);
 509         return r;
 510 }
 511
 512 /**
 513  * amdgpu_move_vram_ram - Copy VRAM buffer to RAM buffer
 514  *
 515  * Called by amdgpu_bo_move().
 516  */
 517 static int amdgpu_move_vram_ram(struct ttm_buffer_object *bo, bool evict,
 518                                 struct ttm_operation_ctx *ctx,
 519                                 struct ttm_resource *new_mem)
 520 {
 521         struct ttm_resource *old_mem = &bo->mem;
 522         struct ttm_resource tmp_mem;
 523         struct ttm_place placements;
 524         struct ttm_placement placement;
 525         int r;
 526
 527         /* create space/pages for new_mem in GTT space */
 528         tmp_mem = *new_mem;
 529         tmp_mem.mm_node = NULL;
 530         placement.num_placement = 1;
 531         placement.placement = &placements;
 532         placement.num_busy_placement = 1;
 533         placement.busy_placement = &placements;
 534         placements.fpfn = 0;
 535         placements.lpfn = 0;
 536         placements.flags = TTM_PL_MASK_CACHING | TTM_PL_FLAG_TT;
 537         r = ttm_bo_mem_space(bo, &placement, &tmp_mem, ctx);
 538         if (unlikely(r)) {
 539                 pr_err("Failed to find GTT space for blit from VRAM\n");
 540                 return r;
 541         }
 542
 543         /* set caching flags */
 544         r = ttm_tt_set_placement_caching(bo->ttm, tmp_mem.placement);
 545         if (unlikely(r)) {
 546                 goto out_cleanup;
 547         }
 548
 549         /* Bind the memory to the GTT space */
 550         r = ttm_tt_bind(bo->bdev, bo->ttm, &tmp_mem, ctx);
 551         if (unlikely(r)) {
 552                 goto out_cleanup;
 553         }
 554
 555         /* blit VRAM to GTT */
 556         r = amdgpu_move_blit(bo, evict, &tmp_mem, old_mem);
 557         if (unlikely(r)) {
 558                 goto out_cleanup;
 559         }
 560
 561         /* move BO (in tmp_mem) to new_mem */
 562         r = ttm_bo_move_ttm(bo, ctx, new_mem);
 563 out_cleanup:
 564         ttm_resource_free(bo, &tmp_mem);
 565         return r;
 566 }
 567
 568 /**
 569  * amdgpu_move_ram_vram - Copy buffer from RAM to VRAM
 570  *
 571  * Called by amdgpu_bo_move().
 572  */
 573 static int amdgpu_move_ram_vram(struct ttm_buffer_object *bo, bool evict,
 574                                 struct ttm_operation_ctx *ctx,
 575                                 struct ttm_resource *new_mem)
 576 {
 577         struct ttm_resource *old_mem = &bo->mem;
 578         struct ttm_resource tmp_mem;
 579         struct ttm_placement placement;
 580         struct ttm_place placements;
 581         int r;
 582
 583         /* make space in GTT for old_mem buffer */
 584         tmp_mem = *new_mem;
 585         tmp_mem.mm_node = NULL;
 586         placement.num_placement = 1;
 587         placement.placement = &placements;
 588         placement.num_busy_placement = 1;
 589         placement.busy_placement = &placements;
 590         placements.fpfn = 0;
 591         placements.lpfn = 0;
 592         placements.flags = TTM_PL_MASK_CACHING | TTM_PL_FLAG_TT;
 593         r = ttm_bo_mem_space(bo, &placement, &tmp_mem, ctx);
 594         if (unlikely(r)) {
 595                 pr_err("Failed to find GTT space for blit to VRAM\n");
 596                 return r;
 597         }
 598
 599         /* move/bind old memory to GTT space */
 600         r = ttm_bo_move_ttm(bo, ctx, &tmp_mem);
 601         if (unlikely(r)) {
 602                 goto out_cleanup;
 603         }
 604
 605         /* copy to VRAM */
 606         r = amdgpu_move_blit(bo, evict, new_mem, old_mem);
 607         if (unlikely(r)) {
 608                 goto out_cleanup;
 609         }
 610 out_cleanup:
 611         ttm_resource_free(bo, &tmp_mem);
 612         return r;
 613 }
 614
 615 /**
 616  * amdgpu_mem_visible - Check that memory can be accessed by ttm_bo_move_memcpy
 617  *
 618  * Called by amdgpu_bo_move()
 619  */
 620 static bool amdgpu_mem_visible(struct amdgpu_device *adev,
 621                                struct ttm_resource *mem)
 622 {
 623         struct drm_mm_node *nodes = mem->mm_node;
 624
 625         if (mem->mem_type == TTM_PL_SYSTEM ||
 626             mem->mem_type == TTM_PL_TT)
 627                 return true;
 628         if (mem->mem_type != TTM_PL_VRAM)
 629                 return false;
 630
 631         /* ttm_resource_ioremap only supports contiguous memory */
 632         if (nodes->size != mem->num_pages)
 633                 return false;
 634
 635         return ((nodes->start + nodes->size) << PAGE_SHIFT)
 636                 <= adev->gmc.visible_vram_size;
 637 }
 638
 639 /**
 640  * amdgpu_bo_move - Move a buffer object to a new memory location
 641  *
 642  * Called by ttm_bo_handle_move_mem()
 643  */
 644 static int amdgpu_bo_move(struct ttm_buffer_object *bo, bool evict,
 645                           struct ttm_operation_ctx *ctx,
 646                           struct ttm_resource *new_mem)
 647 {
 648         struct amdgpu_device *adev;
 649         struct amdgpu_bo *abo;
 650         struct ttm_resource *old_mem = &bo->mem;
 651         int r;
 652
 653         /* Can't move a pinned BO */
 654         abo = ttm_to_amdgpu_bo(bo);
 655         if (WARN_ON_ONCE(abo->pin_count > 0))
 656                 return -EINVAL;
 657
 658         adev = amdgpu_ttm_adev(bo->bdev);
 659
 660         if (old_mem->mem_type == TTM_PL_SYSTEM && bo->ttm == NULL) {
 661                 ttm_bo_move_null(bo, new_mem);
 662                 return 0;
 663         }
 664         if ((old_mem->mem_type == TTM_PL_TT &&
 665              new_mem->mem_type == TTM_PL_SYSTEM) ||
 666             (old_mem->mem_type == TTM_PL_SYSTEM &&
 667              new_mem->mem_type == TTM_PL_TT)) {
 668                 /* bind is enough */
 669                 ttm_bo_move_null(bo, new_mem);
 670                 return 0;
 671         }
 672         if (old_mem->mem_type == AMDGPU_PL_GDS ||
 673             old_mem->mem_type == AMDGPU_PL_GWS ||
 674             old_mem->mem_type == AMDGPU_PL_OA ||
 675             new_mem->mem_type == AMDGPU_PL_GDS ||
 676             new_mem->mem_type == AMDGPU_PL_GWS ||
 677             new_mem->mem_type == AMDGPU_PL_OA) {
 678                 /* Nothing to save here */
 679                 ttm_bo_move_null(bo, new_mem);
 680                 return 0;
 681         }
 682
 683         if (!adev->mman.buffer_funcs_enabled) {
 684                 r = -ENODEV;
 685                 goto memcpy;
 686         }
 687
 688         if (old_mem->mem_type == TTM_PL_VRAM &&
 689             new_mem->mem_type == TTM_PL_SYSTEM) {
 690                 r = amdgpu_move_vram_ram(bo, evict, ctx, new_mem);
 691         } else if (old_mem->mem_type == TTM_PL_SYSTEM &&
 692                    new_mem->mem_type == TTM_PL_VRAM) {
 693                 r = amdgpu_move_ram_vram(bo, evict, ctx, new_mem);
 694         } else {
 695                 r = amdgpu_move_blit(bo, evict,
 696                                      new_mem, old_mem);
 697         }
 698
 699         if (r) {
 700 memcpy:
 701                 /* Check that all memory is CPU accessible */
 702                 if (!amdgpu_mem_visible(adev, old_mem) ||
 703                     !amdgpu_mem_visible(adev, new_mem)) {
 704                         pr_err("Move buffer fallback to memcpy unavailable\n");
 705                         return r;
 706                 }
 707
 708                 r = ttm_bo_move_memcpy(bo, ctx, new_mem);
 709                 if (r)
 710                         return r;
 711         }
 712
 713         if (bo->type == ttm_bo_type_device &&
 714             new_mem->mem_type == TTM_PL_VRAM &&
 715             old_mem->mem_type != TTM_PL_VRAM) {
 716                 /* amdgpu_bo_fault_reserve_notify will re-set this if the CPU
 717                  * accesses the BO after it's moved.
 718                  */
 719                 abo->flags &= ~AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED;
 720         }
 721
 722         /* update statistics */
 723         atomic64_add((u64)bo->num_pages << PAGE_SHIFT, &adev->num_bytes_moved);
 724         return 0;
 725 }
 726
 727 /**
 728  * amdgpu_ttm_io_mem_reserve - Reserve a block of memory during a fault
 729  *
 730  * Called by ttm_mem_io_reserve() ultimately via ttm_bo_vm_fault()
 731  */
 732 static int amdgpu_ttm_io_mem_reserve(struct ttm_bo_device *bdev, struct ttm_resource *mem)
 733 {
 734         struct amdgpu_device *adev = amdgpu_ttm_adev(bdev);
 735         struct drm_mm_node *mm_node = mem->mm_node;
 736         size_t bus_size = (size_t)mem->num_pages << PAGE_SHIFT;
 737
 738         switch (mem->mem_type) {
 739         case TTM_PL_SYSTEM:
 740                 /* system memory */
 741                 return 0;
 742         case TTM_PL_TT:
 743                 break;
 744         case TTM_PL_VRAM:
 745                 mem->bus.offset = mem->start << PAGE_SHIFT;
 746                 /* check if it's visible */
 747                 if ((mem->bus.offset + bus_size) > adev->gmc.visible_vram_size)
 748                         return -EINVAL;
 749                 /* Only physically contiguous buffers apply. In a contiguous
 750                  * buffer, size of the first mm_node would match the number of
 751                  * pages in ttm_resource.
 752                  */
 753                 if (adev->mman.aper_base_kaddr &&
 754                     (mm_node->size == mem->num_pages))
 755                         mem->bus.addr = (u8 *)adev->mman.aper_base_kaddr +
 756                                         mem->bus.offset;
 757
 758                 mem->bus.offset += adev->gmc.aper_base;
 759                 mem->bus.is_iomem = true;
 760                 break;
 761         default:
 762                 return -EINVAL;
 763         }
 764         return 0;
 765 }
 766
 767 static unsigned long amdgpu_ttm_io_mem_pfn(struct ttm_buffer_object *bo,
 768                                            unsigned long page_offset)
 769 {
 770         struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev);
 771         uint64_t offset = (page_offset << PAGE_SHIFT);
 772         struct drm_mm_node *mm;
 773
 774         mm = amdgpu_find_mm_node(&bo->mem, &offset);
 775         offset += adev->gmc.aper_base;
 776         return mm->start + (offset >> PAGE_SHIFT);
 777 }
 778
 779 /**
 780  * amdgpu_ttm_domain_start - Returns GPU start address
 781  * @adev: amdgpu device object
 782  * @type: type of the memory
 783  *
 784  * Returns:
 785  * GPU start address of a memory domain
 786  */
 787
 788 uint64_t amdgpu_ttm_domain_start(struct amdgpu_device *adev, uint32_t type)
 789 {
 790         switch (type) {
 791         case TTM_PL_TT:
 792                 return adev->gmc.gart_start;
 793         case TTM_PL_VRAM:
 794                 return adev->gmc.vram_start;
 795         }
 796
 797         return 0;
 798 }
 799
 800 /*
 801  * TTM backend functions.
 802  */
 803 struct amdgpu_ttm_tt {
 804         struct ttm_dma_tt       ttm;
 805         struct drm_gem_object   *gobj;
 806         u64                     offset;
 807         uint64_t                userptr;
 808         struct task_struct      *usertask;
 809         uint32_t                userflags;
 810 #if IS_ENABLED(CONFIG_DRM_AMDGPU_USERPTR)
 811         struct hmm_range        *range;
 812 #endif
 813 };
 814
 815 #ifdef CONFIG_DRM_AMDGPU_USERPTR
 816 /**
 817  * amdgpu_ttm_tt_get_user_pages - get device accessible pages that back user
 818  * memory and start HMM tracking CPU page table update
 819  *
 820  * Calling function must call amdgpu_ttm_tt_userptr_range_done() once and only
 821  * once afterwards to stop HMM tracking
 822  */
 823 int amdgpu_ttm_tt_get_user_pages(struct amdgpu_bo *bo, struct page **pages)
 824 {
 825         struct ttm_tt *ttm = bo->tbo.ttm;
 826         struct amdgpu_ttm_tt *gtt = (void *)ttm;
 827         unsigned long start = gtt->userptr;
 828         struct vm_area_struct *vma;
 829         struct hmm_range *range;
 830         unsigned long timeout;
 831         struct mm_struct *mm;
 832         unsigned long i;
 833         int r = 0;
 834
 835         mm = bo->notifier.mm;
 836         if (unlikely(!mm)) {
 837                 DRM_DEBUG_DRIVER("BO is not registered?\n");
 838                 return -EFAULT;
 839         }
 840
 841         /* Another get_user_pages is running at the same time?? */
 842         if (WARN_ON(gtt->range))
 843                 return -EFAULT;
 844
 845         if (!mmget_not_zero(mm)) /* Happens during process shutdown */
 846                 return -ESRCH;
 847
 848         range = kzalloc(sizeof(*range), GFP_KERNEL);
 849         if (unlikely(!range)) {
 850                 r = -ENOMEM;
 851                 goto out;
 852         }
 853         range->notifier = &bo->notifier;
 854         range->start = bo->notifier.interval_tree.start;
 855         range->end = bo->notifier.interval_tree.last + 1;
 856         range->default_flags = HMM_PFN_REQ_FAULT;
 857         if (!amdgpu_ttm_tt_is_readonly(ttm))
 858                 range->default_flags |= HMM_PFN_REQ_WRITE;
 859
 860         range->hmm_pfns = kvmalloc_array(ttm->num_pages,
 861                                          sizeof(*range->hmm_pfns), GFP_KERNEL);
 862         if (unlikely(!range->hmm_pfns)) {
 863                 r = -ENOMEM;
 864                 goto out_free_ranges;
 865         }
 866
 867         mmap_read_lock(mm);
 868         vma = find_vma(mm, start);
 869         if (unlikely(!vma || start < vma->vm_start)) {
 870                 r = -EFAULT;
 871                 goto out_unlock;
 872         }
 873         if (unlikely((gtt->userflags & AMDGPU_GEM_USERPTR_ANONONLY) &&
 874                 vma->vm_file)) {
 875                 r = -EPERM;
 876                 goto out_unlock;
 877         }
 878         mmap_read_unlock(mm);
 879         timeout = jiffies + msecs_to_jiffies(HMM_RANGE_DEFAULT_TIMEOUT);
 880
 881 retry:
 882         range->notifier_seq = mmu_interval_read_begin(&bo->notifier);
 883
 884         mmap_read_lock(mm);
 885         r = hmm_range_fault(range);
 886         mmap_read_unlock(mm);
 887         if (unlikely(r)) {
 888                 /*
 889                  * FIXME: This timeout should encompass the retry from
 890                  * mmu_interval_read_retry() as well.
 891                  */
 892                 if (r == -EBUSY && !time_after(jiffies, timeout))
 893                         goto retry;
 894                 goto out_free_pfns;
 895         }
 896
 897         /*
 898          * Due to default_flags, all pages are HMM_PFN_VALID or
 899          * hmm_range_fault() fails. FIXME: The pages cannot be touched outside
 900          * the notifier_lock, and mmu_interval_read_retry() must be done first.
 901          */
 902         for (i = 0; i < ttm->num_pages; i++)
 903                 pages[i] = hmm_pfn_to_page(range->hmm_pfns[i]);
 904
 905         gtt->range = range;
 906         mmput(mm);
 907
 908         return 0;
 909
 910 out_unlock:
 911         mmap_read_unlock(mm);
 912 out_free_pfns:
 913         kvfree(range->hmm_pfns);
 914 out_free_ranges:
 915         kfree(range);
 916 out:
 917         mmput(mm);
 918         return r;
 919 }
 920
 921 /**
 922  * amdgpu_ttm_tt_userptr_range_done - stop HMM track the CPU page table change
 923  * Check if the pages backing this ttm range have been invalidated
 924  *
 925  * Returns: true if pages are still valid
 926  */
 927 bool amdgpu_ttm_tt_get_user_pages_done(struct ttm_tt *ttm)
 928 {
 929         struct amdgpu_ttm_tt *gtt = (void *)ttm;
 930         bool r = false;
 931
 932         if (!gtt || !gtt->userptr)
 933                 return false;
 934
 935         DRM_DEBUG_DRIVER("user_pages_done 0x%llx pages 0x%lx\n",
 936                 gtt->userptr, ttm->num_pages);
 937
 938         WARN_ONCE(!gtt->range || !gtt->range->hmm_pfns,
 939                 "No user pages to check\n");
 940
 941         if (gtt->range) {
 942                 /*
 943                  * FIXME: Must always hold notifier_lock for this, and must
 944                  * not ignore the return code.
 945                  */
 946                 r = mmu_interval_read_retry(gtt->range->notifier,
 947                                          gtt->range->notifier_seq);
 948                 kvfree(gtt->range->hmm_pfns);
 949                 kfree(gtt->range);
 950                 gtt->range = NULL;
 951         }
 952
 953         return !r;
 954 }
 955 #endif
 956
 957 /**
 958  * amdgpu_ttm_tt_set_user_pages - Copy pages in, putting old pages as necessary.
 959  *
 960  * Called by amdgpu_cs_list_validate(). This creates the page list
 961  * that backs user memory and will ultimately be mapped into the device
 962  * address space.
 963  */
 964 void amdgpu_ttm_tt_set_user_pages(struct ttm_tt *ttm, struct page **pages)
 965 {
 966         unsigned long i;
 967
 968         for (i = 0; i < ttm->num_pages; ++i)
 969                 ttm->pages[i] = pages ? pages[i] : NULL;
 970 }
 971
 972 /**
 973  * amdgpu_ttm_tt_pin_userptr -  prepare the sg table with the user pages
 974  *
 975  * Called by amdgpu_ttm_backend_bind()
 976  **/
 977 static int amdgpu_ttm_tt_pin_userptr(struct ttm_bo_device *bdev,
 978                                      struct ttm_tt *ttm)
 979 {
 980         struct amdgpu_device *adev = amdgpu_ttm_adev(bdev);
 981         struct amdgpu_ttm_tt *gtt = (void *)ttm;
 982         int r;
 983
 984         int write = !(gtt->userflags & AMDGPU_GEM_USERPTR_READONLY);
 985         enum dma_data_direction direction = write ?
 986                 DMA_BIDIRECTIONAL : DMA_TO_DEVICE;
 987
 988         /* Allocate an SG array and squash pages into it */
 989         r = sg_alloc_table_from_pages(ttm->sg, ttm->pages, ttm->num_pages, 0,
 990                                       ttm->num_pages << PAGE_SHIFT,
 991                                       GFP_KERNEL);
 992         if (r)
 993                 goto release_sg;
 994
 995         /* Map SG to device */
 996         r = dma_map_sgtable(adev->dev, ttm->sg, direction, 0);
 997         if (r)
 998                 goto release_sg;
 999
1000         /* convert SG to linear array of pages and dma addresses */
1001         drm_prime_sg_to_page_addr_arrays(ttm->sg, ttm->pages,
1002                                          gtt->ttm.dma_address, ttm->num_pages);
1003
1004         return 0;
1005
1006 release_sg:
1007         kfree(ttm->sg);
1008         return r;
1009 }
1010
1011 /**
1012  * amdgpu_ttm_tt_unpin_userptr - Unpin and unmap userptr pages
1013  */
1014 static void amdgpu_ttm_tt_unpin_userptr(struct ttm_bo_device *bdev,
1015                                         struct ttm_tt *ttm)
1016 {
1017         struct amdgpu_device *adev = amdgpu_ttm_adev(bdev);
1018         struct amdgpu_ttm_tt *gtt = (void *)ttm;
1019
1020         int write = !(gtt->userflags & AMDGPU_GEM_USERPTR_READONLY);
1021         enum dma_data_direction direction = write ?
1022                 DMA_BIDIRECTIONAL : DMA_TO_DEVICE;
1023
1024         /* double check that we don't free the table twice */
1025         if (!ttm->sg->sgl)
1026                 return;
1027
1028         /* unmap the pages mapped to the device */
1029         dma_unmap_sgtable(adev->dev, ttm->sg, direction, 0);
1030         sg_free_table(ttm->sg);
1031
1032 #if IS_ENABLED(CONFIG_DRM_AMDGPU_USERPTR)
1033         if (gtt->range) {
1034                 unsigned long i;
1035
1036                 for (i = 0; i < ttm->num_pages; i++) {
1037                         if (ttm->pages[i] !=
1038                             hmm_pfn_to_page(gtt->range->hmm_pfns[i]))
1039                                 break;
1040                 }
1041
1042                 WARN((i == ttm->num_pages), "Missing get_user_page_done\n");
1043         }
1044 #endif
1045 }
1046
1047 static int amdgpu_ttm_gart_bind(struct amdgpu_device *adev,
1048                                 struct ttm_buffer_object *tbo,
1049                                 uint64_t flags)
1050 {
1051         struct amdgpu_bo *abo = ttm_to_amdgpu_bo(tbo);
1052         struct ttm_tt *ttm = tbo->ttm;
1053         struct amdgpu_ttm_tt *gtt = (void *)ttm;
1054         int r;
1055
1056         if (amdgpu_bo_encrypted(abo))
1057                 flags |= AMDGPU_PTE_TMZ;
1058
1059         if (abo->flags & AMDGPU_GEM_CREATE_CP_MQD_GFX9) {
1060                 uint64_t page_idx = 1;
1061
1062                 r = amdgpu_gart_bind(adev, gtt->offset, page_idx,
1063                                 ttm->pages, gtt->ttm.dma_address, flags);
1064                 if (r)
1065                         goto gart_bind_fail;
1066
1067                 /* The memory type of the first page defaults to UC. Now
1068                  * modify the memory type to NC from the second page of
1069                  * the BO onward.
1070                  */
1071                 flags &= ~AMDGPU_PTE_MTYPE_VG10_MASK;
1072                 flags |= AMDGPU_PTE_MTYPE_VG10(AMDGPU_MTYPE_NC);
1073
1074                 r = amdgpu_gart_bind(adev,
1075                                 gtt->offset + (page_idx << PAGE_SHIFT),
1076                                 ttm->num_pages - page_idx,
1077                                 &ttm->pages[page_idx],
1078                                 &(gtt->ttm.dma_address[page_idx]), flags);
1079         } else {
1080                 r = amdgpu_gart_bind(adev, gtt->offset, ttm->num_pages,
1081                                      ttm->pages, gtt->ttm.dma_address, flags);
1082         }
1083
1084 gart_bind_fail:
1085         if (r)
1086                 DRM_ERROR("failed to bind %lu pages at 0x%08llX\n",
1087                           ttm->num_pages, gtt->offset);
1088
1089         return r;
1090 }
1091
1092 /**
1093  * amdgpu_ttm_backend_bind - Bind GTT memory
1094  *
1095  * Called by ttm_tt_bind() on behalf of ttm_bo_handle_move_mem().
1096  * This handles binding GTT memory to the device address space.
1097  */
1098 static int amdgpu_ttm_backend_bind(struct ttm_bo_device *bdev,
1099                                    struct ttm_tt *ttm,
1100                                    struct ttm_resource *bo_mem)
1101 {
1102         struct amdgpu_device *adev = amdgpu_ttm_adev(bdev);
1103         struct amdgpu_ttm_tt *gtt = (void*)ttm;
1104         uint64_t flags;
1105         int r = 0;
1106
1107         if (gtt->userptr) {
1108                 r = amdgpu_ttm_tt_pin_userptr(bdev, ttm);
1109                 if (r) {
1110                         DRM_ERROR("failed to pin userptr\n");
1111                         return r;
1112                 }
1113         }
1114         if (!ttm->num_pages) {
1115                 WARN(1, "nothing to bind %lu pages for mreg %p back %p!\n",
1116                      ttm->num_pages, bo_mem, ttm);
1117         }
1118
1119         if (bo_mem->mem_type == AMDGPU_PL_GDS ||
1120             bo_mem->mem_type == AMDGPU_PL_GWS ||
1121             bo_mem->mem_type == AMDGPU_PL_OA)
1122                 return -EINVAL;
1123
1124         if (!amdgpu_gtt_mgr_has_gart_addr(bo_mem)) {
1125                 gtt->offset = AMDGPU_BO_INVALID_OFFSET;
1126                 return 0;
1127         }
1128
1129         /* compute PTE flags relevant to this BO memory */
1130         flags = amdgpu_ttm_tt_pte_flags(adev, ttm, bo_mem);
1131
1132         /* bind pages into GART page tables */
1133         gtt->offset = (u64)bo_mem->start << PAGE_SHIFT;
1134         r = amdgpu_gart_bind(adev, gtt->offset, ttm->num_pages,
1135                 ttm->pages, gtt->ttm.dma_address, flags);
1136
1137         if (r)
1138                 DRM_ERROR("failed to bind %lu pages at 0x%08llX\n",
1139                           ttm->num_pages, gtt->offset);
1140         return r;
1141 }
1142
1143 /**
1144  * amdgpu_ttm_alloc_gart - Allocate GART memory for buffer object
1145  */
1146 int amdgpu_ttm_alloc_gart(struct ttm_buffer_object *bo)
1147 {
1148         struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev);
1149         struct ttm_operation_ctx ctx = { false, false };
1150         struct amdgpu_ttm_tt *gtt = (void*)bo->ttm;
1151         struct ttm_resource tmp;
1152         struct ttm_placement placement;
1153         struct ttm_place placements;
1154         uint64_t addr, flags;
1155         int r;
1156
1157         if (bo->mem.start != AMDGPU_BO_INVALID_OFFSET)
1158                 return 0;
1159
1160         addr = amdgpu_gmc_agp_addr(bo);
1161         if (addr != AMDGPU_BO_INVALID_OFFSET) {
1162                 bo->mem.start = addr >> PAGE_SHIFT;
1163         } else {
1164
1165                 /* allocate GART space */
1166                 tmp = bo->mem;
1167                 tmp.mm_node = NULL;
1168                 placement.num_placement = 1;
1169                 placement.placement = &placements;
1170                 placement.num_busy_placement = 1;
1171                 placement.busy_placement = &placements;
1172                 placements.fpfn = 0;
1173                 placements.lpfn = adev->gmc.gart_size >> PAGE_SHIFT;
1174                 placements.flags = (bo->mem.placement & ~TTM_PL_MASK_MEM) |
1175                         TTM_PL_FLAG_TT;
1176
1177                 r = ttm_bo_mem_space(bo, &placement, &tmp, &ctx);
1178                 if (unlikely(r))
1179                         return r;
1180
1181                 /* compute PTE flags for this buffer object */
1182                 flags = amdgpu_ttm_tt_pte_flags(adev, bo->ttm, &tmp);
1183
1184                 /* Bind pages */
1185                 gtt->offset = (u64)tmp.start << PAGE_SHIFT;
1186                 r = amdgpu_ttm_gart_bind(adev, bo, flags);
1187                 if (unlikely(r)) {
1188                         ttm_resource_free(bo, &tmp);
1189                         return r;
1190                 }
1191
1192                 ttm_resource_free(bo, &bo->mem);
1193                 bo->mem = tmp;
1194         }
1195
1196         return 0;
1197 }
1198
1199 /**
1200  * amdgpu_ttm_recover_gart - Rebind GTT pages
1201  *
1202  * Called by amdgpu_gtt_mgr_recover() from amdgpu_device_reset() to
1203  * rebind GTT pages during a GPU reset.
1204  */
1205 int amdgpu_ttm_recover_gart(struct ttm_buffer_object *tbo)
1206 {
1207         struct amdgpu_device *adev = amdgpu_ttm_adev(tbo->bdev);
1208         uint64_t flags;
1209         int r;
1210
1211         if (!tbo->ttm)
1212                 return 0;
1213
1214         flags = amdgpu_ttm_tt_pte_flags(adev, tbo->ttm, &tbo->mem);
1215         r = amdgpu_ttm_gart_bind(adev, tbo, flags);
1216
1217         return r;
1218 }
1219
1220 /**
1221  * amdgpu_ttm_backend_unbind - Unbind GTT mapped pages
1222  *
1223  * Called by ttm_tt_unbind() on behalf of ttm_bo_move_ttm() and
1224  * ttm_tt_destroy().
1225  */
1226 static void amdgpu_ttm_backend_unbind(struct ttm_bo_device *bdev,
1227                                       struct ttm_tt *ttm)
1228 {
1229         struct amdgpu_device *adev = amdgpu_ttm_adev(bdev);
1230         struct amdgpu_ttm_tt *gtt = (void *)ttm;
1231         int r;
1232
1233         /* if the pages have userptr pinning then clear that first */
1234         if (gtt->userptr)
1235                 amdgpu_ttm_tt_unpin_userptr(bdev, ttm);
1236
1237         if (gtt->offset == AMDGPU_BO_INVALID_OFFSET)
1238                 return;
1239
1240         /* unbind shouldn't be done for GDS/GWS/OA in ttm_bo_clean_mm */
1241         r = amdgpu_gart_unbind(adev, gtt->offset, ttm->num_pages);
1242         if (r)
1243                 DRM_ERROR("failed to unbind %lu pages at 0x%08llX\n",
1244                           gtt->ttm.ttm.num_pages, gtt->offset);
1245 }
1246
1247 static void amdgpu_ttm_backend_destroy(struct ttm_bo_device *bdev,
1248                                        struct ttm_tt *ttm)
1249 {
1250         struct amdgpu_ttm_tt *gtt = (void *)ttm;
1251
1252         if (gtt->usertask)
1253                 put_task_struct(gtt->usertask);
1254
1255         ttm_dma_tt_fini(&gtt->ttm);
1256         kfree(gtt);
1257 }
1258
1259 /**
1260  * amdgpu_ttm_tt_create - Create a ttm_tt object for a given BO
1261  *
1262  * @bo: The buffer object to create a GTT ttm_tt object around
1263  *
1264  * Called by ttm_tt_create().
1265  */
1266 static struct ttm_tt *amdgpu_ttm_tt_create(struct ttm_buffer_object *bo,
1267                                            uint32_t page_flags)
1268 {
1269         struct amdgpu_ttm_tt *gtt;
1270
1271         gtt = kzalloc(sizeof(struct amdgpu_ttm_tt), GFP_KERNEL);
1272         if (gtt == NULL) {
1273                 return NULL;
1274         }
1275         gtt->gobj = &bo->base;
1276
1277         /* allocate space for the uninitialized page entries */
1278         if (ttm_sg_tt_init(&gtt->ttm, bo, page_flags)) {
1279                 kfree(gtt);
1280                 return NULL;
1281         }
1282         return &gtt->ttm.ttm;
1283 }
1284
1285 /**
1286  * amdgpu_ttm_tt_populate - Map GTT pages visible to the device
1287  *
1288  * Map the pages of a ttm_tt object to an address space visible
1289  * to the underlying device.
1290  */
1291 static int amdgpu_ttm_tt_populate(struct ttm_bo_device *bdev,
1292                                   struct ttm_tt *ttm,
1293                                   struct ttm_operation_ctx *ctx)
1294 {
1295         struct amdgpu_device *adev = amdgpu_ttm_adev(bdev);
1296         struct amdgpu_ttm_tt *gtt = (void *)ttm;
1297
1298         /* user pages are bound by amdgpu_ttm_tt_pin_userptr() */
1299         if (gtt && gtt->userptr) {
1300                 ttm->sg = kzalloc(sizeof(struct sg_table), GFP_KERNEL);
1301                 if (!ttm->sg)
1302                         return -ENOMEM;
1303
1304                 ttm->page_flags |= TTM_PAGE_FLAG_SG;
1305                 ttm->state = tt_unbound;
1306                 return 0;
1307         }
1308
1309         if (ttm->page_flags & TTM_PAGE_FLAG_SG) {
1310                 if (!ttm->sg) {
1311                         struct dma_buf_attachment *attach;
1312                         struct sg_table *sgt;
1313
1314                         attach = gtt->gobj->import_attach;
1315                         sgt = dma_buf_map_attachment(attach, DMA_BIDIRECTIONAL);
1316                         if (IS_ERR(sgt))
1317                                 return PTR_ERR(sgt);
1318
1319                         ttm->sg = sgt;
1320                 }
1321
1322                 drm_prime_sg_to_page_addr_arrays(ttm->sg, ttm->pages,
1323                                                  gtt->ttm.dma_address,
1324                                                  ttm->num_pages);
1325                 ttm->state = tt_unbound;
1326                 return 0;
1327         }
1328
1329 #ifdef CONFIG_SWIOTLB
1330         if (adev->need_swiotlb && swiotlb_nr_tbl()) {
1331                 return ttm_dma_populate(&gtt->ttm, adev->dev, ctx);
1332         }
1333 #endif
1334
1335         /* fall back to generic helper to populate the page array
1336          * and map them to the device */
1337         return ttm_populate_and_map_pages(adev->dev, &gtt->ttm, ctx);
1338 }
1339
1340 /**
1341  * amdgpu_ttm_tt_unpopulate - unmap GTT pages and unpopulate page arrays
1342  *
1343  * Unmaps pages of a ttm_tt object from the device address space and
1344  * unpopulates the page array backing it.
1345  */
1346 static void amdgpu_ttm_tt_unpopulate(struct ttm_bo_device *bdev, struct ttm_tt *ttm)
1347 {
1348         struct amdgpu_ttm_tt *gtt = (void *)ttm;
1349         struct amdgpu_device *adev;
1350
1351         if (gtt && gtt->userptr) {
1352                 amdgpu_ttm_tt_set_user_pages(ttm, NULL);
1353                 kfree(ttm->sg);
1354                 ttm->page_flags &= ~TTM_PAGE_FLAG_SG;
1355                 return;
1356         }
1357
1358         if (ttm->sg && gtt->gobj->import_attach) {
1359                 struct dma_buf_attachment *attach;
1360
1361                 attach = gtt->gobj->import_attach;
1362                 dma_buf_unmap_attachment(attach, ttm->sg, DMA_BIDIRECTIONAL);
1363                 ttm->sg = NULL;
1364                 return;
1365         }
1366
1367         if (ttm->page_flags & TTM_PAGE_FLAG_SG)
1368                 return;
1369
1370         adev = amdgpu_ttm_adev(bdev);
1371
1372 #ifdef CONFIG_SWIOTLB
1373         if (adev->need_swiotlb && swiotlb_nr_tbl()) {
1374                 ttm_dma_unpopulate(&gtt->ttm, adev->dev);
1375                 return;
1376         }
1377 #endif
1378
1379         /* fall back to generic helper to unmap and unpopulate array */
1380         ttm_unmap_and_unpopulate_pages(adev->dev, &gtt->ttm);
1381 }
1382
1383 /**
1384  * amdgpu_ttm_tt_set_userptr - Initialize userptr GTT ttm_tt for the current
1385  * task
1386  *
1387  * @bo: The ttm_buffer_object to bind this userptr to
1388  * @addr:  The address in the current tasks VM space to use
1389  * @flags: Requirements of userptr object.
1390  *
1391  * Called by amdgpu_gem_userptr_ioctl() to bind userptr pages
1392  * to current task
1393  */
1394 int amdgpu_ttm_tt_set_userptr(struct ttm_buffer_object *bo,
1395                               uint64_t addr, uint32_t flags)
1396 {
1397         struct amdgpu_ttm_tt *gtt;
1398
1399         if (!bo->ttm) {
1400                 /* TODO: We want a separate TTM object type for userptrs */
1401                 bo->ttm = amdgpu_ttm_tt_create(bo, 0);
1402                 if (bo->ttm == NULL)
1403                         return -ENOMEM;
1404         }
1405
1406         gtt = (void*)bo->ttm;
1407         gtt->userptr = addr;
1408         gtt->userflags = flags;
1409
1410         if (gtt->usertask)
1411                 put_task_struct(gtt->usertask);
1412         gtt->usertask = current->group_leader;
1413         get_task_struct(gtt->usertask);
1414
1415         return 0;
1416 }
1417
1418 /**
1419  * amdgpu_ttm_tt_get_usermm - Return memory manager for ttm_tt object
1420  */
1421 struct mm_struct *amdgpu_ttm_tt_get_usermm(struct ttm_tt *ttm)
1422 {
1423         struct amdgpu_ttm_tt *gtt = (void *)ttm;
1424
1425         if (gtt == NULL)
1426                 return NULL;
1427
1428         if (gtt->usertask == NULL)
1429                 return NULL;
1430
1431         return gtt->usertask->mm;
1432 }
1433
1434 /**
1435  * amdgpu_ttm_tt_affect_userptr - Determine if a ttm_tt object lays inside an
1436  * address range for the current task.
1437  *
1438  */
1439 bool amdgpu_ttm_tt_affect_userptr(struct ttm_tt *ttm, unsigned long start,
1440                                   unsigned long end)
1441 {
1442         struct amdgpu_ttm_tt *gtt = (void *)ttm;
1443         unsigned long size;
1444
1445         if (gtt == NULL || !gtt->userptr)
1446                 return false;
1447
1448         /* Return false if no part of the ttm_tt object lies within
1449          * the range
1450          */
1451         size = (unsigned long)gtt->ttm.ttm.num_pages * PAGE_SIZE;
1452         if (gtt->userptr > end || gtt->userptr + size <= start)
1453                 return false;
1454
1455         return true;
1456 }
1457
1458 /**
1459  * amdgpu_ttm_tt_is_userptr - Have the pages backing by userptr?
1460  */
1461 bool amdgpu_ttm_tt_is_userptr(struct ttm_tt *ttm)
1462 {
1463         struct amdgpu_ttm_tt *gtt = (void *)ttm;
1464
1465         if (gtt == NULL || !gtt->userptr)
1466                 return false;
1467
1468         return true;
1469 }
1470
1471 /**
1472  * amdgpu_ttm_tt_is_readonly - Is the ttm_tt object read only?
1473  */
1474 bool amdgpu_ttm_tt_is_readonly(struct ttm_tt *ttm)
1475 {
1476         struct amdgpu_ttm_tt *gtt = (void *)ttm;
1477
1478         if (gtt == NULL)
1479                 return false;
1480
1481         return !!(gtt->userflags & AMDGPU_GEM_USERPTR_READONLY);
1482 }
1483
1484 /**
1485  * amdgpu_ttm_tt_pde_flags - Compute PDE flags for ttm_tt object
1486  *
1487  * @ttm: The ttm_tt object to compute the flags for
1488  * @mem: The memory registry backing this ttm_tt object
1489  *
1490  * Figure out the flags to use for a VM PDE (Page Directory Entry).
1491  */
1492 uint64_t amdgpu_ttm_tt_pde_flags(struct ttm_tt *ttm, struct ttm_resource *mem)
1493 {
1494         uint64_t flags = 0;
1495
1496         if (mem && mem->mem_type != TTM_PL_SYSTEM)
1497                 flags |= AMDGPU_PTE_VALID;
1498
1499         if (mem && mem->mem_type == TTM_PL_TT) {
1500                 flags |= AMDGPU_PTE_SYSTEM;
1501
1502                 if (ttm->caching_state == tt_cached)
1503                         flags |= AMDGPU_PTE_SNOOPED;
1504         }
1505
1506         return flags;
1507 }
1508
1509 /**
1510  * amdgpu_ttm_tt_pte_flags - Compute PTE flags for ttm_tt object
1511  *
1512  * @ttm: The ttm_tt object to compute the flags for
1513  * @mem: The memory registry backing this ttm_tt object
1514
1515  * Figure out the flags to use for a VM PTE (Page Table Entry).
1516  */
1517 uint64_t amdgpu_ttm_tt_pte_flags(struct amdgpu_device *adev, struct ttm_tt *ttm,
1518                                  struct ttm_resource *mem)
1519 {
1520         uint64_t flags = amdgpu_ttm_tt_pde_flags(ttm, mem);
1521
1522         flags |= adev->gart.gart_pte_flags;
1523         flags |= AMDGPU_PTE_READABLE;
1524
1525         if (!amdgpu_ttm_tt_is_readonly(ttm))
1526                 flags |= AMDGPU_PTE_WRITEABLE;
1527
1528         return flags;
1529 }
1530
1531 /**
1532  * amdgpu_ttm_bo_eviction_valuable - Check to see if we can evict a buffer
1533  * object.
1534  *
1535  * Return true if eviction is sensible. Called by ttm_mem_evict_first() on
1536  * behalf of ttm_bo_mem_force_space() which tries to evict buffer objects until
1537  * it can find space for a new object and by ttm_bo_force_list_clean() which is
1538  * used to clean out a memory space.
1539  */
1540 static bool amdgpu_ttm_bo_eviction_valuable(struct ttm_buffer_object *bo,
1541                                             const struct ttm_place *place)
1542 {
1543         unsigned long num_pages = bo->mem.num_pages;
1544         struct drm_mm_node *node = bo->mem.mm_node;
1545         struct dma_resv_list *flist;
1546         struct dma_fence *f;
1547         int i;
1548
1549         if (bo->type == ttm_bo_type_kernel &&
1550             !amdgpu_vm_evictable(ttm_to_amdgpu_bo(bo)))
1551                 return false;
1552
1553         /* If bo is a KFD BO, check if the bo belongs to the current process.
1554          * If true, then return false as any KFD process needs all its BOs to
1555          * be resident to run successfully
1556          */
1557         flist = dma_resv_get_list(bo->base.resv);
1558         if (flist) {
1559                 for (i = 0; i < flist->shared_count; ++i) {
1560                         f = rcu_dereference_protected(flist->shared[i],
1561                                 dma_resv_held(bo->base.resv));
1562                         if (amdkfd_fence_check_mm(f, current->mm))
1563                                 return false;
1564                 }
1565         }
1566
1567         switch (bo->mem.mem_type) {
1568         case TTM_PL_TT:
1569                 if (amdgpu_bo_is_amdgpu_bo(bo) &&
1570                     amdgpu_bo_encrypted(ttm_to_amdgpu_bo(bo)))
1571                         return false;
1572                 return true;
1573
1574         case TTM_PL_VRAM:
1575                 /* Check each drm MM node individually */
1576                 while (num_pages) {
1577                         if (place->fpfn < (node->start + node->size) &&
1578                             !(place->lpfn && place->lpfn <= node->start))
1579                                 return true;
1580
1581                         num_pages -= node->size;
1582                         ++node;
1583                 }
1584                 return false;
1585
1586         default:
1587                 break;
1588         }
1589
1590         return ttm_bo_eviction_valuable(bo, place);
1591 }
1592
1593 /**
1594  * amdgpu_ttm_access_memory - Read or Write memory that backs a buffer object.
1595  *
1596  * @bo:  The buffer object to read/write
1597  * @offset:  Offset into buffer object
1598  * @buf:  Secondary buffer to write/read from
1599  * @len: Length in bytes of access
1600  * @write:  true if writing
1601  *
1602  * This is used to access VRAM that backs a buffer object via MMIO
1603  * access for debugging purposes.
1604  */
1605 static int amdgpu_ttm_access_memory(struct ttm_buffer_object *bo,
1606                                     unsigned long offset,
1607                                     void *buf, int len, int write)
1608 {
1609         struct amdgpu_bo *abo = ttm_to_amdgpu_bo(bo);
1610         struct amdgpu_device *adev = amdgpu_ttm_adev(abo->tbo.bdev);
1611         struct drm_mm_node *nodes;
1612         uint32_t value = 0;
1613         int ret = 0;
1614         uint64_t pos;
1615         unsigned long flags;
1616
1617         if (bo->mem.mem_type != TTM_PL_VRAM)
1618                 return -EIO;
1619
1620         pos = offset;
1621         nodes = amdgpu_find_mm_node(&abo->tbo.mem, &pos);
1622         pos += (nodes->start << PAGE_SHIFT);
1623
1624         while (len && pos < adev->gmc.mc_vram_size) {
1625                 uint64_t aligned_pos = pos & ~(uint64_t)3;
1626                 uint64_t bytes = 4 - (pos & 3);
1627                 uint32_t shift = (pos & 3) * 8;
1628                 uint32_t mask = 0xffffffff << shift;
1629
1630                 if (len < bytes) {
1631                         mask &= 0xffffffff >> (bytes - len) * 8;
1632                         bytes = len;
1633                 }
1634
1635                 if (mask != 0xffffffff) {
1636                         spin_lock_irqsave(&adev->mmio_idx_lock, flags);
1637                         WREG32_NO_KIQ(mmMM_INDEX, ((uint32_t)aligned_pos) | 0x80000000);
1638                         WREG32_NO_KIQ(mmMM_INDEX_HI, aligned_pos >> 31);
1639                         if (!write || mask != 0xffffffff)
1640                                 value = RREG32_NO_KIQ(mmMM_DATA);
1641                         if (write) {
1642                                 value &= ~mask;
1643                                 value |= (*(uint32_t *)buf << shift) & mask;
1644                                 WREG32_NO_KIQ(mmMM_DATA, value);
1645                         }
1646                         spin_unlock_irqrestore(&adev->mmio_idx_lock, flags);
1647                         if (!write) {
1648                                 value = (value & mask) >> shift;
1649                                 memcpy(buf, &value, bytes);
1650                         }
1651                 } else {
1652                         bytes = (nodes->start + nodes->size) << PAGE_SHIFT;
1653                         bytes = min(bytes - pos, (uint64_t)len & ~0x3ull);
1654
1655                         amdgpu_device_vram_access(adev, pos, (uint32_t *)buf,
1656                                                   bytes, write);
1657                 }
1658
1659                 ret += bytes;
1660                 buf = (uint8_t *)buf + bytes;
1661                 pos += bytes;
1662                 len -= bytes;
1663                 if (pos >= (nodes->start + nodes->size) << PAGE_SHIFT) {
1664                         ++nodes;
1665                         pos = (nodes->start << PAGE_SHIFT);
1666                 }
1667         }
1668
1669         return ret;
1670 }
1671
1672 static struct ttm_bo_driver amdgpu_bo_driver = {
1673         .ttm_tt_create = &amdgpu_ttm_tt_create,
1674         .ttm_tt_populate = &amdgpu_ttm_tt_populate,
1675         .ttm_tt_unpopulate = &amdgpu_ttm_tt_unpopulate,
1676         .ttm_tt_bind = &amdgpu_ttm_backend_bind,
1677         .ttm_tt_unbind = &amdgpu_ttm_backend_unbind,
1678         .ttm_tt_destroy = &amdgpu_ttm_backend_destroy,
1679         .eviction_valuable = amdgpu_ttm_bo_eviction_valuable,
1680         .evict_flags = &amdgpu_evict_flags,
1681         .move = &amdgpu_bo_move,
1682         .verify_access = &amdgpu_verify_access,
1683         .move_notify = &amdgpu_bo_move_notify,
1684         .release_notify = &amdgpu_bo_release_notify,
1685         .fault_reserve_notify = &amdgpu_bo_fault_reserve_notify,
1686         .io_mem_reserve = &amdgpu_ttm_io_mem_reserve,
1687         .io_mem_pfn = amdgpu_ttm_io_mem_pfn,
1688         .access_memory = &amdgpu_ttm_access_memory,
1689         .del_from_lru_notify = &amdgpu_vm_del_from_lru_notify
1690 };
1691
1692 /*
1693  * Firmware Reservation functions
1694  */
1695 /**
1696  * amdgpu_ttm_fw_reserve_vram_fini - free fw reserved vram
1697  *
1698  * @adev: amdgpu_device pointer
1699  *
1700  * free fw reserved vram if it has been reserved.
1701  */
1702 static void amdgpu_ttm_fw_reserve_vram_fini(struct amdgpu_device *adev)
1703 {
1704         amdgpu_bo_free_kernel(&adev->fw_vram_usage.reserved_bo,
1705                 NULL, &adev->fw_vram_usage.va);
1706 }
1707
1708 /**
1709  * amdgpu_ttm_fw_reserve_vram_init - create bo vram reservation from fw
1710  *
1711  * @adev: amdgpu_device pointer
1712  *
1713  * create bo vram reservation from fw.
1714  */
1715 static int amdgpu_ttm_fw_reserve_vram_init(struct amdgpu_device *adev)
1716 {
1717         uint64_t vram_size = adev->gmc.visible_vram_size;
1718
1719         adev->fw_vram_usage.va = NULL;
1720         adev->fw_vram_usage.reserved_bo = NULL;
1721
1722         if (adev->fw_vram_usage.size == 0 ||
1723             adev->fw_vram_usage.size > vram_size)
1724                 return 0;
1725
1726         return amdgpu_bo_create_kernel_at(adev,
1727                                           adev->fw_vram_usage.start_offset,
1728                                           adev->fw_vram_usage.size,
1729                                           AMDGPU_GEM_DOMAIN_VRAM,
1730                                           &adev->fw_vram_usage.reserved_bo,
1731                                           &adev->fw_vram_usage.va);
1732 }
1733
1734 /*
1735  * Memoy training reservation functions
1736  */
1737
1738 /**
1739  * amdgpu_ttm_training_reserve_vram_fini - free memory training reserved vram
1740  *
1741  * @adev: amdgpu_device pointer
1742  *
1743  * free memory training reserved vram if it has been reserved.
1744  */
1745 static int amdgpu_ttm_training_reserve_vram_fini(struct amdgpu_device *adev)
1746 {
1747         struct psp_memory_training_context *ctx = &adev->psp.mem_train_ctx;
1748
1749         ctx->init = PSP_MEM_TRAIN_NOT_SUPPORT;
1750         amdgpu_bo_free_kernel(&ctx->c2p_bo, NULL, NULL);
1751         ctx->c2p_bo = NULL;
1752
1753         return 0;
1754 }
1755
1756 static void amdgpu_ttm_training_data_block_init(struct amdgpu_device *adev)
1757 {
1758         struct psp_memory_training_context *ctx = &adev->psp.mem_train_ctx;
1759
1760         memset(ctx, 0, sizeof(*ctx));
1761
1762         ctx->c2p_train_data_offset =
1763                 ALIGN((adev->gmc.mc_vram_size - adev->discovery_tmr_size - SZ_1M), SZ_1M);
1764         ctx->p2c_train_data_offset =
1765                 (adev->gmc.mc_vram_size - GDDR6_MEM_TRAINING_OFFSET);
1766         ctx->train_data_size =
1767                 GDDR6_MEM_TRAINING_DATA_SIZE_IN_BYTES;
1768
1769         DRM_DEBUG("train_data_size:%llx,p2c_train_data_offset:%llx,c2p_train_data_offset:%llx.\n",
1770                         ctx->train_data_size,
1771                         ctx->p2c_train_data_offset,
1772                         ctx->c2p_train_data_offset);
1773 }
1774
1775 /*
1776  * reserve TMR memory at the top of VRAM which holds
1777  * IP Discovery data and is protected by PSP.
1778  */
1779 static int amdgpu_ttm_reserve_tmr(struct amdgpu_device *adev)
1780 {
1781         int ret;
1782         struct psp_memory_training_context *ctx = &adev->psp.mem_train_ctx;
1783         bool mem_train_support = false;
1784
1785         if (!amdgpu_sriov_vf(adev)) {
1786                 ret = amdgpu_mem_train_support(adev);
1787                 if (ret == 1)
1788                         mem_train_support = true;
1789                 else if (ret == -1)
1790                         return -EINVAL;
1791                 else
1792                         DRM_DEBUG("memory training does not support!\n");
1793         }
1794
1795         /*
1796          * Query reserved tmr size through atom firmwareinfo for Sienna_Cichlid and onwards for all
1797          * the use cases (IP discovery/G6 memory training/profiling/diagnostic data.etc)
1798          *
1799          * Otherwise, fallback to legacy approach to check and reserve tmr block for ip
1800          * discovery data and G6 memory training data respectively
1801          */
1802         adev->discovery_tmr_size =
1803                 amdgpu_atomfirmware_get_fw_reserved_fb_size(adev);
1804         if (!adev->discovery_tmr_size)
1805                 adev->discovery_tmr_size = DISCOVERY_TMR_OFFSET;
1806
1807         if (mem_train_support) {
1808                 /* reserve vram for mem train according to TMR location */
1809                 amdgpu_ttm_training_data_block_init(adev);
1810                 ret = amdgpu_bo_create_kernel_at(adev,
1811                                          ctx->c2p_train_data_offset,
1812                                          ctx->train_data_size,
1813                                          AMDGPU_GEM_DOMAIN_VRAM,
1814                                          &ctx->c2p_bo,
1815                                          NULL);
1816                 if (ret) {
1817                         DRM_ERROR("alloc c2p_bo failed(%d)!\n", ret);
1818                         amdgpu_ttm_training_reserve_vram_fini(adev);
1819                         return ret;
1820                 }
1821                 ctx->init = PSP_MEM_TRAIN_RESERVE_SUCCESS;
1822         }
1823
1824         ret = amdgpu_bo_create_kernel_at(adev,
1825                                 adev->gmc.real_vram_size - adev->discovery_tmr_size,
1826                                 adev->discovery_tmr_size,
1827                                 AMDGPU_GEM_DOMAIN_VRAM,
1828                                 &adev->discovery_memory,
1829                                 NULL);
1830         if (ret) {
1831                 DRM_ERROR("alloc tmr failed(%d)!\n", ret);
1832                 amdgpu_bo_free_kernel(&adev->discovery_memory, NULL, NULL);
1833                 return ret;
1834         }
1835
1836         return 0;
1837 }
1838
1839 /**
1840  * amdgpu_ttm_init - Init the memory management (ttm) as well as various
1841  * gtt/vram related fields.
1842  *
1843  * This initializes all of the memory space pools that the TTM layer
1844  * will need such as the GTT space (system memory mapped to the device),
1845  * VRAM (on-board memory), and on-chip memories (GDS, GWS, OA) which
1846  * can be mapped per VMID.
1847  */
1848 int amdgpu_ttm_init(struct amdgpu_device *adev)
1849 {
1850         uint64_t gtt_size;
1851         int r;
1852         u64 vis_vram_limit;
1853         void *stolen_vga_buf;
1854
1855         mutex_init(&adev->mman.gtt_window_lock);
1856
1857         /* No others user of address space so set it to 0 */
1858         r = ttm_bo_device_init(&adev->mman.bdev,
1859                                &amdgpu_bo_driver,
1860                                adev->ddev->anon_inode->i_mapping,
1861                                adev->ddev->vma_offset_manager,
1862                                dma_addressing_limited(adev->dev));
1863         if (r) {
1864                 DRM_ERROR("failed initializing buffer object driver(%d).\n", r);
1865                 return r;
1866         }
1867         adev->mman.initialized = true;
1868
1869         /* We opt to avoid OOM on system pages allocations */
1870         adev->mman.bdev.no_retry = true;
1871
1872         /* Initialize VRAM pool with all of VRAM divided into pages */
1873         r = amdgpu_vram_mgr_init(adev);
1874         if (r) {
1875                 DRM_ERROR("Failed initializing VRAM heap.\n");
1876                 return r;
1877         }
1878
1879         /* Reduce size of CPU-visible VRAM if requested */
1880         vis_vram_limit = (u64)amdgpu_vis_vram_limit * 1024 * 1024;
1881         if (amdgpu_vis_vram_limit > 0 &&
1882             vis_vram_limit <= adev->gmc.visible_vram_size)
1883                 adev->gmc.visible_vram_size = vis_vram_limit;
1884
1885         /* Change the size here instead of the init above so only lpfn is affected */
1886         amdgpu_ttm_set_buffer_funcs_status(adev, false);
1887 #ifdef CONFIG_64BIT
1888         adev->mman.aper_base_kaddr = ioremap_wc(adev->gmc.aper_base,
1889                                                 adev->gmc.visible_vram_size);
1890 #endif
1891
1892         /*
1893          *The reserved vram for firmware must be pinned to the specified
1894          *place on the VRAM, so reserve it early.
1895          */
1896         r = amdgpu_ttm_fw_reserve_vram_init(adev);
1897         if (r) {
1898                 return r;
1899         }
1900
1901         /*
1902          * only NAVI10 and onwards ASIC support for IP discovery.
1903          * If IP discovery enabled, a block of memory should be
1904          * reserved for IP discovey.
1905          */
1906         if (adev->discovery_bin) {
1907                 r = amdgpu_ttm_reserve_tmr(adev);
1908                 if (r)
1909                         return r;
1910         }
1911
1912         /* allocate memory as required for VGA
1913          * This is used for VGA emulation and pre-OS scanout buffers to
1914          * avoid display artifacts while transitioning between pre-OS
1915          * and driver.  */
1916         r = amdgpu_bo_create_kernel(adev, adev->gmc.stolen_size, PAGE_SIZE,
1917                                     AMDGPU_GEM_DOMAIN_VRAM,
1918                                     &adev->stolen_vga_memory,
1919                                     NULL, &stolen_vga_buf);
1920         if (r)
1921                 return r;
1922
1923         DRM_INFO("amdgpu: %uM of VRAM memory ready\n",
1924                  (unsigned) (adev->gmc.real_vram_size / (1024 * 1024)));
1925
1926         /* Compute GTT size, either bsaed on 3/4th the size of RAM size
1927          * or whatever the user passed on module init */
1928         if (amdgpu_gtt_size == -1) {
1929                 struct sysinfo si;
1930
1931                 si_meminfo(&si);
1932                 gtt_size = min(max((AMDGPU_DEFAULT_GTT_SIZE_MB << 20),
1933                                adev->gmc.mc_vram_size),
1934                                ((uint64_t)si.totalram * si.mem_unit * 3/4));
1935         }
1936         else
1937                 gtt_size = (uint64_t)amdgpu_gtt_size << 20;
1938
1939         /* Initialize GTT memory pool */
1940         r = amdgpu_gtt_mgr_init(adev, gtt_size);
1941         if (r) {
1942                 DRM_ERROR("Failed initializing GTT heap.\n");
1943                 return r;
1944         }
1945         DRM_INFO("amdgpu: %uM of GTT memory ready.\n",
1946                  (unsigned)(gtt_size / (1024 * 1024)));
1947
1948         /* Initialize various on-chip memory pools */
1949         r = amdgpu_ttm_init_on_chip(adev, AMDGPU_PL_GDS, adev->gds.gds_size);
1950         if (r) {
1951                 DRM_ERROR("Failed initializing GDS heap.\n");
1952                 return r;
1953         }
1954
1955         r = amdgpu_ttm_init_on_chip(adev, AMDGPU_PL_GWS, adev->gds.gws_size);
1956         if (r) {
1957                 DRM_ERROR("Failed initializing gws heap.\n");
1958                 return r;
1959         }
1960
1961         r = amdgpu_ttm_init_on_chip(adev, AMDGPU_PL_OA, adev->gds.oa_size);
1962         if (r) {
1963                 DRM_ERROR("Failed initializing oa heap.\n");
1964                 return r;
1965         }
1966
1967         return 0;
1968 }
1969
1970 /**
1971  * amdgpu_ttm_late_init - Handle any late initialization for amdgpu_ttm
1972  */
1973 void amdgpu_ttm_late_init(struct amdgpu_device *adev)
1974 {
1975         void *stolen_vga_buf;
1976         /* return the VGA stolen memory (if any) back to VRAM */
1977         amdgpu_bo_free_kernel(&adev->stolen_vga_memory, NULL, &stolen_vga_buf);
1978 }
1979
1980 /**
1981  * amdgpu_ttm_fini - De-initialize the TTM memory pools
1982  */
1983 void amdgpu_ttm_fini(struct amdgpu_device *adev)
1984 {
1985         if (!adev->mman.initialized)
1986                 return;
1987
1988         amdgpu_ttm_training_reserve_vram_fini(adev);
1989         /* return the IP Discovery TMR memory back to VRAM */
1990         amdgpu_bo_free_kernel(&adev->discovery_memory, NULL, NULL);
1991         amdgpu_ttm_fw_reserve_vram_fini(adev);
1992
1993         if (adev->mman.aper_base_kaddr)
1994                 iounmap(adev->mman.aper_base_kaddr);
1995         adev->mman.aper_base_kaddr = NULL;
1996
1997         amdgpu_vram_mgr_fini(adev);
1998         amdgpu_gtt_mgr_fini(adev);
1999         ttm_range_man_fini(&adev->mman.bdev, AMDGPU_PL_GDS);
2000         ttm_range_man_fini(&adev->mman.bdev, AMDGPU_PL_GWS);
2001         ttm_range_man_fini(&adev->mman.bdev, AMDGPU_PL_OA);
2002         ttm_bo_device_release(&adev->mman.bdev);
2003         adev->mman.initialized = false;
2004         DRM_INFO("amdgpu: ttm finalized\n");
2005 }
2006
2007 /**
2008  * amdgpu_ttm_set_buffer_funcs_status - enable/disable use of buffer functions
2009  *
2010  * @adev: amdgpu_device pointer
2011  * @enable: true when we can use buffer functions.
2012  *
2013  * Enable/disable use of buffer functions during suspend/resume. This should
2014  * only be called at bootup or when userspace isn't running.
2015  */
2016 void amdgpu_ttm_set_buffer_funcs_status(struct amdgpu_device *adev, bool enable)
2017 {
2018         struct ttm_resource_manager *man = ttm_manager_type(&adev->mman.bdev, TTM_PL_VRAM);
2019         uint64_t size;
2020         int r;
2021
2022         if (!adev->mman.initialized || adev->in_gpu_reset ||
2023             adev->mman.buffer_funcs_enabled == enable)
2024                 return;
2025
2026         if (enable) {
2027                 struct amdgpu_ring *ring;
2028                 struct drm_gpu_scheduler *sched;
2029
2030                 ring = adev->mman.buffer_funcs_ring;
2031                 sched = &ring->sched;
2032                 r = drm_sched_entity_init(&adev->mman.entity,
2033                                           DRM_SCHED_PRIORITY_KERNEL, &sched,
2034                                           1, NULL);
2035                 if (r) {
2036                         DRM_ERROR("Failed setting up TTM BO move entity (%d)\n",
2037                                   r);
2038                         return;
2039                 }
2040         } else {
2041                 drm_sched_entity_destroy(&adev->mman.entity);
2042                 dma_fence_put(man->move);
2043                 man->move = NULL;
2044         }
2045
2046         /* this just adjusts TTM size idea, which sets lpfn to the correct value */
2047         if (enable)
2048                 size = adev->gmc.real_vram_size;
2049         else
2050                 size = adev->gmc.visible_vram_size;
2051         man->size = size >> PAGE_SHIFT;
2052         adev->mman.buffer_funcs_enabled = enable;
2053 }
2054
2055 int amdgpu_mmap(struct file *filp, struct vm_area_struct *vma)
2056 {
2057         struct drm_file *file_priv = filp->private_data;
2058         struct amdgpu_device *adev = file_priv->minor->dev->dev_private;
2059
2060         if (adev == NULL)
2061                 return -EINVAL;
2062
2063         return ttm_bo_mmap(filp, vma, &adev->mman.bdev);
2064 }
2065
2066 int amdgpu_copy_buffer(struct amdgpu_ring *ring, uint64_t src_offset,
2067                        uint64_t dst_offset, uint32_t byte_count,
2068                        struct dma_resv *resv,
2069                        struct dma_fence **fence, bool direct_submit,
2070                        bool vm_needs_flush, bool tmz)
2071 {
2072         enum amdgpu_ib_pool_type pool = direct_submit ? AMDGPU_IB_POOL_DIRECT :
2073                 AMDGPU_IB_POOL_DELAYED;
2074         struct amdgpu_device *adev = ring->adev;
2075         struct amdgpu_job *job;
2076
2077         uint32_t max_bytes;
2078         unsigned num_loops, num_dw;
2079         unsigned i;
2080         int r;
2081
2082         if (direct_submit && !ring->sched.ready) {
2083                 DRM_ERROR("Trying to move memory with ring turned off.\n");
2084                 return -EINVAL;
2085         }
2086
2087         max_bytes = adev->mman.buffer_funcs->copy_max_bytes;
2088         num_loops = DIV_ROUND_UP(byte_count, max_bytes);
2089         num_dw = ALIGN(num_loops * adev->mman.buffer_funcs->copy_num_dw, 8);
2090
2091         r = amdgpu_job_alloc_with_ib(adev, num_dw * 4, pool, &job);
2092         if (r)
2093                 return r;
2094
2095         if (vm_needs_flush) {
2096                 job->vm_pd_addr = amdgpu_gmc_pd_addr(adev->gart.bo);
2097                 job->vm_needs_flush = true;
2098         }
2099         if (resv) {
2100                 r = amdgpu_sync_resv(adev, &job->sync, resv,
2101                                      AMDGPU_SYNC_ALWAYS,
2102                                      AMDGPU_FENCE_OWNER_UNDEFINED);
2103                 if (r) {
2104                         DRM_ERROR("sync failed (%d).\n", r);
2105                         goto error_free;
2106                 }
2107         }
2108
2109         for (i = 0; i < num_loops; i++) {
2110                 uint32_t cur_size_in_bytes = min(byte_count, max_bytes);
2111
2112                 amdgpu_emit_copy_buffer(adev, &job->ibs[0], src_offset,
2113                                         dst_offset, cur_size_in_bytes, tmz);
2114
2115                 src_offset += cur_size_in_bytes;
2116                 dst_offset += cur_size_in_bytes;
2117                 byte_count -= cur_size_in_bytes;
2118         }
2119
2120         amdgpu_ring_pad_ib(ring, &job->ibs[0]);
2121         WARN_ON(job->ibs[0].length_dw > num_dw);
2122         if (direct_submit)
2123                 r = amdgpu_job_submit_direct(job, ring, fence);
2124         else
2125                 r = amdgpu_job_submit(job, &adev->mman.entity,
2126                                       AMDGPU_FENCE_OWNER_UNDEFINED, fence);
2127         if (r)
2128                 goto error_free;
2129
2130         return r;
2131
2132 error_free:
2133         amdgpu_job_free(job);
2134         DRM_ERROR("Error scheduling IBs (%d)\n", r);
2135         return r;
2136 }
2137
2138 int amdgpu_fill_buffer(struct amdgpu_bo *bo,
2139                        uint32_t src_data,
2140                        struct dma_resv *resv,
2141                        struct dma_fence **fence)
2142 {
2143         struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
2144         uint32_t max_bytes = adev->mman.buffer_funcs->fill_max_bytes;
2145         struct amdgpu_ring *ring = adev->mman.buffer_funcs_ring;
2146
2147         struct drm_mm_node *mm_node;
2148         unsigned long num_pages;
2149         unsigned int num_loops, num_dw;
2150
2151         struct amdgpu_job *job;
2152         int r;
2153
2154         if (!adev->mman.buffer_funcs_enabled) {
2155                 DRM_ERROR("Trying to clear memory with ring turned off.\n");
2156                 return -EINVAL;
2157         }
2158
2159         if (bo->tbo.mem.mem_type == TTM_PL_TT) {
2160                 r = amdgpu_ttm_alloc_gart(&bo->tbo);
2161                 if (r)
2162                         return r;
2163         }
2164
2165         num_pages = bo->tbo.num_pages;
2166         mm_node = bo->tbo.mem.mm_node;
2167         num_loops = 0;
2168         while (num_pages) {
2169                 uint64_t byte_count = mm_node->size << PAGE_SHIFT;
2170
2171                 num_loops += DIV_ROUND_UP_ULL(byte_count, max_bytes);
2172                 num_pages -= mm_node->size;
2173                 ++mm_node;
2174         }
2175         num_dw = num_loops * adev->mman.buffer_funcs->fill_num_dw;
2176
2177         /* for IB padding */
2178         num_dw += 64;
2179
2180         r = amdgpu_job_alloc_with_ib(adev, num_dw * 4, AMDGPU_IB_POOL_DELAYED,
2181                                      &job);
2182         if (r)
2183                 return r;
2184
2185         if (resv) {
2186                 r = amdgpu_sync_resv(adev, &job->sync, resv,
2187                                      AMDGPU_SYNC_ALWAYS,
2188                                      AMDGPU_FENCE_OWNER_UNDEFINED);
2189                 if (r) {
2190                         DRM_ERROR("sync failed (%d).\n", r);
2191                         goto error_free;
2192                 }
2193         }
2194
2195         num_pages = bo->tbo.num_pages;
2196         mm_node = bo->tbo.mem.mm_node;
2197
2198         while (num_pages) {
2199                 uint64_t byte_count = mm_node->size << PAGE_SHIFT;
2200                 uint64_t dst_addr;
2201
2202                 dst_addr = amdgpu_mm_node_addr(&bo->tbo, mm_node, &bo->tbo.mem);
2203                 while (byte_count) {
2204                         uint32_t cur_size_in_bytes = min_t(uint64_t, byte_count,
2205                                                            max_bytes);
2206
2207                         amdgpu_emit_fill_buffer(adev, &job->ibs[0], src_data,
2208                                                 dst_addr, cur_size_in_bytes);
2209
2210                         dst_addr += cur_size_in_bytes;
2211                         byte_count -= cur_size_in_bytes;
2212                 }
2213
2214                 num_pages -= mm_node->size;
2215                 ++mm_node;
2216         }
2217
2218         amdgpu_ring_pad_ib(ring, &job->ibs[0]);
2219         WARN_ON(job->ibs[0].length_dw > num_dw);
2220         r = amdgpu_job_submit(job, &adev->mman.entity,
2221                               AMDGPU_FENCE_OWNER_UNDEFINED, fence);
2222         if (r)
2223                 goto error_free;
2224
2225         return 0;
2226
2227 error_free:
2228         amdgpu_job_free(job);
2229         return r;
2230 }
2231
2232 #if defined(CONFIG_DEBUG_FS)
2233
2234 static int amdgpu_mm_dump_table(struct seq_file *m, void *data)
2235 {
2236         struct drm_info_node *node = (struct drm_info_node *)m->private;
2237         unsigned ttm_pl = (uintptr_t)node->info_ent->data;
2238         struct drm_device *dev = node->minor->dev;
2239         struct amdgpu_device *adev = dev->dev_private;
2240         struct ttm_resource_manager *man = ttm_manager_type(&adev->mman.bdev, ttm_pl);
2241         struct drm_printer p = drm_seq_file_printer(m);
2242
2243         man->func->debug(man, &p);
2244         return 0;
2245 }
2246
2247 static const struct drm_info_list amdgpu_ttm_debugfs_list[] = {
2248         {"amdgpu_vram_mm", amdgpu_mm_dump_table, 0, (void *)TTM_PL_VRAM},
2249         {"amdgpu_gtt_mm", amdgpu_mm_dump_table, 0, (void *)TTM_PL_TT},
2250         {"amdgpu_gds_mm", amdgpu_mm_dump_table, 0, (void *)AMDGPU_PL_GDS},
2251         {"amdgpu_gws_mm", amdgpu_mm_dump_table, 0, (void *)AMDGPU_PL_GWS},
2252         {"amdgpu_oa_mm", amdgpu_mm_dump_table, 0, (void *)AMDGPU_PL_OA},
2253         {"ttm_page_pool", ttm_page_alloc_debugfs, 0, NULL},
2254 #ifdef CONFIG_SWIOTLB
2255         {"ttm_dma_page_pool", ttm_dma_page_alloc_debugfs, 0, NULL}
2256 #endif
2257 };
2258
2259 /**
2260  * amdgpu_ttm_vram_read - Linear read access to VRAM
2261  *
2262  * Accesses VRAM via MMIO for debugging purposes.
2263  */
2264 static ssize_t amdgpu_ttm_vram_read(struct file *f, char __user *buf,
2265                                     size_t size, loff_t *pos)
2266 {
2267         struct amdgpu_device *adev = file_inode(f)->i_private;
2268         ssize_t result = 0;
2269
2270         if (size & 0x3 || *pos & 0x3)
2271                 return -EINVAL;
2272
2273         if (*pos >= adev->gmc.mc_vram_size)
2274                 return -ENXIO;
2275
2276         size = min(size, (size_t)(adev->gmc.mc_vram_size - *pos));
2277         while (size) {
2278                 size_t bytes = min(size, AMDGPU_TTM_VRAM_MAX_DW_READ * 4);
2279                 uint32_t value[AMDGPU_TTM_VRAM_MAX_DW_READ];
2280
2281                 amdgpu_device_vram_access(adev, *pos, value, bytes, false);
2282                 if (copy_to_user(buf, value, bytes))
2283                         return -EFAULT;
2284
2285                 result += bytes;
2286                 buf += bytes;
2287                 *pos += bytes;
2288                 size -= bytes;
2289         }
2290
2291         return result;
2292 }
2293
2294 /**
2295  * amdgpu_ttm_vram_write - Linear write access to VRAM
2296  *
2297  * Accesses VRAM via MMIO for debugging purposes.
2298  */
2299 static ssize_t amdgpu_ttm_vram_write(struct file *f, const char __user *buf,
2300                                     size_t size, loff_t *pos)
2301 {
2302         struct amdgpu_device *adev = file_inode(f)->i_private;
2303         ssize_t result = 0;
2304         int r;
2305
2306         if (size & 0x3 || *pos & 0x3)
2307                 return -EINVAL;
2308
2309         if (*pos >= adev->gmc.mc_vram_size)
2310                 return -ENXIO;
2311
2312         while (size) {
2313                 unsigned long flags;
2314                 uint32_t value;
2315
2316                 if (*pos >= adev->gmc.mc_vram_size)
2317                         return result;
2318
2319                 r = get_user(value, (uint32_t *)buf);
2320                 if (r)
2321                         return r;
2322
2323                 spin_lock_irqsave(&adev->mmio_idx_lock, flags);
2324                 WREG32_NO_KIQ(mmMM_INDEX, ((uint32_t)*pos) | 0x80000000);
2325                 WREG32_NO_KIQ(mmMM_INDEX_HI, *pos >> 31);
2326                 WREG32_NO_KIQ(mmMM_DATA, value);
2327                 spin_unlock_irqrestore(&adev->mmio_idx_lock, flags);
2328
2329                 result += 4;
2330                 buf += 4;
2331                 *pos += 4;
2332                 size -= 4;
2333         }
2334
2335         return result;
2336 }
2337
2338 static const struct file_operations amdgpu_ttm_vram_fops = {
2339         .owner = THIS_MODULE,
2340         .read = amdgpu_ttm_vram_read,
2341         .write = amdgpu_ttm_vram_write,
2342         .llseek = default_llseek,
2343 };
2344
2345 #ifdef CONFIG_DRM_AMDGPU_GART_DEBUGFS
2346
2347 /**
2348  * amdgpu_ttm_gtt_read - Linear read access to GTT memory
2349  */
2350 static ssize_t amdgpu_ttm_gtt_read(struct file *f, char __user *buf,
2351                                    size_t size, loff_t *pos)
2352 {
2353         struct amdgpu_device *adev = file_inode(f)->i_private;
2354         ssize_t result = 0;
2355         int r;
2356
2357         while (size) {
2358                 loff_t p = *pos / PAGE_SIZE;
2359                 unsigned off = *pos & ~PAGE_MASK;
2360                 size_t cur_size = min_t(size_t, size, PAGE_SIZE - off);
2361                 struct page *page;
2362                 void *ptr;
2363
2364                 if (p >= adev->gart.num_cpu_pages)
2365                         return result;
2366
2367                 page = adev->gart.pages[p];
2368                 if (page) {
2369                         ptr = kmap(page);
2370                         ptr += off;
2371
2372                         r = copy_to_user(buf, ptr, cur_size);
2373                         kunmap(adev->gart.pages[p]);
2374                 } else
2375                         r = clear_user(buf, cur_size);
2376
2377                 if (r)
2378                         return -EFAULT;
2379
2380                 result += cur_size;
2381                 buf += cur_size;
2382                 *pos += cur_size;
2383                 size -= cur_size;
2384         }
2385
2386         return result;
2387 }
2388
2389 static const struct file_operations amdgpu_ttm_gtt_fops = {
2390         .owner = THIS_MODULE,
2391         .read = amdgpu_ttm_gtt_read,
2392         .llseek = default_llseek
2393 };
2394
2395 #endif
2396
2397 /**
2398  * amdgpu_iomem_read - Virtual read access to GPU mapped memory
2399  *
2400  * This function is used to read memory that has been mapped to the
2401  * GPU and the known addresses are not physical addresses but instead
2402  * bus addresses (e.g., what you'd put in an IB or ring buffer).
2403  */
2404 static ssize_t amdgpu_iomem_read(struct file *f, char __user *buf,
2405                                  size_t size, loff_t *pos)
2406 {
2407         struct amdgpu_device *adev = file_inode(f)->i_private;
2408         struct iommu_domain *dom;
2409         ssize_t result = 0;
2410         int r;
2411
2412         /* retrieve the IOMMU domain if any for this device */
2413         dom = iommu_get_domain_for_dev(adev->dev);
2414
2415         while (size) {
2416                 phys_addr_t addr = *pos & PAGE_MASK;
2417                 loff_t off = *pos & ~PAGE_MASK;
2418                 size_t bytes = PAGE_SIZE - off;
2419                 unsigned long pfn;
2420                 struct page *p;
2421                 void *ptr;
2422
2423                 bytes = bytes < size ? bytes : size;
2424
2425                 /* Translate the bus address to a physical address.  If
2426                  * the domain is NULL it means there is no IOMMU active
2427                  * and the address translation is the identity
2428                  */
2429                 addr = dom ? iommu_iova_to_phys(dom, addr) : addr;
2430
2431                 pfn = addr >> PAGE_SHIFT;
2432                 if (!pfn_valid(pfn))
2433                         return -EPERM;
2434
2435                 p = pfn_to_page(pfn);
2436                 if (p->mapping != adev->mman.bdev.dev_mapping)
2437                         return -EPERM;
2438
2439                 ptr = kmap(p);
2440                 r = copy_to_user(buf, ptr + off, bytes);
2441                 kunmap(p);
2442                 if (r)
2443                         return -EFAULT;
2444
2445                 size -= bytes;
2446                 *pos += bytes;
2447                 result += bytes;
2448         }
2449
2450         return result;
2451 }
2452
2453 /**
2454  * amdgpu_iomem_write - Virtual write access to GPU mapped memory
2455  *
2456  * This function is used to write memory that has been mapped to the
2457  * GPU and the known addresses are not physical addresses but instead
2458  * bus addresses (e.g., what you'd put in an IB or ring buffer).
2459  */
2460 static ssize_t amdgpu_iomem_write(struct file *f, const char __user *buf,
2461                                  size_t size, loff_t *pos)
2462 {
2463         struct amdgpu_device *adev = file_inode(f)->i_private;
2464         struct iommu_domain *dom;
2465         ssize_t result = 0;
2466         int r;
2467
2468         dom = iommu_get_domain_for_dev(adev->dev);
2469
2470         while (size) {
2471                 phys_addr_t addr = *pos & PAGE_MASK;
2472                 loff_t off = *pos & ~PAGE_MASK;
2473                 size_t bytes = PAGE_SIZE - off;
2474                 unsigned long pfn;
2475                 struct page *p;
2476                 void *ptr;
2477
2478                 bytes = bytes < size ? bytes : size;
2479
2480                 addr = dom ? iommu_iova_to_phys(dom, addr) : addr;
2481
2482                 pfn = addr >> PAGE_SHIFT;
2483                 if (!pfn_valid(pfn))
2484                         return -EPERM;
2485
2486                 p = pfn_to_page(pfn);
2487                 if (p->mapping != adev->mman.bdev.dev_mapping)
2488                         return -EPERM;
2489
2490                 ptr = kmap(p);
2491                 r = copy_from_user(ptr + off, buf, bytes);
2492                 kunmap(p);
2493                 if (r)
2494                         return -EFAULT;
2495
2496                 size -= bytes;
2497                 *pos += bytes;
2498                 result += bytes;
2499         }
2500
2501         return result;
2502 }
2503
2504 static const struct file_operations amdgpu_ttm_iomem_fops = {
2505         .owner = THIS_MODULE,
2506         .read = amdgpu_iomem_read,
2507         .write = amdgpu_iomem_write,
2508         .llseek = default_llseek
2509 };
2510
2511 static const struct {
2512         char *name;
2513         const struct file_operations *fops;
2514         int domain;
2515 } ttm_debugfs_entries[] = {
2516         { "amdgpu_vram", &amdgpu_ttm_vram_fops, TTM_PL_VRAM },
2517 #ifdef CONFIG_DRM_AMDGPU_GART_DEBUGFS
2518         { "amdgpu_gtt", &amdgpu_ttm_gtt_fops, TTM_PL_TT },
2519 #endif
2520         { "amdgpu_iomem", &amdgpu_ttm_iomem_fops, TTM_PL_SYSTEM },
2521 };
2522
2523 #endif
2524
2525 int amdgpu_ttm_debugfs_init(struct amdgpu_device *adev)
2526 {
2527 #if defined(CONFIG_DEBUG_FS)
2528         unsigned count;
2529
2530         struct drm_minor *minor = adev->ddev->primary;
2531         struct dentry *ent, *root = minor->debugfs_root;
2532
2533         for (count = 0; count < ARRAY_SIZE(ttm_debugfs_entries); count++) {
2534                 ent = debugfs_create_file(
2535                                 ttm_debugfs_entries[count].name,
2536                                 S_IFREG | S_IRUGO, root,
2537                                 adev,
2538                                 ttm_debugfs_entries[count].fops);
2539                 if (IS_ERR(ent))
2540                         return PTR_ERR(ent);
2541                 if (ttm_debugfs_entries[count].domain == TTM_PL_VRAM)
2542                         i_size_write(ent->d_inode, adev->gmc.mc_vram_size);
2543                 else if (ttm_debugfs_entries[count].domain == TTM_PL_TT)
2544                         i_size_write(ent->d_inode, adev->gmc.gart_size);
2545                 adev->mman.debugfs_entries[count] = ent;
2546         }
2547
2548         count = ARRAY_SIZE(amdgpu_ttm_debugfs_list);
2549
2550 #ifdef CONFIG_SWIOTLB
2551         if (!(adev->need_swiotlb && swiotlb_nr_tbl()))
2552                 --count;
2553 #endif
2554
2555         return amdgpu_debugfs_add_files(adev, amdgpu_ttm_debugfs_list, count);
2556 #else
2557         return 0;
2558 #endif
2559 }