drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c

   1 /*
   2  * Copyright 2009 Jerome Glisse.
   3  * All Rights Reserved.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the
   7  * "Software"), to deal in the Software without restriction, including
   8  * without limitation the rights to use, copy, modify, merge, publish,
   9  * distribute, sub license, and/or sell copies of the Software, and to
  10  * permit persons to whom the Software is furnished to do so, subject to
  11  * the following conditions:
  12  *
  13  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  14  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  15  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  16  * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
  17  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  18  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  19  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  20  *
  21  * The above copyright notice and this permission notice (including the
  22  * next paragraph) shall be included in all copies or substantial portions
  23  * of the Software.
  24  *
  25  */
  26 /*
  27  * Authors:
  28  *    Jerome Glisse <glisse@freedesktop.org>
  29  *    Thomas Hellstrom <thomas-at-tungstengraphics-dot-com>
  30  *    Dave Airlie
  31  */
  32
  33 #include <linux/dma-mapping.h>
  34 #include <linux/iommu.h>
  35 #include <linux/hmm.h>
  36 #include <linux/pagemap.h>
  37 #include <linux/sched/task.h>
  38 #include <linux/sched/mm.h>
  39 #include <linux/seq_file.h>
  40 #include <linux/slab.h>
  41 #include <linux/swap.h>
  42 #include <linux/swiotlb.h>
  43 #include <linux/dma-buf.h>
  44 #include <linux/sizes.h>
  45
  46 #include <drm/ttm/ttm_bo_api.h>
  47 #include <drm/ttm/ttm_bo_driver.h>
  48 #include <drm/ttm/ttm_placement.h>
  49 #include <drm/ttm/ttm_module.h>
  50 #include <drm/ttm/ttm_page_alloc.h>
  51
  52 #include <drm/drm_debugfs.h>
  53 #include <drm/amdgpu_drm.h>
  54
  55 #include "amdgpu.h"
  56 #include "amdgpu_object.h"
  57 #include "amdgpu_trace.h"
  58 #include "amdgpu_amdkfd.h"
  59 #include "amdgpu_sdma.h"
  60 #include "amdgpu_ras.h"
  61 #include "amdgpu_atomfirmware.h"
  62 #include "bif/bif_4_1_d.h"
  63
  64 #define AMDGPU_TTM_VRAM_MAX_DW_READ     (size_t)128
  65
  66 static int amdgpu_ttm_init_on_chip(struct amdgpu_device *adev,
  67                                     unsigned int type,
  68                                     uint64_t size)
  69 {
  70         return ttm_range_man_init(&adev->mman.bdev, type,
  71                                   TTM_PL_FLAG_UNCACHED,
  72                                   false, size >> PAGE_SHIFT);
  73 }
  74
  75 /**
  76  * amdgpu_evict_flags - Compute placement flags
  77  *
  78  * @bo: The buffer object to evict
  79  * @placement: Possible destination(s) for evicted BO
  80  *
  81  * Fill in placement data when ttm_bo_evict() is called
  82  */
  83 static void amdgpu_evict_flags(struct ttm_buffer_object *bo,
  84                                 struct ttm_placement *placement)
  85 {
  86         struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev);
  87         struct amdgpu_bo *abo;
  88         static const struct ttm_place placements = {
  89                 .fpfn = 0,
  90                 .lpfn = 0,
  91                 .mem_type = TTM_PL_SYSTEM,
  92                 .flags = TTM_PL_MASK_CACHING
  93         };
  94
  95         /* Don't handle scatter gather BOs */
  96         if (bo->type == ttm_bo_type_sg) {
  97                 placement->num_placement = 0;
  98                 placement->num_busy_placement = 0;
  99                 return;
 100         }
 101
 102         /* Object isn't an AMDGPU object so ignore */
 103         if (!amdgpu_bo_is_amdgpu_bo(bo)) {
 104                 placement->placement = &placements;
 105                 placement->busy_placement = &placements;
 106                 placement->num_placement = 1;
 107                 placement->num_busy_placement = 1;
 108                 return;
 109         }
 110
 111         abo = ttm_to_amdgpu_bo(bo);
 112         switch (bo->mem.mem_type) {
 113         case AMDGPU_PL_GDS:
 114         case AMDGPU_PL_GWS:
 115         case AMDGPU_PL_OA:
 116                 placement->num_placement = 0;
 117                 placement->num_busy_placement = 0;
 118                 return;
 119
 120         case TTM_PL_VRAM:
 121                 if (!adev->mman.buffer_funcs_enabled) {
 122                         /* Move to system memory */
 123                         amdgpu_bo_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_CPU);
 124                 } else if (!amdgpu_gmc_vram_full_visible(&adev->gmc) &&
 125                            !(abo->flags & AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED) &&
 126                            amdgpu_bo_in_cpu_visible_vram(abo)) {
 127
 128                         /* Try evicting to the CPU inaccessible part of VRAM
 129                          * first, but only set GTT as busy placement, so this
 130                          * BO will be evicted to GTT rather than causing other
 131                          * BOs to be evicted from VRAM
 132                          */
 133                         amdgpu_bo_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_VRAM |
 134                                                          AMDGPU_GEM_DOMAIN_GTT);
 135                         abo->placements[0].fpfn = adev->gmc.visible_vram_size >> PAGE_SHIFT;
 136                         abo->placements[0].lpfn = 0;
 137                         abo->placement.busy_placement = &abo->placements[1];
 138                         abo->placement.num_busy_placement = 1;
 139                 } else {
 140                         /* Move to GTT memory */
 141                         amdgpu_bo_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_GTT);
 142                 }
 143                 break;
 144         case TTM_PL_TT:
 145         default:
 146                 amdgpu_bo_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_CPU);
 147                 break;
 148         }
 149         *placement = abo->placement;
 150 }
 151
 152 /**
 153  * amdgpu_verify_access - Verify access for a mmap call
 154  *
 155  * @bo: The buffer object to map
 156  * @filp: The file pointer from the process performing the mmap
 157  *
 158  * This is called by ttm_bo_mmap() to verify whether a process
 159  * has the right to mmap a BO to their process space.
 160  */
 161 static int amdgpu_verify_access(struct ttm_buffer_object *bo, struct file *filp)
 162 {
 163         struct amdgpu_bo *abo = ttm_to_amdgpu_bo(bo);
 164
 165         /*
 166          * Don't verify access for KFD BOs. They don't have a GEM
 167          * object associated with them.
 168          */
 169         if (abo->kfd_bo)
 170                 return 0;
 171
 172         if (amdgpu_ttm_tt_get_usermm(bo->ttm))
 173                 return -EPERM;
 174         return drm_vma_node_verify_access(&abo->tbo.base.vma_node,
 175                                           filp->private_data);
 176 }
 177
 178 /**
 179  * amdgpu_mm_node_addr - Compute the GPU relative offset of a GTT buffer.
 180  *
 181  * @bo: The bo to assign the memory to.
 182  * @mm_node: Memory manager node for drm allocator.
 183  * @mem: The region where the bo resides.
 184  *
 185  */
 186 static uint64_t amdgpu_mm_node_addr(struct ttm_buffer_object *bo,
 187                                     struct drm_mm_node *mm_node,
 188                                     struct ttm_resource *mem)
 189 {
 190         uint64_t addr = 0;
 191
 192         if (mm_node->start != AMDGPU_BO_INVALID_OFFSET) {
 193                 addr = mm_node->start << PAGE_SHIFT;
 194                 addr += amdgpu_ttm_domain_start(amdgpu_ttm_adev(bo->bdev),
 195                                                 mem->mem_type);
 196         }
 197         return addr;
 198 }
 199
 200 /**
 201  * amdgpu_find_mm_node - Helper function finds the drm_mm_node corresponding to
 202  * @offset. It also modifies the offset to be within the drm_mm_node returned
 203  *
 204  * @mem: The region where the bo resides.
 205  * @offset: The offset that drm_mm_node is used for finding.
 206  *
 207  */
 208 static struct drm_mm_node *amdgpu_find_mm_node(struct ttm_resource *mem,
 209                                                uint64_t *offset)
 210 {
 211         struct drm_mm_node *mm_node = mem->mm_node;
 212
 213         while (*offset >= (mm_node->size << PAGE_SHIFT)) {
 214                 *offset -= (mm_node->size << PAGE_SHIFT);
 215                 ++mm_node;
 216         }
 217         return mm_node;
 218 }
 219
 220 /**
 221  * amdgpu_ttm_map_buffer - Map memory into the GART windows
 222  * @bo: buffer object to map
 223  * @mem: memory object to map
 224  * @mm_node: drm_mm node object to map
 225  * @num_pages: number of pages to map
 226  * @offset: offset into @mm_node where to start
 227  * @window: which GART window to use
 228  * @ring: DMA ring to use for the copy
 229  * @tmz: if we should setup a TMZ enabled mapping
 230  * @addr: resulting address inside the MC address space
 231  *
 232  * Setup one of the GART windows to access a specific piece of memory or return
 233  * the physical address for local memory.
 234  */
 235 static int amdgpu_ttm_map_buffer(struct ttm_buffer_object *bo,
 236                                  struct ttm_resource *mem,
 237                                  struct drm_mm_node *mm_node,
 238                                  unsigned num_pages, uint64_t offset,
 239                                  unsigned window, struct amdgpu_ring *ring,
 240                                  bool tmz, uint64_t *addr)
 241 {
 242         struct amdgpu_device *adev = ring->adev;
 243         struct amdgpu_job *job;
 244         unsigned num_dw, num_bytes;
 245         struct dma_fence *fence;
 246         uint64_t src_addr, dst_addr;
 247         void *cpu_addr;
 248         uint64_t flags;
 249         unsigned int i;
 250         int r;
 251
 252         BUG_ON(adev->mman.buffer_funcs->copy_max_bytes <
 253                AMDGPU_GTT_MAX_TRANSFER_SIZE * 8);
 254
 255         /* Map only what can't be accessed directly */
 256         if (!tmz && mem->start != AMDGPU_BO_INVALID_OFFSET) {
 257                 *addr = amdgpu_mm_node_addr(bo, mm_node, mem) + offset;
 258                 return 0;
 259         }
 260
 261         *addr = adev->gmc.gart_start;
 262         *addr += (u64)window * AMDGPU_GTT_MAX_TRANSFER_SIZE *
 263                 AMDGPU_GPU_PAGE_SIZE;
 264         *addr += offset & ~PAGE_MASK;
 265
 266         num_dw = ALIGN(adev->mman.buffer_funcs->copy_num_dw, 8);
 267         num_bytes = num_pages * 8;
 268
 269         r = amdgpu_job_alloc_with_ib(adev, num_dw * 4 + num_bytes,
 270                                      AMDGPU_IB_POOL_DELAYED, &job);
 271         if (r)
 272                 return r;
 273
 274         src_addr = num_dw * 4;
 275         src_addr += job->ibs[0].gpu_addr;
 276
 277         dst_addr = amdgpu_bo_gpu_offset(adev->gart.bo);
 278         dst_addr += window * AMDGPU_GTT_MAX_TRANSFER_SIZE * 8;
 279         amdgpu_emit_copy_buffer(adev, &job->ibs[0], src_addr,
 280                                 dst_addr, num_bytes, false);
 281
 282         amdgpu_ring_pad_ib(ring, &job->ibs[0]);
 283         WARN_ON(job->ibs[0].length_dw > num_dw);
 284
 285         flags = amdgpu_ttm_tt_pte_flags(adev, bo->ttm, mem);
 286         if (tmz)
 287                 flags |= AMDGPU_PTE_TMZ;
 288
 289         cpu_addr = &job->ibs[0].ptr[num_dw];
 290
 291         if (mem->mem_type == TTM_PL_TT) {
 292                 struct ttm_dma_tt *dma;
 293                 dma_addr_t *dma_address;
 294
 295                 dma = container_of(bo->ttm, struct ttm_dma_tt, ttm);
 296                 dma_address = &dma->dma_address[offset >> PAGE_SHIFT];
 297                 r = amdgpu_gart_map(adev, 0, num_pages, dma_address, flags,
 298                                     cpu_addr);
 299                 if (r)
 300                         goto error_free;
 301         } else {
 302                 dma_addr_t dma_address;
 303
 304                 dma_address = (mm_node->start << PAGE_SHIFT) + offset;
 305                 dma_address += adev->vm_manager.vram_base_offset;
 306
 307                 for (i = 0; i < num_pages; ++i) {
 308                         r = amdgpu_gart_map(adev, i << PAGE_SHIFT, 1,
 309                                             &dma_address, flags, cpu_addr);
 310                         if (r)
 311                                 goto error_free;
 312
 313                         dma_address += PAGE_SIZE;
 314                 }
 315         }
 316
 317         r = amdgpu_job_submit(job, &adev->mman.entity,
 318                               AMDGPU_FENCE_OWNER_UNDEFINED, &fence);
 319         if (r)
 320                 goto error_free;
 321
 322         dma_fence_put(fence);
 323
 324         return r;
 325
 326 error_free:
 327         amdgpu_job_free(job);
 328         return r;
 329 }
 330
 331 /**
 332  * amdgpu_copy_ttm_mem_to_mem - Helper function for copy
 333  * @adev: amdgpu device
 334  * @src: buffer/address where to read from
 335  * @dst: buffer/address where to write to
 336  * @size: number of bytes to copy
 337  * @tmz: if a secure copy should be used
 338  * @resv: resv object to sync to
 339  * @f: Returns the last fence if multiple jobs are submitted.
 340  *
 341  * The function copies @size bytes from {src->mem + src->offset} to
 342  * {dst->mem + dst->offset}. src->bo and dst->bo could be same BO for a
 343  * move and different for a BO to BO copy.
 344  *
 345  */
 346 int amdgpu_ttm_copy_mem_to_mem(struct amdgpu_device *adev,
 347                                const struct amdgpu_copy_mem *src,
 348                                const struct amdgpu_copy_mem *dst,
 349                                uint64_t size, bool tmz,
 350                                struct dma_resv *resv,
 351                                struct dma_fence **f)
 352 {
 353         const uint32_t GTT_MAX_BYTES = (AMDGPU_GTT_MAX_TRANSFER_SIZE *
 354                                         AMDGPU_GPU_PAGE_SIZE);
 355
 356         uint64_t src_node_size, dst_node_size, src_offset, dst_offset;
 357         struct amdgpu_ring *ring = adev->mman.buffer_funcs_ring;
 358         struct drm_mm_node *src_mm, *dst_mm;
 359         struct dma_fence *fence = NULL;
 360         int r = 0;
 361
 362         if (!adev->mman.buffer_funcs_enabled) {
 363                 DRM_ERROR("Trying to move memory with ring turned off.\n");
 364                 return -EINVAL;
 365         }
 366
 367         src_offset = src->offset;
 368         if (src->mem->mm_node) {
 369                 src_mm = amdgpu_find_mm_node(src->mem, &src_offset);
 370                 src_node_size = (src_mm->size << PAGE_SHIFT) - src_offset;
 371         } else {
 372                 src_mm = NULL;
 373                 src_node_size = ULLONG_MAX;
 374         }
 375
 376         dst_offset = dst->offset;
 377         if (dst->mem->mm_node) {
 378                 dst_mm = amdgpu_find_mm_node(dst->mem, &dst_offset);
 379                 dst_node_size = (dst_mm->size << PAGE_SHIFT) - dst_offset;
 380         } else {
 381                 dst_mm = NULL;
 382                 dst_node_size = ULLONG_MAX;
 383         }
 384
 385         mutex_lock(&adev->mman.gtt_window_lock);
 386
 387         while (size) {
 388                 uint32_t src_page_offset = src_offset & ~PAGE_MASK;
 389                 uint32_t dst_page_offset = dst_offset & ~PAGE_MASK;
 390                 struct dma_fence *next;
 391                 uint32_t cur_size;
 392                 uint64_t from, to;
 393
 394                 /* Copy size cannot exceed GTT_MAX_BYTES. So if src or dst
 395                  * begins at an offset, then adjust the size accordingly
 396                  */
 397                 cur_size = max(src_page_offset, dst_page_offset);
 398                 cur_size = min(min3(src_node_size, dst_node_size, size),
 399                                (uint64_t)(GTT_MAX_BYTES - cur_size));
 400
 401                 /* Map src to window 0 and dst to window 1. */
 402                 r = amdgpu_ttm_map_buffer(src->bo, src->mem, src_mm,
 403                                           PFN_UP(cur_size + src_page_offset),
 404                                           src_offset, 0, ring, tmz, &from);
 405                 if (r)
 406                         goto error;
 407
 408                 r = amdgpu_ttm_map_buffer(dst->bo, dst->mem, dst_mm,
 409                                           PFN_UP(cur_size + dst_page_offset),
 410                                           dst_offset, 1, ring, tmz, &to);
 411                 if (r)
 412                         goto error;
 413
 414                 r = amdgpu_copy_buffer(ring, from, to, cur_size,
 415                                        resv, &next, false, true, tmz);
 416                 if (r)
 417                         goto error;
 418
 419                 dma_fence_put(fence);
 420                 fence = next;
 421
 422                 size -= cur_size;
 423                 if (!size)
 424                         break;
 425
 426                 src_node_size -= cur_size;
 427                 if (!src_node_size) {
 428                         ++src_mm;
 429                         src_node_size = src_mm->size << PAGE_SHIFT;
 430                         src_offset = 0;
 431                 } else {
 432                         src_offset += cur_size;
 433                 }
 434
 435                 dst_node_size -= cur_size;
 436                 if (!dst_node_size) {
 437                         ++dst_mm;
 438                         dst_node_size = dst_mm->size << PAGE_SHIFT;
 439                         dst_offset = 0;
 440                 } else {
 441                         dst_offset += cur_size;
 442                 }
 443         }
 444 error:
 445         mutex_unlock(&adev->mman.gtt_window_lock);
 446         if (f)
 447                 *f = dma_fence_get(fence);
 448         dma_fence_put(fence);
 449         return r;
 450 }
 451
 452 /**
 453  * amdgpu_move_blit - Copy an entire buffer to another buffer
 454  *
 455  * This is a helper called by amdgpu_bo_move() and amdgpu_move_vram_ram() to
 456  * help move buffers to and from VRAM.
 457  */
 458 static int amdgpu_move_blit(struct ttm_buffer_object *bo,
 459                             bool evict,
 460                             struct ttm_resource *new_mem,
 461                             struct ttm_resource *old_mem)
 462 {
 463         struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev);
 464         struct amdgpu_bo *abo = ttm_to_amdgpu_bo(bo);
 465         struct amdgpu_copy_mem src, dst;
 466         struct dma_fence *fence = NULL;
 467         int r;
 468
 469         src.bo = bo;
 470         dst.bo = bo;
 471         src.mem = old_mem;
 472         dst.mem = new_mem;
 473         src.offset = 0;
 474         dst.offset = 0;
 475
 476         r = amdgpu_ttm_copy_mem_to_mem(adev, &src, &dst,
 477                                        new_mem->num_pages << PAGE_SHIFT,
 478                                        amdgpu_bo_encrypted(abo),
 479                                        bo->base.resv, &fence);
 480         if (r)
 481                 goto error;
 482
 483         /* clear the space being freed */
 484         if (old_mem->mem_type == TTM_PL_VRAM &&
 485             (abo->flags & AMDGPU_GEM_CREATE_VRAM_WIPE_ON_RELEASE)) {
 486                 struct dma_fence *wipe_fence = NULL;
 487
 488                 r = amdgpu_fill_buffer(ttm_to_amdgpu_bo(bo), AMDGPU_POISON,
 489                                        NULL, &wipe_fence);
 490                 if (r) {
 491                         goto error;
 492                 } else if (wipe_fence) {
 493                         dma_fence_put(fence);
 494                         fence = wipe_fence;
 495                 }
 496         }
 497
 498         /* Always block for VM page tables before committing the new location */
 499         if (bo->type == ttm_bo_type_kernel)
 500                 r = ttm_bo_move_accel_cleanup(bo, fence, true, new_mem);
 501         else
 502                 r = ttm_bo_pipeline_move(bo, fence, evict, new_mem);
 503         dma_fence_put(fence);
 504         return r;
 505
 506 error:
 507         if (fence)
 508                 dma_fence_wait(fence, false);
 509         dma_fence_put(fence);
 510         return r;
 511 }
 512
 513 /**
 514  * amdgpu_move_vram_ram - Copy VRAM buffer to RAM buffer
 515  *
 516  * Called by amdgpu_bo_move().
 517  */
 518 static int amdgpu_move_vram_ram(struct ttm_buffer_object *bo, bool evict,
 519                                 struct ttm_operation_ctx *ctx,
 520                                 struct ttm_resource *new_mem)
 521 {
 522         struct ttm_resource *old_mem = &bo->mem;
 523         struct ttm_resource tmp_mem;
 524         struct ttm_place placements;
 525         struct ttm_placement placement;
 526         int r;
 527
 528         /* create space/pages for new_mem in GTT space */
 529         tmp_mem = *new_mem;
 530         tmp_mem.mm_node = NULL;
 531         placement.num_placement = 1;
 532         placement.placement = &placements;
 533         placement.num_busy_placement = 1;
 534         placement.busy_placement = &placements;
 535         placements.fpfn = 0;
 536         placements.lpfn = 0;
 537         placements.mem_type = TTM_PL_TT;
 538         placements.flags = TTM_PL_MASK_CACHING;
 539         r = ttm_bo_mem_space(bo, &placement, &tmp_mem, ctx);
 540         if (unlikely(r)) {
 541                 pr_err("Failed to find GTT space for blit from VRAM\n");
 542                 return r;
 543         }
 544
 545         /* set caching flags */
 546         r = ttm_tt_set_placement_caching(bo->ttm, tmp_mem.placement);
 547         if (unlikely(r)) {
 548                 goto out_cleanup;
 549         }
 550
 551         /* Bind the memory to the GTT space */
 552         r = ttm_tt_bind(bo->bdev, bo->ttm, &tmp_mem, ctx);
 553         if (unlikely(r)) {
 554                 goto out_cleanup;
 555         }
 556
 557         /* blit VRAM to GTT */
 558         r = amdgpu_move_blit(bo, evict, &tmp_mem, old_mem);
 559         if (unlikely(r)) {
 560                 goto out_cleanup;
 561         }
 562
 563         /* move BO (in tmp_mem) to new_mem */
 564         r = ttm_bo_move_ttm(bo, ctx, new_mem);
 565 out_cleanup:
 566         ttm_resource_free(bo, &tmp_mem);
 567         return r;
 568 }
 569
 570 /**
 571  * amdgpu_move_ram_vram - Copy buffer from RAM to VRAM
 572  *
 573  * Called by amdgpu_bo_move().
 574  */
 575 static int amdgpu_move_ram_vram(struct ttm_buffer_object *bo, bool evict,
 576                                 struct ttm_operation_ctx *ctx,
 577                                 struct ttm_resource *new_mem)
 578 {
 579         struct ttm_resource *old_mem = &bo->mem;
 580         struct ttm_resource tmp_mem;
 581         struct ttm_placement placement;
 582         struct ttm_place placements;
 583         int r;
 584
 585         /* make space in GTT for old_mem buffer */
 586         tmp_mem = *new_mem;
 587         tmp_mem.mm_node = NULL;
 588         placement.num_placement = 1;
 589         placement.placement = &placements;
 590         placement.num_busy_placement = 1;
 591         placement.busy_placement = &placements;
 592         placements.fpfn = 0;
 593         placements.lpfn = 0;
 594         placements.mem_type = TTM_PL_TT;
 595         placements.flags = TTM_PL_MASK_CACHING;
 596         r = ttm_bo_mem_space(bo, &placement, &tmp_mem, ctx);
 597         if (unlikely(r)) {
 598                 pr_err("Failed to find GTT space for blit to VRAM\n");
 599                 return r;
 600         }
 601
 602         /* move/bind old memory to GTT space */
 603         r = ttm_bo_move_ttm(bo, ctx, &tmp_mem);
 604         if (unlikely(r)) {
 605                 goto out_cleanup;
 606         }
 607
 608         /* copy to VRAM */
 609         r = amdgpu_move_blit(bo, evict, new_mem, old_mem);
 610         if (unlikely(r)) {
 611                 goto out_cleanup;
 612         }
 613 out_cleanup:
 614         ttm_resource_free(bo, &tmp_mem);
 615         return r;
 616 }
 617
 618 /**
 619  * amdgpu_mem_visible - Check that memory can be accessed by ttm_bo_move_memcpy
 620  *
 621  * Called by amdgpu_bo_move()
 622  */
 623 static bool amdgpu_mem_visible(struct amdgpu_device *adev,
 624                                struct ttm_resource *mem)
 625 {
 626         struct drm_mm_node *nodes = mem->mm_node;
 627
 628         if (mem->mem_type == TTM_PL_SYSTEM ||
 629             mem->mem_type == TTM_PL_TT)
 630                 return true;
 631         if (mem->mem_type != TTM_PL_VRAM)
 632                 return false;
 633
 634         /* ttm_resource_ioremap only supports contiguous memory */
 635         if (nodes->size != mem->num_pages)
 636                 return false;
 637
 638         return ((nodes->start + nodes->size) << PAGE_SHIFT)
 639                 <= adev->gmc.visible_vram_size;
 640 }
 641
 642 /**
 643  * amdgpu_bo_move - Move a buffer object to a new memory location
 644  *
 645  * Called by ttm_bo_handle_move_mem()
 646  */
 647 static int amdgpu_bo_move(struct ttm_buffer_object *bo, bool evict,
 648                           struct ttm_operation_ctx *ctx,
 649                           struct ttm_resource *new_mem)
 650 {
 651         struct amdgpu_device *adev;
 652         struct amdgpu_bo *abo;
 653         struct ttm_resource *old_mem = &bo->mem;
 654         int r;
 655
 656         /* Can't move a pinned BO */
 657         abo = ttm_to_amdgpu_bo(bo);
 658         if (WARN_ON_ONCE(abo->pin_count > 0))
 659                 return -EINVAL;
 660
 661         adev = amdgpu_ttm_adev(bo->bdev);
 662
 663         if (old_mem->mem_type == TTM_PL_SYSTEM && bo->ttm == NULL) {
 664                 ttm_bo_move_null(bo, new_mem);
 665                 return 0;
 666         }
 667         if ((old_mem->mem_type == TTM_PL_TT &&
 668              new_mem->mem_type == TTM_PL_SYSTEM) ||
 669             (old_mem->mem_type == TTM_PL_SYSTEM &&
 670              new_mem->mem_type == TTM_PL_TT)) {
 671                 /* bind is enough */
 672                 ttm_bo_move_null(bo, new_mem);
 673                 return 0;
 674         }
 675         if (old_mem->mem_type == AMDGPU_PL_GDS ||
 676             old_mem->mem_type == AMDGPU_PL_GWS ||
 677             old_mem->mem_type == AMDGPU_PL_OA ||
 678             new_mem->mem_type == AMDGPU_PL_GDS ||
 679             new_mem->mem_type == AMDGPU_PL_GWS ||
 680             new_mem->mem_type == AMDGPU_PL_OA) {
 681                 /* Nothing to save here */
 682                 ttm_bo_move_null(bo, new_mem);
 683                 return 0;
 684         }
 685
 686         if (!adev->mman.buffer_funcs_enabled) {
 687                 r = -ENODEV;
 688                 goto memcpy;
 689         }
 690
 691         if (old_mem->mem_type == TTM_PL_VRAM &&
 692             new_mem->mem_type == TTM_PL_SYSTEM) {
 693                 r = amdgpu_move_vram_ram(bo, evict, ctx, new_mem);
 694         } else if (old_mem->mem_type == TTM_PL_SYSTEM &&
 695                    new_mem->mem_type == TTM_PL_VRAM) {
 696                 r = amdgpu_move_ram_vram(bo, evict, ctx, new_mem);
 697         } else {
 698                 r = amdgpu_move_blit(bo, evict,
 699                                      new_mem, old_mem);
 700         }
 701
 702         if (r) {
 703 memcpy:
 704                 /* Check that all memory is CPU accessible */
 705                 if (!amdgpu_mem_visible(adev, old_mem) ||
 706                     !amdgpu_mem_visible(adev, new_mem)) {
 707                         pr_err("Move buffer fallback to memcpy unavailable\n");
 708                         return r;
 709                 }
 710
 711                 r = ttm_bo_move_memcpy(bo, ctx, new_mem);
 712                 if (r)
 713                         return r;
 714         }
 715
 716         if (bo->type == ttm_bo_type_device &&
 717             new_mem->mem_type == TTM_PL_VRAM &&
 718             old_mem->mem_type != TTM_PL_VRAM) {
 719                 /* amdgpu_bo_fault_reserve_notify will re-set this if the CPU
 720                  * accesses the BO after it's moved.
 721                  */
 722                 abo->flags &= ~AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED;
 723         }
 724
 725         /* update statistics */
 726         atomic64_add((u64)bo->num_pages << PAGE_SHIFT, &adev->num_bytes_moved);
 727         return 0;
 728 }
 729
 730 /**
 731  * amdgpu_ttm_io_mem_reserve - Reserve a block of memory during a fault
 732  *
 733  * Called by ttm_mem_io_reserve() ultimately via ttm_bo_vm_fault()
 734  */
 735 static int amdgpu_ttm_io_mem_reserve(struct ttm_bo_device *bdev, struct ttm_resource *mem)
 736 {
 737         struct amdgpu_device *adev = amdgpu_ttm_adev(bdev);
 738         struct drm_mm_node *mm_node = mem->mm_node;
 739         size_t bus_size = (size_t)mem->num_pages << PAGE_SHIFT;
 740
 741         switch (mem->mem_type) {
 742         case TTM_PL_SYSTEM:
 743                 /* system memory */
 744                 return 0;
 745         case TTM_PL_TT:
 746                 break;
 747         case TTM_PL_VRAM:
 748                 mem->bus.offset = mem->start << PAGE_SHIFT;
 749                 /* check if it's visible */
 750                 if ((mem->bus.offset + bus_size) > adev->gmc.visible_vram_size)
 751                         return -EINVAL;
 752                 /* Only physically contiguous buffers apply. In a contiguous
 753                  * buffer, size of the first mm_node would match the number of
 754                  * pages in ttm_resource.
 755                  */
 756                 if (adev->mman.aper_base_kaddr &&
 757                     (mm_node->size == mem->num_pages))
 758                         mem->bus.addr = (u8 *)adev->mman.aper_base_kaddr +
 759                                         mem->bus.offset;
 760
 761                 mem->bus.offset += adev->gmc.aper_base;
 762                 mem->bus.is_iomem = true;
 763                 break;
 764         default:
 765                 return -EINVAL;
 766         }
 767         return 0;
 768 }
 769
 770 static unsigned long amdgpu_ttm_io_mem_pfn(struct ttm_buffer_object *bo,
 771                                            unsigned long page_offset)
 772 {
 773         struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev);
 774         uint64_t offset = (page_offset << PAGE_SHIFT);
 775         struct drm_mm_node *mm;
 776
 777         mm = amdgpu_find_mm_node(&bo->mem, &offset);
 778         offset += adev->gmc.aper_base;
 779         return mm->start + (offset >> PAGE_SHIFT);
 780 }
 781
 782 /**
 783  * amdgpu_ttm_domain_start - Returns GPU start address
 784  * @adev: amdgpu device object
 785  * @type: type of the memory
 786  *
 787  * Returns:
 788  * GPU start address of a memory domain
 789  */
 790
 791 uint64_t amdgpu_ttm_domain_start(struct amdgpu_device *adev, uint32_t type)
 792 {
 793         switch (type) {
 794         case TTM_PL_TT:
 795                 return adev->gmc.gart_start;
 796         case TTM_PL_VRAM:
 797                 return adev->gmc.vram_start;
 798         }
 799
 800         return 0;
 801 }
 802
 803 /*
 804  * TTM backend functions.
 805  */
 806 struct amdgpu_ttm_tt {
 807         struct ttm_dma_tt       ttm;
 808         struct drm_gem_object   *gobj;
 809         u64                     offset;
 810         uint64_t                userptr;
 811         struct task_struct      *usertask;
 812         uint32_t                userflags;
 813 #if IS_ENABLED(CONFIG_DRM_AMDGPU_USERPTR)
 814         struct hmm_range        *range;
 815 #endif
 816 };
 817
 818 #ifdef CONFIG_DRM_AMDGPU_USERPTR
 819 /**
 820  * amdgpu_ttm_tt_get_user_pages - get device accessible pages that back user
 821  * memory and start HMM tracking CPU page table update
 822  *
 823  * Calling function must call amdgpu_ttm_tt_userptr_range_done() once and only
 824  * once afterwards to stop HMM tracking
 825  */
 826 int amdgpu_ttm_tt_get_user_pages(struct amdgpu_bo *bo, struct page **pages)
 827 {
 828         struct ttm_tt *ttm = bo->tbo.ttm;
 829         struct amdgpu_ttm_tt *gtt = (void *)ttm;
 830         unsigned long start = gtt->userptr;
 831         struct vm_area_struct *vma;
 832         struct hmm_range *range;
 833         unsigned long timeout;
 834         struct mm_struct *mm;
 835         unsigned long i;
 836         int r = 0;
 837
 838         mm = bo->notifier.mm;
 839         if (unlikely(!mm)) {
 840                 DRM_DEBUG_DRIVER("BO is not registered?\n");
 841                 return -EFAULT;
 842         }
 843
 844         /* Another get_user_pages is running at the same time?? */
 845         if (WARN_ON(gtt->range))
 846                 return -EFAULT;
 847
 848         if (!mmget_not_zero(mm)) /* Happens during process shutdown */
 849                 return -ESRCH;
 850
 851         range = kzalloc(sizeof(*range), GFP_KERNEL);
 852         if (unlikely(!range)) {
 853                 r = -ENOMEM;
 854                 goto out;
 855         }
 856         range->notifier = &bo->notifier;
 857         range->start = bo->notifier.interval_tree.start;
 858         range->end = bo->notifier.interval_tree.last + 1;
 859         range->default_flags = HMM_PFN_REQ_FAULT;
 860         if (!amdgpu_ttm_tt_is_readonly(ttm))
 861                 range->default_flags |= HMM_PFN_REQ_WRITE;
 862
 863         range->hmm_pfns = kvmalloc_array(ttm->num_pages,
 864                                          sizeof(*range->hmm_pfns), GFP_KERNEL);
 865         if (unlikely(!range->hmm_pfns)) {
 866                 r = -ENOMEM;
 867                 goto out_free_ranges;
 868         }
 869
 870         mmap_read_lock(mm);
 871         vma = find_vma(mm, start);
 872         if (unlikely(!vma || start < vma->vm_start)) {
 873                 r = -EFAULT;
 874                 goto out_unlock;
 875         }
 876         if (unlikely((gtt->userflags & AMDGPU_GEM_USERPTR_ANONONLY) &&
 877                 vma->vm_file)) {
 878                 r = -EPERM;
 879                 goto out_unlock;
 880         }
 881         mmap_read_unlock(mm);
 882         timeout = jiffies + msecs_to_jiffies(HMM_RANGE_DEFAULT_TIMEOUT);
 883
 884 retry:
 885         range->notifier_seq = mmu_interval_read_begin(&bo->notifier);
 886
 887         mmap_read_lock(mm);
 888         r = hmm_range_fault(range);
 889         mmap_read_unlock(mm);
 890         if (unlikely(r)) {
 891                 /*
 892                  * FIXME: This timeout should encompass the retry from
 893                  * mmu_interval_read_retry() as well.
 894                  */
 895                 if (r == -EBUSY && !time_after(jiffies, timeout))
 896                         goto retry;
 897                 goto out_free_pfns;
 898         }
 899
 900         /*
 901          * Due to default_flags, all pages are HMM_PFN_VALID or
 902          * hmm_range_fault() fails. FIXME: The pages cannot be touched outside
 903          * the notifier_lock, and mmu_interval_read_retry() must be done first.
 904          */
 905         for (i = 0; i < ttm->num_pages; i++)
 906                 pages[i] = hmm_pfn_to_page(range->hmm_pfns[i]);
 907
 908         gtt->range = range;
 909         mmput(mm);
 910
 911         return 0;
 912
 913 out_unlock:
 914         mmap_read_unlock(mm);
 915 out_free_pfns:
 916         kvfree(range->hmm_pfns);
 917 out_free_ranges:
 918         kfree(range);
 919 out:
 920         mmput(mm);
 921         return r;
 922 }
 923
 924 /**
 925  * amdgpu_ttm_tt_userptr_range_done - stop HMM track the CPU page table change
 926  * Check if the pages backing this ttm range have been invalidated
 927  *
 928  * Returns: true if pages are still valid
 929  */
 930 bool amdgpu_ttm_tt_get_user_pages_done(struct ttm_tt *ttm)
 931 {
 932         struct amdgpu_ttm_tt *gtt = (void *)ttm;
 933         bool r = false;
 934
 935         if (!gtt || !gtt->userptr)
 936                 return false;
 937
 938         DRM_DEBUG_DRIVER("user_pages_done 0x%llx pages 0x%lx\n",
 939                 gtt->userptr, ttm->num_pages);
 940
 941         WARN_ONCE(!gtt->range || !gtt->range->hmm_pfns,
 942                 "No user pages to check\n");
 943
 944         if (gtt->range) {
 945                 /*
 946                  * FIXME: Must always hold notifier_lock for this, and must
 947                  * not ignore the return code.
 948                  */
 949                 r = mmu_interval_read_retry(gtt->range->notifier,
 950                                          gtt->range->notifier_seq);
 951                 kvfree(gtt->range->hmm_pfns);
 952                 kfree(gtt->range);
 953                 gtt->range = NULL;
 954         }
 955
 956         return !r;
 957 }
 958 #endif
 959
 960 /**
 961  * amdgpu_ttm_tt_set_user_pages - Copy pages in, putting old pages as necessary.
 962  *
 963  * Called by amdgpu_cs_list_validate(). This creates the page list
 964  * that backs user memory and will ultimately be mapped into the device
 965  * address space.
 966  */
 967 void amdgpu_ttm_tt_set_user_pages(struct ttm_tt *ttm, struct page **pages)
 968 {
 969         unsigned long i;
 970
 971         for (i = 0; i < ttm->num_pages; ++i)
 972                 ttm->pages[i] = pages ? pages[i] : NULL;
 973 }
 974
 975 /**
 976  * amdgpu_ttm_tt_pin_userptr -  prepare the sg table with the user pages
 977  *
 978  * Called by amdgpu_ttm_backend_bind()
 979  **/
 980 static int amdgpu_ttm_tt_pin_userptr(struct ttm_bo_device *bdev,
 981                                      struct ttm_tt *ttm)
 982 {
 983         struct amdgpu_device *adev = amdgpu_ttm_adev(bdev);
 984         struct amdgpu_ttm_tt *gtt = (void *)ttm;
 985         int r;
 986
 987         int write = !(gtt->userflags & AMDGPU_GEM_USERPTR_READONLY);
 988         enum dma_data_direction direction = write ?
 989                 DMA_BIDIRECTIONAL : DMA_TO_DEVICE;
 990
 991         /* Allocate an SG array and squash pages into it */
 992         r = sg_alloc_table_from_pages(ttm->sg, ttm->pages, ttm->num_pages, 0,
 993                                       ttm->num_pages << PAGE_SHIFT,
 994                                       GFP_KERNEL);
 995         if (r)
 996                 goto release_sg;
 997
 998         /* Map SG to device */
 999         r = dma_map_sgtable(adev->dev, ttm->sg, direction, 0);
1000         if (r)
1001                 goto release_sg;
1002
1003         /* convert SG to linear array of pages and dma addresses */
1004         drm_prime_sg_to_page_addr_arrays(ttm->sg, ttm->pages,
1005                                          gtt->ttm.dma_address, ttm->num_pages);
1006
1007         return 0;
1008
1009 release_sg:
1010         kfree(ttm->sg);
1011         return r;
1012 }
1013
1014 /**
1015  * amdgpu_ttm_tt_unpin_userptr - Unpin and unmap userptr pages
1016  */
1017 static void amdgpu_ttm_tt_unpin_userptr(struct ttm_bo_device *bdev,
1018                                         struct ttm_tt *ttm)
1019 {
1020         struct amdgpu_device *adev = amdgpu_ttm_adev(bdev);
1021         struct amdgpu_ttm_tt *gtt = (void *)ttm;
1022
1023         int write = !(gtt->userflags & AMDGPU_GEM_USERPTR_READONLY);
1024         enum dma_data_direction direction = write ?
1025                 DMA_BIDIRECTIONAL : DMA_TO_DEVICE;
1026
1027         /* double check that we don't free the table twice */
1028         if (!ttm->sg->sgl)
1029                 return;
1030
1031         /* unmap the pages mapped to the device */
1032         dma_unmap_sgtable(adev->dev, ttm->sg, direction, 0);
1033         sg_free_table(ttm->sg);
1034
1035 #if IS_ENABLED(CONFIG_DRM_AMDGPU_USERPTR)
1036         if (gtt->range) {
1037                 unsigned long i;
1038
1039                 for (i = 0; i < ttm->num_pages; i++) {
1040                         if (ttm->pages[i] !=
1041                             hmm_pfn_to_page(gtt->range->hmm_pfns[i]))
1042                                 break;
1043                 }
1044
1045                 WARN((i == ttm->num_pages), "Missing get_user_page_done\n");
1046         }
1047 #endif
1048 }
1049
1050 static int amdgpu_ttm_gart_bind(struct amdgpu_device *adev,
1051                                 struct ttm_buffer_object *tbo,
1052                                 uint64_t flags)
1053 {
1054         struct amdgpu_bo *abo = ttm_to_amdgpu_bo(tbo);
1055         struct ttm_tt *ttm = tbo->ttm;
1056         struct amdgpu_ttm_tt *gtt = (void *)ttm;
1057         int r;
1058
1059         if (amdgpu_bo_encrypted(abo))
1060                 flags |= AMDGPU_PTE_TMZ;
1061
1062         if (abo->flags & AMDGPU_GEM_CREATE_CP_MQD_GFX9) {
1063                 uint64_t page_idx = 1;
1064
1065                 r = amdgpu_gart_bind(adev, gtt->offset, page_idx,
1066                                 ttm->pages, gtt->ttm.dma_address, flags);
1067                 if (r)
1068                         goto gart_bind_fail;
1069
1070                 /* The memory type of the first page defaults to UC. Now
1071                  * modify the memory type to NC from the second page of
1072                  * the BO onward.
1073                  */
1074                 flags &= ~AMDGPU_PTE_MTYPE_VG10_MASK;
1075                 flags |= AMDGPU_PTE_MTYPE_VG10(AMDGPU_MTYPE_NC);
1076
1077                 r = amdgpu_gart_bind(adev,
1078                                 gtt->offset + (page_idx << PAGE_SHIFT),
1079                                 ttm->num_pages - page_idx,
1080                                 &ttm->pages[page_idx],
1081                                 &(gtt->ttm.dma_address[page_idx]), flags);
1082         } else {
1083                 r = amdgpu_gart_bind(adev, gtt->offset, ttm->num_pages,
1084                                      ttm->pages, gtt->ttm.dma_address, flags);
1085         }
1086
1087 gart_bind_fail:
1088         if (r)
1089                 DRM_ERROR("failed to bind %lu pages at 0x%08llX\n",
1090                           ttm->num_pages, gtt->offset);
1091
1092         return r;
1093 }
1094
1095 /**
1096  * amdgpu_ttm_backend_bind - Bind GTT memory
1097  *
1098  * Called by ttm_tt_bind() on behalf of ttm_bo_handle_move_mem().
1099  * This handles binding GTT memory to the device address space.
1100  */
1101 static int amdgpu_ttm_backend_bind(struct ttm_bo_device *bdev,
1102                                    struct ttm_tt *ttm,
1103                                    struct ttm_resource *bo_mem)
1104 {
1105         struct amdgpu_device *adev = amdgpu_ttm_adev(bdev);
1106         struct amdgpu_ttm_tt *gtt = (void*)ttm;
1107         uint64_t flags;
1108         int r = 0;
1109
1110         if (gtt->userptr) {
1111                 r = amdgpu_ttm_tt_pin_userptr(bdev, ttm);
1112                 if (r) {
1113                         DRM_ERROR("failed to pin userptr\n");
1114                         return r;
1115                 }
1116         }
1117         if (!ttm->num_pages) {
1118                 WARN(1, "nothing to bind %lu pages for mreg %p back %p!\n",
1119                      ttm->num_pages, bo_mem, ttm);
1120         }
1121
1122         if (bo_mem->mem_type == AMDGPU_PL_GDS ||
1123             bo_mem->mem_type == AMDGPU_PL_GWS ||
1124             bo_mem->mem_type == AMDGPU_PL_OA)
1125                 return -EINVAL;
1126
1127         if (!amdgpu_gtt_mgr_has_gart_addr(bo_mem)) {
1128                 gtt->offset = AMDGPU_BO_INVALID_OFFSET;
1129                 return 0;
1130         }
1131
1132         /* compute PTE flags relevant to this BO memory */
1133         flags = amdgpu_ttm_tt_pte_flags(adev, ttm, bo_mem);
1134
1135         /* bind pages into GART page tables */
1136         gtt->offset = (u64)bo_mem->start << PAGE_SHIFT;
1137         r = amdgpu_gart_bind(adev, gtt->offset, ttm->num_pages,
1138                 ttm->pages, gtt->ttm.dma_address, flags);
1139
1140         if (r)
1141                 DRM_ERROR("failed to bind %lu pages at 0x%08llX\n",
1142                           ttm->num_pages, gtt->offset);
1143         return r;
1144 }
1145
1146 /**
1147  * amdgpu_ttm_alloc_gart - Allocate GART memory for buffer object
1148  */
1149 int amdgpu_ttm_alloc_gart(struct ttm_buffer_object *bo)
1150 {
1151         struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev);
1152         struct ttm_operation_ctx ctx = { false, false };
1153         struct amdgpu_ttm_tt *gtt = (void*)bo->ttm;
1154         struct ttm_resource tmp;
1155         struct ttm_placement placement;
1156         struct ttm_place placements;
1157         uint64_t addr, flags;
1158         int r;
1159
1160         if (bo->mem.start != AMDGPU_BO_INVALID_OFFSET)
1161                 return 0;
1162
1163         addr = amdgpu_gmc_agp_addr(bo);
1164         if (addr != AMDGPU_BO_INVALID_OFFSET) {
1165                 bo->mem.start = addr >> PAGE_SHIFT;
1166         } else {
1167
1168                 /* allocate GART space */
1169                 tmp = bo->mem;
1170                 tmp.mm_node = NULL;
1171                 placement.num_placement = 1;
1172                 placement.placement = &placements;
1173                 placement.num_busy_placement = 1;
1174                 placement.busy_placement = &placements;
1175                 placements.fpfn = 0;
1176                 placements.lpfn = adev->gmc.gart_size >> PAGE_SHIFT;
1177                 placements.mem_type = TTM_PL_TT;
1178                 placements.flags = bo->mem.placement;
1179
1180                 r = ttm_bo_mem_space(bo, &placement, &tmp, &ctx);
1181                 if (unlikely(r))
1182                         return r;
1183
1184                 /* compute PTE flags for this buffer object */
1185                 flags = amdgpu_ttm_tt_pte_flags(adev, bo->ttm, &tmp);
1186
1187                 /* Bind pages */
1188                 gtt->offset = (u64)tmp.start << PAGE_SHIFT;
1189                 r = amdgpu_ttm_gart_bind(adev, bo, flags);
1190                 if (unlikely(r)) {
1191                         ttm_resource_free(bo, &tmp);
1192                         return r;
1193                 }
1194
1195                 ttm_resource_free(bo, &bo->mem);
1196                 bo->mem = tmp;
1197         }
1198
1199         return 0;
1200 }
1201
1202 /**
1203  * amdgpu_ttm_recover_gart - Rebind GTT pages
1204  *
1205  * Called by amdgpu_gtt_mgr_recover() from amdgpu_device_reset() to
1206  * rebind GTT pages during a GPU reset.
1207  */
1208 int amdgpu_ttm_recover_gart(struct ttm_buffer_object *tbo)
1209 {
1210         struct amdgpu_device *adev = amdgpu_ttm_adev(tbo->bdev);
1211         uint64_t flags;
1212         int r;
1213
1214         if (!tbo->ttm)
1215                 return 0;
1216
1217         flags = amdgpu_ttm_tt_pte_flags(adev, tbo->ttm, &tbo->mem);
1218         r = amdgpu_ttm_gart_bind(adev, tbo, flags);
1219
1220         return r;
1221 }
1222
1223 /**
1224  * amdgpu_ttm_backend_unbind - Unbind GTT mapped pages
1225  *
1226  * Called by ttm_tt_unbind() on behalf of ttm_bo_move_ttm() and
1227  * ttm_tt_destroy().
1228  */
1229 static void amdgpu_ttm_backend_unbind(struct ttm_bo_device *bdev,
1230                                       struct ttm_tt *ttm)
1231 {
1232         struct amdgpu_device *adev = amdgpu_ttm_adev(bdev);
1233         struct amdgpu_ttm_tt *gtt = (void *)ttm;
1234         int r;
1235
1236         /* if the pages have userptr pinning then clear that first */
1237         if (gtt->userptr)
1238                 amdgpu_ttm_tt_unpin_userptr(bdev, ttm);
1239
1240         if (gtt->offset == AMDGPU_BO_INVALID_OFFSET)
1241                 return;
1242
1243         /* unbind shouldn't be done for GDS/GWS/OA in ttm_bo_clean_mm */
1244         r = amdgpu_gart_unbind(adev, gtt->offset, ttm->num_pages);
1245         if (r)
1246                 DRM_ERROR("failed to unbind %lu pages at 0x%08llX\n",
1247                           gtt->ttm.ttm.num_pages, gtt->offset);
1248 }
1249
1250 static void amdgpu_ttm_backend_destroy(struct ttm_bo_device *bdev,
1251                                        struct ttm_tt *ttm)
1252 {
1253         struct amdgpu_ttm_tt *gtt = (void *)ttm;
1254
1255         if (gtt->usertask)
1256                 put_task_struct(gtt->usertask);
1257
1258         ttm_dma_tt_fini(&gtt->ttm);
1259         kfree(gtt);
1260 }
1261
1262 /**
1263  * amdgpu_ttm_tt_create - Create a ttm_tt object for a given BO
1264  *
1265  * @bo: The buffer object to create a GTT ttm_tt object around
1266  *
1267  * Called by ttm_tt_create().
1268  */
1269 static struct ttm_tt *amdgpu_ttm_tt_create(struct ttm_buffer_object *bo,
1270                                            uint32_t page_flags)
1271 {
1272         struct amdgpu_ttm_tt *gtt;
1273
1274         gtt = kzalloc(sizeof(struct amdgpu_ttm_tt), GFP_KERNEL);
1275         if (gtt == NULL) {
1276                 return NULL;
1277         }
1278         gtt->gobj = &bo->base;
1279
1280         /* allocate space for the uninitialized page entries */
1281         if (ttm_sg_tt_init(&gtt->ttm, bo, page_flags)) {
1282                 kfree(gtt);
1283                 return NULL;
1284         }
1285         return &gtt->ttm.ttm;
1286 }
1287
1288 /**
1289  * amdgpu_ttm_tt_populate - Map GTT pages visible to the device
1290  *
1291  * Map the pages of a ttm_tt object to an address space visible
1292  * to the underlying device.
1293  */
1294 static int amdgpu_ttm_tt_populate(struct ttm_bo_device *bdev,
1295                                   struct ttm_tt *ttm,
1296                                   struct ttm_operation_ctx *ctx)
1297 {
1298         struct amdgpu_device *adev = amdgpu_ttm_adev(bdev);
1299         struct amdgpu_ttm_tt *gtt = (void *)ttm;
1300
1301         /* user pages are bound by amdgpu_ttm_tt_pin_userptr() */
1302         if (gtt && gtt->userptr) {
1303                 ttm->sg = kzalloc(sizeof(struct sg_table), GFP_KERNEL);
1304                 if (!ttm->sg)
1305                         return -ENOMEM;
1306
1307                 ttm->page_flags |= TTM_PAGE_FLAG_SG;
1308                 ttm->state = tt_unbound;
1309                 return 0;
1310         }
1311
1312         if (ttm->page_flags & TTM_PAGE_FLAG_SG) {
1313                 if (!ttm->sg) {
1314                         struct dma_buf_attachment *attach;
1315                         struct sg_table *sgt;
1316
1317                         attach = gtt->gobj->import_attach;
1318                         sgt = dma_buf_map_attachment(attach, DMA_BIDIRECTIONAL);
1319                         if (IS_ERR(sgt))
1320                                 return PTR_ERR(sgt);
1321
1322                         ttm->sg = sgt;
1323                 }
1324
1325                 drm_prime_sg_to_page_addr_arrays(ttm->sg, ttm->pages,
1326                                                  gtt->ttm.dma_address,
1327                                                  ttm->num_pages);
1328                 ttm->state = tt_unbound;
1329                 return 0;
1330         }
1331
1332 #ifdef CONFIG_SWIOTLB
1333         if (adev->need_swiotlb && swiotlb_nr_tbl()) {
1334                 return ttm_dma_populate(&gtt->ttm, adev->dev, ctx);
1335         }
1336 #endif
1337
1338         /* fall back to generic helper to populate the page array
1339          * and map them to the device */
1340         return ttm_populate_and_map_pages(adev->dev, &gtt->ttm, ctx);
1341 }
1342
1343 /**
1344  * amdgpu_ttm_tt_unpopulate - unmap GTT pages and unpopulate page arrays
1345  *
1346  * Unmaps pages of a ttm_tt object from the device address space and
1347  * unpopulates the page array backing it.
1348  */
1349 static void amdgpu_ttm_tt_unpopulate(struct ttm_bo_device *bdev, struct ttm_tt *ttm)
1350 {
1351         struct amdgpu_ttm_tt *gtt = (void *)ttm;
1352         struct amdgpu_device *adev;
1353
1354         if (gtt && gtt->userptr) {
1355                 amdgpu_ttm_tt_set_user_pages(ttm, NULL);
1356                 kfree(ttm->sg);
1357                 ttm->page_flags &= ~TTM_PAGE_FLAG_SG;
1358                 return;
1359         }
1360
1361         if (ttm->sg && gtt->gobj->import_attach) {
1362                 struct dma_buf_attachment *attach;
1363
1364                 attach = gtt->gobj->import_attach;
1365                 dma_buf_unmap_attachment(attach, ttm->sg, DMA_BIDIRECTIONAL);
1366                 ttm->sg = NULL;
1367                 return;
1368         }
1369
1370         if (ttm->page_flags & TTM_PAGE_FLAG_SG)
1371                 return;
1372
1373         adev = amdgpu_ttm_adev(bdev);
1374
1375 #ifdef CONFIG_SWIOTLB
1376         if (adev->need_swiotlb && swiotlb_nr_tbl()) {
1377                 ttm_dma_unpopulate(&gtt->ttm, adev->dev);
1378                 return;
1379         }
1380 #endif
1381
1382         /* fall back to generic helper to unmap and unpopulate array */
1383         ttm_unmap_and_unpopulate_pages(adev->dev, &gtt->ttm);
1384 }
1385
1386 /**
1387  * amdgpu_ttm_tt_set_userptr - Initialize userptr GTT ttm_tt for the current
1388  * task
1389  *
1390  * @bo: The ttm_buffer_object to bind this userptr to
1391  * @addr:  The address in the current tasks VM space to use
1392  * @flags: Requirements of userptr object.
1393  *
1394  * Called by amdgpu_gem_userptr_ioctl() to bind userptr pages
1395  * to current task
1396  */
1397 int amdgpu_ttm_tt_set_userptr(struct ttm_buffer_object *bo,
1398                               uint64_t addr, uint32_t flags)
1399 {
1400         struct amdgpu_ttm_tt *gtt;
1401
1402         if (!bo->ttm) {
1403                 /* TODO: We want a separate TTM object type for userptrs */
1404                 bo->ttm = amdgpu_ttm_tt_create(bo, 0);
1405                 if (bo->ttm == NULL)
1406                         return -ENOMEM;
1407         }
1408
1409         gtt = (void*)bo->ttm;
1410         gtt->userptr = addr;
1411         gtt->userflags = flags;
1412
1413         if (gtt->usertask)
1414                 put_task_struct(gtt->usertask);
1415         gtt->usertask = current->group_leader;
1416         get_task_struct(gtt->usertask);
1417
1418         return 0;
1419 }
1420
1421 /**
1422  * amdgpu_ttm_tt_get_usermm - Return memory manager for ttm_tt object
1423  */
1424 struct mm_struct *amdgpu_ttm_tt_get_usermm(struct ttm_tt *ttm)
1425 {
1426         struct amdgpu_ttm_tt *gtt = (void *)ttm;
1427
1428         if (gtt == NULL)
1429                 return NULL;
1430
1431         if (gtt->usertask == NULL)
1432                 return NULL;
1433
1434         return gtt->usertask->mm;
1435 }
1436
1437 /**
1438  * amdgpu_ttm_tt_affect_userptr - Determine if a ttm_tt object lays inside an
1439  * address range for the current task.
1440  *
1441  */
1442 bool amdgpu_ttm_tt_affect_userptr(struct ttm_tt *ttm, unsigned long start,
1443                                   unsigned long end)
1444 {
1445         struct amdgpu_ttm_tt *gtt = (void *)ttm;
1446         unsigned long size;
1447
1448         if (gtt == NULL || !gtt->userptr)
1449                 return false;
1450
1451         /* Return false if no part of the ttm_tt object lies within
1452          * the range
1453          */
1454         size = (unsigned long)gtt->ttm.ttm.num_pages * PAGE_SIZE;
1455         if (gtt->userptr > end || gtt->userptr + size <= start)
1456                 return false;
1457
1458         return true;
1459 }
1460
1461 /**
1462  * amdgpu_ttm_tt_is_userptr - Have the pages backing by userptr?
1463  */
1464 bool amdgpu_ttm_tt_is_userptr(struct ttm_tt *ttm)
1465 {
1466         struct amdgpu_ttm_tt *gtt = (void *)ttm;
1467
1468         if (gtt == NULL || !gtt->userptr)
1469                 return false;
1470
1471         return true;
1472 }
1473
1474 /**
1475  * amdgpu_ttm_tt_is_readonly - Is the ttm_tt object read only?
1476  */
1477 bool amdgpu_ttm_tt_is_readonly(struct ttm_tt *ttm)
1478 {
1479         struct amdgpu_ttm_tt *gtt = (void *)ttm;
1480
1481         if (gtt == NULL)
1482                 return false;
1483
1484         return !!(gtt->userflags & AMDGPU_GEM_USERPTR_READONLY);
1485 }
1486
1487 /**
1488  * amdgpu_ttm_tt_pde_flags - Compute PDE flags for ttm_tt object
1489  *
1490  * @ttm: The ttm_tt object to compute the flags for
1491  * @mem: The memory registry backing this ttm_tt object
1492  *
1493  * Figure out the flags to use for a VM PDE (Page Directory Entry).
1494  */
1495 uint64_t amdgpu_ttm_tt_pde_flags(struct ttm_tt *ttm, struct ttm_resource *mem)
1496 {
1497         uint64_t flags = 0;
1498
1499         if (mem && mem->mem_type != TTM_PL_SYSTEM)
1500                 flags |= AMDGPU_PTE_VALID;
1501
1502         if (mem && mem->mem_type == TTM_PL_TT) {
1503                 flags |= AMDGPU_PTE_SYSTEM;
1504
1505                 if (ttm->caching_state == tt_cached)
1506                         flags |= AMDGPU_PTE_SNOOPED;
1507         }
1508
1509         return flags;
1510 }
1511
1512 /**
1513  * amdgpu_ttm_tt_pte_flags - Compute PTE flags for ttm_tt object
1514  *
1515  * @ttm: The ttm_tt object to compute the flags for
1516  * @mem: The memory registry backing this ttm_tt object
1517
1518  * Figure out the flags to use for a VM PTE (Page Table Entry).
1519  */
1520 uint64_t amdgpu_ttm_tt_pte_flags(struct amdgpu_device *adev, struct ttm_tt *ttm,
1521                                  struct ttm_resource *mem)
1522 {
1523         uint64_t flags = amdgpu_ttm_tt_pde_flags(ttm, mem);
1524
1525         flags |= adev->gart.gart_pte_flags;
1526         flags |= AMDGPU_PTE_READABLE;
1527
1528         if (!amdgpu_ttm_tt_is_readonly(ttm))
1529                 flags |= AMDGPU_PTE_WRITEABLE;
1530
1531         return flags;
1532 }
1533
1534 /**
1535  * amdgpu_ttm_bo_eviction_valuable - Check to see if we can evict a buffer
1536  * object.
1537  *
1538  * Return true if eviction is sensible. Called by ttm_mem_evict_first() on
1539  * behalf of ttm_bo_mem_force_space() which tries to evict buffer objects until
1540  * it can find space for a new object and by ttm_bo_force_list_clean() which is
1541  * used to clean out a memory space.
1542  */
1543 static bool amdgpu_ttm_bo_eviction_valuable(struct ttm_buffer_object *bo,
1544                                             const struct ttm_place *place)
1545 {
1546         unsigned long num_pages = bo->mem.num_pages;
1547         struct drm_mm_node *node = bo->mem.mm_node;
1548         struct dma_resv_list *flist;
1549         struct dma_fence *f;
1550         int i;
1551
1552         if (bo->type == ttm_bo_type_kernel &&
1553             !amdgpu_vm_evictable(ttm_to_amdgpu_bo(bo)))
1554                 return false;
1555
1556         /* If bo is a KFD BO, check if the bo belongs to the current process.
1557          * If true, then return false as any KFD process needs all its BOs to
1558          * be resident to run successfully
1559          */
1560         flist = dma_resv_get_list(bo->base.resv);
1561         if (flist) {
1562                 for (i = 0; i < flist->shared_count; ++i) {
1563                         f = rcu_dereference_protected(flist->shared[i],
1564                                 dma_resv_held(bo->base.resv));
1565                         if (amdkfd_fence_check_mm(f, current->mm))
1566                                 return false;
1567                 }
1568         }
1569
1570         switch (bo->mem.mem_type) {
1571         case TTM_PL_TT:
1572                 if (amdgpu_bo_is_amdgpu_bo(bo) &&
1573                     amdgpu_bo_encrypted(ttm_to_amdgpu_bo(bo)))
1574                         return false;
1575                 return true;
1576
1577         case TTM_PL_VRAM:
1578                 /* Check each drm MM node individually */
1579                 while (num_pages) {
1580                         if (place->fpfn < (node->start + node->size) &&
1581                             !(place->lpfn && place->lpfn <= node->start))
1582                                 return true;
1583
1584                         num_pages -= node->size;
1585                         ++node;
1586                 }
1587                 return false;
1588
1589         default:
1590                 break;
1591         }
1592
1593         return ttm_bo_eviction_valuable(bo, place);
1594 }
1595
1596 /**
1597  * amdgpu_ttm_access_memory - Read or Write memory that backs a buffer object.
1598  *
1599  * @bo:  The buffer object to read/write
1600  * @offset:  Offset into buffer object
1601  * @buf:  Secondary buffer to write/read from
1602  * @len: Length in bytes of access
1603  * @write:  true if writing
1604  *
1605  * This is used to access VRAM that backs a buffer object via MMIO
1606  * access for debugging purposes.
1607  */
1608 static int amdgpu_ttm_access_memory(struct ttm_buffer_object *bo,
1609                                     unsigned long offset,
1610                                     void *buf, int len, int write)
1611 {
1612         struct amdgpu_bo *abo = ttm_to_amdgpu_bo(bo);
1613         struct amdgpu_device *adev = amdgpu_ttm_adev(abo->tbo.bdev);
1614         struct drm_mm_node *nodes;
1615         uint32_t value = 0;
1616         int ret = 0;
1617         uint64_t pos;
1618         unsigned long flags;
1619
1620         if (bo->mem.mem_type != TTM_PL_VRAM)
1621                 return -EIO;
1622
1623         pos = offset;
1624         nodes = amdgpu_find_mm_node(&abo->tbo.mem, &pos);
1625         pos += (nodes->start << PAGE_SHIFT);
1626
1627         while (len && pos < adev->gmc.mc_vram_size) {
1628                 uint64_t aligned_pos = pos & ~(uint64_t)3;
1629                 uint64_t bytes = 4 - (pos & 3);
1630                 uint32_t shift = (pos & 3) * 8;
1631                 uint32_t mask = 0xffffffff << shift;
1632
1633                 if (len < bytes) {
1634                         mask &= 0xffffffff >> (bytes - len) * 8;
1635                         bytes = len;
1636                 }
1637
1638                 if (mask != 0xffffffff) {
1639                         spin_lock_irqsave(&adev->mmio_idx_lock, flags);
1640                         WREG32_NO_KIQ(mmMM_INDEX, ((uint32_t)aligned_pos) | 0x80000000);
1641                         WREG32_NO_KIQ(mmMM_INDEX_HI, aligned_pos >> 31);
1642                         if (!write || mask != 0xffffffff)
1643                                 value = RREG32_NO_KIQ(mmMM_DATA);
1644                         if (write) {
1645                                 value &= ~mask;
1646                                 value |= (*(uint32_t *)buf << shift) & mask;
1647                                 WREG32_NO_KIQ(mmMM_DATA, value);
1648                         }
1649                         spin_unlock_irqrestore(&adev->mmio_idx_lock, flags);
1650                         if (!write) {
1651                                 value = (value & mask) >> shift;
1652                                 memcpy(buf, &value, bytes);
1653                         }
1654                 } else {
1655                         bytes = (nodes->start + nodes->size) << PAGE_SHIFT;
1656                         bytes = min(bytes - pos, (uint64_t)len & ~0x3ull);
1657
1658                         amdgpu_device_vram_access(adev, pos, (uint32_t *)buf,
1659                                                   bytes, write);
1660                 }
1661
1662                 ret += bytes;
1663                 buf = (uint8_t *)buf + bytes;
1664                 pos += bytes;
1665                 len -= bytes;
1666                 if (pos >= (nodes->start + nodes->size) << PAGE_SHIFT) {
1667                         ++nodes;
1668                         pos = (nodes->start << PAGE_SHIFT);
1669                 }
1670         }
1671
1672         return ret;
1673 }
1674
1675 static struct ttm_bo_driver amdgpu_bo_driver = {
1676         .ttm_tt_create = &amdgpu_ttm_tt_create,
1677         .ttm_tt_populate = &amdgpu_ttm_tt_populate,
1678         .ttm_tt_unpopulate = &amdgpu_ttm_tt_unpopulate,
1679         .ttm_tt_bind = &amdgpu_ttm_backend_bind,
1680         .ttm_tt_unbind = &amdgpu_ttm_backend_unbind,
1681         .ttm_tt_destroy = &amdgpu_ttm_backend_destroy,
1682         .eviction_valuable = amdgpu_ttm_bo_eviction_valuable,
1683         .evict_flags = &amdgpu_evict_flags,
1684         .move = &amdgpu_bo_move,
1685         .verify_access = &amdgpu_verify_access,
1686         .move_notify = &amdgpu_bo_move_notify,
1687         .release_notify = &amdgpu_bo_release_notify,
1688         .fault_reserve_notify = &amdgpu_bo_fault_reserve_notify,
1689         .io_mem_reserve = &amdgpu_ttm_io_mem_reserve,
1690         .io_mem_pfn = amdgpu_ttm_io_mem_pfn,
1691         .access_memory = &amdgpu_ttm_access_memory,
1692         .del_from_lru_notify = &amdgpu_vm_del_from_lru_notify
1693 };
1694
1695 /*
1696  * Firmware Reservation functions
1697  */
1698 /**
1699  * amdgpu_ttm_fw_reserve_vram_fini - free fw reserved vram
1700  *
1701  * @adev: amdgpu_device pointer
1702  *
1703  * free fw reserved vram if it has been reserved.
1704  */
1705 static void amdgpu_ttm_fw_reserve_vram_fini(struct amdgpu_device *adev)
1706 {
1707         amdgpu_bo_free_kernel(&adev->mman.fw_vram_usage_reserved_bo,
1708                 NULL, &adev->mman.fw_vram_usage_va);
1709 }
1710
1711 /**
1712  * amdgpu_ttm_fw_reserve_vram_init - create bo vram reservation from fw
1713  *
1714  * @adev: amdgpu_device pointer
1715  *
1716  * create bo vram reservation from fw.
1717  */
1718 static int amdgpu_ttm_fw_reserve_vram_init(struct amdgpu_device *adev)
1719 {
1720         uint64_t vram_size = adev->gmc.visible_vram_size;
1721
1722         adev->mman.fw_vram_usage_va = NULL;
1723         adev->mman.fw_vram_usage_reserved_bo = NULL;
1724
1725         if (adev->mman.fw_vram_usage_size == 0 ||
1726             adev->mman.fw_vram_usage_size > vram_size)
1727                 return 0;
1728
1729         return amdgpu_bo_create_kernel_at(adev,
1730                                           adev->mman.fw_vram_usage_start_offset,
1731                                           adev->mman.fw_vram_usage_size,
1732                                           AMDGPU_GEM_DOMAIN_VRAM,
1733                                           &adev->mman.fw_vram_usage_reserved_bo,
1734                                           &adev->mman.fw_vram_usage_va);
1735 }
1736
1737 /*
1738  * Memoy training reservation functions
1739  */
1740
1741 /**
1742  * amdgpu_ttm_training_reserve_vram_fini - free memory training reserved vram
1743  *
1744  * @adev: amdgpu_device pointer
1745  *
1746  * free memory training reserved vram if it has been reserved.
1747  */
1748 static int amdgpu_ttm_training_reserve_vram_fini(struct amdgpu_device *adev)
1749 {
1750         struct psp_memory_training_context *ctx = &adev->psp.mem_train_ctx;
1751
1752         ctx->init = PSP_MEM_TRAIN_NOT_SUPPORT;
1753         amdgpu_bo_free_kernel(&ctx->c2p_bo, NULL, NULL);
1754         ctx->c2p_bo = NULL;
1755
1756         return 0;
1757 }
1758
1759 static void amdgpu_ttm_training_data_block_init(struct amdgpu_device *adev)
1760 {
1761         struct psp_memory_training_context *ctx = &adev->psp.mem_train_ctx;
1762
1763         memset(ctx, 0, sizeof(*ctx));
1764
1765         ctx->c2p_train_data_offset =
1766                 ALIGN((adev->gmc.mc_vram_size - adev->mman.discovery_tmr_size - SZ_1M), SZ_1M);
1767         ctx->p2c_train_data_offset =
1768                 (adev->gmc.mc_vram_size - GDDR6_MEM_TRAINING_OFFSET);
1769         ctx->train_data_size =
1770                 GDDR6_MEM_TRAINING_DATA_SIZE_IN_BYTES;
1771
1772         DRM_DEBUG("train_data_size:%llx,p2c_train_data_offset:%llx,c2p_train_data_offset:%llx.\n",
1773                         ctx->train_data_size,
1774                         ctx->p2c_train_data_offset,
1775                         ctx->c2p_train_data_offset);
1776 }
1777
1778 /*
1779  * reserve TMR memory at the top of VRAM which holds
1780  * IP Discovery data and is protected by PSP.
1781  */
1782 static int amdgpu_ttm_reserve_tmr(struct amdgpu_device *adev)
1783 {
1784         int ret;
1785         struct psp_memory_training_context *ctx = &adev->psp.mem_train_ctx;
1786         bool mem_train_support = false;
1787
1788         if (!amdgpu_sriov_vf(adev)) {
1789                 ret = amdgpu_mem_train_support(adev);
1790                 if (ret == 1)
1791                         mem_train_support = true;
1792                 else if (ret == -1)
1793                         return -EINVAL;
1794                 else
1795                         DRM_DEBUG("memory training does not support!\n");
1796         }
1797
1798         /*
1799          * Query reserved tmr size through atom firmwareinfo for Sienna_Cichlid and onwards for all
1800          * the use cases (IP discovery/G6 memory training/profiling/diagnostic data.etc)
1801          *
1802          * Otherwise, fallback to legacy approach to check and reserve tmr block for ip
1803          * discovery data and G6 memory training data respectively
1804          */
1805         adev->mman.discovery_tmr_size =
1806                 amdgpu_atomfirmware_get_fw_reserved_fb_size(adev);
1807         if (!adev->mman.discovery_tmr_size)
1808                 adev->mman.discovery_tmr_size = DISCOVERY_TMR_OFFSET;
1809
1810         if (mem_train_support) {
1811                 /* reserve vram for mem train according to TMR location */
1812                 amdgpu_ttm_training_data_block_init(adev);
1813                 ret = amdgpu_bo_create_kernel_at(adev,
1814                                          ctx->c2p_train_data_offset,
1815                                          ctx->train_data_size,
1816                                          AMDGPU_GEM_DOMAIN_VRAM,
1817                                          &ctx->c2p_bo,
1818                                          NULL);
1819                 if (ret) {
1820                         DRM_ERROR("alloc c2p_bo failed(%d)!\n", ret);
1821                         amdgpu_ttm_training_reserve_vram_fini(adev);
1822                         return ret;
1823                 }
1824                 ctx->init = PSP_MEM_TRAIN_RESERVE_SUCCESS;
1825         }
1826
1827         ret = amdgpu_bo_create_kernel_at(adev,
1828                                 adev->gmc.real_vram_size - adev->mman.discovery_tmr_size,
1829                                 adev->mman.discovery_tmr_size,
1830                                 AMDGPU_GEM_DOMAIN_VRAM,
1831                                 &adev->mman.discovery_memory,
1832                                 NULL);
1833         if (ret) {
1834                 DRM_ERROR("alloc tmr failed(%d)!\n", ret);
1835                 amdgpu_bo_free_kernel(&adev->mman.discovery_memory, NULL, NULL);
1836                 return ret;
1837         }
1838
1839         return 0;
1840 }
1841
1842 /**
1843  * amdgpu_ttm_init - Init the memory management (ttm) as well as various
1844  * gtt/vram related fields.
1845  *
1846  * This initializes all of the memory space pools that the TTM layer
1847  * will need such as the GTT space (system memory mapped to the device),
1848  * VRAM (on-board memory), and on-chip memories (GDS, GWS, OA) which
1849  * can be mapped per VMID.
1850  */
1851 int amdgpu_ttm_init(struct amdgpu_device *adev)
1852 {
1853         uint64_t gtt_size;
1854         int r;
1855         u64 vis_vram_limit;
1856
1857         mutex_init(&adev->mman.gtt_window_lock);
1858
1859         /* No others user of address space so set it to 0 */
1860         r = ttm_bo_device_init(&adev->mman.bdev,
1861                                &amdgpu_bo_driver,
1862                                adev_to_drm(adev)->anon_inode->i_mapping,
1863                                adev_to_drm(adev)->vma_offset_manager,
1864                                dma_addressing_limited(adev->dev));
1865         if (r) {
1866                 DRM_ERROR("failed initializing buffer object driver(%d).\n", r);
1867                 return r;
1868         }
1869         adev->mman.initialized = true;
1870
1871         /* We opt to avoid OOM on system pages allocations */
1872         adev->mman.bdev.no_retry = true;
1873
1874         /* Initialize VRAM pool with all of VRAM divided into pages */
1875         r = amdgpu_vram_mgr_init(adev);
1876         if (r) {
1877                 DRM_ERROR("Failed initializing VRAM heap.\n");
1878                 return r;
1879         }
1880
1881         /* Reduce size of CPU-visible VRAM if requested */
1882         vis_vram_limit = (u64)amdgpu_vis_vram_limit * 1024 * 1024;
1883         if (amdgpu_vis_vram_limit > 0 &&
1884             vis_vram_limit <= adev->gmc.visible_vram_size)
1885                 adev->gmc.visible_vram_size = vis_vram_limit;
1886
1887         /* Change the size here instead of the init above so only lpfn is affected */
1888         amdgpu_ttm_set_buffer_funcs_status(adev, false);
1889 #ifdef CONFIG_64BIT
1890         adev->mman.aper_base_kaddr = ioremap_wc(adev->gmc.aper_base,
1891                                                 adev->gmc.visible_vram_size);
1892 #endif
1893
1894         /*
1895          *The reserved vram for firmware must be pinned to the specified
1896          *place on the VRAM, so reserve it early.
1897          */
1898         r = amdgpu_ttm_fw_reserve_vram_init(adev);
1899         if (r) {
1900                 return r;
1901         }
1902
1903         /*
1904          * only NAVI10 and onwards ASIC support for IP discovery.
1905          * If IP discovery enabled, a block of memory should be
1906          * reserved for IP discovey.
1907          */
1908         if (adev->mman.discovery_bin) {
1909                 r = amdgpu_ttm_reserve_tmr(adev);
1910                 if (r)
1911                         return r;
1912         }
1913
1914         /* allocate memory as required for VGA
1915          * This is used for VGA emulation and pre-OS scanout buffers to
1916          * avoid display artifacts while transitioning between pre-OS
1917          * and driver.  */
1918         r = amdgpu_bo_create_kernel_at(adev, 0, adev->mman.stolen_vga_size,
1919                                        AMDGPU_GEM_DOMAIN_VRAM,
1920                                        &adev->mman.stolen_vga_memory,
1921                                        NULL);
1922         if (r)
1923                 return r;
1924         r = amdgpu_bo_create_kernel_at(adev, adev->mman.stolen_vga_size,
1925                                        adev->mman.stolen_extended_size,
1926                                        AMDGPU_GEM_DOMAIN_VRAM,
1927                                        &adev->mman.stolen_extended_memory,
1928                                        NULL);
1929         if (r)
1930                 return r;
1931
1932         DRM_INFO("amdgpu: %uM of VRAM memory ready\n",
1933                  (unsigned) (adev->gmc.real_vram_size / (1024 * 1024)));
1934
1935         /* Compute GTT size, either bsaed on 3/4th the size of RAM size
1936          * or whatever the user passed on module init */
1937         if (amdgpu_gtt_size == -1) {
1938                 struct sysinfo si;
1939
1940                 si_meminfo(&si);
1941                 gtt_size = min(max((AMDGPU_DEFAULT_GTT_SIZE_MB << 20),
1942                                adev->gmc.mc_vram_size),
1943                                ((uint64_t)si.totalram * si.mem_unit * 3/4));
1944         }
1945         else
1946                 gtt_size = (uint64_t)amdgpu_gtt_size << 20;
1947
1948         /* Initialize GTT memory pool */
1949         r = amdgpu_gtt_mgr_init(adev, gtt_size);
1950         if (r) {
1951                 DRM_ERROR("Failed initializing GTT heap.\n");
1952                 return r;
1953         }
1954         DRM_INFO("amdgpu: %uM of GTT memory ready.\n",
1955                  (unsigned)(gtt_size / (1024 * 1024)));
1956
1957         /* Initialize various on-chip memory pools */
1958         r = amdgpu_ttm_init_on_chip(adev, AMDGPU_PL_GDS, adev->gds.gds_size);
1959         if (r) {
1960                 DRM_ERROR("Failed initializing GDS heap.\n");
1961                 return r;
1962         }
1963
1964         r = amdgpu_ttm_init_on_chip(adev, AMDGPU_PL_GWS, adev->gds.gws_size);
1965         if (r) {
1966                 DRM_ERROR("Failed initializing gws heap.\n");
1967                 return r;
1968         }
1969
1970         r = amdgpu_ttm_init_on_chip(adev, AMDGPU_PL_OA, adev->gds.oa_size);
1971         if (r) {
1972                 DRM_ERROR("Failed initializing oa heap.\n");
1973                 return r;
1974         }
1975
1976         return 0;
1977 }
1978
1979 /**
1980  * amdgpu_ttm_late_init - Handle any late initialization for amdgpu_ttm
1981  */
1982 void amdgpu_ttm_late_init(struct amdgpu_device *adev)
1983 {
1984         /* return the VGA stolen memory (if any) back to VRAM */
1985         if (!adev->mman.keep_stolen_vga_memory)
1986                 amdgpu_bo_free_kernel(&adev->mman.stolen_vga_memory, NULL, NULL);
1987         amdgpu_bo_free_kernel(&adev->mman.stolen_extended_memory, NULL, NULL);
1988 }
1989
1990 /**
1991  * amdgpu_ttm_fini - De-initialize the TTM memory pools
1992  */
1993 void amdgpu_ttm_fini(struct amdgpu_device *adev)
1994 {
1995         if (!adev->mman.initialized)
1996                 return;
1997
1998         amdgpu_ttm_training_reserve_vram_fini(adev);
1999         /* return the stolen vga memory back to VRAM */
2000         if (adev->mman.keep_stolen_vga_memory)
2001                 amdgpu_bo_free_kernel(&adev->mman.stolen_vga_memory, NULL, NULL);
2002         /* return the IP Discovery TMR memory back to VRAM */
2003         amdgpu_bo_free_kernel(&adev->mman.discovery_memory, NULL, NULL);
2004         amdgpu_ttm_fw_reserve_vram_fini(adev);
2005
2006         if (adev->mman.aper_base_kaddr)
2007                 iounmap(adev->mman.aper_base_kaddr);
2008         adev->mman.aper_base_kaddr = NULL;
2009
2010         amdgpu_vram_mgr_fini(adev);
2011         amdgpu_gtt_mgr_fini(adev);
2012         ttm_range_man_fini(&adev->mman.bdev, AMDGPU_PL_GDS);
2013         ttm_range_man_fini(&adev->mman.bdev, AMDGPU_PL_GWS);
2014         ttm_range_man_fini(&adev->mman.bdev, AMDGPU_PL_OA);
2015         ttm_bo_device_release(&adev->mman.bdev);
2016         adev->mman.initialized = false;
2017         DRM_INFO("amdgpu: ttm finalized\n");
2018 }
2019
2020 /**
2021  * amdgpu_ttm_set_buffer_funcs_status - enable/disable use of buffer functions
2022  *
2023  * @adev: amdgpu_device pointer
2024  * @enable: true when we can use buffer functions.
2025  *
2026  * Enable/disable use of buffer functions during suspend/resume. This should
2027  * only be called at bootup or when userspace isn't running.
2028  */
2029 void amdgpu_ttm_set_buffer_funcs_status(struct amdgpu_device *adev, bool enable)
2030 {
2031         struct ttm_resource_manager *man = ttm_manager_type(&adev->mman.bdev, TTM_PL_VRAM);
2032         uint64_t size;
2033         int r;
2034
2035         if (!adev->mman.initialized || amdgpu_in_reset(adev) ||
2036             adev->mman.buffer_funcs_enabled == enable)
2037                 return;
2038
2039         if (enable) {
2040                 struct amdgpu_ring *ring;
2041                 struct drm_gpu_scheduler *sched;
2042
2043                 ring = adev->mman.buffer_funcs_ring;
2044                 sched = &ring->sched;
2045                 r = drm_sched_entity_init(&adev->mman.entity,
2046                                           DRM_SCHED_PRIORITY_KERNEL, &sched,
2047                                           1, NULL);
2048                 if (r) {
2049                         DRM_ERROR("Failed setting up TTM BO move entity (%d)\n",
2050                                   r);
2051                         return;
2052                 }
2053         } else {
2054                 drm_sched_entity_destroy(&adev->mman.entity);
2055                 dma_fence_put(man->move);
2056                 man->move = NULL;
2057         }
2058
2059         /* this just adjusts TTM size idea, which sets lpfn to the correct value */
2060         if (enable)
2061                 size = adev->gmc.real_vram_size;
2062         else
2063                 size = adev->gmc.visible_vram_size;
2064         man->size = size >> PAGE_SHIFT;
2065         adev->mman.buffer_funcs_enabled = enable;
2066 }
2067
2068 int amdgpu_mmap(struct file *filp, struct vm_area_struct *vma)
2069 {
2070         struct drm_file *file_priv = filp->private_data;
2071         struct amdgpu_device *adev = drm_to_adev(file_priv->minor->dev);
2072
2073         if (adev == NULL)
2074                 return -EINVAL;
2075
2076         return ttm_bo_mmap(filp, vma, &adev->mman.bdev);
2077 }
2078
2079 int amdgpu_copy_buffer(struct amdgpu_ring *ring, uint64_t src_offset,
2080                        uint64_t dst_offset, uint32_t byte_count,
2081                        struct dma_resv *resv,
2082                        struct dma_fence **fence, bool direct_submit,
2083                        bool vm_needs_flush, bool tmz)
2084 {
2085         enum amdgpu_ib_pool_type pool = direct_submit ? AMDGPU_IB_POOL_DIRECT :
2086                 AMDGPU_IB_POOL_DELAYED;
2087         struct amdgpu_device *adev = ring->adev;
2088         struct amdgpu_job *job;
2089
2090         uint32_t max_bytes;
2091         unsigned num_loops, num_dw;
2092         unsigned i;
2093         int r;
2094
2095         if (direct_submit && !ring->sched.ready) {
2096                 DRM_ERROR("Trying to move memory with ring turned off.\n");
2097                 return -EINVAL;
2098         }
2099
2100         max_bytes = adev->mman.buffer_funcs->copy_max_bytes;
2101         num_loops = DIV_ROUND_UP(byte_count, max_bytes);
2102         num_dw = ALIGN(num_loops * adev->mman.buffer_funcs->copy_num_dw, 8);
2103
2104         r = amdgpu_job_alloc_with_ib(adev, num_dw * 4, pool, &job);
2105         if (r)
2106                 return r;
2107
2108         if (vm_needs_flush) {
2109                 job->vm_pd_addr = amdgpu_gmc_pd_addr(adev->gart.bo);
2110                 job->vm_needs_flush = true;
2111         }
2112         if (resv) {
2113                 r = amdgpu_sync_resv(adev, &job->sync, resv,
2114                                      AMDGPU_SYNC_ALWAYS,
2115                                      AMDGPU_FENCE_OWNER_UNDEFINED);
2116                 if (r) {
2117                         DRM_ERROR("sync failed (%d).\n", r);
2118                         goto error_free;
2119                 }
2120         }
2121
2122         for (i = 0; i < num_loops; i++) {
2123                 uint32_t cur_size_in_bytes = min(byte_count, max_bytes);
2124
2125                 amdgpu_emit_copy_buffer(adev, &job->ibs[0], src_offset,
2126                                         dst_offset, cur_size_in_bytes, tmz);
2127
2128                 src_offset += cur_size_in_bytes;
2129                 dst_offset += cur_size_in_bytes;
2130                 byte_count -= cur_size_in_bytes;
2131         }
2132
2133         amdgpu_ring_pad_ib(ring, &job->ibs[0]);
2134         WARN_ON(job->ibs[0].length_dw > num_dw);
2135         if (direct_submit)
2136                 r = amdgpu_job_submit_direct(job, ring, fence);
2137         else
2138                 r = amdgpu_job_submit(job, &adev->mman.entity,
2139                                       AMDGPU_FENCE_OWNER_UNDEFINED, fence);
2140         if (r)
2141                 goto error_free;
2142
2143         return r;
2144
2145 error_free:
2146         amdgpu_job_free(job);
2147         DRM_ERROR("Error scheduling IBs (%d)\n", r);
2148         return r;
2149 }
2150
2151 int amdgpu_fill_buffer(struct amdgpu_bo *bo,
2152                        uint32_t src_data,
2153                        struct dma_resv *resv,
2154                        struct dma_fence **fence)
2155 {
2156         struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
2157         uint32_t max_bytes = adev->mman.buffer_funcs->fill_max_bytes;
2158         struct amdgpu_ring *ring = adev->mman.buffer_funcs_ring;
2159
2160         struct drm_mm_node *mm_node;
2161         unsigned long num_pages;
2162         unsigned int num_loops, num_dw;
2163
2164         struct amdgpu_job *job;
2165         int r;
2166
2167         if (!adev->mman.buffer_funcs_enabled) {
2168                 DRM_ERROR("Trying to clear memory with ring turned off.\n");
2169                 return -EINVAL;
2170         }
2171
2172         if (bo->tbo.mem.mem_type == TTM_PL_TT) {
2173                 r = amdgpu_ttm_alloc_gart(&bo->tbo);
2174                 if (r)
2175                         return r;
2176         }
2177
2178         num_pages = bo->tbo.num_pages;
2179         mm_node = bo->tbo.mem.mm_node;
2180         num_loops = 0;
2181         while (num_pages) {
2182                 uint64_t byte_count = mm_node->size << PAGE_SHIFT;
2183
2184                 num_loops += DIV_ROUND_UP_ULL(byte_count, max_bytes);
2185                 num_pages -= mm_node->size;
2186                 ++mm_node;
2187         }
2188         num_dw = num_loops * adev->mman.buffer_funcs->fill_num_dw;
2189
2190         /* for IB padding */
2191         num_dw += 64;
2192
2193         r = amdgpu_job_alloc_with_ib(adev, num_dw * 4, AMDGPU_IB_POOL_DELAYED,
2194                                      &job);
2195         if (r)
2196                 return r;
2197
2198         if (resv) {
2199                 r = amdgpu_sync_resv(adev, &job->sync, resv,
2200                                      AMDGPU_SYNC_ALWAYS,
2201                                      AMDGPU_FENCE_OWNER_UNDEFINED);
2202                 if (r) {
2203                         DRM_ERROR("sync failed (%d).\n", r);
2204                         goto error_free;
2205                 }
2206         }
2207
2208         num_pages = bo->tbo.num_pages;
2209         mm_node = bo->tbo.mem.mm_node;
2210
2211         while (num_pages) {
2212                 uint64_t byte_count = mm_node->size << PAGE_SHIFT;
2213                 uint64_t dst_addr;
2214
2215                 dst_addr = amdgpu_mm_node_addr(&bo->tbo, mm_node, &bo->tbo.mem);
2216                 while (byte_count) {
2217                         uint32_t cur_size_in_bytes = min_t(uint64_t, byte_count,
2218                                                            max_bytes);
2219
2220                         amdgpu_emit_fill_buffer(adev, &job->ibs[0], src_data,
2221                                                 dst_addr, cur_size_in_bytes);
2222
2223                         dst_addr += cur_size_in_bytes;
2224                         byte_count -= cur_size_in_bytes;
2225                 }
2226
2227                 num_pages -= mm_node->size;
2228                 ++mm_node;
2229         }
2230
2231         amdgpu_ring_pad_ib(ring, &job->ibs[0]);
2232         WARN_ON(job->ibs[0].length_dw > num_dw);
2233         r = amdgpu_job_submit(job, &adev->mman.entity,
2234                               AMDGPU_FENCE_OWNER_UNDEFINED, fence);
2235         if (r)
2236                 goto error_free;
2237
2238         return 0;
2239
2240 error_free:
2241         amdgpu_job_free(job);
2242         return r;
2243 }
2244
2245 #if defined(CONFIG_DEBUG_FS)
2246
2247 static int amdgpu_mm_dump_table(struct seq_file *m, void *data)
2248 {
2249         struct drm_info_node *node = (struct drm_info_node *)m->private;
2250         unsigned ttm_pl = (uintptr_t)node->info_ent->data;
2251         struct drm_device *dev = node->minor->dev;
2252         struct amdgpu_device *adev = drm_to_adev(dev);
2253         struct ttm_resource_manager *man = ttm_manager_type(&adev->mman.bdev, ttm_pl);
2254         struct drm_printer p = drm_seq_file_printer(m);
2255
2256         man->func->debug(man, &p);
2257         return 0;
2258 }
2259
2260 static const struct drm_info_list amdgpu_ttm_debugfs_list[] = {
2261         {"amdgpu_vram_mm", amdgpu_mm_dump_table, 0, (void *)TTM_PL_VRAM},
2262         {"amdgpu_gtt_mm", amdgpu_mm_dump_table, 0, (void *)TTM_PL_TT},
2263         {"amdgpu_gds_mm", amdgpu_mm_dump_table, 0, (void *)AMDGPU_PL_GDS},
2264         {"amdgpu_gws_mm", amdgpu_mm_dump_table, 0, (void *)AMDGPU_PL_GWS},
2265         {"amdgpu_oa_mm", amdgpu_mm_dump_table, 0, (void *)AMDGPU_PL_OA},
2266         {"ttm_page_pool", ttm_page_alloc_debugfs, 0, NULL},
2267 #ifdef CONFIG_SWIOTLB
2268         {"ttm_dma_page_pool", ttm_dma_page_alloc_debugfs, 0, NULL}
2269 #endif
2270 };
2271
2272 /**
2273  * amdgpu_ttm_vram_read - Linear read access to VRAM
2274  *
2275  * Accesses VRAM via MMIO for debugging purposes.
2276  */
2277 static ssize_t amdgpu_ttm_vram_read(struct file *f, char __user *buf,
2278                                     size_t size, loff_t *pos)
2279 {
2280         struct amdgpu_device *adev = file_inode(f)->i_private;
2281         ssize_t result = 0;
2282
2283         if (size & 0x3 || *pos & 0x3)
2284                 return -EINVAL;
2285
2286         if (*pos >= adev->gmc.mc_vram_size)
2287                 return -ENXIO;
2288
2289         size = min(size, (size_t)(adev->gmc.mc_vram_size - *pos));
2290         while (size) {
2291                 size_t bytes = min(size, AMDGPU_TTM_VRAM_MAX_DW_READ * 4);
2292                 uint32_t value[AMDGPU_TTM_VRAM_MAX_DW_READ];
2293
2294                 amdgpu_device_vram_access(adev, *pos, value, bytes, false);
2295                 if (copy_to_user(buf, value, bytes))
2296                         return -EFAULT;
2297
2298                 result += bytes;
2299                 buf += bytes;
2300                 *pos += bytes;
2301                 size -= bytes;
2302         }
2303
2304         return result;
2305 }
2306
2307 /**
2308  * amdgpu_ttm_vram_write - Linear write access to VRAM
2309  *
2310  * Accesses VRAM via MMIO for debugging purposes.
2311  */
2312 static ssize_t amdgpu_ttm_vram_write(struct file *f, const char __user *buf,
2313                                     size_t size, loff_t *pos)
2314 {
2315         struct amdgpu_device *adev = file_inode(f)->i_private;
2316         ssize_t result = 0;
2317         int r;
2318
2319         if (size & 0x3 || *pos & 0x3)
2320                 return -EINVAL;
2321
2322         if (*pos >= adev->gmc.mc_vram_size)
2323                 return -ENXIO;
2324
2325         while (size) {
2326                 unsigned long flags;
2327                 uint32_t value;
2328
2329                 if (*pos >= adev->gmc.mc_vram_size)
2330                         return result;
2331
2332                 r = get_user(value, (uint32_t *)buf);
2333                 if (r)
2334                         return r;
2335
2336                 spin_lock_irqsave(&adev->mmio_idx_lock, flags);
2337                 WREG32_NO_KIQ(mmMM_INDEX, ((uint32_t)*pos) | 0x80000000);
2338                 WREG32_NO_KIQ(mmMM_INDEX_HI, *pos >> 31);
2339                 WREG32_NO_KIQ(mmMM_DATA, value);
2340                 spin_unlock_irqrestore(&adev->mmio_idx_lock, flags);
2341
2342                 result += 4;
2343                 buf += 4;
2344                 *pos += 4;
2345                 size -= 4;
2346         }
2347
2348         return result;
2349 }
2350
2351 static const struct file_operations amdgpu_ttm_vram_fops = {
2352         .owner = THIS_MODULE,
2353         .read = amdgpu_ttm_vram_read,
2354         .write = amdgpu_ttm_vram_write,
2355         .llseek = default_llseek,
2356 };
2357
2358 #ifdef CONFIG_DRM_AMDGPU_GART_DEBUGFS
2359
2360 /**
2361  * amdgpu_ttm_gtt_read - Linear read access to GTT memory
2362  */
2363 static ssize_t amdgpu_ttm_gtt_read(struct file *f, char __user *buf,
2364                                    size_t size, loff_t *pos)
2365 {
2366         struct amdgpu_device *adev = file_inode(f)->i_private;
2367         ssize_t result = 0;
2368         int r;
2369
2370         while (size) {
2371                 loff_t p = *pos / PAGE_SIZE;
2372                 unsigned off = *pos & ~PAGE_MASK;
2373                 size_t cur_size = min_t(size_t, size, PAGE_SIZE - off);
2374                 struct page *page;
2375                 void *ptr;
2376
2377                 if (p >= adev->gart.num_cpu_pages)
2378                         return result;
2379
2380                 page = adev->gart.pages[p];
2381                 if (page) {
2382                         ptr = kmap(page);
2383                         ptr += off;
2384
2385                         r = copy_to_user(buf, ptr, cur_size);
2386                         kunmap(adev->gart.pages[p]);
2387                 } else
2388                         r = clear_user(buf, cur_size);
2389
2390                 if (r)
2391                         return -EFAULT;
2392
2393                 result += cur_size;
2394                 buf += cur_size;
2395                 *pos += cur_size;
2396                 size -= cur_size;
2397         }
2398
2399         return result;
2400 }
2401
2402 static const struct file_operations amdgpu_ttm_gtt_fops = {
2403         .owner = THIS_MODULE,
2404         .read = amdgpu_ttm_gtt_read,
2405         .llseek = default_llseek
2406 };
2407
2408 #endif
2409
2410 /**
2411  * amdgpu_iomem_read - Virtual read access to GPU mapped memory
2412  *
2413  * This function is used to read memory that has been mapped to the
2414  * GPU and the known addresses are not physical addresses but instead
2415  * bus addresses (e.g., what you'd put in an IB or ring buffer).
2416  */
2417 static ssize_t amdgpu_iomem_read(struct file *f, char __user *buf,
2418                                  size_t size, loff_t *pos)
2419 {
2420         struct amdgpu_device *adev = file_inode(f)->i_private;
2421         struct iommu_domain *dom;
2422         ssize_t result = 0;
2423         int r;
2424
2425         /* retrieve the IOMMU domain if any for this device */
2426         dom = iommu_get_domain_for_dev(adev->dev);
2427
2428         while (size) {
2429                 phys_addr_t addr = *pos & PAGE_MASK;
2430                 loff_t off = *pos & ~PAGE_MASK;
2431                 size_t bytes = PAGE_SIZE - off;
2432                 unsigned long pfn;
2433                 struct page *p;
2434                 void *ptr;
2435
2436                 bytes = bytes < size ? bytes : size;
2437
2438                 /* Translate the bus address to a physical address.  If
2439                  * the domain is NULL it means there is no IOMMU active
2440                  * and the address translation is the identity
2441                  */
2442                 addr = dom ? iommu_iova_to_phys(dom, addr) : addr;
2443
2444                 pfn = addr >> PAGE_SHIFT;
2445                 if (!pfn_valid(pfn))
2446                         return -EPERM;
2447
2448                 p = pfn_to_page(pfn);
2449                 if (p->mapping != adev->mman.bdev.dev_mapping)
2450                         return -EPERM;
2451
2452                 ptr = kmap(p);
2453                 r = copy_to_user(buf, ptr + off, bytes);
2454                 kunmap(p);
2455                 if (r)
2456                         return -EFAULT;
2457
2458                 size -= bytes;
2459                 *pos += bytes;
2460                 result += bytes;
2461         }
2462
2463         return result;
2464 }
2465
2466 /**
2467  * amdgpu_iomem_write - Virtual write access to GPU mapped memory
2468  *
2469  * This function is used to write memory that has been mapped to the
2470  * GPU and the known addresses are not physical addresses but instead
2471  * bus addresses (e.g., what you'd put in an IB or ring buffer).
2472  */
2473 static ssize_t amdgpu_iomem_write(struct file *f, const char __user *buf,
2474                                  size_t size, loff_t *pos)
2475 {
2476         struct amdgpu_device *adev = file_inode(f)->i_private;
2477         struct iommu_domain *dom;
2478         ssize_t result = 0;
2479         int r;
2480
2481         dom = iommu_get_domain_for_dev(adev->dev);
2482
2483         while (size) {
2484                 phys_addr_t addr = *pos & PAGE_MASK;
2485                 loff_t off = *pos & ~PAGE_MASK;
2486                 size_t bytes = PAGE_SIZE - off;
2487                 unsigned long pfn;
2488                 struct page *p;
2489                 void *ptr;
2490
2491                 bytes = bytes < size ? bytes : size;
2492
2493                 addr = dom ? iommu_iova_to_phys(dom, addr) : addr;
2494
2495                 pfn = addr >> PAGE_SHIFT;
2496                 if (!pfn_valid(pfn))
2497                         return -EPERM;
2498
2499                 p = pfn_to_page(pfn);
2500                 if (p->mapping != adev->mman.bdev.dev_mapping)
2501                         return -EPERM;
2502
2503                 ptr = kmap(p);
2504                 r = copy_from_user(ptr + off, buf, bytes);
2505                 kunmap(p);
2506                 if (r)
2507                         return -EFAULT;
2508
2509                 size -= bytes;
2510                 *pos += bytes;
2511                 result += bytes;
2512         }
2513
2514         return result;
2515 }
2516
2517 static const struct file_operations amdgpu_ttm_iomem_fops = {
2518         .owner = THIS_MODULE,
2519         .read = amdgpu_iomem_read,
2520         .write = amdgpu_iomem_write,
2521         .llseek = default_llseek
2522 };
2523
2524 static const struct {
2525         char *name;
2526         const struct file_operations *fops;
2527         int domain;
2528 } ttm_debugfs_entries[] = {
2529         { "amdgpu_vram", &amdgpu_ttm_vram_fops, TTM_PL_VRAM },
2530 #ifdef CONFIG_DRM_AMDGPU_GART_DEBUGFS
2531         { "amdgpu_gtt", &amdgpu_ttm_gtt_fops, TTM_PL_TT },
2532 #endif
2533         { "amdgpu_iomem", &amdgpu_ttm_iomem_fops, TTM_PL_SYSTEM },
2534 };
2535
2536 #endif
2537
2538 int amdgpu_ttm_debugfs_init(struct amdgpu_device *adev)
2539 {
2540 #if defined(CONFIG_DEBUG_FS)
2541         unsigned count;
2542
2543         struct drm_minor *minor = adev_to_drm(adev)->primary;
2544         struct dentry *ent, *root = minor->debugfs_root;
2545
2546         for (count = 0; count < ARRAY_SIZE(ttm_debugfs_entries); count++) {
2547                 ent = debugfs_create_file(
2548                                 ttm_debugfs_entries[count].name,
2549                                 S_IFREG | S_IRUGO, root,
2550                                 adev,
2551                                 ttm_debugfs_entries[count].fops);
2552                 if (IS_ERR(ent))
2553                         return PTR_ERR(ent);
2554                 if (ttm_debugfs_entries[count].domain == TTM_PL_VRAM)
2555                         i_size_write(ent->d_inode, adev->gmc.mc_vram_size);
2556                 else if (ttm_debugfs_entries[count].domain == TTM_PL_TT)
2557                         i_size_write(ent->d_inode, adev->gmc.gart_size);
2558                 adev->mman.debugfs_entries[count] = ent;
2559         }
2560
2561         count = ARRAY_SIZE(amdgpu_ttm_debugfs_list);
2562
2563 #ifdef CONFIG_SWIOTLB
2564         if (!(adev->need_swiotlb && swiotlb_nr_tbl()))
2565                 --count;
2566 #endif
2567
2568         return amdgpu_debugfs_add_files(adev, amdgpu_ttm_debugfs_list, count);
2569 #else
2570         return 0;
2571 #endif
2572 }