2 * Copyright 2009 VMware, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
22 * Authors: Michel Dänzer
25 #include <drm/amdgpu_drm.h>
27 #include "amdgpu_uvd.h"
28 #include "amdgpu_vce.h"
30 /* Test BO GTT->VRAM and VRAM->GTT GPU copies across the whole GTT aperture */
31 static void amdgpu_do_test_moves(struct amdgpu_device *adev)
33 struct amdgpu_ring *ring = adev->mman.buffer_funcs_ring;
34 struct amdgpu_bo *vram_obj = NULL;
35 struct amdgpu_bo **gtt_obj = NULL;
36 uint64_t gtt_addr, vram_addr;
43 * (Total GTT - IB pool - writeback page - ring buffers) / test size
45 n = adev->mc.gtt_size - AMDGPU_IB_POOL_SIZE*64*1024;
46 for (i = 0; i < AMDGPU_MAX_RINGS; ++i)
48 n -= adev->rings[i]->ring_size;
50 n -= AMDGPU_GPU_PAGE_SIZE;
51 if (adev->irq.ih.ring_obj)
52 n -= adev->irq.ih.ring_size;
55 gtt_obj = kzalloc(n * sizeof(*gtt_obj), GFP_KERNEL);
57 DRM_ERROR("Failed to allocate %d pointers\n", n);
62 r = amdgpu_bo_create(adev, size, PAGE_SIZE, true, AMDGPU_GEM_DOMAIN_VRAM, 0,
65 DRM_ERROR("Failed to create VRAM object\n");
68 r = amdgpu_bo_reserve(vram_obj, false);
71 r = amdgpu_bo_pin(vram_obj, AMDGPU_GEM_DOMAIN_VRAM, &vram_addr);
73 DRM_ERROR("Failed to pin VRAM object\n");
76 for (i = 0; i < n; i++) {
77 void *gtt_map, *vram_map;
78 void **gtt_start, **gtt_end;
79 void **vram_start, **vram_end;
80 struct amdgpu_fence *fence = NULL;
82 r = amdgpu_bo_create(adev, size, PAGE_SIZE, true,
83 AMDGPU_GEM_DOMAIN_GTT, 0, NULL, gtt_obj + i);
85 DRM_ERROR("Failed to create GTT object %d\n", i);
89 r = amdgpu_bo_reserve(gtt_obj[i], false);
91 goto out_lclean_unref;
92 r = amdgpu_bo_pin(gtt_obj[i], AMDGPU_GEM_DOMAIN_GTT, >t_addr);
94 DRM_ERROR("Failed to pin GTT object %d\n", i);
95 goto out_lclean_unres;
98 r = amdgpu_bo_kmap(gtt_obj[i], >t_map);
100 DRM_ERROR("Failed to map GTT object %d\n", i);
101 goto out_lclean_unpin;
104 for (gtt_start = gtt_map, gtt_end = gtt_map + size;
107 *gtt_start = gtt_start;
109 amdgpu_bo_kunmap(gtt_obj[i]);
111 r = amdgpu_copy_buffer(ring, gtt_addr, vram_addr,
115 DRM_ERROR("Failed GTT->VRAM copy %d\n", i);
116 goto out_lclean_unpin;
119 r = fence_wait(&fence->base, false);
121 DRM_ERROR("Failed to wait for GTT->VRAM fence %d\n", i);
122 goto out_lclean_unpin;
125 amdgpu_fence_unref(&fence);
127 r = amdgpu_bo_kmap(vram_obj, &vram_map);
129 DRM_ERROR("Failed to map VRAM object after copy %d\n", i);
130 goto out_lclean_unpin;
133 for (gtt_start = gtt_map, gtt_end = gtt_map + size,
134 vram_start = vram_map, vram_end = vram_map + size;
135 vram_start < vram_end;
136 gtt_start++, vram_start++) {
137 if (*vram_start != gtt_start) {
138 DRM_ERROR("Incorrect GTT->VRAM copy %d: Got 0x%p, "
139 "expected 0x%p (GTT/VRAM offset "
140 "0x%16llx/0x%16llx)\n",
141 i, *vram_start, gtt_start,
143 (gtt_addr - adev->mc.gtt_start +
144 (void*)gtt_start - gtt_map),
146 (vram_addr - adev->mc.vram_start +
147 (void*)gtt_start - gtt_map));
148 amdgpu_bo_kunmap(vram_obj);
149 goto out_lclean_unpin;
151 *vram_start = vram_start;
154 amdgpu_bo_kunmap(vram_obj);
156 r = amdgpu_copy_buffer(ring, vram_addr, gtt_addr,
160 DRM_ERROR("Failed VRAM->GTT copy %d\n", i);
161 goto out_lclean_unpin;
164 r = fence_wait(&fence->base, false);
166 DRM_ERROR("Failed to wait for VRAM->GTT fence %d\n", i);
167 goto out_lclean_unpin;
170 amdgpu_fence_unref(&fence);
172 r = amdgpu_bo_kmap(gtt_obj[i], >t_map);
174 DRM_ERROR("Failed to map GTT object after copy %d\n", i);
175 goto out_lclean_unpin;
178 for (gtt_start = gtt_map, gtt_end = gtt_map + size,
179 vram_start = vram_map, vram_end = vram_map + size;
181 gtt_start++, vram_start++) {
182 if (*gtt_start != vram_start) {
183 DRM_ERROR("Incorrect VRAM->GTT copy %d: Got 0x%p, "
184 "expected 0x%p (VRAM/GTT offset "
185 "0x%16llx/0x%16llx)\n",
186 i, *gtt_start, vram_start,
188 (vram_addr - adev->mc.vram_start +
189 (void*)vram_start - vram_map),
191 (gtt_addr - adev->mc.gtt_start +
192 (void*)vram_start - vram_map));
193 amdgpu_bo_kunmap(gtt_obj[i]);
194 goto out_lclean_unpin;
198 amdgpu_bo_kunmap(gtt_obj[i]);
200 DRM_INFO("Tested GTT->VRAM and VRAM->GTT copy for GTT offset 0x%llx\n",
201 gtt_addr - adev->mc.gtt_start);
205 amdgpu_bo_unpin(gtt_obj[i]);
207 amdgpu_bo_unreserve(gtt_obj[i]);
209 amdgpu_bo_unref(>t_obj[i]);
211 for (--i; i >= 0; --i) {
212 amdgpu_bo_unpin(gtt_obj[i]);
213 amdgpu_bo_unreserve(gtt_obj[i]);
214 amdgpu_bo_unref(>t_obj[i]);
217 amdgpu_fence_unref(&fence);
221 amdgpu_bo_unpin(vram_obj);
223 amdgpu_bo_unreserve(vram_obj);
225 amdgpu_bo_unref(&vram_obj);
229 printk(KERN_WARNING "Error while testing BO move.\n");
233 void amdgpu_test_moves(struct amdgpu_device *adev)
235 if (adev->mman.buffer_funcs)
236 amdgpu_do_test_moves(adev);
239 static int amdgpu_test_create_and_emit_fence(struct amdgpu_device *adev,
240 struct amdgpu_ring *ring,
241 struct fence **fence)
243 uint32_t handle = ring->idx ^ 0xdeafbeef;
246 if (ring == &adev->uvd.ring) {
247 r = amdgpu_uvd_get_create_msg(ring, handle, NULL);
249 DRM_ERROR("Failed to get dummy create msg\n");
253 r = amdgpu_uvd_get_destroy_msg(ring, handle, fence);
255 DRM_ERROR("Failed to get dummy destroy msg\n");
259 } else if (ring == &adev->vce.ring[0] ||
260 ring == &adev->vce.ring[1]) {
261 r = amdgpu_vce_get_create_msg(ring, handle, NULL);
263 DRM_ERROR("Failed to get dummy create msg\n");
267 r = amdgpu_vce_get_destroy_msg(ring, handle, fence);
269 DRM_ERROR("Failed to get dummy destroy msg\n");
273 struct amdgpu_fence *a_fence = NULL;
274 r = amdgpu_ring_lock(ring, 64);
276 DRM_ERROR("Failed to lock ring A %d\n", ring->idx);
279 amdgpu_fence_emit(ring, AMDGPU_FENCE_OWNER_UNDEFINED, &a_fence);
280 amdgpu_ring_unlock_commit(ring);
281 *fence = &a_fence->base;
286 void amdgpu_test_ring_sync(struct amdgpu_device *adev,
287 struct amdgpu_ring *ringA,
288 struct amdgpu_ring *ringB)
290 struct fence *fence1 = NULL, *fence2 = NULL;
291 struct amdgpu_semaphore *semaphore = NULL;
294 r = amdgpu_semaphore_create(adev, &semaphore);
296 DRM_ERROR("Failed to create semaphore\n");
300 r = amdgpu_ring_lock(ringA, 64);
302 DRM_ERROR("Failed to lock ring A %d\n", ringA->idx);
305 amdgpu_semaphore_emit_wait(ringA, semaphore);
306 amdgpu_ring_unlock_commit(ringA);
308 r = amdgpu_test_create_and_emit_fence(adev, ringA, &fence1);
312 r = amdgpu_ring_lock(ringA, 64);
314 DRM_ERROR("Failed to lock ring A %d\n", ringA->idx);
317 amdgpu_semaphore_emit_wait(ringA, semaphore);
318 amdgpu_ring_unlock_commit(ringA);
320 r = amdgpu_test_create_and_emit_fence(adev, ringA, &fence2);
326 if (fence_is_signaled(fence1)) {
327 DRM_ERROR("Fence 1 signaled without waiting for semaphore.\n");
331 r = amdgpu_ring_lock(ringB, 64);
333 DRM_ERROR("Failed to lock ring B %p\n", ringB);
336 amdgpu_semaphore_emit_signal(ringB, semaphore);
337 amdgpu_ring_unlock_commit(ringB);
339 r = fence_wait(fence1, false);
341 DRM_ERROR("Failed to wait for sync fence 1\n");
347 if (fence_is_signaled(fence2)) {
348 DRM_ERROR("Fence 2 signaled without waiting for semaphore.\n");
352 r = amdgpu_ring_lock(ringB, 64);
354 DRM_ERROR("Failed to lock ring B %p\n", ringB);
357 amdgpu_semaphore_emit_signal(ringB, semaphore);
358 amdgpu_ring_unlock_commit(ringB);
360 r = fence_wait(fence2, false);
362 DRM_ERROR("Failed to wait for sync fence 1\n");
367 amdgpu_semaphore_free(adev, &semaphore, NULL);
376 printk(KERN_WARNING "Error while testing ring sync (%d).\n", r);
379 static void amdgpu_test_ring_sync2(struct amdgpu_device *adev,
380 struct amdgpu_ring *ringA,
381 struct amdgpu_ring *ringB,
382 struct amdgpu_ring *ringC)
384 struct fence *fenceA = NULL, *fenceB = NULL;
385 struct amdgpu_semaphore *semaphore = NULL;
389 r = amdgpu_semaphore_create(adev, &semaphore);
391 DRM_ERROR("Failed to create semaphore\n");
395 r = amdgpu_ring_lock(ringA, 64);
397 DRM_ERROR("Failed to lock ring A %d\n", ringA->idx);
400 amdgpu_semaphore_emit_wait(ringA, semaphore);
401 amdgpu_ring_unlock_commit(ringA);
403 r = amdgpu_test_create_and_emit_fence(adev, ringA, &fenceA);
407 r = amdgpu_ring_lock(ringB, 64);
409 DRM_ERROR("Failed to lock ring B %d\n", ringB->idx);
412 amdgpu_semaphore_emit_wait(ringB, semaphore);
413 amdgpu_ring_unlock_commit(ringB);
414 r = amdgpu_test_create_and_emit_fence(adev, ringB, &fenceB);
420 if (fence_is_signaled(fenceA)) {
421 DRM_ERROR("Fence A signaled without waiting for semaphore.\n");
424 if (fence_is_signaled(fenceB)) {
425 DRM_ERROR("Fence B signaled without waiting for semaphore.\n");
429 r = amdgpu_ring_lock(ringC, 64);
431 DRM_ERROR("Failed to lock ring B %p\n", ringC);
434 amdgpu_semaphore_emit_signal(ringC, semaphore);
435 amdgpu_ring_unlock_commit(ringC);
437 for (i = 0; i < 30; ++i) {
439 sigA = fence_is_signaled(fenceA);
440 sigB = fence_is_signaled(fenceB);
445 if (!sigA && !sigB) {
446 DRM_ERROR("Neither fence A nor B has been signaled\n");
448 } else if (sigA && sigB) {
449 DRM_ERROR("Both fence A and B has been signaled\n");
453 DRM_INFO("Fence %c was first signaled\n", sigA ? 'A' : 'B');
455 r = amdgpu_ring_lock(ringC, 64);
457 DRM_ERROR("Failed to lock ring B %p\n", ringC);
460 amdgpu_semaphore_emit_signal(ringC, semaphore);
461 amdgpu_ring_unlock_commit(ringC);
465 r = fence_wait(fenceA, false);
467 DRM_ERROR("Failed to wait for sync fence A\n");
470 r = fence_wait(fenceB, false);
472 DRM_ERROR("Failed to wait for sync fence B\n");
477 amdgpu_semaphore_free(adev, &semaphore, NULL);
486 printk(KERN_WARNING "Error while testing ring sync (%d).\n", r);
489 static bool amdgpu_test_sync_possible(struct amdgpu_ring *ringA,
490 struct amdgpu_ring *ringB)
492 if (ringA == &ringA->adev->vce.ring[0] &&
493 ringB == &ringB->adev->vce.ring[1])
499 void amdgpu_test_syncing(struct amdgpu_device *adev)
503 for (i = 1; i < AMDGPU_MAX_RINGS; ++i) {
504 struct amdgpu_ring *ringA = adev->rings[i];
505 if (!ringA || !ringA->ready)
508 for (j = 0; j < i; ++j) {
509 struct amdgpu_ring *ringB = adev->rings[j];
510 if (!ringB || !ringB->ready)
513 if (!amdgpu_test_sync_possible(ringA, ringB))
516 DRM_INFO("Testing syncing between rings %d and %d...\n", i, j);
517 amdgpu_test_ring_sync(adev, ringA, ringB);
519 DRM_INFO("Testing syncing between rings %d and %d...\n", j, i);
520 amdgpu_test_ring_sync(adev, ringB, ringA);
522 for (k = 0; k < j; ++k) {
523 struct amdgpu_ring *ringC = adev->rings[k];
524 if (!ringC || !ringC->ready)
527 if (!amdgpu_test_sync_possible(ringA, ringC))
530 if (!amdgpu_test_sync_possible(ringB, ringC))
533 DRM_INFO("Testing syncing between rings %d, %d and %d...\n", i, j, k);
534 amdgpu_test_ring_sync2(adev, ringA, ringB, ringC);
536 DRM_INFO("Testing syncing between rings %d, %d and %d...\n", i, k, j);
537 amdgpu_test_ring_sync2(adev, ringA, ringC, ringB);
539 DRM_INFO("Testing syncing between rings %d, %d and %d...\n", j, i, k);
540 amdgpu_test_ring_sync2(adev, ringB, ringA, ringC);
542 DRM_INFO("Testing syncing between rings %d, %d and %d...\n", j, k, i);
543 amdgpu_test_ring_sync2(adev, ringB, ringC, ringA);
545 DRM_INFO("Testing syncing between rings %d, %d and %d...\n", k, i, j);
546 amdgpu_test_ring_sync2(adev, ringC, ringA, ringB);
548 DRM_INFO("Testing syncing between rings %d, %d and %d...\n", k, j, i);
549 amdgpu_test_ring_sync2(adev, ringC, ringB, ringA);