2 * Copyright 2018 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
24 #ifndef __AMDGPU_SDMA_H__
25 #define __AMDGPU_SDMA_H__
27 /* max number of IP instances */
28 #define AMDGPU_MAX_SDMA_INSTANCES 8
30 enum amdgpu_sdma_irq {
31 AMDGPU_SDMA_IRQ_INSTANCE0 = 0,
32 AMDGPU_SDMA_IRQ_INSTANCE1,
33 AMDGPU_SDMA_IRQ_INSTANCE2,
34 AMDGPU_SDMA_IRQ_INSTANCE3,
35 AMDGPU_SDMA_IRQ_INSTANCE4,
36 AMDGPU_SDMA_IRQ_INSTANCE5,
37 AMDGPU_SDMA_IRQ_INSTANCE6,
38 AMDGPU_SDMA_IRQ_INSTANCE7,
42 struct amdgpu_sdma_instance {
44 const struct firmware *fw;
46 uint32_t feature_version;
48 struct amdgpu_ring ring;
49 struct amdgpu_ring page;
53 struct amdgpu_sdma_ras_funcs {
54 int (*query_ras_error_count)(struct amdgpu_device *adev,
55 uint32_t instance, void *ras_error_status);
59 struct amdgpu_sdma_instance instance[AMDGPU_MAX_SDMA_INSTANCES];
60 struct drm_gpu_scheduler *sdma_sched[AMDGPU_MAX_SDMA_INSTANCES];
61 uint32_t num_sdma_sched;
62 struct amdgpu_irq_src trap_irq;
63 struct amdgpu_irq_src illegal_inst_irq;
64 struct amdgpu_irq_src ecc_irq;
66 uint32_t srbm_soft_reset;
68 struct ras_common_if *ras_if;
69 const struct amdgpu_sdma_ras_funcs *funcs;
73 * Provided by hw blocks that can move/clear data. e.g., gfx or sdma
74 * But currently, we use sdma to move data.
76 struct amdgpu_buffer_funcs {
77 /* maximum bytes in a single operation */
78 uint32_t copy_max_bytes;
80 /* number of dw to reserve per operation */
83 /* used for buffer migration */
84 void (*emit_copy_buffer)(struct amdgpu_ib *ib,
85 /* src addr in bytes */
87 /* dst addr in bytes */
89 /* number of byte to transfer */
92 /* maximum bytes in a single operation */
93 uint32_t fill_max_bytes;
95 /* number of dw to reserve per operation */
98 /* used for buffer clearing */
99 void (*emit_fill_buffer)(struct amdgpu_ib *ib,
100 /* value to write to memory */
102 /* dst addr in bytes */
104 /* number of byte to fill */
105 uint32_t byte_count);
108 #define amdgpu_emit_copy_buffer(adev, ib, s, d, b) (adev)->mman.buffer_funcs->emit_copy_buffer((ib), (s), (d), (b))
109 #define amdgpu_emit_fill_buffer(adev, ib, s, d, b) (adev)->mman.buffer_funcs->emit_fill_buffer((ib), (s), (d), (b))
111 struct amdgpu_sdma_instance *
112 amdgpu_sdma_get_instance_from_ring(struct amdgpu_ring *ring);
113 int amdgpu_sdma_get_index_from_ring(struct amdgpu_ring *ring, uint32_t *index);
114 uint64_t amdgpu_sdma_get_csa_mc_addr(struct amdgpu_ring *ring, unsigned vmid);
115 int amdgpu_sdma_ras_late_init(struct amdgpu_device *adev,
117 void amdgpu_sdma_ras_fini(struct amdgpu_device *adev);
118 int amdgpu_sdma_process_ras_data_cb(struct amdgpu_device *adev,
120 struct amdgpu_iv_entry *entry);
121 int amdgpu_sdma_process_ecc_irq(struct amdgpu_device *adev,
122 struct amdgpu_irq_src *source,
123 struct amdgpu_iv_entry *entry);