drivers/gpu/drm/amd/amdgpu/amdgpu_rlc.h

   1 /*
   2  * Copyright 2014 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23
  24 #ifndef __AMDGPU_RLC_H__
  25 #define __AMDGPU_RLC_H__
  26
  27 #include "clearstate_defs.h"
  28
  29 /* firmware ID used in rlc toc */
  30 typedef enum _FIRMWARE_ID_ {
  31         FIRMWARE_ID_INVALID                                     = 0,
  32         FIRMWARE_ID_RLC_G_UCODE                                 = 1,
  33         FIRMWARE_ID_RLC_TOC                                     = 2,
  34         FIRMWARE_ID_RLCG_SCRATCH                                = 3,
  35         FIRMWARE_ID_RLC_SRM_ARAM                                = 4,
  36         FIRMWARE_ID_RLC_SRM_INDEX_ADDR                          = 5,
  37         FIRMWARE_ID_RLC_SRM_INDEX_DATA                          = 6,
  38         FIRMWARE_ID_RLC_P_UCODE                                 = 7,
  39         FIRMWARE_ID_RLC_V_UCODE                                 = 8,
  40         FIRMWARE_ID_RLX6_UCODE                                  = 9,
  41         FIRMWARE_ID_RLX6_DRAM_BOOT                              = 10,
  42         FIRMWARE_ID_GLOBAL_TAP_DELAYS                           = 11,
  43         FIRMWARE_ID_SE0_TAP_DELAYS                              = 12,
  44         FIRMWARE_ID_SE1_TAP_DELAYS                              = 13,
  45         FIRMWARE_ID_GLOBAL_SE0_SE1_SKEW_DELAYS                  = 14,
  46         FIRMWARE_ID_SDMA0_UCODE                                 = 15,
  47         FIRMWARE_ID_SDMA0_JT                                    = 16,
  48         FIRMWARE_ID_SDMA1_UCODE                                 = 17,
  49         FIRMWARE_ID_SDMA1_JT                                    = 18,
  50         FIRMWARE_ID_CP_CE                                       = 19,
  51         FIRMWARE_ID_CP_PFP                                      = 20,
  52         FIRMWARE_ID_CP_ME                                       = 21,
  53         FIRMWARE_ID_CP_MEC                                      = 22,
  54         FIRMWARE_ID_CP_MES                                      = 23,
  55         FIRMWARE_ID_MES_STACK                                   = 24,
  56         FIRMWARE_ID_RLC_SRM_DRAM_SR                             = 25,
  57         FIRMWARE_ID_RLCG_SCRATCH_SR                             = 26,
  58         FIRMWARE_ID_RLCP_SCRATCH_SR                             = 27,
  59         FIRMWARE_ID_RLCV_SCRATCH_SR                             = 28,
  60         FIRMWARE_ID_RLX6_DRAM_SR                                = 29,
  61         FIRMWARE_ID_SDMA0_PG_CONTEXT                            = 30,
  62         FIRMWARE_ID_SDMA1_PG_CONTEXT                            = 31,
  63         FIRMWARE_ID_GLOBAL_MUX_SELECT_RAM                       = 32,
  64         FIRMWARE_ID_SE0_MUX_SELECT_RAM                          = 33,
  65         FIRMWARE_ID_SE1_MUX_SELECT_RAM                          = 34,
  66         FIRMWARE_ID_ACCUM_CTRL_RAM                              = 35,
  67         FIRMWARE_ID_RLCP_CAM                                    = 36,
  68         FIRMWARE_ID_RLC_SPP_CAM_EXT                             = 37,
  69         FIRMWARE_ID_MAX                                         = 38,
  70 } FIRMWARE_ID;
  71
  72 typedef enum _SOC21_FIRMWARE_ID_ {
  73     SOC21_FIRMWARE_ID_INVALID                     = 0,
  74     SOC21_FIRMWARE_ID_RLC_G_UCODE                 = 1,
  75     SOC21_FIRMWARE_ID_RLC_TOC                     = 2,
  76     SOC21_FIRMWARE_ID_RLCG_SCRATCH                = 3,
  77     SOC21_FIRMWARE_ID_RLC_SRM_ARAM                = 4,
  78     SOC21_FIRMWARE_ID_RLC_P_UCODE                 = 5,
  79     SOC21_FIRMWARE_ID_RLC_V_UCODE                 = 6,
  80     SOC21_FIRMWARE_ID_RLX6_UCODE                  = 7,
  81     SOC21_FIRMWARE_ID_RLX6_UCODE_CORE1            = 8,
  82     SOC21_FIRMWARE_ID_RLX6_DRAM_BOOT              = 9,
  83     SOC21_FIRMWARE_ID_RLX6_DRAM_BOOT_CORE1        = 10,
  84     SOC21_FIRMWARE_ID_SDMA_UCODE_TH0              = 11,
  85     SOC21_FIRMWARE_ID_SDMA_UCODE_TH1              = 12,
  86     SOC21_FIRMWARE_ID_CP_PFP                      = 13,
  87     SOC21_FIRMWARE_ID_CP_ME                       = 14,
  88     SOC21_FIRMWARE_ID_CP_MEC                      = 15,
  89     SOC21_FIRMWARE_ID_RS64_MES_P0                 = 16,
  90     SOC21_FIRMWARE_ID_RS64_MES_P1                 = 17,
  91     SOC21_FIRMWARE_ID_RS64_PFP                    = 18,
  92     SOC21_FIRMWARE_ID_RS64_ME                     = 19,
  93     SOC21_FIRMWARE_ID_RS64_MEC                    = 20,
  94     SOC21_FIRMWARE_ID_RS64_MES_P0_STACK           = 21,
  95     SOC21_FIRMWARE_ID_RS64_MES_P1_STACK           = 22,
  96     SOC21_FIRMWARE_ID_RS64_PFP_P0_STACK           = 23,
  97     SOC21_FIRMWARE_ID_RS64_PFP_P1_STACK           = 24,
  98     SOC21_FIRMWARE_ID_RS64_ME_P0_STACK            = 25,
  99     SOC21_FIRMWARE_ID_RS64_ME_P1_STACK            = 26,
 100     SOC21_FIRMWARE_ID_RS64_MEC_P0_STACK           = 27,
 101     SOC21_FIRMWARE_ID_RS64_MEC_P1_STACK           = 28,
 102     SOC21_FIRMWARE_ID_RS64_MEC_P2_STACK           = 29,
 103     SOC21_FIRMWARE_ID_RS64_MEC_P3_STACK           = 30,
 104     SOC21_FIRMWARE_ID_RLC_SRM_DRAM_SR             = 31,
 105     SOC21_FIRMWARE_ID_RLCG_SCRATCH_SR             = 32,
 106     SOC21_FIRMWARE_ID_RLCP_SCRATCH_SR             = 33,
 107     SOC21_FIRMWARE_ID_RLCV_SCRATCH_SR             = 34,
 108     SOC21_FIRMWARE_ID_RLX6_DRAM_SR                = 35,
 109     SOC21_FIRMWARE_ID_RLX6_DRAM_SR_CORE1          = 36,
 110     SOC21_FIRMWARE_ID_MAX                         = 37
 111 } SOC21_FIRMWARE_ID;
 112
 113 typedef struct _RLC_TABLE_OF_CONTENT {
 114         union {
 115                 unsigned int    DW0;
 116                 struct {
 117                         unsigned int    offset          : 25;
 118                         unsigned int    id              : 7;
 119                 };
 120         };
 121
 122         union {
 123                 unsigned int    DW1;
 124                 struct {
 125                         unsigned int    load_at_boot            : 1;
 126                         unsigned int    load_at_vddgfx          : 1;
 127                         unsigned int    load_at_reset           : 1;
 128                         unsigned int    memory_destination      : 2;
 129                         unsigned int    vfflr_image_code        : 4;
 130                         unsigned int    load_mode_direct        : 1;
 131                         unsigned int    save_for_vddgfx         : 1;
 132                         unsigned int    save_for_vfflr          : 1;
 133                         unsigned int    reserved                : 1;
 134                         unsigned int    signed_source           : 1;
 135                         unsigned int    size                    : 18;
 136                 };
 137         };
 138
 139         union {
 140                 unsigned int    DW2;
 141                 struct {
 142                         unsigned int    indirect_addr_reg       : 16;
 143                         unsigned int    index                   : 16;
 144                 };
 145         };
 146
 147         union {
 148                 unsigned int    DW3;
 149                 struct {
 150                         unsigned int    indirect_data_reg       : 16;
 151                         unsigned int    indirect_start_offset   : 16;
 152                 };
 153         };
 154 } RLC_TABLE_OF_CONTENT;
 155
 156 #define RLC_TOC_MAX_SIZE                64
 157
 158 struct amdgpu_rlc_funcs {
 159         bool (*is_rlc_enabled)(struct amdgpu_device *adev);
 160         void (*set_safe_mode)(struct amdgpu_device *adev, int xcc_id);
 161         void (*unset_safe_mode)(struct amdgpu_device *adev, int xcc_id);
 162         int  (*init)(struct amdgpu_device *adev);
 163         u32  (*get_csb_size)(struct amdgpu_device *adev);
 164         void (*get_csb_buffer)(struct amdgpu_device *adev, volatile u32 *buffer);
 165         int  (*get_cp_table_num)(struct amdgpu_device *adev);
 166         int  (*resume)(struct amdgpu_device *adev);
 167         void (*stop)(struct amdgpu_device *adev);
 168         void (*reset)(struct amdgpu_device *adev);
 169         void (*start)(struct amdgpu_device *adev);
 170         void (*update_spm_vmid)(struct amdgpu_device *adev, unsigned vmid);
 171         bool (*is_rlcg_access_range)(struct amdgpu_device *adev, uint32_t reg);
 172 };
 173
 174 struct amdgpu_rlcg_reg_access_ctrl {
 175         uint32_t scratch_reg0;
 176         uint32_t scratch_reg1;
 177         uint32_t scratch_reg2;
 178         uint32_t scratch_reg3;
 179         uint32_t grbm_cntl;
 180         uint32_t grbm_idx;
 181         uint32_t spare_int;
 182 };
 183
 184 struct amdgpu_rlc {
 185         /* for power gating */
 186         struct amdgpu_bo        *save_restore_obj;
 187         uint64_t                save_restore_gpu_addr;
 188         volatile uint32_t       *sr_ptr;
 189         const u32               *reg_list;
 190         u32                     reg_list_size;
 191         /* for clear state */
 192         struct amdgpu_bo        *clear_state_obj;
 193         uint64_t                clear_state_gpu_addr;
 194         volatile uint32_t       *cs_ptr;
 195         const struct cs_section_def   *cs_data;
 196         u32                     clear_state_size;
 197         /* for cp tables */
 198         struct amdgpu_bo        *cp_table_obj;
 199         uint64_t                cp_table_gpu_addr;
 200         volatile uint32_t       *cp_table_ptr;
 201         u32                     cp_table_size;
 202
 203         /* safe mode for updating CG/PG state */
 204         bool in_safe_mode[8];
 205         const struct amdgpu_rlc_funcs *funcs;
 206
 207         /* for firmware data */
 208         u32 save_and_restore_offset;
 209         u32 clear_state_descriptor_offset;
 210         u32 avail_scratch_ram_locations;
 211         u32 reg_restore_list_size;
 212         u32 reg_list_format_start;
 213         u32 reg_list_format_separate_start;
 214         u32 starting_offsets_start;
 215         u32 reg_list_format_size_bytes;
 216         u32 reg_list_size_bytes;
 217         u32 reg_list_format_direct_reg_list_length;
 218         u32 save_restore_list_cntl_size_bytes;
 219         u32 save_restore_list_gpm_size_bytes;
 220         u32 save_restore_list_srm_size_bytes;
 221         u32 rlc_iram_ucode_size_bytes;
 222         u32 rlc_dram_ucode_size_bytes;
 223         u32 rlcp_ucode_size_bytes;
 224         u32 rlcv_ucode_size_bytes;
 225         u32 global_tap_delays_ucode_size_bytes;
 226         u32 se0_tap_delays_ucode_size_bytes;
 227         u32 se1_tap_delays_ucode_size_bytes;
 228         u32 se2_tap_delays_ucode_size_bytes;
 229         u32 se3_tap_delays_ucode_size_bytes;
 230
 231         u32 *register_list_format;
 232         u32 *register_restore;
 233         u8 *save_restore_list_cntl;
 234         u8 *save_restore_list_gpm;
 235         u8 *save_restore_list_srm;
 236         u8 *rlc_iram_ucode;
 237         u8 *rlc_dram_ucode;
 238         u8 *rlcp_ucode;
 239         u8 *rlcv_ucode;
 240         u8 *global_tap_delays_ucode;
 241         u8 *se0_tap_delays_ucode;
 242         u8 *se1_tap_delays_ucode;
 243         u8 *se2_tap_delays_ucode;
 244         u8 *se3_tap_delays_ucode;
 245
 246         bool is_rlc_v2_1;
 247
 248         /* for rlc autoload */
 249         struct amdgpu_bo        *rlc_autoload_bo;
 250         u64                     rlc_autoload_gpu_addr;
 251         void                    *rlc_autoload_ptr;
 252
 253         /* rlc toc buffer */
 254         struct amdgpu_bo        *rlc_toc_bo;
 255         uint64_t                rlc_toc_gpu_addr;
 256         void                    *rlc_toc_buf;
 257
 258         bool rlcg_reg_access_supported;
 259         /* registers for rlcg indirect reg access */
 260         struct amdgpu_rlcg_reg_access_ctrl reg_access_ctrl;
 261 };
 262
 263 void amdgpu_gfx_rlc_enter_safe_mode(struct amdgpu_device *adev, int xcc_id);
 264 void amdgpu_gfx_rlc_exit_safe_mode(struct amdgpu_device *adev, int xcc_id);
 265 int amdgpu_gfx_rlc_init_sr(struct amdgpu_device *adev, u32 dws);
 266 int amdgpu_gfx_rlc_init_csb(struct amdgpu_device *adev);
 267 int amdgpu_gfx_rlc_init_cpt(struct amdgpu_device *adev);
 268 void amdgpu_gfx_rlc_setup_cp_table(struct amdgpu_device *adev);
 269 void amdgpu_gfx_rlc_fini(struct amdgpu_device *adev);
 270 int amdgpu_gfx_rlc_init_microcode(struct amdgpu_device *adev,
 271                                   uint16_t version_major,
 272                                   uint16_t version_minor);
 273 #endif