2 * Copyright 2019 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
24 #include "amdgpu_ras_eeprom.h"
26 #include "amdgpu_ras.h"
27 #include <linux/bits.h>
30 #define EEPROM_I2C_TARGET_ADDR_VEGA20 0xA0
31 #define EEPROM_I2C_TARGET_ADDR_ARCTURUS 0xA8
32 #define EEPROM_I2C_TARGET_ADDR_ARCTURUS_D342 0xA0
35 * The 2 macros bellow represent the actual size in bytes that
36 * those entities occupy in the EEPROM memory.
37 * EEPROM_TABLE_RECORD_SIZE is different than sizeof(eeprom_table_record) which
38 * uses uint64 to store 6b fields such as retired_page.
40 #define EEPROM_TABLE_HEADER_SIZE 20
41 #define EEPROM_TABLE_RECORD_SIZE 24
43 #define EEPROM_ADDRESS_SIZE 0x2
45 /* Table hdr is 'AMDR' */
46 #define EEPROM_TABLE_HDR_VAL 0x414d4452
47 #define EEPROM_TABLE_VER 0x00010000
49 /* Assume 2 Mbit size */
50 #define EEPROM_SIZE_BYTES 256000
51 #define EEPROM_PAGE__SIZE_BYTES 256
52 #define EEPROM_HDR_START 0
53 #define EEPROM_RECORD_START (EEPROM_HDR_START + EEPROM_TABLE_HEADER_SIZE)
54 #define EEPROM_MAX_RECORD_NUM ((EEPROM_SIZE_BYTES - EEPROM_TABLE_HEADER_SIZE) / EEPROM_TABLE_RECORD_SIZE)
55 #define EEPROM_ADDR_MSB_MASK GENMASK(17, 8)
57 #define to_amdgpu_device(x) (container_of(x, struct amdgpu_ras, eeprom_control))->adev
59 static bool __get_eeprom_i2c_addr_arct(struct amdgpu_device *adev,
62 struct atom_context *atom_ctx = adev->mode_info.atom_context;
64 if (!i2c_addr || !atom_ctx)
67 if (strnstr(atom_ctx->vbios_version,
69 sizeof(atom_ctx->vbios_version)))
70 *i2c_addr = EEPROM_I2C_TARGET_ADDR_ARCTURUS_D342;
72 *i2c_addr = EEPROM_I2C_TARGET_ADDR_ARCTURUS;
77 static bool __get_eeprom_i2c_addr(struct amdgpu_device *adev,
83 switch (adev->asic_type) {
85 *i2c_addr = EEPROM_I2C_TARGET_ADDR_VEGA20;
89 return __get_eeprom_i2c_addr_arct(adev, i2c_addr);
98 static void __encode_table_header_to_buff(struct amdgpu_ras_eeprom_table_header *hdr,
101 uint32_t *pp = (uint32_t *) buff;
103 pp[0] = cpu_to_le32(hdr->header);
104 pp[1] = cpu_to_le32(hdr->version);
105 pp[2] = cpu_to_le32(hdr->first_rec_offset);
106 pp[3] = cpu_to_le32(hdr->tbl_size);
107 pp[4] = cpu_to_le32(hdr->checksum);
110 static void __decode_table_header_from_buff(struct amdgpu_ras_eeprom_table_header *hdr,
113 uint32_t *pp = (uint32_t *)buff;
115 hdr->header = le32_to_cpu(pp[0]);
116 hdr->version = le32_to_cpu(pp[1]);
117 hdr->first_rec_offset = le32_to_cpu(pp[2]);
118 hdr->tbl_size = le32_to_cpu(pp[3]);
119 hdr->checksum = le32_to_cpu(pp[4]);
122 static int __update_table_header(struct amdgpu_ras_eeprom_control *control,
126 struct amdgpu_device *adev = to_amdgpu_device(control);
127 struct i2c_msg msg = {
130 .len = EEPROM_ADDRESS_SIZE + EEPROM_TABLE_HEADER_SIZE,
135 *(uint16_t *)buff = EEPROM_HDR_START;
136 __encode_table_header_to_buff(&control->tbl_hdr, buff + EEPROM_ADDRESS_SIZE);
138 msg.addr = control->i2c_address;
140 ret = i2c_transfer(&adev->pm.smu_i2c, &msg, 1);
142 DRM_ERROR("Failed to write EEPROM table header, ret:%d", ret);
147 static uint32_t __calc_hdr_byte_sum(struct amdgpu_ras_eeprom_control *control)
150 uint32_t tbl_sum = 0;
152 /* Header checksum, skip checksum field in the calculation */
153 for (i = 0; i < sizeof(control->tbl_hdr) - sizeof(control->tbl_hdr.checksum); i++)
154 tbl_sum += *(((unsigned char *)&control->tbl_hdr) + i);
159 static uint32_t __calc_recs_byte_sum(struct eeprom_table_record *records,
163 uint32_t tbl_sum = 0;
165 /* Records checksum */
166 for (i = 0; i < num; i++) {
167 struct eeprom_table_record *record = &records[i];
169 for (j = 0; j < sizeof(*record); j++) {
170 tbl_sum += *(((unsigned char *)record) + j);
177 static inline uint32_t __calc_tbl_byte_sum(struct amdgpu_ras_eeprom_control *control,
178 struct eeprom_table_record *records, int num)
180 return __calc_hdr_byte_sum(control) + __calc_recs_byte_sum(records, num);
183 /* Checksum = 256 -((sum of all table entries) mod 256) */
184 static void __update_tbl_checksum(struct amdgpu_ras_eeprom_control *control,
185 struct eeprom_table_record *records, int num,
186 uint32_t old_hdr_byte_sum)
189 * This will update the table sum with new records.
191 * TODO: What happens when the EEPROM table is to be wrapped around
192 * and old records from start will get overridden.
195 /* need to recalculate updated header byte sum */
196 control->tbl_byte_sum -= old_hdr_byte_sum;
197 control->tbl_byte_sum += __calc_tbl_byte_sum(control, records, num);
199 control->tbl_hdr.checksum = 256 - (control->tbl_byte_sum % 256);
202 /* table sum mod 256 + checksum must equals 256 */
203 static bool __validate_tbl_checksum(struct amdgpu_ras_eeprom_control *control,
204 struct eeprom_table_record *records, int num)
206 control->tbl_byte_sum = __calc_tbl_byte_sum(control, records, num);
208 if (control->tbl_hdr.checksum + (control->tbl_byte_sum % 256) != 256) {
209 DRM_WARN("Checksum mismatch, checksum: %u ", control->tbl_hdr.checksum);
216 int amdgpu_ras_eeprom_reset_table(struct amdgpu_ras_eeprom_control *control)
218 unsigned char buff[EEPROM_ADDRESS_SIZE + EEPROM_TABLE_HEADER_SIZE] = { 0 };
219 struct amdgpu_ras_eeprom_table_header *hdr = &control->tbl_hdr;
222 mutex_lock(&control->tbl_mutex);
224 hdr->header = EEPROM_TABLE_HDR_VAL;
225 hdr->version = EEPROM_TABLE_VER;
226 hdr->first_rec_offset = EEPROM_RECORD_START;
227 hdr->tbl_size = EEPROM_TABLE_HEADER_SIZE;
229 control->tbl_byte_sum = 0;
230 __update_tbl_checksum(control, NULL, 0, 0);
231 control->next_addr = EEPROM_RECORD_START;
233 ret = __update_table_header(control, buff);
235 mutex_unlock(&control->tbl_mutex);
241 int amdgpu_ras_eeprom_init(struct amdgpu_ras_eeprom_control *control)
244 struct amdgpu_device *adev = to_amdgpu_device(control);
245 unsigned char buff[EEPROM_ADDRESS_SIZE + EEPROM_TABLE_HEADER_SIZE] = { 0 };
246 struct amdgpu_ras_eeprom_table_header *hdr = &control->tbl_hdr;
247 struct i2c_msg msg = {
250 .len = EEPROM_ADDRESS_SIZE + EEPROM_TABLE_HEADER_SIZE,
254 /* Verify i2c adapter is initialized */
255 if (!adev->pm.smu_i2c.algo)
258 if (!__get_eeprom_i2c_addr(adev, &control->i2c_address))
261 mutex_init(&control->tbl_mutex);
263 msg.addr = control->i2c_address;
264 /* Read/Create table header from EEPROM address 0 */
265 ret = i2c_transfer(&adev->pm.smu_i2c, &msg, 1);
267 DRM_ERROR("Failed to read EEPROM table header, ret:%d", ret);
271 __decode_table_header_from_buff(hdr, &buff[2]);
273 if (hdr->header == EEPROM_TABLE_HDR_VAL) {
274 control->num_recs = (hdr->tbl_size - EEPROM_TABLE_HEADER_SIZE) /
275 EEPROM_TABLE_RECORD_SIZE;
276 control->tbl_byte_sum = __calc_hdr_byte_sum(control);
277 control->next_addr = EEPROM_RECORD_START;
279 DRM_DEBUG_DRIVER("Found existing EEPROM table with %d records",
283 DRM_INFO("Creating new EEPROM table");
285 ret = amdgpu_ras_eeprom_reset_table(control);
288 return ret == 1 ? 0 : -EIO;
291 static void __encode_table_record_to_buff(struct amdgpu_ras_eeprom_control *control,
292 struct eeprom_table_record *record,
298 /* Next are all record fields according to EEPROM page spec in LE foramt */
299 buff[i++] = record->err_type;
301 buff[i++] = record->bank;
303 tmp = cpu_to_le64(record->ts);
304 memcpy(buff + i, &tmp, 8);
307 tmp = cpu_to_le64((record->offset & 0xffffffffffff));
308 memcpy(buff + i, &tmp, 6);
311 buff[i++] = record->mem_channel;
312 buff[i++] = record->mcumc_id;
314 tmp = cpu_to_le64((record->retired_page & 0xffffffffffff));
315 memcpy(buff + i, &tmp, 6);
318 static void __decode_table_record_from_buff(struct amdgpu_ras_eeprom_control *control,
319 struct eeprom_table_record *record,
325 /* Next are all record fields according to EEPROM page spec in LE foramt */
326 record->err_type = buff[i++];
328 record->bank = buff[i++];
330 memcpy(&tmp, buff + i, 8);
331 record->ts = le64_to_cpu(tmp);
334 memcpy(&tmp, buff + i, 6);
335 record->offset = (le64_to_cpu(tmp) & 0xffffffffffff);
338 record->mem_channel = buff[i++];
339 record->mcumc_id = buff[i++];
341 memcpy(&tmp, buff + i, 6);
342 record->retired_page = (le64_to_cpu(tmp) & 0xffffffffffff);
346 * When reaching end of EEPROM memory jump back to 0 record address
347 * When next record access will go beyond EEPROM page boundary modify bits A17/A8
348 * in I2C selector to go to next page
350 static uint32_t __correct_eeprom_dest_address(uint32_t curr_address)
352 uint32_t next_address = curr_address + EEPROM_TABLE_RECORD_SIZE;
354 /* When all EEPROM memory used jump back to 0 address */
355 if (next_address > EEPROM_SIZE_BYTES) {
356 DRM_INFO("Reached end of EEPROM memory, jumping to 0 "
357 "and overriding old record");
358 return EEPROM_RECORD_START;
362 * To check if we overflow page boundary compare next address with
363 * current and see if bits 17/8 of the EEPROM address will change
364 * If they do start from the next 256b page
366 * https://www.st.com/resource/en/datasheet/m24m02-dr.pdf sec. 5.1.2
368 if ((curr_address & EEPROM_ADDR_MSB_MASK) != (next_address & EEPROM_ADDR_MSB_MASK)) {
369 DRM_DEBUG_DRIVER("Reached end of EEPROM memory page, jumping to next: %lx",
370 (next_address & EEPROM_ADDR_MSB_MASK));
372 return (next_address & EEPROM_ADDR_MSB_MASK);
378 int amdgpu_ras_eeprom_process_recods(struct amdgpu_ras_eeprom_control *control,
379 struct eeprom_table_record *records,
384 struct i2c_msg *msgs, *msg;
385 unsigned char *buffs, *buff;
386 struct eeprom_table_record *record;
387 struct amdgpu_device *adev = to_amdgpu_device(control);
389 if (adev->asic_type != CHIP_VEGA20 && adev->asic_type != CHIP_ARCTURUS)
392 buffs = kcalloc(num, EEPROM_ADDRESS_SIZE + EEPROM_TABLE_RECORD_SIZE,
397 mutex_lock(&control->tbl_mutex);
399 msgs = kcalloc(num, sizeof(*msgs), GFP_KERNEL);
405 /* In case of overflow just start from beginning to not lose newest records */
406 if (write && (control->next_addr + EEPROM_TABLE_RECORD_SIZE * num > EEPROM_SIZE_BYTES))
407 control->next_addr = EEPROM_RECORD_START;
411 * TODO Currently makes EEPROM writes for each record, this creates
412 * internal fragmentation. Optimized the code to do full page write of
415 for (i = 0; i < num; i++) {
416 buff = &buffs[i * (EEPROM_ADDRESS_SIZE + EEPROM_TABLE_RECORD_SIZE)];
417 record = &records[i];
420 control->next_addr = __correct_eeprom_dest_address(control->next_addr);
423 * Update bits 16,17 of EEPROM address in I2C address by setting them
424 * to bits 1,2 of Device address byte
426 msg->addr = control->i2c_address |
427 ((control->next_addr & EEPROM_ADDR_MSB_MASK) >> 15);
428 msg->flags = write ? 0 : I2C_M_RD;
429 msg->len = EEPROM_ADDRESS_SIZE + EEPROM_TABLE_RECORD_SIZE;
432 /* Insert the EEPROM dest addess, bits 0-15 */
433 buff[0] = ((control->next_addr >> 8) & 0xff);
434 buff[1] = (control->next_addr & 0xff);
436 /* EEPROM table content is stored in LE format */
438 __encode_table_record_to_buff(control, record, buff + EEPROM_ADDRESS_SIZE);
441 * The destination EEPROM address might need to be corrected to account
442 * for page or entire memory wrapping
444 control->next_addr += EEPROM_TABLE_RECORD_SIZE;
447 ret = i2c_transfer(&adev->pm.smu_i2c, msgs, num);
449 DRM_ERROR("Failed to process EEPROM table records, ret:%d", ret);
451 /* TODO Restore prev next EEPROM address ? */
457 for (i = 0; i < num; i++) {
458 buff = &buffs[i*(EEPROM_ADDRESS_SIZE + EEPROM_TABLE_RECORD_SIZE)];
459 record = &records[i];
461 __decode_table_record_from_buff(control, record, buff + EEPROM_ADDRESS_SIZE);
466 uint32_t old_hdr_byte_sum = __calc_hdr_byte_sum(control);
469 * Update table header with size and CRC and account for table
470 * wrap around where the assumption is that we treat it as empty
473 * TODO - Check the assumption is correct
475 control->num_recs += num;
476 control->num_recs %= EEPROM_MAX_RECORD_NUM;
477 control->tbl_hdr.tbl_size += EEPROM_TABLE_RECORD_SIZE * num;
478 if (control->tbl_hdr.tbl_size > EEPROM_SIZE_BYTES)
479 control->tbl_hdr.tbl_size = EEPROM_TABLE_HEADER_SIZE +
480 control->num_recs * EEPROM_TABLE_RECORD_SIZE;
482 __update_tbl_checksum(control, records, num, old_hdr_byte_sum);
484 __update_table_header(control, buffs);
485 } else if (!__validate_tbl_checksum(control, records, num)) {
486 DRM_WARN("EEPROM Table checksum mismatch!");
487 /* TODO Uncomment when EEPROM read/write is relliable */
497 mutex_unlock(&control->tbl_mutex);
499 return ret == num ? 0 : -EIO;
502 /* Used for testing if bugs encountered */
504 void amdgpu_ras_eeprom_test(struct amdgpu_ras_eeprom_control *control)
507 struct eeprom_table_record *recs = kcalloc(1, sizeof(*recs), GFP_KERNEL);
512 for (i = 0; i < 1 ; i++) {
513 recs[i].address = 0xdeadbeef;
514 recs[i].retired_page = i;
517 if (!amdgpu_ras_eeprom_process_recods(control, recs, true, 1)) {
519 memset(recs, 0, sizeof(*recs) * 1);
521 control->next_addr = EEPROM_RECORD_START;
523 if (!amdgpu_ras_eeprom_process_recods(control, recs, false, 1)) {
524 for (i = 0; i < 1; i++)
525 DRM_INFO("rec.address :0x%llx, rec.retired_page :%llu",
526 recs[i].address, recs[i].retired_page);
528 DRM_ERROR("Failed in reading from table");
531 DRM_ERROR("Failed in writing to table");