2 * Copyright 2019 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
24 #include "amdgpu_ras_eeprom.h"
26 #include "amdgpu_ras.h"
27 #include <linux/bits.h>
29 #include "amdgpu_eeprom.h"
30 #include "amdgpu_atomfirmware.h"
31 #include <linux/debugfs.h>
32 #include <linux/uaccess.h>
34 #define EEPROM_I2C_MADDR_VEGA20 0x0
35 #define EEPROM_I2C_MADDR_ARCTURUS 0x40000
36 #define EEPROM_I2C_MADDR_ARCTURUS_D342 0x0
37 #define EEPROM_I2C_MADDR_SIENNA_CICHLID 0x0
38 #define EEPROM_I2C_MADDR_ALDEBARAN 0x0
41 * The 2 macros bellow represent the actual size in bytes that
42 * those entities occupy in the EEPROM memory.
43 * RAS_TABLE_RECORD_SIZE is different than sizeof(eeprom_table_record) which
44 * uses uint64 to store 6b fields such as retired_page.
46 #define RAS_TABLE_HEADER_SIZE 20
47 #define RAS_TABLE_RECORD_SIZE 24
49 /* Table hdr is 'AMDR' */
50 #define RAS_TABLE_HDR_VAL 0x414d4452
51 #define RAS_TABLE_VER 0x00010000
53 /* Bad GPU tag ‘BADG’ */
54 #define RAS_TABLE_HDR_BAD 0x42414447
56 /* Assume 2-Mbit size EEPROM and take up the whole space. */
57 #define RAS_TBL_SIZE_BYTES (256 * 1024)
58 #define RAS_TABLE_START 0
59 #define RAS_HDR_START RAS_TABLE_START
60 #define RAS_RECORD_START (RAS_HDR_START + RAS_TABLE_HEADER_SIZE)
61 #define RAS_MAX_RECORD_COUNT ((RAS_TBL_SIZE_BYTES - RAS_TABLE_HEADER_SIZE) \
62 / RAS_TABLE_RECORD_SIZE)
64 /* Given a zero-based index of an EEPROM RAS record, yields the EEPROM
65 * offset off of RAS_TABLE_START. That is, this is something you can
66 * add to control->i2c_address, and then tell I2C layer to read
67 * from/write to there. _N is the so called absolute index,
68 * because it starts right after the table header.
70 #define RAS_INDEX_TO_OFFSET(_C, _N) ((_C)->ras_record_offset + \
71 (_N) * RAS_TABLE_RECORD_SIZE)
73 #define RAS_OFFSET_TO_INDEX(_C, _O) (((_O) - \
74 (_C)->ras_record_offset) / RAS_TABLE_RECORD_SIZE)
76 /* Given a 0-based relative record index, 0, 1, 2, ..., etc., off
77 * of "fri", return the absolute record index off of the end of
80 #define RAS_RI_TO_AI(_C, _I) (((_I) + (_C)->ras_fri) % \
81 (_C)->ras_max_record_count)
83 #define RAS_NUM_RECS(_tbl_hdr) (((_tbl_hdr)->tbl_size - \
84 RAS_TABLE_HEADER_SIZE) / RAS_TABLE_RECORD_SIZE)
86 #define to_amdgpu_device(x) (container_of(x, struct amdgpu_ras, eeprom_control))->adev
88 static bool __is_ras_eeprom_supported(struct amdgpu_device *adev)
90 return adev->asic_type == CHIP_VEGA20 ||
91 adev->asic_type == CHIP_ARCTURUS ||
92 adev->asic_type == CHIP_SIENNA_CICHLID ||
93 adev->asic_type == CHIP_ALDEBARAN;
96 static bool __get_eeprom_i2c_addr_arct(struct amdgpu_device *adev,
97 struct amdgpu_ras_eeprom_control *control)
99 struct atom_context *atom_ctx = adev->mode_info.atom_context;
101 if (!control || !atom_ctx)
104 if (strnstr(atom_ctx->vbios_version,
106 sizeof(atom_ctx->vbios_version)))
107 control->i2c_address = EEPROM_I2C_MADDR_ARCTURUS_D342;
109 control->i2c_address = EEPROM_I2C_MADDR_ARCTURUS;
114 static bool __get_eeprom_i2c_addr(struct amdgpu_device *adev,
115 struct amdgpu_ras_eeprom_control *control)
117 uint8_t ras_rom_i2c_slave_addr;
122 control->i2c_address = 0;
124 if (amdgpu_atomfirmware_ras_rom_addr(adev, &ras_rom_i2c_slave_addr))
126 switch (ras_rom_i2c_slave_addr) {
128 control->i2c_address = 0;
131 control->i2c_address = 0x40000;
134 dev_warn(adev->dev, "RAS EEPROM I2C slave address %02x not supported",
135 ras_rom_i2c_slave_addr);
140 switch (adev->asic_type) {
142 control->i2c_address = EEPROM_I2C_MADDR_VEGA20;
146 return __get_eeprom_i2c_addr_arct(adev, control);
148 case CHIP_SIENNA_CICHLID:
149 control->i2c_address = EEPROM_I2C_MADDR_SIENNA_CICHLID;
153 control->i2c_address = EEPROM_I2C_MADDR_ALDEBARAN;
164 __encode_table_header_to_buf(struct amdgpu_ras_eeprom_table_header *hdr,
167 u32 *pp = (uint32_t *)buf;
169 pp[0] = cpu_to_le32(hdr->header);
170 pp[1] = cpu_to_le32(hdr->version);
171 pp[2] = cpu_to_le32(hdr->first_rec_offset);
172 pp[3] = cpu_to_le32(hdr->tbl_size);
173 pp[4] = cpu_to_le32(hdr->checksum);
177 __decode_table_header_from_buf(struct amdgpu_ras_eeprom_table_header *hdr,
180 u32 *pp = (uint32_t *)buf;
182 hdr->header = le32_to_cpu(pp[0]);
183 hdr->version = le32_to_cpu(pp[1]);
184 hdr->first_rec_offset = le32_to_cpu(pp[2]);
185 hdr->tbl_size = le32_to_cpu(pp[3]);
186 hdr->checksum = le32_to_cpu(pp[4]);
189 static int __write_table_header(struct amdgpu_ras_eeprom_control *control)
191 u8 buf[RAS_TABLE_HEADER_SIZE];
192 struct amdgpu_device *adev = to_amdgpu_device(control);
195 memset(buf, 0, sizeof(buf));
196 __encode_table_header_to_buf(&control->tbl_hdr, buf);
198 /* i2c may be unstable in gpu reset */
199 down_read(&adev->reset_sem);
200 res = amdgpu_eeprom_write(&adev->pm.smu_i2c,
201 control->i2c_address +
202 control->ras_header_offset,
203 buf, RAS_TABLE_HEADER_SIZE);
204 up_read(&adev->reset_sem);
207 DRM_ERROR("Failed to write EEPROM table header:%d", res);
208 } else if (res < RAS_TABLE_HEADER_SIZE) {
209 DRM_ERROR("Short write:%d out of %d\n",
210 res, RAS_TABLE_HEADER_SIZE);
219 static u8 __calc_hdr_byte_sum(const struct amdgpu_ras_eeprom_control *control)
225 /* Header checksum, skip checksum field in the calculation */
226 sz = sizeof(control->tbl_hdr) - sizeof(control->tbl_hdr.checksum);
227 pp = (u8 *) &control->tbl_hdr;
229 for (ii = 0; ii < sz; ii++, pp++)
235 static int amdgpu_ras_eeprom_correct_header_tag(
236 struct amdgpu_ras_eeprom_control *control,
239 struct amdgpu_ras_eeprom_table_header *hdr = &control->tbl_hdr;
244 csum = -hdr->checksum;
246 hh = (void *) &hdr->header;
247 csum -= (hh[0] + hh[1] + hh[2] + hh[3]);
248 hh = (void *) &header;
249 csum += hh[0] + hh[1] + hh[2] + hh[3];
251 mutex_lock(&control->ras_tbl_mutex);
252 hdr->header = header;
253 hdr->checksum = csum;
254 res = __write_table_header(control);
255 mutex_unlock(&control->ras_tbl_mutex);
261 * amdgpu_ras_eeprom_reset_table -- Reset the RAS EEPROM table
262 * @control: pointer to control structure
264 * Reset the contents of the header of the RAS EEPROM table.
265 * Return 0 on success, -errno on error.
267 int amdgpu_ras_eeprom_reset_table(struct amdgpu_ras_eeprom_control *control)
269 struct amdgpu_ras_eeprom_table_header *hdr = &control->tbl_hdr;
273 mutex_lock(&control->ras_tbl_mutex);
275 hdr->header = RAS_TABLE_HDR_VAL;
276 hdr->version = RAS_TABLE_VER;
277 hdr->first_rec_offset = RAS_RECORD_START;
278 hdr->tbl_size = RAS_TABLE_HEADER_SIZE;
280 csum = __calc_hdr_byte_sum(control);
282 hdr->checksum = csum;
283 res = __write_table_header(control);
285 control->ras_num_recs = 0;
286 control->ras_fri = 0;
288 amdgpu_ras_debugfs_set_ret_size(control);
290 mutex_unlock(&control->ras_tbl_mutex);
296 __encode_table_record_to_buf(struct amdgpu_ras_eeprom_control *control,
297 struct eeprom_table_record *record,
303 /* Next are all record fields according to EEPROM page spec in LE foramt */
304 buf[i++] = record->err_type;
306 buf[i++] = record->bank;
308 tmp = cpu_to_le64(record->ts);
309 memcpy(buf + i, &tmp, 8);
312 tmp = cpu_to_le64((record->offset & 0xffffffffffff));
313 memcpy(buf + i, &tmp, 6);
316 buf[i++] = record->mem_channel;
317 buf[i++] = record->mcumc_id;
319 tmp = cpu_to_le64((record->retired_page & 0xffffffffffff));
320 memcpy(buf + i, &tmp, 6);
324 __decode_table_record_from_buf(struct amdgpu_ras_eeprom_control *control,
325 struct eeprom_table_record *record,
331 /* Next are all record fields according to EEPROM page spec in LE foramt */
332 record->err_type = buf[i++];
334 record->bank = buf[i++];
336 memcpy(&tmp, buf + i, 8);
337 record->ts = le64_to_cpu(tmp);
340 memcpy(&tmp, buf + i, 6);
341 record->offset = (le64_to_cpu(tmp) & 0xffffffffffff);
344 record->mem_channel = buf[i++];
345 record->mcumc_id = buf[i++];
347 memcpy(&tmp, buf + i, 6);
348 record->retired_page = (le64_to_cpu(tmp) & 0xffffffffffff);
351 bool amdgpu_ras_eeprom_check_err_threshold(struct amdgpu_device *adev)
353 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
355 if (!__is_ras_eeprom_supported(adev))
358 /* skip check eeprom table for VEGA20 Gaming */
362 if (!(con->features & BIT(AMDGPU_RAS_BLOCK__UMC)))
365 if (con->eeprom_control.tbl_hdr.header == RAS_TABLE_HDR_BAD) {
366 dev_warn(adev->dev, "This GPU is in BAD status.");
367 dev_warn(adev->dev, "Please retire it or set a larger "
368 "threshold value when reloading driver.\n");
376 * __amdgpu_ras_eeprom_write -- write indexed from buffer to EEPROM
377 * @control: pointer to control structure
378 * @buf: pointer to buffer containing data to write
379 * @fri: start writing at this index
380 * @num: number of records to write
382 * The caller must hold the table mutex in @control.
383 * Return 0 on success, -errno otherwise.
385 static int __amdgpu_ras_eeprom_write(struct amdgpu_ras_eeprom_control *control,
386 u8 *buf, const u32 fri, const u32 num)
388 struct amdgpu_device *adev = to_amdgpu_device(control);
392 /* i2c may be unstable in gpu reset */
393 down_read(&adev->reset_sem);
394 buf_size = num * RAS_TABLE_RECORD_SIZE;
395 res = amdgpu_eeprom_write(&adev->pm.smu_i2c,
396 control->i2c_address +
397 RAS_INDEX_TO_OFFSET(control, fri),
399 up_read(&adev->reset_sem);
401 DRM_ERROR("Writing %d EEPROM table records error:%d",
403 } else if (res < buf_size) {
404 /* Short write, return error.
406 DRM_ERROR("Wrote %d records out of %d",
407 res / RAS_TABLE_RECORD_SIZE, num);
417 amdgpu_ras_eeprom_append_table(struct amdgpu_ras_eeprom_control *control,
418 struct eeprom_table_record *record,
425 buf = kcalloc(num, RAS_TABLE_RECORD_SIZE, GFP_KERNEL);
429 /* Encode all of them in one go.
432 for (i = 0; i < num; i++, pp += RAS_TABLE_RECORD_SIZE)
433 __encode_table_record_to_buf(control, &record[i], pp);
435 /* a, first record index to write into.
436 * b, last record index to write into.
437 * a = first index to read (fri) + number of records in the table,
439 * Let N = control->ras_max_num_record_count, then we have,
440 * case 0: 0 <= a <= b < N,
441 * just append @num records starting at a;
442 * case 1: 0 <= a < N <= b,
443 * append (N - a) records starting at a, and
444 * append the remainder, b % N + 1, starting at 0.
445 * case 2: 0 <= fri < N <= a <= b, then modulo N we get two subcases,
446 * case 2a: 0 <= a <= b < N
447 * append num records starting at a; and fix fri if b overwrote it,
448 * and since a <= b, if b overwrote it then a must've also,
449 * and if b didn't overwrite it, then a didn't also.
450 * case 2b: 0 <= b < a < N
451 * write num records starting at a, which wraps around 0=N
452 * and overwrite fri unconditionally. Now from case 2a,
453 * this means that b eclipsed fri to overwrite it and wrap
454 * around 0 again, i.e. b = 2N+r pre modulo N, so we unconditionally
455 * set fri = b + 1 (mod N).
456 * Now, since fri is updated in every case, except the trivial case 0,
457 * the number of records present in the table after writing, is,
458 * num_recs - 1 = b - fri (mod N), and we take the positive value,
459 * by adding an arbitrary multiple of N before taking the modulo N
462 a = control->ras_fri + control->ras_num_recs;
464 if (b < control->ras_max_record_count) {
465 res = __amdgpu_ras_eeprom_write(control, buf, a, num);
466 } else if (a < control->ras_max_record_count) {
469 g0 = control->ras_max_record_count - a;
470 g1 = b % control->ras_max_record_count + 1;
471 res = __amdgpu_ras_eeprom_write(control, buf, a, g0);
474 res = __amdgpu_ras_eeprom_write(control,
475 buf + g0 * RAS_TABLE_RECORD_SIZE,
479 if (g1 > control->ras_fri)
480 control->ras_fri = g1 % control->ras_max_record_count;
482 a %= control->ras_max_record_count;
483 b %= control->ras_max_record_count;
486 /* Note that, b - a + 1 = num. */
487 res = __amdgpu_ras_eeprom_write(control, buf, a, num);
490 if (b >= control->ras_fri)
491 control->ras_fri = (b + 1) % control->ras_max_record_count;
495 /* b < a, which means, we write from
496 * a to the end of the table, and from
497 * the start of the table to b.
499 g0 = control->ras_max_record_count - a;
501 res = __amdgpu_ras_eeprom_write(control, buf, a, g0);
504 res = __amdgpu_ras_eeprom_write(control,
505 buf + g0 * RAS_TABLE_RECORD_SIZE,
509 control->ras_fri = g1 % control->ras_max_record_count;
512 control->ras_num_recs = 1 + (control->ras_max_record_count + b
514 % control->ras_max_record_count;
521 amdgpu_ras_eeprom_update_header(struct amdgpu_ras_eeprom_control *control)
523 struct amdgpu_device *adev = to_amdgpu_device(control);
524 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev);
529 /* Modify the header if it exceeds.
531 if (amdgpu_bad_page_threshold != 0 &&
532 control->ras_num_recs >= ras->bad_page_cnt_threshold) {
534 "Saved bad pages %d reaches threshold value %d\n",
535 control->ras_num_recs, ras->bad_page_cnt_threshold);
536 control->tbl_hdr.header = RAS_TABLE_HDR_BAD;
539 control->tbl_hdr.version = RAS_TABLE_VER;
540 control->tbl_hdr.first_rec_offset = RAS_INDEX_TO_OFFSET(control, control->ras_fri);
541 control->tbl_hdr.tbl_size = RAS_TABLE_HEADER_SIZE + control->ras_num_recs * RAS_TABLE_RECORD_SIZE;
542 control->tbl_hdr.checksum = 0;
544 buf_size = control->ras_num_recs * RAS_TABLE_RECORD_SIZE;
545 buf = kcalloc(control->ras_num_recs, RAS_TABLE_RECORD_SIZE, GFP_KERNEL);
547 DRM_ERROR("allocating memory for table of size %d bytes failed\n",
548 control->tbl_hdr.tbl_size);
553 down_read(&adev->reset_sem);
554 res = amdgpu_eeprom_read(&adev->pm.smu_i2c,
555 control->i2c_address +
556 control->ras_record_offset,
558 up_read(&adev->reset_sem);
560 DRM_ERROR("EEPROM failed reading records:%d\n",
563 } else if (res < buf_size) {
564 DRM_ERROR("EEPROM read %d out of %d bytes\n",
570 /* Recalc the checksum.
573 for (pp = buf; pp < buf + buf_size; pp++)
576 csum += __calc_hdr_byte_sum(control);
577 /* avoid sign extension when assigning to "checksum" */
579 control->tbl_hdr.checksum = csum;
580 res = __write_table_header(control);
587 * amdgpu_ras_eeprom_append -- append records to the EEPROM RAS table
588 * @control: pointer to control structure
589 * @record: array of records to append
590 * @num: number of records in @record array
592 * Append @num records to the table, calculate the checksum and write
593 * the table back to EEPROM. The maximum number of records that
594 * can be appended is between 1 and control->ras_max_record_count,
595 * regardless of how many records are already stored in the table.
597 * Return 0 on success or if EEPROM is not supported, -errno on error.
599 int amdgpu_ras_eeprom_append(struct amdgpu_ras_eeprom_control *control,
600 struct eeprom_table_record *record,
603 struct amdgpu_device *adev = to_amdgpu_device(control);
606 if (!__is_ras_eeprom_supported(adev))
610 DRM_ERROR("will not append 0 records\n");
612 } else if (num > control->ras_max_record_count) {
613 DRM_ERROR("cannot append %d records than the size of table %d\n",
614 num, control->ras_max_record_count);
618 mutex_lock(&control->ras_tbl_mutex);
620 res = amdgpu_ras_eeprom_append_table(control, record, num);
622 res = amdgpu_ras_eeprom_update_header(control);
624 amdgpu_ras_debugfs_set_ret_size(control);
626 mutex_unlock(&control->ras_tbl_mutex);
631 * __amdgpu_ras_eeprom_read -- read indexed from EEPROM into buffer
632 * @control: pointer to control structure
633 * @buf: pointer to buffer to read into
634 * @fri: first record index, start reading at this index, absolute index
635 * @num: number of records to read
637 * The caller must hold the table mutex in @control.
638 * Return 0 on success, -errno otherwise.
640 static int __amdgpu_ras_eeprom_read(struct amdgpu_ras_eeprom_control *control,
641 u8 *buf, const u32 fri, const u32 num)
643 struct amdgpu_device *adev = to_amdgpu_device(control);
647 /* i2c may be unstable in gpu reset */
648 down_read(&adev->reset_sem);
649 buf_size = num * RAS_TABLE_RECORD_SIZE;
650 res = amdgpu_eeprom_read(&adev->pm.smu_i2c,
651 control->i2c_address +
652 RAS_INDEX_TO_OFFSET(control, fri),
654 up_read(&adev->reset_sem);
656 DRM_ERROR("Reading %d EEPROM table records error:%d",
658 } else if (res < buf_size) {
659 /* Short read, return error.
661 DRM_ERROR("Read %d records out of %d",
662 res / RAS_TABLE_RECORD_SIZE, num);
672 * amdgpu_ras_eeprom_read -- read EEPROM
673 * @control: pointer to control structure
674 * @record: array of records to read into
675 * @num: number of records in @record
677 * Reads num records from the RAS table in EEPROM and
678 * writes the data into @record array.
680 * Returns 0 on success, -errno on error.
682 int amdgpu_ras_eeprom_read(struct amdgpu_ras_eeprom_control *control,
683 struct eeprom_table_record *record,
686 struct amdgpu_device *adev = to_amdgpu_device(control);
691 if (!__is_ras_eeprom_supported(adev))
695 DRM_ERROR("will not read 0 records\n");
697 } else if (num > control->ras_num_recs) {
698 DRM_ERROR("too many records to read:%d available:%d\n",
699 num, control->ras_num_recs);
703 buf = kcalloc(num, RAS_TABLE_RECORD_SIZE, GFP_KERNEL);
707 /* Determine how many records to read, from the first record
708 * index, fri, to the end of the table, and from the beginning
709 * of the table, such that the total number of records is
710 * @num, and we handle wrap around when fri > 0 and
711 * fri + num > RAS_MAX_RECORD_COUNT.
713 * First we compute the index of the last element
714 * which would be fetched from each region,
715 * g0 is in [fri, fri + num - 1], and
716 * g1 is in [0, RAS_MAX_RECORD_COUNT - 1].
717 * Then, if g0 < RAS_MAX_RECORD_COUNT, the index of
718 * the last element to fetch, we set g0 to _the number_
719 * of elements to fetch, @num, since we know that the last
720 * indexed to be fetched does not exceed the table.
722 * If, however, g0 >= RAS_MAX_RECORD_COUNT, then
723 * we set g0 to the number of elements to read
724 * until the end of the table, and g1 to the number of
725 * elements to read from the beginning of the table.
727 g0 = control->ras_fri + num - 1;
728 g1 = g0 % control->ras_max_record_count;
729 if (g0 < control->ras_max_record_count) {
733 g0 = control->ras_max_record_count - control->ras_fri;
737 mutex_lock(&control->ras_tbl_mutex);
738 res = __amdgpu_ras_eeprom_read(control, buf, control->ras_fri, g0);
742 res = __amdgpu_ras_eeprom_read(control,
743 buf + g0 * RAS_TABLE_RECORD_SIZE,
751 /* Read up everything? Then transform.
754 for (i = 0; i < num; i++, pp += RAS_TABLE_RECORD_SIZE)
755 __decode_table_record_from_buf(control, &record[i], pp);
758 mutex_unlock(&control->ras_tbl_mutex);
763 inline uint32_t amdgpu_ras_eeprom_max_record_count(void)
765 return RAS_MAX_RECORD_COUNT;
769 amdgpu_ras_debugfs_eeprom_size_read(struct file *f, char __user *buf,
770 size_t size, loff_t *pos)
772 struct amdgpu_device *adev = (struct amdgpu_device *)file_inode(f)->i_private;
773 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev);
774 struct amdgpu_ras_eeprom_control *control = ras ? &ras->eeprom_control : NULL;
781 if (!ras || !control) {
782 res = snprintf(data, sizeof(data), "Not supported\n");
784 res = snprintf(data, sizeof(data), "%d bytes or %d records\n",
785 RAS_TBL_SIZE_BYTES, control->ras_max_record_count);
792 res = min_t(size_t, res, size);
794 if (copy_to_user(buf, &data[*pos], res))
802 const struct file_operations amdgpu_ras_debugfs_eeprom_size_ops = {
803 .owner = THIS_MODULE,
804 .read = amdgpu_ras_debugfs_eeprom_size_read,
806 .llseek = default_llseek,
809 static const char *tbl_hdr_str = " Signature Version FirstOffs Size Checksum\n";
810 static const char *tbl_hdr_fmt = "0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n";
811 #define tbl_hdr_fmt_size (5 * (2+8) + 4 + 1)
812 static const char *rec_hdr_str = "Index Offset ErrType Bank/CU TimeStamp Offs/Addr MemChl MCUMCID RetiredPage\n";
813 static const char *rec_hdr_fmt = "%5d 0x%05X %7s 0x%02X 0x%016llX 0x%012llX 0x%02X 0x%02X 0x%012llX\n";
814 #define rec_hdr_fmt_size (5 + 1 + 7 + 1 + 7 + 1 + 7 + 1 + 18 + 1 + 14 + 1 + 6 + 1 + 7 + 1 + 14 + 1)
816 static const char *record_err_type_str[AMDGPU_RAS_EEPROM_ERR_COUNT] = {
822 static loff_t amdgpu_ras_debugfs_table_size(struct amdgpu_ras_eeprom_control *control)
824 return strlen(tbl_hdr_str) + tbl_hdr_fmt_size +
825 strlen(rec_hdr_str) + rec_hdr_fmt_size * control->ras_num_recs;
828 void amdgpu_ras_debugfs_set_ret_size(struct amdgpu_ras_eeprom_control *control)
830 struct amdgpu_ras *ras = container_of(control, struct amdgpu_ras,
832 struct dentry *de = ras->de_ras_eeprom_table;
835 d_inode(de)->i_size = amdgpu_ras_debugfs_table_size(control);
838 static ssize_t amdgpu_ras_debugfs_table_read(struct file *f, char __user *buf,
839 size_t size, loff_t *pos)
841 struct amdgpu_device *adev = (struct amdgpu_device *)file_inode(f)->i_private;
842 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev);
843 struct amdgpu_ras_eeprom_control *control = &ras->eeprom_control;
844 const size_t orig_size = size;
848 mutex_lock(&control->ras_tbl_mutex);
850 /* We want *pos - data_len > 0, which means there's
851 * bytes to be printed from data.
853 data_len = strlen(tbl_hdr_str);
854 if (*pos < data_len) {
856 data_len = min_t(size_t, data_len, size);
857 if (copy_to_user(buf, &tbl_hdr_str[*pos], data_len))
864 data_len = strlen(tbl_hdr_str) + tbl_hdr_fmt_size;
865 if (*pos < data_len && size > 0) {
866 u8 data[tbl_hdr_fmt_size + 1];
869 snprintf(data, sizeof(data), tbl_hdr_fmt,
870 control->tbl_hdr.header,
871 control->tbl_hdr.version,
872 control->tbl_hdr.first_rec_offset,
873 control->tbl_hdr.tbl_size,
874 control->tbl_hdr.checksum);
877 data_len = min_t(size_t, data_len, size);
878 lpos = *pos - strlen(tbl_hdr_str);
879 if (copy_to_user(buf, &data[lpos], data_len))
886 data_len = strlen(tbl_hdr_str) + tbl_hdr_fmt_size + strlen(rec_hdr_str);
887 if (*pos < data_len && size > 0) {
891 data_len = min_t(size_t, data_len, size);
892 lpos = *pos - strlen(tbl_hdr_str) - tbl_hdr_fmt_size;
893 if (copy_to_user(buf, &rec_hdr_str[lpos], data_len))
900 data_len = amdgpu_ras_debugfs_table_size(control);
901 if (*pos < data_len && size > 0) {
902 u8 dare[RAS_TABLE_RECORD_SIZE];
903 u8 data[rec_hdr_fmt_size + 1];
904 struct eeprom_table_record record;
907 /* Find the starting record index
909 s = *pos - strlen(tbl_hdr_str) - tbl_hdr_fmt_size -
911 s = s / rec_hdr_fmt_size;
912 r = *pos - strlen(tbl_hdr_str) - tbl_hdr_fmt_size -
914 r = r % rec_hdr_fmt_size;
916 for ( ; size > 0 && s < control->ras_num_recs; s++) {
917 u32 ai = RAS_RI_TO_AI(control, s);
918 /* Read a single record
920 res = __amdgpu_ras_eeprom_read(control, dare, ai, 1);
923 __decode_table_record_from_buf(control, &record, dare);
924 snprintf(data, sizeof(data), rec_hdr_fmt,
926 RAS_INDEX_TO_OFFSET(control, ai),
927 record_err_type_str[record.err_type],
933 record.retired_page);
935 data_len = min_t(size_t, rec_hdr_fmt_size - r, size);
936 if (copy_to_user(buf, &data[r], data_len)) {
948 mutex_unlock(&control->ras_tbl_mutex);
949 return res < 0 ? res : orig_size - size;
953 amdgpu_ras_debugfs_eeprom_table_read(struct file *f, char __user *buf,
954 size_t size, loff_t *pos)
956 struct amdgpu_device *adev = (struct amdgpu_device *)file_inode(f)->i_private;
957 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev);
958 struct amdgpu_ras_eeprom_control *control = ras ? &ras->eeprom_control : NULL;
965 if (!ras || !control) {
966 res = snprintf(data, sizeof(data), "Not supported\n");
971 res = min_t(size_t, res, size);
973 if (copy_to_user(buf, &data[*pos], res))
980 return amdgpu_ras_debugfs_table_read(f, buf, size, pos);
984 const struct file_operations amdgpu_ras_debugfs_eeprom_table_ops = {
985 .owner = THIS_MODULE,
986 .read = amdgpu_ras_debugfs_eeprom_table_read,
988 .llseek = default_llseek,
992 * __verify_ras_table_checksum -- verify the RAS EEPROM table checksum
993 * @control: pointer to control structure
995 * Check the checksum of the stored in EEPROM RAS table.
997 * Return 0 if the checksum is correct,
998 * positive if it is not correct, and
999 * -errno on I/O error.
1001 static int __verify_ras_table_checksum(struct amdgpu_ras_eeprom_control *control)
1003 struct amdgpu_device *adev = to_amdgpu_device(control);
1007 buf_size = RAS_TABLE_HEADER_SIZE +
1008 control->ras_num_recs * RAS_TABLE_RECORD_SIZE;
1009 buf = kzalloc(buf_size, GFP_KERNEL);
1011 DRM_ERROR("Out of memory checking RAS table checksum.\n");
1015 res = amdgpu_eeprom_read(&adev->pm.smu_i2c,
1016 control->i2c_address +
1017 control->ras_header_offset,
1019 if (res < buf_size) {
1020 DRM_ERROR("Partial read for checksum, res:%d\n", res);
1021 /* On partial reads, return -EIO.
1029 for (pp = buf; pp < buf + buf_size; pp++)
1033 return res < 0 ? res : csum;
1036 int amdgpu_ras_eeprom_init(struct amdgpu_ras_eeprom_control *control,
1037 bool *exceed_err_limit)
1039 struct amdgpu_device *adev = to_amdgpu_device(control);
1040 unsigned char buf[RAS_TABLE_HEADER_SIZE] = { 0 };
1041 struct amdgpu_ras_eeprom_table_header *hdr = &control->tbl_hdr;
1042 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev);
1045 *exceed_err_limit = false;
1047 if (!__is_ras_eeprom_supported(adev))
1050 /* Verify i2c adapter is initialized */
1051 if (!adev->pm.smu_i2c.algo)
1054 if (!__get_eeprom_i2c_addr(adev, control))
1057 control->ras_header_offset = RAS_HDR_START;
1058 control->ras_record_offset = RAS_RECORD_START;
1059 control->ras_max_record_count = RAS_MAX_RECORD_COUNT;
1060 mutex_init(&control->ras_tbl_mutex);
1062 /* Read the table header from EEPROM address */
1063 res = amdgpu_eeprom_read(&adev->pm.smu_i2c,
1064 control->i2c_address + control->ras_header_offset,
1065 buf, RAS_TABLE_HEADER_SIZE);
1066 if (res < RAS_TABLE_HEADER_SIZE) {
1067 DRM_ERROR("Failed to read EEPROM table header, res:%d", res);
1068 return res >= 0 ? -EIO : res;
1071 __decode_table_header_from_buf(hdr, buf);
1073 control->ras_num_recs = RAS_NUM_RECS(hdr);
1074 control->ras_fri = RAS_OFFSET_TO_INDEX(control, hdr->first_rec_offset);
1076 if (hdr->header == RAS_TABLE_HDR_VAL) {
1077 DRM_DEBUG_DRIVER("Found existing EEPROM table with %d records",
1078 control->ras_num_recs);
1079 res = __verify_ras_table_checksum(control);
1081 DRM_ERROR("RAS table incorrect checksum or error:%d\n",
1083 } else if (hdr->header == RAS_TABLE_HDR_BAD &&
1084 amdgpu_bad_page_threshold != 0) {
1085 res = __verify_ras_table_checksum(control);
1087 DRM_ERROR("RAS Table incorrect checksum or error:%d\n",
1089 if (ras->bad_page_cnt_threshold > control->ras_num_recs) {
1090 /* This means that, the threshold was increased since
1091 * the last time the system was booted, and now,
1092 * ras->bad_page_cnt_threshold - control->num_recs > 0,
1093 * so that at least one more record can be saved,
1094 * before the page count threshold is reached.
1097 "records:%d threshold:%d, resetting "
1098 "RAS table header signature",
1099 control->ras_num_recs,
1100 ras->bad_page_cnt_threshold);
1101 res = amdgpu_ras_eeprom_correct_header_tag(control,
1104 *exceed_err_limit = true;
1106 "RAS records:%d exceed threshold:%d, "
1107 "maybe retire this GPU?",
1108 control->ras_num_recs, ras->bad_page_cnt_threshold);
1111 DRM_INFO("Creating a new EEPROM table");
1113 res = amdgpu_ras_eeprom_reset_table(control);
1116 return res < 0 ? res : 0;