drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h

   1 /*
   2  * Copyright 2018 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  *
  23  */
  24 #ifndef _AMDGPU_RAS_H
  25 #define _AMDGPU_RAS_H
  26
  27 #include <linux/debugfs.h>
  28 #include <linux/list.h>
  29 #include "amdgpu.h"
  30 #include "amdgpu_psp.h"
  31 #include "ta_ras_if.h"
  32 #include "amdgpu_ras_eeprom.h"
  33
  34 #define AMDGPU_RAS_FLAG_INIT_BY_VBIOS           (0x1 << 0)
  35
  36 enum amdgpu_ras_block {
  37         AMDGPU_RAS_BLOCK__UMC = 0,
  38         AMDGPU_RAS_BLOCK__SDMA,
  39         AMDGPU_RAS_BLOCK__GFX,
  40         AMDGPU_RAS_BLOCK__MMHUB,
  41         AMDGPU_RAS_BLOCK__ATHUB,
  42         AMDGPU_RAS_BLOCK__PCIE_BIF,
  43         AMDGPU_RAS_BLOCK__HDP,
  44         AMDGPU_RAS_BLOCK__XGMI_WAFL,
  45         AMDGPU_RAS_BLOCK__DF,
  46         AMDGPU_RAS_BLOCK__SMN,
  47         AMDGPU_RAS_BLOCK__SEM,
  48         AMDGPU_RAS_BLOCK__MP0,
  49         AMDGPU_RAS_BLOCK__MP1,
  50         AMDGPU_RAS_BLOCK__FUSE,
  51         AMDGPU_RAS_BLOCK__MCA,
  52
  53         AMDGPU_RAS_BLOCK__LAST
  54 };
  55
  56 enum amdgpu_ras_mca_block {
  57         AMDGPU_RAS_MCA_BLOCK__MP0 = 0,
  58         AMDGPU_RAS_MCA_BLOCK__MP1,
  59         AMDGPU_RAS_MCA_BLOCK__MPIO,
  60         AMDGPU_RAS_MCA_BLOCK__IOHC,
  61
  62         AMDGPU_RAS_MCA_BLOCK__LAST
  63 };
  64
  65 #define AMDGPU_RAS_BLOCK_COUNT  AMDGPU_RAS_BLOCK__LAST
  66 #define AMDGPU_RAS_MCA_BLOCK_COUNT      AMDGPU_RAS_MCA_BLOCK__LAST
  67 #define AMDGPU_RAS_BLOCK_MASK   ((1ULL << AMDGPU_RAS_BLOCK_COUNT) - 1)
  68
  69 enum amdgpu_ras_gfx_subblock {
  70         /* CPC */
  71         AMDGPU_RAS_BLOCK__GFX_CPC_INDEX_START = 0,
  72         AMDGPU_RAS_BLOCK__GFX_CPC_SCRATCH =
  73                 AMDGPU_RAS_BLOCK__GFX_CPC_INDEX_START,
  74         AMDGPU_RAS_BLOCK__GFX_CPC_UCODE,
  75         AMDGPU_RAS_BLOCK__GFX_DC_STATE_ME1,
  76         AMDGPU_RAS_BLOCK__GFX_DC_CSINVOC_ME1,
  77         AMDGPU_RAS_BLOCK__GFX_DC_RESTORE_ME1,
  78         AMDGPU_RAS_BLOCK__GFX_DC_STATE_ME2,
  79         AMDGPU_RAS_BLOCK__GFX_DC_CSINVOC_ME2,
  80         AMDGPU_RAS_BLOCK__GFX_DC_RESTORE_ME2,
  81         AMDGPU_RAS_BLOCK__GFX_CPC_INDEX_END =
  82                 AMDGPU_RAS_BLOCK__GFX_DC_RESTORE_ME2,
  83         /* CPF */
  84         AMDGPU_RAS_BLOCK__GFX_CPF_INDEX_START,
  85         AMDGPU_RAS_BLOCK__GFX_CPF_ROQ_ME2 =
  86                 AMDGPU_RAS_BLOCK__GFX_CPF_INDEX_START,
  87         AMDGPU_RAS_BLOCK__GFX_CPF_ROQ_ME1,
  88         AMDGPU_RAS_BLOCK__GFX_CPF_TAG,
  89         AMDGPU_RAS_BLOCK__GFX_CPF_INDEX_END = AMDGPU_RAS_BLOCK__GFX_CPF_TAG,
  90         /* CPG */
  91         AMDGPU_RAS_BLOCK__GFX_CPG_INDEX_START,
  92         AMDGPU_RAS_BLOCK__GFX_CPG_DMA_ROQ =
  93                 AMDGPU_RAS_BLOCK__GFX_CPG_INDEX_START,
  94         AMDGPU_RAS_BLOCK__GFX_CPG_DMA_TAG,
  95         AMDGPU_RAS_BLOCK__GFX_CPG_TAG,
  96         AMDGPU_RAS_BLOCK__GFX_CPG_INDEX_END = AMDGPU_RAS_BLOCK__GFX_CPG_TAG,
  97         /* GDS */
  98         AMDGPU_RAS_BLOCK__GFX_GDS_INDEX_START,
  99         AMDGPU_RAS_BLOCK__GFX_GDS_MEM = AMDGPU_RAS_BLOCK__GFX_GDS_INDEX_START,
 100         AMDGPU_RAS_BLOCK__GFX_GDS_INPUT_QUEUE,
 101         AMDGPU_RAS_BLOCK__GFX_GDS_OA_PHY_CMD_RAM_MEM,
 102         AMDGPU_RAS_BLOCK__GFX_GDS_OA_PHY_DATA_RAM_MEM,
 103         AMDGPU_RAS_BLOCK__GFX_GDS_OA_PIPE_MEM,
 104         AMDGPU_RAS_BLOCK__GFX_GDS_INDEX_END =
 105                 AMDGPU_RAS_BLOCK__GFX_GDS_OA_PIPE_MEM,
 106         /* SPI */
 107         AMDGPU_RAS_BLOCK__GFX_SPI_SR_MEM,
 108         /* SQ */
 109         AMDGPU_RAS_BLOCK__GFX_SQ_INDEX_START,
 110         AMDGPU_RAS_BLOCK__GFX_SQ_SGPR = AMDGPU_RAS_BLOCK__GFX_SQ_INDEX_START,
 111         AMDGPU_RAS_BLOCK__GFX_SQ_LDS_D,
 112         AMDGPU_RAS_BLOCK__GFX_SQ_LDS_I,
 113         AMDGPU_RAS_BLOCK__GFX_SQ_VGPR,
 114         AMDGPU_RAS_BLOCK__GFX_SQ_INDEX_END = AMDGPU_RAS_BLOCK__GFX_SQ_VGPR,
 115         /* SQC (3 ranges) */
 116         AMDGPU_RAS_BLOCK__GFX_SQC_INDEX_START,
 117         /* SQC range 0 */
 118         AMDGPU_RAS_BLOCK__GFX_SQC_INDEX0_START =
 119                 AMDGPU_RAS_BLOCK__GFX_SQC_INDEX_START,
 120         AMDGPU_RAS_BLOCK__GFX_SQC_INST_UTCL1_LFIFO =
 121                 AMDGPU_RAS_BLOCK__GFX_SQC_INDEX0_START,
 122         AMDGPU_RAS_BLOCK__GFX_SQC_DATA_CU0_WRITE_DATA_BUF,
 123         AMDGPU_RAS_BLOCK__GFX_SQC_DATA_CU0_UTCL1_LFIFO,
 124         AMDGPU_RAS_BLOCK__GFX_SQC_DATA_CU1_WRITE_DATA_BUF,
 125         AMDGPU_RAS_BLOCK__GFX_SQC_DATA_CU1_UTCL1_LFIFO,
 126         AMDGPU_RAS_BLOCK__GFX_SQC_DATA_CU2_WRITE_DATA_BUF,
 127         AMDGPU_RAS_BLOCK__GFX_SQC_DATA_CU2_UTCL1_LFIFO,
 128         AMDGPU_RAS_BLOCK__GFX_SQC_INDEX0_END =
 129                 AMDGPU_RAS_BLOCK__GFX_SQC_DATA_CU2_UTCL1_LFIFO,
 130         /* SQC range 1 */
 131         AMDGPU_RAS_BLOCK__GFX_SQC_INDEX1_START,
 132         AMDGPU_RAS_BLOCK__GFX_SQC_INST_BANKA_TAG_RAM =
 133                 AMDGPU_RAS_BLOCK__GFX_SQC_INDEX1_START,
 134         AMDGPU_RAS_BLOCK__GFX_SQC_INST_BANKA_UTCL1_MISS_FIFO,
 135         AMDGPU_RAS_BLOCK__GFX_SQC_INST_BANKA_MISS_FIFO,
 136         AMDGPU_RAS_BLOCK__GFX_SQC_INST_BANKA_BANK_RAM,
 137         AMDGPU_RAS_BLOCK__GFX_SQC_DATA_BANKA_TAG_RAM,
 138         AMDGPU_RAS_BLOCK__GFX_SQC_DATA_BANKA_HIT_FIFO,
 139         AMDGPU_RAS_BLOCK__GFX_SQC_DATA_BANKA_MISS_FIFO,
 140         AMDGPU_RAS_BLOCK__GFX_SQC_DATA_BANKA_DIRTY_BIT_RAM,
 141         AMDGPU_RAS_BLOCK__GFX_SQC_DATA_BANKA_BANK_RAM,
 142         AMDGPU_RAS_BLOCK__GFX_SQC_INDEX1_END =
 143                 AMDGPU_RAS_BLOCK__GFX_SQC_DATA_BANKA_BANK_RAM,
 144         /* SQC range 2 */
 145         AMDGPU_RAS_BLOCK__GFX_SQC_INDEX2_START,
 146         AMDGPU_RAS_BLOCK__GFX_SQC_INST_BANKB_TAG_RAM =
 147                 AMDGPU_RAS_BLOCK__GFX_SQC_INDEX2_START,
 148         AMDGPU_RAS_BLOCK__GFX_SQC_INST_BANKB_UTCL1_MISS_FIFO,
 149         AMDGPU_RAS_BLOCK__GFX_SQC_INST_BANKB_MISS_FIFO,
 150         AMDGPU_RAS_BLOCK__GFX_SQC_INST_BANKB_BANK_RAM,
 151         AMDGPU_RAS_BLOCK__GFX_SQC_DATA_BANKB_TAG_RAM,
 152         AMDGPU_RAS_BLOCK__GFX_SQC_DATA_BANKB_HIT_FIFO,
 153         AMDGPU_RAS_BLOCK__GFX_SQC_DATA_BANKB_MISS_FIFO,
 154         AMDGPU_RAS_BLOCK__GFX_SQC_DATA_BANKB_DIRTY_BIT_RAM,
 155         AMDGPU_RAS_BLOCK__GFX_SQC_DATA_BANKB_BANK_RAM,
 156         AMDGPU_RAS_BLOCK__GFX_SQC_INDEX2_END =
 157                 AMDGPU_RAS_BLOCK__GFX_SQC_DATA_BANKB_BANK_RAM,
 158         AMDGPU_RAS_BLOCK__GFX_SQC_INDEX_END =
 159                 AMDGPU_RAS_BLOCK__GFX_SQC_INDEX2_END,
 160         /* TA */
 161         AMDGPU_RAS_BLOCK__GFX_TA_INDEX_START,
 162         AMDGPU_RAS_BLOCK__GFX_TA_FS_DFIFO =
 163                 AMDGPU_RAS_BLOCK__GFX_TA_INDEX_START,
 164         AMDGPU_RAS_BLOCK__GFX_TA_FS_AFIFO,
 165         AMDGPU_RAS_BLOCK__GFX_TA_FL_LFIFO,
 166         AMDGPU_RAS_BLOCK__GFX_TA_FX_LFIFO,
 167         AMDGPU_RAS_BLOCK__GFX_TA_FS_CFIFO,
 168         AMDGPU_RAS_BLOCK__GFX_TA_INDEX_END = AMDGPU_RAS_BLOCK__GFX_TA_FS_CFIFO,
 169         /* TCA */
 170         AMDGPU_RAS_BLOCK__GFX_TCA_INDEX_START,
 171         AMDGPU_RAS_BLOCK__GFX_TCA_HOLE_FIFO =
 172                 AMDGPU_RAS_BLOCK__GFX_TCA_INDEX_START,
 173         AMDGPU_RAS_BLOCK__GFX_TCA_REQ_FIFO,
 174         AMDGPU_RAS_BLOCK__GFX_TCA_INDEX_END =
 175                 AMDGPU_RAS_BLOCK__GFX_TCA_REQ_FIFO,
 176         /* TCC (5 sub-ranges) */
 177         AMDGPU_RAS_BLOCK__GFX_TCC_INDEX_START,
 178         /* TCC range 0 */
 179         AMDGPU_RAS_BLOCK__GFX_TCC_INDEX0_START =
 180                 AMDGPU_RAS_BLOCK__GFX_TCC_INDEX_START,
 181         AMDGPU_RAS_BLOCK__GFX_TCC_CACHE_DATA =
 182                 AMDGPU_RAS_BLOCK__GFX_TCC_INDEX0_START,
 183         AMDGPU_RAS_BLOCK__GFX_TCC_CACHE_DATA_BANK_0_1,
 184         AMDGPU_RAS_BLOCK__GFX_TCC_CACHE_DATA_BANK_1_0,
 185         AMDGPU_RAS_BLOCK__GFX_TCC_CACHE_DATA_BANK_1_1,
 186         AMDGPU_RAS_BLOCK__GFX_TCC_CACHE_DIRTY_BANK_0,
 187         AMDGPU_RAS_BLOCK__GFX_TCC_CACHE_DIRTY_BANK_1,
 188         AMDGPU_RAS_BLOCK__GFX_TCC_HIGH_RATE_TAG,
 189         AMDGPU_RAS_BLOCK__GFX_TCC_LOW_RATE_TAG,
 190         AMDGPU_RAS_BLOCK__GFX_TCC_INDEX0_END =
 191                 AMDGPU_RAS_BLOCK__GFX_TCC_LOW_RATE_TAG,
 192         /* TCC range 1 */
 193         AMDGPU_RAS_BLOCK__GFX_TCC_INDEX1_START,
 194         AMDGPU_RAS_BLOCK__GFX_TCC_IN_USE_DEC =
 195                 AMDGPU_RAS_BLOCK__GFX_TCC_INDEX1_START,
 196         AMDGPU_RAS_BLOCK__GFX_TCC_IN_USE_TRANSFER,
 197         AMDGPU_RAS_BLOCK__GFX_TCC_INDEX1_END =
 198                 AMDGPU_RAS_BLOCK__GFX_TCC_IN_USE_TRANSFER,
 199         /* TCC range 2 */
 200         AMDGPU_RAS_BLOCK__GFX_TCC_INDEX2_START,
 201         AMDGPU_RAS_BLOCK__GFX_TCC_RETURN_DATA =
 202                 AMDGPU_RAS_BLOCK__GFX_TCC_INDEX2_START,
 203         AMDGPU_RAS_BLOCK__GFX_TCC_RETURN_CONTROL,
 204         AMDGPU_RAS_BLOCK__GFX_TCC_UC_ATOMIC_FIFO,
 205         AMDGPU_RAS_BLOCK__GFX_TCC_WRITE_RETURN,
 206         AMDGPU_RAS_BLOCK__GFX_TCC_WRITE_CACHE_READ,
 207         AMDGPU_RAS_BLOCK__GFX_TCC_SRC_FIFO,
 208         AMDGPU_RAS_BLOCK__GFX_TCC_SRC_FIFO_NEXT_RAM,
 209         AMDGPU_RAS_BLOCK__GFX_TCC_CACHE_TAG_PROBE_FIFO,
 210         AMDGPU_RAS_BLOCK__GFX_TCC_INDEX2_END =
 211                 AMDGPU_RAS_BLOCK__GFX_TCC_CACHE_TAG_PROBE_FIFO,
 212         /* TCC range 3 */
 213         AMDGPU_RAS_BLOCK__GFX_TCC_INDEX3_START,
 214         AMDGPU_RAS_BLOCK__GFX_TCC_LATENCY_FIFO =
 215                 AMDGPU_RAS_BLOCK__GFX_TCC_INDEX3_START,
 216         AMDGPU_RAS_BLOCK__GFX_TCC_LATENCY_FIFO_NEXT_RAM,
 217         AMDGPU_RAS_BLOCK__GFX_TCC_INDEX3_END =
 218                 AMDGPU_RAS_BLOCK__GFX_TCC_LATENCY_FIFO_NEXT_RAM,
 219         /* TCC range 4 */
 220         AMDGPU_RAS_BLOCK__GFX_TCC_INDEX4_START,
 221         AMDGPU_RAS_BLOCK__GFX_TCC_WRRET_TAG_WRITE_RETURN =
 222                 AMDGPU_RAS_BLOCK__GFX_TCC_INDEX4_START,
 223         AMDGPU_RAS_BLOCK__GFX_TCC_ATOMIC_RETURN_BUFFER,
 224         AMDGPU_RAS_BLOCK__GFX_TCC_INDEX4_END =
 225                 AMDGPU_RAS_BLOCK__GFX_TCC_ATOMIC_RETURN_BUFFER,
 226         AMDGPU_RAS_BLOCK__GFX_TCC_INDEX_END =
 227                 AMDGPU_RAS_BLOCK__GFX_TCC_INDEX4_END,
 228         /* TCI */
 229         AMDGPU_RAS_BLOCK__GFX_TCI_WRITE_RAM,
 230         /* TCP */
 231         AMDGPU_RAS_BLOCK__GFX_TCP_INDEX_START,
 232         AMDGPU_RAS_BLOCK__GFX_TCP_CACHE_RAM =
 233                 AMDGPU_RAS_BLOCK__GFX_TCP_INDEX_START,
 234         AMDGPU_RAS_BLOCK__GFX_TCP_LFIFO_RAM,
 235         AMDGPU_RAS_BLOCK__GFX_TCP_CMD_FIFO,
 236         AMDGPU_RAS_BLOCK__GFX_TCP_VM_FIFO,
 237         AMDGPU_RAS_BLOCK__GFX_TCP_DB_RAM,
 238         AMDGPU_RAS_BLOCK__GFX_TCP_UTCL1_LFIFO0,
 239         AMDGPU_RAS_BLOCK__GFX_TCP_UTCL1_LFIFO1,
 240         AMDGPU_RAS_BLOCK__GFX_TCP_INDEX_END =
 241                 AMDGPU_RAS_BLOCK__GFX_TCP_UTCL1_LFIFO1,
 242         /* TD */
 243         AMDGPU_RAS_BLOCK__GFX_TD_INDEX_START,
 244         AMDGPU_RAS_BLOCK__GFX_TD_SS_FIFO_LO =
 245                 AMDGPU_RAS_BLOCK__GFX_TD_INDEX_START,
 246         AMDGPU_RAS_BLOCK__GFX_TD_SS_FIFO_HI,
 247         AMDGPU_RAS_BLOCK__GFX_TD_CS_FIFO,
 248         AMDGPU_RAS_BLOCK__GFX_TD_INDEX_END = AMDGPU_RAS_BLOCK__GFX_TD_CS_FIFO,
 249         /* EA (3 sub-ranges) */
 250         AMDGPU_RAS_BLOCK__GFX_EA_INDEX_START,
 251         /* EA range 0 */
 252         AMDGPU_RAS_BLOCK__GFX_EA_INDEX0_START =
 253                 AMDGPU_RAS_BLOCK__GFX_EA_INDEX_START,
 254         AMDGPU_RAS_BLOCK__GFX_EA_DRAMRD_CMDMEM =
 255                 AMDGPU_RAS_BLOCK__GFX_EA_INDEX0_START,
 256         AMDGPU_RAS_BLOCK__GFX_EA_DRAMWR_CMDMEM,
 257         AMDGPU_RAS_BLOCK__GFX_EA_DRAMWR_DATAMEM,
 258         AMDGPU_RAS_BLOCK__GFX_EA_RRET_TAGMEM,
 259         AMDGPU_RAS_BLOCK__GFX_EA_WRET_TAGMEM,
 260         AMDGPU_RAS_BLOCK__GFX_EA_GMIRD_CMDMEM,
 261         AMDGPU_RAS_BLOCK__GFX_EA_GMIWR_CMDMEM,
 262         AMDGPU_RAS_BLOCK__GFX_EA_GMIWR_DATAMEM,
 263         AMDGPU_RAS_BLOCK__GFX_EA_INDEX0_END =
 264                 AMDGPU_RAS_BLOCK__GFX_EA_GMIWR_DATAMEM,
 265         /* EA range 1 */
 266         AMDGPU_RAS_BLOCK__GFX_EA_INDEX1_START,
 267         AMDGPU_RAS_BLOCK__GFX_EA_DRAMRD_PAGEMEM =
 268                 AMDGPU_RAS_BLOCK__GFX_EA_INDEX1_START,
 269         AMDGPU_RAS_BLOCK__GFX_EA_DRAMWR_PAGEMEM,
 270         AMDGPU_RAS_BLOCK__GFX_EA_IORD_CMDMEM,
 271         AMDGPU_RAS_BLOCK__GFX_EA_IOWR_CMDMEM,
 272         AMDGPU_RAS_BLOCK__GFX_EA_IOWR_DATAMEM,
 273         AMDGPU_RAS_BLOCK__GFX_EA_GMIRD_PAGEMEM,
 274         AMDGPU_RAS_BLOCK__GFX_EA_GMIWR_PAGEMEM,
 275         AMDGPU_RAS_BLOCK__GFX_EA_INDEX1_END =
 276                 AMDGPU_RAS_BLOCK__GFX_EA_GMIWR_PAGEMEM,
 277         /* EA range 2 */
 278         AMDGPU_RAS_BLOCK__GFX_EA_INDEX2_START,
 279         AMDGPU_RAS_BLOCK__GFX_EA_MAM_D0MEM =
 280                 AMDGPU_RAS_BLOCK__GFX_EA_INDEX2_START,
 281         AMDGPU_RAS_BLOCK__GFX_EA_MAM_D1MEM,
 282         AMDGPU_RAS_BLOCK__GFX_EA_MAM_D2MEM,
 283         AMDGPU_RAS_BLOCK__GFX_EA_MAM_D3MEM,
 284         AMDGPU_RAS_BLOCK__GFX_EA_INDEX2_END =
 285                 AMDGPU_RAS_BLOCK__GFX_EA_MAM_D3MEM,
 286         AMDGPU_RAS_BLOCK__GFX_EA_INDEX_END =
 287                 AMDGPU_RAS_BLOCK__GFX_EA_INDEX2_END,
 288         /* UTC VM L2 bank */
 289         AMDGPU_RAS_BLOCK__UTC_VML2_BANK_CACHE,
 290         /* UTC VM walker */
 291         AMDGPU_RAS_BLOCK__UTC_VML2_WALKER,
 292         /* UTC ATC L2 2MB cache */
 293         AMDGPU_RAS_BLOCK__UTC_ATCL2_CACHE_2M_BANK,
 294         /* UTC ATC L2 4KB cache */
 295         AMDGPU_RAS_BLOCK__UTC_ATCL2_CACHE_4K_BANK,
 296         AMDGPU_RAS_BLOCK__GFX_MAX
 297 };
 298
 299 enum amdgpu_ras_error_type {
 300         AMDGPU_RAS_ERROR__NONE                                                  = 0,
 301         AMDGPU_RAS_ERROR__PARITY                                                = 1,
 302         AMDGPU_RAS_ERROR__SINGLE_CORRECTABLE                                    = 2,
 303         AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE                                   = 4,
 304         AMDGPU_RAS_ERROR__POISON                                                = 8,
 305 };
 306
 307 enum amdgpu_ras_ret {
 308         AMDGPU_RAS_SUCCESS = 0,
 309         AMDGPU_RAS_FAIL,
 310         AMDGPU_RAS_UE,
 311         AMDGPU_RAS_CE,
 312         AMDGPU_RAS_PT,
 313 };
 314
 315 struct ras_common_if {
 316         enum amdgpu_ras_block block;
 317         enum amdgpu_ras_error_type type;
 318         uint32_t sub_block_index;
 319         char name[32];
 320 };
 321
 322 struct amdgpu_ras {
 323         /* ras infrastructure */
 324         /* for ras itself. */
 325         uint32_t features;
 326         struct list_head head;
 327         /* sysfs */
 328         struct device_attribute features_attr;
 329         struct bin_attribute badpages_attr;
 330         struct dentry *de_ras_eeprom_table;
 331         /* block array */
 332         struct ras_manager *objs;
 333
 334         /* gpu recovery */
 335         struct work_struct recovery_work;
 336         atomic_t in_recovery;
 337         struct amdgpu_device *adev;
 338         /* error handler data */
 339         struct ras_err_handler_data *eh_data;
 340         struct mutex recovery_lock;
 341
 342         uint32_t flags;
 343         bool reboot;
 344         struct amdgpu_ras_eeprom_control eeprom_control;
 345
 346         bool error_query_ready;
 347
 348         /* bad page count threshold */
 349         uint32_t bad_page_cnt_threshold;
 350
 351         /* disable ras error count harvest in recovery */
 352         bool disable_ras_err_cnt_harvest;
 353
 354         /* is poison mode supported */
 355         bool poison_supported;
 356
 357         /* RAS count errors delayed work */
 358         struct delayed_work ras_counte_delay_work;
 359         atomic_t ras_ue_count;
 360         atomic_t ras_ce_count;
 361 };
 362
 363 struct ras_fs_data {
 364         char sysfs_name[32];
 365         char debugfs_name[32];
 366 };
 367
 368 struct ras_err_data {
 369         unsigned long ue_count;
 370         unsigned long ce_count;
 371         unsigned long err_addr_cnt;
 372         struct eeprom_table_record *err_addr;
 373 };
 374
 375 struct ras_err_handler_data {
 376         /* point to bad page records array */
 377         struct eeprom_table_record *bps;
 378         /* the count of entries */
 379         int count;
 380         /* the space can place new entries */
 381         int space_left;
 382 };
 383
 384 typedef int (*ras_ih_cb)(struct amdgpu_device *adev,
 385                 void *err_data,
 386                 struct amdgpu_iv_entry *entry);
 387
 388 struct ras_ih_data {
 389         /* interrupt bottom half */
 390         struct work_struct ih_work;
 391         int inuse;
 392         /* IP callback */
 393         ras_ih_cb cb;
 394         /* full of entries */
 395         unsigned char *ring;
 396         unsigned int ring_size;
 397         unsigned int element_size;
 398         unsigned int aligned_element_size;
 399         unsigned int rptr;
 400         unsigned int wptr;
 401 };
 402
 403 struct ras_manager {
 404         struct ras_common_if head;
 405         /* reference count */
 406         int use;
 407         /* ras block link */
 408         struct list_head node;
 409         /* the device */
 410         struct amdgpu_device *adev;
 411         /* sysfs */
 412         struct device_attribute sysfs_attr;
 413         int attr_inuse;
 414
 415         /* fs node name */
 416         struct ras_fs_data fs_data;
 417
 418         /* IH data */
 419         struct ras_ih_data ih_data;
 420
 421         struct ras_err_data err_data;
 422 };
 423
 424 struct ras_badpage {
 425         unsigned int bp;
 426         unsigned int size;
 427         unsigned int flags;
 428 };
 429
 430 /* interfaces for IP */
 431 struct ras_fs_if {
 432         struct ras_common_if head;
 433         const char* sysfs_name;
 434         char debugfs_name[32];
 435 };
 436
 437 struct ras_query_if {
 438         struct ras_common_if head;
 439         unsigned long ue_count;
 440         unsigned long ce_count;
 441 };
 442
 443 struct ras_inject_if {
 444         struct ras_common_if head;
 445         uint64_t address;
 446         uint64_t value;
 447 };
 448
 449 struct ras_cure_if {
 450         struct ras_common_if head;
 451         uint64_t address;
 452 };
 453
 454 struct ras_ih_if {
 455         struct ras_common_if head;
 456         ras_ih_cb cb;
 457 };
 458
 459 struct ras_dispatch_if {
 460         struct ras_common_if head;
 461         struct amdgpu_iv_entry *entry;
 462 };
 463
 464 struct ras_debug_if {
 465         union {
 466                 struct ras_common_if head;
 467                 struct ras_inject_if inject;
 468         };
 469         int op;
 470 };
 471 /* work flow
 472  * vbios
 473  * 1: ras feature enable (enabled by default)
 474  * psp
 475  * 2: ras framework init (in ip_init)
 476  * IP
 477  * 3: IH add
 478  * 4: debugfs/sysfs create
 479  * 5: query/inject
 480  * 6: debugfs/sysfs remove
 481  * 7: IH remove
 482  * 8: feature disable
 483  */
 484
 485 #define amdgpu_ras_get_context(adev)            ((adev)->psp.ras_context.ras)
 486 #define amdgpu_ras_set_context(adev, ras_con)   ((adev)->psp.ras_context.ras = (ras_con))
 487
 488 /* check if ras is supported on block, say, sdma, gfx */
 489 static inline int amdgpu_ras_is_supported(struct amdgpu_device *adev,
 490                 unsigned int block)
 491 {
 492         struct amdgpu_ras *ras = amdgpu_ras_get_context(adev);
 493
 494         if (block >= AMDGPU_RAS_BLOCK_COUNT)
 495                 return 0;
 496         return ras && (adev->ras_enabled & (1 << block));
 497 }
 498
 499 int amdgpu_ras_recovery_init(struct amdgpu_device *adev);
 500
 501 void amdgpu_ras_resume(struct amdgpu_device *adev);
 502 void amdgpu_ras_suspend(struct amdgpu_device *adev);
 503
 504 int amdgpu_ras_query_error_count(struct amdgpu_device *adev,
 505                                  unsigned long *ce_count,
 506                                  unsigned long *ue_count);
 507
 508 /* error handling functions */
 509 int amdgpu_ras_add_bad_pages(struct amdgpu_device *adev,
 510                 struct eeprom_table_record *bps, int pages);
 511
 512 int amdgpu_ras_save_bad_pages(struct amdgpu_device *adev);
 513
 514 static inline int amdgpu_ras_reset_gpu(struct amdgpu_device *adev)
 515 {
 516         struct amdgpu_ras *ras = amdgpu_ras_get_context(adev);
 517
 518         if (atomic_cmpxchg(&ras->in_recovery, 0, 1) == 0)
 519                 schedule_work(&ras->recovery_work);
 520         return 0;
 521 }
 522
 523 static inline enum ta_ras_block
 524 amdgpu_ras_block_to_ta(enum amdgpu_ras_block block) {
 525         switch (block) {
 526         case AMDGPU_RAS_BLOCK__UMC:
 527                 return TA_RAS_BLOCK__UMC;
 528         case AMDGPU_RAS_BLOCK__SDMA:
 529                 return TA_RAS_BLOCK__SDMA;
 530         case AMDGPU_RAS_BLOCK__GFX:
 531                 return TA_RAS_BLOCK__GFX;
 532         case AMDGPU_RAS_BLOCK__MMHUB:
 533                 return TA_RAS_BLOCK__MMHUB;
 534         case AMDGPU_RAS_BLOCK__ATHUB:
 535                 return TA_RAS_BLOCK__ATHUB;
 536         case AMDGPU_RAS_BLOCK__PCIE_BIF:
 537                 return TA_RAS_BLOCK__PCIE_BIF;
 538         case AMDGPU_RAS_BLOCK__HDP:
 539                 return TA_RAS_BLOCK__HDP;
 540         case AMDGPU_RAS_BLOCK__XGMI_WAFL:
 541                 return TA_RAS_BLOCK__XGMI_WAFL;
 542         case AMDGPU_RAS_BLOCK__DF:
 543                 return TA_RAS_BLOCK__DF;
 544         case AMDGPU_RAS_BLOCK__SMN:
 545                 return TA_RAS_BLOCK__SMN;
 546         case AMDGPU_RAS_BLOCK__SEM:
 547                 return TA_RAS_BLOCK__SEM;
 548         case AMDGPU_RAS_BLOCK__MP0:
 549                 return TA_RAS_BLOCK__MP0;
 550         case AMDGPU_RAS_BLOCK__MP1:
 551                 return TA_RAS_BLOCK__MP1;
 552         case AMDGPU_RAS_BLOCK__FUSE:
 553                 return TA_RAS_BLOCK__FUSE;
 554         case AMDGPU_RAS_BLOCK__MCA:
 555                 return TA_RAS_BLOCK__MCA;
 556         default:
 557                 WARN_ONCE(1, "RAS ERROR: unexpected block id %d\n", block);
 558                 return TA_RAS_BLOCK__UMC;
 559         }
 560 }
 561
 562 static inline enum ta_ras_error_type
 563 amdgpu_ras_error_to_ta(enum amdgpu_ras_error_type error) {
 564         switch (error) {
 565         case AMDGPU_RAS_ERROR__NONE:
 566                 return TA_RAS_ERROR__NONE;
 567         case AMDGPU_RAS_ERROR__PARITY:
 568                 return TA_RAS_ERROR__PARITY;
 569         case AMDGPU_RAS_ERROR__SINGLE_CORRECTABLE:
 570                 return TA_RAS_ERROR__SINGLE_CORRECTABLE;
 571         case AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE:
 572                 return TA_RAS_ERROR__MULTI_UNCORRECTABLE;
 573         case AMDGPU_RAS_ERROR__POISON:
 574                 return TA_RAS_ERROR__POISON;
 575         default:
 576                 WARN_ONCE(1, "RAS ERROR: unexpected error type %d\n", error);
 577                 return TA_RAS_ERROR__NONE;
 578         }
 579 }
 580
 581 /* called in ip_init and ip_fini */
 582 int amdgpu_ras_init(struct amdgpu_device *adev);
 583 int amdgpu_ras_fini(struct amdgpu_device *adev);
 584 int amdgpu_ras_pre_fini(struct amdgpu_device *adev);
 585 int amdgpu_ras_late_init(struct amdgpu_device *adev,
 586                          struct ras_common_if *ras_block,
 587                          struct ras_fs_if *fs_info,
 588                          struct ras_ih_if *ih_info);
 589 void amdgpu_ras_late_fini(struct amdgpu_device *adev,
 590                           struct ras_common_if *ras_block,
 591                           struct ras_ih_if *ih_info);
 592
 593 int amdgpu_ras_feature_enable(struct amdgpu_device *adev,
 594                 struct ras_common_if *head, bool enable);
 595
 596 int amdgpu_ras_feature_enable_on_boot(struct amdgpu_device *adev,
 597                 struct ras_common_if *head, bool enable);
 598
 599 int amdgpu_ras_sysfs_create(struct amdgpu_device *adev,
 600                 struct ras_fs_if *head);
 601
 602 int amdgpu_ras_sysfs_remove(struct amdgpu_device *adev,
 603                 struct ras_common_if *head);
 604
 605 void amdgpu_ras_debugfs_create_all(struct amdgpu_device *adev);
 606
 607 int amdgpu_ras_query_error_status(struct amdgpu_device *adev,
 608                 struct ras_query_if *info);
 609
 610 int amdgpu_ras_reset_error_status(struct amdgpu_device *adev,
 611                 enum amdgpu_ras_block block);
 612
 613 int amdgpu_ras_error_inject(struct amdgpu_device *adev,
 614                 struct ras_inject_if *info);
 615
 616 int amdgpu_ras_interrupt_add_handler(struct amdgpu_device *adev,
 617                 struct ras_ih_if *info);
 618
 619 int amdgpu_ras_interrupt_remove_handler(struct amdgpu_device *adev,
 620                 struct ras_ih_if *info);
 621
 622 int amdgpu_ras_interrupt_dispatch(struct amdgpu_device *adev,
 623                 struct ras_dispatch_if *info);
 624
 625 struct ras_manager *amdgpu_ras_find_obj(struct amdgpu_device *adev,
 626                 struct ras_common_if *head);
 627
 628 extern atomic_t amdgpu_ras_in_intr;
 629
 630 static inline bool amdgpu_ras_intr_triggered(void)
 631 {
 632         return !!atomic_read(&amdgpu_ras_in_intr);
 633 }
 634
 635 static inline void amdgpu_ras_intr_cleared(void)
 636 {
 637         atomic_set(&amdgpu_ras_in_intr, 0);
 638 }
 639
 640 void amdgpu_ras_global_ras_isr(struct amdgpu_device *adev);
 641
 642 void amdgpu_ras_set_error_query_ready(struct amdgpu_device *adev, bool ready);
 643
 644 bool amdgpu_ras_need_emergency_restart(struct amdgpu_device *adev);
 645
 646 void amdgpu_release_ras_context(struct amdgpu_device *adev);
 647
 648 int amdgpu_persistent_edc_harvesting_supported(struct amdgpu_device *adev);
 649
 650 const char *get_ras_block_str(struct ras_common_if *ras_block);
 651
 652 bool amdgpu_ras_is_poison_mode_supported(struct amdgpu_device *adev);
 653
 654 #endif