2 * Copyright 2018 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
24 #include <linux/debugfs.h>
25 #include <linux/list.h>
26 #include <linux/module.h>
27 #include <linux/uaccess.h>
28 #include <linux/reboot.h>
29 #include <linux/syscalls.h>
30 #include <linux/pm_runtime.h>
33 #include "amdgpu_ras.h"
34 #include "amdgpu_atomfirmware.h"
35 #include "amdgpu_xgmi.h"
36 #include "ivsrcid/nbio/irqsrcs_nbif_7_4.h"
37 #include "nbio_v4_3.h"
38 #include "nbio_v7_9.h"
40 #include "amdgpu_reset.h"
42 #ifdef CONFIG_X86_MCE_AMD
45 static bool notifier_registered;
47 static const char *RAS_FS_NAME = "ras";
49 const char *ras_error_string[] = {
53 "multi_uncorrectable",
57 const char *ras_block_string[] = {
77 const char *ras_mca_block_string[] = {
84 struct amdgpu_ras_block_list {
86 struct list_head node;
88 struct amdgpu_ras_block_object *ras_obj;
91 const char *get_ras_block_str(struct ras_common_if *ras_block)
96 if (ras_block->block >= AMDGPU_RAS_BLOCK_COUNT)
97 return "OUT OF RANGE";
99 if (ras_block->block == AMDGPU_RAS_BLOCK__MCA)
100 return ras_mca_block_string[ras_block->sub_block_index];
102 return ras_block_string[ras_block->block];
105 #define ras_block_str(_BLOCK_) \
106 (((_BLOCK_) < ARRAY_SIZE(ras_block_string)) ? ras_block_string[_BLOCK_] : "Out Of Range")
108 #define ras_err_str(i) (ras_error_string[ffs(i)])
110 #define RAS_DEFAULT_FLAGS (AMDGPU_RAS_FLAG_INIT_BY_VBIOS)
112 /* inject address is 52 bits */
113 #define RAS_UMC_INJECT_ADDR_LIMIT (0x1ULL << 52)
115 /* typical ECC bad page rate is 1 bad page per 100MB VRAM */
116 #define RAS_BAD_PAGE_COVER (100 * 1024 * 1024ULL)
118 enum amdgpu_ras_retire_page_reservation {
119 AMDGPU_RAS_RETIRE_PAGE_RESERVED,
120 AMDGPU_RAS_RETIRE_PAGE_PENDING,
121 AMDGPU_RAS_RETIRE_PAGE_FAULT,
124 atomic_t amdgpu_ras_in_intr = ATOMIC_INIT(0);
126 static bool amdgpu_ras_check_bad_page_unlock(struct amdgpu_ras *con,
128 static bool amdgpu_ras_check_bad_page(struct amdgpu_device *adev,
130 #ifdef CONFIG_X86_MCE_AMD
131 static void amdgpu_register_bad_pages_mca_notifier(struct amdgpu_device *adev);
132 struct mce_notifier_adev_list {
133 struct amdgpu_device *devs[MAX_GPU_INSTANCE];
136 static struct mce_notifier_adev_list mce_adev_list;
139 void amdgpu_ras_set_error_query_ready(struct amdgpu_device *adev, bool ready)
141 if (adev && amdgpu_ras_get_context(adev))
142 amdgpu_ras_get_context(adev)->error_query_ready = ready;
145 static bool amdgpu_ras_get_error_query_ready(struct amdgpu_device *adev)
147 if (adev && amdgpu_ras_get_context(adev))
148 return amdgpu_ras_get_context(adev)->error_query_ready;
153 static int amdgpu_reserve_page_direct(struct amdgpu_device *adev, uint64_t address)
155 struct ras_err_data err_data = {0, 0, 0, NULL};
156 struct eeprom_table_record err_rec;
158 if ((address >= adev->gmc.mc_vram_size) ||
159 (address >= RAS_UMC_INJECT_ADDR_LIMIT)) {
161 "RAS WARN: input address 0x%llx is invalid.\n",
166 if (amdgpu_ras_check_bad_page(adev, address)) {
168 "RAS WARN: 0x%llx has already been marked as bad page!\n",
173 memset(&err_rec, 0x0, sizeof(struct eeprom_table_record));
174 err_data.err_addr = &err_rec;
175 amdgpu_umc_fill_error_record(&err_data, address, address, 0, 0);
177 if (amdgpu_bad_page_threshold != 0) {
178 amdgpu_ras_add_bad_pages(adev, err_data.err_addr,
179 err_data.err_addr_cnt);
180 amdgpu_ras_save_bad_pages(adev, NULL);
183 dev_warn(adev->dev, "WARNING: THIS IS ONLY FOR TEST PURPOSES AND WILL CORRUPT RAS EEPROM\n");
184 dev_warn(adev->dev, "Clear EEPROM:\n");
185 dev_warn(adev->dev, " echo 1 > /sys/kernel/debug/dri/0/ras/ras_eeprom_reset\n");
190 static ssize_t amdgpu_ras_debugfs_read(struct file *f, char __user *buf,
191 size_t size, loff_t *pos)
193 struct ras_manager *obj = (struct ras_manager *)file_inode(f)->i_private;
194 struct ras_query_if info = {
200 if (amdgpu_ras_query_error_status(obj->adev, &info))
203 /* Hardware counter will be reset automatically after the query on Vega20 and Arcturus */
204 if (obj->adev->ip_versions[MP0_HWIP][0] != IP_VERSION(11, 0, 2) &&
205 obj->adev->ip_versions[MP0_HWIP][0] != IP_VERSION(11, 0, 4)) {
206 if (amdgpu_ras_reset_error_status(obj->adev, info.head.block))
207 dev_warn(obj->adev->dev, "Failed to reset error counter and error status");
210 s = snprintf(val, sizeof(val), "%s: %lu\n%s: %lu\n",
212 "ce", info.ce_count);
217 s = min_t(u64, s, size);
220 if (copy_to_user(buf, &val[*pos], s))
228 static const struct file_operations amdgpu_ras_debugfs_ops = {
229 .owner = THIS_MODULE,
230 .read = amdgpu_ras_debugfs_read,
232 .llseek = default_llseek
235 static int amdgpu_ras_find_block_id_by_name(const char *name, int *block_id)
239 for (i = 0; i < ARRAY_SIZE(ras_block_string); i++) {
241 if (strcmp(name, ras_block_string[i]) == 0)
247 static int amdgpu_ras_debugfs_ctrl_parse_data(struct file *f,
248 const char __user *buf, size_t size,
249 loff_t *pos, struct ras_debug_if *data)
251 ssize_t s = min_t(u64, 64, size);
259 /* default value is 0 if the mask is not set by user */
260 u32 instance_mask = 0;
266 memset(str, 0, sizeof(str));
267 memset(data, 0, sizeof(*data));
269 if (copy_from_user(str, buf, s))
272 if (sscanf(str, "disable %32s", block_name) == 1)
274 else if (sscanf(str, "enable %32s %8s", block_name, err) == 2)
276 else if (sscanf(str, "inject %32s %8s", block_name, err) == 2)
278 else if (strstr(str, "retire_page") != NULL)
280 else if (str[0] && str[1] && str[2] && str[3])
281 /* ascii string, but commands are not matched. */
286 if (sscanf(str, "%*s 0x%llx", &address) != 1 &&
287 sscanf(str, "%*s %llu", &address) != 1)
291 data->inject.address = address;
296 if (amdgpu_ras_find_block_id_by_name(block_name, &block_id))
299 data->head.block = block_id;
300 /* only ue and ce errors are supported */
301 if (!memcmp("ue", err, 2))
302 data->head.type = AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE;
303 else if (!memcmp("ce", err, 2))
304 data->head.type = AMDGPU_RAS_ERROR__SINGLE_CORRECTABLE;
311 if (sscanf(str, "%*s %*s %*s 0x%x 0x%llx 0x%llx 0x%x",
312 &sub_block, &address, &value, &instance_mask) != 4 &&
313 sscanf(str, "%*s %*s %*s %u %llu %llu %u",
314 &sub_block, &address, &value, &instance_mask) != 4 &&
315 sscanf(str, "%*s %*s %*s 0x%x 0x%llx 0x%llx",
316 &sub_block, &address, &value) != 3 &&
317 sscanf(str, "%*s %*s %*s %u %llu %llu",
318 &sub_block, &address, &value) != 3)
320 data->head.sub_block_index = sub_block;
321 data->inject.address = address;
322 data->inject.value = value;
323 data->inject.instance_mask = instance_mask;
326 if (size < sizeof(*data))
329 if (copy_from_user(data, buf, sizeof(*data)))
336 static void amdgpu_ras_instance_mask_check(struct amdgpu_device *adev,
337 struct ras_debug_if *data)
339 int num_xcc = adev->gfx.xcc_mask ? NUM_XCC(adev->gfx.xcc_mask) : 1;
340 uint32_t mask, inst_mask = data->inject.instance_mask;
342 /* no need to set instance mask if there is only one instance */
343 if (num_xcc <= 1 && inst_mask) {
344 data->inject.instance_mask = 0;
346 "RAS inject mask(0x%x) isn't supported and force it to 0.\n",
352 switch (data->head.block) {
353 case AMDGPU_RAS_BLOCK__GFX:
354 mask = GENMASK(num_xcc - 1, 0);
356 case AMDGPU_RAS_BLOCK__SDMA:
357 mask = GENMASK(adev->sdma.num_instances - 1, 0);
359 case AMDGPU_RAS_BLOCK__VCN:
360 case AMDGPU_RAS_BLOCK__JPEG:
361 mask = GENMASK(adev->vcn.num_vcn_inst - 1, 0);
368 /* remove invalid bits in instance mask */
369 data->inject.instance_mask &= mask;
370 if (inst_mask != data->inject.instance_mask)
372 "Adjust RAS inject mask 0x%x to 0x%x\n",
373 inst_mask, data->inject.instance_mask);
377 * DOC: AMDGPU RAS debugfs control interface
379 * The control interface accepts struct ras_debug_if which has two members.
381 * First member: ras_debug_if::head or ras_debug_if::inject.
383 * head is used to indicate which IP block will be under control.
385 * head has four members, they are block, type, sub_block_index, name.
386 * block: which IP will be under control.
387 * type: what kind of error will be enabled/disabled/injected.
388 * sub_block_index: some IPs have subcomponets. say, GFX, sDMA.
389 * name: the name of IP.
391 * inject has three more members than head, they are address, value and mask.
392 * As their names indicate, inject operation will write the
393 * value to the address.
395 * The second member: struct ras_debug_if::op.
396 * It has three kinds of operations.
398 * - 0: disable RAS on the block. Take ::head as its data.
399 * - 1: enable RAS on the block. Take ::head as its data.
400 * - 2: inject errors on the block. Take ::inject as its data.
402 * How to use the interface?
406 * Copy the struct ras_debug_if in your code and initialize it.
407 * Write the struct to the control interface.
411 * .. code-block:: bash
413 * echo "disable <block>" > /sys/kernel/debug/dri/<N>/ras/ras_ctrl
414 * echo "enable <block> <error>" > /sys/kernel/debug/dri/<N>/ras/ras_ctrl
415 * echo "inject <block> <error> <sub-block> <address> <value> <mask>" > /sys/kernel/debug/dri/<N>/ras/ras_ctrl
417 * Where N, is the card which you want to affect.
419 * "disable" requires only the block.
420 * "enable" requires the block and error type.
421 * "inject" requires the block, error type, address, and value.
423 * The block is one of: umc, sdma, gfx, etc.
424 * see ras_block_string[] for details
426 * The error type is one of: ue, ce, where,
427 * ue is multi-uncorrectable
428 * ce is single-correctable
430 * The sub-block is a the sub-block index, pass 0 if there is no sub-block.
431 * The address and value are hexadecimal numbers, leading 0x is optional.
432 * The mask means instance mask, is optional, default value is 0x1.
436 * .. code-block:: bash
438 * echo inject umc ue 0x0 0x0 0x0 > /sys/kernel/debug/dri/0/ras/ras_ctrl
439 * echo inject umc ce 0 0 0 3 > /sys/kernel/debug/dri/0/ras/ras_ctrl
440 * echo disable umc > /sys/kernel/debug/dri/0/ras/ras_ctrl
442 * How to check the result of the operation?
444 * To check disable/enable, see "ras" features at,
445 * /sys/class/drm/card[0/1/2...]/device/ras/features
447 * To check inject, see the corresponding error count at,
448 * /sys/class/drm/card[0/1/2...]/device/ras/[gfx|sdma|umc|...]_err_count
451 * Operations are only allowed on blocks which are supported.
452 * Check the "ras" mask at /sys/module/amdgpu/parameters/ras_mask
453 * to see which blocks support RAS on a particular asic.
456 static ssize_t amdgpu_ras_debugfs_ctrl_write(struct file *f,
457 const char __user *buf,
458 size_t size, loff_t *pos)
460 struct amdgpu_device *adev = (struct amdgpu_device *)file_inode(f)->i_private;
461 struct ras_debug_if data;
464 if (!amdgpu_ras_get_error_query_ready(adev)) {
465 dev_warn(adev->dev, "RAS WARN: error injection "
466 "currently inaccessible\n");
470 ret = amdgpu_ras_debugfs_ctrl_parse_data(f, buf, size, pos, &data);
475 ret = amdgpu_reserve_page_direct(adev, data.inject.address);
482 if (!amdgpu_ras_is_supported(adev, data.head.block))
487 ret = amdgpu_ras_feature_enable(adev, &data.head, 0);
490 ret = amdgpu_ras_feature_enable(adev, &data.head, 1);
493 if ((data.inject.address >= adev->gmc.mc_vram_size &&
494 adev->gmc.mc_vram_size) ||
495 (data.inject.address >= RAS_UMC_INJECT_ADDR_LIMIT)) {
496 dev_warn(adev->dev, "RAS WARN: input address "
497 "0x%llx is invalid.",
498 data.inject.address);
503 /* umc ce/ue error injection for a bad page is not allowed */
504 if ((data.head.block == AMDGPU_RAS_BLOCK__UMC) &&
505 amdgpu_ras_check_bad_page(adev, data.inject.address)) {
506 dev_warn(adev->dev, "RAS WARN: inject: 0x%llx has "
507 "already been marked as bad!\n",
508 data.inject.address);
512 amdgpu_ras_instance_mask_check(adev, &data);
514 /* data.inject.address is offset instead of absolute gpu address */
515 ret = amdgpu_ras_error_inject(adev, &data.inject);
529 * DOC: AMDGPU RAS debugfs EEPROM table reset interface
531 * Some boards contain an EEPROM which is used to persistently store a list of
532 * bad pages which experiences ECC errors in vram. This interface provides
533 * a way to reset the EEPROM, e.g., after testing error injection.
537 * .. code-block:: bash
539 * echo 1 > ../ras/ras_eeprom_reset
541 * will reset EEPROM table to 0 entries.
544 static ssize_t amdgpu_ras_debugfs_eeprom_write(struct file *f,
545 const char __user *buf,
546 size_t size, loff_t *pos)
548 struct amdgpu_device *adev =
549 (struct amdgpu_device *)file_inode(f)->i_private;
552 ret = amdgpu_ras_eeprom_reset_table(
553 &(amdgpu_ras_get_context(adev)->eeprom_control));
556 /* Something was written to EEPROM.
558 amdgpu_ras_get_context(adev)->flags = RAS_DEFAULT_FLAGS;
565 static const struct file_operations amdgpu_ras_debugfs_ctrl_ops = {
566 .owner = THIS_MODULE,
568 .write = amdgpu_ras_debugfs_ctrl_write,
569 .llseek = default_llseek
572 static const struct file_operations amdgpu_ras_debugfs_eeprom_ops = {
573 .owner = THIS_MODULE,
575 .write = amdgpu_ras_debugfs_eeprom_write,
576 .llseek = default_llseek
580 * DOC: AMDGPU RAS sysfs Error Count Interface
582 * It allows the user to read the error count for each IP block on the gpu through
583 * /sys/class/drm/card[0/1/2...]/device/ras/[gfx/sdma/...]_err_count
585 * It outputs the multiple lines which report the uncorrected (ue) and corrected
588 * The format of one line is below,
594 * .. code-block:: bash
600 static ssize_t amdgpu_ras_sysfs_read(struct device *dev,
601 struct device_attribute *attr, char *buf)
603 struct ras_manager *obj = container_of(attr, struct ras_manager, sysfs_attr);
604 struct ras_query_if info = {
608 if (!amdgpu_ras_get_error_query_ready(obj->adev))
609 return sysfs_emit(buf, "Query currently inaccessible\n");
611 if (amdgpu_ras_query_error_status(obj->adev, &info))
614 if (obj->adev->ip_versions[MP0_HWIP][0] != IP_VERSION(11, 0, 2) &&
615 obj->adev->ip_versions[MP0_HWIP][0] != IP_VERSION(11, 0, 4)) {
616 if (amdgpu_ras_reset_error_status(obj->adev, info.head.block))
617 dev_warn(obj->adev->dev, "Failed to reset error counter and error status");
620 return sysfs_emit(buf, "%s: %lu\n%s: %lu\n", "ue", info.ue_count,
621 "ce", info.ce_count);
626 #define get_obj(obj) do { (obj)->use++; } while (0)
627 #define alive_obj(obj) ((obj)->use)
629 static inline void put_obj(struct ras_manager *obj)
631 if (obj && (--obj->use == 0))
632 list_del(&obj->node);
633 if (obj && (obj->use < 0))
634 DRM_ERROR("RAS ERROR: Unbalance obj(%s) use\n", get_ras_block_str(&obj->head));
637 /* make one obj and return it. */
638 static struct ras_manager *amdgpu_ras_create_obj(struct amdgpu_device *adev,
639 struct ras_common_if *head)
641 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
642 struct ras_manager *obj;
644 if (!adev->ras_enabled || !con)
647 if (head->block >= AMDGPU_RAS_BLOCK_COUNT)
650 if (head->block == AMDGPU_RAS_BLOCK__MCA) {
651 if (head->sub_block_index >= AMDGPU_RAS_MCA_BLOCK__LAST)
654 obj = &con->objs[AMDGPU_RAS_BLOCK__LAST + head->sub_block_index];
656 obj = &con->objs[head->block];
658 /* already exist. return obj? */
664 list_add(&obj->node, &con->head);
670 /* return an obj equal to head, or the first when head is NULL */
671 struct ras_manager *amdgpu_ras_find_obj(struct amdgpu_device *adev,
672 struct ras_common_if *head)
674 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
675 struct ras_manager *obj;
678 if (!adev->ras_enabled || !con)
682 if (head->block >= AMDGPU_RAS_BLOCK_COUNT)
685 if (head->block == AMDGPU_RAS_BLOCK__MCA) {
686 if (head->sub_block_index >= AMDGPU_RAS_MCA_BLOCK__LAST)
689 obj = &con->objs[AMDGPU_RAS_BLOCK__LAST + head->sub_block_index];
691 obj = &con->objs[head->block];
696 for (i = 0; i < AMDGPU_RAS_BLOCK_COUNT + AMDGPU_RAS_MCA_BLOCK_COUNT; i++) {
707 /* feature ctl begin */
708 static int amdgpu_ras_is_feature_allowed(struct amdgpu_device *adev,
709 struct ras_common_if *head)
711 return adev->ras_hw_enabled & BIT(head->block);
714 static int amdgpu_ras_is_feature_enabled(struct amdgpu_device *adev,
715 struct ras_common_if *head)
717 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
719 return con->features & BIT(head->block);
723 * if obj is not created, then create one.
724 * set feature enable flag.
726 static int __amdgpu_ras_feature_enable(struct amdgpu_device *adev,
727 struct ras_common_if *head, int enable)
729 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
730 struct ras_manager *obj = amdgpu_ras_find_obj(adev, head);
732 /* If hardware does not support ras, then do not create obj.
733 * But if hardware support ras, we can create the obj.
734 * Ras framework checks con->hw_supported to see if it need do
735 * corresponding initialization.
736 * IP checks con->support to see if it need disable ras.
738 if (!amdgpu_ras_is_feature_allowed(adev, head))
743 obj = amdgpu_ras_create_obj(adev, head);
747 /* In case we create obj somewhere else */
750 con->features |= BIT(head->block);
752 if (obj && amdgpu_ras_is_feature_enabled(adev, head)) {
753 con->features &= ~BIT(head->block);
761 /* wrapper of psp_ras_enable_features */
762 int amdgpu_ras_feature_enable(struct amdgpu_device *adev,
763 struct ras_common_if *head, bool enable)
765 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
766 union ta_ras_cmd_input *info;
772 /* Do not enable ras feature if it is not allowed */
774 head->block != AMDGPU_RAS_BLOCK__GFX &&
775 !amdgpu_ras_is_feature_allowed(adev, head))
778 /* Only enable gfx ras feature from host side */
779 if (head->block == AMDGPU_RAS_BLOCK__GFX &&
780 !amdgpu_sriov_vf(adev) &&
781 !amdgpu_ras_intr_triggered()) {
782 info = kzalloc(sizeof(union ta_ras_cmd_input), GFP_KERNEL);
787 info->disable_features = (struct ta_ras_disable_features_input) {
788 .block_id = amdgpu_ras_block_to_ta(head->block),
789 .error_type = amdgpu_ras_error_to_ta(head->type),
792 info->enable_features = (struct ta_ras_enable_features_input) {
793 .block_id = amdgpu_ras_block_to_ta(head->block),
794 .error_type = amdgpu_ras_error_to_ta(head->type),
798 ret = psp_ras_enable_features(&adev->psp, info, enable);
800 dev_err(adev->dev, "ras %s %s failed poison:%d ret:%d\n",
801 enable ? "enable":"disable",
802 get_ras_block_str(head),
803 amdgpu_ras_is_poison_mode_supported(adev), ret);
812 __amdgpu_ras_feature_enable(adev, head, enable);
817 /* Only used in device probe stage and called only once. */
818 int amdgpu_ras_feature_enable_on_boot(struct amdgpu_device *adev,
819 struct ras_common_if *head, bool enable)
821 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
827 if (con->flags & AMDGPU_RAS_FLAG_INIT_BY_VBIOS) {
829 /* There is no harm to issue a ras TA cmd regardless of
830 * the currecnt ras state.
831 * If current state == target state, it will do nothing
832 * But sometimes it requests driver to reset and repost
833 * with error code -EAGAIN.
835 ret = amdgpu_ras_feature_enable(adev, head, 1);
836 /* With old ras TA, we might fail to enable ras.
837 * Log it and just setup the object.
838 * TODO need remove this WA in the future.
840 if (ret == -EINVAL) {
841 ret = __amdgpu_ras_feature_enable(adev, head, 1);
844 "RAS INFO: %s setup object\n",
845 get_ras_block_str(head));
848 /* setup the object then issue a ras TA disable cmd.*/
849 ret = __amdgpu_ras_feature_enable(adev, head, 1);
853 /* gfx block ras dsiable cmd must send to ras-ta */
854 if (head->block == AMDGPU_RAS_BLOCK__GFX)
855 con->features |= BIT(head->block);
857 ret = amdgpu_ras_feature_enable(adev, head, 0);
859 /* clean gfx block ras features flag */
860 if (adev->ras_enabled && head->block == AMDGPU_RAS_BLOCK__GFX)
861 con->features &= ~BIT(head->block);
864 ret = amdgpu_ras_feature_enable(adev, head, enable);
869 static int amdgpu_ras_disable_all_features(struct amdgpu_device *adev,
872 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
873 struct ras_manager *obj, *tmp;
875 list_for_each_entry_safe(obj, tmp, &con->head, node) {
877 * aka just release the obj and corresponding flags
880 if (__amdgpu_ras_feature_enable(adev, &obj->head, 0))
883 if (amdgpu_ras_feature_enable(adev, &obj->head, 0))
888 return con->features;
891 static int amdgpu_ras_enable_all_features(struct amdgpu_device *adev,
894 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
896 const enum amdgpu_ras_error_type default_ras_type = AMDGPU_RAS_ERROR__NONE;
898 for (i = 0; i < AMDGPU_RAS_BLOCK_COUNT; i++) {
899 struct ras_common_if head = {
901 .type = default_ras_type,
902 .sub_block_index = 0,
905 if (i == AMDGPU_RAS_BLOCK__MCA)
910 * bypass psp. vbios enable ras for us.
911 * so just create the obj
913 if (__amdgpu_ras_feature_enable(adev, &head, 1))
916 if (amdgpu_ras_feature_enable(adev, &head, 1))
921 for (i = 0; i < AMDGPU_RAS_MCA_BLOCK_COUNT; i++) {
922 struct ras_common_if head = {
923 .block = AMDGPU_RAS_BLOCK__MCA,
924 .type = default_ras_type,
925 .sub_block_index = i,
930 * bypass psp. vbios enable ras for us.
931 * so just create the obj
933 if (__amdgpu_ras_feature_enable(adev, &head, 1))
936 if (amdgpu_ras_feature_enable(adev, &head, 1))
941 return con->features;
943 /* feature ctl end */
945 static int amdgpu_ras_block_match_default(struct amdgpu_ras_block_object *block_obj,
946 enum amdgpu_ras_block block)
951 if (block_obj->ras_comm.block == block)
957 static struct amdgpu_ras_block_object *amdgpu_ras_get_ras_block(struct amdgpu_device *adev,
958 enum amdgpu_ras_block block, uint32_t sub_block_index)
960 struct amdgpu_ras_block_list *node, *tmp;
961 struct amdgpu_ras_block_object *obj;
963 if (block >= AMDGPU_RAS_BLOCK__LAST)
966 list_for_each_entry_safe(node, tmp, &adev->ras_list, node) {
967 if (!node->ras_obj) {
968 dev_warn(adev->dev, "Warning: abnormal ras list node.\n");
973 if (obj->ras_block_match) {
974 if (obj->ras_block_match(obj, block, sub_block_index) == 0)
977 if (amdgpu_ras_block_match_default(obj, block) == 0)
985 static void amdgpu_ras_get_ecc_info(struct amdgpu_device *adev, struct ras_err_data *err_data)
987 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev);
991 * choosing right query method according to
992 * whether smu support query error information
994 ret = amdgpu_dpm_get_ecc_info(adev, (void *)&(ras->umc_ecc));
995 if (ret == -EOPNOTSUPP) {
996 if (adev->umc.ras && adev->umc.ras->ras_block.hw_ops &&
997 adev->umc.ras->ras_block.hw_ops->query_ras_error_count)
998 adev->umc.ras->ras_block.hw_ops->query_ras_error_count(adev, err_data);
1000 /* umc query_ras_error_address is also responsible for clearing
1003 if (adev->umc.ras && adev->umc.ras->ras_block.hw_ops &&
1004 adev->umc.ras->ras_block.hw_ops->query_ras_error_address)
1005 adev->umc.ras->ras_block.hw_ops->query_ras_error_address(adev, err_data);
1007 if (adev->umc.ras &&
1008 adev->umc.ras->ecc_info_query_ras_error_count)
1009 adev->umc.ras->ecc_info_query_ras_error_count(adev, err_data);
1011 if (adev->umc.ras &&
1012 adev->umc.ras->ecc_info_query_ras_error_address)
1013 adev->umc.ras->ecc_info_query_ras_error_address(adev, err_data);
1017 /* query/inject/cure begin */
1018 int amdgpu_ras_query_error_status(struct amdgpu_device *adev,
1019 struct ras_query_if *info)
1021 struct amdgpu_ras_block_object *block_obj = NULL;
1022 struct ras_manager *obj = amdgpu_ras_find_obj(adev, &info->head);
1023 struct ras_err_data err_data = {0, 0, 0, NULL};
1028 if (info->head.block == AMDGPU_RAS_BLOCK__UMC) {
1029 amdgpu_ras_get_ecc_info(adev, &err_data);
1031 block_obj = amdgpu_ras_get_ras_block(adev, info->head.block, 0);
1032 if (!block_obj || !block_obj->hw_ops) {
1033 dev_dbg_once(adev->dev, "%s doesn't config RAS function\n",
1034 get_ras_block_str(&info->head));
1038 if (block_obj->hw_ops->query_ras_error_count)
1039 block_obj->hw_ops->query_ras_error_count(adev, &err_data);
1041 if ((info->head.block == AMDGPU_RAS_BLOCK__SDMA) ||
1042 (info->head.block == AMDGPU_RAS_BLOCK__GFX) ||
1043 (info->head.block == AMDGPU_RAS_BLOCK__MMHUB)) {
1044 if (block_obj->hw_ops->query_ras_error_status)
1045 block_obj->hw_ops->query_ras_error_status(adev);
1049 obj->err_data.ue_count += err_data.ue_count;
1050 obj->err_data.ce_count += err_data.ce_count;
1052 info->ue_count = obj->err_data.ue_count;
1053 info->ce_count = obj->err_data.ce_count;
1055 if (err_data.ce_count) {
1056 if (!adev->aid_mask &&
1057 adev->smuio.funcs &&
1058 adev->smuio.funcs->get_socket_id &&
1059 adev->smuio.funcs->get_die_id) {
1060 dev_info(adev->dev, "socket: %d, die: %d "
1061 "%ld correctable hardware errors "
1062 "detected in %s block, no user "
1063 "action is needed.\n",
1064 adev->smuio.funcs->get_socket_id(adev),
1065 adev->smuio.funcs->get_die_id(adev),
1066 obj->err_data.ce_count,
1067 get_ras_block_str(&info->head));
1069 dev_info(adev->dev, "%ld correctable hardware errors "
1070 "detected in %s block, no user "
1071 "action is needed.\n",
1072 obj->err_data.ce_count,
1073 get_ras_block_str(&info->head));
1076 if (err_data.ue_count) {
1077 if (!adev->aid_mask &&
1078 adev->smuio.funcs &&
1079 adev->smuio.funcs->get_socket_id &&
1080 adev->smuio.funcs->get_die_id) {
1081 dev_info(adev->dev, "socket: %d, die: %d "
1082 "%ld uncorrectable hardware errors "
1083 "detected in %s block\n",
1084 adev->smuio.funcs->get_socket_id(adev),
1085 adev->smuio.funcs->get_die_id(adev),
1086 obj->err_data.ue_count,
1087 get_ras_block_str(&info->head));
1089 dev_info(adev->dev, "%ld uncorrectable hardware errors "
1090 "detected in %s block\n",
1091 obj->err_data.ue_count,
1092 get_ras_block_str(&info->head));
1099 int amdgpu_ras_reset_error_status(struct amdgpu_device *adev,
1100 enum amdgpu_ras_block block)
1102 struct amdgpu_ras_block_object *block_obj = amdgpu_ras_get_ras_block(adev, block, 0);
1104 if (!amdgpu_ras_is_supported(adev, block))
1107 if (!block_obj || !block_obj->hw_ops) {
1108 dev_dbg_once(adev->dev, "%s doesn't config RAS function\n",
1109 ras_block_str(block));
1113 if (block_obj->hw_ops->reset_ras_error_count)
1114 block_obj->hw_ops->reset_ras_error_count(adev);
1116 if ((block == AMDGPU_RAS_BLOCK__GFX) ||
1117 (block == AMDGPU_RAS_BLOCK__MMHUB)) {
1118 if (block_obj->hw_ops->reset_ras_error_status)
1119 block_obj->hw_ops->reset_ras_error_status(adev);
1125 /* wrapper of psp_ras_trigger_error */
1126 int amdgpu_ras_error_inject(struct amdgpu_device *adev,
1127 struct ras_inject_if *info)
1129 struct ras_manager *obj = amdgpu_ras_find_obj(adev, &info->head);
1130 struct ta_ras_trigger_error_input block_info = {
1131 .block_id = amdgpu_ras_block_to_ta(info->head.block),
1132 .inject_error_type = amdgpu_ras_error_to_ta(info->head.type),
1133 .sub_block_index = info->head.sub_block_index,
1134 .address = info->address,
1135 .value = info->value,
1138 struct amdgpu_ras_block_object *block_obj = amdgpu_ras_get_ras_block(adev,
1140 info->head.sub_block_index);
1142 /* inject on guest isn't allowed, return success directly */
1143 if (amdgpu_sriov_vf(adev))
1149 if (!block_obj || !block_obj->hw_ops) {
1150 dev_dbg_once(adev->dev, "%s doesn't config RAS function\n",
1151 get_ras_block_str(&info->head));
1155 /* Calculate XGMI relative offset */
1156 if (adev->gmc.xgmi.num_physical_nodes > 1 &&
1157 info->head.block != AMDGPU_RAS_BLOCK__GFX) {
1158 block_info.address =
1159 amdgpu_xgmi_get_relative_phy_addr(adev,
1160 block_info.address);
1163 if (block_obj->hw_ops->ras_error_inject) {
1164 if (info->head.block == AMDGPU_RAS_BLOCK__GFX)
1165 ret = block_obj->hw_ops->ras_error_inject(adev, info, info->instance_mask);
1166 else /* Special ras_error_inject is defined (e.g: xgmi) */
1167 ret = block_obj->hw_ops->ras_error_inject(adev, &block_info,
1168 info->instance_mask);
1171 ret = psp_ras_trigger_error(&adev->psp, &block_info, info->instance_mask);
1175 dev_err(adev->dev, "ras inject %s failed %d\n",
1176 get_ras_block_str(&info->head), ret);
1182 * amdgpu_ras_query_error_count_helper -- Get error counter for specific IP
1183 * @adev: pointer to AMD GPU device
1184 * @ce_count: pointer to an integer to be set to the count of correctible errors.
1185 * @ue_count: pointer to an integer to be set to the count of uncorrectible errors.
1186 * @query_info: pointer to ras_query_if
1188 * Return 0 for query success or do nothing, otherwise return an error
1191 static int amdgpu_ras_query_error_count_helper(struct amdgpu_device *adev,
1192 unsigned long *ce_count,
1193 unsigned long *ue_count,
1194 struct ras_query_if *query_info)
1199 /* do nothing if query_info is not specified */
1202 ret = amdgpu_ras_query_error_status(adev, query_info);
1206 *ce_count += query_info->ce_count;
1207 *ue_count += query_info->ue_count;
1209 /* some hardware/IP supports read to clear
1210 * no need to explictly reset the err status after the query call */
1211 if (adev->ip_versions[MP0_HWIP][0] != IP_VERSION(11, 0, 2) &&
1212 adev->ip_versions[MP0_HWIP][0] != IP_VERSION(11, 0, 4)) {
1213 if (amdgpu_ras_reset_error_status(adev, query_info->head.block))
1215 "Failed to reset error counter and error status\n");
1222 * amdgpu_ras_query_error_count -- Get error counts of all IPs or specific IP
1223 * @adev: pointer to AMD GPU device
1224 * @ce_count: pointer to an integer to be set to the count of correctible errors.
1225 * @ue_count: pointer to an integer to be set to the count of uncorrectible
1227 * @query_info: pointer to ras_query_if if the query request is only for
1228 * specific ip block; if info is NULL, then the qurey request is for
1229 * all the ip blocks that support query ras error counters/status
1231 * If set, @ce_count or @ue_count, count and return the corresponding
1232 * error counts in those integer pointers. Return 0 if the device
1233 * supports RAS. Return -EOPNOTSUPP if the device doesn't support RAS.
1235 int amdgpu_ras_query_error_count(struct amdgpu_device *adev,
1236 unsigned long *ce_count,
1237 unsigned long *ue_count,
1238 struct ras_query_if *query_info)
1240 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1241 struct ras_manager *obj;
1242 unsigned long ce, ue;
1245 if (!adev->ras_enabled || !con)
1248 /* Don't count since no reporting.
1250 if (!ce_count && !ue_count)
1256 /* query all the ip blocks that support ras query interface */
1257 list_for_each_entry(obj, &con->head, node) {
1258 struct ras_query_if info = {
1262 ret = amdgpu_ras_query_error_count_helper(adev, &ce, &ue, &info);
1265 /* query specific ip block */
1266 ret = amdgpu_ras_query_error_count_helper(adev, &ce, &ue, query_info);
1280 /* query/inject/cure end */
1285 static int amdgpu_ras_badpages_read(struct amdgpu_device *adev,
1286 struct ras_badpage **bps, unsigned int *count);
1288 static char *amdgpu_ras_badpage_flags_str(unsigned int flags)
1291 case AMDGPU_RAS_RETIRE_PAGE_RESERVED:
1293 case AMDGPU_RAS_RETIRE_PAGE_PENDING:
1295 case AMDGPU_RAS_RETIRE_PAGE_FAULT:
1302 * DOC: AMDGPU RAS sysfs gpu_vram_bad_pages Interface
1304 * It allows user to read the bad pages of vram on the gpu through
1305 * /sys/class/drm/card[0/1/2...]/device/ras/gpu_vram_bad_pages
1307 * It outputs multiple lines, and each line stands for one gpu page.
1309 * The format of one line is below,
1310 * gpu pfn : gpu page size : flags
1312 * gpu pfn and gpu page size are printed in hex format.
1313 * flags can be one of below character,
1315 * R: reserved, this gpu page is reserved and not able to use.
1317 * P: pending for reserve, this gpu page is marked as bad, will be reserved
1318 * in next window of page_reserve.
1320 * F: unable to reserve. this gpu page can't be reserved due to some reasons.
1324 * .. code-block:: bash
1326 * 0x00000001 : 0x00001000 : R
1327 * 0x00000002 : 0x00001000 : P
1331 static ssize_t amdgpu_ras_sysfs_badpages_read(struct file *f,
1332 struct kobject *kobj, struct bin_attribute *attr,
1333 char *buf, loff_t ppos, size_t count)
1335 struct amdgpu_ras *con =
1336 container_of(attr, struct amdgpu_ras, badpages_attr);
1337 struct amdgpu_device *adev = con->adev;
1338 const unsigned int element_size =
1339 sizeof("0xabcdabcd : 0x12345678 : R\n") - 1;
1340 unsigned int start = div64_ul(ppos + element_size - 1, element_size);
1341 unsigned int end = div64_ul(ppos + count - 1, element_size);
1343 struct ras_badpage *bps = NULL;
1344 unsigned int bps_count = 0;
1346 memset(buf, 0, count);
1348 if (amdgpu_ras_badpages_read(adev, &bps, &bps_count))
1351 for (; start < end && start < bps_count; start++)
1352 s += scnprintf(&buf[s], element_size + 1,
1353 "0x%08x : 0x%08x : %1s\n",
1356 amdgpu_ras_badpage_flags_str(bps[start].flags));
1363 static ssize_t amdgpu_ras_sysfs_features_read(struct device *dev,
1364 struct device_attribute *attr, char *buf)
1366 struct amdgpu_ras *con =
1367 container_of(attr, struct amdgpu_ras, features_attr);
1369 return sysfs_emit(buf, "feature mask: 0x%x\n", con->features);
1372 static void amdgpu_ras_sysfs_remove_bad_page_node(struct amdgpu_device *adev)
1374 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1376 sysfs_remove_file_from_group(&adev->dev->kobj,
1377 &con->badpages_attr.attr,
1381 static int amdgpu_ras_sysfs_remove_feature_node(struct amdgpu_device *adev)
1383 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1384 struct attribute *attrs[] = {
1385 &con->features_attr.attr,
1388 struct attribute_group group = {
1389 .name = RAS_FS_NAME,
1393 sysfs_remove_group(&adev->dev->kobj, &group);
1398 int amdgpu_ras_sysfs_create(struct amdgpu_device *adev,
1399 struct ras_common_if *head)
1401 struct ras_manager *obj = amdgpu_ras_find_obj(adev, head);
1403 if (!obj || obj->attr_inuse)
1408 snprintf(obj->fs_data.sysfs_name, sizeof(obj->fs_data.sysfs_name),
1409 "%s_err_count", head->name);
1411 obj->sysfs_attr = (struct device_attribute){
1413 .name = obj->fs_data.sysfs_name,
1416 .show = amdgpu_ras_sysfs_read,
1418 sysfs_attr_init(&obj->sysfs_attr.attr);
1420 if (sysfs_add_file_to_group(&adev->dev->kobj,
1421 &obj->sysfs_attr.attr,
1427 obj->attr_inuse = 1;
1432 int amdgpu_ras_sysfs_remove(struct amdgpu_device *adev,
1433 struct ras_common_if *head)
1435 struct ras_manager *obj = amdgpu_ras_find_obj(adev, head);
1437 if (!obj || !obj->attr_inuse)
1440 sysfs_remove_file_from_group(&adev->dev->kobj,
1441 &obj->sysfs_attr.attr,
1443 obj->attr_inuse = 0;
1449 static int amdgpu_ras_sysfs_remove_all(struct amdgpu_device *adev)
1451 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1452 struct ras_manager *obj, *tmp;
1454 list_for_each_entry_safe(obj, tmp, &con->head, node) {
1455 amdgpu_ras_sysfs_remove(adev, &obj->head);
1458 if (amdgpu_bad_page_threshold != 0)
1459 amdgpu_ras_sysfs_remove_bad_page_node(adev);
1461 amdgpu_ras_sysfs_remove_feature_node(adev);
1468 * DOC: AMDGPU RAS Reboot Behavior for Unrecoverable Errors
1470 * Normally when there is an uncorrectable error, the driver will reset
1471 * the GPU to recover. However, in the event of an unrecoverable error,
1472 * the driver provides an interface to reboot the system automatically
1475 * The following file in debugfs provides that interface:
1476 * /sys/kernel/debug/dri/[0/1/2...]/ras/auto_reboot
1480 * .. code-block:: bash
1482 * echo true > .../ras/auto_reboot
1486 static struct dentry *amdgpu_ras_debugfs_create_ctrl_node(struct amdgpu_device *adev)
1488 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1489 struct amdgpu_ras_eeprom_control *eeprom = &con->eeprom_control;
1490 struct drm_minor *minor = adev_to_drm(adev)->primary;
1493 dir = debugfs_create_dir(RAS_FS_NAME, minor->debugfs_root);
1494 debugfs_create_file("ras_ctrl", S_IWUGO | S_IRUGO, dir, adev,
1495 &amdgpu_ras_debugfs_ctrl_ops);
1496 debugfs_create_file("ras_eeprom_reset", S_IWUGO | S_IRUGO, dir, adev,
1497 &amdgpu_ras_debugfs_eeprom_ops);
1498 debugfs_create_u32("bad_page_cnt_threshold", 0444, dir,
1499 &con->bad_page_cnt_threshold);
1500 debugfs_create_u32("ras_num_recs", 0444, dir, &eeprom->ras_num_recs);
1501 debugfs_create_x32("ras_hw_enabled", 0444, dir, &adev->ras_hw_enabled);
1502 debugfs_create_x32("ras_enabled", 0444, dir, &adev->ras_enabled);
1503 debugfs_create_file("ras_eeprom_size", S_IRUGO, dir, adev,
1504 &amdgpu_ras_debugfs_eeprom_size_ops);
1505 con->de_ras_eeprom_table = debugfs_create_file("ras_eeprom_table",
1507 &amdgpu_ras_debugfs_eeprom_table_ops);
1508 amdgpu_ras_debugfs_set_ret_size(&con->eeprom_control);
1511 * After one uncorrectable error happens, usually GPU recovery will
1512 * be scheduled. But due to the known problem in GPU recovery failing
1513 * to bring GPU back, below interface provides one direct way to
1514 * user to reboot system automatically in such case within
1515 * ERREVENT_ATHUB_INTERRUPT generated. Normal GPU recovery routine
1516 * will never be called.
1518 debugfs_create_bool("auto_reboot", S_IWUGO | S_IRUGO, dir, &con->reboot);
1521 * User could set this not to clean up hardware's error count register
1522 * of RAS IPs during ras recovery.
1524 debugfs_create_bool("disable_ras_err_cnt_harvest", 0644, dir,
1525 &con->disable_ras_err_cnt_harvest);
1529 static void amdgpu_ras_debugfs_create(struct amdgpu_device *adev,
1530 struct ras_fs_if *head,
1533 struct ras_manager *obj = amdgpu_ras_find_obj(adev, &head->head);
1540 memcpy(obj->fs_data.debugfs_name,
1542 sizeof(obj->fs_data.debugfs_name));
1544 debugfs_create_file(obj->fs_data.debugfs_name, S_IWUGO | S_IRUGO, dir,
1545 obj, &amdgpu_ras_debugfs_ops);
1548 void amdgpu_ras_debugfs_create_all(struct amdgpu_device *adev)
1550 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1552 struct ras_manager *obj;
1553 struct ras_fs_if fs_info;
1556 * it won't be called in resume path, no need to check
1557 * suspend and gpu reset status
1559 if (!IS_ENABLED(CONFIG_DEBUG_FS) || !con)
1562 dir = amdgpu_ras_debugfs_create_ctrl_node(adev);
1564 list_for_each_entry(obj, &con->head, node) {
1565 if (amdgpu_ras_is_supported(adev, obj->head.block) &&
1566 (obj->attr_inuse == 1)) {
1567 sprintf(fs_info.debugfs_name, "%s_err_inject",
1568 get_ras_block_str(&obj->head));
1569 fs_info.head = obj->head;
1570 amdgpu_ras_debugfs_create(adev, &fs_info, dir);
1578 static BIN_ATTR(gpu_vram_bad_pages, S_IRUGO,
1579 amdgpu_ras_sysfs_badpages_read, NULL, 0);
1580 static DEVICE_ATTR(features, S_IRUGO,
1581 amdgpu_ras_sysfs_features_read, NULL);
1582 static int amdgpu_ras_fs_init(struct amdgpu_device *adev)
1584 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1585 struct attribute_group group = {
1586 .name = RAS_FS_NAME,
1588 struct attribute *attrs[] = {
1589 &con->features_attr.attr,
1592 struct bin_attribute *bin_attrs[] = {
1598 /* add features entry */
1599 con->features_attr = dev_attr_features;
1600 group.attrs = attrs;
1601 sysfs_attr_init(attrs[0]);
1603 if (amdgpu_bad_page_threshold != 0) {
1604 /* add bad_page_features entry */
1605 bin_attr_gpu_vram_bad_pages.private = NULL;
1606 con->badpages_attr = bin_attr_gpu_vram_bad_pages;
1607 bin_attrs[0] = &con->badpages_attr;
1608 group.bin_attrs = bin_attrs;
1609 sysfs_bin_attr_init(bin_attrs[0]);
1612 r = sysfs_create_group(&adev->dev->kobj, &group);
1614 dev_err(adev->dev, "Failed to create RAS sysfs group!");
1619 static int amdgpu_ras_fs_fini(struct amdgpu_device *adev)
1621 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1622 struct ras_manager *con_obj, *ip_obj, *tmp;
1624 if (IS_ENABLED(CONFIG_DEBUG_FS)) {
1625 list_for_each_entry_safe(con_obj, tmp, &con->head, node) {
1626 ip_obj = amdgpu_ras_find_obj(adev, &con_obj->head);
1632 amdgpu_ras_sysfs_remove_all(adev);
1639 /* For the hardware that cannot enable bif ring for both ras_controller_irq
1640 * and ras_err_evnet_athub_irq ih cookies, the driver has to poll status
1641 * register to check whether the interrupt is triggered or not, and properly
1642 * ack the interrupt if it is there
1644 void amdgpu_ras_interrupt_fatal_error_handler(struct amdgpu_device *adev)
1646 /* Fatal error events are handled on host side */
1647 if (amdgpu_sriov_vf(adev))
1650 if (adev->nbio.ras &&
1651 adev->nbio.ras->handle_ras_controller_intr_no_bifring)
1652 adev->nbio.ras->handle_ras_controller_intr_no_bifring(adev);
1654 if (adev->nbio.ras &&
1655 adev->nbio.ras->handle_ras_err_event_athub_intr_no_bifring)
1656 adev->nbio.ras->handle_ras_err_event_athub_intr_no_bifring(adev);
1659 static void amdgpu_ras_interrupt_poison_consumption_handler(struct ras_manager *obj,
1660 struct amdgpu_iv_entry *entry)
1662 bool poison_stat = false;
1663 struct amdgpu_device *adev = obj->adev;
1664 struct amdgpu_ras_block_object *block_obj =
1665 amdgpu_ras_get_ras_block(adev, obj->head.block, 0);
1670 /* both query_poison_status and handle_poison_consumption are optional,
1671 * but at least one of them should be implemented if we need poison
1672 * consumption handler
1674 if (block_obj->hw_ops && block_obj->hw_ops->query_poison_status) {
1675 poison_stat = block_obj->hw_ops->query_poison_status(adev);
1677 /* Not poison consumption interrupt, no need to handle it */
1678 dev_info(adev->dev, "No RAS poison status in %s poison IH.\n",
1679 block_obj->ras_comm.name);
1685 amdgpu_umc_poison_handler(adev, false);
1687 if (block_obj->hw_ops && block_obj->hw_ops->handle_poison_consumption)
1688 poison_stat = block_obj->hw_ops->handle_poison_consumption(adev);
1690 /* gpu reset is fallback for failed and default cases */
1692 dev_info(adev->dev, "GPU reset for %s RAS poison consumption is issued!\n",
1693 block_obj->ras_comm.name);
1694 amdgpu_ras_reset_gpu(adev);
1696 amdgpu_gfx_poison_consumption_handler(adev, entry);
1700 static void amdgpu_ras_interrupt_poison_creation_handler(struct ras_manager *obj,
1701 struct amdgpu_iv_entry *entry)
1703 dev_info(obj->adev->dev,
1704 "Poison is created, no user action is needed.\n");
1707 static void amdgpu_ras_interrupt_umc_handler(struct ras_manager *obj,
1708 struct amdgpu_iv_entry *entry)
1710 struct ras_ih_data *data = &obj->ih_data;
1711 struct ras_err_data err_data = {0, 0, 0, NULL};
1717 /* Let IP handle its data, maybe we need get the output
1718 * from the callback to update the error type/count, etc
1720 ret = data->cb(obj->adev, &err_data, entry);
1721 /* ue will trigger an interrupt, and in that case
1722 * we need do a reset to recovery the whole system.
1723 * But leave IP do that recovery, here we just dispatch
1726 if (ret == AMDGPU_RAS_SUCCESS) {
1727 /* these counts could be left as 0 if
1728 * some blocks do not count error number
1730 obj->err_data.ue_count += err_data.ue_count;
1731 obj->err_data.ce_count += err_data.ce_count;
1735 static void amdgpu_ras_interrupt_handler(struct ras_manager *obj)
1737 struct ras_ih_data *data = &obj->ih_data;
1738 struct amdgpu_iv_entry entry;
1740 while (data->rptr != data->wptr) {
1742 memcpy(&entry, &data->ring[data->rptr],
1743 data->element_size);
1746 data->rptr = (data->aligned_element_size +
1747 data->rptr) % data->ring_size;
1749 if (amdgpu_ras_is_poison_mode_supported(obj->adev)) {
1750 if (obj->head.block == AMDGPU_RAS_BLOCK__UMC)
1751 amdgpu_ras_interrupt_poison_creation_handler(obj, &entry);
1753 amdgpu_ras_interrupt_poison_consumption_handler(obj, &entry);
1755 if (obj->head.block == AMDGPU_RAS_BLOCK__UMC)
1756 amdgpu_ras_interrupt_umc_handler(obj, &entry);
1758 dev_warn(obj->adev->dev,
1759 "No RAS interrupt handler for non-UMC block with poison disabled.\n");
1764 static void amdgpu_ras_interrupt_process_handler(struct work_struct *work)
1766 struct ras_ih_data *data =
1767 container_of(work, struct ras_ih_data, ih_work);
1768 struct ras_manager *obj =
1769 container_of(data, struct ras_manager, ih_data);
1771 amdgpu_ras_interrupt_handler(obj);
1774 int amdgpu_ras_interrupt_dispatch(struct amdgpu_device *adev,
1775 struct ras_dispatch_if *info)
1777 struct ras_manager *obj = amdgpu_ras_find_obj(adev, &info->head);
1778 struct ras_ih_data *data = &obj->ih_data;
1783 if (data->inuse == 0)
1786 /* Might be overflow... */
1787 memcpy(&data->ring[data->wptr], info->entry,
1788 data->element_size);
1791 data->wptr = (data->aligned_element_size +
1792 data->wptr) % data->ring_size;
1794 schedule_work(&data->ih_work);
1799 int amdgpu_ras_interrupt_remove_handler(struct amdgpu_device *adev,
1800 struct ras_common_if *head)
1802 struct ras_manager *obj = amdgpu_ras_find_obj(adev, head);
1803 struct ras_ih_data *data;
1808 data = &obj->ih_data;
1809 if (data->inuse == 0)
1812 cancel_work_sync(&data->ih_work);
1815 memset(data, 0, sizeof(*data));
1821 int amdgpu_ras_interrupt_add_handler(struct amdgpu_device *adev,
1822 struct ras_common_if *head)
1824 struct ras_manager *obj = amdgpu_ras_find_obj(adev, head);
1825 struct ras_ih_data *data;
1826 struct amdgpu_ras_block_object *ras_obj;
1829 /* in case we registe the IH before enable ras feature */
1830 obj = amdgpu_ras_create_obj(adev, head);
1836 ras_obj = container_of(head, struct amdgpu_ras_block_object, ras_comm);
1838 data = &obj->ih_data;
1839 /* add the callback.etc */
1840 *data = (struct ras_ih_data) {
1842 .cb = ras_obj->ras_cb,
1843 .element_size = sizeof(struct amdgpu_iv_entry),
1848 INIT_WORK(&data->ih_work, amdgpu_ras_interrupt_process_handler);
1850 data->aligned_element_size = ALIGN(data->element_size, 8);
1851 /* the ring can store 64 iv entries. */
1852 data->ring_size = 64 * data->aligned_element_size;
1853 data->ring = kmalloc(data->ring_size, GFP_KERNEL);
1865 static int amdgpu_ras_interrupt_remove_all(struct amdgpu_device *adev)
1867 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1868 struct ras_manager *obj, *tmp;
1870 list_for_each_entry_safe(obj, tmp, &con->head, node) {
1871 amdgpu_ras_interrupt_remove_handler(adev, &obj->head);
1878 /* traversal all IPs except NBIO to query error counter */
1879 static void amdgpu_ras_log_on_err_counter(struct amdgpu_device *adev)
1881 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1882 struct ras_manager *obj;
1884 if (!adev->ras_enabled || !con)
1887 list_for_each_entry(obj, &con->head, node) {
1888 struct ras_query_if info = {
1893 * PCIE_BIF IP has one different isr by ras controller
1894 * interrupt, the specific ras counter query will be
1895 * done in that isr. So skip such block from common
1896 * sync flood interrupt isr calling.
1898 if (info.head.block == AMDGPU_RAS_BLOCK__PCIE_BIF)
1902 * this is a workaround for aldebaran, skip send msg to
1903 * smu to get ecc_info table due to smu handle get ecc
1904 * info table failed temporarily.
1905 * should be removed until smu fix handle ecc_info table.
1907 if ((info.head.block == AMDGPU_RAS_BLOCK__UMC) &&
1908 (adev->ip_versions[MP1_HWIP][0] == IP_VERSION(13, 0, 2)))
1911 amdgpu_ras_query_error_status(adev, &info);
1913 if (adev->ip_versions[MP0_HWIP][0] != IP_VERSION(11, 0, 2) &&
1914 adev->ip_versions[MP0_HWIP][0] != IP_VERSION(11, 0, 4) &&
1915 adev->ip_versions[MP0_HWIP][0] != IP_VERSION(13, 0, 0)) {
1916 if (amdgpu_ras_reset_error_status(adev, info.head.block))
1917 dev_warn(adev->dev, "Failed to reset error counter and error status");
1922 /* Parse RdRspStatus and WrRspStatus */
1923 static void amdgpu_ras_error_status_query(struct amdgpu_device *adev,
1924 struct ras_query_if *info)
1926 struct amdgpu_ras_block_object *block_obj;
1928 * Only two block need to query read/write
1929 * RspStatus at current state
1931 if ((info->head.block != AMDGPU_RAS_BLOCK__GFX) &&
1932 (info->head.block != AMDGPU_RAS_BLOCK__MMHUB))
1935 block_obj = amdgpu_ras_get_ras_block(adev,
1937 info->head.sub_block_index);
1939 if (!block_obj || !block_obj->hw_ops) {
1940 dev_dbg_once(adev->dev, "%s doesn't config RAS function\n",
1941 get_ras_block_str(&info->head));
1945 if (block_obj->hw_ops->query_ras_error_status)
1946 block_obj->hw_ops->query_ras_error_status(adev);
1950 static void amdgpu_ras_query_err_status(struct amdgpu_device *adev)
1952 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1953 struct ras_manager *obj;
1955 if (!adev->ras_enabled || !con)
1958 list_for_each_entry(obj, &con->head, node) {
1959 struct ras_query_if info = {
1963 amdgpu_ras_error_status_query(adev, &info);
1967 /* recovery begin */
1969 /* return 0 on success.
1970 * caller need free bps.
1972 static int amdgpu_ras_badpages_read(struct amdgpu_device *adev,
1973 struct ras_badpage **bps, unsigned int *count)
1975 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1976 struct ras_err_handler_data *data;
1978 int ret = 0, status;
1980 if (!con || !con->eh_data || !bps || !count)
1983 mutex_lock(&con->recovery_lock);
1984 data = con->eh_data;
1985 if (!data || data->count == 0) {
1991 *bps = kmalloc(sizeof(struct ras_badpage) * data->count, GFP_KERNEL);
1997 for (; i < data->count; i++) {
1998 (*bps)[i] = (struct ras_badpage){
1999 .bp = data->bps[i].retired_page,
2000 .size = AMDGPU_GPU_PAGE_SIZE,
2001 .flags = AMDGPU_RAS_RETIRE_PAGE_RESERVED,
2003 status = amdgpu_vram_mgr_query_page_status(&adev->mman.vram_mgr,
2004 data->bps[i].retired_page);
2005 if (status == -EBUSY)
2006 (*bps)[i].flags = AMDGPU_RAS_RETIRE_PAGE_PENDING;
2007 else if (status == -ENOENT)
2008 (*bps)[i].flags = AMDGPU_RAS_RETIRE_PAGE_FAULT;
2011 *count = data->count;
2013 mutex_unlock(&con->recovery_lock);
2017 static void amdgpu_ras_do_recovery(struct work_struct *work)
2019 struct amdgpu_ras *ras =
2020 container_of(work, struct amdgpu_ras, recovery_work);
2021 struct amdgpu_device *remote_adev = NULL;
2022 struct amdgpu_device *adev = ras->adev;
2023 struct list_head device_list, *device_list_handle = NULL;
2025 if (!ras->disable_ras_err_cnt_harvest) {
2026 struct amdgpu_hive_info *hive = amdgpu_get_xgmi_hive(adev);
2028 /* Build list of devices to query RAS related errors */
2029 if (hive && adev->gmc.xgmi.num_physical_nodes > 1) {
2030 device_list_handle = &hive->device_list;
2032 INIT_LIST_HEAD(&device_list);
2033 list_add_tail(&adev->gmc.xgmi.head, &device_list);
2034 device_list_handle = &device_list;
2037 list_for_each_entry(remote_adev,
2038 device_list_handle, gmc.xgmi.head) {
2039 amdgpu_ras_query_err_status(remote_adev);
2040 amdgpu_ras_log_on_err_counter(remote_adev);
2043 amdgpu_put_xgmi_hive(hive);
2046 if (amdgpu_device_should_recover_gpu(ras->adev)) {
2047 struct amdgpu_reset_context reset_context;
2048 memset(&reset_context, 0, sizeof(reset_context));
2050 reset_context.method = AMD_RESET_METHOD_NONE;
2051 reset_context.reset_req_dev = adev;
2053 /* Perform full reset in fatal error mode */
2054 if (!amdgpu_ras_is_poison_mode_supported(ras->adev))
2055 set_bit(AMDGPU_NEED_FULL_RESET, &reset_context.flags);
2057 clear_bit(AMDGPU_NEED_FULL_RESET, &reset_context.flags);
2059 if (ras->gpu_reset_flags & AMDGPU_RAS_GPU_RESET_MODE2_RESET) {
2060 ras->gpu_reset_flags &= ~AMDGPU_RAS_GPU_RESET_MODE2_RESET;
2061 reset_context.method = AMD_RESET_METHOD_MODE2;
2064 /* Fatal error occurs in poison mode, mode1 reset is used to
2067 if (ras->gpu_reset_flags & AMDGPU_RAS_GPU_RESET_MODE1_RESET) {
2068 ras->gpu_reset_flags &= ~AMDGPU_RAS_GPU_RESET_MODE1_RESET;
2069 set_bit(AMDGPU_NEED_FULL_RESET, &reset_context.flags);
2071 psp_fatal_error_recovery_quirk(&adev->psp);
2075 amdgpu_device_gpu_recover(ras->adev, NULL, &reset_context);
2077 atomic_set(&ras->in_recovery, 0);
2080 /* alloc/realloc bps array */
2081 static int amdgpu_ras_realloc_eh_data_space(struct amdgpu_device *adev,
2082 struct ras_err_handler_data *data, int pages)
2084 unsigned int old_space = data->count + data->space_left;
2085 unsigned int new_space = old_space + pages;
2086 unsigned int align_space = ALIGN(new_space, 512);
2087 void *bps = kmalloc(align_space * sizeof(*data->bps), GFP_KERNEL);
2094 memcpy(bps, data->bps,
2095 data->count * sizeof(*data->bps));
2100 data->space_left += align_space - old_space;
2104 /* it deal with vram only. */
2105 int amdgpu_ras_add_bad_pages(struct amdgpu_device *adev,
2106 struct eeprom_table_record *bps, int pages)
2108 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
2109 struct ras_err_handler_data *data;
2113 if (!con || !con->eh_data || !bps || pages <= 0)
2116 mutex_lock(&con->recovery_lock);
2117 data = con->eh_data;
2121 for (i = 0; i < pages; i++) {
2122 if (amdgpu_ras_check_bad_page_unlock(con,
2123 bps[i].retired_page << AMDGPU_GPU_PAGE_SHIFT))
2126 if (!data->space_left &&
2127 amdgpu_ras_realloc_eh_data_space(adev, data, 256)) {
2132 amdgpu_vram_mgr_reserve_range(&adev->mman.vram_mgr,
2133 bps[i].retired_page << AMDGPU_GPU_PAGE_SHIFT,
2134 AMDGPU_GPU_PAGE_SIZE);
2136 memcpy(&data->bps[data->count], &bps[i], sizeof(*data->bps));
2141 mutex_unlock(&con->recovery_lock);
2147 * write error record array to eeprom, the function should be
2148 * protected by recovery_lock
2149 * new_cnt: new added UE count, excluding reserved bad pages, can be NULL
2151 int amdgpu_ras_save_bad_pages(struct amdgpu_device *adev,
2152 unsigned long *new_cnt)
2154 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
2155 struct ras_err_handler_data *data;
2156 struct amdgpu_ras_eeprom_control *control;
2159 if (!con || !con->eh_data) {
2166 mutex_lock(&con->recovery_lock);
2167 control = &con->eeprom_control;
2168 data = con->eh_data;
2169 save_count = data->count - control->ras_num_recs;
2170 mutex_unlock(&con->recovery_lock);
2173 *new_cnt = save_count / adev->umc.retire_unit;
2175 /* only new entries are saved */
2176 if (save_count > 0) {
2177 if (amdgpu_ras_eeprom_append(control,
2178 &data->bps[control->ras_num_recs],
2180 dev_err(adev->dev, "Failed to save EEPROM table data!");
2184 dev_info(adev->dev, "Saved %d pages to EEPROM table.\n", save_count);
2191 * read error record array in eeprom and reserve enough space for
2192 * storing new bad pages
2194 static int amdgpu_ras_load_bad_pages(struct amdgpu_device *adev)
2196 struct amdgpu_ras_eeprom_control *control =
2197 &adev->psp.ras_context.ras->eeprom_control;
2198 struct eeprom_table_record *bps;
2201 /* no bad page record, skip eeprom access */
2202 if (control->ras_num_recs == 0 || amdgpu_bad_page_threshold == 0)
2205 bps = kcalloc(control->ras_num_recs, sizeof(*bps), GFP_KERNEL);
2209 ret = amdgpu_ras_eeprom_read(control, bps, control->ras_num_recs);
2211 dev_err(adev->dev, "Failed to load EEPROM table records!");
2213 ret = amdgpu_ras_add_bad_pages(adev, bps, control->ras_num_recs);
2219 static bool amdgpu_ras_check_bad_page_unlock(struct amdgpu_ras *con,
2222 struct ras_err_handler_data *data = con->eh_data;
2225 addr >>= AMDGPU_GPU_PAGE_SHIFT;
2226 for (i = 0; i < data->count; i++)
2227 if (addr == data->bps[i].retired_page)
2234 * check if an address belongs to bad page
2236 * Note: this check is only for umc block
2238 static bool amdgpu_ras_check_bad_page(struct amdgpu_device *adev,
2241 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
2244 if (!con || !con->eh_data)
2247 mutex_lock(&con->recovery_lock);
2248 ret = amdgpu_ras_check_bad_page_unlock(con, addr);
2249 mutex_unlock(&con->recovery_lock);
2253 static void amdgpu_ras_validate_threshold(struct amdgpu_device *adev,
2256 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
2259 * Justification of value bad_page_cnt_threshold in ras structure
2261 * Generally, 0 <= amdgpu_bad_page_threshold <= max record length
2262 * in eeprom or amdgpu_bad_page_threshold == -2, introduce two
2263 * scenarios accordingly.
2265 * Bad page retirement enablement:
2266 * - If amdgpu_bad_page_threshold = -2,
2267 * bad_page_cnt_threshold = typical value by formula.
2269 * - When the value from user is 0 < amdgpu_bad_page_threshold <
2270 * max record length in eeprom, use it directly.
2272 * Bad page retirement disablement:
2273 * - If amdgpu_bad_page_threshold = 0, bad page retirement
2274 * functionality is disabled, and bad_page_cnt_threshold will
2278 if (amdgpu_bad_page_threshold < 0) {
2279 u64 val = adev->gmc.mc_vram_size;
2281 do_div(val, RAS_BAD_PAGE_COVER);
2282 con->bad_page_cnt_threshold = min(lower_32_bits(val),
2285 con->bad_page_cnt_threshold = min_t(int, max_count,
2286 amdgpu_bad_page_threshold);
2290 int amdgpu_ras_recovery_init(struct amdgpu_device *adev)
2292 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
2293 struct ras_err_handler_data **data;
2294 u32 max_eeprom_records_count = 0;
2295 bool exc_err_limit = false;
2298 if (!con || amdgpu_sriov_vf(adev))
2301 /* Allow access to RAS EEPROM via debugfs, when the ASIC
2302 * supports RAS and debugfs is enabled, but when
2303 * adev->ras_enabled is unset, i.e. when "ras_enable"
2304 * module parameter is set to 0.
2308 if (!adev->ras_enabled)
2311 data = &con->eh_data;
2312 *data = kmalloc(sizeof(**data), GFP_KERNEL | __GFP_ZERO);
2318 mutex_init(&con->recovery_lock);
2319 INIT_WORK(&con->recovery_work, amdgpu_ras_do_recovery);
2320 atomic_set(&con->in_recovery, 0);
2321 con->eeprom_control.bad_channel_bitmap = 0;
2323 max_eeprom_records_count = amdgpu_ras_eeprom_max_record_count(&con->eeprom_control);
2324 amdgpu_ras_validate_threshold(adev, max_eeprom_records_count);
2326 /* Todo: During test the SMU might fail to read the eeprom through I2C
2327 * when the GPU is pending on XGMI reset during probe time
2328 * (Mostly after second bus reset), skip it now
2330 if (adev->gmc.xgmi.pending_reset)
2332 ret = amdgpu_ras_eeprom_init(&con->eeprom_control, &exc_err_limit);
2334 * This calling fails when exc_err_limit is true or
2337 if (exc_err_limit || ret)
2340 if (con->eeprom_control.ras_num_recs) {
2341 ret = amdgpu_ras_load_bad_pages(adev);
2345 amdgpu_dpm_send_hbm_bad_pages_num(adev, con->eeprom_control.ras_num_recs);
2347 if (con->update_channel_flag == true) {
2348 amdgpu_dpm_send_hbm_bad_channel_flag(adev, con->eeprom_control.bad_channel_bitmap);
2349 con->update_channel_flag = false;
2353 #ifdef CONFIG_X86_MCE_AMD
2354 if ((adev->asic_type == CHIP_ALDEBARAN) &&
2355 (adev->gmc.xgmi.connected_to_cpu))
2356 amdgpu_register_bad_pages_mca_notifier(adev);
2361 kfree((*data)->bps);
2363 con->eh_data = NULL;
2365 dev_warn(adev->dev, "Failed to initialize ras recovery! (%d)\n", ret);
2368 * Except error threshold exceeding case, other failure cases in this
2369 * function would not fail amdgpu driver init.
2379 static int amdgpu_ras_recovery_fini(struct amdgpu_device *adev)
2381 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
2382 struct ras_err_handler_data *data = con->eh_data;
2384 /* recovery_init failed to init it, fini is useless */
2388 cancel_work_sync(&con->recovery_work);
2390 mutex_lock(&con->recovery_lock);
2391 con->eh_data = NULL;
2394 mutex_unlock(&con->recovery_lock);
2400 static bool amdgpu_ras_asic_supported(struct amdgpu_device *adev)
2402 if (amdgpu_sriov_vf(adev)) {
2403 switch (adev->ip_versions[MP0_HWIP][0]) {
2404 case IP_VERSION(13, 0, 2):
2405 case IP_VERSION(13, 0, 6):
2412 if (adev->asic_type == CHIP_IP_DISCOVERY) {
2413 switch (adev->ip_versions[MP0_HWIP][0]) {
2414 case IP_VERSION(13, 0, 0):
2415 case IP_VERSION(13, 0, 6):
2416 case IP_VERSION(13, 0, 10):
2423 return adev->asic_type == CHIP_VEGA10 ||
2424 adev->asic_type == CHIP_VEGA20 ||
2425 adev->asic_type == CHIP_ARCTURUS ||
2426 adev->asic_type == CHIP_ALDEBARAN ||
2427 adev->asic_type == CHIP_SIENNA_CICHLID;
2431 * this is workaround for vega20 workstation sku,
2432 * force enable gfx ras, ignore vbios gfx ras flag
2433 * due to GC EDC can not write
2435 static void amdgpu_ras_get_quirks(struct amdgpu_device *adev)
2437 struct atom_context *ctx = adev->mode_info.atom_context;
2442 if (strnstr(ctx->vbios_pn, "D16406",
2443 sizeof(ctx->vbios_pn)) ||
2444 strnstr(ctx->vbios_pn, "D36002",
2445 sizeof(ctx->vbios_pn)))
2446 adev->ras_hw_enabled |= (1 << AMDGPU_RAS_BLOCK__GFX);
2450 * check hardware's ras ability which will be saved in hw_supported.
2451 * if hardware does not support ras, we can skip some ras initializtion and
2452 * forbid some ras operations from IP.
2453 * if software itself, say boot parameter, limit the ras ability. We still
2454 * need allow IP do some limited operations, like disable. In such case,
2455 * we have to initialize ras as normal. but need check if operation is
2456 * allowed or not in each function.
2458 static void amdgpu_ras_check_supported(struct amdgpu_device *adev)
2460 adev->ras_hw_enabled = adev->ras_enabled = 0;
2462 if (!amdgpu_ras_asic_supported(adev))
2465 if (!adev->gmc.xgmi.connected_to_cpu && !adev->gmc.is_app_apu) {
2466 if (amdgpu_atomfirmware_mem_ecc_supported(adev)) {
2467 dev_info(adev->dev, "MEM ECC is active.\n");
2468 adev->ras_hw_enabled |= (1 << AMDGPU_RAS_BLOCK__UMC |
2469 1 << AMDGPU_RAS_BLOCK__DF);
2471 dev_info(adev->dev, "MEM ECC is not presented.\n");
2474 if (amdgpu_atomfirmware_sram_ecc_supported(adev)) {
2475 dev_info(adev->dev, "SRAM ECC is active.\n");
2476 if (!amdgpu_sriov_vf(adev))
2477 adev->ras_hw_enabled |= ~(1 << AMDGPU_RAS_BLOCK__UMC |
2478 1 << AMDGPU_RAS_BLOCK__DF);
2480 adev->ras_hw_enabled |= (1 << AMDGPU_RAS_BLOCK__PCIE_BIF |
2481 1 << AMDGPU_RAS_BLOCK__SDMA |
2482 1 << AMDGPU_RAS_BLOCK__GFX);
2484 /* VCN/JPEG RAS can be supported on both bare metal and
2487 if (adev->ip_versions[VCN_HWIP][0] == IP_VERSION(2, 6, 0) ||
2488 adev->ip_versions[VCN_HWIP][0] == IP_VERSION(4, 0, 0))
2489 adev->ras_hw_enabled |= (1 << AMDGPU_RAS_BLOCK__VCN |
2490 1 << AMDGPU_RAS_BLOCK__JPEG);
2492 adev->ras_hw_enabled &= ~(1 << AMDGPU_RAS_BLOCK__VCN |
2493 1 << AMDGPU_RAS_BLOCK__JPEG);
2496 * XGMI RAS is not supported if xgmi num physical nodes
2499 if (!adev->gmc.xgmi.num_physical_nodes)
2500 adev->ras_hw_enabled &= ~(1 << AMDGPU_RAS_BLOCK__XGMI_WAFL);
2502 dev_info(adev->dev, "SRAM ECC is not presented.\n");
2505 /* driver only manages a few IP blocks RAS feature
2506 * when GPU is connected cpu through XGMI */
2507 adev->ras_hw_enabled |= (1 << AMDGPU_RAS_BLOCK__GFX |
2508 1 << AMDGPU_RAS_BLOCK__SDMA |
2509 1 << AMDGPU_RAS_BLOCK__MMHUB);
2512 amdgpu_ras_get_quirks(adev);
2514 /* hw_supported needs to be aligned with RAS block mask. */
2515 adev->ras_hw_enabled &= AMDGPU_RAS_BLOCK_MASK;
2519 * Disable ras feature for aqua vanjaram
2520 * by default on apu platform.
2522 if (adev->ip_versions[MP0_HWIP][0] == IP_VERSION(13, 0, 6) &&
2523 adev->gmc.is_app_apu)
2524 adev->ras_enabled = amdgpu_ras_enable != 1 ? 0 :
2525 adev->ras_hw_enabled & amdgpu_ras_mask;
2527 adev->ras_enabled = amdgpu_ras_enable == 0 ? 0 :
2528 adev->ras_hw_enabled & amdgpu_ras_mask;
2531 static void amdgpu_ras_counte_dw(struct work_struct *work)
2533 struct amdgpu_ras *con = container_of(work, struct amdgpu_ras,
2534 ras_counte_delay_work.work);
2535 struct amdgpu_device *adev = con->adev;
2536 struct drm_device *dev = adev_to_drm(adev);
2537 unsigned long ce_count, ue_count;
2540 res = pm_runtime_get_sync(dev->dev);
2544 /* Cache new values.
2546 if (amdgpu_ras_query_error_count(adev, &ce_count, &ue_count, NULL) == 0) {
2547 atomic_set(&con->ras_ce_count, ce_count);
2548 atomic_set(&con->ras_ue_count, ue_count);
2551 pm_runtime_mark_last_busy(dev->dev);
2553 pm_runtime_put_autosuspend(dev->dev);
2556 static void amdgpu_ras_query_poison_mode(struct amdgpu_device *adev)
2558 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
2559 bool df_poison, umc_poison;
2561 /* poison setting is useless on SRIOV guest */
2562 if (amdgpu_sriov_vf(adev) || !con)
2565 /* Init poison supported flag, the default value is false */
2566 if (adev->gmc.xgmi.connected_to_cpu) {
2567 /* enabled by default when GPU is connected to CPU */
2568 con->poison_supported = true;
2569 } else if (adev->df.funcs &&
2570 adev->df.funcs->query_ras_poison_mode &&
2572 adev->umc.ras->query_ras_poison_mode) {
2574 adev->df.funcs->query_ras_poison_mode(adev);
2576 adev->umc.ras->query_ras_poison_mode(adev);
2578 /* Only poison is set in both DF and UMC, we can support it */
2579 if (df_poison && umc_poison)
2580 con->poison_supported = true;
2581 else if (df_poison != umc_poison)
2583 "Poison setting is inconsistent in DF/UMC(%d:%d)!\n",
2584 df_poison, umc_poison);
2588 int amdgpu_ras_init(struct amdgpu_device *adev)
2590 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
2596 con = kmalloc(sizeof(struct amdgpu_ras) +
2597 sizeof(struct ras_manager) * AMDGPU_RAS_BLOCK_COUNT +
2598 sizeof(struct ras_manager) * AMDGPU_RAS_MCA_BLOCK_COUNT,
2599 GFP_KERNEL|__GFP_ZERO);
2604 INIT_DELAYED_WORK(&con->ras_counte_delay_work, amdgpu_ras_counte_dw);
2605 atomic_set(&con->ras_ce_count, 0);
2606 atomic_set(&con->ras_ue_count, 0);
2608 con->objs = (struct ras_manager *)(con + 1);
2610 amdgpu_ras_set_context(adev, con);
2612 amdgpu_ras_check_supported(adev);
2614 if (!adev->ras_enabled || adev->asic_type == CHIP_VEGA10) {
2615 /* set gfx block ras context feature for VEGA20 Gaming
2616 * send ras disable cmd to ras ta during ras late init.
2618 if (!adev->ras_enabled && adev->asic_type == CHIP_VEGA20) {
2619 con->features |= BIT(AMDGPU_RAS_BLOCK__GFX);
2628 con->update_channel_flag = false;
2630 INIT_LIST_HEAD(&con->head);
2631 /* Might need get this flag from vbios. */
2632 con->flags = RAS_DEFAULT_FLAGS;
2634 /* initialize nbio ras function ahead of any other
2635 * ras functions so hardware fatal error interrupt
2636 * can be enabled as early as possible */
2637 switch (adev->ip_versions[NBIO_HWIP][0]) {
2638 case IP_VERSION(7, 4, 0):
2639 case IP_VERSION(7, 4, 1):
2640 case IP_VERSION(7, 4, 4):
2641 if (!adev->gmc.xgmi.connected_to_cpu)
2642 adev->nbio.ras = &nbio_v7_4_ras;
2644 case IP_VERSION(4, 3, 0):
2645 if (adev->ras_hw_enabled & (1 << AMDGPU_RAS_BLOCK__DF))
2646 /* unlike other generation of nbio ras,
2647 * nbio v4_3 only support fatal error interrupt
2648 * to inform software that DF is freezed due to
2649 * system fatal error event. driver should not
2650 * enable nbio ras in such case. Instead,
2652 adev->nbio.ras = &nbio_v4_3_ras;
2654 case IP_VERSION(7, 9, 0):
2655 if (!adev->gmc.is_app_apu)
2656 adev->nbio.ras = &nbio_v7_9_ras;
2659 /* nbio ras is not available */
2663 /* nbio ras block needs to be enabled ahead of other ras blocks
2664 * to handle fatal error */
2665 r = amdgpu_nbio_ras_sw_init(adev);
2669 if (adev->nbio.ras &&
2670 adev->nbio.ras->init_ras_controller_interrupt) {
2671 r = adev->nbio.ras->init_ras_controller_interrupt(adev);
2676 if (adev->nbio.ras &&
2677 adev->nbio.ras->init_ras_err_event_athub_interrupt) {
2678 r = adev->nbio.ras->init_ras_err_event_athub_interrupt(adev);
2683 amdgpu_ras_query_poison_mode(adev);
2685 if (amdgpu_ras_fs_init(adev)) {
2690 dev_info(adev->dev, "RAS INFO: ras initialized successfully, "
2691 "hardware ability[%x] ras_mask[%x]\n",
2692 adev->ras_hw_enabled, adev->ras_enabled);
2696 amdgpu_ras_set_context(adev, NULL);
2702 int amdgpu_persistent_edc_harvesting_supported(struct amdgpu_device *adev)
2704 if (adev->gmc.xgmi.connected_to_cpu ||
2705 adev->gmc.is_app_apu)
2710 static int amdgpu_persistent_edc_harvesting(struct amdgpu_device *adev,
2711 struct ras_common_if *ras_block)
2713 struct ras_query_if info = {
2717 if (!amdgpu_persistent_edc_harvesting_supported(adev))
2720 if (amdgpu_ras_query_error_status(adev, &info) != 0)
2721 DRM_WARN("RAS init harvest failure");
2723 if (amdgpu_ras_reset_error_status(adev, ras_block->block) != 0)
2724 DRM_WARN("RAS init harvest reset failure");
2729 bool amdgpu_ras_is_poison_mode_supported(struct amdgpu_device *adev)
2731 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
2736 return con->poison_supported;
2739 /* helper function to handle common stuff in ip late init phase */
2740 int amdgpu_ras_block_late_init(struct amdgpu_device *adev,
2741 struct ras_common_if *ras_block)
2743 struct amdgpu_ras_block_object *ras_obj = NULL;
2744 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
2745 struct ras_query_if *query_info;
2746 unsigned long ue_count, ce_count;
2749 /* disable RAS feature per IP block if it is not supported */
2750 if (!amdgpu_ras_is_supported(adev, ras_block->block)) {
2751 amdgpu_ras_feature_enable_on_boot(adev, ras_block, 0);
2755 r = amdgpu_ras_feature_enable_on_boot(adev, ras_block, 1);
2757 if (adev->in_suspend || amdgpu_in_reset(adev)) {
2758 /* in resume phase, if fail to enable ras,
2759 * clean up all ras fs nodes, and disable ras */
2765 /* check for errors on warm reset edc persisant supported ASIC */
2766 amdgpu_persistent_edc_harvesting(adev, ras_block);
2768 /* in resume phase, no need to create ras fs node */
2769 if (adev->in_suspend || amdgpu_in_reset(adev))
2772 ras_obj = container_of(ras_block, struct amdgpu_ras_block_object, ras_comm);
2773 if (ras_obj->ras_cb || (ras_obj->hw_ops &&
2774 (ras_obj->hw_ops->query_poison_status ||
2775 ras_obj->hw_ops->handle_poison_consumption))) {
2776 r = amdgpu_ras_interrupt_add_handler(adev, ras_block);
2781 if (ras_obj->hw_ops &&
2782 (ras_obj->hw_ops->query_ras_error_count ||
2783 ras_obj->hw_ops->query_ras_error_status)) {
2784 r = amdgpu_ras_sysfs_create(adev, ras_block);
2788 /* Those are the cached values at init.
2790 query_info = kzalloc(sizeof(*query_info), GFP_KERNEL);
2793 memcpy(&query_info->head, ras_block, sizeof(struct ras_common_if));
2795 if (amdgpu_ras_query_error_count(adev, &ce_count, &ue_count, query_info) == 0) {
2796 atomic_set(&con->ras_ce_count, ce_count);
2797 atomic_set(&con->ras_ue_count, ue_count);
2806 if (ras_obj->ras_cb)
2807 amdgpu_ras_interrupt_remove_handler(adev, ras_block);
2809 amdgpu_ras_feature_enable(adev, ras_block, 0);
2813 static int amdgpu_ras_block_late_init_default(struct amdgpu_device *adev,
2814 struct ras_common_if *ras_block)
2816 return amdgpu_ras_block_late_init(adev, ras_block);
2819 /* helper function to remove ras fs node and interrupt handler */
2820 void amdgpu_ras_block_late_fini(struct amdgpu_device *adev,
2821 struct ras_common_if *ras_block)
2823 struct amdgpu_ras_block_object *ras_obj;
2827 amdgpu_ras_sysfs_remove(adev, ras_block);
2829 ras_obj = container_of(ras_block, struct amdgpu_ras_block_object, ras_comm);
2830 if (ras_obj->ras_cb)
2831 amdgpu_ras_interrupt_remove_handler(adev, ras_block);
2834 static void amdgpu_ras_block_late_fini_default(struct amdgpu_device *adev,
2835 struct ras_common_if *ras_block)
2837 return amdgpu_ras_block_late_fini(adev, ras_block);
2840 /* do some init work after IP late init as dependence.
2841 * and it runs in resume/gpu reset/booting up cases.
2843 void amdgpu_ras_resume(struct amdgpu_device *adev)
2845 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
2846 struct ras_manager *obj, *tmp;
2848 if (!adev->ras_enabled || !con) {
2849 /* clean ras context for VEGA20 Gaming after send ras disable cmd */
2850 amdgpu_release_ras_context(adev);
2855 if (con->flags & AMDGPU_RAS_FLAG_INIT_BY_VBIOS) {
2856 /* Set up all other IPs which are not implemented. There is a
2857 * tricky thing that IP's actual ras error type should be
2858 * MULTI_UNCORRECTABLE, but as driver does not handle it, so
2859 * ERROR_NONE make sense anyway.
2861 amdgpu_ras_enable_all_features(adev, 1);
2863 /* We enable ras on all hw_supported block, but as boot
2864 * parameter might disable some of them and one or more IP has
2865 * not implemented yet. So we disable them on behalf.
2867 list_for_each_entry_safe(obj, tmp, &con->head, node) {
2868 if (!amdgpu_ras_is_supported(adev, obj->head.block)) {
2869 amdgpu_ras_feature_enable(adev, &obj->head, 0);
2870 /* there should be no any reference. */
2871 WARN_ON(alive_obj(obj));
2877 void amdgpu_ras_suspend(struct amdgpu_device *adev)
2879 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
2881 if (!adev->ras_enabled || !con)
2884 amdgpu_ras_disable_all_features(adev, 0);
2885 /* Make sure all ras objects are disabled. */
2887 amdgpu_ras_disable_all_features(adev, 1);
2890 int amdgpu_ras_late_init(struct amdgpu_device *adev)
2892 struct amdgpu_ras_block_list *node, *tmp;
2893 struct amdgpu_ras_block_object *obj;
2896 /* Guest side doesn't need init ras feature */
2897 if (amdgpu_sriov_vf(adev))
2900 list_for_each_entry_safe(node, tmp, &adev->ras_list, node) {
2901 if (!node->ras_obj) {
2902 dev_warn(adev->dev, "Warning: abnormal ras list node.\n");
2906 obj = node->ras_obj;
2907 if (obj->ras_late_init) {
2908 r = obj->ras_late_init(adev, &obj->ras_comm);
2910 dev_err(adev->dev, "%s failed to execute ras_late_init! ret:%d\n",
2911 obj->ras_comm.name, r);
2915 amdgpu_ras_block_late_init_default(adev, &obj->ras_comm);
2921 /* do some fini work before IP fini as dependence */
2922 int amdgpu_ras_pre_fini(struct amdgpu_device *adev)
2924 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
2926 if (!adev->ras_enabled || !con)
2930 /* Need disable ras on all IPs here before ip [hw/sw]fini */
2932 amdgpu_ras_disable_all_features(adev, 0);
2933 amdgpu_ras_recovery_fini(adev);
2937 int amdgpu_ras_fini(struct amdgpu_device *adev)
2939 struct amdgpu_ras_block_list *ras_node, *tmp;
2940 struct amdgpu_ras_block_object *obj = NULL;
2941 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
2943 if (!adev->ras_enabled || !con)
2946 list_for_each_entry_safe(ras_node, tmp, &adev->ras_list, node) {
2947 if (ras_node->ras_obj) {
2948 obj = ras_node->ras_obj;
2949 if (amdgpu_ras_is_supported(adev, obj->ras_comm.block) &&
2951 obj->ras_fini(adev, &obj->ras_comm);
2953 amdgpu_ras_block_late_fini_default(adev, &obj->ras_comm);
2956 /* Clear ras blocks from ras_list and free ras block list node */
2957 list_del(&ras_node->node);
2961 amdgpu_ras_fs_fini(adev);
2962 amdgpu_ras_interrupt_remove_all(adev);
2964 WARN(con->features, "Feature mask is not cleared");
2967 amdgpu_ras_disable_all_features(adev, 1);
2969 cancel_delayed_work_sync(&con->ras_counte_delay_work);
2971 amdgpu_ras_set_context(adev, NULL);
2977 void amdgpu_ras_global_ras_isr(struct amdgpu_device *adev)
2979 if (atomic_cmpxchg(&amdgpu_ras_in_intr, 0, 1) == 0) {
2980 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev);
2982 dev_info(adev->dev, "uncorrectable hardware error"
2983 "(ERREVENT_ATHUB_INTERRUPT) detected!\n");
2985 ras->gpu_reset_flags |= AMDGPU_RAS_GPU_RESET_MODE1_RESET;
2986 amdgpu_ras_reset_gpu(adev);
2990 bool amdgpu_ras_need_emergency_restart(struct amdgpu_device *adev)
2992 if (adev->asic_type == CHIP_VEGA20 &&
2993 adev->pm.fw_version <= 0x283400) {
2994 return !(amdgpu_asic_reset_method(adev) == AMD_RESET_METHOD_BACO) &&
2995 amdgpu_ras_intr_triggered();
3001 void amdgpu_release_ras_context(struct amdgpu_device *adev)
3003 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
3008 if (!adev->ras_enabled && con->features & BIT(AMDGPU_RAS_BLOCK__GFX)) {
3009 con->features &= ~BIT(AMDGPU_RAS_BLOCK__GFX);
3010 amdgpu_ras_set_context(adev, NULL);
3015 #ifdef CONFIG_X86_MCE_AMD
3016 static struct amdgpu_device *find_adev(uint32_t node_id)
3019 struct amdgpu_device *adev = NULL;
3021 for (i = 0; i < mce_adev_list.num_gpu; i++) {
3022 adev = mce_adev_list.devs[i];
3024 if (adev && adev->gmc.xgmi.connected_to_cpu &&
3025 adev->gmc.xgmi.physical_node_id == node_id)
3033 #define GET_MCA_IPID_GPUID(m) (((m) >> 44) & 0xF)
3034 #define GET_UMC_INST(m) (((m) >> 21) & 0x7)
3035 #define GET_CHAN_INDEX(m) ((((m) >> 12) & 0x3) | (((m) >> 18) & 0x4))
3036 #define GPU_ID_OFFSET 8
3038 static int amdgpu_bad_page_notifier(struct notifier_block *nb,
3039 unsigned long val, void *data)
3041 struct mce *m = (struct mce *)data;
3042 struct amdgpu_device *adev = NULL;
3043 uint32_t gpu_id = 0;
3044 uint32_t umc_inst = 0, ch_inst = 0;
3047 * If the error was generated in UMC_V2, which belongs to GPU UMCs,
3048 * and error occurred in DramECC (Extended error code = 0) then only
3049 * process the error, else bail out.
3051 if (!m || !((smca_get_bank_type(m->extcpu, m->bank) == SMCA_UMC_V2) &&
3052 (XEC(m->status, 0x3f) == 0x0)))
3056 * If it is correctable error, return.
3058 if (mce_is_correctable(m))
3062 * GPU Id is offset by GPU_ID_OFFSET in MCA_IPID_UMC register.
3064 gpu_id = GET_MCA_IPID_GPUID(m->ipid) - GPU_ID_OFFSET;
3066 adev = find_adev(gpu_id);
3068 DRM_WARN("%s: Unable to find adev for gpu_id: %d\n", __func__,
3074 * If it is uncorrectable error, then find out UMC instance and
3077 umc_inst = GET_UMC_INST(m->ipid);
3078 ch_inst = GET_CHAN_INDEX(m->ipid);
3080 dev_info(adev->dev, "Uncorrectable error detected in UMC inst: %d, chan_idx: %d",
3083 if (!amdgpu_umc_page_retirement_mca(adev, m->addr, ch_inst, umc_inst))
3089 static struct notifier_block amdgpu_bad_page_nb = {
3090 .notifier_call = amdgpu_bad_page_notifier,
3091 .priority = MCE_PRIO_UC,
3094 static void amdgpu_register_bad_pages_mca_notifier(struct amdgpu_device *adev)
3097 * Add the adev to the mce_adev_list.
3098 * During mode2 reset, amdgpu device is temporarily
3099 * removed from the mgpu_info list which can cause
3100 * page retirement to fail.
3101 * Use this list instead of mgpu_info to find the amdgpu
3102 * device on which the UMC error was reported.
3104 mce_adev_list.devs[mce_adev_list.num_gpu++] = adev;
3107 * Register the x86 notifier only once
3108 * with MCE subsystem.
3110 if (notifier_registered == false) {
3111 mce_register_decode_chain(&amdgpu_bad_page_nb);
3112 notifier_registered = true;
3117 struct amdgpu_ras *amdgpu_ras_get_context(struct amdgpu_device *adev)
3122 return adev->psp.ras_context.ras;
3125 int amdgpu_ras_set_context(struct amdgpu_device *adev, struct amdgpu_ras *ras_con)
3130 adev->psp.ras_context.ras = ras_con;
3134 /* check if ras is supported on block, say, sdma, gfx */
3135 int amdgpu_ras_is_supported(struct amdgpu_device *adev,
3139 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev);
3141 if (block >= AMDGPU_RAS_BLOCK_COUNT)
3144 ret = ras && (adev->ras_enabled & (1 << block));
3146 /* For the special asic with mem ecc enabled but sram ecc
3147 * not enabled, even if the ras block is not supported on
3148 * .ras_enabled, if the asic supports poison mode and the
3149 * ras block has ras configuration, it can be considered
3150 * that the ras block supports ras function.
3153 (block == AMDGPU_RAS_BLOCK__GFX ||
3154 block == AMDGPU_RAS_BLOCK__SDMA ||
3155 block == AMDGPU_RAS_BLOCK__VCN ||
3156 block == AMDGPU_RAS_BLOCK__JPEG) &&
3157 amdgpu_ras_is_poison_mode_supported(adev) &&
3158 amdgpu_ras_get_ras_block(adev, block, 0))
3164 int amdgpu_ras_reset_gpu(struct amdgpu_device *adev)
3166 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev);
3168 if (atomic_cmpxchg(&ras->in_recovery, 0, 1) == 0)
3169 amdgpu_reset_domain_schedule(ras->adev->reset_domain, &ras->recovery_work);
3174 /* Register each ip ras block into amdgpu ras */
3175 int amdgpu_ras_register_ras_block(struct amdgpu_device *adev,
3176 struct amdgpu_ras_block_object *ras_block_obj)
3178 struct amdgpu_ras_block_list *ras_node;
3179 if (!adev || !ras_block_obj)
3182 ras_node = kzalloc(sizeof(*ras_node), GFP_KERNEL);
3186 INIT_LIST_HEAD(&ras_node->node);
3187 ras_node->ras_obj = ras_block_obj;
3188 list_add_tail(&ras_node->node, &adev->ras_list);
3193 void amdgpu_ras_get_error_type_name(uint32_t err_type, char *err_type_name)
3199 case AMDGPU_RAS_ERROR__SINGLE_CORRECTABLE:
3200 sprintf(err_type_name, "correctable");
3202 case AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE:
3203 sprintf(err_type_name, "uncorrectable");
3206 sprintf(err_type_name, "unknown");
3211 bool amdgpu_ras_inst_get_memory_id_field(struct amdgpu_device *adev,
3212 const struct amdgpu_ras_err_status_reg_entry *reg_entry,
3214 uint32_t *memory_id)
3216 uint32_t err_status_lo_data, err_status_lo_offset;
3221 err_status_lo_offset =
3222 AMDGPU_RAS_REG_ENTRY_OFFSET(reg_entry->hwip, instance,
3223 reg_entry->seg_lo, reg_entry->reg_lo);
3224 err_status_lo_data = RREG32(err_status_lo_offset);
3226 if ((reg_entry->flags & AMDGPU_RAS_ERR_STATUS_VALID) &&
3227 !REG_GET_FIELD(err_status_lo_data, ERR_STATUS_LO, ERR_STATUS_VALID_FLAG))
3230 *memory_id = REG_GET_FIELD(err_status_lo_data, ERR_STATUS_LO, MEMORY_ID);
3235 bool amdgpu_ras_inst_get_err_cnt_field(struct amdgpu_device *adev,
3236 const struct amdgpu_ras_err_status_reg_entry *reg_entry,
3238 unsigned long *err_cnt)
3240 uint32_t err_status_hi_data, err_status_hi_offset;
3245 err_status_hi_offset =
3246 AMDGPU_RAS_REG_ENTRY_OFFSET(reg_entry->hwip, instance,
3247 reg_entry->seg_hi, reg_entry->reg_hi);
3248 err_status_hi_data = RREG32(err_status_hi_offset);
3250 if ((reg_entry->flags & AMDGPU_RAS_ERR_INFO_VALID) &&
3251 !REG_GET_FIELD(err_status_hi_data, ERR_STATUS_HI, ERR_INFO_VALID_FLAG))
3252 /* keep the check here in case we need to refer to the result later */
3253 dev_dbg(adev->dev, "Invalid err_info field\n");
3255 /* read err count */
3256 *err_cnt = REG_GET_FIELD(err_status_hi_data, ERR_STATUS, ERR_CNT);
3261 void amdgpu_ras_inst_query_ras_error_count(struct amdgpu_device *adev,
3262 const struct amdgpu_ras_err_status_reg_entry *reg_list,
3263 uint32_t reg_list_size,
3264 const struct amdgpu_ras_memory_id_entry *mem_list,
3265 uint32_t mem_list_size,
3268 unsigned long *err_count)
3271 unsigned long err_cnt;
3272 char err_type_name[16];
3275 for (i = 0; i < reg_list_size; i++) {
3276 /* query memory_id from err_status_lo */
3277 if (!amdgpu_ras_inst_get_memory_id_field(adev, ®_list[i],
3278 instance, &memory_id))
3281 /* query err_cnt from err_status_hi */
3282 if (!amdgpu_ras_inst_get_err_cnt_field(adev, ®_list[i],
3283 instance, &err_cnt) ||
3287 *err_count += err_cnt;
3289 /* log the errors */
3290 amdgpu_ras_get_error_type_name(err_type, err_type_name);
3292 /* memory_list is not supported */
3294 "%ld %s hardware errors detected in %s, instance: %d, memory_id: %d\n",
3295 err_cnt, err_type_name,
3296 reg_list[i].block_name,
3297 instance, memory_id);
3299 for (j = 0; j < mem_list_size; j++) {
3300 if (memory_id == mem_list[j].memory_id) {
3302 "%ld %s hardware errors detected in %s, instance: %d, memory block: %s\n",
3303 err_cnt, err_type_name,
3304 reg_list[i].block_name,
3305 instance, mem_list[j].name);
3313 void amdgpu_ras_inst_reset_ras_error_count(struct amdgpu_device *adev,
3314 const struct amdgpu_ras_err_status_reg_entry *reg_list,
3315 uint32_t reg_list_size,
3318 uint32_t err_status_lo_offset, err_status_hi_offset;
3321 for (i = 0; i < reg_list_size; i++) {
3322 err_status_lo_offset =
3323 AMDGPU_RAS_REG_ENTRY_OFFSET(reg_list[i].hwip, instance,
3324 reg_list[i].seg_lo, reg_list[i].reg_lo);
3325 err_status_hi_offset =
3326 AMDGPU_RAS_REG_ENTRY_OFFSET(reg_list[i].hwip, instance,
3327 reg_list[i].seg_hi, reg_list[i].reg_hi);
3328 WREG32(err_status_lo_offset, 0);
3329 WREG32(err_status_hi_offset, 0);