drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c

   1 /*
   2  * Copyright 2018 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  *
  23  */
  24 #include <linux/debugfs.h>
  25 #include <linux/list.h>
  26 #include <linux/module.h>
  27 #include <linux/uaccess.h>
  28 #include <linux/reboot.h>
  29 #include <linux/syscalls.h>
  30 #include <linux/pm_runtime.h>
  31
  32 #include "amdgpu.h"
  33 #include "amdgpu_ras.h"
  34 #include "amdgpu_atomfirmware.h"
  35 #include "amdgpu_xgmi.h"
  36 #include "ivsrcid/nbio/irqsrcs_nbif_7_4.h"
  37 #include "nbio_v4_3.h"
  38 #include "nbio_v7_9.h"
  39 #include "atom.h"
  40 #include "amdgpu_reset.h"
  41
  42 #ifdef CONFIG_X86_MCE_AMD
  43 #include <asm/mce.h>
  44
  45 static bool notifier_registered;
  46 #endif
  47 static const char *RAS_FS_NAME = "ras";
  48
  49 const char *ras_error_string[] = {
  50         "none",
  51         "parity",
  52         "single_correctable",
  53         "multi_uncorrectable",
  54         "poison",
  55 };
  56
  57 const char *ras_block_string[] = {
  58         "umc",
  59         "sdma",
  60         "gfx",
  61         "mmhub",
  62         "athub",
  63         "pcie_bif",
  64         "hdp",
  65         "xgmi_wafl",
  66         "df",
  67         "smn",
  68         "sem",
  69         "mp0",
  70         "mp1",
  71         "fuse",
  72         "mca",
  73         "vcn",
  74         "jpeg",
  75 };
  76
  77 const char *ras_mca_block_string[] = {
  78         "mca_mp0",
  79         "mca_mp1",
  80         "mca_mpio",
  81         "mca_iohc",
  82 };
  83
  84 struct amdgpu_ras_block_list {
  85         /* ras block link */
  86         struct list_head node;
  87
  88         struct amdgpu_ras_block_object *ras_obj;
  89 };
  90
  91 const char *get_ras_block_str(struct ras_common_if *ras_block)
  92 {
  93         if (!ras_block)
  94                 return "NULL";
  95
  96         if (ras_block->block >= AMDGPU_RAS_BLOCK_COUNT)
  97                 return "OUT OF RANGE";
  98
  99         if (ras_block->block == AMDGPU_RAS_BLOCK__MCA)
 100                 return ras_mca_block_string[ras_block->sub_block_index];
 101
 102         return ras_block_string[ras_block->block];
 103 }
 104
 105 #define ras_block_str(_BLOCK_) \
 106         (((_BLOCK_) < ARRAY_SIZE(ras_block_string)) ? ras_block_string[_BLOCK_] : "Out Of Range")
 107
 108 #define ras_err_str(i) (ras_error_string[ffs(i)])
 109
 110 #define RAS_DEFAULT_FLAGS (AMDGPU_RAS_FLAG_INIT_BY_VBIOS)
 111
 112 /* inject address is 52 bits */
 113 #define RAS_UMC_INJECT_ADDR_LIMIT       (0x1ULL << 52)
 114
 115 /* typical ECC bad page rate is 1 bad page per 100MB VRAM */
 116 #define RAS_BAD_PAGE_COVER              (100 * 1024 * 1024ULL)
 117
 118 enum amdgpu_ras_retire_page_reservation {
 119         AMDGPU_RAS_RETIRE_PAGE_RESERVED,
 120         AMDGPU_RAS_RETIRE_PAGE_PENDING,
 121         AMDGPU_RAS_RETIRE_PAGE_FAULT,
 122 };
 123
 124 atomic_t amdgpu_ras_in_intr = ATOMIC_INIT(0);
 125
 126 static bool amdgpu_ras_check_bad_page_unlock(struct amdgpu_ras *con,
 127                                 uint64_t addr);
 128 static bool amdgpu_ras_check_bad_page(struct amdgpu_device *adev,
 129                                 uint64_t addr);
 130 #ifdef CONFIG_X86_MCE_AMD
 131 static void amdgpu_register_bad_pages_mca_notifier(struct amdgpu_device *adev);
 132 struct mce_notifier_adev_list {
 133         struct amdgpu_device *devs[MAX_GPU_INSTANCE];
 134         int num_gpu;
 135 };
 136 static struct mce_notifier_adev_list mce_adev_list;
 137 #endif
 138
 139 void amdgpu_ras_set_error_query_ready(struct amdgpu_device *adev, bool ready)
 140 {
 141         if (adev && amdgpu_ras_get_context(adev))
 142                 amdgpu_ras_get_context(adev)->error_query_ready = ready;
 143 }
 144
 145 static bool amdgpu_ras_get_error_query_ready(struct amdgpu_device *adev)
 146 {
 147         if (adev && amdgpu_ras_get_context(adev))
 148                 return amdgpu_ras_get_context(adev)->error_query_ready;
 149
 150         return false;
 151 }
 152
 153 static int amdgpu_reserve_page_direct(struct amdgpu_device *adev, uint64_t address)
 154 {
 155         struct ras_err_data err_data = {0, 0, 0, NULL};
 156         struct eeprom_table_record err_rec;
 157
 158         if ((address >= adev->gmc.mc_vram_size) ||
 159             (address >= RAS_UMC_INJECT_ADDR_LIMIT)) {
 160                 dev_warn(adev->dev,
 161                          "RAS WARN: input address 0x%llx is invalid.\n",
 162                          address);
 163                 return -EINVAL;
 164         }
 165
 166         if (amdgpu_ras_check_bad_page(adev, address)) {
 167                 dev_warn(adev->dev,
 168                          "RAS WARN: 0x%llx has already been marked as bad page!\n",
 169                          address);
 170                 return 0;
 171         }
 172
 173         memset(&err_rec, 0x0, sizeof(struct eeprom_table_record));
 174         err_data.err_addr = &err_rec;
 175         amdgpu_umc_fill_error_record(&err_data, address, address, 0, 0);
 176
 177         if (amdgpu_bad_page_threshold != 0) {
 178                 amdgpu_ras_add_bad_pages(adev, err_data.err_addr,
 179                                          err_data.err_addr_cnt);
 180                 amdgpu_ras_save_bad_pages(adev, NULL);
 181         }
 182
 183         dev_warn(adev->dev, "WARNING: THIS IS ONLY FOR TEST PURPOSES AND WILL CORRUPT RAS EEPROM\n");
 184         dev_warn(adev->dev, "Clear EEPROM:\n");
 185         dev_warn(adev->dev, "    echo 1 > /sys/kernel/debug/dri/0/ras/ras_eeprom_reset\n");
 186
 187         return 0;
 188 }
 189
 190 static ssize_t amdgpu_ras_debugfs_read(struct file *f, char __user *buf,
 191                                         size_t size, loff_t *pos)
 192 {
 193         struct ras_manager *obj = (struct ras_manager *)file_inode(f)->i_private;
 194         struct ras_query_if info = {
 195                 .head = obj->head,
 196         };
 197         ssize_t s;
 198         char val[128];
 199
 200         if (amdgpu_ras_query_error_status(obj->adev, &info))
 201                 return -EINVAL;
 202
 203         /* Hardware counter will be reset automatically after the query on Vega20 and Arcturus */
 204         if (obj->adev->ip_versions[MP0_HWIP][0] != IP_VERSION(11, 0, 2) &&
 205             obj->adev->ip_versions[MP0_HWIP][0] != IP_VERSION(11, 0, 4)) {
 206                 if (amdgpu_ras_reset_error_status(obj->adev, info.head.block))
 207                         dev_warn(obj->adev->dev, "Failed to reset error counter and error status");
 208         }
 209
 210         s = snprintf(val, sizeof(val), "%s: %lu\n%s: %lu\n",
 211                         "ue", info.ue_count,
 212                         "ce", info.ce_count);
 213         if (*pos >= s)
 214                 return 0;
 215
 216         s -= *pos;
 217         s = min_t(u64, s, size);
 218
 219
 220         if (copy_to_user(buf, &val[*pos], s))
 221                 return -EINVAL;
 222
 223         *pos += s;
 224
 225         return s;
 226 }
 227
 228 static const struct file_operations amdgpu_ras_debugfs_ops = {
 229         .owner = THIS_MODULE,
 230         .read = amdgpu_ras_debugfs_read,
 231         .write = NULL,
 232         .llseek = default_llseek
 233 };
 234
 235 static int amdgpu_ras_find_block_id_by_name(const char *name, int *block_id)
 236 {
 237         int i;
 238
 239         for (i = 0; i < ARRAY_SIZE(ras_block_string); i++) {
 240                 *block_id = i;
 241                 if (strcmp(name, ras_block_string[i]) == 0)
 242                         return 0;
 243         }
 244         return -EINVAL;
 245 }
 246
 247 static int amdgpu_ras_debugfs_ctrl_parse_data(struct file *f,
 248                 const char __user *buf, size_t size,
 249                 loff_t *pos, struct ras_debug_if *data)
 250 {
 251         ssize_t s = min_t(u64, 64, size);
 252         char str[65];
 253         char block_name[33];
 254         char err[9] = "ue";
 255         int op = -1;
 256         int block_id;
 257         uint32_t sub_block;
 258         u64 address, value;
 259         /* default value is 0 if the mask is not set by user */
 260         u32 instance_mask = 0;
 261
 262         if (*pos)
 263                 return -EINVAL;
 264         *pos = size;
 265
 266         memset(str, 0, sizeof(str));
 267         memset(data, 0, sizeof(*data));
 268
 269         if (copy_from_user(str, buf, s))
 270                 return -EINVAL;
 271
 272         if (sscanf(str, "disable %32s", block_name) == 1)
 273                 op = 0;
 274         else if (sscanf(str, "enable %32s %8s", block_name, err) == 2)
 275                 op = 1;
 276         else if (sscanf(str, "inject %32s %8s", block_name, err) == 2)
 277                 op = 2;
 278         else if (strstr(str, "retire_page") != NULL)
 279                 op = 3;
 280         else if (str[0] && str[1] && str[2] && str[3])
 281                 /* ascii string, but commands are not matched. */
 282                 return -EINVAL;
 283
 284         if (op != -1) {
 285                 if (op == 3) {
 286                         if (sscanf(str, "%*s 0x%llx", &address) != 1 &&
 287                             sscanf(str, "%*s %llu", &address) != 1)
 288                                 return -EINVAL;
 289
 290                         data->op = op;
 291                         data->inject.address = address;
 292
 293                         return 0;
 294                 }
 295
 296                 if (amdgpu_ras_find_block_id_by_name(block_name, &block_id))
 297                         return -EINVAL;
 298
 299                 data->head.block = block_id;
 300                 /* only ue and ce errors are supported */
 301                 if (!memcmp("ue", err, 2))
 302                         data->head.type = AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE;
 303                 else if (!memcmp("ce", err, 2))
 304                         data->head.type = AMDGPU_RAS_ERROR__SINGLE_CORRECTABLE;
 305                 else
 306                         return -EINVAL;
 307
 308                 data->op = op;
 309
 310                 if (op == 2) {
 311                         if (sscanf(str, "%*s %*s %*s 0x%x 0x%llx 0x%llx 0x%x",
 312                                    &sub_block, &address, &value, &instance_mask) != 4 &&
 313                             sscanf(str, "%*s %*s %*s %u %llu %llu %u",
 314                                    &sub_block, &address, &value, &instance_mask) != 4 &&
 315                                 sscanf(str, "%*s %*s %*s 0x%x 0x%llx 0x%llx",
 316                                    &sub_block, &address, &value) != 3 &&
 317                             sscanf(str, "%*s %*s %*s %u %llu %llu",
 318                                    &sub_block, &address, &value) != 3)
 319                                 return -EINVAL;
 320                         data->head.sub_block_index = sub_block;
 321                         data->inject.address = address;
 322                         data->inject.value = value;
 323                         data->inject.instance_mask = instance_mask;
 324                 }
 325         } else {
 326                 if (size < sizeof(*data))
 327                         return -EINVAL;
 328
 329                 if (copy_from_user(data, buf, sizeof(*data)))
 330                         return -EINVAL;
 331         }
 332
 333         return 0;
 334 }
 335
 336 static void amdgpu_ras_instance_mask_check(struct amdgpu_device *adev,
 337                                 struct ras_debug_if *data)
 338 {
 339         int num_xcc = adev->gfx.xcc_mask ? NUM_XCC(adev->gfx.xcc_mask) : 1;
 340         uint32_t mask, inst_mask = data->inject.instance_mask;
 341
 342         /* no need to set instance mask if there is only one instance */
 343         if (num_xcc <= 1 && inst_mask) {
 344                 data->inject.instance_mask = 0;
 345                 dev_dbg(adev->dev,
 346                         "RAS inject mask(0x%x) isn't supported and force it to 0.\n",
 347                         inst_mask);
 348
 349                 return;
 350         }
 351
 352         switch (data->head.block) {
 353         case AMDGPU_RAS_BLOCK__GFX:
 354                 mask = GENMASK(num_xcc - 1, 0);
 355                 break;
 356         case AMDGPU_RAS_BLOCK__SDMA:
 357                 mask = GENMASK(adev->sdma.num_instances - 1, 0);
 358                 break;
 359         case AMDGPU_RAS_BLOCK__VCN:
 360         case AMDGPU_RAS_BLOCK__JPEG:
 361                 mask = GENMASK(adev->vcn.num_vcn_inst - 1, 0);
 362                 break;
 363         default:
 364                 mask = inst_mask;
 365                 break;
 366         }
 367
 368         /* remove invalid bits in instance mask */
 369         data->inject.instance_mask &= mask;
 370         if (inst_mask != data->inject.instance_mask)
 371                 dev_dbg(adev->dev,
 372                         "Adjust RAS inject mask 0x%x to 0x%x\n",
 373                         inst_mask, data->inject.instance_mask);
 374 }
 375
 376 /**
 377  * DOC: AMDGPU RAS debugfs control interface
 378  *
 379  * The control interface accepts struct ras_debug_if which has two members.
 380  *
 381  * First member: ras_debug_if::head or ras_debug_if::inject.
 382  *
 383  * head is used to indicate which IP block will be under control.
 384  *
 385  * head has four members, they are block, type, sub_block_index, name.
 386  * block: which IP will be under control.
 387  * type: what kind of error will be enabled/disabled/injected.
 388  * sub_block_index: some IPs have subcomponets. say, GFX, sDMA.
 389  * name: the name of IP.
 390  *
 391  * inject has three more members than head, they are address, value and mask.
 392  * As their names indicate, inject operation will write the
 393  * value to the address.
 394  *
 395  * The second member: struct ras_debug_if::op.
 396  * It has three kinds of operations.
 397  *
 398  * - 0: disable RAS on the block. Take ::head as its data.
 399  * - 1: enable RAS on the block. Take ::head as its data.
 400  * - 2: inject errors on the block. Take ::inject as its data.
 401  *
 402  * How to use the interface?
 403  *
 404  * In a program
 405  *
 406  * Copy the struct ras_debug_if in your code and initialize it.
 407  * Write the struct to the control interface.
 408  *
 409  * From shell
 410  *
 411  * .. code-block:: bash
 412  *
 413  *      echo "disable <block>" > /sys/kernel/debug/dri/<N>/ras/ras_ctrl
 414  *      echo "enable  <block> <error>" > /sys/kernel/debug/dri/<N>/ras/ras_ctrl
 415  *      echo "inject  <block> <error> <sub-block> <address> <value> <mask>" > /sys/kernel/debug/dri/<N>/ras/ras_ctrl
 416  *
 417  * Where N, is the card which you want to affect.
 418  *
 419  * "disable" requires only the block.
 420  * "enable" requires the block and error type.
 421  * "inject" requires the block, error type, address, and value.
 422  *
 423  * The block is one of: umc, sdma, gfx, etc.
 424  *      see ras_block_string[] for details
 425  *
 426  * The error type is one of: ue, ce, where,
 427  *      ue is multi-uncorrectable
 428  *      ce is single-correctable
 429  *
 430  * The sub-block is a the sub-block index, pass 0 if there is no sub-block.
 431  * The address and value are hexadecimal numbers, leading 0x is optional.
 432  * The mask means instance mask, is optional, default value is 0x1.
 433  *
 434  * For instance,
 435  *
 436  * .. code-block:: bash
 437  *
 438  *      echo inject umc ue 0x0 0x0 0x0 > /sys/kernel/debug/dri/0/ras/ras_ctrl
 439  *      echo inject umc ce 0 0 0 3 > /sys/kernel/debug/dri/0/ras/ras_ctrl
 440  *      echo disable umc > /sys/kernel/debug/dri/0/ras/ras_ctrl
 441  *
 442  * How to check the result of the operation?
 443  *
 444  * To check disable/enable, see "ras" features at,
 445  * /sys/class/drm/card[0/1/2...]/device/ras/features
 446  *
 447  * To check inject, see the corresponding error count at,
 448  * /sys/class/drm/card[0/1/2...]/device/ras/[gfx|sdma|umc|...]_err_count
 449  *
 450  * .. note::
 451  *      Operations are only allowed on blocks which are supported.
 452  *      Check the "ras" mask at /sys/module/amdgpu/parameters/ras_mask
 453  *      to see which blocks support RAS on a particular asic.
 454  *
 455  */
 456 static ssize_t amdgpu_ras_debugfs_ctrl_write(struct file *f,
 457                                              const char __user *buf,
 458                                              size_t size, loff_t *pos)
 459 {
 460         struct amdgpu_device *adev = (struct amdgpu_device *)file_inode(f)->i_private;
 461         struct ras_debug_if data;
 462         int ret = 0;
 463
 464         if (!amdgpu_ras_get_error_query_ready(adev)) {
 465                 dev_warn(adev->dev, "RAS WARN: error injection "
 466                                 "currently inaccessible\n");
 467                 return size;
 468         }
 469
 470         ret = amdgpu_ras_debugfs_ctrl_parse_data(f, buf, size, pos, &data);
 471         if (ret)
 472                 return ret;
 473
 474         if (data.op == 3) {
 475                 ret = amdgpu_reserve_page_direct(adev, data.inject.address);
 476                 if (!ret)
 477                         return size;
 478                 else
 479                         return ret;
 480         }
 481
 482         if (!amdgpu_ras_is_supported(adev, data.head.block))
 483                 return -EINVAL;
 484
 485         switch (data.op) {
 486         case 0:
 487                 ret = amdgpu_ras_feature_enable(adev, &data.head, 0);
 488                 break;
 489         case 1:
 490                 ret = amdgpu_ras_feature_enable(adev, &data.head, 1);
 491                 break;
 492         case 2:
 493                 if ((data.inject.address >= adev->gmc.mc_vram_size &&
 494                     adev->gmc.mc_vram_size) ||
 495                     (data.inject.address >= RAS_UMC_INJECT_ADDR_LIMIT)) {
 496                         dev_warn(adev->dev, "RAS WARN: input address "
 497                                         "0x%llx is invalid.",
 498                                         data.inject.address);
 499                         ret = -EINVAL;
 500                         break;
 501                 }
 502
 503                 /* umc ce/ue error injection for a bad page is not allowed */
 504                 if ((data.head.block == AMDGPU_RAS_BLOCK__UMC) &&
 505                     amdgpu_ras_check_bad_page(adev, data.inject.address)) {
 506                         dev_warn(adev->dev, "RAS WARN: inject: 0x%llx has "
 507                                  "already been marked as bad!\n",
 508                                  data.inject.address);
 509                         break;
 510                 }
 511
 512                 amdgpu_ras_instance_mask_check(adev, &data);
 513
 514                 /* data.inject.address is offset instead of absolute gpu address */
 515                 ret = amdgpu_ras_error_inject(adev, &data.inject);
 516                 break;
 517         default:
 518                 ret = -EINVAL;
 519                 break;
 520         }
 521
 522         if (ret)
 523                 return ret;
 524
 525         return size;
 526 }
 527
 528 /**
 529  * DOC: AMDGPU RAS debugfs EEPROM table reset interface
 530  *
 531  * Some boards contain an EEPROM which is used to persistently store a list of
 532  * bad pages which experiences ECC errors in vram.  This interface provides
 533  * a way to reset the EEPROM, e.g., after testing error injection.
 534  *
 535  * Usage:
 536  *
 537  * .. code-block:: bash
 538  *
 539  *      echo 1 > ../ras/ras_eeprom_reset
 540  *
 541  * will reset EEPROM table to 0 entries.
 542  *
 543  */
 544 static ssize_t amdgpu_ras_debugfs_eeprom_write(struct file *f,
 545                                                const char __user *buf,
 546                                                size_t size, loff_t *pos)
 547 {
 548         struct amdgpu_device *adev =
 549                 (struct amdgpu_device *)file_inode(f)->i_private;
 550         int ret;
 551
 552         ret = amdgpu_ras_eeprom_reset_table(
 553                 &(amdgpu_ras_get_context(adev)->eeprom_control));
 554
 555         if (!ret) {
 556                 /* Something was written to EEPROM.
 557                  */
 558                 amdgpu_ras_get_context(adev)->flags = RAS_DEFAULT_FLAGS;
 559                 return size;
 560         } else {
 561                 return ret;
 562         }
 563 }
 564
 565 static const struct file_operations amdgpu_ras_debugfs_ctrl_ops = {
 566         .owner = THIS_MODULE,
 567         .read = NULL,
 568         .write = amdgpu_ras_debugfs_ctrl_write,
 569         .llseek = default_llseek
 570 };
 571
 572 static const struct file_operations amdgpu_ras_debugfs_eeprom_ops = {
 573         .owner = THIS_MODULE,
 574         .read = NULL,
 575         .write = amdgpu_ras_debugfs_eeprom_write,
 576         .llseek = default_llseek
 577 };
 578
 579 /**
 580  * DOC: AMDGPU RAS sysfs Error Count Interface
 581  *
 582  * It allows the user to read the error count for each IP block on the gpu through
 583  * /sys/class/drm/card[0/1/2...]/device/ras/[gfx/sdma/...]_err_count
 584  *
 585  * It outputs the multiple lines which report the uncorrected (ue) and corrected
 586  * (ce) error counts.
 587  *
 588  * The format of one line is below,
 589  *
 590  * [ce|ue]: count
 591  *
 592  * Example:
 593  *
 594  * .. code-block:: bash
 595  *
 596  *      ue: 0
 597  *      ce: 1
 598  *
 599  */
 600 static ssize_t amdgpu_ras_sysfs_read(struct device *dev,
 601                 struct device_attribute *attr, char *buf)
 602 {
 603         struct ras_manager *obj = container_of(attr, struct ras_manager, sysfs_attr);
 604         struct ras_query_if info = {
 605                 .head = obj->head,
 606         };
 607
 608         if (!amdgpu_ras_get_error_query_ready(obj->adev))
 609                 return sysfs_emit(buf, "Query currently inaccessible\n");
 610
 611         if (amdgpu_ras_query_error_status(obj->adev, &info))
 612                 return -EINVAL;
 613
 614         if (obj->adev->ip_versions[MP0_HWIP][0] != IP_VERSION(11, 0, 2) &&
 615             obj->adev->ip_versions[MP0_HWIP][0] != IP_VERSION(11, 0, 4)) {
 616                 if (amdgpu_ras_reset_error_status(obj->adev, info.head.block))
 617                         dev_warn(obj->adev->dev, "Failed to reset error counter and error status");
 618         }
 619
 620         return sysfs_emit(buf, "%s: %lu\n%s: %lu\n", "ue", info.ue_count,
 621                           "ce", info.ce_count);
 622 }
 623
 624 /* obj begin */
 625
 626 #define get_obj(obj) do { (obj)->use++; } while (0)
 627 #define alive_obj(obj) ((obj)->use)
 628
 629 static inline void put_obj(struct ras_manager *obj)
 630 {
 631         if (obj && (--obj->use == 0))
 632                 list_del(&obj->node);
 633         if (obj && (obj->use < 0))
 634                 DRM_ERROR("RAS ERROR: Unbalance obj(%s) use\n", get_ras_block_str(&obj->head));
 635 }
 636
 637 /* make one obj and return it. */
 638 static struct ras_manager *amdgpu_ras_create_obj(struct amdgpu_device *adev,
 639                 struct ras_common_if *head)
 640 {
 641         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
 642         struct ras_manager *obj;
 643
 644         if (!adev->ras_enabled || !con)
 645                 return NULL;
 646
 647         if (head->block >= AMDGPU_RAS_BLOCK_COUNT)
 648                 return NULL;
 649
 650         if (head->block == AMDGPU_RAS_BLOCK__MCA) {
 651                 if (head->sub_block_index >= AMDGPU_RAS_MCA_BLOCK__LAST)
 652                         return NULL;
 653
 654                 obj = &con->objs[AMDGPU_RAS_BLOCK__LAST + head->sub_block_index];
 655         } else
 656                 obj = &con->objs[head->block];
 657
 658         /* already exist. return obj? */
 659         if (alive_obj(obj))
 660                 return NULL;
 661
 662         obj->head = *head;
 663         obj->adev = adev;
 664         list_add(&obj->node, &con->head);
 665         get_obj(obj);
 666
 667         return obj;
 668 }
 669
 670 /* return an obj equal to head, or the first when head is NULL */
 671 struct ras_manager *amdgpu_ras_find_obj(struct amdgpu_device *adev,
 672                 struct ras_common_if *head)
 673 {
 674         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
 675         struct ras_manager *obj;
 676         int i;
 677
 678         if (!adev->ras_enabled || !con)
 679                 return NULL;
 680
 681         if (head) {
 682                 if (head->block >= AMDGPU_RAS_BLOCK_COUNT)
 683                         return NULL;
 684
 685                 if (head->block == AMDGPU_RAS_BLOCK__MCA) {
 686                         if (head->sub_block_index >= AMDGPU_RAS_MCA_BLOCK__LAST)
 687                                 return NULL;
 688
 689                         obj = &con->objs[AMDGPU_RAS_BLOCK__LAST + head->sub_block_index];
 690                 } else
 691                         obj = &con->objs[head->block];
 692
 693                 if (alive_obj(obj))
 694                         return obj;
 695         } else {
 696                 for (i = 0; i < AMDGPU_RAS_BLOCK_COUNT + AMDGPU_RAS_MCA_BLOCK_COUNT; i++) {
 697                         obj = &con->objs[i];
 698                         if (alive_obj(obj))
 699                                 return obj;
 700                 }
 701         }
 702
 703         return NULL;
 704 }
 705 /* obj end */
 706
 707 /* feature ctl begin */
 708 static int amdgpu_ras_is_feature_allowed(struct amdgpu_device *adev,
 709                                          struct ras_common_if *head)
 710 {
 711         return adev->ras_hw_enabled & BIT(head->block);
 712 }
 713
 714 static int amdgpu_ras_is_feature_enabled(struct amdgpu_device *adev,
 715                 struct ras_common_if *head)
 716 {
 717         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
 718
 719         return con->features & BIT(head->block);
 720 }
 721
 722 /*
 723  * if obj is not created, then create one.
 724  * set feature enable flag.
 725  */
 726 static int __amdgpu_ras_feature_enable(struct amdgpu_device *adev,
 727                 struct ras_common_if *head, int enable)
 728 {
 729         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
 730         struct ras_manager *obj = amdgpu_ras_find_obj(adev, head);
 731
 732         /* If hardware does not support ras, then do not create obj.
 733          * But if hardware support ras, we can create the obj.
 734          * Ras framework checks con->hw_supported to see if it need do
 735          * corresponding initialization.
 736          * IP checks con->support to see if it need disable ras.
 737          */
 738         if (!amdgpu_ras_is_feature_allowed(adev, head))
 739                 return 0;
 740
 741         if (enable) {
 742                 if (!obj) {
 743                         obj = amdgpu_ras_create_obj(adev, head);
 744                         if (!obj)
 745                                 return -EINVAL;
 746                 } else {
 747                         /* In case we create obj somewhere else */
 748                         get_obj(obj);
 749                 }
 750                 con->features |= BIT(head->block);
 751         } else {
 752                 if (obj && amdgpu_ras_is_feature_enabled(adev, head)) {
 753                         con->features &= ~BIT(head->block);
 754                         put_obj(obj);
 755                 }
 756         }
 757
 758         return 0;
 759 }
 760
 761 /* wrapper of psp_ras_enable_features */
 762 int amdgpu_ras_feature_enable(struct amdgpu_device *adev,
 763                 struct ras_common_if *head, bool enable)
 764 {
 765         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
 766         union ta_ras_cmd_input *info;
 767         int ret;
 768
 769         if (!con)
 770                 return -EINVAL;
 771
 772         /* Do not enable ras feature if it is not allowed */
 773         if (enable &&
 774             head->block != AMDGPU_RAS_BLOCK__GFX &&
 775             !amdgpu_ras_is_feature_allowed(adev, head))
 776                 return 0;
 777
 778         /* Only enable gfx ras feature from host side */
 779         if (head->block == AMDGPU_RAS_BLOCK__GFX &&
 780             !amdgpu_sriov_vf(adev) &&
 781             !amdgpu_ras_intr_triggered()) {
 782                 info = kzalloc(sizeof(union ta_ras_cmd_input), GFP_KERNEL);
 783                 if (!info)
 784                         return -ENOMEM;
 785
 786                 if (!enable) {
 787                         info->disable_features = (struct ta_ras_disable_features_input) {
 788                                 .block_id =  amdgpu_ras_block_to_ta(head->block),
 789                                 .error_type = amdgpu_ras_error_to_ta(head->type),
 790                         };
 791                 } else {
 792                         info->enable_features = (struct ta_ras_enable_features_input) {
 793                                 .block_id =  amdgpu_ras_block_to_ta(head->block),
 794                                 .error_type = amdgpu_ras_error_to_ta(head->type),
 795                         };
 796                 }
 797
 798                 ret = psp_ras_enable_features(&adev->psp, info, enable);
 799                 if (ret) {
 800                         dev_err(adev->dev, "ras %s %s failed poison:%d ret:%d\n",
 801                                 enable ? "enable":"disable",
 802                                 get_ras_block_str(head),
 803                                 amdgpu_ras_is_poison_mode_supported(adev), ret);
 804                         return ret;
 805                 }
 806
 807                 kfree(info);
 808         }
 809
 810         /* setup the obj */
 811         __amdgpu_ras_feature_enable(adev, head, enable);
 812
 813         return 0;
 814 }
 815
 816 /* Only used in device probe stage and called only once. */
 817 int amdgpu_ras_feature_enable_on_boot(struct amdgpu_device *adev,
 818                 struct ras_common_if *head, bool enable)
 819 {
 820         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
 821         int ret;
 822
 823         if (!con)
 824                 return -EINVAL;
 825
 826         if (con->flags & AMDGPU_RAS_FLAG_INIT_BY_VBIOS) {
 827                 if (enable) {
 828                         /* There is no harm to issue a ras TA cmd regardless of
 829                          * the currecnt ras state.
 830                          * If current state == target state, it will do nothing
 831                          * But sometimes it requests driver to reset and repost
 832                          * with error code -EAGAIN.
 833                          */
 834                         ret = amdgpu_ras_feature_enable(adev, head, 1);
 835                         /* With old ras TA, we might fail to enable ras.
 836                          * Log it and just setup the object.
 837                          * TODO need remove this WA in the future.
 838                          */
 839                         if (ret == -EINVAL) {
 840                                 ret = __amdgpu_ras_feature_enable(adev, head, 1);
 841                                 if (!ret)
 842                                         dev_info(adev->dev,
 843                                                 "RAS INFO: %s setup object\n",
 844                                                 get_ras_block_str(head));
 845                         }
 846                 } else {
 847                         /* setup the object then issue a ras TA disable cmd.*/
 848                         ret = __amdgpu_ras_feature_enable(adev, head, 1);
 849                         if (ret)
 850                                 return ret;
 851
 852                         /* gfx block ras dsiable cmd must send to ras-ta */
 853                         if (head->block == AMDGPU_RAS_BLOCK__GFX)
 854                                 con->features |= BIT(head->block);
 855
 856                         ret = amdgpu_ras_feature_enable(adev, head, 0);
 857
 858                         /* clean gfx block ras features flag */
 859                         if (adev->ras_enabled && head->block == AMDGPU_RAS_BLOCK__GFX)
 860                                 con->features &= ~BIT(head->block);
 861                 }
 862         } else
 863                 ret = amdgpu_ras_feature_enable(adev, head, enable);
 864
 865         return ret;
 866 }
 867
 868 static int amdgpu_ras_disable_all_features(struct amdgpu_device *adev,
 869                 bool bypass)
 870 {
 871         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
 872         struct ras_manager *obj, *tmp;
 873
 874         list_for_each_entry_safe(obj, tmp, &con->head, node) {
 875                 /* bypass psp.
 876                  * aka just release the obj and corresponding flags
 877                  */
 878                 if (bypass) {
 879                         if (__amdgpu_ras_feature_enable(adev, &obj->head, 0))
 880                                 break;
 881                 } else {
 882                         if (amdgpu_ras_feature_enable(adev, &obj->head, 0))
 883                                 break;
 884                 }
 885         }
 886
 887         return con->features;
 888 }
 889
 890 static int amdgpu_ras_enable_all_features(struct amdgpu_device *adev,
 891                 bool bypass)
 892 {
 893         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
 894         int i;
 895         const enum amdgpu_ras_error_type default_ras_type = AMDGPU_RAS_ERROR__NONE;
 896
 897         for (i = 0; i < AMDGPU_RAS_BLOCK_COUNT; i++) {
 898                 struct ras_common_if head = {
 899                         .block = i,
 900                         .type = default_ras_type,
 901                         .sub_block_index = 0,
 902                 };
 903
 904                 if (i == AMDGPU_RAS_BLOCK__MCA)
 905                         continue;
 906
 907                 if (bypass) {
 908                         /*
 909                          * bypass psp. vbios enable ras for us.
 910                          * so just create the obj
 911                          */
 912                         if (__amdgpu_ras_feature_enable(adev, &head, 1))
 913                                 break;
 914                 } else {
 915                         if (amdgpu_ras_feature_enable(adev, &head, 1))
 916                                 break;
 917                 }
 918         }
 919
 920         for (i = 0; i < AMDGPU_RAS_MCA_BLOCK_COUNT; i++) {
 921                 struct ras_common_if head = {
 922                         .block = AMDGPU_RAS_BLOCK__MCA,
 923                         .type = default_ras_type,
 924                         .sub_block_index = i,
 925                 };
 926
 927                 if (bypass) {
 928                         /*
 929                          * bypass psp. vbios enable ras for us.
 930                          * so just create the obj
 931                          */
 932                         if (__amdgpu_ras_feature_enable(adev, &head, 1))
 933                                 break;
 934                 } else {
 935                         if (amdgpu_ras_feature_enable(adev, &head, 1))
 936                                 break;
 937                 }
 938         }
 939
 940         return con->features;
 941 }
 942 /* feature ctl end */
 943
 944 static int amdgpu_ras_block_match_default(struct amdgpu_ras_block_object *block_obj,
 945                 enum amdgpu_ras_block block)
 946 {
 947         if (!block_obj)
 948                 return -EINVAL;
 949
 950         if (block_obj->ras_comm.block == block)
 951                 return 0;
 952
 953         return -EINVAL;
 954 }
 955
 956 static struct amdgpu_ras_block_object *amdgpu_ras_get_ras_block(struct amdgpu_device *adev,
 957                                         enum amdgpu_ras_block block, uint32_t sub_block_index)
 958 {
 959         struct amdgpu_ras_block_list *node, *tmp;
 960         struct amdgpu_ras_block_object *obj;
 961
 962         if (block >= AMDGPU_RAS_BLOCK__LAST)
 963                 return NULL;
 964
 965         list_for_each_entry_safe(node, tmp, &adev->ras_list, node) {
 966                 if (!node->ras_obj) {
 967                         dev_warn(adev->dev, "Warning: abnormal ras list node.\n");
 968                         continue;
 969                 }
 970
 971                 obj = node->ras_obj;
 972                 if (obj->ras_block_match) {
 973                         if (obj->ras_block_match(obj, block, sub_block_index) == 0)
 974                                 return obj;
 975                 } else {
 976                         if (amdgpu_ras_block_match_default(obj, block) == 0)
 977                                 return obj;
 978                 }
 979         }
 980
 981         return NULL;
 982 }
 983
 984 static void amdgpu_ras_get_ecc_info(struct amdgpu_device *adev, struct ras_err_data *err_data)
 985 {
 986         struct amdgpu_ras *ras = amdgpu_ras_get_context(adev);
 987         int ret = 0;
 988
 989         /*
 990          * choosing right query method according to
 991          * whether smu support query error information
 992          */
 993         ret = amdgpu_dpm_get_ecc_info(adev, (void *)&(ras->umc_ecc));
 994         if (ret == -EOPNOTSUPP) {
 995                 if (adev->umc.ras && adev->umc.ras->ras_block.hw_ops &&
 996                         adev->umc.ras->ras_block.hw_ops->query_ras_error_count)
 997                         adev->umc.ras->ras_block.hw_ops->query_ras_error_count(adev, err_data);
 998
 999                 /* umc query_ras_error_address is also responsible for clearing
1000                  * error status
1001                  */
1002                 if (adev->umc.ras && adev->umc.ras->ras_block.hw_ops &&
1003                     adev->umc.ras->ras_block.hw_ops->query_ras_error_address)
1004                         adev->umc.ras->ras_block.hw_ops->query_ras_error_address(adev, err_data);
1005         } else if (!ret) {
1006                 if (adev->umc.ras &&
1007                         adev->umc.ras->ecc_info_query_ras_error_count)
1008                         adev->umc.ras->ecc_info_query_ras_error_count(adev, err_data);
1009
1010                 if (adev->umc.ras &&
1011                         adev->umc.ras->ecc_info_query_ras_error_address)
1012                         adev->umc.ras->ecc_info_query_ras_error_address(adev, err_data);
1013         }
1014 }
1015
1016 /* query/inject/cure begin */
1017 int amdgpu_ras_query_error_status(struct amdgpu_device *adev,
1018                                   struct ras_query_if *info)
1019 {
1020         struct amdgpu_ras_block_object *block_obj = NULL;
1021         struct ras_manager *obj = amdgpu_ras_find_obj(adev, &info->head);
1022         struct ras_err_data err_data = {0, 0, 0, NULL};
1023
1024         if (!obj)
1025                 return -EINVAL;
1026
1027         if (info->head.block == AMDGPU_RAS_BLOCK__UMC) {
1028                 amdgpu_ras_get_ecc_info(adev, &err_data);
1029         } else {
1030                 block_obj = amdgpu_ras_get_ras_block(adev, info->head.block, 0);
1031                 if (!block_obj || !block_obj->hw_ops)   {
1032                         dev_dbg_once(adev->dev, "%s doesn't config RAS function\n",
1033                                      get_ras_block_str(&info->head));
1034                         return -EINVAL;
1035                 }
1036
1037                 if (block_obj->hw_ops->query_ras_error_count)
1038                         block_obj->hw_ops->query_ras_error_count(adev, &err_data);
1039
1040                 if ((info->head.block == AMDGPU_RAS_BLOCK__SDMA) ||
1041                     (info->head.block == AMDGPU_RAS_BLOCK__GFX) ||
1042                     (info->head.block == AMDGPU_RAS_BLOCK__MMHUB)) {
1043                                 if (block_obj->hw_ops->query_ras_error_status)
1044                                         block_obj->hw_ops->query_ras_error_status(adev);
1045                         }
1046         }
1047
1048         obj->err_data.ue_count += err_data.ue_count;
1049         obj->err_data.ce_count += err_data.ce_count;
1050
1051         info->ue_count = obj->err_data.ue_count;
1052         info->ce_count = obj->err_data.ce_count;
1053
1054         if (err_data.ce_count) {
1055                 if (!adev->aid_mask &&
1056                     adev->smuio.funcs &&
1057                     adev->smuio.funcs->get_socket_id &&
1058                     adev->smuio.funcs->get_die_id) {
1059                         dev_info(adev->dev, "socket: %d, die: %d "
1060                                         "%ld correctable hardware errors "
1061                                         "detected in %s block, no user "
1062                                         "action is needed.\n",
1063                                         adev->smuio.funcs->get_socket_id(adev),
1064                                         adev->smuio.funcs->get_die_id(adev),
1065                                         obj->err_data.ce_count,
1066                                         get_ras_block_str(&info->head));
1067                 } else {
1068                         dev_info(adev->dev, "%ld correctable hardware errors "
1069                                         "detected in %s block, no user "
1070                                         "action is needed.\n",
1071                                         obj->err_data.ce_count,
1072                                         get_ras_block_str(&info->head));
1073                 }
1074         }
1075         if (err_data.ue_count) {
1076                 if (!adev->aid_mask &&
1077                     adev->smuio.funcs &&
1078                     adev->smuio.funcs->get_socket_id &&
1079                     adev->smuio.funcs->get_die_id) {
1080                         dev_info(adev->dev, "socket: %d, die: %d "
1081                                         "%ld uncorrectable hardware errors "
1082                                         "detected in %s block\n",
1083                                         adev->smuio.funcs->get_socket_id(adev),
1084                                         adev->smuio.funcs->get_die_id(adev),
1085                                         obj->err_data.ue_count,
1086                                         get_ras_block_str(&info->head));
1087                 } else {
1088                         dev_info(adev->dev, "%ld uncorrectable hardware errors "
1089                                         "detected in %s block\n",
1090                                         obj->err_data.ue_count,
1091                                         get_ras_block_str(&info->head));
1092                 }
1093         }
1094
1095         return 0;
1096 }
1097
1098 int amdgpu_ras_reset_error_status(struct amdgpu_device *adev,
1099                 enum amdgpu_ras_block block)
1100 {
1101         struct amdgpu_ras_block_object *block_obj = amdgpu_ras_get_ras_block(adev, block, 0);
1102
1103         if (!amdgpu_ras_is_supported(adev, block))
1104                 return -EINVAL;
1105
1106         if (!block_obj || !block_obj->hw_ops)   {
1107                 dev_dbg_once(adev->dev, "%s doesn't config RAS function\n",
1108                              ras_block_str(block));
1109                 return -EINVAL;
1110         }
1111
1112         if (block_obj->hw_ops->reset_ras_error_count)
1113                 block_obj->hw_ops->reset_ras_error_count(adev);
1114
1115         if ((block == AMDGPU_RAS_BLOCK__GFX) ||
1116             (block == AMDGPU_RAS_BLOCK__MMHUB)) {
1117                 if (block_obj->hw_ops->reset_ras_error_status)
1118                         block_obj->hw_ops->reset_ras_error_status(adev);
1119         }
1120
1121         return 0;
1122 }
1123
1124 /* wrapper of psp_ras_trigger_error */
1125 int amdgpu_ras_error_inject(struct amdgpu_device *adev,
1126                 struct ras_inject_if *info)
1127 {
1128         struct ras_manager *obj = amdgpu_ras_find_obj(adev, &info->head);
1129         struct ta_ras_trigger_error_input block_info = {
1130                 .block_id =  amdgpu_ras_block_to_ta(info->head.block),
1131                 .inject_error_type = amdgpu_ras_error_to_ta(info->head.type),
1132                 .sub_block_index = info->head.sub_block_index,
1133                 .address = info->address,
1134                 .value = info->value,
1135         };
1136         int ret = -EINVAL;
1137         struct amdgpu_ras_block_object *block_obj = amdgpu_ras_get_ras_block(adev,
1138                                                         info->head.block,
1139                                                         info->head.sub_block_index);
1140
1141         /* inject on guest isn't allowed, return success directly */
1142         if (amdgpu_sriov_vf(adev))
1143                 return 0;
1144
1145         if (!obj)
1146                 return -EINVAL;
1147
1148         if (!block_obj || !block_obj->hw_ops)   {
1149                 dev_dbg_once(adev->dev, "%s doesn't config RAS function\n",
1150                              get_ras_block_str(&info->head));
1151                 return -EINVAL;
1152         }
1153
1154         /* Calculate XGMI relative offset */
1155         if (adev->gmc.xgmi.num_physical_nodes > 1 &&
1156             info->head.block != AMDGPU_RAS_BLOCK__GFX) {
1157                 block_info.address =
1158                         amdgpu_xgmi_get_relative_phy_addr(adev,
1159                                                           block_info.address);
1160         }
1161
1162         if (block_obj->hw_ops->ras_error_inject) {
1163                 if (info->head.block == AMDGPU_RAS_BLOCK__GFX)
1164                         ret = block_obj->hw_ops->ras_error_inject(adev, info, info->instance_mask);
1165                 else /* Special ras_error_inject is defined (e.g: xgmi) */
1166                         ret = block_obj->hw_ops->ras_error_inject(adev, &block_info,
1167                                                 info->instance_mask);
1168         } else {
1169                 /* default path */
1170                 ret = psp_ras_trigger_error(&adev->psp, &block_info, info->instance_mask);
1171         }
1172
1173         if (ret)
1174                 dev_err(adev->dev, "ras inject %s failed %d\n",
1175                         get_ras_block_str(&info->head), ret);
1176
1177         return ret;
1178 }
1179
1180 /**
1181  * amdgpu_ras_query_error_count_helper -- Get error counter for specific IP
1182  * @adev: pointer to AMD GPU device
1183  * @ce_count: pointer to an integer to be set to the count of correctible errors.
1184  * @ue_count: pointer to an integer to be set to the count of uncorrectible errors.
1185  * @query_info: pointer to ras_query_if
1186  *
1187  * Return 0 for query success or do nothing, otherwise return an error
1188  * on failures
1189  */
1190 static int amdgpu_ras_query_error_count_helper(struct amdgpu_device *adev,
1191                                                unsigned long *ce_count,
1192                                                unsigned long *ue_count,
1193                                                struct ras_query_if *query_info)
1194 {
1195         int ret;
1196
1197         if (!query_info)
1198                 /* do nothing if query_info is not specified */
1199                 return 0;
1200
1201         ret = amdgpu_ras_query_error_status(adev, query_info);
1202         if (ret)
1203                 return ret;
1204
1205         *ce_count += query_info->ce_count;
1206         *ue_count += query_info->ue_count;
1207
1208         /* some hardware/IP supports read to clear
1209          * no need to explictly reset the err status after the query call */
1210         if (adev->ip_versions[MP0_HWIP][0] != IP_VERSION(11, 0, 2) &&
1211             adev->ip_versions[MP0_HWIP][0] != IP_VERSION(11, 0, 4)) {
1212                 if (amdgpu_ras_reset_error_status(adev, query_info->head.block))
1213                         dev_warn(adev->dev,
1214                                  "Failed to reset error counter and error status\n");
1215         }
1216
1217         return 0;
1218 }
1219
1220 /**
1221  * amdgpu_ras_query_error_count -- Get error counts of all IPs or specific IP
1222  * @adev: pointer to AMD GPU device
1223  * @ce_count: pointer to an integer to be set to the count of correctible errors.
1224  * @ue_count: pointer to an integer to be set to the count of uncorrectible
1225  * errors.
1226  * @query_info: pointer to ras_query_if if the query request is only for
1227  * specific ip block; if info is NULL, then the qurey request is for
1228  * all the ip blocks that support query ras error counters/status
1229  *
1230  * If set, @ce_count or @ue_count, count and return the corresponding
1231  * error counts in those integer pointers. Return 0 if the device
1232  * supports RAS. Return -EOPNOTSUPP if the device doesn't support RAS.
1233  */
1234 int amdgpu_ras_query_error_count(struct amdgpu_device *adev,
1235                                  unsigned long *ce_count,
1236                                  unsigned long *ue_count,
1237                                  struct ras_query_if *query_info)
1238 {
1239         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1240         struct ras_manager *obj;
1241         unsigned long ce, ue;
1242         int ret;
1243
1244         if (!adev->ras_enabled || !con)
1245                 return -EOPNOTSUPP;
1246
1247         /* Don't count since no reporting.
1248          */
1249         if (!ce_count && !ue_count)
1250                 return 0;
1251
1252         ce = 0;
1253         ue = 0;
1254         if (!query_info) {
1255                 /* query all the ip blocks that support ras query interface */
1256                 list_for_each_entry(obj, &con->head, node) {
1257                         struct ras_query_if info = {
1258                                 .head = obj->head,
1259                         };
1260
1261                         ret = amdgpu_ras_query_error_count_helper(adev, &ce, &ue, &info);
1262                 }
1263         } else {
1264                 /* query specific ip block */
1265                 ret = amdgpu_ras_query_error_count_helper(adev, &ce, &ue, query_info);
1266         }
1267
1268         if (ret)
1269                 return ret;
1270
1271         if (ce_count)
1272                 *ce_count = ce;
1273
1274         if (ue_count)
1275                 *ue_count = ue;
1276
1277         return 0;
1278 }
1279 /* query/inject/cure end */
1280
1281
1282 /* sysfs begin */
1283
1284 static int amdgpu_ras_badpages_read(struct amdgpu_device *adev,
1285                 struct ras_badpage **bps, unsigned int *count);
1286
1287 static char *amdgpu_ras_badpage_flags_str(unsigned int flags)
1288 {
1289         switch (flags) {
1290         case AMDGPU_RAS_RETIRE_PAGE_RESERVED:
1291                 return "R";
1292         case AMDGPU_RAS_RETIRE_PAGE_PENDING:
1293                 return "P";
1294         case AMDGPU_RAS_RETIRE_PAGE_FAULT:
1295         default:
1296                 return "F";
1297         }
1298 }
1299
1300 /**
1301  * DOC: AMDGPU RAS sysfs gpu_vram_bad_pages Interface
1302  *
1303  * It allows user to read the bad pages of vram on the gpu through
1304  * /sys/class/drm/card[0/1/2...]/device/ras/gpu_vram_bad_pages
1305  *
1306  * It outputs multiple lines, and each line stands for one gpu page.
1307  *
1308  * The format of one line is below,
1309  * gpu pfn : gpu page size : flags
1310  *
1311  * gpu pfn and gpu page size are printed in hex format.
1312  * flags can be one of below character,
1313  *
1314  * R: reserved, this gpu page is reserved and not able to use.
1315  *
1316  * P: pending for reserve, this gpu page is marked as bad, will be reserved
1317  * in next window of page_reserve.
1318  *
1319  * F: unable to reserve. this gpu page can't be reserved due to some reasons.
1320  *
1321  * Examples:
1322  *
1323  * .. code-block:: bash
1324  *
1325  *      0x00000001 : 0x00001000 : R
1326  *      0x00000002 : 0x00001000 : P
1327  *
1328  */
1329
1330 static ssize_t amdgpu_ras_sysfs_badpages_read(struct file *f,
1331                 struct kobject *kobj, struct bin_attribute *attr,
1332                 char *buf, loff_t ppos, size_t count)
1333 {
1334         struct amdgpu_ras *con =
1335                 container_of(attr, struct amdgpu_ras, badpages_attr);
1336         struct amdgpu_device *adev = con->adev;
1337         const unsigned int element_size =
1338                 sizeof("0xabcdabcd : 0x12345678 : R\n") - 1;
1339         unsigned int start = div64_ul(ppos + element_size - 1, element_size);
1340         unsigned int end = div64_ul(ppos + count - 1, element_size);
1341         ssize_t s = 0;
1342         struct ras_badpage *bps = NULL;
1343         unsigned int bps_count = 0;
1344
1345         memset(buf, 0, count);
1346
1347         if (amdgpu_ras_badpages_read(adev, &bps, &bps_count))
1348                 return 0;
1349
1350         for (; start < end && start < bps_count; start++)
1351                 s += scnprintf(&buf[s], element_size + 1,
1352                                 "0x%08x : 0x%08x : %1s\n",
1353                                 bps[start].bp,
1354                                 bps[start].size,
1355                                 amdgpu_ras_badpage_flags_str(bps[start].flags));
1356
1357         kfree(bps);
1358
1359         return s;
1360 }
1361
1362 static ssize_t amdgpu_ras_sysfs_features_read(struct device *dev,
1363                 struct device_attribute *attr, char *buf)
1364 {
1365         struct amdgpu_ras *con =
1366                 container_of(attr, struct amdgpu_ras, features_attr);
1367
1368         return sysfs_emit(buf, "feature mask: 0x%x\n", con->features);
1369 }
1370
1371 static void amdgpu_ras_sysfs_remove_bad_page_node(struct amdgpu_device *adev)
1372 {
1373         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1374
1375         sysfs_remove_file_from_group(&adev->dev->kobj,
1376                                 &con->badpages_attr.attr,
1377                                 RAS_FS_NAME);
1378 }
1379
1380 static int amdgpu_ras_sysfs_remove_feature_node(struct amdgpu_device *adev)
1381 {
1382         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1383         struct attribute *attrs[] = {
1384                 &con->features_attr.attr,
1385                 NULL
1386         };
1387         struct attribute_group group = {
1388                 .name = RAS_FS_NAME,
1389                 .attrs = attrs,
1390         };
1391
1392         sysfs_remove_group(&adev->dev->kobj, &group);
1393
1394         return 0;
1395 }
1396
1397 int amdgpu_ras_sysfs_create(struct amdgpu_device *adev,
1398                 struct ras_common_if *head)
1399 {
1400         struct ras_manager *obj = amdgpu_ras_find_obj(adev, head);
1401
1402         if (!obj || obj->attr_inuse)
1403                 return -EINVAL;
1404
1405         get_obj(obj);
1406
1407         snprintf(obj->fs_data.sysfs_name, sizeof(obj->fs_data.sysfs_name),
1408                 "%s_err_count", head->name);
1409
1410         obj->sysfs_attr = (struct device_attribute){
1411                 .attr = {
1412                         .name = obj->fs_data.sysfs_name,
1413                         .mode = S_IRUGO,
1414                 },
1415                         .show = amdgpu_ras_sysfs_read,
1416         };
1417         sysfs_attr_init(&obj->sysfs_attr.attr);
1418
1419         if (sysfs_add_file_to_group(&adev->dev->kobj,
1420                                 &obj->sysfs_attr.attr,
1421                                 RAS_FS_NAME)) {
1422                 put_obj(obj);
1423                 return -EINVAL;
1424         }
1425
1426         obj->attr_inuse = 1;
1427
1428         return 0;
1429 }
1430
1431 int amdgpu_ras_sysfs_remove(struct amdgpu_device *adev,
1432                 struct ras_common_if *head)
1433 {
1434         struct ras_manager *obj = amdgpu_ras_find_obj(adev, head);
1435
1436         if (!obj || !obj->attr_inuse)
1437                 return -EINVAL;
1438
1439         sysfs_remove_file_from_group(&adev->dev->kobj,
1440                                 &obj->sysfs_attr.attr,
1441                                 RAS_FS_NAME);
1442         obj->attr_inuse = 0;
1443         put_obj(obj);
1444
1445         return 0;
1446 }
1447
1448 static int amdgpu_ras_sysfs_remove_all(struct amdgpu_device *adev)
1449 {
1450         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1451         struct ras_manager *obj, *tmp;
1452
1453         list_for_each_entry_safe(obj, tmp, &con->head, node) {
1454                 amdgpu_ras_sysfs_remove(adev, &obj->head);
1455         }
1456
1457         if (amdgpu_bad_page_threshold != 0)
1458                 amdgpu_ras_sysfs_remove_bad_page_node(adev);
1459
1460         amdgpu_ras_sysfs_remove_feature_node(adev);
1461
1462         return 0;
1463 }
1464 /* sysfs end */
1465
1466 /**
1467  * DOC: AMDGPU RAS Reboot Behavior for Unrecoverable Errors
1468  *
1469  * Normally when there is an uncorrectable error, the driver will reset
1470  * the GPU to recover.  However, in the event of an unrecoverable error,
1471  * the driver provides an interface to reboot the system automatically
1472  * in that event.
1473  *
1474  * The following file in debugfs provides that interface:
1475  * /sys/kernel/debug/dri/[0/1/2...]/ras/auto_reboot
1476  *
1477  * Usage:
1478  *
1479  * .. code-block:: bash
1480  *
1481  *      echo true > .../ras/auto_reboot
1482  *
1483  */
1484 /* debugfs begin */
1485 static struct dentry *amdgpu_ras_debugfs_create_ctrl_node(struct amdgpu_device *adev)
1486 {
1487         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1488         struct amdgpu_ras_eeprom_control *eeprom = &con->eeprom_control;
1489         struct drm_minor  *minor = adev_to_drm(adev)->primary;
1490         struct dentry     *dir;
1491
1492         dir = debugfs_create_dir(RAS_FS_NAME, minor->debugfs_root);
1493         debugfs_create_file("ras_ctrl", S_IWUGO | S_IRUGO, dir, adev,
1494                             &amdgpu_ras_debugfs_ctrl_ops);
1495         debugfs_create_file("ras_eeprom_reset", S_IWUGO | S_IRUGO, dir, adev,
1496                             &amdgpu_ras_debugfs_eeprom_ops);
1497         debugfs_create_u32("bad_page_cnt_threshold", 0444, dir,
1498                            &con->bad_page_cnt_threshold);
1499         debugfs_create_u32("ras_num_recs", 0444, dir, &eeprom->ras_num_recs);
1500         debugfs_create_x32("ras_hw_enabled", 0444, dir, &adev->ras_hw_enabled);
1501         debugfs_create_x32("ras_enabled", 0444, dir, &adev->ras_enabled);
1502         debugfs_create_file("ras_eeprom_size", S_IRUGO, dir, adev,
1503                             &amdgpu_ras_debugfs_eeprom_size_ops);
1504         con->de_ras_eeprom_table = debugfs_create_file("ras_eeprom_table",
1505                                                        S_IRUGO, dir, adev,
1506                                                        &amdgpu_ras_debugfs_eeprom_table_ops);
1507         amdgpu_ras_debugfs_set_ret_size(&con->eeprom_control);
1508
1509         /*
1510          * After one uncorrectable error happens, usually GPU recovery will
1511          * be scheduled. But due to the known problem in GPU recovery failing
1512          * to bring GPU back, below interface provides one direct way to
1513          * user to reboot system automatically in such case within
1514          * ERREVENT_ATHUB_INTERRUPT generated. Normal GPU recovery routine
1515          * will never be called.
1516          */
1517         debugfs_create_bool("auto_reboot", S_IWUGO | S_IRUGO, dir, &con->reboot);
1518
1519         /*
1520          * User could set this not to clean up hardware's error count register
1521          * of RAS IPs during ras recovery.
1522          */
1523         debugfs_create_bool("disable_ras_err_cnt_harvest", 0644, dir,
1524                             &con->disable_ras_err_cnt_harvest);
1525         return dir;
1526 }
1527
1528 static void amdgpu_ras_debugfs_create(struct amdgpu_device *adev,
1529                                       struct ras_fs_if *head,
1530                                       struct dentry *dir)
1531 {
1532         struct ras_manager *obj = amdgpu_ras_find_obj(adev, &head->head);
1533
1534         if (!obj || !dir)
1535                 return;
1536
1537         get_obj(obj);
1538
1539         memcpy(obj->fs_data.debugfs_name,
1540                         head->debugfs_name,
1541                         sizeof(obj->fs_data.debugfs_name));
1542
1543         debugfs_create_file(obj->fs_data.debugfs_name, S_IWUGO | S_IRUGO, dir,
1544                             obj, &amdgpu_ras_debugfs_ops);
1545 }
1546
1547 void amdgpu_ras_debugfs_create_all(struct amdgpu_device *adev)
1548 {
1549         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1550         struct dentry *dir;
1551         struct ras_manager *obj;
1552         struct ras_fs_if fs_info;
1553
1554         /*
1555          * it won't be called in resume path, no need to check
1556          * suspend and gpu reset status
1557          */
1558         if (!IS_ENABLED(CONFIG_DEBUG_FS) || !con)
1559                 return;
1560
1561         dir = amdgpu_ras_debugfs_create_ctrl_node(adev);
1562
1563         list_for_each_entry(obj, &con->head, node) {
1564                 if (amdgpu_ras_is_supported(adev, obj->head.block) &&
1565                         (obj->attr_inuse == 1)) {
1566                         sprintf(fs_info.debugfs_name, "%s_err_inject",
1567                                         get_ras_block_str(&obj->head));
1568                         fs_info.head = obj->head;
1569                         amdgpu_ras_debugfs_create(adev, &fs_info, dir);
1570                 }
1571         }
1572 }
1573
1574 /* debugfs end */
1575
1576 /* ras fs */
1577 static BIN_ATTR(gpu_vram_bad_pages, S_IRUGO,
1578                 amdgpu_ras_sysfs_badpages_read, NULL, 0);
1579 static DEVICE_ATTR(features, S_IRUGO,
1580                 amdgpu_ras_sysfs_features_read, NULL);
1581 static int amdgpu_ras_fs_init(struct amdgpu_device *adev)
1582 {
1583         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1584         struct attribute_group group = {
1585                 .name = RAS_FS_NAME,
1586         };
1587         struct attribute *attrs[] = {
1588                 &con->features_attr.attr,
1589                 NULL
1590         };
1591         struct bin_attribute *bin_attrs[] = {
1592                 NULL,
1593                 NULL,
1594         };
1595         int r;
1596
1597         /* add features entry */
1598         con->features_attr = dev_attr_features;
1599         group.attrs = attrs;
1600         sysfs_attr_init(attrs[0]);
1601
1602         if (amdgpu_bad_page_threshold != 0) {
1603                 /* add bad_page_features entry */
1604                 bin_attr_gpu_vram_bad_pages.private = NULL;
1605                 con->badpages_attr = bin_attr_gpu_vram_bad_pages;
1606                 bin_attrs[0] = &con->badpages_attr;
1607                 group.bin_attrs = bin_attrs;
1608                 sysfs_bin_attr_init(bin_attrs[0]);
1609         }
1610
1611         r = sysfs_create_group(&adev->dev->kobj, &group);
1612         if (r)
1613                 dev_err(adev->dev, "Failed to create RAS sysfs group!");
1614
1615         return 0;
1616 }
1617
1618 static int amdgpu_ras_fs_fini(struct amdgpu_device *adev)
1619 {
1620         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1621         struct ras_manager *con_obj, *ip_obj, *tmp;
1622
1623         if (IS_ENABLED(CONFIG_DEBUG_FS)) {
1624                 list_for_each_entry_safe(con_obj, tmp, &con->head, node) {
1625                         ip_obj = amdgpu_ras_find_obj(adev, &con_obj->head);
1626                         if (ip_obj)
1627                                 put_obj(ip_obj);
1628                 }
1629         }
1630
1631         amdgpu_ras_sysfs_remove_all(adev);
1632         return 0;
1633 }
1634 /* ras fs end */
1635
1636 /* ih begin */
1637
1638 /* For the hardware that cannot enable bif ring for both ras_controller_irq
1639  * and ras_err_evnet_athub_irq ih cookies, the driver has to poll status
1640  * register to check whether the interrupt is triggered or not, and properly
1641  * ack the interrupt if it is there
1642  */
1643 void amdgpu_ras_interrupt_fatal_error_handler(struct amdgpu_device *adev)
1644 {
1645         /* Fatal error events are handled on host side */
1646         if (amdgpu_sriov_vf(adev))
1647                 return;
1648
1649         if (adev->nbio.ras &&
1650             adev->nbio.ras->handle_ras_controller_intr_no_bifring)
1651                 adev->nbio.ras->handle_ras_controller_intr_no_bifring(adev);
1652
1653         if (adev->nbio.ras &&
1654             adev->nbio.ras->handle_ras_err_event_athub_intr_no_bifring)
1655                 adev->nbio.ras->handle_ras_err_event_athub_intr_no_bifring(adev);
1656 }
1657
1658 static void amdgpu_ras_interrupt_poison_consumption_handler(struct ras_manager *obj,
1659                                 struct amdgpu_iv_entry *entry)
1660 {
1661         bool poison_stat = false;
1662         struct amdgpu_device *adev = obj->adev;
1663         struct amdgpu_ras_block_object *block_obj =
1664                 amdgpu_ras_get_ras_block(adev, obj->head.block, 0);
1665
1666         if (!block_obj)
1667                 return;
1668
1669         /* both query_poison_status and handle_poison_consumption are optional,
1670          * but at least one of them should be implemented if we need poison
1671          * consumption handler
1672          */
1673         if (block_obj->hw_ops && block_obj->hw_ops->query_poison_status) {
1674                 poison_stat = block_obj->hw_ops->query_poison_status(adev);
1675                 if (!poison_stat) {
1676                         /* Not poison consumption interrupt, no need to handle it */
1677                         dev_info(adev->dev, "No RAS poison status in %s poison IH.\n",
1678                                         block_obj->ras_comm.name);
1679
1680                         return;
1681                 }
1682         }
1683
1684         amdgpu_umc_poison_handler(adev, false);
1685
1686         if (block_obj->hw_ops && block_obj->hw_ops->handle_poison_consumption)
1687                 poison_stat = block_obj->hw_ops->handle_poison_consumption(adev);
1688
1689         /* gpu reset is fallback for failed and default cases */
1690         if (poison_stat) {
1691                 dev_info(adev->dev, "GPU reset for %s RAS poison consumption is issued!\n",
1692                                 block_obj->ras_comm.name);
1693                 amdgpu_ras_reset_gpu(adev);
1694         } else {
1695                 amdgpu_gfx_poison_consumption_handler(adev, entry);
1696         }
1697 }
1698
1699 static void amdgpu_ras_interrupt_poison_creation_handler(struct ras_manager *obj,
1700                                 struct amdgpu_iv_entry *entry)
1701 {
1702         dev_info(obj->adev->dev,
1703                 "Poison is created, no user action is needed.\n");
1704 }
1705
1706 static void amdgpu_ras_interrupt_umc_handler(struct ras_manager *obj,
1707                                 struct amdgpu_iv_entry *entry)
1708 {
1709         struct ras_ih_data *data = &obj->ih_data;
1710         struct ras_err_data err_data = {0, 0, 0, NULL};
1711         int ret;
1712
1713         if (!data->cb)
1714                 return;
1715
1716         /* Let IP handle its data, maybe we need get the output
1717          * from the callback to update the error type/count, etc
1718          */
1719         ret = data->cb(obj->adev, &err_data, entry);
1720         /* ue will trigger an interrupt, and in that case
1721          * we need do a reset to recovery the whole system.
1722          * But leave IP do that recovery, here we just dispatch
1723          * the error.
1724          */
1725         if (ret == AMDGPU_RAS_SUCCESS) {
1726                 /* these counts could be left as 0 if
1727                  * some blocks do not count error number
1728                  */
1729                 obj->err_data.ue_count += err_data.ue_count;
1730                 obj->err_data.ce_count += err_data.ce_count;
1731         }
1732 }
1733
1734 static void amdgpu_ras_interrupt_handler(struct ras_manager *obj)
1735 {
1736         struct ras_ih_data *data = &obj->ih_data;
1737         struct amdgpu_iv_entry entry;
1738
1739         while (data->rptr != data->wptr) {
1740                 rmb();
1741                 memcpy(&entry, &data->ring[data->rptr],
1742                                 data->element_size);
1743
1744                 wmb();
1745                 data->rptr = (data->aligned_element_size +
1746                                 data->rptr) % data->ring_size;
1747
1748                 if (amdgpu_ras_is_poison_mode_supported(obj->adev)) {
1749                         if (obj->head.block == AMDGPU_RAS_BLOCK__UMC)
1750                                 amdgpu_ras_interrupt_poison_creation_handler(obj, &entry);
1751                         else
1752                                 amdgpu_ras_interrupt_poison_consumption_handler(obj, &entry);
1753                 } else {
1754                         if (obj->head.block == AMDGPU_RAS_BLOCK__UMC)
1755                                 amdgpu_ras_interrupt_umc_handler(obj, &entry);
1756                         else
1757                                 dev_warn(obj->adev->dev,
1758                                         "No RAS interrupt handler for non-UMC block with poison disabled.\n");
1759                 }
1760         }
1761 }
1762
1763 static void amdgpu_ras_interrupt_process_handler(struct work_struct *work)
1764 {
1765         struct ras_ih_data *data =
1766                 container_of(work, struct ras_ih_data, ih_work);
1767         struct ras_manager *obj =
1768                 container_of(data, struct ras_manager, ih_data);
1769
1770         amdgpu_ras_interrupt_handler(obj);
1771 }
1772
1773 int amdgpu_ras_interrupt_dispatch(struct amdgpu_device *adev,
1774                 struct ras_dispatch_if *info)
1775 {
1776         struct ras_manager *obj = amdgpu_ras_find_obj(adev, &info->head);
1777         struct ras_ih_data *data = &obj->ih_data;
1778
1779         if (!obj)
1780                 return -EINVAL;
1781
1782         if (data->inuse == 0)
1783                 return 0;
1784
1785         /* Might be overflow... */
1786         memcpy(&data->ring[data->wptr], info->entry,
1787                         data->element_size);
1788
1789         wmb();
1790         data->wptr = (data->aligned_element_size +
1791                         data->wptr) % data->ring_size;
1792
1793         schedule_work(&data->ih_work);
1794
1795         return 0;
1796 }
1797
1798 int amdgpu_ras_interrupt_remove_handler(struct amdgpu_device *adev,
1799                 struct ras_common_if *head)
1800 {
1801         struct ras_manager *obj = amdgpu_ras_find_obj(adev, head);
1802         struct ras_ih_data *data;
1803
1804         if (!obj)
1805                 return -EINVAL;
1806
1807         data = &obj->ih_data;
1808         if (data->inuse == 0)
1809                 return 0;
1810
1811         cancel_work_sync(&data->ih_work);
1812
1813         kfree(data->ring);
1814         memset(data, 0, sizeof(*data));
1815         put_obj(obj);
1816
1817         return 0;
1818 }
1819
1820 int amdgpu_ras_interrupt_add_handler(struct amdgpu_device *adev,
1821                 struct ras_common_if *head)
1822 {
1823         struct ras_manager *obj = amdgpu_ras_find_obj(adev, head);
1824         struct ras_ih_data *data;
1825         struct amdgpu_ras_block_object *ras_obj;
1826
1827         if (!obj) {
1828                 /* in case we registe the IH before enable ras feature */
1829                 obj = amdgpu_ras_create_obj(adev, head);
1830                 if (!obj)
1831                         return -EINVAL;
1832         } else
1833                 get_obj(obj);
1834
1835         ras_obj = container_of(head, struct amdgpu_ras_block_object, ras_comm);
1836
1837         data = &obj->ih_data;
1838         /* add the callback.etc */
1839         *data = (struct ras_ih_data) {
1840                 .inuse = 0,
1841                 .cb = ras_obj->ras_cb,
1842                 .element_size = sizeof(struct amdgpu_iv_entry),
1843                 .rptr = 0,
1844                 .wptr = 0,
1845         };
1846
1847         INIT_WORK(&data->ih_work, amdgpu_ras_interrupt_process_handler);
1848
1849         data->aligned_element_size = ALIGN(data->element_size, 8);
1850         /* the ring can store 64 iv entries. */
1851         data->ring_size = 64 * data->aligned_element_size;
1852         data->ring = kmalloc(data->ring_size, GFP_KERNEL);
1853         if (!data->ring) {
1854                 put_obj(obj);
1855                 return -ENOMEM;
1856         }
1857
1858         /* IH is ready */
1859         data->inuse = 1;
1860
1861         return 0;
1862 }
1863
1864 static int amdgpu_ras_interrupt_remove_all(struct amdgpu_device *adev)
1865 {
1866         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1867         struct ras_manager *obj, *tmp;
1868
1869         list_for_each_entry_safe(obj, tmp, &con->head, node) {
1870                 amdgpu_ras_interrupt_remove_handler(adev, &obj->head);
1871         }
1872
1873         return 0;
1874 }
1875 /* ih end */
1876
1877 /* traversal all IPs except NBIO to query error counter */
1878 static void amdgpu_ras_log_on_err_counter(struct amdgpu_device *adev)
1879 {
1880         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1881         struct ras_manager *obj;
1882
1883         if (!adev->ras_enabled || !con)
1884                 return;
1885
1886         list_for_each_entry(obj, &con->head, node) {
1887                 struct ras_query_if info = {
1888                         .head = obj->head,
1889                 };
1890
1891                 /*
1892                  * PCIE_BIF IP has one different isr by ras controller
1893                  * interrupt, the specific ras counter query will be
1894                  * done in that isr. So skip such block from common
1895                  * sync flood interrupt isr calling.
1896                  */
1897                 if (info.head.block == AMDGPU_RAS_BLOCK__PCIE_BIF)
1898                         continue;
1899
1900                 /*
1901                  * this is a workaround for aldebaran, skip send msg to
1902                  * smu to get ecc_info table due to smu handle get ecc
1903                  * info table failed temporarily.
1904                  * should be removed until smu fix handle ecc_info table.
1905                  */
1906                 if ((info.head.block == AMDGPU_RAS_BLOCK__UMC) &&
1907                         (adev->ip_versions[MP1_HWIP][0] == IP_VERSION(13, 0, 2)))
1908                         continue;
1909
1910                 amdgpu_ras_query_error_status(adev, &info);
1911
1912                 if (adev->ip_versions[MP0_HWIP][0] != IP_VERSION(11, 0, 2) &&
1913                     adev->ip_versions[MP0_HWIP][0] != IP_VERSION(11, 0, 4) &&
1914                     adev->ip_versions[MP0_HWIP][0] != IP_VERSION(13, 0, 0)) {
1915                         if (amdgpu_ras_reset_error_status(adev, info.head.block))
1916                                 dev_warn(adev->dev, "Failed to reset error counter and error status");
1917                 }
1918         }
1919 }
1920
1921 /* Parse RdRspStatus and WrRspStatus */
1922 static void amdgpu_ras_error_status_query(struct amdgpu_device *adev,
1923                                           struct ras_query_if *info)
1924 {
1925         struct amdgpu_ras_block_object *block_obj;
1926         /*
1927          * Only two block need to query read/write
1928          * RspStatus at current state
1929          */
1930         if ((info->head.block != AMDGPU_RAS_BLOCK__GFX) &&
1931                 (info->head.block != AMDGPU_RAS_BLOCK__MMHUB))
1932                 return;
1933
1934         block_obj = amdgpu_ras_get_ras_block(adev,
1935                                         info->head.block,
1936                                         info->head.sub_block_index);
1937
1938         if (!block_obj || !block_obj->hw_ops) {
1939                 dev_dbg_once(adev->dev, "%s doesn't config RAS function\n",
1940                              get_ras_block_str(&info->head));
1941                 return;
1942         }
1943
1944         if (block_obj->hw_ops->query_ras_error_status)
1945                 block_obj->hw_ops->query_ras_error_status(adev);
1946
1947 }
1948
1949 static void amdgpu_ras_query_err_status(struct amdgpu_device *adev)
1950 {
1951         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1952         struct ras_manager *obj;
1953
1954         if (!adev->ras_enabled || !con)
1955                 return;
1956
1957         list_for_each_entry(obj, &con->head, node) {
1958                 struct ras_query_if info = {
1959                         .head = obj->head,
1960                 };
1961
1962                 amdgpu_ras_error_status_query(adev, &info);
1963         }
1964 }
1965
1966 /* recovery begin */
1967
1968 /* return 0 on success.
1969  * caller need free bps.
1970  */
1971 static int amdgpu_ras_badpages_read(struct amdgpu_device *adev,
1972                 struct ras_badpage **bps, unsigned int *count)
1973 {
1974         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1975         struct ras_err_handler_data *data;
1976         int i = 0;
1977         int ret = 0, status;
1978
1979         if (!con || !con->eh_data || !bps || !count)
1980                 return -EINVAL;
1981
1982         mutex_lock(&con->recovery_lock);
1983         data = con->eh_data;
1984         if (!data || data->count == 0) {
1985                 *bps = NULL;
1986                 ret = -EINVAL;
1987                 goto out;
1988         }
1989
1990         *bps = kmalloc(sizeof(struct ras_badpage) * data->count, GFP_KERNEL);
1991         if (!*bps) {
1992                 ret = -ENOMEM;
1993                 goto out;
1994         }
1995
1996         for (; i < data->count; i++) {
1997                 (*bps)[i] = (struct ras_badpage){
1998                         .bp = data->bps[i].retired_page,
1999                         .size = AMDGPU_GPU_PAGE_SIZE,
2000                         .flags = AMDGPU_RAS_RETIRE_PAGE_RESERVED,
2001                 };
2002                 status = amdgpu_vram_mgr_query_page_status(&adev->mman.vram_mgr,
2003                                 data->bps[i].retired_page);
2004                 if (status == -EBUSY)
2005                         (*bps)[i].flags = AMDGPU_RAS_RETIRE_PAGE_PENDING;
2006                 else if (status == -ENOENT)
2007                         (*bps)[i].flags = AMDGPU_RAS_RETIRE_PAGE_FAULT;
2008         }
2009
2010         *count = data->count;
2011 out:
2012         mutex_unlock(&con->recovery_lock);
2013         return ret;
2014 }
2015
2016 static void amdgpu_ras_do_recovery(struct work_struct *work)
2017 {
2018         struct amdgpu_ras *ras =
2019                 container_of(work, struct amdgpu_ras, recovery_work);
2020         struct amdgpu_device *remote_adev = NULL;
2021         struct amdgpu_device *adev = ras->adev;
2022         struct list_head device_list, *device_list_handle =  NULL;
2023
2024         if (!ras->disable_ras_err_cnt_harvest) {
2025                 struct amdgpu_hive_info *hive = amdgpu_get_xgmi_hive(adev);
2026
2027                 /* Build list of devices to query RAS related errors */
2028                 if  (hive && adev->gmc.xgmi.num_physical_nodes > 1) {
2029                         device_list_handle = &hive->device_list;
2030                 } else {
2031                         INIT_LIST_HEAD(&device_list);
2032                         list_add_tail(&adev->gmc.xgmi.head, &device_list);
2033                         device_list_handle = &device_list;
2034                 }
2035
2036                 list_for_each_entry(remote_adev,
2037                                 device_list_handle, gmc.xgmi.head) {
2038                         amdgpu_ras_query_err_status(remote_adev);
2039                         amdgpu_ras_log_on_err_counter(remote_adev);
2040                 }
2041
2042                 amdgpu_put_xgmi_hive(hive);
2043         }
2044
2045         if (amdgpu_device_should_recover_gpu(ras->adev)) {
2046                 struct amdgpu_reset_context reset_context;
2047                 memset(&reset_context, 0, sizeof(reset_context));
2048
2049                 reset_context.method = AMD_RESET_METHOD_NONE;
2050                 reset_context.reset_req_dev = adev;
2051
2052                 /* Perform full reset in fatal error mode */
2053                 if (!amdgpu_ras_is_poison_mode_supported(ras->adev))
2054                         set_bit(AMDGPU_NEED_FULL_RESET, &reset_context.flags);
2055                 else {
2056                         clear_bit(AMDGPU_NEED_FULL_RESET, &reset_context.flags);
2057
2058                         if (ras->gpu_reset_flags & AMDGPU_RAS_GPU_RESET_MODE2_RESET) {
2059                                 ras->gpu_reset_flags &= ~AMDGPU_RAS_GPU_RESET_MODE2_RESET;
2060                                 reset_context.method = AMD_RESET_METHOD_MODE2;
2061                         }
2062
2063                         /* Fatal error occurs in poison mode, mode1 reset is used to
2064                          * recover gpu.
2065                          */
2066                         if (ras->gpu_reset_flags & AMDGPU_RAS_GPU_RESET_MODE1_RESET) {
2067                                 ras->gpu_reset_flags &= ~AMDGPU_RAS_GPU_RESET_MODE1_RESET;
2068                                 set_bit(AMDGPU_NEED_FULL_RESET, &reset_context.flags);
2069
2070                                 psp_fatal_error_recovery_quirk(&adev->psp);
2071                         }
2072                 }
2073
2074                 amdgpu_device_gpu_recover(ras->adev, NULL, &reset_context);
2075         }
2076         atomic_set(&ras->in_recovery, 0);
2077 }
2078
2079 /* alloc/realloc bps array */
2080 static int amdgpu_ras_realloc_eh_data_space(struct amdgpu_device *adev,
2081                 struct ras_err_handler_data *data, int pages)
2082 {
2083         unsigned int old_space = data->count + data->space_left;
2084         unsigned int new_space = old_space + pages;
2085         unsigned int align_space = ALIGN(new_space, 512);
2086         void *bps = kmalloc(align_space * sizeof(*data->bps), GFP_KERNEL);
2087
2088         if (!bps) {
2089                 return -ENOMEM;
2090         }
2091
2092         if (data->bps) {
2093                 memcpy(bps, data->bps,
2094                                 data->count * sizeof(*data->bps));
2095                 kfree(data->bps);
2096         }
2097
2098         data->bps = bps;
2099         data->space_left += align_space - old_space;
2100         return 0;
2101 }
2102
2103 /* it deal with vram only. */
2104 int amdgpu_ras_add_bad_pages(struct amdgpu_device *adev,
2105                 struct eeprom_table_record *bps, int pages)
2106 {
2107         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
2108         struct ras_err_handler_data *data;
2109         int ret = 0;
2110         uint32_t i;
2111
2112         if (!con || !con->eh_data || !bps || pages <= 0)
2113                 return 0;
2114
2115         mutex_lock(&con->recovery_lock);
2116         data = con->eh_data;
2117         if (!data)
2118                 goto out;
2119
2120         for (i = 0; i < pages; i++) {
2121                 if (amdgpu_ras_check_bad_page_unlock(con,
2122                         bps[i].retired_page << AMDGPU_GPU_PAGE_SHIFT))
2123                         continue;
2124
2125                 if (!data->space_left &&
2126                         amdgpu_ras_realloc_eh_data_space(adev, data, 256)) {
2127                         ret = -ENOMEM;
2128                         goto out;
2129                 }
2130
2131                 amdgpu_vram_mgr_reserve_range(&adev->mman.vram_mgr,
2132                         bps[i].retired_page << AMDGPU_GPU_PAGE_SHIFT,
2133                         AMDGPU_GPU_PAGE_SIZE);
2134
2135                 memcpy(&data->bps[data->count], &bps[i], sizeof(*data->bps));
2136                 data->count++;
2137                 data->space_left--;
2138         }
2139 out:
2140         mutex_unlock(&con->recovery_lock);
2141
2142         return ret;
2143 }
2144
2145 /*
2146  * write error record array to eeprom, the function should be
2147  * protected by recovery_lock
2148  * new_cnt: new added UE count, excluding reserved bad pages, can be NULL
2149  */
2150 int amdgpu_ras_save_bad_pages(struct amdgpu_device *adev,
2151                 unsigned long *new_cnt)
2152 {
2153         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
2154         struct ras_err_handler_data *data;
2155         struct amdgpu_ras_eeprom_control *control;
2156         int save_count;
2157
2158         if (!con || !con->eh_data) {
2159                 if (new_cnt)
2160                         *new_cnt = 0;
2161
2162                 return 0;
2163         }
2164
2165         mutex_lock(&con->recovery_lock);
2166         control = &con->eeprom_control;
2167         data = con->eh_data;
2168         save_count = data->count - control->ras_num_recs;
2169         mutex_unlock(&con->recovery_lock);
2170
2171         if (new_cnt)
2172                 *new_cnt = save_count / adev->umc.retire_unit;
2173
2174         /* only new entries are saved */
2175         if (save_count > 0) {
2176                 if (amdgpu_ras_eeprom_append(control,
2177                                              &data->bps[control->ras_num_recs],
2178                                              save_count)) {
2179                         dev_err(adev->dev, "Failed to save EEPROM table data!");
2180                         return -EIO;
2181                 }
2182
2183                 dev_info(adev->dev, "Saved %d pages to EEPROM table.\n", save_count);
2184         }
2185
2186         return 0;
2187 }
2188
2189 /*
2190  * read error record array in eeprom and reserve enough space for
2191  * storing new bad pages
2192  */
2193 static int amdgpu_ras_load_bad_pages(struct amdgpu_device *adev)
2194 {
2195         struct amdgpu_ras_eeprom_control *control =
2196                 &adev->psp.ras_context.ras->eeprom_control;
2197         struct eeprom_table_record *bps;
2198         int ret;
2199
2200         /* no bad page record, skip eeprom access */
2201         if (control->ras_num_recs == 0 || amdgpu_bad_page_threshold == 0)
2202                 return 0;
2203
2204         bps = kcalloc(control->ras_num_recs, sizeof(*bps), GFP_KERNEL);
2205         if (!bps)
2206                 return -ENOMEM;
2207
2208         ret = amdgpu_ras_eeprom_read(control, bps, control->ras_num_recs);
2209         if (ret)
2210                 dev_err(adev->dev, "Failed to load EEPROM table records!");
2211         else
2212                 ret = amdgpu_ras_add_bad_pages(adev, bps, control->ras_num_recs);
2213
2214         kfree(bps);
2215         return ret;
2216 }
2217
2218 static bool amdgpu_ras_check_bad_page_unlock(struct amdgpu_ras *con,
2219                                 uint64_t addr)
2220 {
2221         struct ras_err_handler_data *data = con->eh_data;
2222         int i;
2223
2224         addr >>= AMDGPU_GPU_PAGE_SHIFT;
2225         for (i = 0; i < data->count; i++)
2226                 if (addr == data->bps[i].retired_page)
2227                         return true;
2228
2229         return false;
2230 }
2231
2232 /*
2233  * check if an address belongs to bad page
2234  *
2235  * Note: this check is only for umc block
2236  */
2237 static bool amdgpu_ras_check_bad_page(struct amdgpu_device *adev,
2238                                 uint64_t addr)
2239 {
2240         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
2241         bool ret = false;
2242
2243         if (!con || !con->eh_data)
2244                 return ret;
2245
2246         mutex_lock(&con->recovery_lock);
2247         ret = amdgpu_ras_check_bad_page_unlock(con, addr);
2248         mutex_unlock(&con->recovery_lock);
2249         return ret;
2250 }
2251
2252 static void amdgpu_ras_validate_threshold(struct amdgpu_device *adev,
2253                                           uint32_t max_count)
2254 {
2255         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
2256
2257         /*
2258          * Justification of value bad_page_cnt_threshold in ras structure
2259          *
2260          * Generally, 0 <= amdgpu_bad_page_threshold <= max record length
2261          * in eeprom or amdgpu_bad_page_threshold == -2, introduce two
2262          * scenarios accordingly.
2263          *
2264          * Bad page retirement enablement:
2265          *    - If amdgpu_bad_page_threshold = -2,
2266          *      bad_page_cnt_threshold = typical value by formula.
2267          *
2268          *    - When the value from user is 0 < amdgpu_bad_page_threshold <
2269          *      max record length in eeprom, use it directly.
2270          *
2271          * Bad page retirement disablement:
2272          *    - If amdgpu_bad_page_threshold = 0, bad page retirement
2273          *      functionality is disabled, and bad_page_cnt_threshold will
2274          *      take no effect.
2275          */
2276
2277         if (amdgpu_bad_page_threshold < 0) {
2278                 u64 val = adev->gmc.mc_vram_size;
2279
2280                 do_div(val, RAS_BAD_PAGE_COVER);
2281                 con->bad_page_cnt_threshold = min(lower_32_bits(val),
2282                                                   max_count);
2283         } else {
2284                 con->bad_page_cnt_threshold = min_t(int, max_count,
2285                                                     amdgpu_bad_page_threshold);
2286         }
2287 }
2288
2289 int amdgpu_ras_recovery_init(struct amdgpu_device *adev)
2290 {
2291         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
2292         struct ras_err_handler_data **data;
2293         u32  max_eeprom_records_count = 0;
2294         bool exc_err_limit = false;
2295         int ret;
2296
2297         if (!con || amdgpu_sriov_vf(adev))
2298                 return 0;
2299
2300         /* Allow access to RAS EEPROM via debugfs, when the ASIC
2301          * supports RAS and debugfs is enabled, but when
2302          * adev->ras_enabled is unset, i.e. when "ras_enable"
2303          * module parameter is set to 0.
2304          */
2305         con->adev = adev;
2306
2307         if (!adev->ras_enabled)
2308                 return 0;
2309
2310         data = &con->eh_data;
2311         *data = kmalloc(sizeof(**data), GFP_KERNEL | __GFP_ZERO);
2312         if (!*data) {
2313                 ret = -ENOMEM;
2314                 goto out;
2315         }
2316
2317         mutex_init(&con->recovery_lock);
2318         INIT_WORK(&con->recovery_work, amdgpu_ras_do_recovery);
2319         atomic_set(&con->in_recovery, 0);
2320         con->eeprom_control.bad_channel_bitmap = 0;
2321
2322         max_eeprom_records_count = amdgpu_ras_eeprom_max_record_count(&con->eeprom_control);
2323         amdgpu_ras_validate_threshold(adev, max_eeprom_records_count);
2324
2325         /* Todo: During test the SMU might fail to read the eeprom through I2C
2326          * when the GPU is pending on XGMI reset during probe time
2327          * (Mostly after second bus reset), skip it now
2328          */
2329         if (adev->gmc.xgmi.pending_reset)
2330                 return 0;
2331         ret = amdgpu_ras_eeprom_init(&con->eeprom_control, &exc_err_limit);
2332         /*
2333          * This calling fails when exc_err_limit is true or
2334          * ret != 0.
2335          */
2336         if (exc_err_limit || ret)
2337                 goto free;
2338
2339         if (con->eeprom_control.ras_num_recs) {
2340                 ret = amdgpu_ras_load_bad_pages(adev);
2341                 if (ret)
2342                         goto free;
2343
2344                 amdgpu_dpm_send_hbm_bad_pages_num(adev, con->eeprom_control.ras_num_recs);
2345
2346                 if (con->update_channel_flag == true) {
2347                         amdgpu_dpm_send_hbm_bad_channel_flag(adev, con->eeprom_control.bad_channel_bitmap);
2348                         con->update_channel_flag = false;
2349                 }
2350         }
2351
2352 #ifdef CONFIG_X86_MCE_AMD
2353         if ((adev->asic_type == CHIP_ALDEBARAN) &&
2354             (adev->gmc.xgmi.connected_to_cpu))
2355                 amdgpu_register_bad_pages_mca_notifier(adev);
2356 #endif
2357         return 0;
2358
2359 free:
2360         kfree((*data)->bps);
2361         kfree(*data);
2362         con->eh_data = NULL;
2363 out:
2364         dev_warn(adev->dev, "Failed to initialize ras recovery! (%d)\n", ret);
2365
2366         /*
2367          * Except error threshold exceeding case, other failure cases in this
2368          * function would not fail amdgpu driver init.
2369          */
2370         if (!exc_err_limit)
2371                 ret = 0;
2372         else
2373                 ret = -EINVAL;
2374
2375         return ret;
2376 }
2377
2378 static int amdgpu_ras_recovery_fini(struct amdgpu_device *adev)
2379 {
2380         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
2381         struct ras_err_handler_data *data = con->eh_data;
2382
2383         /* recovery_init failed to init it, fini is useless */
2384         if (!data)
2385                 return 0;
2386
2387         cancel_work_sync(&con->recovery_work);
2388
2389         mutex_lock(&con->recovery_lock);
2390         con->eh_data = NULL;
2391         kfree(data->bps);
2392         kfree(data);
2393         mutex_unlock(&con->recovery_lock);
2394
2395         return 0;
2396 }
2397 /* recovery end */
2398
2399 static bool amdgpu_ras_asic_supported(struct amdgpu_device *adev)
2400 {
2401         if (amdgpu_sriov_vf(adev)) {
2402                 switch (adev->ip_versions[MP0_HWIP][0]) {
2403                 case IP_VERSION(13, 0, 2):
2404                 case IP_VERSION(13, 0, 6):
2405                         return true;
2406                 default:
2407                         return false;
2408                 }
2409         }
2410
2411         if (adev->asic_type == CHIP_IP_DISCOVERY) {
2412                 switch (adev->ip_versions[MP0_HWIP][0]) {
2413                 case IP_VERSION(13, 0, 0):
2414                 case IP_VERSION(13, 0, 6):
2415                 case IP_VERSION(13, 0, 10):
2416                         return true;
2417                 default:
2418                         return false;
2419                 }
2420         }
2421
2422         return adev->asic_type == CHIP_VEGA10 ||
2423                 adev->asic_type == CHIP_VEGA20 ||
2424                 adev->asic_type == CHIP_ARCTURUS ||
2425                 adev->asic_type == CHIP_ALDEBARAN ||
2426                 adev->asic_type == CHIP_SIENNA_CICHLID;
2427 }
2428
2429 /*
2430  * this is workaround for vega20 workstation sku,
2431  * force enable gfx ras, ignore vbios gfx ras flag
2432  * due to GC EDC can not write
2433  */
2434 static void amdgpu_ras_get_quirks(struct amdgpu_device *adev)
2435 {
2436         struct atom_context *ctx = adev->mode_info.atom_context;
2437
2438         if (!ctx)
2439                 return;
2440
2441         if (strnstr(ctx->vbios_pn, "D16406",
2442                     sizeof(ctx->vbios_pn)) ||
2443                 strnstr(ctx->vbios_pn, "D36002",
2444                         sizeof(ctx->vbios_pn)))
2445                 adev->ras_hw_enabled |= (1 << AMDGPU_RAS_BLOCK__GFX);
2446 }
2447
2448 /*
2449  * check hardware's ras ability which will be saved in hw_supported.
2450  * if hardware does not support ras, we can skip some ras initializtion and
2451  * forbid some ras operations from IP.
2452  * if software itself, say boot parameter, limit the ras ability. We still
2453  * need allow IP do some limited operations, like disable. In such case,
2454  * we have to initialize ras as normal. but need check if operation is
2455  * allowed or not in each function.
2456  */
2457 static void amdgpu_ras_check_supported(struct amdgpu_device *adev)
2458 {
2459         adev->ras_hw_enabled = adev->ras_enabled = 0;
2460
2461         if (!amdgpu_ras_asic_supported(adev))
2462                 return;
2463
2464         if (!adev->gmc.xgmi.connected_to_cpu && !adev->gmc.is_app_apu) {
2465                 if (amdgpu_atomfirmware_mem_ecc_supported(adev)) {
2466                         dev_info(adev->dev, "MEM ECC is active.\n");
2467                         adev->ras_hw_enabled |= (1 << AMDGPU_RAS_BLOCK__UMC |
2468                                                    1 << AMDGPU_RAS_BLOCK__DF);
2469                 } else {
2470                         dev_info(adev->dev, "MEM ECC is not presented.\n");
2471                 }
2472
2473                 if (amdgpu_atomfirmware_sram_ecc_supported(adev)) {
2474                         dev_info(adev->dev, "SRAM ECC is active.\n");
2475                         if (!amdgpu_sriov_vf(adev))
2476                                 adev->ras_hw_enabled |= ~(1 << AMDGPU_RAS_BLOCK__UMC |
2477                                                             1 << AMDGPU_RAS_BLOCK__DF);
2478                         else
2479                                 adev->ras_hw_enabled |= (1 << AMDGPU_RAS_BLOCK__PCIE_BIF |
2480                                                                 1 << AMDGPU_RAS_BLOCK__SDMA |
2481                                                                 1 << AMDGPU_RAS_BLOCK__GFX);
2482
2483                         /* VCN/JPEG RAS can be supported on both bare metal and
2484                          * SRIOV environment
2485                          */
2486                         if (adev->ip_versions[VCN_HWIP][0] == IP_VERSION(2, 6, 0) ||
2487                             adev->ip_versions[VCN_HWIP][0] == IP_VERSION(4, 0, 0))
2488                                 adev->ras_hw_enabled |= (1 << AMDGPU_RAS_BLOCK__VCN |
2489                                                         1 << AMDGPU_RAS_BLOCK__JPEG);
2490                         else
2491                                 adev->ras_hw_enabled &= ~(1 << AMDGPU_RAS_BLOCK__VCN |
2492                                                         1 << AMDGPU_RAS_BLOCK__JPEG);
2493
2494                         /*
2495                          * XGMI RAS is not supported if xgmi num physical nodes
2496                          * is zero
2497                          */
2498                         if (!adev->gmc.xgmi.num_physical_nodes)
2499                                 adev->ras_hw_enabled &= ~(1 << AMDGPU_RAS_BLOCK__XGMI_WAFL);
2500                 } else {
2501                         dev_info(adev->dev, "SRAM ECC is not presented.\n");
2502                 }
2503         } else {
2504                 /* driver only manages a few IP blocks RAS feature
2505                  * when GPU is connected cpu through XGMI */
2506                 adev->ras_hw_enabled |= (1 << AMDGPU_RAS_BLOCK__GFX |
2507                                            1 << AMDGPU_RAS_BLOCK__SDMA |
2508                                            1 << AMDGPU_RAS_BLOCK__MMHUB);
2509         }
2510
2511         amdgpu_ras_get_quirks(adev);
2512
2513         /* hw_supported needs to be aligned with RAS block mask. */
2514         adev->ras_hw_enabled &= AMDGPU_RAS_BLOCK_MASK;
2515
2516
2517         /*
2518          * Disable ras feature for aqua vanjaram
2519          * by default on apu platform.
2520          */
2521         if (adev->ip_versions[MP0_HWIP][0] == IP_VERSION(13, 0, 6) &&
2522             adev->gmc.is_app_apu)
2523                 adev->ras_enabled = amdgpu_ras_enable != 1 ? 0 :
2524                         adev->ras_hw_enabled & amdgpu_ras_mask;
2525         else
2526                 adev->ras_enabled = amdgpu_ras_enable == 0 ? 0 :
2527                         adev->ras_hw_enabled & amdgpu_ras_mask;
2528 }
2529
2530 static void amdgpu_ras_counte_dw(struct work_struct *work)
2531 {
2532         struct amdgpu_ras *con = container_of(work, struct amdgpu_ras,
2533                                               ras_counte_delay_work.work);
2534         struct amdgpu_device *adev = con->adev;
2535         struct drm_device *dev = adev_to_drm(adev);
2536         unsigned long ce_count, ue_count;
2537         int res;
2538
2539         res = pm_runtime_get_sync(dev->dev);
2540         if (res < 0)
2541                 goto Out;
2542
2543         /* Cache new values.
2544          */
2545         if (amdgpu_ras_query_error_count(adev, &ce_count, &ue_count, NULL) == 0) {
2546                 atomic_set(&con->ras_ce_count, ce_count);
2547                 atomic_set(&con->ras_ue_count, ue_count);
2548         }
2549
2550         pm_runtime_mark_last_busy(dev->dev);
2551 Out:
2552         pm_runtime_put_autosuspend(dev->dev);
2553 }
2554
2555 static void amdgpu_ras_query_poison_mode(struct amdgpu_device *adev)
2556 {
2557         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
2558         bool df_poison, umc_poison;
2559
2560         /* poison setting is useless on SRIOV guest */
2561         if (amdgpu_sriov_vf(adev) || !con)
2562                 return;
2563
2564         /* Init poison supported flag, the default value is false */
2565         if (adev->gmc.xgmi.connected_to_cpu) {
2566                 /* enabled by default when GPU is connected to CPU */
2567                 con->poison_supported = true;
2568         } else if (adev->df.funcs &&
2569             adev->df.funcs->query_ras_poison_mode &&
2570             adev->umc.ras &&
2571             adev->umc.ras->query_ras_poison_mode) {
2572                 df_poison =
2573                         adev->df.funcs->query_ras_poison_mode(adev);
2574                 umc_poison =
2575                         adev->umc.ras->query_ras_poison_mode(adev);
2576
2577                 /* Only poison is set in both DF and UMC, we can support it */
2578                 if (df_poison && umc_poison)
2579                         con->poison_supported = true;
2580                 else if (df_poison != umc_poison)
2581                         dev_warn(adev->dev,
2582                                 "Poison setting is inconsistent in DF/UMC(%d:%d)!\n",
2583                                 df_poison, umc_poison);
2584         }
2585 }
2586
2587 int amdgpu_ras_init(struct amdgpu_device *adev)
2588 {
2589         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
2590         int r;
2591
2592         if (con)
2593                 return 0;
2594
2595         con = kmalloc(sizeof(struct amdgpu_ras) +
2596                         sizeof(struct ras_manager) * AMDGPU_RAS_BLOCK_COUNT +
2597                         sizeof(struct ras_manager) * AMDGPU_RAS_MCA_BLOCK_COUNT,
2598                         GFP_KERNEL|__GFP_ZERO);
2599         if (!con)
2600                 return -ENOMEM;
2601
2602         con->adev = adev;
2603         INIT_DELAYED_WORK(&con->ras_counte_delay_work, amdgpu_ras_counte_dw);
2604         atomic_set(&con->ras_ce_count, 0);
2605         atomic_set(&con->ras_ue_count, 0);
2606
2607         con->objs = (struct ras_manager *)(con + 1);
2608
2609         amdgpu_ras_set_context(adev, con);
2610
2611         amdgpu_ras_check_supported(adev);
2612
2613         if (!adev->ras_enabled || adev->asic_type == CHIP_VEGA10) {
2614                 /* set gfx block ras context feature for VEGA20 Gaming
2615                  * send ras disable cmd to ras ta during ras late init.
2616                  */
2617                 if (!adev->ras_enabled && adev->asic_type == CHIP_VEGA20) {
2618                         con->features |= BIT(AMDGPU_RAS_BLOCK__GFX);
2619
2620                         return 0;
2621                 }
2622
2623                 r = 0;
2624                 goto release_con;
2625         }
2626
2627         con->update_channel_flag = false;
2628         con->features = 0;
2629         INIT_LIST_HEAD(&con->head);
2630         /* Might need get this flag from vbios. */
2631         con->flags = RAS_DEFAULT_FLAGS;
2632
2633         /* initialize nbio ras function ahead of any other
2634          * ras functions so hardware fatal error interrupt
2635          * can be enabled as early as possible */
2636         switch (adev->ip_versions[NBIO_HWIP][0]) {
2637         case IP_VERSION(7, 4, 0):
2638         case IP_VERSION(7, 4, 1):
2639         case IP_VERSION(7, 4, 4):
2640                 if (!adev->gmc.xgmi.connected_to_cpu)
2641                         adev->nbio.ras = &nbio_v7_4_ras;
2642                 break;
2643         case IP_VERSION(4, 3, 0):
2644                 if (adev->ras_hw_enabled & (1 << AMDGPU_RAS_BLOCK__DF))
2645                         /* unlike other generation of nbio ras,
2646                          * nbio v4_3 only support fatal error interrupt
2647                          * to inform software that DF is freezed due to
2648                          * system fatal error event. driver should not
2649                          * enable nbio ras in such case. Instead,
2650                          * check DF RAS */
2651                         adev->nbio.ras = &nbio_v4_3_ras;
2652                 break;
2653         case IP_VERSION(7, 9, 0):
2654                 if (!adev->gmc.is_app_apu)
2655                         adev->nbio.ras = &nbio_v7_9_ras;
2656                 break;
2657         default:
2658                 /* nbio ras is not available */
2659                 break;
2660         }
2661
2662         /* nbio ras block needs to be enabled ahead of other ras blocks
2663          * to handle fatal error */
2664         r = amdgpu_nbio_ras_sw_init(adev);
2665         if (r)
2666                 return r;
2667
2668         if (adev->nbio.ras &&
2669             adev->nbio.ras->init_ras_controller_interrupt) {
2670                 r = adev->nbio.ras->init_ras_controller_interrupt(adev);
2671                 if (r)
2672                         goto release_con;
2673         }
2674
2675         if (adev->nbio.ras &&
2676             adev->nbio.ras->init_ras_err_event_athub_interrupt) {
2677                 r = adev->nbio.ras->init_ras_err_event_athub_interrupt(adev);
2678                 if (r)
2679                         goto release_con;
2680         }
2681
2682         amdgpu_ras_query_poison_mode(adev);
2683
2684         if (amdgpu_ras_fs_init(adev)) {
2685                 r = -EINVAL;
2686                 goto release_con;
2687         }
2688
2689         dev_info(adev->dev, "RAS INFO: ras initialized successfully, "
2690                  "hardware ability[%x] ras_mask[%x]\n",
2691                  adev->ras_hw_enabled, adev->ras_enabled);
2692
2693         return 0;
2694 release_con:
2695         amdgpu_ras_set_context(adev, NULL);
2696         kfree(con);
2697
2698         return r;
2699 }
2700
2701 int amdgpu_persistent_edc_harvesting_supported(struct amdgpu_device *adev)
2702 {
2703         if (adev->gmc.xgmi.connected_to_cpu ||
2704             adev->gmc.is_app_apu)
2705                 return 1;
2706         return 0;
2707 }
2708
2709 static int amdgpu_persistent_edc_harvesting(struct amdgpu_device *adev,
2710                                         struct ras_common_if *ras_block)
2711 {
2712         struct ras_query_if info = {
2713                 .head = *ras_block,
2714         };
2715
2716         if (!amdgpu_persistent_edc_harvesting_supported(adev))
2717                 return 0;
2718
2719         if (amdgpu_ras_query_error_status(adev, &info) != 0)
2720                 DRM_WARN("RAS init harvest failure");
2721
2722         if (amdgpu_ras_reset_error_status(adev, ras_block->block) != 0)
2723                 DRM_WARN("RAS init harvest reset failure");
2724
2725         return 0;
2726 }
2727
2728 bool amdgpu_ras_is_poison_mode_supported(struct amdgpu_device *adev)
2729 {
2730        struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
2731
2732        if (!con)
2733                return false;
2734
2735        return con->poison_supported;
2736 }
2737
2738 /* helper function to handle common stuff in ip late init phase */
2739 int amdgpu_ras_block_late_init(struct amdgpu_device *adev,
2740                          struct ras_common_if *ras_block)
2741 {
2742         struct amdgpu_ras_block_object *ras_obj = NULL;
2743         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
2744         struct ras_query_if *query_info;
2745         unsigned long ue_count, ce_count;
2746         int r;
2747
2748         /* disable RAS feature per IP block if it is not supported */
2749         if (!amdgpu_ras_is_supported(adev, ras_block->block)) {
2750                 amdgpu_ras_feature_enable_on_boot(adev, ras_block, 0);
2751                 return 0;
2752         }
2753
2754         r = amdgpu_ras_feature_enable_on_boot(adev, ras_block, 1);
2755         if (r) {
2756                 if (adev->in_suspend || amdgpu_in_reset(adev)) {
2757                         /* in resume phase, if fail to enable ras,
2758                          * clean up all ras fs nodes, and disable ras */
2759                         goto cleanup;
2760                 } else
2761                         return r;
2762         }
2763
2764         /* check for errors on warm reset edc persisant supported ASIC */
2765         amdgpu_persistent_edc_harvesting(adev, ras_block);
2766
2767         /* in resume phase, no need to create ras fs node */
2768         if (adev->in_suspend || amdgpu_in_reset(adev))
2769                 return 0;
2770
2771         ras_obj = container_of(ras_block, struct amdgpu_ras_block_object, ras_comm);
2772         if (ras_obj->ras_cb || (ras_obj->hw_ops &&
2773             (ras_obj->hw_ops->query_poison_status ||
2774             ras_obj->hw_ops->handle_poison_consumption))) {
2775                 r = amdgpu_ras_interrupt_add_handler(adev, ras_block);
2776                 if (r)
2777                         goto cleanup;
2778         }
2779
2780         if (ras_obj->hw_ops &&
2781             (ras_obj->hw_ops->query_ras_error_count ||
2782              ras_obj->hw_ops->query_ras_error_status)) {
2783                 r = amdgpu_ras_sysfs_create(adev, ras_block);
2784                 if (r)
2785                         goto interrupt;
2786
2787                 /* Those are the cached values at init.
2788                  */
2789                 query_info = kzalloc(sizeof(*query_info), GFP_KERNEL);
2790                 if (!query_info)
2791                         return -ENOMEM;
2792                 memcpy(&query_info->head, ras_block, sizeof(struct ras_common_if));
2793
2794                 if (amdgpu_ras_query_error_count(adev, &ce_count, &ue_count, query_info) == 0) {
2795                         atomic_set(&con->ras_ce_count, ce_count);
2796                         atomic_set(&con->ras_ue_count, ue_count);
2797                 }
2798
2799                 kfree(query_info);
2800         }
2801
2802         return 0;
2803
2804 interrupt:
2805         if (ras_obj->ras_cb)
2806                 amdgpu_ras_interrupt_remove_handler(adev, ras_block);
2807 cleanup:
2808         amdgpu_ras_feature_enable(adev, ras_block, 0);
2809         return r;
2810 }
2811
2812 static int amdgpu_ras_block_late_init_default(struct amdgpu_device *adev,
2813                          struct ras_common_if *ras_block)
2814 {
2815         return amdgpu_ras_block_late_init(adev, ras_block);
2816 }
2817
2818 /* helper function to remove ras fs node and interrupt handler */
2819 void amdgpu_ras_block_late_fini(struct amdgpu_device *adev,
2820                           struct ras_common_if *ras_block)
2821 {
2822         struct amdgpu_ras_block_object *ras_obj;
2823         if (!ras_block)
2824                 return;
2825
2826         amdgpu_ras_sysfs_remove(adev, ras_block);
2827
2828         ras_obj = container_of(ras_block, struct amdgpu_ras_block_object, ras_comm);
2829         if (ras_obj->ras_cb)
2830                 amdgpu_ras_interrupt_remove_handler(adev, ras_block);
2831 }
2832
2833 static void amdgpu_ras_block_late_fini_default(struct amdgpu_device *adev,
2834                           struct ras_common_if *ras_block)
2835 {
2836         return amdgpu_ras_block_late_fini(adev, ras_block);
2837 }
2838
2839 /* do some init work after IP late init as dependence.
2840  * and it runs in resume/gpu reset/booting up cases.
2841  */
2842 void amdgpu_ras_resume(struct amdgpu_device *adev)
2843 {
2844         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
2845         struct ras_manager *obj, *tmp;
2846
2847         if (!adev->ras_enabled || !con) {
2848                 /* clean ras context for VEGA20 Gaming after send ras disable cmd */
2849                 amdgpu_release_ras_context(adev);
2850
2851                 return;
2852         }
2853
2854         if (con->flags & AMDGPU_RAS_FLAG_INIT_BY_VBIOS) {
2855                 /* Set up all other IPs which are not implemented. There is a
2856                  * tricky thing that IP's actual ras error type should be
2857                  * MULTI_UNCORRECTABLE, but as driver does not handle it, so
2858                  * ERROR_NONE make sense anyway.
2859                  */
2860                 amdgpu_ras_enable_all_features(adev, 1);
2861
2862                 /* We enable ras on all hw_supported block, but as boot
2863                  * parameter might disable some of them and one or more IP has
2864                  * not implemented yet. So we disable them on behalf.
2865                  */
2866                 list_for_each_entry_safe(obj, tmp, &con->head, node) {
2867                         if (!amdgpu_ras_is_supported(adev, obj->head.block)) {
2868                                 amdgpu_ras_feature_enable(adev, &obj->head, 0);
2869                                 /* there should be no any reference. */
2870                                 WARN_ON(alive_obj(obj));
2871                         }
2872                 }
2873         }
2874 }
2875
2876 void amdgpu_ras_suspend(struct amdgpu_device *adev)
2877 {
2878         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
2879
2880         if (!adev->ras_enabled || !con)
2881                 return;
2882
2883         amdgpu_ras_disable_all_features(adev, 0);
2884         /* Make sure all ras objects are disabled. */
2885         if (con->features)
2886                 amdgpu_ras_disable_all_features(adev, 1);
2887 }
2888
2889 int amdgpu_ras_late_init(struct amdgpu_device *adev)
2890 {
2891         struct amdgpu_ras_block_list *node, *tmp;
2892         struct amdgpu_ras_block_object *obj;
2893         int r;
2894
2895         /* Guest side doesn't need init ras feature */
2896         if (amdgpu_sriov_vf(adev))
2897                 return 0;
2898
2899         list_for_each_entry_safe(node, tmp, &adev->ras_list, node) {
2900                 if (!node->ras_obj) {
2901                         dev_warn(adev->dev, "Warning: abnormal ras list node.\n");
2902                         continue;
2903                 }
2904
2905                 obj = node->ras_obj;
2906                 if (obj->ras_late_init) {
2907                         r = obj->ras_late_init(adev, &obj->ras_comm);
2908                         if (r) {
2909                                 dev_err(adev->dev, "%s failed to execute ras_late_init! ret:%d\n",
2910                                         obj->ras_comm.name, r);
2911                                 return r;
2912                         }
2913                 } else
2914                         amdgpu_ras_block_late_init_default(adev, &obj->ras_comm);
2915         }
2916
2917         return 0;
2918 }
2919
2920 /* do some fini work before IP fini as dependence */
2921 int amdgpu_ras_pre_fini(struct amdgpu_device *adev)
2922 {
2923         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
2924
2925         if (!adev->ras_enabled || !con)
2926                 return 0;
2927
2928
2929         /* Need disable ras on all IPs here before ip [hw/sw]fini */
2930         if (con->features)
2931                 amdgpu_ras_disable_all_features(adev, 0);
2932         amdgpu_ras_recovery_fini(adev);
2933         return 0;
2934 }
2935
2936 int amdgpu_ras_fini(struct amdgpu_device *adev)
2937 {
2938         struct amdgpu_ras_block_list *ras_node, *tmp;
2939         struct amdgpu_ras_block_object *obj = NULL;
2940         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
2941
2942         if (!adev->ras_enabled || !con)
2943                 return 0;
2944
2945         list_for_each_entry_safe(ras_node, tmp, &adev->ras_list, node) {
2946                 if (ras_node->ras_obj) {
2947                         obj = ras_node->ras_obj;
2948                         if (amdgpu_ras_is_supported(adev, obj->ras_comm.block) &&
2949                             obj->ras_fini)
2950                                 obj->ras_fini(adev, &obj->ras_comm);
2951                         else
2952                                 amdgpu_ras_block_late_fini_default(adev, &obj->ras_comm);
2953                 }
2954
2955                 /* Clear ras blocks from ras_list and free ras block list node */
2956                 list_del(&ras_node->node);
2957                 kfree(ras_node);
2958         }
2959
2960         amdgpu_ras_fs_fini(adev);
2961         amdgpu_ras_interrupt_remove_all(adev);
2962
2963         WARN(con->features, "Feature mask is not cleared");
2964
2965         if (con->features)
2966                 amdgpu_ras_disable_all_features(adev, 1);
2967
2968         cancel_delayed_work_sync(&con->ras_counte_delay_work);
2969
2970         amdgpu_ras_set_context(adev, NULL);
2971         kfree(con);
2972
2973         return 0;
2974 }
2975
2976 void amdgpu_ras_global_ras_isr(struct amdgpu_device *adev)
2977 {
2978         if (atomic_cmpxchg(&amdgpu_ras_in_intr, 0, 1) == 0) {
2979                 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev);
2980
2981                 dev_info(adev->dev, "uncorrectable hardware error"
2982                         "(ERREVENT_ATHUB_INTERRUPT) detected!\n");
2983
2984                 ras->gpu_reset_flags |= AMDGPU_RAS_GPU_RESET_MODE1_RESET;
2985                 amdgpu_ras_reset_gpu(adev);
2986         }
2987 }
2988
2989 bool amdgpu_ras_need_emergency_restart(struct amdgpu_device *adev)
2990 {
2991         if (adev->asic_type == CHIP_VEGA20 &&
2992             adev->pm.fw_version <= 0x283400) {
2993                 return !(amdgpu_asic_reset_method(adev) == AMD_RESET_METHOD_BACO) &&
2994                                 amdgpu_ras_intr_triggered();
2995         }
2996
2997         return false;
2998 }
2999
3000 void amdgpu_release_ras_context(struct amdgpu_device *adev)
3001 {
3002         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
3003
3004         if (!con)
3005                 return;
3006
3007         if (!adev->ras_enabled && con->features & BIT(AMDGPU_RAS_BLOCK__GFX)) {
3008                 con->features &= ~BIT(AMDGPU_RAS_BLOCK__GFX);
3009                 amdgpu_ras_set_context(adev, NULL);
3010                 kfree(con);
3011         }
3012 }
3013
3014 #ifdef CONFIG_X86_MCE_AMD
3015 static struct amdgpu_device *find_adev(uint32_t node_id)
3016 {
3017         int i;
3018         struct amdgpu_device *adev = NULL;
3019
3020         for (i = 0; i < mce_adev_list.num_gpu; i++) {
3021                 adev = mce_adev_list.devs[i];
3022
3023                 if (adev && adev->gmc.xgmi.connected_to_cpu &&
3024                     adev->gmc.xgmi.physical_node_id == node_id)
3025                         break;
3026                 adev = NULL;
3027         }
3028
3029         return adev;
3030 }
3031
3032 #define GET_MCA_IPID_GPUID(m)   (((m) >> 44) & 0xF)
3033 #define GET_UMC_INST(m)         (((m) >> 21) & 0x7)
3034 #define GET_CHAN_INDEX(m)       ((((m) >> 12) & 0x3) | (((m) >> 18) & 0x4))
3035 #define GPU_ID_OFFSET           8
3036
3037 static int amdgpu_bad_page_notifier(struct notifier_block *nb,
3038                                     unsigned long val, void *data)
3039 {
3040         struct mce *m = (struct mce *)data;
3041         struct amdgpu_device *adev = NULL;
3042         uint32_t gpu_id = 0;
3043         uint32_t umc_inst = 0, ch_inst = 0;
3044
3045         /*
3046          * If the error was generated in UMC_V2, which belongs to GPU UMCs,
3047          * and error occurred in DramECC (Extended error code = 0) then only
3048          * process the error, else bail out.
3049          */
3050         if (!m || !((smca_get_bank_type(m->extcpu, m->bank) == SMCA_UMC_V2) &&
3051                     (XEC(m->status, 0x3f) == 0x0)))
3052                 return NOTIFY_DONE;
3053
3054         /*
3055          * If it is correctable error, return.
3056          */
3057         if (mce_is_correctable(m))
3058                 return NOTIFY_OK;
3059
3060         /*
3061          * GPU Id is offset by GPU_ID_OFFSET in MCA_IPID_UMC register.
3062          */
3063         gpu_id = GET_MCA_IPID_GPUID(m->ipid) - GPU_ID_OFFSET;
3064
3065         adev = find_adev(gpu_id);
3066         if (!adev) {
3067                 DRM_WARN("%s: Unable to find adev for gpu_id: %d\n", __func__,
3068                                                                 gpu_id);
3069                 return NOTIFY_DONE;
3070         }
3071
3072         /*
3073          * If it is uncorrectable error, then find out UMC instance and
3074          * channel index.
3075          */
3076         umc_inst = GET_UMC_INST(m->ipid);
3077         ch_inst = GET_CHAN_INDEX(m->ipid);
3078
3079         dev_info(adev->dev, "Uncorrectable error detected in UMC inst: %d, chan_idx: %d",
3080                              umc_inst, ch_inst);
3081
3082         if (!amdgpu_umc_page_retirement_mca(adev, m->addr, ch_inst, umc_inst))
3083                 return NOTIFY_OK;
3084         else
3085                 return NOTIFY_DONE;
3086 }
3087
3088 static struct notifier_block amdgpu_bad_page_nb = {
3089         .notifier_call  = amdgpu_bad_page_notifier,
3090         .priority       = MCE_PRIO_UC,
3091 };
3092
3093 static void amdgpu_register_bad_pages_mca_notifier(struct amdgpu_device *adev)
3094 {
3095         /*
3096          * Add the adev to the mce_adev_list.
3097          * During mode2 reset, amdgpu device is temporarily
3098          * removed from the mgpu_info list which can cause
3099          * page retirement to fail.
3100          * Use this list instead of mgpu_info to find the amdgpu
3101          * device on which the UMC error was reported.
3102          */
3103         mce_adev_list.devs[mce_adev_list.num_gpu++] = adev;
3104
3105         /*
3106          * Register the x86 notifier only once
3107          * with MCE subsystem.
3108          */
3109         if (notifier_registered == false) {
3110                 mce_register_decode_chain(&amdgpu_bad_page_nb);
3111                 notifier_registered = true;
3112         }
3113 }
3114 #endif
3115
3116 struct amdgpu_ras *amdgpu_ras_get_context(struct amdgpu_device *adev)
3117 {
3118         if (!adev)
3119                 return NULL;
3120
3121         return adev->psp.ras_context.ras;
3122 }
3123
3124 int amdgpu_ras_set_context(struct amdgpu_device *adev, struct amdgpu_ras *ras_con)
3125 {
3126         if (!adev)
3127                 return -EINVAL;
3128
3129         adev->psp.ras_context.ras = ras_con;
3130         return 0;
3131 }
3132
3133 /* check if ras is supported on block, say, sdma, gfx */
3134 int amdgpu_ras_is_supported(struct amdgpu_device *adev,
3135                 unsigned int block)
3136 {
3137         int ret = 0;
3138         struct amdgpu_ras *ras = amdgpu_ras_get_context(adev);
3139
3140         if (block >= AMDGPU_RAS_BLOCK_COUNT)
3141                 return 0;
3142
3143         ret = ras && (adev->ras_enabled & (1 << block));
3144
3145         /* For the special asic with mem ecc enabled but sram ecc
3146          * not enabled, even if the ras block is not supported on
3147          * .ras_enabled, if the asic supports poison mode and the
3148          * ras block has ras configuration, it can be considered
3149          * that the ras block supports ras function.
3150          */
3151         if (!ret &&
3152             (block == AMDGPU_RAS_BLOCK__GFX ||
3153              block == AMDGPU_RAS_BLOCK__SDMA ||
3154              block == AMDGPU_RAS_BLOCK__VCN ||
3155              block == AMDGPU_RAS_BLOCK__JPEG) &&
3156             amdgpu_ras_is_poison_mode_supported(adev) &&
3157             amdgpu_ras_get_ras_block(adev, block, 0))
3158                 ret = 1;
3159
3160         return ret;
3161 }
3162
3163 int amdgpu_ras_reset_gpu(struct amdgpu_device *adev)
3164 {
3165         struct amdgpu_ras *ras = amdgpu_ras_get_context(adev);
3166
3167         if (atomic_cmpxchg(&ras->in_recovery, 0, 1) == 0)
3168                 amdgpu_reset_domain_schedule(ras->adev->reset_domain, &ras->recovery_work);
3169         return 0;
3170 }
3171
3172
3173 /* Register each ip ras block into amdgpu ras */
3174 int amdgpu_ras_register_ras_block(struct amdgpu_device *adev,
3175                 struct amdgpu_ras_block_object *ras_block_obj)
3176 {
3177         struct amdgpu_ras_block_list *ras_node;
3178         if (!adev || !ras_block_obj)
3179                 return -EINVAL;
3180
3181         ras_node = kzalloc(sizeof(*ras_node), GFP_KERNEL);
3182         if (!ras_node)
3183                 return -ENOMEM;
3184
3185         INIT_LIST_HEAD(&ras_node->node);
3186         ras_node->ras_obj = ras_block_obj;
3187         list_add_tail(&ras_node->node, &adev->ras_list);
3188
3189         return 0;
3190 }
3191
3192 void amdgpu_ras_get_error_type_name(uint32_t err_type, char *err_type_name)
3193 {
3194         if (!err_type_name)
3195                 return;
3196
3197         switch (err_type) {
3198         case AMDGPU_RAS_ERROR__SINGLE_CORRECTABLE:
3199                 sprintf(err_type_name, "correctable");
3200                 break;
3201         case AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE:
3202                 sprintf(err_type_name, "uncorrectable");
3203                 break;
3204         default:
3205                 sprintf(err_type_name, "unknown");
3206                 break;
3207         }
3208 }
3209
3210 bool amdgpu_ras_inst_get_memory_id_field(struct amdgpu_device *adev,
3211                                          const struct amdgpu_ras_err_status_reg_entry *reg_entry,
3212                                          uint32_t instance,
3213                                          uint32_t *memory_id)
3214 {
3215         uint32_t err_status_lo_data, err_status_lo_offset;
3216
3217         if (!reg_entry)
3218                 return false;
3219
3220         err_status_lo_offset =
3221                 AMDGPU_RAS_REG_ENTRY_OFFSET(reg_entry->hwip, instance,
3222                                             reg_entry->seg_lo, reg_entry->reg_lo);
3223         err_status_lo_data = RREG32(err_status_lo_offset);
3224
3225         if ((reg_entry->flags & AMDGPU_RAS_ERR_STATUS_VALID) &&
3226             !REG_GET_FIELD(err_status_lo_data, ERR_STATUS_LO, ERR_STATUS_VALID_FLAG))
3227                 return false;
3228
3229         *memory_id = REG_GET_FIELD(err_status_lo_data, ERR_STATUS_LO, MEMORY_ID);
3230
3231         return true;
3232 }
3233
3234 bool amdgpu_ras_inst_get_err_cnt_field(struct amdgpu_device *adev,
3235                                        const struct amdgpu_ras_err_status_reg_entry *reg_entry,
3236                                        uint32_t instance,
3237                                        unsigned long *err_cnt)
3238 {
3239         uint32_t err_status_hi_data, err_status_hi_offset;
3240
3241         if (!reg_entry)
3242                 return false;
3243
3244         err_status_hi_offset =
3245                 AMDGPU_RAS_REG_ENTRY_OFFSET(reg_entry->hwip, instance,
3246                                             reg_entry->seg_hi, reg_entry->reg_hi);
3247         err_status_hi_data = RREG32(err_status_hi_offset);
3248
3249         if ((reg_entry->flags & AMDGPU_RAS_ERR_INFO_VALID) &&
3250             !REG_GET_FIELD(err_status_hi_data, ERR_STATUS_HI, ERR_INFO_VALID_FLAG))
3251                 /* keep the check here in case we need to refer to the result later */
3252                 dev_dbg(adev->dev, "Invalid err_info field\n");
3253
3254         /* read err count */
3255         *err_cnt = REG_GET_FIELD(err_status_hi_data, ERR_STATUS, ERR_CNT);
3256
3257         return true;
3258 }
3259
3260 void amdgpu_ras_inst_query_ras_error_count(struct amdgpu_device *adev,
3261                                            const struct amdgpu_ras_err_status_reg_entry *reg_list,
3262                                            uint32_t reg_list_size,
3263                                            const struct amdgpu_ras_memory_id_entry *mem_list,
3264                                            uint32_t mem_list_size,
3265                                            uint32_t instance,
3266                                            uint32_t err_type,
3267                                            unsigned long *err_count)
3268 {
3269         uint32_t memory_id;
3270         unsigned long err_cnt;
3271         char err_type_name[16];
3272         uint32_t i, j;
3273
3274         for (i = 0; i < reg_list_size; i++) {
3275                 /* query memory_id from err_status_lo */
3276                 if (!amdgpu_ras_inst_get_memory_id_field(adev, &reg_list[i],
3277                                                          instance, &memory_id))
3278                         continue;
3279
3280                 /* query err_cnt from err_status_hi */
3281                 if (!amdgpu_ras_inst_get_err_cnt_field(adev, &reg_list[i],
3282                                                        instance, &err_cnt) ||
3283                     !err_cnt)
3284                         continue;
3285
3286                 *err_count += err_cnt;
3287
3288                 /* log the errors */
3289                 amdgpu_ras_get_error_type_name(err_type, err_type_name);
3290                 if (!mem_list) {
3291                         /* memory_list is not supported */
3292                         dev_info(adev->dev,
3293                                  "%ld %s hardware errors detected in %s, instance: %d, memory_id: %d\n",
3294                                  err_cnt, err_type_name,
3295                                  reg_list[i].block_name,
3296                                  instance, memory_id);
3297                 } else {
3298                         for (j = 0; j < mem_list_size; j++) {
3299                                 if (memory_id == mem_list[j].memory_id) {
3300                                         dev_info(adev->dev,
3301                                                  "%ld %s hardware errors detected in %s, instance: %d, memory block: %s\n",
3302                                                  err_cnt, err_type_name,
3303                                                  reg_list[i].block_name,
3304                                                  instance, mem_list[j].name);
3305                                         break;
3306                                 }
3307                         }
3308                 }
3309         }
3310 }
3311
3312 void amdgpu_ras_inst_reset_ras_error_count(struct amdgpu_device *adev,
3313                                            const struct amdgpu_ras_err_status_reg_entry *reg_list,
3314                                            uint32_t reg_list_size,
3315                                            uint32_t instance)
3316 {
3317         uint32_t err_status_lo_offset, err_status_hi_offset;
3318         uint32_t i;
3319
3320         for (i = 0; i < reg_list_size; i++) {
3321                 err_status_lo_offset =
3322                         AMDGPU_RAS_REG_ENTRY_OFFSET(reg_list[i].hwip, instance,
3323                                                     reg_list[i].seg_lo, reg_list[i].reg_lo);
3324                 err_status_hi_offset =
3325                         AMDGPU_RAS_REG_ENTRY_OFFSET(reg_list[i].hwip, instance,
3326                                                     reg_list[i].seg_hi, reg_list[i].reg_hi);
3327                 WREG32(err_status_lo_offset, 0);
3328                 WREG32(err_status_hi_offset, 0);
3329         }
3330 }