drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c

   1 /*
   2  * Copyright 2018 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  *
  23  */
  24 #include <linux/debugfs.h>
  25 #include <linux/list.h>
  26 #include <linux/module.h>
  27 #include <linux/uaccess.h>
  28 #include <linux/reboot.h>
  29 #include <linux/syscalls.h>
  30 #include <linux/pm_runtime.h>
  31
  32 #include "amdgpu.h"
  33 #include "amdgpu_ras.h"
  34 #include "amdgpu_atomfirmware.h"
  35 #include "amdgpu_xgmi.h"
  36 #include "ivsrcid/nbio/irqsrcs_nbif_7_4.h"
  37 #include "nbio_v4_3.h"
  38 #include "nbio_v7_9.h"
  39 #include "atom.h"
  40 #include "amdgpu_reset.h"
  41
  42 #ifdef CONFIG_X86_MCE_AMD
  43 #include <asm/mce.h>
  44
  45 static bool notifier_registered;
  46 #endif
  47 static const char *RAS_FS_NAME = "ras";
  48
  49 const char *ras_error_string[] = {
  50         "none",
  51         "parity",
  52         "single_correctable",
  53         "multi_uncorrectable",
  54         "poison",
  55 };
  56
  57 const char *ras_block_string[] = {
  58         "umc",
  59         "sdma",
  60         "gfx",
  61         "mmhub",
  62         "athub",
  63         "pcie_bif",
  64         "hdp",
  65         "xgmi_wafl",
  66         "df",
  67         "smn",
  68         "sem",
  69         "mp0",
  70         "mp1",
  71         "fuse",
  72         "mca",
  73         "vcn",
  74         "jpeg",
  75 };
  76
  77 const char *ras_mca_block_string[] = {
  78         "mca_mp0",
  79         "mca_mp1",
  80         "mca_mpio",
  81         "mca_iohc",
  82 };
  83
  84 struct amdgpu_ras_block_list {
  85         /* ras block link */
  86         struct list_head node;
  87
  88         struct amdgpu_ras_block_object *ras_obj;
  89 };
  90
  91 const char *get_ras_block_str(struct ras_common_if *ras_block)
  92 {
  93         if (!ras_block)
  94                 return "NULL";
  95
  96         if (ras_block->block >= AMDGPU_RAS_BLOCK_COUNT)
  97                 return "OUT OF RANGE";
  98
  99         if (ras_block->block == AMDGPU_RAS_BLOCK__MCA)
 100                 return ras_mca_block_string[ras_block->sub_block_index];
 101
 102         return ras_block_string[ras_block->block];
 103 }
 104
 105 #define ras_block_str(_BLOCK_) \
 106         (((_BLOCK_) < ARRAY_SIZE(ras_block_string)) ? ras_block_string[_BLOCK_] : "Out Of Range")
 107
 108 #define ras_err_str(i) (ras_error_string[ffs(i)])
 109
 110 #define RAS_DEFAULT_FLAGS (AMDGPU_RAS_FLAG_INIT_BY_VBIOS)
 111
 112 /* inject address is 52 bits */
 113 #define RAS_UMC_INJECT_ADDR_LIMIT       (0x1ULL << 52)
 114
 115 /* typical ECC bad page rate is 1 bad page per 100MB VRAM */
 116 #define RAS_BAD_PAGE_COVER              (100 * 1024 * 1024ULL)
 117
 118 enum amdgpu_ras_retire_page_reservation {
 119         AMDGPU_RAS_RETIRE_PAGE_RESERVED,
 120         AMDGPU_RAS_RETIRE_PAGE_PENDING,
 121         AMDGPU_RAS_RETIRE_PAGE_FAULT,
 122 };
 123
 124 atomic_t amdgpu_ras_in_intr = ATOMIC_INIT(0);
 125
 126 static bool amdgpu_ras_check_bad_page_unlock(struct amdgpu_ras *con,
 127                                 uint64_t addr);
 128 static bool amdgpu_ras_check_bad_page(struct amdgpu_device *adev,
 129                                 uint64_t addr);
 130 #ifdef CONFIG_X86_MCE_AMD
 131 static void amdgpu_register_bad_pages_mca_notifier(struct amdgpu_device *adev);
 132 struct mce_notifier_adev_list {
 133         struct amdgpu_device *devs[MAX_GPU_INSTANCE];
 134         int num_gpu;
 135 };
 136 static struct mce_notifier_adev_list mce_adev_list;
 137 #endif
 138
 139 void amdgpu_ras_set_error_query_ready(struct amdgpu_device *adev, bool ready)
 140 {
 141         if (adev && amdgpu_ras_get_context(adev))
 142                 amdgpu_ras_get_context(adev)->error_query_ready = ready;
 143 }
 144
 145 static bool amdgpu_ras_get_error_query_ready(struct amdgpu_device *adev)
 146 {
 147         if (adev && amdgpu_ras_get_context(adev))
 148                 return amdgpu_ras_get_context(adev)->error_query_ready;
 149
 150         return false;
 151 }
 152
 153 static int amdgpu_reserve_page_direct(struct amdgpu_device *adev, uint64_t address)
 154 {
 155         struct ras_err_data err_data;
 156         struct eeprom_table_record err_rec;
 157         int ret;
 158
 159         if ((address >= adev->gmc.mc_vram_size) ||
 160             (address >= RAS_UMC_INJECT_ADDR_LIMIT)) {
 161                 dev_warn(adev->dev,
 162                          "RAS WARN: input address 0x%llx is invalid.\n",
 163                          address);
 164                 return -EINVAL;
 165         }
 166
 167         if (amdgpu_ras_check_bad_page(adev, address)) {
 168                 dev_warn(adev->dev,
 169                          "RAS WARN: 0x%llx has already been marked as bad page!\n",
 170                          address);
 171                 return 0;
 172         }
 173
 174         ret = amdgpu_ras_error_data_init(&err_data);
 175         if (ret)
 176                 return ret;
 177
 178         memset(&err_rec, 0x0, sizeof(struct eeprom_table_record));
 179         err_data.err_addr = &err_rec;
 180         amdgpu_umc_fill_error_record(&err_data, address, address, 0, 0);
 181
 182         if (amdgpu_bad_page_threshold != 0) {
 183                 amdgpu_ras_add_bad_pages(adev, err_data.err_addr,
 184                                          err_data.err_addr_cnt);
 185                 amdgpu_ras_save_bad_pages(adev, NULL);
 186         }
 187
 188         amdgpu_ras_error_data_fini(&err_data);
 189
 190         dev_warn(adev->dev, "WARNING: THIS IS ONLY FOR TEST PURPOSES AND WILL CORRUPT RAS EEPROM\n");
 191         dev_warn(adev->dev, "Clear EEPROM:\n");
 192         dev_warn(adev->dev, "    echo 1 > /sys/kernel/debug/dri/0/ras/ras_eeprom_reset\n");
 193
 194         return 0;
 195 }
 196
 197 static ssize_t amdgpu_ras_debugfs_read(struct file *f, char __user *buf,
 198                                         size_t size, loff_t *pos)
 199 {
 200         struct ras_manager *obj = (struct ras_manager *)file_inode(f)->i_private;
 201         struct ras_query_if info = {
 202                 .head = obj->head,
 203         };
 204         ssize_t s;
 205         char val[128];
 206
 207         if (amdgpu_ras_query_error_status(obj->adev, &info))
 208                 return -EINVAL;
 209
 210         /* Hardware counter will be reset automatically after the query on Vega20 and Arcturus */
 211         if (amdgpu_ip_version(obj->adev, MP0_HWIP, 0) != IP_VERSION(11, 0, 2) &&
 212             amdgpu_ip_version(obj->adev, MP0_HWIP, 0) != IP_VERSION(11, 0, 4)) {
 213                 if (amdgpu_ras_reset_error_status(obj->adev, info.head.block))
 214                         dev_warn(obj->adev->dev, "Failed to reset error counter and error status");
 215         }
 216
 217         s = snprintf(val, sizeof(val), "%s: %lu\n%s: %lu\n",
 218                         "ue", info.ue_count,
 219                         "ce", info.ce_count);
 220         if (*pos >= s)
 221                 return 0;
 222
 223         s -= *pos;
 224         s = min_t(u64, s, size);
 225
 226
 227         if (copy_to_user(buf, &val[*pos], s))
 228                 return -EINVAL;
 229
 230         *pos += s;
 231
 232         return s;
 233 }
 234
 235 static const struct file_operations amdgpu_ras_debugfs_ops = {
 236         .owner = THIS_MODULE,
 237         .read = amdgpu_ras_debugfs_read,
 238         .write = NULL,
 239         .llseek = default_llseek
 240 };
 241
 242 static int amdgpu_ras_find_block_id_by_name(const char *name, int *block_id)
 243 {
 244         int i;
 245
 246         for (i = 0; i < ARRAY_SIZE(ras_block_string); i++) {
 247                 *block_id = i;
 248                 if (strcmp(name, ras_block_string[i]) == 0)
 249                         return 0;
 250         }
 251         return -EINVAL;
 252 }
 253
 254 static int amdgpu_ras_debugfs_ctrl_parse_data(struct file *f,
 255                 const char __user *buf, size_t size,
 256                 loff_t *pos, struct ras_debug_if *data)
 257 {
 258         ssize_t s = min_t(u64, 64, size);
 259         char str[65];
 260         char block_name[33];
 261         char err[9] = "ue";
 262         int op = -1;
 263         int block_id;
 264         uint32_t sub_block;
 265         u64 address, value;
 266         /* default value is 0 if the mask is not set by user */
 267         u32 instance_mask = 0;
 268
 269         if (*pos)
 270                 return -EINVAL;
 271         *pos = size;
 272
 273         memset(str, 0, sizeof(str));
 274         memset(data, 0, sizeof(*data));
 275
 276         if (copy_from_user(str, buf, s))
 277                 return -EINVAL;
 278
 279         if (sscanf(str, "disable %32s", block_name) == 1)
 280                 op = 0;
 281         else if (sscanf(str, "enable %32s %8s", block_name, err) == 2)
 282                 op = 1;
 283         else if (sscanf(str, "inject %32s %8s", block_name, err) == 2)
 284                 op = 2;
 285         else if (strstr(str, "retire_page") != NULL)
 286                 op = 3;
 287         else if (str[0] && str[1] && str[2] && str[3])
 288                 /* ascii string, but commands are not matched. */
 289                 return -EINVAL;
 290
 291         if (op != -1) {
 292                 if (op == 3) {
 293                         if (sscanf(str, "%*s 0x%llx", &address) != 1 &&
 294                             sscanf(str, "%*s %llu", &address) != 1)
 295                                 return -EINVAL;
 296
 297                         data->op = op;
 298                         data->inject.address = address;
 299
 300                         return 0;
 301                 }
 302
 303                 if (amdgpu_ras_find_block_id_by_name(block_name, &block_id))
 304                         return -EINVAL;
 305
 306                 data->head.block = block_id;
 307                 /* only ue and ce errors are supported */
 308                 if (!memcmp("ue", err, 2))
 309                         data->head.type = AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE;
 310                 else if (!memcmp("ce", err, 2))
 311                         data->head.type = AMDGPU_RAS_ERROR__SINGLE_CORRECTABLE;
 312                 else
 313                         return -EINVAL;
 314
 315                 data->op = op;
 316
 317                 if (op == 2) {
 318                         if (sscanf(str, "%*s %*s %*s 0x%x 0x%llx 0x%llx 0x%x",
 319                                    &sub_block, &address, &value, &instance_mask) != 4 &&
 320                             sscanf(str, "%*s %*s %*s %u %llu %llu %u",
 321                                    &sub_block, &address, &value, &instance_mask) != 4 &&
 322                                 sscanf(str, "%*s %*s %*s 0x%x 0x%llx 0x%llx",
 323                                    &sub_block, &address, &value) != 3 &&
 324                             sscanf(str, "%*s %*s %*s %u %llu %llu",
 325                                    &sub_block, &address, &value) != 3)
 326                                 return -EINVAL;
 327                         data->head.sub_block_index = sub_block;
 328                         data->inject.address = address;
 329                         data->inject.value = value;
 330                         data->inject.instance_mask = instance_mask;
 331                 }
 332         } else {
 333                 if (size < sizeof(*data))
 334                         return -EINVAL;
 335
 336                 if (copy_from_user(data, buf, sizeof(*data)))
 337                         return -EINVAL;
 338         }
 339
 340         return 0;
 341 }
 342
 343 static void amdgpu_ras_instance_mask_check(struct amdgpu_device *adev,
 344                                 struct ras_debug_if *data)
 345 {
 346         int num_xcc = adev->gfx.xcc_mask ? NUM_XCC(adev->gfx.xcc_mask) : 1;
 347         uint32_t mask, inst_mask = data->inject.instance_mask;
 348
 349         /* no need to set instance mask if there is only one instance */
 350         if (num_xcc <= 1 && inst_mask) {
 351                 data->inject.instance_mask = 0;
 352                 dev_dbg(adev->dev,
 353                         "RAS inject mask(0x%x) isn't supported and force it to 0.\n",
 354                         inst_mask);
 355
 356                 return;
 357         }
 358
 359         switch (data->head.block) {
 360         case AMDGPU_RAS_BLOCK__GFX:
 361                 mask = GENMASK(num_xcc - 1, 0);
 362                 break;
 363         case AMDGPU_RAS_BLOCK__SDMA:
 364                 mask = GENMASK(adev->sdma.num_instances - 1, 0);
 365                 break;
 366         case AMDGPU_RAS_BLOCK__VCN:
 367         case AMDGPU_RAS_BLOCK__JPEG:
 368                 mask = GENMASK(adev->vcn.num_vcn_inst - 1, 0);
 369                 break;
 370         default:
 371                 mask = inst_mask;
 372                 break;
 373         }
 374
 375         /* remove invalid bits in instance mask */
 376         data->inject.instance_mask &= mask;
 377         if (inst_mask != data->inject.instance_mask)
 378                 dev_dbg(adev->dev,
 379                         "Adjust RAS inject mask 0x%x to 0x%x\n",
 380                         inst_mask, data->inject.instance_mask);
 381 }
 382
 383 /**
 384  * DOC: AMDGPU RAS debugfs control interface
 385  *
 386  * The control interface accepts struct ras_debug_if which has two members.
 387  *
 388  * First member: ras_debug_if::head or ras_debug_if::inject.
 389  *
 390  * head is used to indicate which IP block will be under control.
 391  *
 392  * head has four members, they are block, type, sub_block_index, name.
 393  * block: which IP will be under control.
 394  * type: what kind of error will be enabled/disabled/injected.
 395  * sub_block_index: some IPs have subcomponets. say, GFX, sDMA.
 396  * name: the name of IP.
 397  *
 398  * inject has three more members than head, they are address, value and mask.
 399  * As their names indicate, inject operation will write the
 400  * value to the address.
 401  *
 402  * The second member: struct ras_debug_if::op.
 403  * It has three kinds of operations.
 404  *
 405  * - 0: disable RAS on the block. Take ::head as its data.
 406  * - 1: enable RAS on the block. Take ::head as its data.
 407  * - 2: inject errors on the block. Take ::inject as its data.
 408  *
 409  * How to use the interface?
 410  *
 411  * In a program
 412  *
 413  * Copy the struct ras_debug_if in your code and initialize it.
 414  * Write the struct to the control interface.
 415  *
 416  * From shell
 417  *
 418  * .. code-block:: bash
 419  *
 420  *      echo "disable <block>" > /sys/kernel/debug/dri/<N>/ras/ras_ctrl
 421  *      echo "enable  <block> <error>" > /sys/kernel/debug/dri/<N>/ras/ras_ctrl
 422  *      echo "inject  <block> <error> <sub-block> <address> <value> <mask>" > /sys/kernel/debug/dri/<N>/ras/ras_ctrl
 423  *
 424  * Where N, is the card which you want to affect.
 425  *
 426  * "disable" requires only the block.
 427  * "enable" requires the block and error type.
 428  * "inject" requires the block, error type, address, and value.
 429  *
 430  * The block is one of: umc, sdma, gfx, etc.
 431  *      see ras_block_string[] for details
 432  *
 433  * The error type is one of: ue, ce, where,
 434  *      ue is multi-uncorrectable
 435  *      ce is single-correctable
 436  *
 437  * The sub-block is a the sub-block index, pass 0 if there is no sub-block.
 438  * The address and value are hexadecimal numbers, leading 0x is optional.
 439  * The mask means instance mask, is optional, default value is 0x1.
 440  *
 441  * For instance,
 442  *
 443  * .. code-block:: bash
 444  *
 445  *      echo inject umc ue 0x0 0x0 0x0 > /sys/kernel/debug/dri/0/ras/ras_ctrl
 446  *      echo inject umc ce 0 0 0 3 > /sys/kernel/debug/dri/0/ras/ras_ctrl
 447  *      echo disable umc > /sys/kernel/debug/dri/0/ras/ras_ctrl
 448  *
 449  * How to check the result of the operation?
 450  *
 451  * To check disable/enable, see "ras" features at,
 452  * /sys/class/drm/card[0/1/2...]/device/ras/features
 453  *
 454  * To check inject, see the corresponding error count at,
 455  * /sys/class/drm/card[0/1/2...]/device/ras/[gfx|sdma|umc|...]_err_count
 456  *
 457  * .. note::
 458  *      Operations are only allowed on blocks which are supported.
 459  *      Check the "ras" mask at /sys/module/amdgpu/parameters/ras_mask
 460  *      to see which blocks support RAS on a particular asic.
 461  *
 462  */
 463 static ssize_t amdgpu_ras_debugfs_ctrl_write(struct file *f,
 464                                              const char __user *buf,
 465                                              size_t size, loff_t *pos)
 466 {
 467         struct amdgpu_device *adev = (struct amdgpu_device *)file_inode(f)->i_private;
 468         struct ras_debug_if data;
 469         int ret = 0;
 470
 471         if (!amdgpu_ras_get_error_query_ready(adev)) {
 472                 dev_warn(adev->dev, "RAS WARN: error injection "
 473                                 "currently inaccessible\n");
 474                 return size;
 475         }
 476
 477         ret = amdgpu_ras_debugfs_ctrl_parse_data(f, buf, size, pos, &data);
 478         if (ret)
 479                 return ret;
 480
 481         if (data.op == 3) {
 482                 ret = amdgpu_reserve_page_direct(adev, data.inject.address);
 483                 if (!ret)
 484                         return size;
 485                 else
 486                         return ret;
 487         }
 488
 489         if (!amdgpu_ras_is_supported(adev, data.head.block))
 490                 return -EINVAL;
 491
 492         switch (data.op) {
 493         case 0:
 494                 ret = amdgpu_ras_feature_enable(adev, &data.head, 0);
 495                 break;
 496         case 1:
 497                 ret = amdgpu_ras_feature_enable(adev, &data.head, 1);
 498                 break;
 499         case 2:
 500                 if ((data.inject.address >= adev->gmc.mc_vram_size &&
 501                     adev->gmc.mc_vram_size) ||
 502                     (data.inject.address >= RAS_UMC_INJECT_ADDR_LIMIT)) {
 503                         dev_warn(adev->dev, "RAS WARN: input address "
 504                                         "0x%llx is invalid.",
 505                                         data.inject.address);
 506                         ret = -EINVAL;
 507                         break;
 508                 }
 509
 510                 /* umc ce/ue error injection for a bad page is not allowed */
 511                 if ((data.head.block == AMDGPU_RAS_BLOCK__UMC) &&
 512                     amdgpu_ras_check_bad_page(adev, data.inject.address)) {
 513                         dev_warn(adev->dev, "RAS WARN: inject: 0x%llx has "
 514                                  "already been marked as bad!\n",
 515                                  data.inject.address);
 516                         break;
 517                 }
 518
 519                 amdgpu_ras_instance_mask_check(adev, &data);
 520
 521                 /* data.inject.address is offset instead of absolute gpu address */
 522                 ret = amdgpu_ras_error_inject(adev, &data.inject);
 523                 break;
 524         default:
 525                 ret = -EINVAL;
 526                 break;
 527         }
 528
 529         if (ret)
 530                 return ret;
 531
 532         return size;
 533 }
 534
 535 /**
 536  * DOC: AMDGPU RAS debugfs EEPROM table reset interface
 537  *
 538  * Some boards contain an EEPROM which is used to persistently store a list of
 539  * bad pages which experiences ECC errors in vram.  This interface provides
 540  * a way to reset the EEPROM, e.g., after testing error injection.
 541  *
 542  * Usage:
 543  *
 544  * .. code-block:: bash
 545  *
 546  *      echo 1 > ../ras/ras_eeprom_reset
 547  *
 548  * will reset EEPROM table to 0 entries.
 549  *
 550  */
 551 static ssize_t amdgpu_ras_debugfs_eeprom_write(struct file *f,
 552                                                const char __user *buf,
 553                                                size_t size, loff_t *pos)
 554 {
 555         struct amdgpu_device *adev =
 556                 (struct amdgpu_device *)file_inode(f)->i_private;
 557         int ret;
 558
 559         ret = amdgpu_ras_eeprom_reset_table(
 560                 &(amdgpu_ras_get_context(adev)->eeprom_control));
 561
 562         if (!ret) {
 563                 /* Something was written to EEPROM.
 564                  */
 565                 amdgpu_ras_get_context(adev)->flags = RAS_DEFAULT_FLAGS;
 566                 return size;
 567         } else {
 568                 return ret;
 569         }
 570 }
 571
 572 static const struct file_operations amdgpu_ras_debugfs_ctrl_ops = {
 573         .owner = THIS_MODULE,
 574         .read = NULL,
 575         .write = amdgpu_ras_debugfs_ctrl_write,
 576         .llseek = default_llseek
 577 };
 578
 579 static const struct file_operations amdgpu_ras_debugfs_eeprom_ops = {
 580         .owner = THIS_MODULE,
 581         .read = NULL,
 582         .write = amdgpu_ras_debugfs_eeprom_write,
 583         .llseek = default_llseek
 584 };
 585
 586 /**
 587  * DOC: AMDGPU RAS sysfs Error Count Interface
 588  *
 589  * It allows the user to read the error count for each IP block on the gpu through
 590  * /sys/class/drm/card[0/1/2...]/device/ras/[gfx/sdma/...]_err_count
 591  *
 592  * It outputs the multiple lines which report the uncorrected (ue) and corrected
 593  * (ce) error counts.
 594  *
 595  * The format of one line is below,
 596  *
 597  * [ce|ue]: count
 598  *
 599  * Example:
 600  *
 601  * .. code-block:: bash
 602  *
 603  *      ue: 0
 604  *      ce: 1
 605  *
 606  */
 607 static ssize_t amdgpu_ras_sysfs_read(struct device *dev,
 608                 struct device_attribute *attr, char *buf)
 609 {
 610         struct ras_manager *obj = container_of(attr, struct ras_manager, sysfs_attr);
 611         struct ras_query_if info = {
 612                 .head = obj->head,
 613         };
 614
 615         if (!amdgpu_ras_get_error_query_ready(obj->adev))
 616                 return sysfs_emit(buf, "Query currently inaccessible\n");
 617
 618         if (amdgpu_ras_query_error_status(obj->adev, &info))
 619                 return -EINVAL;
 620
 621         if (amdgpu_ip_version(obj->adev, MP0_HWIP, 0) != IP_VERSION(11, 0, 2) &&
 622             amdgpu_ip_version(obj->adev, MP0_HWIP, 0) != IP_VERSION(11, 0, 4)) {
 623                 if (amdgpu_ras_reset_error_status(obj->adev, info.head.block))
 624                         dev_warn(obj->adev->dev, "Failed to reset error counter and error status");
 625         }
 626
 627         return sysfs_emit(buf, "%s: %lu\n%s: %lu\n", "ue", info.ue_count,
 628                           "ce", info.ce_count);
 629 }
 630
 631 /* obj begin */
 632
 633 #define get_obj(obj) do { (obj)->use++; } while (0)
 634 #define alive_obj(obj) ((obj)->use)
 635
 636 static inline void put_obj(struct ras_manager *obj)
 637 {
 638         if (obj && (--obj->use == 0))
 639                 list_del(&obj->node);
 640         if (obj && (obj->use < 0))
 641                 DRM_ERROR("RAS ERROR: Unbalance obj(%s) use\n", get_ras_block_str(&obj->head));
 642 }
 643
 644 /* make one obj and return it. */
 645 static struct ras_manager *amdgpu_ras_create_obj(struct amdgpu_device *adev,
 646                 struct ras_common_if *head)
 647 {
 648         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
 649         struct ras_manager *obj;
 650
 651         if (!adev->ras_enabled || !con)
 652                 return NULL;
 653
 654         if (head->block >= AMDGPU_RAS_BLOCK_COUNT)
 655                 return NULL;
 656
 657         if (head->block == AMDGPU_RAS_BLOCK__MCA) {
 658                 if (head->sub_block_index >= AMDGPU_RAS_MCA_BLOCK__LAST)
 659                         return NULL;
 660
 661                 obj = &con->objs[AMDGPU_RAS_BLOCK__LAST + head->sub_block_index];
 662         } else
 663                 obj = &con->objs[head->block];
 664
 665         /* already exist. return obj? */
 666         if (alive_obj(obj))
 667                 return NULL;
 668
 669         obj->head = *head;
 670         obj->adev = adev;
 671         list_add(&obj->node, &con->head);
 672         get_obj(obj);
 673
 674         return obj;
 675 }
 676
 677 /* return an obj equal to head, or the first when head is NULL */
 678 struct ras_manager *amdgpu_ras_find_obj(struct amdgpu_device *adev,
 679                 struct ras_common_if *head)
 680 {
 681         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
 682         struct ras_manager *obj;
 683         int i;
 684
 685         if (!adev->ras_enabled || !con)
 686                 return NULL;
 687
 688         if (head) {
 689                 if (head->block >= AMDGPU_RAS_BLOCK_COUNT)
 690                         return NULL;
 691
 692                 if (head->block == AMDGPU_RAS_BLOCK__MCA) {
 693                         if (head->sub_block_index >= AMDGPU_RAS_MCA_BLOCK__LAST)
 694                                 return NULL;
 695
 696                         obj = &con->objs[AMDGPU_RAS_BLOCK__LAST + head->sub_block_index];
 697                 } else
 698                         obj = &con->objs[head->block];
 699
 700                 if (alive_obj(obj))
 701                         return obj;
 702         } else {
 703                 for (i = 0; i < AMDGPU_RAS_BLOCK_COUNT + AMDGPU_RAS_MCA_BLOCK_COUNT; i++) {
 704                         obj = &con->objs[i];
 705                         if (alive_obj(obj))
 706                                 return obj;
 707                 }
 708         }
 709
 710         return NULL;
 711 }
 712 /* obj end */
 713
 714 /* feature ctl begin */
 715 static int amdgpu_ras_is_feature_allowed(struct amdgpu_device *adev,
 716                                          struct ras_common_if *head)
 717 {
 718         return adev->ras_hw_enabled & BIT(head->block);
 719 }
 720
 721 static int amdgpu_ras_is_feature_enabled(struct amdgpu_device *adev,
 722                 struct ras_common_if *head)
 723 {
 724         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
 725
 726         return con->features & BIT(head->block);
 727 }
 728
 729 /*
 730  * if obj is not created, then create one.
 731  * set feature enable flag.
 732  */
 733 static int __amdgpu_ras_feature_enable(struct amdgpu_device *adev,
 734                 struct ras_common_if *head, int enable)
 735 {
 736         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
 737         struct ras_manager *obj = amdgpu_ras_find_obj(adev, head);
 738
 739         /* If hardware does not support ras, then do not create obj.
 740          * But if hardware support ras, we can create the obj.
 741          * Ras framework checks con->hw_supported to see if it need do
 742          * corresponding initialization.
 743          * IP checks con->support to see if it need disable ras.
 744          */
 745         if (!amdgpu_ras_is_feature_allowed(adev, head))
 746                 return 0;
 747
 748         if (enable) {
 749                 if (!obj) {
 750                         obj = amdgpu_ras_create_obj(adev, head);
 751                         if (!obj)
 752                                 return -EINVAL;
 753                 } else {
 754                         /* In case we create obj somewhere else */
 755                         get_obj(obj);
 756                 }
 757                 con->features |= BIT(head->block);
 758         } else {
 759                 if (obj && amdgpu_ras_is_feature_enabled(adev, head)) {
 760                         con->features &= ~BIT(head->block);
 761                         put_obj(obj);
 762                 }
 763         }
 764
 765         return 0;
 766 }
 767
 768 /* wrapper of psp_ras_enable_features */
 769 int amdgpu_ras_feature_enable(struct amdgpu_device *adev,
 770                 struct ras_common_if *head, bool enable)
 771 {
 772         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
 773         union ta_ras_cmd_input *info;
 774         int ret;
 775
 776         if (!con)
 777                 return -EINVAL;
 778
 779         /* For non-gfx ip, do not enable ras feature if it is not allowed */
 780         /* For gfx ip, regardless of feature support status, */
 781         /* Force issue enable or disable ras feature commands */
 782         if (head->block != AMDGPU_RAS_BLOCK__GFX &&
 783             !amdgpu_ras_is_feature_allowed(adev, head))
 784                 return 0;
 785
 786         /* Only enable gfx ras feature from host side */
 787         if (head->block == AMDGPU_RAS_BLOCK__GFX &&
 788             !amdgpu_sriov_vf(adev) &&
 789             !amdgpu_ras_intr_triggered()) {
 790                 info = kzalloc(sizeof(union ta_ras_cmd_input), GFP_KERNEL);
 791                 if (!info)
 792                         return -ENOMEM;
 793
 794                 if (!enable) {
 795                         info->disable_features = (struct ta_ras_disable_features_input) {
 796                                 .block_id =  amdgpu_ras_block_to_ta(head->block),
 797                                 .error_type = amdgpu_ras_error_to_ta(head->type),
 798                         };
 799                 } else {
 800                         info->enable_features = (struct ta_ras_enable_features_input) {
 801                                 .block_id =  amdgpu_ras_block_to_ta(head->block),
 802                                 .error_type = amdgpu_ras_error_to_ta(head->type),
 803                         };
 804                 }
 805
 806                 ret = psp_ras_enable_features(&adev->psp, info, enable);
 807                 if (ret) {
 808                         dev_err(adev->dev, "ras %s %s failed poison:%d ret:%d\n",
 809                                 enable ? "enable":"disable",
 810                                 get_ras_block_str(head),
 811                                 amdgpu_ras_is_poison_mode_supported(adev), ret);
 812                         kfree(info);
 813                         return ret;
 814                 }
 815
 816                 kfree(info);
 817         }
 818
 819         /* setup the obj */
 820         __amdgpu_ras_feature_enable(adev, head, enable);
 821
 822         return 0;
 823 }
 824
 825 /* Only used in device probe stage and called only once. */
 826 int amdgpu_ras_feature_enable_on_boot(struct amdgpu_device *adev,
 827                 struct ras_common_if *head, bool enable)
 828 {
 829         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
 830         int ret;
 831
 832         if (!con)
 833                 return -EINVAL;
 834
 835         if (con->flags & AMDGPU_RAS_FLAG_INIT_BY_VBIOS) {
 836                 if (enable) {
 837                         /* There is no harm to issue a ras TA cmd regardless of
 838                          * the currecnt ras state.
 839                          * If current state == target state, it will do nothing
 840                          * But sometimes it requests driver to reset and repost
 841                          * with error code -EAGAIN.
 842                          */
 843                         ret = amdgpu_ras_feature_enable(adev, head, 1);
 844                         /* With old ras TA, we might fail to enable ras.
 845                          * Log it and just setup the object.
 846                          * TODO need remove this WA in the future.
 847                          */
 848                         if (ret == -EINVAL) {
 849                                 ret = __amdgpu_ras_feature_enable(adev, head, 1);
 850                                 if (!ret)
 851                                         dev_info(adev->dev,
 852                                                 "RAS INFO: %s setup object\n",
 853                                                 get_ras_block_str(head));
 854                         }
 855                 } else {
 856                         /* setup the object then issue a ras TA disable cmd.*/
 857                         ret = __amdgpu_ras_feature_enable(adev, head, 1);
 858                         if (ret)
 859                                 return ret;
 860
 861                         /* gfx block ras dsiable cmd must send to ras-ta */
 862                         if (head->block == AMDGPU_RAS_BLOCK__GFX)
 863                                 con->features |= BIT(head->block);
 864
 865                         ret = amdgpu_ras_feature_enable(adev, head, 0);
 866
 867                         /* clean gfx block ras features flag */
 868                         if (adev->ras_enabled && head->block == AMDGPU_RAS_BLOCK__GFX)
 869                                 con->features &= ~BIT(head->block);
 870                 }
 871         } else
 872                 ret = amdgpu_ras_feature_enable(adev, head, enable);
 873
 874         return ret;
 875 }
 876
 877 static int amdgpu_ras_disable_all_features(struct amdgpu_device *adev,
 878                 bool bypass)
 879 {
 880         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
 881         struct ras_manager *obj, *tmp;
 882
 883         list_for_each_entry_safe(obj, tmp, &con->head, node) {
 884                 /* bypass psp.
 885                  * aka just release the obj and corresponding flags
 886                  */
 887                 if (bypass) {
 888                         if (__amdgpu_ras_feature_enable(adev, &obj->head, 0))
 889                                 break;
 890                 } else {
 891                         if (amdgpu_ras_feature_enable(adev, &obj->head, 0))
 892                                 break;
 893                 }
 894         }
 895
 896         return con->features;
 897 }
 898
 899 static int amdgpu_ras_enable_all_features(struct amdgpu_device *adev,
 900                 bool bypass)
 901 {
 902         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
 903         int i;
 904         const enum amdgpu_ras_error_type default_ras_type = AMDGPU_RAS_ERROR__NONE;
 905
 906         for (i = 0; i < AMDGPU_RAS_BLOCK_COUNT; i++) {
 907                 struct ras_common_if head = {
 908                         .block = i,
 909                         .type = default_ras_type,
 910                         .sub_block_index = 0,
 911                 };
 912
 913                 if (i == AMDGPU_RAS_BLOCK__MCA)
 914                         continue;
 915
 916                 if (bypass) {
 917                         /*
 918                          * bypass psp. vbios enable ras for us.
 919                          * so just create the obj
 920                          */
 921                         if (__amdgpu_ras_feature_enable(adev, &head, 1))
 922                                 break;
 923                 } else {
 924                         if (amdgpu_ras_feature_enable(adev, &head, 1))
 925                                 break;
 926                 }
 927         }
 928
 929         for (i = 0; i < AMDGPU_RAS_MCA_BLOCK_COUNT; i++) {
 930                 struct ras_common_if head = {
 931                         .block = AMDGPU_RAS_BLOCK__MCA,
 932                         .type = default_ras_type,
 933                         .sub_block_index = i,
 934                 };
 935
 936                 if (bypass) {
 937                         /*
 938                          * bypass psp. vbios enable ras for us.
 939                          * so just create the obj
 940                          */
 941                         if (__amdgpu_ras_feature_enable(adev, &head, 1))
 942                                 break;
 943                 } else {
 944                         if (amdgpu_ras_feature_enable(adev, &head, 1))
 945                                 break;
 946                 }
 947         }
 948
 949         return con->features;
 950 }
 951 /* feature ctl end */
 952
 953 static int amdgpu_ras_block_match_default(struct amdgpu_ras_block_object *block_obj,
 954                 enum amdgpu_ras_block block)
 955 {
 956         if (!block_obj)
 957                 return -EINVAL;
 958
 959         if (block_obj->ras_comm.block == block)
 960                 return 0;
 961
 962         return -EINVAL;
 963 }
 964
 965 static struct amdgpu_ras_block_object *amdgpu_ras_get_ras_block(struct amdgpu_device *adev,
 966                                         enum amdgpu_ras_block block, uint32_t sub_block_index)
 967 {
 968         struct amdgpu_ras_block_list *node, *tmp;
 969         struct amdgpu_ras_block_object *obj;
 970
 971         if (block >= AMDGPU_RAS_BLOCK__LAST)
 972                 return NULL;
 973
 974         list_for_each_entry_safe(node, tmp, &adev->ras_list, node) {
 975                 if (!node->ras_obj) {
 976                         dev_warn(adev->dev, "Warning: abnormal ras list node.\n");
 977                         continue;
 978                 }
 979
 980                 obj = node->ras_obj;
 981                 if (obj->ras_block_match) {
 982                         if (obj->ras_block_match(obj, block, sub_block_index) == 0)
 983                                 return obj;
 984                 } else {
 985                         if (amdgpu_ras_block_match_default(obj, block) == 0)
 986                                 return obj;
 987                 }
 988         }
 989
 990         return NULL;
 991 }
 992
 993 static void amdgpu_ras_get_ecc_info(struct amdgpu_device *adev, struct ras_err_data *err_data)
 994 {
 995         struct amdgpu_ras *ras = amdgpu_ras_get_context(adev);
 996         int ret = 0;
 997
 998         /*
 999          * choosing right query method according to
1000          * whether smu support query error information
1001          */
1002         ret = amdgpu_dpm_get_ecc_info(adev, (void *)&(ras->umc_ecc));
1003         if (ret == -EOPNOTSUPP) {
1004                 if (adev->umc.ras && adev->umc.ras->ras_block.hw_ops &&
1005                         adev->umc.ras->ras_block.hw_ops->query_ras_error_count)
1006                         adev->umc.ras->ras_block.hw_ops->query_ras_error_count(adev, err_data);
1007
1008                 /* umc query_ras_error_address is also responsible for clearing
1009                  * error status
1010                  */
1011                 if (adev->umc.ras && adev->umc.ras->ras_block.hw_ops &&
1012                     adev->umc.ras->ras_block.hw_ops->query_ras_error_address)
1013                         adev->umc.ras->ras_block.hw_ops->query_ras_error_address(adev, err_data);
1014         } else if (!ret) {
1015                 if (adev->umc.ras &&
1016                         adev->umc.ras->ecc_info_query_ras_error_count)
1017                         adev->umc.ras->ecc_info_query_ras_error_count(adev, err_data);
1018
1019                 if (adev->umc.ras &&
1020                         adev->umc.ras->ecc_info_query_ras_error_address)
1021                         adev->umc.ras->ecc_info_query_ras_error_address(adev, err_data);
1022         }
1023 }
1024
1025 static void amdgpu_ras_error_print_error_data(struct amdgpu_device *adev,
1026                                               struct ras_query_if *query_if,
1027                                               struct ras_err_data *err_data,
1028                                               bool is_ue)
1029 {
1030         struct ras_manager *ras_mgr = amdgpu_ras_find_obj(adev, &query_if->head);
1031         const char *blk_name = get_ras_block_str(&query_if->head);
1032         struct amdgpu_smuio_mcm_config_info *mcm_info;
1033         struct ras_err_node *err_node;
1034         struct ras_err_info *err_info;
1035
1036         if (is_ue)
1037                 dev_info(adev->dev, "%ld uncorrectable hardware errors detected in %s block\n",
1038                          ras_mgr->err_data.ue_count, blk_name);
1039         else
1040                 dev_info(adev->dev, "%ld correctable hardware errors detected in %s block\n",
1041                          ras_mgr->err_data.ce_count, blk_name);
1042
1043         for_each_ras_error(err_node, err_data) {
1044                 err_info = &err_node->err_info;
1045                 mcm_info = &err_info->mcm_info;
1046                 if (is_ue && err_info->ue_count) {
1047                         dev_info(adev->dev, "socket: %d, die: %d "
1048                                  "%lld uncorrectable hardware errors detected in %s block\n",
1049                                  mcm_info->socket_id,
1050                                  mcm_info->die_id,
1051                                  err_info->ue_count,
1052                                  blk_name);
1053                 } else if (!is_ue && err_info->ce_count) {
1054                         dev_info(adev->dev, "socket: %d, die: %d "
1055                                  "%lld correctable hardware errors detected in %s block\n",
1056                                  mcm_info->socket_id,
1057                                  mcm_info->die_id,
1058                                  err_info->ce_count,
1059                                  blk_name);
1060                 }
1061         }
1062 }
1063
1064 static void amdgpu_ras_error_generate_report(struct amdgpu_device *adev,
1065                                              struct ras_query_if *query_if,
1066                                              struct ras_err_data *err_data)
1067 {
1068         struct ras_manager *ras_mgr = amdgpu_ras_find_obj(adev, &query_if->head);
1069         const char *blk_name = get_ras_block_str(&query_if->head);
1070
1071         if (err_data->ce_count) {
1072                 if (!list_empty(&err_data->err_node_list)) {
1073                         amdgpu_ras_error_print_error_data(adev, query_if,
1074                                                           err_data, false);
1075                 } else if (!adev->aid_mask &&
1076                            adev->smuio.funcs &&
1077                            adev->smuio.funcs->get_socket_id &&
1078                            adev->smuio.funcs->get_die_id) {
1079                         dev_info(adev->dev, "socket: %d, die: %d "
1080                                  "%ld correctable hardware errors "
1081                                  "detected in %s block, no user "
1082                                  "action is needed.\n",
1083                                  adev->smuio.funcs->get_socket_id(adev),
1084                                  adev->smuio.funcs->get_die_id(adev),
1085                                  ras_mgr->err_data.ce_count,
1086                                  blk_name);
1087                 } else {
1088                         dev_info(adev->dev, "%ld correctable hardware errors "
1089                                  "detected in %s block, no user "
1090                                  "action is needed.\n",
1091                                  ras_mgr->err_data.ce_count,
1092                                  blk_name);
1093                 }
1094         }
1095
1096         if (err_data->ue_count) {
1097                 if (!list_empty(&err_data->err_node_list)) {
1098                         amdgpu_ras_error_print_error_data(adev, query_if,
1099                                                           err_data, true);
1100                 } else if (!adev->aid_mask &&
1101                            adev->smuio.funcs &&
1102                            adev->smuio.funcs->get_socket_id &&
1103                            adev->smuio.funcs->get_die_id) {
1104                         dev_info(adev->dev, "socket: %d, die: %d "
1105                                  "%ld uncorrectable hardware errors "
1106                                  "detected in %s block\n",
1107                                  adev->smuio.funcs->get_socket_id(adev),
1108                                  adev->smuio.funcs->get_die_id(adev),
1109                                  ras_mgr->err_data.ue_count,
1110                                  blk_name);
1111                 } else {
1112                         dev_info(adev->dev, "%ld uncorrectable hardware errors "
1113                                  "detected in %s block\n",
1114                                  ras_mgr->err_data.ue_count,
1115                                  blk_name);
1116                 }
1117         }
1118
1119 }
1120
1121 /* query/inject/cure begin */
1122 int amdgpu_ras_query_error_status(struct amdgpu_device *adev,
1123                                   struct ras_query_if *info)
1124 {
1125         struct amdgpu_ras_block_object *block_obj = NULL;
1126         struct ras_manager *obj = amdgpu_ras_find_obj(adev, &info->head);
1127         struct ras_err_data err_data;
1128         int ret;
1129
1130         if (!obj)
1131                 return -EINVAL;
1132
1133         ret = amdgpu_ras_error_data_init(&err_data);
1134         if (ret)
1135                 return ret;
1136
1137         if (info->head.block == AMDGPU_RAS_BLOCK__UMC) {
1138                 amdgpu_ras_get_ecc_info(adev, &err_data);
1139         } else {
1140                 block_obj = amdgpu_ras_get_ras_block(adev, info->head.block, 0);
1141                 if (!block_obj || !block_obj->hw_ops)   {
1142                         dev_dbg_once(adev->dev, "%s doesn't config RAS function\n",
1143                                      get_ras_block_str(&info->head));
1144                         ret = -EINVAL;
1145                         goto out_fini_err_data;
1146                 }
1147
1148                 if (block_obj->hw_ops->query_ras_error_count)
1149                         block_obj->hw_ops->query_ras_error_count(adev, &err_data);
1150
1151                 if ((info->head.block == AMDGPU_RAS_BLOCK__SDMA) ||
1152                     (info->head.block == AMDGPU_RAS_BLOCK__GFX) ||
1153                     (info->head.block == AMDGPU_RAS_BLOCK__MMHUB)) {
1154                                 if (block_obj->hw_ops->query_ras_error_status)
1155                                         block_obj->hw_ops->query_ras_error_status(adev);
1156                         }
1157         }
1158
1159         obj->err_data.ue_count += err_data.ue_count;
1160         obj->err_data.ce_count += err_data.ce_count;
1161
1162         info->ue_count = obj->err_data.ue_count;
1163         info->ce_count = obj->err_data.ce_count;
1164
1165         amdgpu_ras_error_generate_report(adev, info, &err_data);
1166
1167 out_fini_err_data:
1168         amdgpu_ras_error_data_fini(&err_data);
1169
1170         return ret;
1171 }
1172
1173 int amdgpu_ras_reset_error_count(struct amdgpu_device *adev,
1174                 enum amdgpu_ras_block block)
1175 {
1176         struct amdgpu_ras_block_object *block_obj = amdgpu_ras_get_ras_block(adev, block, 0);
1177
1178         if (!block_obj || !block_obj->hw_ops) {
1179                 dev_dbg_once(adev->dev, "%s doesn't config RAS function\n",
1180                                 ras_block_str(block));
1181                 return -EOPNOTSUPP;
1182         }
1183
1184         if (!amdgpu_ras_is_supported(adev, block))
1185                 return -EOPNOTSUPP;
1186
1187         if (block_obj->hw_ops->reset_ras_error_count)
1188                 block_obj->hw_ops->reset_ras_error_count(adev);
1189
1190         return 0;
1191 }
1192
1193 int amdgpu_ras_reset_error_status(struct amdgpu_device *adev,
1194                 enum amdgpu_ras_block block)
1195 {
1196         struct amdgpu_ras_block_object *block_obj = amdgpu_ras_get_ras_block(adev, block, 0);
1197
1198         if (amdgpu_ras_reset_error_count(adev, block) == -EOPNOTSUPP)
1199                 return 0;
1200
1201         if ((block == AMDGPU_RAS_BLOCK__GFX) ||
1202             (block == AMDGPU_RAS_BLOCK__MMHUB)) {
1203                 if (block_obj->hw_ops->reset_ras_error_status)
1204                         block_obj->hw_ops->reset_ras_error_status(adev);
1205         }
1206
1207         return 0;
1208 }
1209
1210 /* wrapper of psp_ras_trigger_error */
1211 int amdgpu_ras_error_inject(struct amdgpu_device *adev,
1212                 struct ras_inject_if *info)
1213 {
1214         struct ras_manager *obj = amdgpu_ras_find_obj(adev, &info->head);
1215         struct ta_ras_trigger_error_input block_info = {
1216                 .block_id =  amdgpu_ras_block_to_ta(info->head.block),
1217                 .inject_error_type = amdgpu_ras_error_to_ta(info->head.type),
1218                 .sub_block_index = info->head.sub_block_index,
1219                 .address = info->address,
1220                 .value = info->value,
1221         };
1222         int ret = -EINVAL;
1223         struct amdgpu_ras_block_object *block_obj = amdgpu_ras_get_ras_block(adev,
1224                                                         info->head.block,
1225                                                         info->head.sub_block_index);
1226
1227         /* inject on guest isn't allowed, return success directly */
1228         if (amdgpu_sriov_vf(adev))
1229                 return 0;
1230
1231         if (!obj)
1232                 return -EINVAL;
1233
1234         if (!block_obj || !block_obj->hw_ops)   {
1235                 dev_dbg_once(adev->dev, "%s doesn't config RAS function\n",
1236                              get_ras_block_str(&info->head));
1237                 return -EINVAL;
1238         }
1239
1240         /* Calculate XGMI relative offset */
1241         if (adev->gmc.xgmi.num_physical_nodes > 1 &&
1242             info->head.block != AMDGPU_RAS_BLOCK__GFX) {
1243                 block_info.address =
1244                         amdgpu_xgmi_get_relative_phy_addr(adev,
1245                                                           block_info.address);
1246         }
1247
1248         if (block_obj->hw_ops->ras_error_inject) {
1249                 if (info->head.block == AMDGPU_RAS_BLOCK__GFX)
1250                         ret = block_obj->hw_ops->ras_error_inject(adev, info, info->instance_mask);
1251                 else /* Special ras_error_inject is defined (e.g: xgmi) */
1252                         ret = block_obj->hw_ops->ras_error_inject(adev, &block_info,
1253                                                 info->instance_mask);
1254         } else {
1255                 /* default path */
1256                 ret = psp_ras_trigger_error(&adev->psp, &block_info, info->instance_mask);
1257         }
1258
1259         if (ret)
1260                 dev_err(adev->dev, "ras inject %s failed %d\n",
1261                         get_ras_block_str(&info->head), ret);
1262
1263         return ret;
1264 }
1265
1266 /**
1267  * amdgpu_ras_query_error_count_helper -- Get error counter for specific IP
1268  * @adev: pointer to AMD GPU device
1269  * @ce_count: pointer to an integer to be set to the count of correctible errors.
1270  * @ue_count: pointer to an integer to be set to the count of uncorrectible errors.
1271  * @query_info: pointer to ras_query_if
1272  *
1273  * Return 0 for query success or do nothing, otherwise return an error
1274  * on failures
1275  */
1276 static int amdgpu_ras_query_error_count_helper(struct amdgpu_device *adev,
1277                                                unsigned long *ce_count,
1278                                                unsigned long *ue_count,
1279                                                struct ras_query_if *query_info)
1280 {
1281         int ret;
1282
1283         if (!query_info)
1284                 /* do nothing if query_info is not specified */
1285                 return 0;
1286
1287         ret = amdgpu_ras_query_error_status(adev, query_info);
1288         if (ret)
1289                 return ret;
1290
1291         *ce_count += query_info->ce_count;
1292         *ue_count += query_info->ue_count;
1293
1294         /* some hardware/IP supports read to clear
1295          * no need to explictly reset the err status after the query call */
1296         if (amdgpu_ip_version(adev, MP0_HWIP, 0) != IP_VERSION(11, 0, 2) &&
1297             amdgpu_ip_version(adev, MP0_HWIP, 0) != IP_VERSION(11, 0, 4)) {
1298                 if (amdgpu_ras_reset_error_status(adev, query_info->head.block))
1299                         dev_warn(adev->dev,
1300                                  "Failed to reset error counter and error status\n");
1301         }
1302
1303         return 0;
1304 }
1305
1306 /**
1307  * amdgpu_ras_query_error_count -- Get error counts of all IPs or specific IP
1308  * @adev: pointer to AMD GPU device
1309  * @ce_count: pointer to an integer to be set to the count of correctible errors.
1310  * @ue_count: pointer to an integer to be set to the count of uncorrectible
1311  * errors.
1312  * @query_info: pointer to ras_query_if if the query request is only for
1313  * specific ip block; if info is NULL, then the qurey request is for
1314  * all the ip blocks that support query ras error counters/status
1315  *
1316  * If set, @ce_count or @ue_count, count and return the corresponding
1317  * error counts in those integer pointers. Return 0 if the device
1318  * supports RAS. Return -EOPNOTSUPP if the device doesn't support RAS.
1319  */
1320 int amdgpu_ras_query_error_count(struct amdgpu_device *adev,
1321                                  unsigned long *ce_count,
1322                                  unsigned long *ue_count,
1323                                  struct ras_query_if *query_info)
1324 {
1325         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1326         struct ras_manager *obj;
1327         unsigned long ce, ue;
1328         int ret;
1329
1330         if (!adev->ras_enabled || !con)
1331                 return -EOPNOTSUPP;
1332
1333         /* Don't count since no reporting.
1334          */
1335         if (!ce_count && !ue_count)
1336                 return 0;
1337
1338         ce = 0;
1339         ue = 0;
1340         if (!query_info) {
1341                 /* query all the ip blocks that support ras query interface */
1342                 list_for_each_entry(obj, &con->head, node) {
1343                         struct ras_query_if info = {
1344                                 .head = obj->head,
1345                         };
1346
1347                         ret = amdgpu_ras_query_error_count_helper(adev, &ce, &ue, &info);
1348                 }
1349         } else {
1350                 /* query specific ip block */
1351                 ret = amdgpu_ras_query_error_count_helper(adev, &ce, &ue, query_info);
1352         }
1353
1354         if (ret)
1355                 return ret;
1356
1357         if (ce_count)
1358                 *ce_count = ce;
1359
1360         if (ue_count)
1361                 *ue_count = ue;
1362
1363         return 0;
1364 }
1365 /* query/inject/cure end */
1366
1367
1368 /* sysfs begin */
1369
1370 static int amdgpu_ras_badpages_read(struct amdgpu_device *adev,
1371                 struct ras_badpage **bps, unsigned int *count);
1372
1373 static char *amdgpu_ras_badpage_flags_str(unsigned int flags)
1374 {
1375         switch (flags) {
1376         case AMDGPU_RAS_RETIRE_PAGE_RESERVED:
1377                 return "R";
1378         case AMDGPU_RAS_RETIRE_PAGE_PENDING:
1379                 return "P";
1380         case AMDGPU_RAS_RETIRE_PAGE_FAULT:
1381         default:
1382                 return "F";
1383         }
1384 }
1385
1386 /**
1387  * DOC: AMDGPU RAS sysfs gpu_vram_bad_pages Interface
1388  *
1389  * It allows user to read the bad pages of vram on the gpu through
1390  * /sys/class/drm/card[0/1/2...]/device/ras/gpu_vram_bad_pages
1391  *
1392  * It outputs multiple lines, and each line stands for one gpu page.
1393  *
1394  * The format of one line is below,
1395  * gpu pfn : gpu page size : flags
1396  *
1397  * gpu pfn and gpu page size are printed in hex format.
1398  * flags can be one of below character,
1399  *
1400  * R: reserved, this gpu page is reserved and not able to use.
1401  *
1402  * P: pending for reserve, this gpu page is marked as bad, will be reserved
1403  * in next window of page_reserve.
1404  *
1405  * F: unable to reserve. this gpu page can't be reserved due to some reasons.
1406  *
1407  * Examples:
1408  *
1409  * .. code-block:: bash
1410  *
1411  *      0x00000001 : 0x00001000 : R
1412  *      0x00000002 : 0x00001000 : P
1413  *
1414  */
1415
1416 static ssize_t amdgpu_ras_sysfs_badpages_read(struct file *f,
1417                 struct kobject *kobj, struct bin_attribute *attr,
1418                 char *buf, loff_t ppos, size_t count)
1419 {
1420         struct amdgpu_ras *con =
1421                 container_of(attr, struct amdgpu_ras, badpages_attr);
1422         struct amdgpu_device *adev = con->adev;
1423         const unsigned int element_size =
1424                 sizeof("0xabcdabcd : 0x12345678 : R\n") - 1;
1425         unsigned int start = div64_ul(ppos + element_size - 1, element_size);
1426         unsigned int end = div64_ul(ppos + count - 1, element_size);
1427         ssize_t s = 0;
1428         struct ras_badpage *bps = NULL;
1429         unsigned int bps_count = 0;
1430
1431         memset(buf, 0, count);
1432
1433         if (amdgpu_ras_badpages_read(adev, &bps, &bps_count))
1434                 return 0;
1435
1436         for (; start < end && start < bps_count; start++)
1437                 s += scnprintf(&buf[s], element_size + 1,
1438                                 "0x%08x : 0x%08x : %1s\n",
1439                                 bps[start].bp,
1440                                 bps[start].size,
1441                                 amdgpu_ras_badpage_flags_str(bps[start].flags));
1442
1443         kfree(bps);
1444
1445         return s;
1446 }
1447
1448 static ssize_t amdgpu_ras_sysfs_features_read(struct device *dev,
1449                 struct device_attribute *attr, char *buf)
1450 {
1451         struct amdgpu_ras *con =
1452                 container_of(attr, struct amdgpu_ras, features_attr);
1453
1454         return sysfs_emit(buf, "feature mask: 0x%x\n", con->features);
1455 }
1456
1457 static ssize_t amdgpu_ras_sysfs_version_show(struct device *dev,
1458                 struct device_attribute *attr, char *buf)
1459 {
1460         struct amdgpu_ras *con =
1461                 container_of(attr, struct amdgpu_ras, version_attr);
1462         return sysfs_emit(buf, "table version: 0x%x\n", con->eeprom_control.tbl_hdr.version);
1463 }
1464
1465 static ssize_t amdgpu_ras_sysfs_schema_show(struct device *dev,
1466                 struct device_attribute *attr, char *buf)
1467 {
1468         struct amdgpu_ras *con =
1469                 container_of(attr, struct amdgpu_ras, schema_attr);
1470         return sysfs_emit(buf, "schema: 0x%x\n", con->schema);
1471 }
1472
1473 static void amdgpu_ras_sysfs_remove_bad_page_node(struct amdgpu_device *adev)
1474 {
1475         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1476
1477         sysfs_remove_file_from_group(&adev->dev->kobj,
1478                                 &con->badpages_attr.attr,
1479                                 RAS_FS_NAME);
1480 }
1481
1482 static int amdgpu_ras_sysfs_remove_dev_attr_node(struct amdgpu_device *adev)
1483 {
1484         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1485         struct attribute *attrs[] = {
1486                 &con->features_attr.attr,
1487                 &con->version_attr.attr,
1488                 &con->schema_attr.attr,
1489                 NULL
1490         };
1491         struct attribute_group group = {
1492                 .name = RAS_FS_NAME,
1493                 .attrs = attrs,
1494         };
1495
1496         sysfs_remove_group(&adev->dev->kobj, &group);
1497
1498         return 0;
1499 }
1500
1501 int amdgpu_ras_sysfs_create(struct amdgpu_device *adev,
1502                 struct ras_common_if *head)
1503 {
1504         struct ras_manager *obj = amdgpu_ras_find_obj(adev, head);
1505
1506         if (!obj || obj->attr_inuse)
1507                 return -EINVAL;
1508
1509         get_obj(obj);
1510
1511         snprintf(obj->fs_data.sysfs_name, sizeof(obj->fs_data.sysfs_name),
1512                 "%s_err_count", head->name);
1513
1514         obj->sysfs_attr = (struct device_attribute){
1515                 .attr = {
1516                         .name = obj->fs_data.sysfs_name,
1517                         .mode = S_IRUGO,
1518                 },
1519                         .show = amdgpu_ras_sysfs_read,
1520         };
1521         sysfs_attr_init(&obj->sysfs_attr.attr);
1522
1523         if (sysfs_add_file_to_group(&adev->dev->kobj,
1524                                 &obj->sysfs_attr.attr,
1525                                 RAS_FS_NAME)) {
1526                 put_obj(obj);
1527                 return -EINVAL;
1528         }
1529
1530         obj->attr_inuse = 1;
1531
1532         return 0;
1533 }
1534
1535 int amdgpu_ras_sysfs_remove(struct amdgpu_device *adev,
1536                 struct ras_common_if *head)
1537 {
1538         struct ras_manager *obj = amdgpu_ras_find_obj(adev, head);
1539
1540         if (!obj || !obj->attr_inuse)
1541                 return -EINVAL;
1542
1543         sysfs_remove_file_from_group(&adev->dev->kobj,
1544                                 &obj->sysfs_attr.attr,
1545                                 RAS_FS_NAME);
1546         obj->attr_inuse = 0;
1547         put_obj(obj);
1548
1549         return 0;
1550 }
1551
1552 static int amdgpu_ras_sysfs_remove_all(struct amdgpu_device *adev)
1553 {
1554         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1555         struct ras_manager *obj, *tmp;
1556
1557         list_for_each_entry_safe(obj, tmp, &con->head, node) {
1558                 amdgpu_ras_sysfs_remove(adev, &obj->head);
1559         }
1560
1561         if (amdgpu_bad_page_threshold != 0)
1562                 amdgpu_ras_sysfs_remove_bad_page_node(adev);
1563
1564         amdgpu_ras_sysfs_remove_dev_attr_node(adev);
1565
1566         return 0;
1567 }
1568 /* sysfs end */
1569
1570 /**
1571  * DOC: AMDGPU RAS Reboot Behavior for Unrecoverable Errors
1572  *
1573  * Normally when there is an uncorrectable error, the driver will reset
1574  * the GPU to recover.  However, in the event of an unrecoverable error,
1575  * the driver provides an interface to reboot the system automatically
1576  * in that event.
1577  *
1578  * The following file in debugfs provides that interface:
1579  * /sys/kernel/debug/dri/[0/1/2...]/ras/auto_reboot
1580  *
1581  * Usage:
1582  *
1583  * .. code-block:: bash
1584  *
1585  *      echo true > .../ras/auto_reboot
1586  *
1587  */
1588 /* debugfs begin */
1589 static struct dentry *amdgpu_ras_debugfs_create_ctrl_node(struct amdgpu_device *adev)
1590 {
1591         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1592         struct amdgpu_ras_eeprom_control *eeprom = &con->eeprom_control;
1593         struct drm_minor  *minor = adev_to_drm(adev)->primary;
1594         struct dentry     *dir;
1595
1596         dir = debugfs_create_dir(RAS_FS_NAME, minor->debugfs_root);
1597         debugfs_create_file("ras_ctrl", S_IWUGO | S_IRUGO, dir, adev,
1598                             &amdgpu_ras_debugfs_ctrl_ops);
1599         debugfs_create_file("ras_eeprom_reset", S_IWUGO | S_IRUGO, dir, adev,
1600                             &amdgpu_ras_debugfs_eeprom_ops);
1601         debugfs_create_u32("bad_page_cnt_threshold", 0444, dir,
1602                            &con->bad_page_cnt_threshold);
1603         debugfs_create_u32("ras_num_recs", 0444, dir, &eeprom->ras_num_recs);
1604         debugfs_create_x32("ras_hw_enabled", 0444, dir, &adev->ras_hw_enabled);
1605         debugfs_create_x32("ras_enabled", 0444, dir, &adev->ras_enabled);
1606         debugfs_create_file("ras_eeprom_size", S_IRUGO, dir, adev,
1607                             &amdgpu_ras_debugfs_eeprom_size_ops);
1608         con->de_ras_eeprom_table = debugfs_create_file("ras_eeprom_table",
1609                                                        S_IRUGO, dir, adev,
1610                                                        &amdgpu_ras_debugfs_eeprom_table_ops);
1611         amdgpu_ras_debugfs_set_ret_size(&con->eeprom_control);
1612
1613         /*
1614          * After one uncorrectable error happens, usually GPU recovery will
1615          * be scheduled. But due to the known problem in GPU recovery failing
1616          * to bring GPU back, below interface provides one direct way to
1617          * user to reboot system automatically in such case within
1618          * ERREVENT_ATHUB_INTERRUPT generated. Normal GPU recovery routine
1619          * will never be called.
1620          */
1621         debugfs_create_bool("auto_reboot", S_IWUGO | S_IRUGO, dir, &con->reboot);
1622
1623         /*
1624          * User could set this not to clean up hardware's error count register
1625          * of RAS IPs during ras recovery.
1626          */
1627         debugfs_create_bool("disable_ras_err_cnt_harvest", 0644, dir,
1628                             &con->disable_ras_err_cnt_harvest);
1629         return dir;
1630 }
1631
1632 static void amdgpu_ras_debugfs_create(struct amdgpu_device *adev,
1633                                       struct ras_fs_if *head,
1634                                       struct dentry *dir)
1635 {
1636         struct ras_manager *obj = amdgpu_ras_find_obj(adev, &head->head);
1637
1638         if (!obj || !dir)
1639                 return;
1640
1641         get_obj(obj);
1642
1643         memcpy(obj->fs_data.debugfs_name,
1644                         head->debugfs_name,
1645                         sizeof(obj->fs_data.debugfs_name));
1646
1647         debugfs_create_file(obj->fs_data.debugfs_name, S_IWUGO | S_IRUGO, dir,
1648                             obj, &amdgpu_ras_debugfs_ops);
1649 }
1650
1651 void amdgpu_ras_debugfs_create_all(struct amdgpu_device *adev)
1652 {
1653         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1654         struct dentry *dir;
1655         struct ras_manager *obj;
1656         struct ras_fs_if fs_info;
1657
1658         /*
1659          * it won't be called in resume path, no need to check
1660          * suspend and gpu reset status
1661          */
1662         if (!IS_ENABLED(CONFIG_DEBUG_FS) || !con)
1663                 return;
1664
1665         dir = amdgpu_ras_debugfs_create_ctrl_node(adev);
1666
1667         list_for_each_entry(obj, &con->head, node) {
1668                 if (amdgpu_ras_is_supported(adev, obj->head.block) &&
1669                         (obj->attr_inuse == 1)) {
1670                         sprintf(fs_info.debugfs_name, "%s_err_inject",
1671                                         get_ras_block_str(&obj->head));
1672                         fs_info.head = obj->head;
1673                         amdgpu_ras_debugfs_create(adev, &fs_info, dir);
1674                 }
1675         }
1676
1677         amdgpu_mca_smu_debugfs_init(adev, dir);
1678 }
1679
1680 /* debugfs end */
1681
1682 /* ras fs */
1683 static BIN_ATTR(gpu_vram_bad_pages, S_IRUGO,
1684                 amdgpu_ras_sysfs_badpages_read, NULL, 0);
1685 static DEVICE_ATTR(features, S_IRUGO,
1686                 amdgpu_ras_sysfs_features_read, NULL);
1687 static DEVICE_ATTR(version, 0444,
1688                 amdgpu_ras_sysfs_version_show, NULL);
1689 static DEVICE_ATTR(schema, 0444,
1690                 amdgpu_ras_sysfs_schema_show, NULL);
1691 static int amdgpu_ras_fs_init(struct amdgpu_device *adev)
1692 {
1693         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1694         struct attribute_group group = {
1695                 .name = RAS_FS_NAME,
1696         };
1697         struct attribute *attrs[] = {
1698                 &con->features_attr.attr,
1699                 &con->version_attr.attr,
1700                 &con->schema_attr.attr,
1701                 NULL
1702         };
1703         struct bin_attribute *bin_attrs[] = {
1704                 NULL,
1705                 NULL,
1706         };
1707         int r;
1708
1709         group.attrs = attrs;
1710
1711         /* add features entry */
1712         con->features_attr = dev_attr_features;
1713         sysfs_attr_init(attrs[0]);
1714
1715         /* add version entry */
1716         con->version_attr = dev_attr_version;
1717         sysfs_attr_init(attrs[1]);
1718
1719         /* add schema entry */
1720         con->schema_attr = dev_attr_schema;
1721         sysfs_attr_init(attrs[2]);
1722
1723         if (amdgpu_bad_page_threshold != 0) {
1724                 /* add bad_page_features entry */
1725                 bin_attr_gpu_vram_bad_pages.private = NULL;
1726                 con->badpages_attr = bin_attr_gpu_vram_bad_pages;
1727                 bin_attrs[0] = &con->badpages_attr;
1728                 group.bin_attrs = bin_attrs;
1729                 sysfs_bin_attr_init(bin_attrs[0]);
1730         }
1731
1732         r = sysfs_create_group(&adev->dev->kobj, &group);
1733         if (r)
1734                 dev_err(adev->dev, "Failed to create RAS sysfs group!");
1735
1736         return 0;
1737 }
1738
1739 static int amdgpu_ras_fs_fini(struct amdgpu_device *adev)
1740 {
1741         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1742         struct ras_manager *con_obj, *ip_obj, *tmp;
1743
1744         if (IS_ENABLED(CONFIG_DEBUG_FS)) {
1745                 list_for_each_entry_safe(con_obj, tmp, &con->head, node) {
1746                         ip_obj = amdgpu_ras_find_obj(adev, &con_obj->head);
1747                         if (ip_obj)
1748                                 put_obj(ip_obj);
1749                 }
1750         }
1751
1752         amdgpu_ras_sysfs_remove_all(adev);
1753         return 0;
1754 }
1755 /* ras fs end */
1756
1757 /* ih begin */
1758
1759 /* For the hardware that cannot enable bif ring for both ras_controller_irq
1760  * and ras_err_evnet_athub_irq ih cookies, the driver has to poll status
1761  * register to check whether the interrupt is triggered or not, and properly
1762  * ack the interrupt if it is there
1763  */
1764 void amdgpu_ras_interrupt_fatal_error_handler(struct amdgpu_device *adev)
1765 {
1766         /* Fatal error events are handled on host side */
1767         if (amdgpu_sriov_vf(adev))
1768                 return;
1769
1770         if (adev->nbio.ras &&
1771             adev->nbio.ras->handle_ras_controller_intr_no_bifring)
1772                 adev->nbio.ras->handle_ras_controller_intr_no_bifring(adev);
1773
1774         if (adev->nbio.ras &&
1775             adev->nbio.ras->handle_ras_err_event_athub_intr_no_bifring)
1776                 adev->nbio.ras->handle_ras_err_event_athub_intr_no_bifring(adev);
1777 }
1778
1779 static void amdgpu_ras_interrupt_poison_consumption_handler(struct ras_manager *obj,
1780                                 struct amdgpu_iv_entry *entry)
1781 {
1782         bool poison_stat = false;
1783         struct amdgpu_device *adev = obj->adev;
1784         struct amdgpu_ras_block_object *block_obj =
1785                 amdgpu_ras_get_ras_block(adev, obj->head.block, 0);
1786
1787         if (!block_obj)
1788                 return;
1789
1790         /* both query_poison_status and handle_poison_consumption are optional,
1791          * but at least one of them should be implemented if we need poison
1792          * consumption handler
1793          */
1794         if (block_obj->hw_ops && block_obj->hw_ops->query_poison_status) {
1795                 poison_stat = block_obj->hw_ops->query_poison_status(adev);
1796                 if (!poison_stat) {
1797                         /* Not poison consumption interrupt, no need to handle it */
1798                         dev_info(adev->dev, "No RAS poison status in %s poison IH.\n",
1799                                         block_obj->ras_comm.name);
1800
1801                         return;
1802                 }
1803         }
1804
1805         amdgpu_umc_poison_handler(adev, false);
1806
1807         if (block_obj->hw_ops && block_obj->hw_ops->handle_poison_consumption)
1808                 poison_stat = block_obj->hw_ops->handle_poison_consumption(adev);
1809
1810         /* gpu reset is fallback for failed and default cases */
1811         if (poison_stat) {
1812                 dev_info(adev->dev, "GPU reset for %s RAS poison consumption is issued!\n",
1813                                 block_obj->ras_comm.name);
1814                 amdgpu_ras_reset_gpu(adev);
1815         } else {
1816                 amdgpu_gfx_poison_consumption_handler(adev, entry);
1817         }
1818 }
1819
1820 static void amdgpu_ras_interrupt_poison_creation_handler(struct ras_manager *obj,
1821                                 struct amdgpu_iv_entry *entry)
1822 {
1823         dev_info(obj->adev->dev,
1824                 "Poison is created, no user action is needed.\n");
1825 }
1826
1827 static void amdgpu_ras_interrupt_umc_handler(struct ras_manager *obj,
1828                                 struct amdgpu_iv_entry *entry)
1829 {
1830         struct ras_ih_data *data = &obj->ih_data;
1831         struct ras_err_data err_data;
1832         int ret;
1833
1834         if (!data->cb)
1835                 return;
1836
1837         ret = amdgpu_ras_error_data_init(&err_data);
1838         if (ret)
1839                 return;
1840
1841         /* Let IP handle its data, maybe we need get the output
1842          * from the callback to update the error type/count, etc
1843          */
1844         ret = data->cb(obj->adev, &err_data, entry);
1845         /* ue will trigger an interrupt, and in that case
1846          * we need do a reset to recovery the whole system.
1847          * But leave IP do that recovery, here we just dispatch
1848          * the error.
1849          */
1850         if (ret == AMDGPU_RAS_SUCCESS) {
1851                 /* these counts could be left as 0 if
1852                  * some blocks do not count error number
1853                  */
1854                 obj->err_data.ue_count += err_data.ue_count;
1855                 obj->err_data.ce_count += err_data.ce_count;
1856         }
1857
1858         amdgpu_ras_error_data_fini(&err_data);
1859 }
1860
1861 static void amdgpu_ras_interrupt_handler(struct ras_manager *obj)
1862 {
1863         struct ras_ih_data *data = &obj->ih_data;
1864         struct amdgpu_iv_entry entry;
1865
1866         while (data->rptr != data->wptr) {
1867                 rmb();
1868                 memcpy(&entry, &data->ring[data->rptr],
1869                                 data->element_size);
1870
1871                 wmb();
1872                 data->rptr = (data->aligned_element_size +
1873                                 data->rptr) % data->ring_size;
1874
1875                 if (amdgpu_ras_is_poison_mode_supported(obj->adev)) {
1876                         if (obj->head.block == AMDGPU_RAS_BLOCK__UMC)
1877                                 amdgpu_ras_interrupt_poison_creation_handler(obj, &entry);
1878                         else
1879                                 amdgpu_ras_interrupt_poison_consumption_handler(obj, &entry);
1880                 } else {
1881                         if (obj->head.block == AMDGPU_RAS_BLOCK__UMC)
1882                                 amdgpu_ras_interrupt_umc_handler(obj, &entry);
1883                         else
1884                                 dev_warn(obj->adev->dev,
1885                                         "No RAS interrupt handler for non-UMC block with poison disabled.\n");
1886                 }
1887         }
1888 }
1889
1890 static void amdgpu_ras_interrupt_process_handler(struct work_struct *work)
1891 {
1892         struct ras_ih_data *data =
1893                 container_of(work, struct ras_ih_data, ih_work);
1894         struct ras_manager *obj =
1895                 container_of(data, struct ras_manager, ih_data);
1896
1897         amdgpu_ras_interrupt_handler(obj);
1898 }
1899
1900 int amdgpu_ras_interrupt_dispatch(struct amdgpu_device *adev,
1901                 struct ras_dispatch_if *info)
1902 {
1903         struct ras_manager *obj = amdgpu_ras_find_obj(adev, &info->head);
1904         struct ras_ih_data *data = &obj->ih_data;
1905
1906         if (!obj)
1907                 return -EINVAL;
1908
1909         if (data->inuse == 0)
1910                 return 0;
1911
1912         /* Might be overflow... */
1913         memcpy(&data->ring[data->wptr], info->entry,
1914                         data->element_size);
1915
1916         wmb();
1917         data->wptr = (data->aligned_element_size +
1918                         data->wptr) % data->ring_size;
1919
1920         schedule_work(&data->ih_work);
1921
1922         return 0;
1923 }
1924
1925 int amdgpu_ras_interrupt_remove_handler(struct amdgpu_device *adev,
1926                 struct ras_common_if *head)
1927 {
1928         struct ras_manager *obj = amdgpu_ras_find_obj(adev, head);
1929         struct ras_ih_data *data;
1930
1931         if (!obj)
1932                 return -EINVAL;
1933
1934         data = &obj->ih_data;
1935         if (data->inuse == 0)
1936                 return 0;
1937
1938         cancel_work_sync(&data->ih_work);
1939
1940         kfree(data->ring);
1941         memset(data, 0, sizeof(*data));
1942         put_obj(obj);
1943
1944         return 0;
1945 }
1946
1947 int amdgpu_ras_interrupt_add_handler(struct amdgpu_device *adev,
1948                 struct ras_common_if *head)
1949 {
1950         struct ras_manager *obj = amdgpu_ras_find_obj(adev, head);
1951         struct ras_ih_data *data;
1952         struct amdgpu_ras_block_object *ras_obj;
1953
1954         if (!obj) {
1955                 /* in case we registe the IH before enable ras feature */
1956                 obj = amdgpu_ras_create_obj(adev, head);
1957                 if (!obj)
1958                         return -EINVAL;
1959         } else
1960                 get_obj(obj);
1961
1962         ras_obj = container_of(head, struct amdgpu_ras_block_object, ras_comm);
1963
1964         data = &obj->ih_data;
1965         /* add the callback.etc */
1966         *data = (struct ras_ih_data) {
1967                 .inuse = 0,
1968                 .cb = ras_obj->ras_cb,
1969                 .element_size = sizeof(struct amdgpu_iv_entry),
1970                 .rptr = 0,
1971                 .wptr = 0,
1972         };
1973
1974         INIT_WORK(&data->ih_work, amdgpu_ras_interrupt_process_handler);
1975
1976         data->aligned_element_size = ALIGN(data->element_size, 8);
1977         /* the ring can store 64 iv entries. */
1978         data->ring_size = 64 * data->aligned_element_size;
1979         data->ring = kmalloc(data->ring_size, GFP_KERNEL);
1980         if (!data->ring) {
1981                 put_obj(obj);
1982                 return -ENOMEM;
1983         }
1984
1985         /* IH is ready */
1986         data->inuse = 1;
1987
1988         return 0;
1989 }
1990
1991 static int amdgpu_ras_interrupt_remove_all(struct amdgpu_device *adev)
1992 {
1993         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1994         struct ras_manager *obj, *tmp;
1995
1996         list_for_each_entry_safe(obj, tmp, &con->head, node) {
1997                 amdgpu_ras_interrupt_remove_handler(adev, &obj->head);
1998         }
1999
2000         return 0;
2001 }
2002 /* ih end */
2003
2004 /* traversal all IPs except NBIO to query error counter */
2005 static void amdgpu_ras_log_on_err_counter(struct amdgpu_device *adev)
2006 {
2007         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
2008         struct ras_manager *obj;
2009
2010         if (!adev->ras_enabled || !con)
2011                 return;
2012
2013         list_for_each_entry(obj, &con->head, node) {
2014                 struct ras_query_if info = {
2015                         .head = obj->head,
2016                 };
2017
2018                 /*
2019                  * PCIE_BIF IP has one different isr by ras controller
2020                  * interrupt, the specific ras counter query will be
2021                  * done in that isr. So skip such block from common
2022                  * sync flood interrupt isr calling.
2023                  */
2024                 if (info.head.block == AMDGPU_RAS_BLOCK__PCIE_BIF)
2025                         continue;
2026
2027                 /*
2028                  * this is a workaround for aldebaran, skip send msg to
2029                  * smu to get ecc_info table due to smu handle get ecc
2030                  * info table failed temporarily.
2031                  * should be removed until smu fix handle ecc_info table.
2032                  */
2033                 if ((info.head.block == AMDGPU_RAS_BLOCK__UMC) &&
2034                     (amdgpu_ip_version(adev, MP1_HWIP, 0) ==
2035                      IP_VERSION(13, 0, 2)))
2036                         continue;
2037
2038                 amdgpu_ras_query_error_status(adev, &info);
2039
2040                 if (amdgpu_ip_version(adev, MP0_HWIP, 0) !=
2041                             IP_VERSION(11, 0, 2) &&
2042                     amdgpu_ip_version(adev, MP0_HWIP, 0) !=
2043                             IP_VERSION(11, 0, 4) &&
2044                     amdgpu_ip_version(adev, MP0_HWIP, 0) !=
2045                             IP_VERSION(13, 0, 0)) {
2046                         if (amdgpu_ras_reset_error_status(adev, info.head.block))
2047                                 dev_warn(adev->dev, "Failed to reset error counter and error status");
2048                 }
2049         }
2050 }
2051
2052 /* Parse RdRspStatus and WrRspStatus */
2053 static void amdgpu_ras_error_status_query(struct amdgpu_device *adev,
2054                                           struct ras_query_if *info)
2055 {
2056         struct amdgpu_ras_block_object *block_obj;
2057         /*
2058          * Only two block need to query read/write
2059          * RspStatus at current state
2060          */
2061         if ((info->head.block != AMDGPU_RAS_BLOCK__GFX) &&
2062                 (info->head.block != AMDGPU_RAS_BLOCK__MMHUB))
2063                 return;
2064
2065         block_obj = amdgpu_ras_get_ras_block(adev,
2066                                         info->head.block,
2067                                         info->head.sub_block_index);
2068
2069         if (!block_obj || !block_obj->hw_ops) {
2070                 dev_dbg_once(adev->dev, "%s doesn't config RAS function\n",
2071                              get_ras_block_str(&info->head));
2072                 return;
2073         }
2074
2075         if (block_obj->hw_ops->query_ras_error_status)
2076                 block_obj->hw_ops->query_ras_error_status(adev);
2077
2078 }
2079
2080 static void amdgpu_ras_query_err_status(struct amdgpu_device *adev)
2081 {
2082         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
2083         struct ras_manager *obj;
2084
2085         if (!adev->ras_enabled || !con)
2086                 return;
2087
2088         list_for_each_entry(obj, &con->head, node) {
2089                 struct ras_query_if info = {
2090                         .head = obj->head,
2091                 };
2092
2093                 amdgpu_ras_error_status_query(adev, &info);
2094         }
2095 }
2096
2097 /* recovery begin */
2098
2099 /* return 0 on success.
2100  * caller need free bps.
2101  */
2102 static int amdgpu_ras_badpages_read(struct amdgpu_device *adev,
2103                 struct ras_badpage **bps, unsigned int *count)
2104 {
2105         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
2106         struct ras_err_handler_data *data;
2107         int i = 0;
2108         int ret = 0, status;
2109
2110         if (!con || !con->eh_data || !bps || !count)
2111                 return -EINVAL;
2112
2113         mutex_lock(&con->recovery_lock);
2114         data = con->eh_data;
2115         if (!data || data->count == 0) {
2116                 *bps = NULL;
2117                 ret = -EINVAL;
2118                 goto out;
2119         }
2120
2121         *bps = kmalloc(sizeof(struct ras_badpage) * data->count, GFP_KERNEL);
2122         if (!*bps) {
2123                 ret = -ENOMEM;
2124                 goto out;
2125         }
2126
2127         for (; i < data->count; i++) {
2128                 (*bps)[i] = (struct ras_badpage){
2129                         .bp = data->bps[i].retired_page,
2130                         .size = AMDGPU_GPU_PAGE_SIZE,
2131                         .flags = AMDGPU_RAS_RETIRE_PAGE_RESERVED,
2132                 };
2133                 status = amdgpu_vram_mgr_query_page_status(&adev->mman.vram_mgr,
2134                                 data->bps[i].retired_page);
2135                 if (status == -EBUSY)
2136                         (*bps)[i].flags = AMDGPU_RAS_RETIRE_PAGE_PENDING;
2137                 else if (status == -ENOENT)
2138                         (*bps)[i].flags = AMDGPU_RAS_RETIRE_PAGE_FAULT;
2139         }
2140
2141         *count = data->count;
2142 out:
2143         mutex_unlock(&con->recovery_lock);
2144         return ret;
2145 }
2146
2147 static void amdgpu_ras_do_recovery(struct work_struct *work)
2148 {
2149         struct amdgpu_ras *ras =
2150                 container_of(work, struct amdgpu_ras, recovery_work);
2151         struct amdgpu_device *remote_adev = NULL;
2152         struct amdgpu_device *adev = ras->adev;
2153         struct list_head device_list, *device_list_handle =  NULL;
2154         struct amdgpu_hive_info *hive = amdgpu_get_xgmi_hive(adev);
2155
2156         if (hive)
2157                 atomic_set(&hive->ras_recovery, 1);
2158         if (!ras->disable_ras_err_cnt_harvest) {
2159
2160                 /* Build list of devices to query RAS related errors */
2161                 if  (hive && adev->gmc.xgmi.num_physical_nodes > 1) {
2162                         device_list_handle = &hive->device_list;
2163                 } else {
2164                         INIT_LIST_HEAD(&device_list);
2165                         list_add_tail(&adev->gmc.xgmi.head, &device_list);
2166                         device_list_handle = &device_list;
2167                 }
2168
2169                 list_for_each_entry(remote_adev,
2170                                 device_list_handle, gmc.xgmi.head) {
2171                         amdgpu_ras_query_err_status(remote_adev);
2172                         amdgpu_ras_log_on_err_counter(remote_adev);
2173                 }
2174
2175         }
2176
2177         if (amdgpu_device_should_recover_gpu(ras->adev)) {
2178                 struct amdgpu_reset_context reset_context;
2179                 memset(&reset_context, 0, sizeof(reset_context));
2180
2181                 reset_context.method = AMD_RESET_METHOD_NONE;
2182                 reset_context.reset_req_dev = adev;
2183
2184                 /* Perform full reset in fatal error mode */
2185                 if (!amdgpu_ras_is_poison_mode_supported(ras->adev))
2186                         set_bit(AMDGPU_NEED_FULL_RESET, &reset_context.flags);
2187                 else {
2188                         clear_bit(AMDGPU_NEED_FULL_RESET, &reset_context.flags);
2189
2190                         if (ras->gpu_reset_flags & AMDGPU_RAS_GPU_RESET_MODE2_RESET) {
2191                                 ras->gpu_reset_flags &= ~AMDGPU_RAS_GPU_RESET_MODE2_RESET;
2192                                 reset_context.method = AMD_RESET_METHOD_MODE2;
2193                         }
2194
2195                         /* Fatal error occurs in poison mode, mode1 reset is used to
2196                          * recover gpu.
2197                          */
2198                         if (ras->gpu_reset_flags & AMDGPU_RAS_GPU_RESET_MODE1_RESET) {
2199                                 ras->gpu_reset_flags &= ~AMDGPU_RAS_GPU_RESET_MODE1_RESET;
2200                                 set_bit(AMDGPU_NEED_FULL_RESET, &reset_context.flags);
2201
2202                                 psp_fatal_error_recovery_quirk(&adev->psp);
2203                         }
2204                 }
2205
2206                 amdgpu_device_gpu_recover(ras->adev, NULL, &reset_context);
2207         }
2208         atomic_set(&ras->in_recovery, 0);
2209         if (hive) {
2210                 atomic_set(&hive->ras_recovery, 0);
2211                 amdgpu_put_xgmi_hive(hive);
2212         }
2213 }
2214
2215 /* alloc/realloc bps array */
2216 static int amdgpu_ras_realloc_eh_data_space(struct amdgpu_device *adev,
2217                 struct ras_err_handler_data *data, int pages)
2218 {
2219         unsigned int old_space = data->count + data->space_left;
2220         unsigned int new_space = old_space + pages;
2221         unsigned int align_space = ALIGN(new_space, 512);
2222         void *bps = kmalloc(align_space * sizeof(*data->bps), GFP_KERNEL);
2223
2224         if (!bps) {
2225                 return -ENOMEM;
2226         }
2227
2228         if (data->bps) {
2229                 memcpy(bps, data->bps,
2230                                 data->count * sizeof(*data->bps));
2231                 kfree(data->bps);
2232         }
2233
2234         data->bps = bps;
2235         data->space_left += align_space - old_space;
2236         return 0;
2237 }
2238
2239 /* it deal with vram only. */
2240 int amdgpu_ras_add_bad_pages(struct amdgpu_device *adev,
2241                 struct eeprom_table_record *bps, int pages)
2242 {
2243         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
2244         struct ras_err_handler_data *data;
2245         int ret = 0;
2246         uint32_t i;
2247
2248         if (!con || !con->eh_data || !bps || pages <= 0)
2249                 return 0;
2250
2251         mutex_lock(&con->recovery_lock);
2252         data = con->eh_data;
2253         if (!data)
2254                 goto out;
2255
2256         for (i = 0; i < pages; i++) {
2257                 if (amdgpu_ras_check_bad_page_unlock(con,
2258                         bps[i].retired_page << AMDGPU_GPU_PAGE_SHIFT))
2259                         continue;
2260
2261                 if (!data->space_left &&
2262                         amdgpu_ras_realloc_eh_data_space(adev, data, 256)) {
2263                         ret = -ENOMEM;
2264                         goto out;
2265                 }
2266
2267                 amdgpu_vram_mgr_reserve_range(&adev->mman.vram_mgr,
2268                         bps[i].retired_page << AMDGPU_GPU_PAGE_SHIFT,
2269                         AMDGPU_GPU_PAGE_SIZE);
2270
2271                 memcpy(&data->bps[data->count], &bps[i], sizeof(*data->bps));
2272                 data->count++;
2273                 data->space_left--;
2274         }
2275 out:
2276         mutex_unlock(&con->recovery_lock);
2277
2278         return ret;
2279 }
2280
2281 /*
2282  * write error record array to eeprom, the function should be
2283  * protected by recovery_lock
2284  * new_cnt: new added UE count, excluding reserved bad pages, can be NULL
2285  */
2286 int amdgpu_ras_save_bad_pages(struct amdgpu_device *adev,
2287                 unsigned long *new_cnt)
2288 {
2289         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
2290         struct ras_err_handler_data *data;
2291         struct amdgpu_ras_eeprom_control *control;
2292         int save_count;
2293
2294         if (!con || !con->eh_data) {
2295                 if (new_cnt)
2296                         *new_cnt = 0;
2297
2298                 return 0;
2299         }
2300
2301         mutex_lock(&con->recovery_lock);
2302         control = &con->eeprom_control;
2303         data = con->eh_data;
2304         save_count = data->count - control->ras_num_recs;
2305         mutex_unlock(&con->recovery_lock);
2306
2307         if (new_cnt)
2308                 *new_cnt = save_count / adev->umc.retire_unit;
2309
2310         /* only new entries are saved */
2311         if (save_count > 0) {
2312                 if (amdgpu_ras_eeprom_append(control,
2313                                              &data->bps[control->ras_num_recs],
2314                                              save_count)) {
2315                         dev_err(adev->dev, "Failed to save EEPROM table data!");
2316                         return -EIO;
2317                 }
2318
2319                 dev_info(adev->dev, "Saved %d pages to EEPROM table.\n", save_count);
2320         }
2321
2322         return 0;
2323 }
2324
2325 /*
2326  * read error record array in eeprom and reserve enough space for
2327  * storing new bad pages
2328  */
2329 static int amdgpu_ras_load_bad_pages(struct amdgpu_device *adev)
2330 {
2331         struct amdgpu_ras_eeprom_control *control =
2332                 &adev->psp.ras_context.ras->eeprom_control;
2333         struct eeprom_table_record *bps;
2334         int ret;
2335
2336         /* no bad page record, skip eeprom access */
2337         if (control->ras_num_recs == 0 || amdgpu_bad_page_threshold == 0)
2338                 return 0;
2339
2340         bps = kcalloc(control->ras_num_recs, sizeof(*bps), GFP_KERNEL);
2341         if (!bps)
2342                 return -ENOMEM;
2343
2344         ret = amdgpu_ras_eeprom_read(control, bps, control->ras_num_recs);
2345         if (ret)
2346                 dev_err(adev->dev, "Failed to load EEPROM table records!");
2347         else
2348                 ret = amdgpu_ras_add_bad_pages(adev, bps, control->ras_num_recs);
2349
2350         kfree(bps);
2351         return ret;
2352 }
2353
2354 static bool amdgpu_ras_check_bad_page_unlock(struct amdgpu_ras *con,
2355                                 uint64_t addr)
2356 {
2357         struct ras_err_handler_data *data = con->eh_data;
2358         int i;
2359
2360         addr >>= AMDGPU_GPU_PAGE_SHIFT;
2361         for (i = 0; i < data->count; i++)
2362                 if (addr == data->bps[i].retired_page)
2363                         return true;
2364
2365         return false;
2366 }
2367
2368 /*
2369  * check if an address belongs to bad page
2370  *
2371  * Note: this check is only for umc block
2372  */
2373 static bool amdgpu_ras_check_bad_page(struct amdgpu_device *adev,
2374                                 uint64_t addr)
2375 {
2376         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
2377         bool ret = false;
2378
2379         if (!con || !con->eh_data)
2380                 return ret;
2381
2382         mutex_lock(&con->recovery_lock);
2383         ret = amdgpu_ras_check_bad_page_unlock(con, addr);
2384         mutex_unlock(&con->recovery_lock);
2385         return ret;
2386 }
2387
2388 static void amdgpu_ras_validate_threshold(struct amdgpu_device *adev,
2389                                           uint32_t max_count)
2390 {
2391         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
2392
2393         /*
2394          * Justification of value bad_page_cnt_threshold in ras structure
2395          *
2396          * Generally, 0 <= amdgpu_bad_page_threshold <= max record length
2397          * in eeprom or amdgpu_bad_page_threshold == -2, introduce two
2398          * scenarios accordingly.
2399          *
2400          * Bad page retirement enablement:
2401          *    - If amdgpu_bad_page_threshold = -2,
2402          *      bad_page_cnt_threshold = typical value by formula.
2403          *
2404          *    - When the value from user is 0 < amdgpu_bad_page_threshold <
2405          *      max record length in eeprom, use it directly.
2406          *
2407          * Bad page retirement disablement:
2408          *    - If amdgpu_bad_page_threshold = 0, bad page retirement
2409          *      functionality is disabled, and bad_page_cnt_threshold will
2410          *      take no effect.
2411          */
2412
2413         if (amdgpu_bad_page_threshold < 0) {
2414                 u64 val = adev->gmc.mc_vram_size;
2415
2416                 do_div(val, RAS_BAD_PAGE_COVER);
2417                 con->bad_page_cnt_threshold = min(lower_32_bits(val),
2418                                                   max_count);
2419         } else {
2420                 con->bad_page_cnt_threshold = min_t(int, max_count,
2421                                                     amdgpu_bad_page_threshold);
2422         }
2423 }
2424
2425 int amdgpu_ras_recovery_init(struct amdgpu_device *adev)
2426 {
2427         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
2428         struct ras_err_handler_data **data;
2429         u32  max_eeprom_records_count = 0;
2430         bool exc_err_limit = false;
2431         int ret;
2432
2433         if (!con || amdgpu_sriov_vf(adev))
2434                 return 0;
2435
2436         /* Allow access to RAS EEPROM via debugfs, when the ASIC
2437          * supports RAS and debugfs is enabled, but when
2438          * adev->ras_enabled is unset, i.e. when "ras_enable"
2439          * module parameter is set to 0.
2440          */
2441         con->adev = adev;
2442
2443         if (!adev->ras_enabled)
2444                 return 0;
2445
2446         data = &con->eh_data;
2447         *data = kmalloc(sizeof(**data), GFP_KERNEL | __GFP_ZERO);
2448         if (!*data) {
2449                 ret = -ENOMEM;
2450                 goto out;
2451         }
2452
2453         mutex_init(&con->recovery_lock);
2454         INIT_WORK(&con->recovery_work, amdgpu_ras_do_recovery);
2455         atomic_set(&con->in_recovery, 0);
2456         con->eeprom_control.bad_channel_bitmap = 0;
2457
2458         max_eeprom_records_count = amdgpu_ras_eeprom_max_record_count(&con->eeprom_control);
2459         amdgpu_ras_validate_threshold(adev, max_eeprom_records_count);
2460
2461         /* Todo: During test the SMU might fail to read the eeprom through I2C
2462          * when the GPU is pending on XGMI reset during probe time
2463          * (Mostly after second bus reset), skip it now
2464          */
2465         if (adev->gmc.xgmi.pending_reset)
2466                 return 0;
2467         ret = amdgpu_ras_eeprom_init(&con->eeprom_control, &exc_err_limit);
2468         /*
2469          * This calling fails when exc_err_limit is true or
2470          * ret != 0.
2471          */
2472         if (exc_err_limit || ret)
2473                 goto free;
2474
2475         if (con->eeprom_control.ras_num_recs) {
2476                 ret = amdgpu_ras_load_bad_pages(adev);
2477                 if (ret)
2478                         goto free;
2479
2480                 amdgpu_dpm_send_hbm_bad_pages_num(adev, con->eeprom_control.ras_num_recs);
2481
2482                 if (con->update_channel_flag == true) {
2483                         amdgpu_dpm_send_hbm_bad_channel_flag(adev, con->eeprom_control.bad_channel_bitmap);
2484                         con->update_channel_flag = false;
2485                 }
2486         }
2487
2488 #ifdef CONFIG_X86_MCE_AMD
2489         if ((adev->asic_type == CHIP_ALDEBARAN) &&
2490             (adev->gmc.xgmi.connected_to_cpu))
2491                 amdgpu_register_bad_pages_mca_notifier(adev);
2492 #endif
2493         return 0;
2494
2495 free:
2496         kfree((*data)->bps);
2497         kfree(*data);
2498         con->eh_data = NULL;
2499 out:
2500         dev_warn(adev->dev, "Failed to initialize ras recovery! (%d)\n", ret);
2501
2502         /*
2503          * Except error threshold exceeding case, other failure cases in this
2504          * function would not fail amdgpu driver init.
2505          */
2506         if (!exc_err_limit)
2507                 ret = 0;
2508         else
2509                 ret = -EINVAL;
2510
2511         return ret;
2512 }
2513
2514 static int amdgpu_ras_recovery_fini(struct amdgpu_device *adev)
2515 {
2516         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
2517         struct ras_err_handler_data *data = con->eh_data;
2518
2519         /* recovery_init failed to init it, fini is useless */
2520         if (!data)
2521                 return 0;
2522
2523         cancel_work_sync(&con->recovery_work);
2524
2525         mutex_lock(&con->recovery_lock);
2526         con->eh_data = NULL;
2527         kfree(data->bps);
2528         kfree(data);
2529         mutex_unlock(&con->recovery_lock);
2530
2531         return 0;
2532 }
2533 /* recovery end */
2534
2535 static bool amdgpu_ras_asic_supported(struct amdgpu_device *adev)
2536 {
2537         if (amdgpu_sriov_vf(adev)) {
2538                 switch (amdgpu_ip_version(adev, MP0_HWIP, 0)) {
2539                 case IP_VERSION(13, 0, 2):
2540                 case IP_VERSION(13, 0, 6):
2541                         return true;
2542                 default:
2543                         return false;
2544                 }
2545         }
2546
2547         if (adev->asic_type == CHIP_IP_DISCOVERY) {
2548                 switch (amdgpu_ip_version(adev, MP0_HWIP, 0)) {
2549                 case IP_VERSION(13, 0, 0):
2550                 case IP_VERSION(13, 0, 6):
2551                 case IP_VERSION(13, 0, 10):
2552                         return true;
2553                 default:
2554                         return false;
2555                 }
2556         }
2557
2558         return adev->asic_type == CHIP_VEGA10 ||
2559                 adev->asic_type == CHIP_VEGA20 ||
2560                 adev->asic_type == CHIP_ARCTURUS ||
2561                 adev->asic_type == CHIP_ALDEBARAN ||
2562                 adev->asic_type == CHIP_SIENNA_CICHLID;
2563 }
2564
2565 /*
2566  * this is workaround for vega20 workstation sku,
2567  * force enable gfx ras, ignore vbios gfx ras flag
2568  * due to GC EDC can not write
2569  */
2570 static void amdgpu_ras_get_quirks(struct amdgpu_device *adev)
2571 {
2572         struct atom_context *ctx = adev->mode_info.atom_context;
2573
2574         if (!ctx)
2575                 return;
2576
2577         if (strnstr(ctx->vbios_pn, "D16406",
2578                     sizeof(ctx->vbios_pn)) ||
2579                 strnstr(ctx->vbios_pn, "D36002",
2580                         sizeof(ctx->vbios_pn)))
2581                 adev->ras_hw_enabled |= (1 << AMDGPU_RAS_BLOCK__GFX);
2582 }
2583
2584 /*
2585  * check hardware's ras ability which will be saved in hw_supported.
2586  * if hardware does not support ras, we can skip some ras initializtion and
2587  * forbid some ras operations from IP.
2588  * if software itself, say boot parameter, limit the ras ability. We still
2589  * need allow IP do some limited operations, like disable. In such case,
2590  * we have to initialize ras as normal. but need check if operation is
2591  * allowed or not in each function.
2592  */
2593 static void amdgpu_ras_check_supported(struct amdgpu_device *adev)
2594 {
2595         adev->ras_hw_enabled = adev->ras_enabled = 0;
2596
2597         if (!amdgpu_ras_asic_supported(adev))
2598                 return;
2599
2600         if (!adev->gmc.xgmi.connected_to_cpu && !adev->gmc.is_app_apu) {
2601                 if (amdgpu_atomfirmware_mem_ecc_supported(adev)) {
2602                         dev_info(adev->dev, "MEM ECC is active.\n");
2603                         adev->ras_hw_enabled |= (1 << AMDGPU_RAS_BLOCK__UMC |
2604                                                    1 << AMDGPU_RAS_BLOCK__DF);
2605                 } else {
2606                         dev_info(adev->dev, "MEM ECC is not presented.\n");
2607                 }
2608
2609                 if (amdgpu_atomfirmware_sram_ecc_supported(adev)) {
2610                         dev_info(adev->dev, "SRAM ECC is active.\n");
2611                         if (!amdgpu_sriov_vf(adev))
2612                                 adev->ras_hw_enabled |= ~(1 << AMDGPU_RAS_BLOCK__UMC |
2613                                                             1 << AMDGPU_RAS_BLOCK__DF);
2614                         else
2615                                 adev->ras_hw_enabled |= (1 << AMDGPU_RAS_BLOCK__PCIE_BIF |
2616                                                                 1 << AMDGPU_RAS_BLOCK__SDMA |
2617                                                                 1 << AMDGPU_RAS_BLOCK__GFX);
2618
2619                         /* VCN/JPEG RAS can be supported on both bare metal and
2620                          * SRIOV environment
2621                          */
2622                         if (amdgpu_ip_version(adev, VCN_HWIP, 0) ==
2623                                     IP_VERSION(2, 6, 0) ||
2624                             amdgpu_ip_version(adev, VCN_HWIP, 0) ==
2625                                     IP_VERSION(4, 0, 0) ||
2626                             amdgpu_ip_version(adev, VCN_HWIP, 0) ==
2627                                     IP_VERSION(4, 0, 3))
2628                                 adev->ras_hw_enabled |= (1 << AMDGPU_RAS_BLOCK__VCN |
2629                                                         1 << AMDGPU_RAS_BLOCK__JPEG);
2630                         else
2631                                 adev->ras_hw_enabled &= ~(1 << AMDGPU_RAS_BLOCK__VCN |
2632                                                         1 << AMDGPU_RAS_BLOCK__JPEG);
2633
2634                         /*
2635                          * XGMI RAS is not supported if xgmi num physical nodes
2636                          * is zero
2637                          */
2638                         if (!adev->gmc.xgmi.num_physical_nodes)
2639                                 adev->ras_hw_enabled &= ~(1 << AMDGPU_RAS_BLOCK__XGMI_WAFL);
2640                 } else {
2641                         dev_info(adev->dev, "SRAM ECC is not presented.\n");
2642                 }
2643         } else {
2644                 /* driver only manages a few IP blocks RAS feature
2645                  * when GPU is connected cpu through XGMI */
2646                 adev->ras_hw_enabled |= (1 << AMDGPU_RAS_BLOCK__GFX |
2647                                            1 << AMDGPU_RAS_BLOCK__SDMA |
2648                                            1 << AMDGPU_RAS_BLOCK__MMHUB);
2649         }
2650
2651         amdgpu_ras_get_quirks(adev);
2652
2653         /* hw_supported needs to be aligned with RAS block mask. */
2654         adev->ras_hw_enabled &= AMDGPU_RAS_BLOCK_MASK;
2655
2656         adev->ras_enabled = amdgpu_ras_enable == 0 ? 0 :
2657                 adev->ras_hw_enabled & amdgpu_ras_mask;
2658 }
2659
2660 static void amdgpu_ras_counte_dw(struct work_struct *work)
2661 {
2662         struct amdgpu_ras *con = container_of(work, struct amdgpu_ras,
2663                                               ras_counte_delay_work.work);
2664         struct amdgpu_device *adev = con->adev;
2665         struct drm_device *dev = adev_to_drm(adev);
2666         unsigned long ce_count, ue_count;
2667         int res;
2668
2669         res = pm_runtime_get_sync(dev->dev);
2670         if (res < 0)
2671                 goto Out;
2672
2673         /* Cache new values.
2674          */
2675         if (amdgpu_ras_query_error_count(adev, &ce_count, &ue_count, NULL) == 0) {
2676                 atomic_set(&con->ras_ce_count, ce_count);
2677                 atomic_set(&con->ras_ue_count, ue_count);
2678         }
2679
2680         pm_runtime_mark_last_busy(dev->dev);
2681 Out:
2682         pm_runtime_put_autosuspend(dev->dev);
2683 }
2684
2685 static void amdgpu_ras_query_poison_mode(struct amdgpu_device *adev)
2686 {
2687         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
2688         bool df_poison, umc_poison;
2689
2690         /* poison setting is useless on SRIOV guest */
2691         if (amdgpu_sriov_vf(adev) || !con)
2692                 return;
2693
2694         /* Init poison supported flag, the default value is false */
2695         if (adev->gmc.xgmi.connected_to_cpu) {
2696                 /* enabled by default when GPU is connected to CPU */
2697                 con->poison_supported = true;
2698         } else if (adev->df.funcs &&
2699             adev->df.funcs->query_ras_poison_mode &&
2700             adev->umc.ras &&
2701             adev->umc.ras->query_ras_poison_mode) {
2702                 df_poison =
2703                         adev->df.funcs->query_ras_poison_mode(adev);
2704                 umc_poison =
2705                         adev->umc.ras->query_ras_poison_mode(adev);
2706
2707                 /* Only poison is set in both DF and UMC, we can support it */
2708                 if (df_poison && umc_poison)
2709                         con->poison_supported = true;
2710                 else if (df_poison != umc_poison)
2711                         dev_warn(adev->dev,
2712                                 "Poison setting is inconsistent in DF/UMC(%d:%d)!\n",
2713                                 df_poison, umc_poison);
2714         }
2715 }
2716
2717 static int amdgpu_get_ras_schema(struct amdgpu_device *adev)
2718 {
2719         return  amdgpu_ras_is_poison_mode_supported(adev) ? AMDGPU_RAS_ERROR__POISON : 0 |
2720                         AMDGPU_RAS_ERROR__SINGLE_CORRECTABLE |
2721                         AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE |
2722                         AMDGPU_RAS_ERROR__PARITY;
2723 }
2724
2725 int amdgpu_ras_init(struct amdgpu_device *adev)
2726 {
2727         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
2728         int r;
2729
2730         if (con)
2731                 return 0;
2732
2733         con = kmalloc(sizeof(struct amdgpu_ras) +
2734                         sizeof(struct ras_manager) * AMDGPU_RAS_BLOCK_COUNT +
2735                         sizeof(struct ras_manager) * AMDGPU_RAS_MCA_BLOCK_COUNT,
2736                         GFP_KERNEL|__GFP_ZERO);
2737         if (!con)
2738                 return -ENOMEM;
2739
2740         con->adev = adev;
2741         INIT_DELAYED_WORK(&con->ras_counte_delay_work, amdgpu_ras_counte_dw);
2742         atomic_set(&con->ras_ce_count, 0);
2743         atomic_set(&con->ras_ue_count, 0);
2744
2745         con->objs = (struct ras_manager *)(con + 1);
2746
2747         amdgpu_ras_set_context(adev, con);
2748
2749         amdgpu_ras_check_supported(adev);
2750
2751         if (!adev->ras_enabled || adev->asic_type == CHIP_VEGA10) {
2752                 /* set gfx block ras context feature for VEGA20 Gaming
2753                  * send ras disable cmd to ras ta during ras late init.
2754                  */
2755                 if (!adev->ras_enabled && adev->asic_type == CHIP_VEGA20) {
2756                         con->features |= BIT(AMDGPU_RAS_BLOCK__GFX);
2757
2758                         return 0;
2759                 }
2760
2761                 r = 0;
2762                 goto release_con;
2763         }
2764
2765         con->update_channel_flag = false;
2766         con->features = 0;
2767         con->schema = 0;
2768         INIT_LIST_HEAD(&con->head);
2769         /* Might need get this flag from vbios. */
2770         con->flags = RAS_DEFAULT_FLAGS;
2771
2772         /* initialize nbio ras function ahead of any other
2773          * ras functions so hardware fatal error interrupt
2774          * can be enabled as early as possible */
2775         switch (amdgpu_ip_version(adev, NBIO_HWIP, 0)) {
2776         case IP_VERSION(7, 4, 0):
2777         case IP_VERSION(7, 4, 1):
2778         case IP_VERSION(7, 4, 4):
2779                 if (!adev->gmc.xgmi.connected_to_cpu)
2780                         adev->nbio.ras = &nbio_v7_4_ras;
2781                 break;
2782         case IP_VERSION(4, 3, 0):
2783                 if (adev->ras_hw_enabled & (1 << AMDGPU_RAS_BLOCK__DF))
2784                         /* unlike other generation of nbio ras,
2785                          * nbio v4_3 only support fatal error interrupt
2786                          * to inform software that DF is freezed due to
2787                          * system fatal error event. driver should not
2788                          * enable nbio ras in such case. Instead,
2789                          * check DF RAS */
2790                         adev->nbio.ras = &nbio_v4_3_ras;
2791                 break;
2792         case IP_VERSION(7, 9, 0):
2793                 if (!adev->gmc.is_app_apu)
2794                         adev->nbio.ras = &nbio_v7_9_ras;
2795                 break;
2796         default:
2797                 /* nbio ras is not available */
2798                 break;
2799         }
2800
2801         /* nbio ras block needs to be enabled ahead of other ras blocks
2802          * to handle fatal error */
2803         r = amdgpu_nbio_ras_sw_init(adev);
2804         if (r)
2805                 return r;
2806
2807         if (adev->nbio.ras &&
2808             adev->nbio.ras->init_ras_controller_interrupt) {
2809                 r = adev->nbio.ras->init_ras_controller_interrupt(adev);
2810                 if (r)
2811                         goto release_con;
2812         }
2813
2814         if (adev->nbio.ras &&
2815             adev->nbio.ras->init_ras_err_event_athub_interrupt) {
2816                 r = adev->nbio.ras->init_ras_err_event_athub_interrupt(adev);
2817                 if (r)
2818                         goto release_con;
2819         }
2820
2821         amdgpu_ras_query_poison_mode(adev);
2822
2823         /* Get RAS schema for particular SOC */
2824         con->schema = amdgpu_get_ras_schema(adev);
2825
2826         if (amdgpu_ras_fs_init(adev)) {
2827                 r = -EINVAL;
2828                 goto release_con;
2829         }
2830
2831         dev_info(adev->dev, "RAS INFO: ras initialized successfully, "
2832                  "hardware ability[%x] ras_mask[%x]\n",
2833                  adev->ras_hw_enabled, adev->ras_enabled);
2834
2835         return 0;
2836 release_con:
2837         amdgpu_ras_set_context(adev, NULL);
2838         kfree(con);
2839
2840         return r;
2841 }
2842
2843 int amdgpu_persistent_edc_harvesting_supported(struct amdgpu_device *adev)
2844 {
2845         if (adev->gmc.xgmi.connected_to_cpu ||
2846             adev->gmc.is_app_apu)
2847                 return 1;
2848         return 0;
2849 }
2850
2851 static int amdgpu_persistent_edc_harvesting(struct amdgpu_device *adev,
2852                                         struct ras_common_if *ras_block)
2853 {
2854         struct ras_query_if info = {
2855                 .head = *ras_block,
2856         };
2857
2858         if (!amdgpu_persistent_edc_harvesting_supported(adev))
2859                 return 0;
2860
2861         if (amdgpu_ras_query_error_status(adev, &info) != 0)
2862                 DRM_WARN("RAS init harvest failure");
2863
2864         if (amdgpu_ras_reset_error_status(adev, ras_block->block) != 0)
2865                 DRM_WARN("RAS init harvest reset failure");
2866
2867         return 0;
2868 }
2869
2870 bool amdgpu_ras_is_poison_mode_supported(struct amdgpu_device *adev)
2871 {
2872        struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
2873
2874        if (!con)
2875                return false;
2876
2877        return con->poison_supported;
2878 }
2879
2880 /* helper function to handle common stuff in ip late init phase */
2881 int amdgpu_ras_block_late_init(struct amdgpu_device *adev,
2882                          struct ras_common_if *ras_block)
2883 {
2884         struct amdgpu_ras_block_object *ras_obj = NULL;
2885         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
2886         struct ras_query_if *query_info;
2887         unsigned long ue_count, ce_count;
2888         int r;
2889
2890         /* disable RAS feature per IP block if it is not supported */
2891         if (!amdgpu_ras_is_supported(adev, ras_block->block)) {
2892                 amdgpu_ras_feature_enable_on_boot(adev, ras_block, 0);
2893                 return 0;
2894         }
2895
2896         r = amdgpu_ras_feature_enable_on_boot(adev, ras_block, 1);
2897         if (r) {
2898                 if (adev->in_suspend || amdgpu_in_reset(adev)) {
2899                         /* in resume phase, if fail to enable ras,
2900                          * clean up all ras fs nodes, and disable ras */
2901                         goto cleanup;
2902                 } else
2903                         return r;
2904         }
2905
2906         /* check for errors on warm reset edc persisant supported ASIC */
2907         amdgpu_persistent_edc_harvesting(adev, ras_block);
2908
2909         /* in resume phase, no need to create ras fs node */
2910         if (adev->in_suspend || amdgpu_in_reset(adev))
2911                 return 0;
2912
2913         ras_obj = container_of(ras_block, struct amdgpu_ras_block_object, ras_comm);
2914         if (ras_obj->ras_cb || (ras_obj->hw_ops &&
2915             (ras_obj->hw_ops->query_poison_status ||
2916             ras_obj->hw_ops->handle_poison_consumption))) {
2917                 r = amdgpu_ras_interrupt_add_handler(adev, ras_block);
2918                 if (r)
2919                         goto cleanup;
2920         }
2921
2922         if (ras_obj->hw_ops &&
2923             (ras_obj->hw_ops->query_ras_error_count ||
2924              ras_obj->hw_ops->query_ras_error_status)) {
2925                 r = amdgpu_ras_sysfs_create(adev, ras_block);
2926                 if (r)
2927                         goto interrupt;
2928
2929                 /* Those are the cached values at init.
2930                  */
2931                 query_info = kzalloc(sizeof(*query_info), GFP_KERNEL);
2932                 if (!query_info)
2933                         return -ENOMEM;
2934                 memcpy(&query_info->head, ras_block, sizeof(struct ras_common_if));
2935
2936                 if (amdgpu_ras_query_error_count(adev, &ce_count, &ue_count, query_info) == 0) {
2937                         atomic_set(&con->ras_ce_count, ce_count);
2938                         atomic_set(&con->ras_ue_count, ue_count);
2939                 }
2940
2941                 kfree(query_info);
2942         }
2943
2944         return 0;
2945
2946 interrupt:
2947         if (ras_obj->ras_cb)
2948                 amdgpu_ras_interrupt_remove_handler(adev, ras_block);
2949 cleanup:
2950         amdgpu_ras_feature_enable(adev, ras_block, 0);
2951         return r;
2952 }
2953
2954 static int amdgpu_ras_block_late_init_default(struct amdgpu_device *adev,
2955                          struct ras_common_if *ras_block)
2956 {
2957         return amdgpu_ras_block_late_init(adev, ras_block);
2958 }
2959
2960 /* helper function to remove ras fs node and interrupt handler */
2961 void amdgpu_ras_block_late_fini(struct amdgpu_device *adev,
2962                           struct ras_common_if *ras_block)
2963 {
2964         struct amdgpu_ras_block_object *ras_obj;
2965         if (!ras_block)
2966                 return;
2967
2968         amdgpu_ras_sysfs_remove(adev, ras_block);
2969
2970         ras_obj = container_of(ras_block, struct amdgpu_ras_block_object, ras_comm);
2971         if (ras_obj->ras_cb)
2972                 amdgpu_ras_interrupt_remove_handler(adev, ras_block);
2973 }
2974
2975 static void amdgpu_ras_block_late_fini_default(struct amdgpu_device *adev,
2976                           struct ras_common_if *ras_block)
2977 {
2978         return amdgpu_ras_block_late_fini(adev, ras_block);
2979 }
2980
2981 /* do some init work after IP late init as dependence.
2982  * and it runs in resume/gpu reset/booting up cases.
2983  */
2984 void amdgpu_ras_resume(struct amdgpu_device *adev)
2985 {
2986         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
2987         struct ras_manager *obj, *tmp;
2988
2989         if (!adev->ras_enabled || !con) {
2990                 /* clean ras context for VEGA20 Gaming after send ras disable cmd */
2991                 amdgpu_release_ras_context(adev);
2992
2993                 return;
2994         }
2995
2996         if (con->flags & AMDGPU_RAS_FLAG_INIT_BY_VBIOS) {
2997                 /* Set up all other IPs which are not implemented. There is a
2998                  * tricky thing that IP's actual ras error type should be
2999                  * MULTI_UNCORRECTABLE, but as driver does not handle it, so
3000                  * ERROR_NONE make sense anyway.
3001                  */
3002                 amdgpu_ras_enable_all_features(adev, 1);
3003
3004                 /* We enable ras on all hw_supported block, but as boot
3005                  * parameter might disable some of them and one or more IP has
3006                  * not implemented yet. So we disable them on behalf.
3007                  */
3008                 list_for_each_entry_safe(obj, tmp, &con->head, node) {
3009                         if (!amdgpu_ras_is_supported(adev, obj->head.block)) {
3010                                 amdgpu_ras_feature_enable(adev, &obj->head, 0);
3011                                 /* there should be no any reference. */
3012                                 WARN_ON(alive_obj(obj));
3013                         }
3014                 }
3015         }
3016 }
3017
3018 void amdgpu_ras_suspend(struct amdgpu_device *adev)
3019 {
3020         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
3021
3022         if (!adev->ras_enabled || !con)
3023                 return;
3024
3025         amdgpu_ras_disable_all_features(adev, 0);
3026         /* Make sure all ras objects are disabled. */
3027         if (con->features)
3028                 amdgpu_ras_disable_all_features(adev, 1);
3029 }
3030
3031 int amdgpu_ras_late_init(struct amdgpu_device *adev)
3032 {
3033         struct amdgpu_ras_block_list *node, *tmp;
3034         struct amdgpu_ras_block_object *obj;
3035         int r;
3036
3037         /* Guest side doesn't need init ras feature */
3038         if (amdgpu_sriov_vf(adev))
3039                 return 0;
3040
3041         list_for_each_entry_safe(node, tmp, &adev->ras_list, node) {
3042                 if (!node->ras_obj) {
3043                         dev_warn(adev->dev, "Warning: abnormal ras list node.\n");
3044                         continue;
3045                 }
3046
3047                 obj = node->ras_obj;
3048                 if (obj->ras_late_init) {
3049                         r = obj->ras_late_init(adev, &obj->ras_comm);
3050                         if (r) {
3051                                 dev_err(adev->dev, "%s failed to execute ras_late_init! ret:%d\n",
3052                                         obj->ras_comm.name, r);
3053                                 return r;
3054                         }
3055                 } else
3056                         amdgpu_ras_block_late_init_default(adev, &obj->ras_comm);
3057         }
3058
3059         return 0;
3060 }
3061
3062 /* do some fini work before IP fini as dependence */
3063 int amdgpu_ras_pre_fini(struct amdgpu_device *adev)
3064 {
3065         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
3066
3067         if (!adev->ras_enabled || !con)
3068                 return 0;
3069
3070
3071         /* Need disable ras on all IPs here before ip [hw/sw]fini */
3072         if (con->features)
3073                 amdgpu_ras_disable_all_features(adev, 0);
3074         amdgpu_ras_recovery_fini(adev);
3075         return 0;
3076 }
3077
3078 int amdgpu_ras_fini(struct amdgpu_device *adev)
3079 {
3080         struct amdgpu_ras_block_list *ras_node, *tmp;
3081         struct amdgpu_ras_block_object *obj = NULL;
3082         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
3083
3084         if (!adev->ras_enabled || !con)
3085                 return 0;
3086
3087         list_for_each_entry_safe(ras_node, tmp, &adev->ras_list, node) {
3088                 if (ras_node->ras_obj) {
3089                         obj = ras_node->ras_obj;
3090                         if (amdgpu_ras_is_supported(adev, obj->ras_comm.block) &&
3091                             obj->ras_fini)
3092                                 obj->ras_fini(adev, &obj->ras_comm);
3093                         else
3094                                 amdgpu_ras_block_late_fini_default(adev, &obj->ras_comm);
3095                 }
3096
3097                 /* Clear ras blocks from ras_list and free ras block list node */
3098                 list_del(&ras_node->node);
3099                 kfree(ras_node);
3100         }
3101
3102         amdgpu_ras_fs_fini(adev);
3103         amdgpu_ras_interrupt_remove_all(adev);
3104
3105         WARN(con->features, "Feature mask is not cleared");
3106
3107         if (con->features)
3108                 amdgpu_ras_disable_all_features(adev, 1);
3109
3110         cancel_delayed_work_sync(&con->ras_counte_delay_work);
3111
3112         amdgpu_ras_set_context(adev, NULL);
3113         kfree(con);
3114
3115         return 0;
3116 }
3117
3118 void amdgpu_ras_global_ras_isr(struct amdgpu_device *adev)
3119 {
3120         if (atomic_cmpxchg(&amdgpu_ras_in_intr, 0, 1) == 0) {
3121                 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev);
3122
3123                 dev_info(adev->dev, "uncorrectable hardware error"
3124                         "(ERREVENT_ATHUB_INTERRUPT) detected!\n");
3125
3126                 ras->gpu_reset_flags |= AMDGPU_RAS_GPU_RESET_MODE1_RESET;
3127                 amdgpu_ras_reset_gpu(adev);
3128         }
3129 }
3130
3131 bool amdgpu_ras_need_emergency_restart(struct amdgpu_device *adev)
3132 {
3133         if (adev->asic_type == CHIP_VEGA20 &&
3134             adev->pm.fw_version <= 0x283400) {
3135                 return !(amdgpu_asic_reset_method(adev) == AMD_RESET_METHOD_BACO) &&
3136                                 amdgpu_ras_intr_triggered();
3137         }
3138
3139         return false;
3140 }
3141
3142 void amdgpu_release_ras_context(struct amdgpu_device *adev)
3143 {
3144         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
3145
3146         if (!con)
3147                 return;
3148
3149         if (!adev->ras_enabled && con->features & BIT(AMDGPU_RAS_BLOCK__GFX)) {
3150                 con->features &= ~BIT(AMDGPU_RAS_BLOCK__GFX);
3151                 amdgpu_ras_set_context(adev, NULL);
3152                 kfree(con);
3153         }
3154 }
3155
3156 #ifdef CONFIG_X86_MCE_AMD
3157 static struct amdgpu_device *find_adev(uint32_t node_id)
3158 {
3159         int i;
3160         struct amdgpu_device *adev = NULL;
3161
3162         for (i = 0; i < mce_adev_list.num_gpu; i++) {
3163                 adev = mce_adev_list.devs[i];
3164
3165                 if (adev && adev->gmc.xgmi.connected_to_cpu &&
3166                     adev->gmc.xgmi.physical_node_id == node_id)
3167                         break;
3168                 adev = NULL;
3169         }
3170
3171         return adev;
3172 }
3173
3174 #define GET_MCA_IPID_GPUID(m)   (((m) >> 44) & 0xF)
3175 #define GET_UMC_INST(m)         (((m) >> 21) & 0x7)
3176 #define GET_CHAN_INDEX(m)       ((((m) >> 12) & 0x3) | (((m) >> 18) & 0x4))
3177 #define GPU_ID_OFFSET           8
3178
3179 static int amdgpu_bad_page_notifier(struct notifier_block *nb,
3180                                     unsigned long val, void *data)
3181 {
3182         struct mce *m = (struct mce *)data;
3183         struct amdgpu_device *adev = NULL;
3184         uint32_t gpu_id = 0;
3185         uint32_t umc_inst = 0, ch_inst = 0;
3186
3187         /*
3188          * If the error was generated in UMC_V2, which belongs to GPU UMCs,
3189          * and error occurred in DramECC (Extended error code = 0) then only
3190          * process the error, else bail out.
3191          */
3192         if (!m || !((smca_get_bank_type(m->extcpu, m->bank) == SMCA_UMC_V2) &&
3193                     (XEC(m->status, 0x3f) == 0x0)))
3194                 return NOTIFY_DONE;
3195
3196         /*
3197          * If it is correctable error, return.
3198          */
3199         if (mce_is_correctable(m))
3200                 return NOTIFY_OK;
3201
3202         /*
3203          * GPU Id is offset by GPU_ID_OFFSET in MCA_IPID_UMC register.
3204          */
3205         gpu_id = GET_MCA_IPID_GPUID(m->ipid) - GPU_ID_OFFSET;
3206
3207         adev = find_adev(gpu_id);
3208         if (!adev) {
3209                 DRM_WARN("%s: Unable to find adev for gpu_id: %d\n", __func__,
3210                                                                 gpu_id);
3211                 return NOTIFY_DONE;
3212         }
3213
3214         /*
3215          * If it is uncorrectable error, then find out UMC instance and
3216          * channel index.
3217          */
3218         umc_inst = GET_UMC_INST(m->ipid);
3219         ch_inst = GET_CHAN_INDEX(m->ipid);
3220
3221         dev_info(adev->dev, "Uncorrectable error detected in UMC inst: %d, chan_idx: %d",
3222                              umc_inst, ch_inst);
3223
3224         if (!amdgpu_umc_page_retirement_mca(adev, m->addr, ch_inst, umc_inst))
3225                 return NOTIFY_OK;
3226         else
3227                 return NOTIFY_DONE;
3228 }
3229
3230 static struct notifier_block amdgpu_bad_page_nb = {
3231         .notifier_call  = amdgpu_bad_page_notifier,
3232         .priority       = MCE_PRIO_UC,
3233 };
3234
3235 static void amdgpu_register_bad_pages_mca_notifier(struct amdgpu_device *adev)
3236 {
3237         /*
3238          * Add the adev to the mce_adev_list.
3239          * During mode2 reset, amdgpu device is temporarily
3240          * removed from the mgpu_info list which can cause
3241          * page retirement to fail.
3242          * Use this list instead of mgpu_info to find the amdgpu
3243          * device on which the UMC error was reported.
3244          */
3245         mce_adev_list.devs[mce_adev_list.num_gpu++] = adev;
3246
3247         /*
3248          * Register the x86 notifier only once
3249          * with MCE subsystem.
3250          */
3251         if (notifier_registered == false) {
3252                 mce_register_decode_chain(&amdgpu_bad_page_nb);
3253                 notifier_registered = true;
3254         }
3255 }
3256 #endif
3257
3258 struct amdgpu_ras *amdgpu_ras_get_context(struct amdgpu_device *adev)
3259 {
3260         if (!adev)
3261                 return NULL;
3262
3263         return adev->psp.ras_context.ras;
3264 }
3265
3266 int amdgpu_ras_set_context(struct amdgpu_device *adev, struct amdgpu_ras *ras_con)
3267 {
3268         if (!adev)
3269                 return -EINVAL;
3270
3271         adev->psp.ras_context.ras = ras_con;
3272         return 0;
3273 }
3274
3275 /* check if ras is supported on block, say, sdma, gfx */
3276 int amdgpu_ras_is_supported(struct amdgpu_device *adev,
3277                 unsigned int block)
3278 {
3279         int ret = 0;
3280         struct amdgpu_ras *ras = amdgpu_ras_get_context(adev);
3281
3282         if (block >= AMDGPU_RAS_BLOCK_COUNT)
3283                 return 0;
3284
3285         ret = ras && (adev->ras_enabled & (1 << block));
3286
3287         /* For the special asic with mem ecc enabled but sram ecc
3288          * not enabled, even if the ras block is not supported on
3289          * .ras_enabled, if the asic supports poison mode and the
3290          * ras block has ras configuration, it can be considered
3291          * that the ras block supports ras function.
3292          */
3293         if (!ret &&
3294             (block == AMDGPU_RAS_BLOCK__GFX ||
3295              block == AMDGPU_RAS_BLOCK__SDMA ||
3296              block == AMDGPU_RAS_BLOCK__VCN ||
3297              block == AMDGPU_RAS_BLOCK__JPEG) &&
3298             amdgpu_ras_is_poison_mode_supported(adev) &&
3299             amdgpu_ras_get_ras_block(adev, block, 0))
3300                 ret = 1;
3301
3302         return ret;
3303 }
3304
3305 int amdgpu_ras_reset_gpu(struct amdgpu_device *adev)
3306 {
3307         struct amdgpu_ras *ras = amdgpu_ras_get_context(adev);
3308
3309         if (atomic_cmpxchg(&ras->in_recovery, 0, 1) == 0)
3310                 amdgpu_reset_domain_schedule(ras->adev->reset_domain, &ras->recovery_work);
3311         return 0;
3312 }
3313
3314 void amdgpu_ras_set_mca_debug_mode(struct amdgpu_device *adev, bool enable)
3315 {
3316         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
3317
3318         if (con)
3319                 con->is_mca_debug_mode = enable;
3320 }
3321
3322 bool amdgpu_ras_get_mca_debug_mode(struct amdgpu_device *adev)
3323 {
3324         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
3325         const struct amdgpu_mca_smu_funcs *mca_funcs = adev->mca.mca_funcs;
3326
3327         if (!con)
3328                 return false;
3329
3330         if (mca_funcs && mca_funcs->mca_set_debug_mode)
3331                 return con->is_mca_debug_mode;
3332         else
3333                 return true;
3334 }
3335
3336 /* Register each ip ras block into amdgpu ras */
3337 int amdgpu_ras_register_ras_block(struct amdgpu_device *adev,
3338                 struct amdgpu_ras_block_object *ras_block_obj)
3339 {
3340         struct amdgpu_ras_block_list *ras_node;
3341         if (!adev || !ras_block_obj)
3342                 return -EINVAL;
3343
3344         ras_node = kzalloc(sizeof(*ras_node), GFP_KERNEL);
3345         if (!ras_node)
3346                 return -ENOMEM;
3347
3348         INIT_LIST_HEAD(&ras_node->node);
3349         ras_node->ras_obj = ras_block_obj;
3350         list_add_tail(&ras_node->node, &adev->ras_list);
3351
3352         return 0;
3353 }
3354
3355 void amdgpu_ras_get_error_type_name(uint32_t err_type, char *err_type_name)
3356 {
3357         if (!err_type_name)
3358                 return;
3359
3360         switch (err_type) {
3361         case AMDGPU_RAS_ERROR__SINGLE_CORRECTABLE:
3362                 sprintf(err_type_name, "correctable");
3363                 break;
3364         case AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE:
3365                 sprintf(err_type_name, "uncorrectable");
3366                 break;
3367         default:
3368                 sprintf(err_type_name, "unknown");
3369                 break;
3370         }
3371 }
3372
3373 bool amdgpu_ras_inst_get_memory_id_field(struct amdgpu_device *adev,
3374                                          const struct amdgpu_ras_err_status_reg_entry *reg_entry,
3375                                          uint32_t instance,
3376                                          uint32_t *memory_id)
3377 {
3378         uint32_t err_status_lo_data, err_status_lo_offset;
3379
3380         if (!reg_entry)
3381                 return false;
3382
3383         err_status_lo_offset =
3384                 AMDGPU_RAS_REG_ENTRY_OFFSET(reg_entry->hwip, instance,
3385                                             reg_entry->seg_lo, reg_entry->reg_lo);
3386         err_status_lo_data = RREG32(err_status_lo_offset);
3387
3388         if ((reg_entry->flags & AMDGPU_RAS_ERR_STATUS_VALID) &&
3389             !REG_GET_FIELD(err_status_lo_data, ERR_STATUS_LO, ERR_STATUS_VALID_FLAG))
3390                 return false;
3391
3392         *memory_id = REG_GET_FIELD(err_status_lo_data, ERR_STATUS_LO, MEMORY_ID);
3393
3394         return true;
3395 }
3396
3397 bool amdgpu_ras_inst_get_err_cnt_field(struct amdgpu_device *adev,
3398                                        const struct amdgpu_ras_err_status_reg_entry *reg_entry,
3399                                        uint32_t instance,
3400                                        unsigned long *err_cnt)
3401 {
3402         uint32_t err_status_hi_data, err_status_hi_offset;
3403
3404         if (!reg_entry)
3405                 return false;
3406
3407         err_status_hi_offset =
3408                 AMDGPU_RAS_REG_ENTRY_OFFSET(reg_entry->hwip, instance,
3409                                             reg_entry->seg_hi, reg_entry->reg_hi);
3410         err_status_hi_data = RREG32(err_status_hi_offset);
3411
3412         if ((reg_entry->flags & AMDGPU_RAS_ERR_INFO_VALID) &&
3413             !REG_GET_FIELD(err_status_hi_data, ERR_STATUS_HI, ERR_INFO_VALID_FLAG))
3414                 /* keep the check here in case we need to refer to the result later */
3415                 dev_dbg(adev->dev, "Invalid err_info field\n");
3416
3417         /* read err count */
3418         *err_cnt = REG_GET_FIELD(err_status_hi_data, ERR_STATUS, ERR_CNT);
3419
3420         return true;
3421 }
3422
3423 void amdgpu_ras_inst_query_ras_error_count(struct amdgpu_device *adev,
3424                                            const struct amdgpu_ras_err_status_reg_entry *reg_list,
3425                                            uint32_t reg_list_size,
3426                                            const struct amdgpu_ras_memory_id_entry *mem_list,
3427                                            uint32_t mem_list_size,
3428                                            uint32_t instance,
3429                                            uint32_t err_type,
3430                                            unsigned long *err_count)
3431 {
3432         uint32_t memory_id;
3433         unsigned long err_cnt;
3434         char err_type_name[16];
3435         uint32_t i, j;
3436
3437         for (i = 0; i < reg_list_size; i++) {
3438                 /* query memory_id from err_status_lo */
3439                 if (!amdgpu_ras_inst_get_memory_id_field(adev, &reg_list[i],
3440                                                          instance, &memory_id))
3441                         continue;
3442
3443                 /* query err_cnt from err_status_hi */
3444                 if (!amdgpu_ras_inst_get_err_cnt_field(adev, &reg_list[i],
3445                                                        instance, &err_cnt) ||
3446                     !err_cnt)
3447                         continue;
3448
3449                 *err_count += err_cnt;
3450
3451                 /* log the errors */
3452                 amdgpu_ras_get_error_type_name(err_type, err_type_name);
3453                 if (!mem_list) {
3454                         /* memory_list is not supported */
3455                         dev_info(adev->dev,
3456                                  "%ld %s hardware errors detected in %s, instance: %d, memory_id: %d\n",
3457                                  err_cnt, err_type_name,
3458                                  reg_list[i].block_name,
3459                                  instance, memory_id);
3460                 } else {
3461                         for (j = 0; j < mem_list_size; j++) {
3462                                 if (memory_id == mem_list[j].memory_id) {
3463                                         dev_info(adev->dev,
3464                                                  "%ld %s hardware errors detected in %s, instance: %d, memory block: %s\n",
3465                                                  err_cnt, err_type_name,
3466                                                  reg_list[i].block_name,
3467                                                  instance, mem_list[j].name);
3468                                         break;
3469                                 }
3470                         }
3471                 }
3472         }
3473 }
3474
3475 void amdgpu_ras_inst_reset_ras_error_count(struct amdgpu_device *adev,
3476                                            const struct amdgpu_ras_err_status_reg_entry *reg_list,
3477                                            uint32_t reg_list_size,
3478                                            uint32_t instance)
3479 {
3480         uint32_t err_status_lo_offset, err_status_hi_offset;
3481         uint32_t i;
3482
3483         for (i = 0; i < reg_list_size; i++) {
3484                 err_status_lo_offset =
3485                         AMDGPU_RAS_REG_ENTRY_OFFSET(reg_list[i].hwip, instance,
3486                                                     reg_list[i].seg_lo, reg_list[i].reg_lo);
3487                 err_status_hi_offset =
3488                         AMDGPU_RAS_REG_ENTRY_OFFSET(reg_list[i].hwip, instance,
3489                                                     reg_list[i].seg_hi, reg_list[i].reg_hi);
3490                 WREG32(err_status_lo_offset, 0);
3491                 WREG32(err_status_hi_offset, 0);
3492         }
3493 }
3494
3495 int amdgpu_ras_error_data_init(struct ras_err_data *err_data)
3496 {
3497         memset(err_data, 0, sizeof(*err_data));
3498
3499         INIT_LIST_HEAD(&err_data->err_node_list);
3500
3501         return 0;
3502 }
3503
3504 static void amdgpu_ras_error_node_release(struct ras_err_node *err_node)
3505 {
3506         if (!err_node)
3507                 return;
3508
3509         list_del(&err_node->node);
3510         kvfree(err_node);
3511 }
3512
3513 void amdgpu_ras_error_data_fini(struct ras_err_data *err_data)
3514 {
3515         struct ras_err_node *err_node, *tmp;
3516
3517         list_for_each_entry_safe(err_node, tmp, &err_data->err_node_list, node)
3518                 amdgpu_ras_error_node_release(err_node);
3519 }
3520
3521 static struct ras_err_node *amdgpu_ras_error_find_node_by_id(struct ras_err_data *err_data,
3522                                                              struct amdgpu_smuio_mcm_config_info *mcm_info)
3523 {
3524         struct ras_err_node *err_node;
3525         struct amdgpu_smuio_mcm_config_info *ref_id;
3526
3527         if (!err_data || !mcm_info)
3528                 return NULL;
3529
3530         for_each_ras_error(err_node, err_data) {
3531                 ref_id = &err_node->err_info.mcm_info;
3532
3533                 if (mcm_info->socket_id == ref_id->socket_id &&
3534                     mcm_info->die_id == ref_id->die_id)
3535                         return err_node;
3536         }
3537
3538         return NULL;
3539 }
3540
3541 static struct ras_err_node *amdgpu_ras_error_node_new(void)
3542 {
3543         struct ras_err_node *err_node;
3544
3545         err_node = kvzalloc(sizeof(*err_node), GFP_KERNEL);
3546         if (!err_node)
3547                 return NULL;
3548
3549         INIT_LIST_HEAD(&err_node->node);
3550
3551         return err_node;
3552 }
3553
3554 static struct ras_err_info *amdgpu_ras_error_get_info(struct ras_err_data *err_data,
3555                                                       struct amdgpu_smuio_mcm_config_info *mcm_info)
3556 {
3557         struct ras_err_node *err_node;
3558
3559         err_node = amdgpu_ras_error_find_node_by_id(err_data, mcm_info);
3560         if (err_node)
3561                 return &err_node->err_info;
3562
3563         err_node = amdgpu_ras_error_node_new();
3564         if (!err_node)
3565                 return NULL;
3566
3567         memcpy(&err_node->err_info.mcm_info, mcm_info, sizeof(*mcm_info));
3568
3569         err_data->err_list_count++;
3570         list_add_tail(&err_node->node, &err_data->err_node_list);
3571
3572         return &err_node->err_info;
3573 }
3574
3575 int amdgpu_ras_error_statistic_ue_count(struct ras_err_data *err_data,
3576                                         struct amdgpu_smuio_mcm_config_info *mcm_info, u64 count)
3577 {
3578         struct ras_err_info *err_info;
3579
3580         if (!err_data || !mcm_info)
3581                 return -EINVAL;
3582
3583         if (!count)
3584                 return 0;
3585
3586         err_info = amdgpu_ras_error_get_info(err_data, mcm_info);
3587         if (!err_info)
3588                 return -EINVAL;
3589
3590         err_info->ue_count += count;
3591         err_data->ue_count += count;
3592
3593         return 0;
3594 }
3595
3596 int amdgpu_ras_error_statistic_ce_count(struct ras_err_data *err_data,
3597                                         struct amdgpu_smuio_mcm_config_info *mcm_info, u64 count)
3598 {
3599         struct ras_err_info *err_info;
3600
3601         if (!err_data || !mcm_info)
3602                 return -EINVAL;
3603
3604         if (!count)
3605                 return 0;
3606
3607         err_info = amdgpu_ras_error_get_info(err_data, mcm_info);
3608         if (!err_info)
3609                 return -EINVAL;
3610
3611         err_info->ce_count += count;
3612         err_data->ce_count += count;
3613
3614         return 0;
3615 }